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USER`S MANUAL

1. PRODUCT OVERVIEW PIN ASSIGNMENT P1 7 INT7 P2 0 ADO P2 1 AD1 P2 2 AD2 P2 3 AD3 P2 4 AD4 P2 5 AD5 P2 6 AD6 P2 7 AD7 AVDD P3 0 BUZ P3 1 SCKO P3 2 SO0 P3 3 SIO VDD Vss XOUT XIN TEST1 TEST2 P3 4 SCK1 RESET P3 5 SO1 P3 6 SI1 P3 7 P4 0 SEG39 P4 1 SEG38 P4 2 SEG37 P4 3 SEG36 P4 4 SEG35 9 bd IG td kd 0 kd O S vdivepas 16 9 66935 CI CE Lvd cEDAS CI 66 O Sd LEDAS CI ve L Sd 0 ods GE 6 Sd 6290dS 96 Sd 820dS CI LE S3C831B 100 QFP 1420C VGd Z2DAS CI 86 GGd 9ZDAS CI 66 9Gd S2DAS CI OV LGd peDAS C 1 0 9d e203S CI ev L 9d ecoOdS CI 6 9d L2903S CI vv 9d 020dS CI Sv V9d 6LDAS CI 9r 9 94 81935 CI 99d ZLLDAS CI 8v 88 3 Z9d 9LDAS CI 6v Figure 1 2 S3C831B Pin Assignments 100 QFP 1420C 0 2d SLO3S CI 0S 3C831B P831B AMIF VSSPLL VCOAM VCOFM VDDPLL1 LVREN LVRSEL BIAS VLCO VLC1 VLC2 COMO COM1 COM2 COMS3 SEGO P8 7 SEG1 P8 6 SEG2 P8 5 SEG3 P8 4 SEG4 P8 3 SEG5 P8 2 SEG6 P8 1 SEG7 P8 0 SEG8 P7 7 SEG9 P7 6 SEG10 P7 5 SEG11 P7 4 SEG12 P7 3 SEG13 P7 2 SEG14 P7 1 3C831B P831B P2 1 AD1 P2 2 AD2 CI P2 3 AD3 P2 4 AD4 CI P2 5 AD5 P2 6 AD6 P2 7 AD7 CI AVDD CI P3 0 BUZ CI P3 1 SCKO P3 2 SO0 CI P3 3 SIO VDD Vss XOUT XIN TEST1 TEST2 P3 4 SCK1 RESET P3 5 SO1 P3 6 SM P3 7 P4 0 SEG39 P4 1 SE
2. INTPND 230 EH J O O Location E7H is not mapped Watch Timer Control Register WTCON 232 0 0 0 o o o 0 SIO 0 Control Register 5 000 233 EH 0 SlOODataRegiser SIOODATA 234 EAH 0 0 0 0 O JO J O O SIO 0 PrescalerRegster 800 235 SIO 1 Control SIOICON 2 ecn o Jo J O oO SIO 1 Data Register SIO1DATA 237 EDH 0 o o O O SIO 1 PrescalerRegster sioips 238 EH 0 Converter Control Register ADCON 239 EH 0 0 0 o o o 0 LCD Control Register teon 21 FIH 0 0 o o 0 LCD Mode Register LMOD 242 F2H 0 IF Counter Mode Register IFMOD 243 F3H 0 0 o Counter CNTY 244 0 oO OJO JO O Countero 245 FSH OJO JO O Location FAH is not mapped STOP Control Register STPCON 251 en 0 0 O O Location FCH is not mapped Basic Timer Data Register BTCNT 253 Location is not mapped interrupt Priority Register rex x x x x x x x NOTE Refer to the corresponding register in the chapter 4 ELECTRONICS 8 3 RESET and POWER DOWN 3C8
3. Interval mode Lo 4 Capture mode capture on rising edge counter running OVF can occur a e Capture mode capture on falling edge counter running OVF can occur 1 PWM mode OVF amp match interrupt can occur er 0 Counter Clear Bit note No effect 2 Ti 3 1 Clear the timer 0 counter when write Timer 0 Match Capture Interrupt Enable Disable interrupt 1 Enable interrupt 0 Timer 0 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt NOTE When you write a 1 to TOCON 2 the timer 0 counter value is cleared to 00H Immediately following the write operation the TOCON 2 value is automatically cleared to O ELECTRONICS 4 4 CONTROL REGISTERS 3C831B P831B T1CON Timer 1 Control Register E5H Set 1 Bank 0 Bit Identifier RESET Value Read Write Addressing Mode 7 5 8 4 3 2 4 j 9 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Timer 1 Input Clock Selection Bits ojojoj Fo o r me op oe External clock T1CLK input Not used for the S3C831B Timer 1 Counter Clear Bit Note No effect Clear the timer 1 counter when write Timer 1 Counter Enable Bit Disable counting operation 1 Enable counting operation Timer 1 Interrupt Enable Bit Disable timer 1 interrupt 1 Enable timer 1 interr
4. port with bit programmable pins Schmitt INTO INT3 trigger Input or push pull output and software 92 95 assignable pull ups Alternately used for external interrupt input noise filters interrupt enable and pending control P1 4 P1 7 with bit programmable pins 98 1 INT4 INT7 Input or push pull and software assignable 96 99 pull ups Alternatelv used for external interrupt input Noise filters interrupt enable and pending control P2 0 P2 7 port with bit programmable pins Schmitt 2 9 ADO AD7 trigger input or push pull output and software 100 7 assignable pull ups port with bit programmable pins Input or push pull open drain output and software assignable pull ups P4 0 P4 7 1 O port with nibble programmable pins Input or zs SEG39 SEG32 push pull open drain output and software 24 31 assignable pull ups P5 0 P5 7 Same as Port 4 34 41 SEG31 SEG24 32 39 P6 0 P6 7 port with nibble programmable pins Schmitt H 41 42 49 SEG23 SEG16 trigger input or push pull open drain output and 40 47 software assignable pull ups P7 0 P7 7 I O Same as Port 6 H 41 50 57 SEG15 SEG8 48 55 P8 0 P8 7 I O Same as Port 6 H 41 58 65 SEG7 SEGO 56 63 NOTE The parentheses indicate pin number for 100 TQFP 1414 package 1 6 ELECTRONICS 3C831B P831B PRODUCT OVERVIEW Table 1 1 S3C831B Pin Descriptions Continued Pi Pin Circuit Type Description Type
5. IDLE LED The Yellow LED is ON when the evaluation chip S3E8310 is in idle mode STOP LED The Red LED is ON when the evaluation chip S3E8310 is in stop mode ELECTRONICS 23 5 DEVELOPMENT TOOLS 3C831B P831B Preliminary Spec P1 7 P2 0 P7 2 P2 1 P2 2 P7 4 P2 3 P2 4 P7 6 P2 5 P2 6 P8 0 P2 7 NC P8 2 P3 0 P3 1 P8 4 P3 2 P3 3 P8 6 User_Vcc GND COM3 XOUT XIN 1 GND GND VLC2 P3 4 DEMO_RSTB VLCO P3 5 P3 6 LVRSEL P3 7 P4 0 VDD P4 1 P4 2 VCOAM P4 3 P4 4 AMIF P4 5 P4 6 NC P4 7 P5 0 EO1 P5 1 P5 2 PO O P5 3 P5 4 PO 2 P5 5 P5 6 PO 4 P5 7 P6 0 PO 6 P6 1 P6 2 P1 0 P6 3 P6 4 P1 2 P6 5 P6 5 P1 4 P6 7 P7 0 P1 6 10J99UUO0Q Uld 0S 10199UUO Uld 0S Figure 23 3 50 Pin Connectors J101 J102 for TB831B Target Board Target System J101 J102 J102 J101 1 2 51 52 51 5211 2 aS Se eee Part Name AS50D A Order Cods SM6305 im p SSS 49 50 99 100 99 100 49 50 Figure 23 4 S3C831B P831B Probe Adapter Cables for 100 QFP Package JOJOSUUOND 09 I 7 2 2 e 9 23 6 ELECTRONICS
6. Relationship to Interrupt Pending Bit Types As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with either type of pending condition clear function by hardware or by software Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends ELECTRONICS 5 17 INTERRUPT STRUCTURE 3C831B P831B NOTES 5 18 ELECTRONICS 3C831B P831B INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM88RC instruction set is specifically designed to support the large register files that are typical of most SAMB8 microcontrollers There 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file
7. apn o 07 P2 7 End of Conversion read only Conversion not complete Conversion complete Clock Source Selection Bits ojoje 771 oppe To fa Start or Enable Bit Disable operation 1 Start operation automatically disable operation after conversion complete CONTROL REGISTERS 3C831B P831B BTCON Basic Timer Control Register D3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset fifo 1 Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits o wumem 7 4 Basic Timer Counter Clear Bit 1 No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for all timers 2 No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to OOH Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to OOH Immediately following the write operation the 0 value is automatically cleared to 0 3 The fxx is selected clock for system main OSC only for S3C831B 4 6 ELECTRONICS 3C831B P831B CONTROL REGISTER CLKC
8. ELECTRONICS 10 3 BASIC TIMER and TIMER 0 3C831B P831B RESET or STOP Basic Timer Control Register y Write 1010xxxxB to Disable Data Bus fxx 4096 fxx 1024 8 Bit Up Counter fxx 128 BTCNT Read Only fxx 16 Start the CPU nete NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS 3C831B P831B BASIC TIMER and TIMER 0 8 BIT TIMER COUNTER 0 Timer counter 0 has three operating modes one of which you select using the appropriate setting Interval timer mode Capture input mode with a rising or falling edge trigger at the PO 2 pin PWM mode Timer counter 0 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input PO 1 TOCLK 8 bit counter TOCNT 8 bit comparator and 8 bit reference data register TODATA pins for capture input match output or PWM output PO 2 TOCAP P0 3 TOOUT PO 3 TOPWM Timer 0 overflow interrupt IRQO vector E2H and match capture interrupt IRQO vector EOH generation Timer 0 control register set 1 E2H bank 0 read write TIMER COUNTER 0 CONTROL REGISTER TOCON You use the timer 0 control register TOCON to Select the timer 0 operating mode interval timer capture mode or PWM mode Select th
9. No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F2 r Given RO 77H R6 30H and R7 OOH LDCPD RR 6 RO RR6 RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR 6 RO RR6 RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONICS 3C831B P831B INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI dst src Operation rr rm 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Im or Examples Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt RR6 1 contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 RR6 1 7FH con
10. 3C831B P831B CONTROL REGISTER P2CONL Port 2 Control Register Low Byte E9H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 AD3 Schmitt trigger input mode Lo 4 Schmitt trigger input mode pull up 1 0 Alternative function ADC mode Output mode push pull 5S 4 P2 2 AD2 Co o Smmswermumoe Fo Schmit tigger input mode pue 7119 Aternatve turcion 3 2 P2 1 AD1 Co Sermin viager nomos Fo 1 Schmit tigger input mode 71129 ater tuncion 1 0 P2 0 ADO Schmitt trigger input mode fo 4 Schmitt trigger input mode pull up 1 o Alternative function ADC mode Output mode push pull ELECTRONICS 4 25 CONTROL REGISTERS 3C831B P831B P3CONH Port 3 Control Register High Byte EAH Set 1 Bank 1 Bit Identifier 8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 ofo 0 1 Output mode open drain S 1 0 Not availabe o 5 4 P3 6 SI1 79111 ouput mose open drain afoma SSS 3 2 P3 5 SO1 o ouput moe open drain 7 Jateratvetuneton so 1 0 P3 4 SCK1 0 o Imutmode SCK 0 1 Output mode pullup 117111 1 Al
11. Bytes Cycles Opcode Hex 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to use an EXIT statement Before After Address Data IP 0052 Address Data PC 0060 PCL old PCH 60 Main SP 0022 Exit 22 Data Memory Stack ELECTRONICS 3C831B P831B INSTRUCTION SET IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation In application programs a IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock NOP NOP NOP ELECTRONICS 6 43 INSTRUCTION SET INC Increment INC dst Operation dst lt dst 1 The contents of the destination operand are incremented by Unaffected Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherw
12. Counter PO 6 T2CLK gt 16 Bit Timer PO 7 T2OUT lt Counter2 P3 1 SCKO lt gt P3 2 500 4 SIO 0 P3 3 SIO P3 4 SCK1 lt gt P3 5 501 4 SIO 1 6 511 Timer P3 0 BUZ 4 Watch Timer Port and Interrupt Control SAM88RC Core COMO 3 4 P8 7 P4 0 SEGO 39 LCD Driver BIAS 4 Controller Vico ViC2 VCOAM gt BE VCOFM gt 00 601 Synthesizer AMIF gt gt IF Counter P2 0 P2 7 ADO AD7 bj 8 Bit ADC 2576 byte Register File P8 0 SEG7 lt gt P8 1 SEG6 lt gt P8 2 SEG5 bid P8 3 SEG4 P8 4 sEG3 gt 8 P8 5 SEG2 45 P8 6 SEG1 4 P8 7 SEGO lt gt LVREN Low Voltage LVRSEL Reset t 1 1 TEST1 VDD VSS TEST2 VDDPLLO VSSPLL VDDPLL1 Figure 1 1 Block Diagram ELECTRONICS PRODUCT OVERVIEW HH UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU UUUUUUUU NNNANNAN gox ooOoo BBERBBRM QUOXOOUOUOOO lt OOOOOOOO TIOXOMPROXN O NOUBWONM O OOHRON QO IOOHnRCON CO SS SS SSS 202020202020202 202020202020202 202020202020202 NNNNNNMW TTNTITTWTITTITTITTNTI DOOOODOOG C000 0 00000006 Q0Q0Q00OQO0O NNNNNNWW WWWWWWWW ONURU ONOONO J4O10 J0X0O
13. Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI 6 2 Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst
14. 5 Lev 15 IRQ5 Request Pending Bit 1 4 1 7 ot pending 1 ending 4 Lev 14 IRQ4 Request Pending Bit P1 0 P1 3 ot pending ending 3 Level 3 IRQ3 Request Pending Bit Watch Timer ot pending 8 2 1 ending 2 Level 2 IRQ2 Request Pending Bit SIO 0 SIO 1 Interrupt ot pending 1 ending 4 Level 1 IRQ1 Request Pending Bit Timer 1 Timer 2 Interrupt l le ot pending ending 0 Level 0 IRQO Request Pending Bit Timer 0 Match Capture or Overflow Not pending Pending 4 14 ELECTRONICS 3C831B P831B CONTROL REGISTER cD Control Register F1H Set 1 Bank 0 RESET Value 0 0 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 LCD Output Control LCD output is low and current to dividing resistors is cut off IF LMOD 3 0 LCD display is turned off IF LMOD 3 1 output COM and SEG signals in display mode 6 4 Not used for the S3C831B 3 0 LCD Port Selection Bit 00070 JseleoilCDSEGO 38 o 0 1 Select LoD SEGO 35 P4 0 4 3 as VO pot PO 0 1 OjSeecLCDSEGOSMPAaslOpot 0 0 1 Select Lcd SEGO 27 PA 5 0 5 3 as VO pot o 1 0f 0 Select LoD SEGo 28 P4 P5 as VO porn 0 1 of 1 Select LCD SEGO 19 P4 P5 P6 0 6 3 as VO porn _0 Select LOD SEGO 7 PA PS P6 P7 as VO pot 1 1 1 Select LCD SEG
15. PLLMOD 1 0 Disable INTCE interrupt requests at CE pin MG Enable INTCE interrupt requests at CE pin PLLMOD O a INTCE interrupt is not pending when Clear INTCE pending bit when write INTCE interrupt is pending when read Frequency Division Method Selection Bit PLLMOD 7 Frequency Division Selected Pin Input Input Division Value and Method Voltage Frequency PLLMOD 4 Direct method for AM VcoaM Selected 300mVpp 0 5 30 MHz 16 to 216 1 Vcorw Pulled Low AM Vcorm Pulled Low for AM Vcorm Pulled Low for FM VcoAw Pulled Low NOTE The NF bit a one bit frequency division value is written to bit O in the swallow counter 18 6 ELECTRONICS 3C831B P831B PLL FREQUENCY SYNTHESIZER PLL REFERENCE FREQUENCY SELECTION REGISTER PLLREF The PLL reference frequency selection register PLLREF used to determine the reference frequency You can select one of ten reference frequencies by setting bits PLLREF 3 PLLREF 0 to the appropriate value You can select one of the reference frequencies by setting bits PLLREF 3 PLLREF O Table 18 2 PLLREF Register Organization When fxx 4 5 MHz o o o Select thtizasreference o o o 1 Select ata as reference frequency o o 1 o Select sktz as reference equency o o 1 Select 625 ie reference frequency NA E e a ooo strc femen o o o 1 Select100kkzas reference frequenc
16. fxx 256 gt TOCON 2 fxx 64 fxx 8 pos MUX 8 Bit Up Counter TOCLK Read Only LI TOCON 1 Vss _ gt 8 Bit Comparator V Timer 0 Buffer Register TOCAP x B TOCON 4 3 Match signal TOCON 4 3 N Ct TO Timer 0 Data Register Data BUS Figure 10 8 Timer 0 Block Diagram ELECTRONICS 10 11 BASIC TIMER and TIMER 0 3C831B P831B NOTES 10 12 ELECTRONICS 3C831B P831B 8 BIT TIMER 1 1 1 8 BIT TIMER 1 OVERVIEW The 8 bit timer 1 is an 8 bit general purpose timer Timer 1 has the interval timer mode by using the appropriate T1CON setting Timer 1 has the following functional components Clock frequency divider fxx divided by 256 64 8 or 1 with multiplexer External clock input PO 4 T1CLK 8 bit counter T1CNT 8 bit comparator and 8 bit reference data register T1 DATA Timer 1 interrupt IRQ1 vector E6H generation Timer 1 control register TT CON set 1 Bank 0 E5H read write FUNCTION DESCRIPTION Interval Timer Function The timer 1 can generate an interrupt the timer 1 match interrupt T1INT T1INT belongs to interrupt level IRQ1 and is assigned the separate vector address E6H The T1INT pending condition should be cleared by software when it has been serviced Even though T1INT is disabled the application s service routine can detect a pending condition of T1INT by the software and execute its sub routine When
17. 0 Receive only mode 1 Transmit receive mode Shift clock edge selection bit 0 tx at falling edeges rx at rising edges 1 tx at rising edeges rx at falling edges NOTE SIOO interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending SIOO interrupt enable bit 0 Disable SIOO interrupt 1 Enable SIOO interrupt SIOO shift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter 5100 counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting It is selected SCKO and SOO output type push pull or open drain by PG2CON 6 Figure 16 1 Serial I O Module Control Register SIOOCON ELECTRONICS 3C831B P831B SERIAL INTERFACE Serial I O Module Control Register SIO1CON ECH Set 1 Bank 0 R W SIO1 shift clock selection bit 0 Internal clock P S Clock 1 External clock SCK1 Data direction control bit 0 MSB first mode 1 LSB first mode SIO1 mode selection bit 0 Receive only mode 1 Transmit receive mode Shift clock edge selection bit 0 tx at falling edeges rx at rising edges 1 tx at rising edeges rx at falling edges NOTE SIO1 interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending SIO1 interrupt enable bit 0 Disable SIOO interrupt 1 Enable SIOO interrupt SIO1 sh
18. C L L COMO0 COM3 DO o z 3 ommon signal output for LCD display H CD segment signal output H 41 4 H 42 n SEGO SEG23 O 65 42 63 40 SEG24 SEG39 A CD segment signal output BIAS VLCO VLC1 VLC2 LCD power control LCD power supply Voltage dividing resistors are assignable by software Main power supply PLL IFC power supply PLL IFC ground A D converter power supply Main oscillator pins for CPU oscillation Test signal input pin Must be connected to Vas LVR criterion voltage selection pin Must be connected to Vpp or Vss LVR enable pin Must be connected to Vpp or Vss System reset pin Input pin for checking device power B Normal operation is high level and PLL IFC Operation is stopped at low power PLL s phase error outputO PLL s phase error output1 External VCOAM VCOFM signal inputs NOTE The parentheses indicate pin number for 100 TQFP 1414 package i 73 71 4 op Oo oi 1 e VDDPLLO 1 N RO 80 74 VSSPLL 79 10 gt 2 o o o gt lt O c E x z i N g S9 TEST1 TEST2 17 18 LVRSEL 74 72 k so 29 LVREN 75 N NR e B A A RESET 5 85 83 m o m 83 8 84 8 78 77 76 75 N B 4 gt gt ELECTRONICS 1 7 PRODUCT O
19. E9H and P2CONH high byte E8H In input mode ADC voltage input are also available Port 2 Control Registers Two 8 bit control registers are used to configure port 2 pins P2CONL E9H set 1 Bank 1 for pins 2 0 2 3 and P2CONH E8H set 1 Bank 1 for pins P2 4 P2 7 Each byte contains four bit pairs and each bit pair configures one port 2 pin The P2CONH and the P2CONL registers also control the alternative functions Port 2 Control Register High Byte P2CONH E8H Set 1 Bank 1 R W mw 4 AD4 P2 5 AD5 P2 6 AD6 P2 7 AD7 P2CONH bit pair pin configuration Schmitt trigger input mode Schmitt trigger input mode pull up Alternative function ADC mode Output mode push pull Figure 9 8 Port 2 High Byte Control Register P2CONH ELECTRONICS 9 9 PORTS 3C831B P831B Port 2 Control Register Low Byte P2CONL E9H Set 1 Bank 1 R W P2 3 ADC3 P2CONL bit pair pin configuration Schmitt trigger input mode Schmitt trigger input mode pull up Alternative function ADC mode Output mode push pull Figure 9 9 Port 2 Low Byte Control Register P2CONL 9 10 ELECTRONICS 3C831B P831B PORTS PORT 3 Port 3 is an 8 bit I O port with individually configurable pins Port 3 pins are accessed directly by writing or reading the port 3 data register P3 at location F3H in set 1 bank 1 P3 0 P3 7 can serve as inputs or as push pull open drain outputs You can configure the following alternative func
20. Example 6 68 dst src IR IR 1 dst src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst SIC 3 8 83 IR R Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00H 01H Register 00H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS 3C831B P831B INSTRUCTION SET RCF Reset Carry Flag RCF RCF Operation lt 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET 3C831B P831B RET Return RET Operation Flags Format Example 6 70 PC SP SP lt SP 2 The RET instruction is normally used to return to the previously executing procedure at th
21. Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ ELECTRONICS 5 13 INTERRUPT STRUCTURE 3C831B P831B INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C831B interrupt structure the timer 0 overflow interrupt IRQO belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location
22. Port 3 Pull up Control Register ECH Set 1 Bank 1 R W TTTTTTTT P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 P3PUR bit configuration settings 0 Disable pull up resistor Enable pull up resistor NOTE The corresponding pull up resistor is disabled automatically when a bit of port 3 is selected as output mode Figure 9 12 Port 3 Pull up Control Register P3PUR 3C831B P831B ELECTRONICS 3C831B P831B PORTS PORT 4 5 Port 4 and 5 are 8 bit I O ports with nibble configurable pins respectively Port 4 and 5 pins are accessed directly by writing or reading the port 4 and 5 data registers P4 at location F4H and P5 at location F5H in set 1 bank 1 4 0 4 7 and P5 0 P5 7 can serve as inputs with or without pull ups as output open drain or push pull And they can serve as segment pins for LCD also Port Group 0 Control Register Port 4 and 5 have a 8 bit control register PGOCON 4 7 for 4 0 4 7 PGOCON 0 3 for P5 0 P5 7 A reset clears the PGOCON register to OOH configuring all pins to input mode Port Group 0 Control Register EDH Set 1 Bank 1 R W mM 4 P5 7 SEG27 SEG24 P5 0 P5 3 SEG31 SEG28 P4 4 P4 7 SEG35 SEG32 P4 0 P4 3 SEG39 SEG36 PGOCON bit pair pin configuration settings Input mode Input mode pull up Output mode open drain Output mode push pull NOTE The shared I O ports with LCD segments should be selected as one of two by LCON 3 0 Figure
23. RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS 3C831B P831B ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or Value used
24. the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET 3C831B P831B SCF set Carry Flag SCF Operation Flags Format Example 6 78 Cei The carry flag C is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS 3C831B P831B INSTRUCTION SET SRA Shift Right Arithmetic SRA dst Operation dst 7 lt dst 7 C lt dst 0 dst n lt dst n 1 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags C Setif the bit shifted from the LSB position bit zero was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Always cleared to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R 4 D1 IR Examples Given Register 00H 9AH register 02H register OBCH and C 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H 03H register 03H ODEH C 0 In the first example i
25. 0001 DA DAY 4 14 A7 r DA 10 opc src 0001 DA DAY 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats and 4 the destination address XS rr and the source address XS are each one byte 3 For formats 5 and 6 the destination address rr and the source address rr are each two bytes 4 The DA and r source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory 6 52 ELECTRONICS 3C831B P831B LDC LDE Load Memory LDC LDE Continued INSTRUCTION SET Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC LDE LDC note LDE LDC LDE LDC note LDE LDC LDE LDC LDE LDC note LDE RO RR2 RO RR2 RR2 R0 RR2 R0 RO 01H RR2 RO 01H RR2 01H RR2 RO 01H RR2 RO RO 1 O00H RR2 RO 1 000H RR2 R0 1104H R0 1104H 1105H RO 1105H RO RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 working
26. 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 000001 11B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS 3C831B P831B INSTRUCTION SET BTJRF sit Test Jump Relative on False BTJRF dst src b Operation If src b is a then PC lt PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Re
27. 2 4 Set 1 Set 2 Prime Area Register and LCD Data Register Map ELECTRONICS 2 7 ADDRESS SPACES 3C831B P831B WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byt
28. 3C831B P831B CONTROL REGISTER P1CONL Port 1 Control Register Low Byte E5H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 INT3 Schmitt trigger input mode pull up interrupt on falling edge Lo 4 Schmitt trigger input mode interrupt on rising edge 1 Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull 5 4 P1 2 INT2 Lo o Schmit ager input mode pulkup interrupt on taling edge Lo 1 Schmit rigger input mode interrupt on rising edge Schmit viager input mode interrupt on rising or taling edge 3 2 P1 1 INT1 Lo o Schmit ager input mode interrupt on taling edge Lo 1 Schmit rigger input mode imerrupt on rising edge 71170 Schmit viager input mode interrupt on rising or taling edge 1 0 P1 0 INTO Schmitt trigger input mode pull up interrupt on falling edge Lo 4 Schmitt trigger input mode interrupt on rising edge 1 Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull ELECTRONICS 4 21 CONTROL REGISTERS 3C831B P831B P1INT Port 1 Interrupt Control Register E6H Set 1 Bank 1 Bit Identifier o8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 External Interru
29. 6 511 7 P4 0 SEG39 P4 1 SEG38 P4 2 SEG37 P4 3 SEG36 P4 4 SEG35 Figure 22 1 S3P831B Pin Assignments 100 Pin QFP Package 22 2 88 dVO0L 2 0d Z8 E3 M100L 1 0d S3P831B 100 QFP 1420C S vrd veOdS C3 LE 9 vd OdS CE Lvd eeD3as Eg OGd LEDAS ve L Sd 0 OdS GE 8 Sd ecOds 9 99 8 995 LE VGd LEDAS 8 GGd 92DAS C4 6 9 Sd ScOdS OV L Sd vcOdS C3 Hv 0 9d ecOdS L 9d ecOdS ec 9d IecOdS vv 694 00046 Sr V9d 6LDAS 9v G9d 8LDAS Zr 99d ZIDAS 8v L 9d 91O0dS 6v 0Zd SLO3S 06 3C831B P831B AMIF VSSPLL VCOAM VCOFM VDDPLL1 LVREN LVRSEL BIAS VLCO VLC1 VLC2 COMO 1 2 COM3 SEGO P8 7 SEG1 P8 6 SEG2 P8 5 SEG3 P8 4 SEG4 P8 3 SEG5 P8 2 SEG6 P8 1 SEG7 P8 0 SEG8 P7 7 SEG9 P7 6 SEG10 P7 5 SEG11 P7 4 SEG12 P7 3 SEG13 P7 2 SEG14 P7 1 ELECTRONICS 3C831B P831B P2 1 AD1 1 P3 1 SCKO C SDAT P3 2 SO0 SCLK P3 3 SIO C VDD VDD CE Vss Vss XOUT L XIN C VPP TEST1 CE TEST2 P3 4 SCK1 C RESET RESET CE P3 5 SO1 CE P3 6 SM C P3 7 P4 0 SEG39 C P4 1 SEG38 Figure 22 2 S3P831B Pin Assignments 100 Pin TOFP Package ELECTRONICS IL td 9 Ld IG td IV kd kd 0 kd 66 ZIN 86 4 91N 46 E3 GIN 96 F3 PLN 96 v6 L3 cIN 6 LIN 26 OLN c vrd 9d3S CI 9c vd 96D3S C
30. 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 14 ELECTRONICS 3C83
31. ELECTRONICS 3C831B P831B CONTROL REGISTER INTPND Interrupt Pending Register E6H Set 1 Bank 0 RESET Value 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 2 Not used for the S3C831B Timer 0 Match Capture Interrupt Pending Interrupt request is not pending when read pending bit clear when write 0 Interrupt request is pending 0 Timer 0 Overflow Interrupt Pending Bit Interrupt request is not pending when read pending bit clear when write 0 Interrupt request is pending ELECTRONICS 4 1 CONTROL REGISTERS 3C831B P831B IPH instruction Pointer High Byte DAH Set 1 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only T 0 Instruction Pointer Address High Bvte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 1P8 The lower byte of the IP address is located the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET Value X X X X X X X x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only T 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH 4 12 ELECTRONICS 3C
32. INCW QHR1 gt Register 02H 10H register 03H OOH In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value 03H in register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to 00H and register 02H from OFH to 10H NOTE A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET 3C831B P831B IRET Interrupt Return IRET Operation Flags Format Example NOTE 6 46 IRET Normal IRET Fast FLAGS SP PC o IP SP lt SP 1 FLAGS lt FLAGS PC SP FIS 0 SP lt SP 2 SYM 0 lt 1 This instruction is used at the of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is
33. S3C831B interrupt structure there are seventeen possible interrupt sources When a service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE 3C831B P831B INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S Type 3 One level IRQn multiple vectors V4 V multiple sources S Sh S S nai nem In the S3C831B microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 IRQn 51 2 IRQn S2 5 5 51 3 IRQn NOTES 1 The number of Sn and Vn value is expandable 2 Inthe S8C831B implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Seri
34. S3C831B microcontroller is currently available in 100 pin QFP or 100 pin TQFP package 23 90 0 30 ooa 100 QFP 1420C 17 90 0 30 14 00 40 20 lili 0 80 0 20 Spe 2 65 0 10 3 00 0 80 0 20 osoon Figure 21 1 Package Dimensions 100 QFP 1420C NOTE Dimensions are in millimeters ELECTRONICS 21 1 MECHANICAL DATA 3C831B P831B 16 00 0 20 0 073 0 127 0 037 16 00 0 20 li D 100 TQFP 1414 JIS 0 45 0 75 i 0 05 0 15 1 00 0 05 1 20 MAX NOTE Dimensions are in millimeters Figure 21 2 Package Dimensions 100 TQFP 1414 21 2 ELECTRONICS 3C831B P831B S3P831B OTP S3P831B OTP OVERVIEW The S3P831B single chip CMOS microcontroller is the OTP One Time Programmable version of the S3C831B microcontroller It has an on chip OTP ROM instead of a masked ROM The EPROM is accessed by serial data format The S3P831B is fully compatible with the S3C831B both in function in D C electrical characteristics and in pin configuration Because of its simple programming requirements the S3P831B is ideal as an evaluation chip for the S3C831B ELECTRONICS 22 1 S3P831B OTP P1 7 INT7 P2 0 ADO P2 1 AD1 P2 2 AD2 P2 3 AD3 P2 4 AD4 P2 5 AD5 P2 6 AD6 P2 7 AD7 AVDD P3 0 BUZ P3 1 SCKO SDAT P3 2 SO0 SCLK P3 3 SIO VDp VDD Vss Vss XOUT XIN VPP TEST1 TEST2 P3 4 SCK1 RESET RESET P3 5 SO1
35. S3P831B OTP 3C831B P831B NOTES 22 6 ELECTRONICS 3C831B P831B DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for S307 S3C9 S3C8 families of microcontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source
36. TOOLS TB831B TARGET BOARD The TB831B target board is used for the S3C831B P831B microcontroller It is supported with the SMDS2 Smart Kit and OPENice TB831B rev 2002 12 24 a N To User Vcc E 5 off Jo 22 RESET JP6 Y1 X tal Xin X tal MDS i TB831B 160 QFP 19 29 50 Connector 50 Connector 39 4 JP5 JP2 JP1 LV ON LVRSEL LVRSN EY OEF SM1344A Figure 23 2 TB831B Target Board Configuration ELECTRONICS 23 3 DEVELOPMENT TOOLS 3C831B P831B Table 23 1 Power Selection Settings for TB831B To User Vcc Operating Mode Comments Settings To User Vcc The SMDS2 SMDS2 supplies Vcc to the target an Deo On TAPSIR board evaluation chip and the target system To User Vcc The SMDS2 SMDS2 External supplies Vcc only to the target ui o en Vcc gt board evaluation chip Vss The target system must have its own power supply NOTE The following symbol in the To User Vcc Setting column indicates the electrical short off configuration 23 4 ELECTRONICS 3C831B P831B DEVELOPMENT TOOLS SMDS2 SELECTION 8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 23 2 The SMDS2 Tool Selection Setting Operating Mode RW Target System SMDS2
37. The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 3C831B P831B INSTRUCTION SET DA Decimal Adjust DA dst Operation dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For a
38. WATCH TIMER 3C831B P831B NOTES 13 4 ELECTRONICS 3C831B P831B LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C831B microcontroller can directly drive an up to 20 digit 40 segment LCD panel The LCD block has the following components LCD controller driver Display RAM 00H 13H for storing display data in page 9 40 segment output pins SEGO SEGS39 Four common output pins 0 Three LCD operating power supply pins Vi co Vi c2 and bias pin for LCD driving voltage cp LCD voltage dividing resistors Bit settings in the LCD mode register LMOD determine the LCD frame frequency duty and bias and LCD voltage dividing resistors The LCD control register LCON turns the LCD display on and off and switches current to the LCD voltage dividing resistors for the display LCD data stored in the display RAM locations are transferred to the segment signal pins automatically without program control Bias LCD VLCO VLC2 Controller Driver COMO0 COMS3 sng 19 8 SEGO SEG39 Figure 14 1 LCD Function Diagram ELECTRONICS 14 1 LCD CONTROLLER DRIVER 3C831B P831B LCD CIRCUIT DIAGRAM SEG39 P4 0 SEG38 P4 1 SEG37 P4 2 SEG36 P4 3 SEG35 P4 4 SEG34 P4 5 Segment Driver SEG16 P6 7 SEG15 P7 0 SEG14 P7 1 SEG13 P7 2 SEG12 P7 3 SEG11 P7 4 T SEGO P8 7 COM3 Timing COM COM2 Controller Control COM1 COMO 4 H LCD Voltage Control
39. address E8H and is read write addressable using register addressing mode A reset clears WTCON to 00H This disable the watch timer So if you want to use the watch timer you must write appropriate value to WTCON Watch Timer Control Register WTCON E8H Set 1 Bank 0 R W Not used wal timer interrupt pending bit 0 Interrupt request is not pending Clear pending bit when write 0 Watch timer Enable Disable bit 1 Interrupt request is pending 0 Disable watch timer 1 Enable watch timer Watch timer INT Enable Disable bit 0 Disable watch timer INT Buzzer signal selection bits Enable watch timer INT When fxx 4 5 MHz 00 1 kHz Watch timer speed selection bits 01 1 5 kHz When fxx 4 5 MHz 10 3 kHz 00 Set watch timer interrupt to 1 s 11 6 kHz 01 Set watch timer interrupt to 0 5 s 11 Set watch timer interrupt to 50 ms NOTE If the main clock is 9MHz IFMOD 7 should be set to 1 Figure 13 1 Watch Timer Control Register WTCON 13 2 ELECTRONICS 3C831B P831B WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM BUZZER Output WTCON 1 WTINT 1 kHz 1 5 kHz 3 kHz 6 kHz Circuit Enable Disable WTCON 6 Frequency Divider Frequency 285 Dividing LEE 32 768 kHz Creu 22 meer fLcD 500 Hz fxx Main clock fw Watch timer clock When fxx 4 5MHz and IFMOD 7 0 Watch timer clock When fxx 9 0MHz and IFMOD 7 1 Figure 13 2 Watch Timer Circuit Diagram ELECTRONICS 13 3
40. bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 42 6 43 r Ir opc SIC dst 3 6 44 R R 45 R IR opc dst SIC 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH R1 2AH OR R0 R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H 3FH register 01H 37H OR 01H 00H gt Register OOH 08H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO RT logical ORs the RO and R1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS 3C831B P831B INSTRUCTION SET POP Pop From Stack POP dst Operation dst SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one Flags No flags affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 8 51 IR Examples Given Register 00H 01H register 01H SPH OD8H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00H gt Registe
41. bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET 3C831B P831B RRC Rotate Right Through Carry RRC Operation dst dst 7 C C lt dst 0 dst n lt dst n 1 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples 6 74 C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 R 4 C1 IR Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register OOH 2AH C 1 RRC 01H Register 01H 02H register 02H OBH C 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC OOH rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the
42. file and an auxiliary definition DEF file with device specific information SASM88 The SASMBS is a relocatable assembler for Samsung s S3C8 series microcontrollers The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM88 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code OBJ file by HEX2ROM the value FF is filled into the unused ROM area up to the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all S8C8 series microcontrollers All required target system cables and adapters are included with the device specific target board ELECTRONICS 23 1 DEVELOPMENT TOOLS 3C831B P831B IBM PC AT or Compatible RS 232C SMDS2 4 PROM OTP Writer Unit Target Application Am RAM Break Displav Unit Svstem Trace Timer Unit TB831B lt q SAM8 Base Unit Target Board Eva lt gt Power Supply Unit Chip Figure 23 1 SMDS Product Configuration SMDS2 23 2 ELECTRONICS 3C831B P831B DEVELOPMENT
43. for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 900H gt Register OOH 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 200H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET 3C831B P831B PUSH Push To Stack PUSH Operation Flags Format Examples 6 66 src SP SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH OOH and SPL OOH PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH
44. in 1 points to Instruction MN working register block Program Memory 5o 4 Base Address Address speran dst src E Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES 3C831B P831B INDEXED ADDRESSING MODE Continued Register File Cd RPO or RP1 RPO or RP1 Selected RP points to start of Program Memory 22 OFFSET i RA NEXT 2 Bits 4 bit Working dst src x L Register Register Address Point to Working Pair block Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in E em Sample Instructions LDC R4 404H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS 3C831B P831B ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File orna cu RPO or RP1 RPO or RP1 Selected o o RP points to start of working register BEEN block Program Memory OFFSET OFFSET NEXT 2 Bits 1 1 U 1 U 4 bit Working detis e Re
45. input Input with interrupt generation on falling rising edges P1 0 3 Schmitt trigger input Port 1 Interrupt Enable and Pending Registers P1INT P1PND To process external interrupts at the port 1 pins two additional control registers are provided the port 1 interrupt enable register P1INT E6H set 1 bank 1 and the port 1 interrupt pending register P1PND E7H set 1 bank 1 The port 1 interrupt pending register P1PND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P1PND register at regular intervals When the interrupt enable bit of any port 1 pin is 1 a rising or falling edge at that pin will generate an interrupt request The corresponding P1PND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a 0 to the corresponding P1PND bit 9 6 ELECTRONICS 3C831B P831B PORTS Port 1 Control Register High Byte P1CONH E4H Set 1 Bank 1 R W INT7 INT6 INT5 P1CONH bit pair pin configuration Input mode pull up interrupt on falling edge Input mode interrupt on rising edge Input mode interrupt on rising or falling edge Output mode push pull Figure 9 4 Po
46. is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W ul logic 0 Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Not used for the S3C831B Fast interrupt level selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing E Figure 5 5 System Mode Register SYM ELECTRONICS 5 9 INTERRUPT STRUCTURE 3C831B P831B INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level
47. is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS 3C831B P831B ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES 3C831B P831B INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS 3C831B P831B ADDRESSIN
48. is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W Interrupt level enable bits 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR 5 10 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for t
49. is forced Low level and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation All interrupt is disabled The watchdog function basic timer is enabled Ports 0 3 are set to input mode and all pull up resistors are disabled for the I O port Peripheral control and data register settings are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the Test pin is tied to Vgc A reset enables access to the 64 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET and POWER DOWN 3C831B P831B HARDWARE RESET VALUES Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and
50. millisecond or 8 millisecond interval setting with a rising clock edge When the gate is open the frequency at the AMIF or FMIF pin is counted by the 16 bit counter When the gate closes the IFC gate flag IFCFG is set to 1 An interrupt is then generated and the IFC interrupt pending bit PLLMOD 2 is set Figure 19 2 shows gate timings with a 1 kHz internal clock sees U U 2 ms U U 8 ms l l l I l l l 16 ms Counting Period n L Gate open here Counting ends IFMOD is written IFCFG flag is set to 1 and IFCFG flag is cleared to O PLLMOD 2 is set to 1 2 Figure 19 2 Gate Timing 2 8 or 16 ms 19 4 ELECTRONICS 3C831B P831B INTERMEDIATE FREQUENCY COUNTER Selecting Gate Remains Open If you select gate remain open IFMOD 0 and IFMOD 1 1 the IFC counts the input signal during the open period of the gate The gate closes the next time a value is written to IFMOD Clock 1 kHz 1 U 1 t Gate Time o 0 Counting Period The gate closes when IFMOD is rewritten Gate is opened by writing IFMOD Figure 19 3 Gate Timing When Open When you select gate remains open as the gating time you can control the opening and closing of the gate in one of two ways Set the gate time to a specific interval 2 ms 8 ms or 16 ms by setting bits IFMOD 1 and IFMOD O G
51. of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H SP 0000H Memory locations 0000H 0001H where 4AH is the address that follows the instruction CALL RRO SP 0000H 0000H 0001H 49H CALL 40H 9 SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two
52. of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or RP1 Address These address bits indicate 8 bit 8 bit logical working register address addressing Register pointer hree low order bits provides five high order bits LT TTT tt ty Do 8 bit physical address Figure 2 13 8 Bit Working Register Addressing 2 16 ELECTRONICS 3C831B P831B ADDRESS SPACES RPO Selects RP1 R11 8 bit address Register 1100 form instruction 10101 01 1 address LD R11 R2 OABH Specifies working register addressing Figure 2 14 8 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES 3C831B P831B SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3C831B architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and
53. ouput mose open drain afoma SSS 3 2 P0 5 T10OUT Fo o mumd S Co ouput mode openan SSS y S 71120 Jateratvetuneton OU 1 0 PO 4 T1CLK o 0 Input mode TICLK Lo 4 Output mode open drain 1 0 Notavaiiable 1111000000 ELECTRONICS 4 17 CONTROL REGISTERS 3C831B P831B POCONL Port 0 Control Register Low Byte E1H Set 1 Bank 1 Bit Identifier 8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 PO 3 TOOUT TOPWM ofo Jinputmode o 0 1 Output mode open drain 11111100 1 0 Alternative function TOOUT TOPWM Output mode push pull 5 4 PO 2 TOCAP o o 72111 ouput mose opens afoma SOS 3 2 PO 1 TOCLK 0 79111 output moge opens afoma SSS 1 0 0 o o Jinputmode 000 0 1 JOutputmode open drain 11111000 1 0 Notavaiiable 1101000000 4 18 ELECTRONICS 3C831B P831B CONTROL REGISTER POPUR Port o Pull up Control Register E2H Set 1 Bank 1 Bit Identifier 8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 PO 7 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 6 PO 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 PO 5 Pull up Resistor Enable Bit Pull u
54. pin The PLL frequency synthesizer is disabled and the error output pin is set to floating state whenever the CE pin is Low When CE pin is High level the PLL operates normally The chip enable flag in the PLLREF register CEFG provides the status of the current level of the CE pin Whenever the state of the CE pin goes from Low to High the CEFG flag is set to 1 and a CE reset operation occurs When the CE pin goes from High to Low the CEFG flag is cleared to 0 and a CE interrupt is generated The power on flag in the PLLREF register POFG is set by initiated power on reset but it is not set when a reset occurs on the normal operation The POFG flag is cleared to 0 by writing 0 to POFG flag bit in PLLREF 18 8 ELECTRONICS 3C831B P831B PLL FREQUENCY SYNTHESIZER USING THE PLL FREQUENCY SYNTHESIZER This section describes the steps you should follow when using the PLL direct frequency division method and the pulse swallow method In each case you must make the following selections in this order 1 Frequency division method Direct frequency division and enable 3 bit counter AM or pulse swallow AM FM Input pin VCOAM or VCOFM Reference frequency fp 4 Frequency division value N Direct Frequency Division Method Select the direct frequency division method by writing a 0 to PLLMOD 7 and PLLMOD 4 The VCOAM pin is configured for input when you select the direct frequency division method Select the reference frequen
55. selection bits for function bit CPU clock frequency 0 Enable IRQ for main 00 fxx 16 wake up in power down mode 01 fxx 8 1 Disable IRQ for main 10 fxx 2 wake up in power down mode 11 fxx 1 non divided Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 3 CLOCK CIRCUIT 3C831B P831B STOP Control Register STPCON FBH Set 1 bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before execute the STOP instruction set this STPCON register as 10100101B Otherwise the STOP instruction will not execute as well as reset will be generated Figure 7 5 STOP Control Register STPCON 7 4 ELECTRONICS 3C831B P831B RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the RESET pin is forced to Low level The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings the S3C831B into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required time of a reset operation for oscillation stabilization is 1 millisecond Whenever a reset occurs during normal operation that is when both Vpp and RESET are High level the RESET pin
56. src 3C831B P831B Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS 3C831B P831B INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET 3C831B P831B Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true C
57. stops that is when the specified gate open time has elapsed The frequency applied to FMIF or AMIF pin is counted while the gate is open The frequency applied to FMIF pin is divided by 2 before counting The relationship between the count value and input frequencies and fee is shown below FMIF pin input frequency is fFMIF 2 when TG gate time 2 ms 8 ms 16 ms AMIF pin input frequency is fAMIF N DEC TG when TG gate time 2 ms 8 ms 16 ms Table 19 2 shows the range of frequency that you can apply to the AMIF and FMIF pins Table 19 2 IF Counter Frequency Characteristics o P Voltage Level Frequency Range AMIF 300 m Vpp min 0 1 MHz to 1 MHz FMIF 300 m Vpp min 5 MHz to 15 MHz ELECTRONICS 19 7 INTERMEDIATE FREQUENCY COUNTER 3C831B P831B INPUT PIN CONFIGURATION The AMIF and FMIF pins have built in AC amplifiers see Figure 19 5 The DC component of the input signal must be stripped off by the external capacitor When the AMIF or FMIF pin is selected for the IFC function and the switch is turned on voltage of each pin increases to approximately 1 2 Vpp after a sufficiently long time If the pin voltage does not increase to approximately 1 2 Vpp the AC amplifier exceeds its operating range possibly causing an IFC malfunction To prevent this from occurring you should program a sufficiently long time delay interval before starting the count operation Extern
58. the lower 32 byte area is a single 32 byte common area In case of S3C831B the total number of addressable 8 bit registers is 2 646 Of these 2 646 registers 13 bytes are for CPU and system control registers 57 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 2 560 registers are for general purpose use page 0 page 9 including 20 bytes for LCD display registers You can always address set 1 register locations regardless of which of the ten register pages is currently selected Set 1 locations however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C831B Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte 2 576 common working register area ten 192 byte prime register area including LCD data registers and ten 64 byte set 2 area CPU and system control registers 13 Mapped clock peripheral I O control and data registers 57 Total Addressable Bytes 2 646 ELECTRONICS 2 3 ADDRESS SPACES Bank 0 System and Peripheral Control Registers Register Addressing Mod
59. the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal Opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast OpC 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS 3C831B P831B INSTRUCTION SET JP Jump JP cc dst Conditional JP dst Unconditional Operation If cc is true PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed
60. this case is used the T1INT pending bit must be cleared by the application subroutine by writing a 0 to the T1CON 0 pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the Timer 1 reference data registers T1DATA The match signal generates a timer 1 match interrupt T1INT vector E6H and clears the counter If for example you write the value 10H to T1DATA and OEH to T1CON the counter will increment until it reaches 10H At this point the Timer 1 interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 11 1 8 BIT TIMER 1 3C831B P831B TIMER 1 CONTROL REGISTER T1CON You use the timer 1 control register T1CON to Enable the timer 1 operating interval timer Select the timer 1 input clock frequency Clear the timer 1 counter T1CNT Enable the timer 1 interrupt and clear timer 1 interrupt pending condition T1CON is located in set 1 bank 0 at address E5H and is read write addressable using register addressing mode A reset clears T1CON to 00H This sets timer 1 to disable interval timer mode and disables timer 1 interrupt You can clear the timer 1 counter at any time during normal operation by writing a 1 to T1CON 3 To enable the timer 1 interrupt IRQ1 vector E6H you must write T1CON 2 and T1CON 1 to 1 To detect an interrupt pending condition when T1INT is disabled the applicat
61. timer enable bits Divider clear bit 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear dvider Automatically cleared to 0 Basic timer counter clear bit 0 No effect 12 Clear BTCNT Automatically cleared to 0 Basic timer input clock selection bits 00 fxx 4096 01 fxx 1024 10 50 128 11 fxx 16 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS 3C831B P831B BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock A reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during normal operation the basic timer ov
62. ups as output open drain or push pull And they can serve as segment pins for LCD also Port Group 2 Control Register Port 8 has a 8 bit control register PG2CON for 8 0 8 7 A reset clears the PG2CON register to configuring all pins to input mode Port Group 2 Control Register EFH Set 1 Bank 1 R W SIO1 output control bit 0 SO1 SCK1 output is selected m iuum as push pull 1 501 SCK1 output is selected P8 0 P8 3 as open drain SEG7 SEG4 SIOO output control bit P1 0 P1 3 input enable bit 0 SOO SCKO output is selected as push pull 0 Enable port 1 0 1 3 input 1 500 SCKO output is selected 1 Disable port 1 0 1 3 input as open drain P1 4 P1 7 input enable bit 0 Enable port 1 4 1 7 input 1 Disable port 1 4 1 7 input PG2CON bit pair pin configuration settings Schmitt trigger input mode Schmitt trigger input mode pull up Output mode open drain Output mode push pull NOTE The shared I O ports with LCD segments should be slelected as one of two by LCON 3 0 Figure 9 15 Port Group 2 Control Register PG2CON ELECTRONICS 9 15 PORTS 3C831B P831B NOTES 9 16 ELECTRONICS 3C831B P831B BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 OVERVIEW The S3C831B has two default timers an 8 bit basic timer and one 8 bit general purpose timer counter The 8 bit timer counter is called timer 0 BASIC TIMER BT Vou can use the basic timer BT in tw
63. value is one bit in length Example Given R1 07H BITS R13 o R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET 3C831B P831B BOR Bit or BOR BOR Operation Flags Format Examples 6 22 dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IO ONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 Rb 6 07 Rb r0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR R1 01H 1 R1 07H register 01H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H
64. voltage reset electrical characteristics Serial I O timing characteristics Oscillation characteristics Oscillation stabilization time ELECTRONICS ELECTRICAL DATA 20 1 ELECTRICAL DATA 3C831B P831B Table 20 1 Absolute Maximum Ratings Ta 25 C Output voltage AII VO pins active 60 Bewewmewue Te SiH Table 20 2 D C Electrical Characteristics TA 25 C to 85 C Vpp 2 2V to 5 5 V Operating _ fx 0 4 4 5 MHz Voltage fx 4 5 9 MHz PLL IFC operating Voltage EOO EO1 lop 1 mA Other output ports loy 1 mA Voltage EOO EO1 lg 1 mA Other output ports lo 10 mA 20 2 ELECTRONICS V V Output current low pene AI Output current high One I O pin active TA 3C831B P831B ELECTRICAL DATA Table 20 2 D C Electrical Characteristics Continued 25 C to 85 C me ee Input High Leakage Vin Current All input pins except Xin Xour Input Low Leakage Vi 20V Current All input pins except RESET Xi Vin 0 Xin Output High llon Vout Leakage Current All output pins Output Low lot Vout OV Leakage Current All output pins Pull Up Resistor Pull Down Resistor VCOFM VCOAM AMIF 25 C Oscillator Feed Rosc 5 Ta 25 C Back Resistors Von Xour 0 V LCD Voltage Rico Ta 25 Dividing Resistor COMI Voltage Drop 1
65. 0 3 15 uA per common pin IVicp SEGX 15 uA per common Voltage Drop x 0 39 Voltage ELECTRONICS 20 3 ELECTRICAL DATA 3C831B P831B Table 20 2 D C Electrical Characteristics Concluded TA 25 C to 85 C 2 2 V to 5 5 V Supply current 1 Run mode 12 0 25 0 mA 4 5 MHz crystal oscillator CE Vpp 5 V 10 6 5 15 0 Crystal Oscillator C1 C2 22pF Vpp 23 V 10 96 4 5 MHz 40 9 0 Run mode 9 0 MHz 5 0 12 0 CE 0V Vpp 5V 410 Crystal Oscillator 4 5 MHz 2 5 5 5 C1 C2 22pF Vpp 23 V 10 45MHz 15 35 lppa mode 9 0 MHz 1 5 4 0 CE 0 V Vpp 5V 410 Crystal Oscillator 4 5 MHz 1 0 2 0 C1 C2 22pF 1 2 Vpp 2 3 V 10 96 45MHz 05 lopa 2 Stop mode in LVR disable 05 3 uA CE 0 V TA 25 C 5 V 10 96 NOTES 1 Supply current does not include current drawn through internal pull up resistors PWM or external output current loads 2 1 current when the main clock oscillation stops 3 Every values in this table is measured when bits 4 3 of the system clock control register CLKCON 4 3 is set to 11B 20 4 ELECTRONICS 3C831B P831B ELECTRICAL DATA Table 20 3 A C Electrical Characteristics 25 C to 85 C Vpp 2 2 V to 5 5 V Interrupt input high low width P1 0 P1 7 RESET input low width Figure 20 1 Input Timing for External
66. 0000 0 0 1 1 0 0 1 1 Figure 5 8 Interrupt Priority Register IPR 5 12 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Read only IRQ1 IRQ2 e IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt level request pending bits 0
67. 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S3C831B the set 2 address range is accessible on pages 0 9 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area of page 0 is commonly used for stack operations 2 6 ELECTRONICS 3C831B P831B ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes 00H BFH of the S3C831B s ten 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages O 1 2 3 4 5 6 7 8 or 9 you must set the register page pointer PP to the appropriate source and destination values Set 1 Bank 0 Bank 1 LCD Data Register Area CPU and system control Figure
68. 1B P831B ADDRESS SPACES Selects RPO or Address OPCODE MI 4 bit address Register pointer provides three provides five low order bits high order bits LE MM did Together they create an 8 bit register address Figure 2 11 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register 01110 address 044 201 444 0 NOH 76H Figure 2 12 4 Bit Working Register Addressing Example ELECTRONICS 2 15 ADDRESS SPACES 3C831B P831B 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits
69. 2 646 mapped registers in the internal register file Of these 2 576 are for general purpose This number includes a 16 byte working register common area used as a Scratch area for data operations ten 192 byte prime register areas and ten 64 byte areas Set 2 Thirteen 8 bit registers are used for the CPU and the system control and 57 registers are mapped for peripheral controls and data registers Ten register locations are not mapped ELECTRONICS 2 1 ADDRESS SPACES 3C831B P831B PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C831B has 64K bytes internal mask programmable program memory The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal 65 535 64K bytes Internal Program Memory Area Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS 3C831B P831B ADDRESS SPACES REGISTER ARCHITECTURE In the S3C831B implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and
70. 21 S3 C831B P831B 062003 USER S MANUAL 3C831B P831B 8 Bit CMOS Microcontroller Revision 1 ELECTRONICS 3C831B P831B PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes Among the major CPU features are Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode release by interrupt Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt Sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels 3C831B MICROCONTROLLER The S3C831B single chip microcontroller are fabricated using the highly advanced CMOS process Its design is based on the powerful SAM88RC CPU core Stop and idle power down modes were implemented to reduce power consumption The S3C831B is a microcontroller with a 64K byte mask programmable ROM embedded The S3P831B is a microcontroller with a 64K byte one time programmable ROM embedded Using the SAM88RC modular design approach the following peripherals were integrated with the SAM88RC CPU core Large number of programable I O ports Total 72 pins PLL frequency synthesize
71. 31B P831B Table 8 3 S3C831B Set 1 Bank 1 Register Values after RESET BELLE UE C EET II De 7 6 5 4 3 2 1 0 Port 0 Control Register High Byte POCONH 224 EOH 0 O 0 0 O O O O Port 0 Control Register Low Byte POCONL 225 E1H 0 O 0 O O O O Port 0 Pull up Resistors Enable POPUR 226 E2H Register Locations E3H is not mapped Port 1 Control Register High Byte PICONH 228 EH 0 0 0 0 O O 0 O 1 Control Register Low Byte PICONL 229 ESH 0 O 0 0 O O O O Port 1 Interrupt Control Register PUNT 280 EH O 0 O O O O Port 1 Interrupt Pending Register PIPND 231 ETH 0 O 0 0 O O 0 O Port 2 Control Register High Byte P2CONH 232 EH 0 0 0 0 O 0 O O Port 2 Control Register Low Byte 2 233 ESH 0 O 0 0 O O O O Port Control Register High Byte PSCONH 234 EAH 0 0 0 0 O 0 0 O Port Control Register Low Byte Pacon 235 0 O 0 0 O O O 0 Port 3 Pull up Resistors Enable P3PUR 236 ECH Register Port Group 0 ControRegister PGOCON 27 EDH 0 0 0 0 O 0 PortGroupiControlRegister PGICON 238 0 0 0 0 O O 0 O Port Group 2 ControRegister PG2CON 239 EFH 0 0 0 0 O O 0 O Location FFH is not mappe
72. 831B P831B CONTROL REGISTER IPR Interrupt Priority Register FFH Set 1 Bank 0 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C note Fo Grouppronty undeined Fe e t BeGosaA o o o lojes oO o ofa lilesase Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQA IRQ4 gt IRQ3 2 Interrupt Group Priority Control IRQ2 gt IRQ3 IRQA 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO NOTE Interrupt Group A IRQO IRQ1 Interrupt Group B IRQ2 IRQ3 IRQ4 Interrupt Group C IRQ5 IRQ6 IRQ7 ELECTRONICS 4 1 CONTROL REGISTERS 3C831B P831B IRQ Interrupt Request Register DCH Set 1 Bit Identifier o8 4 j 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit IF Interrupt Not pending Pending 6 Lev 16 IRQ6 Request Pending Bit CE Interrupt ot pending ending
73. 9 13 Port Group 0 Control Register PGOCON ELECTRONICS 9 13 PORTS 3C831B P831B PORT 6 7 Port 6 and 7 are 8 bit I O port with nibble configurable pins respectively Port 6 and 7 pins are accessed directly by writing or reading the port 6 and 7 data registers P6 at location F6H and P7 at location F7H in set 1 bank 1 6 0 6 7 and P7 0 P7 7 can serve as inputs with or without pull ups as output open drain or push pull And they can serve as segment pins for LCD also Port Group 1 Control Register Port 6 and 7 have 8 bit control register PG1CON 4 7 for P6 0 P6 7 and PG1CON 0 3 for 7 0 7 7 A reset clears the PG1CON register to OOH configuring all pins to input mode Port Group 1 Control Register EEH Set 1 Bank 1 R W P7 0 P7 3 SEG11 SEG8 SEG15 SEG12 P6 4 P6 7 SEG19 SEG16 P6 0 P6 3 SEG23 SEG20 PG1CON bit pair pin configuration settings Schmitt trigger input mode Schmitt trigger input mode pull up Output mode open drain Output mode push pull NOTE shared I O ports with LCD segments should be selected as one of two LCON 3 0 Figure 9 14 Port Group 1 Control Register PG1CON 9 14 ELECTRONICS 3C831B P831B PORTS PORT 8 Port 8 is an 8 bit I O port with nibble configurable pins Port 8 pins are accessed directly by writing or reading the port 8 data register P8 at location F8H in set 1 bank 1 8 0 8 7 can serve as inputs with or without pull
74. AL CONVERTER 8 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 8 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 8 bit digital values The analog input level must lie between the AVpp and Vss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type ADC control register ADCON Eight multiplexed analog data input pins ADO AD7 8 A D conversion data output register ADDATA 8 bit digital input port Alternately I O port AVpp pin is internally connected to Vpp FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must set with alternative function for ADC input enable at port 2 the pin set with alternative function can be used for ADC analog input And you write the channel selection data in the A D converter control register ADCON 4 6 to select one of the eight analog input pins ADO 7 and set the conversion start or enable bit ADCON O The read write ADCON register is located in set 1 bank 0 at address The pins which are not used for ADC can be used for normal I O During a normal conversion ADC logic initially sets the successive approximation register to 80H the approximate half way point of an 8 bit register This register is then updated automatica
75. ALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS 3C831B P831B Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP src SRPO SIC SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6 5 INSTRUCTION SET 3C831B P831B FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that de
76. Bit Identifier RESET Value Read Write Bit Addressing Mode R Read only W Write only R W Read write 3C831B P831B Name of individual bit or related bits Register location in the internal register file Register address Register name hexadecimal Set 1 Lr m puro Ae x x x x x x x gt 0 R W R W R W R W R W R W R W R W Register addressing modejoniv Carry Flag C EN Operation does not generate a carry or borrow condition Lo Operation generates carry out or borrow into high order bit 7 EE Zero Flag Z EN Operation result is a non zero value Operation result is zero Sign Flag 5 Operation generates positive number MSB 0 Operation generates negative number MSB 1 Bit number MSB Bit 7 LSB Bit 0 Description of the effect of specific bit settings Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit 4 4 RESET value notation Not used x Undetermined value 0 Logic zero 1 Logic one Figure 4 1 Register Description Format ELECTRONICS 3C831B P831B CONTROL REGISTER ADCON A D Converter Control Register EFH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R R W R W R W Addressing Mode 2 1 ELECTRONICS Register addressing mode only Not used for the S3C831B A D Input Pin Selection Bits of oze op aee
77. C831B P831B PLL FREQUENCY SYNTHESIZER PLL MODE REGISTER PLLMOD The PLL mode register PLLMOD is used to start and stop PLL operation and to enable or disable 3 bit counter for PLLMOD values also determine the frequency dividing method PLLMOD 7 selects the frequency dividing method The basic configuration for the two frequency dividing methods are as follows Direct Method Used for AM mode Swallow counter is not used Vcoam Pin is selected for input Selectable 3 bit counter PLLMOD 7 and 4 Pulse Swallow Method Used for AM FM mode Swallow counter is used Vecorm Pin is selected for input The input frequency at the Vcoam or Vcorm pin is divided by the programmable divider The frequency division value of the programmable divider is written to the PLL data register When the pulse swallow method is selected by setting PLLMOD 7 and PLLMOD 4 the input signal is first divided by a 1 32 or 1 33 prescaler and the divided frequency is input to the programmable divider Table 18 1 shows PLLMOD organization ELECTRONICS 18 5 PLL FREQUENCY SYNTHESIZER 3C831B P831B Table 18 1 PLLMOD Organization PLL Enable and INTIF INTCE Interrupt Control Bits PLLMOD 6 o Disable PLL Enable PLL PLLMOD 3 0 Disable INTIF interrupt Enable INTIF interrupt PLLMOD 2 INTIF interrupt is not pending when read Clear INTIF pending bit when write INTIF interrupt is pending when read
78. CPU but all peripherals remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to OOB If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS 3C831B P831B PORTS I O PORTS OVERVIEW The S3C831B microcontroller has four bit programmable and five nibble programmable I O ports PO P8 The port 0 8 are all 8 bit ports This gives a total of 72 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required All ports of the S3C831B can be configured to input or output mode and P4 P8 are shared with LCD segment signals Table 9 1 gives you a general overview
79. Channel Data Output Disable O Output Disable Enable PG2CON 5 Figure 1 11 Pin Circuit Type D 8 P1 4 P1 7 Figure 1 13 Pin Circuit Type E 4 PO 1 10 ELECTRONICS 3C831B P831B PRODUCT OVERVIEW Pull up Enable Disable SEG ADCEN Output Disable ADC Select ies Figure 1 14 Pin Circuit Type F 16 P2 Figure 1 16 Pin Circuit Type H 39 Figure 1 15 Pin Circuit H COMO COM3 ELECTRONICS 1 11 PRODUCT OVERVIEW 3C831B P831B VDD Pull up VDD Resistor lt Resistor pe Enable P CH Drain Data y o Output Disable1 SEG Circuit Output Type H 39 Disable2 Figure 1 17 Pin Circuit Type H 41 P6 P8 VDD Pull up VDD Resistor 6 H lt Resistor Dia Enable P CH Data Output Disable1 SEG Circuit Output Type H 39 Disable2 Figure 1 18 Pin Circuit Type H 42 P4 P5 1 12 ELECTRONICS 3C831B P831B ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C831B microcontroller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C831B has an internal 64 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes A 20 byte LCD display register file is implemented There are
80. Crystal Crystal oscillation Vpp 2 2V 5 5V frequency Vpp 4 0V 5 5V Stablilization time Stabilization occurs when Vpp is equal to the minimum oscillator voltage range Crystal oscillation Vpp 2 2V 5 5V frequency 4 0V 5 5V Stablilization time External Xin input frequency 1 2 2V 5 5V gt I N AB o o olo T T ALA j lt I N gt gt oaj 0 0 1 input high and low Vpp 2 2V 5 5V k he Clock Vpp 4 0V 5 5V 4 4 10 level width ba tq 4 0V 5 5V 55 NOTES 1 Oscillation frequency and Xy input frequency data are for oscillator characteristics only 2 Stabilization time is the interval required for oscillating stabilization after a power on occurs or when stop mode is terminated 20 10 ELECTRONICS 3C831B P831B ELECTRICAL DATA VDD 0 1V 0 1V Figure 20 6 Clock Timing Measurement at Xy Instruction Clock Main Oscillator Frequency 2 25 MHZ 1 125 MHZ 100 kHz 400 kHz 2 2V Supply Voltage V CPU Clock 1 4n x oscillator frequency n 1 2 8 16 When PLL IFC operation operating voltage range is 2 5 V to 3 5 V or 4 5 V to 5 5 V Figure 20 7 Operating Voltage Range ELECTRONICS 20 11 ELECTRICAL DATA 3C831B P831B NOTES 20 12 ELECTRONICS 3C831B P831B MECHANICAL DATA 2 1 MECHANICAL DATA OVERVIEW The
81. D COM SEG SIGNALS The 40 LCD segment signal pins are connected to corresponding display RAM locations at 00H 13H at page 7 The corresponding bits of the display RAM are synchronized with the common signal output pins COMO COM1 2 and When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin Each bias has select and no select signals 6 1Frame COM SEG Figure 14 4 Select No Select Bias Signals in Static Display Mode ELECTRONICS 14 7 LCD CONTROLLER DRIVER 3C831B P831B COM SEG COM SEG Figure 14 6 Select No Select Bias Signals in 1 3 Duty 1 3 Bias Display Mode 14 8 ELECTRONICS 3C831B P831B LCD CONTROLLER DRIVER Static and 1 3 Bias VLcD 3 V at 5 V 1 2 Bias VLCD 2 5 V at VDD 5 V Bias Pin Bias Pin Vicb 2 5 V Ves Static and 1 3 Bias Vico 5 V at VoD 5 V Voltage Dividing Resistors Adjustment Bias Pin VicD 5 VLe2 B 3R when LMOD 6 1 VLCD NOTES 1 Internal voltage dividing resistors These resistors can be disconnected LMOD 6 2 R External Resistors 3 R External Resistor to adjust VLCD Figure 14 7 Voltage Dividing Resistor Circuit Diagram ELECTRONICS 14 9 LCD CONTROLLER DRIVER 3C831B P831B NOTES 14 10 ELECTRONICS 3C831B P831B 8 BIT ANALOG TO DIGIT
82. DC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles 2 10 ELECTRONICS 3C831B P831B ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register sp
83. ET Value 0 0 0 0 0 0 0 Read Write RAW R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Not used for the S3C831B 6 Watch Timer Enable Bit Disable watch timer clear frequency dividing circuits Enable watch timer 5 4 Buzzer Signal Selection Bits When fxx 4 5 MHz 1 kHz buzzer BUZ signal output fo 1 5 kHz buzzer BUZ signal output 1 3 kHz buzzer BUZ signal output 6 kHz buzzer BUZ signal output 3 2 Watch Timer Speed Selection Bits When fxx 4 5 MHz 7 PO 1 o5smeva S Watch Timer Interrupt Enable Bit Disable watch timer interrupt Enable watch timer interrupt 0 Watch Timer Interrupt Pending Bit Interrupt is not pending when read Clear pending bit when write Interrupt is pending when read NOTE If the main clock is 9MHz IFMOD 7 should be set to 1 4 44 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM88RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals an
84. G MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Program Memory Address Used Next OPCODE Co s PC Value gt Displacement Current Instruction OPCODE Signed a Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES 3C831B P831B IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD Figure 3 14 Immediate Addressing 3 14 ELECTRONICS 3C831B P831B CONTROL RE
85. G38 ELECTRONICS OANDOARWN 9 Ld IG kd kd 0 Ld 48 WMd0L LNOOL E 0d 16 7 1n0Oc1 Z0d 06 f 10e1 9 0d 68 7 1NOL1 S0d 88 A X IOLL r Od 98 3 dVO0L 2e 0d 98 3 X 1001L L0d 08 66 ZLN 86 91N 46 3 SIN 96 FI PIN 66 A ELN v6 3 21 6 3 LIN 26 E3 OLN 42 TIdSSA 92 WVOQA e S3C831B 100 TQFP 1414 c vrd 9dS CI 9c Erd 9EOAS CI Le b vd GSEDAS 8c S vd veDas 6c 9 68995 0 1 69985 C3 16 O0 Sd I OdS CI 06 L Sd 0 OdS CI 66 e Sd 66D3S CI ve EGd 8cDAS CI GE VGd LEDAS 96 GGd 9ZDAS CI ZE 9Gd GZDAS 8 LGd peDAS 66 094 2046 OV L 9d ecOdS CI iv 94 10046 CI ev 9d 020dS v 9d eL O3S CI vv S 9d 8LOdS CI 9 994 1946 CI 9v L 9d 9103S CI 7 0 2d SLO3S CI 8v LZd vLOdS CI 6t 24 61995 CI 0S Figure 1 3 S3C831B Pin Assignments 100 TQFP 1414 PRODUCT OVERVIEW VCOFM VDDPLL1 LVREN LVRSEL BIAS VLCO VLC1 VLC2 COMO 1 2 COMS SEGO P8 7 SEG1 P8 6 SEG2 P8 5 SEG3 P8 4 SEG4 P8 3 SEG5 P8 2 SEG6 P8 1 SEG7 P8 0 SEG8 P7 7 SEG9 P7 6 SEG10 P7 5 SEG11 P7 4 SEG12 P7 3 PRODUCT OVERVIEW 3C831B P831B PIN DESCRIPTIONS Table 1 1 S3C831B Pin Descriptions Circuit Tea Desci t n Type O port with bit programmable pins Schmitt trigger input or push pull open drain output and software assignable pull ups TOOUT TOPWM T1CLK TOUT P1 0 P1 3
86. GISTER CONTROL REGISTERS OVERVIEW In this chapter detailed descriptions of the S3C831B control registers are presented in an easy to read format You can use this chapter as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual Data and counter registers are not described in detail in this reference chapter More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C831B register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 17 6 5 4 3 2 1 0 Locations DOH D2H not mapped L JEW Basiotinercontolregster 24 AW e o e o e v e system cock contol register za oe mw System fags register Faes 29 os Register pomero Reo z mw 1 1 e o o Register pointer mm zs om mw 1 1 e o 1 Finer
87. I Le b vd GEDAS CI 8c S vd veDas CI 6c 9 66995 CI 0 1 6995 Le OGd LEDAS CI ce L Sd 0 OdS 66 6 S8d 620dS ve t6 A 1NOZE1 Z70d 06 MIOEL 90d 68 L1NOLL S0d 88 3 MIOLLVOd EGd 82DAS GE 48 7 WMd0l LNOOL E0d 98 dVO0l c 0d 98 3 X 1001 L0d S3P831B 100 TQFP 1414 VGd Z2DAS 9 GGd 92DAS LE 9Gd SZDAS 8 LGd peDAS C 66 O9d EcOAS OV L 9d ecOdS C3 Lh e 9d L2903S CI ev 9d 020dS v 9d eL O3S C3 vv G9d 8LDAS 9 08 OTIdQQA 9 9d 193S CI 9p L 9d 91903S CI Lb 0 2d SLO3S CI 8v 44 E43 TIdSSA 97 WVOOA LZd vVOdS CI 6t 24 619985 CI 06 S3P831B OTP VCOFM VDDPLL1 LVREN LVRSEL BIAS VLCO VLC1 VLC2 COMO 1 2 COMS SEGO P8 7 SEG1 P8 6 SEG2 P8 5 SEG3 P8 4 SEG4 P8 3 SEG5 P8 2 SEG6 P8 1 SEG7 P8 0 SEG8 P7 7 SEG9 P7 6 SEG10 P7 5 SEG11 P7 4 SEG12 P7 3 22 3 S3P831B OTP 3C831B P831B Table 22 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming P3 2 SO0 SDAT 13 11 Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port 3 510 SCLK Serial clock pin Input only pin TEST1 Power supply pin for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option RESET RESET 2220 1 Chi
88. IEW The 16 bit timer 2 is an 16 bit general purpose timer Timer 2 has the interval timer mode by using the appropriate T2CON setting Timer 2 has the following functional components Clock frequency divider fxx divided by 256 64 8 or 1 with multiplexer External clock input T2CLK 16 bit counter T2CNTH L 16 bit comparator and 16 bit reference data register T2DATAH L Timer 2 interrupt IRQ1 vector E4H generation Timer 2 control register T2CON set 1 Bank 1 FEH read write FUNCTION DESCRIPTION Interval Timer Function The timer 2 can generate an interrupt the timer 2 match interrupt T2INT T2INT belongs to interrupt level IRQ1 and is assigned the separate vector address E4H The T2INT pending condition should be cleared by software when it has been serviced Even though T2INT is disabled the application s service routine can detect a pending condition of T2INT by the software and execute it s sub routine When this case is used the T2INT pending bit must be cleared by the application subroutine by writing a 0 to the T2CON 0 pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the Timer 2 reference data registers T2DATA The match signal generates a timer 2 match interrupt T2INT vector E4H and clears the counter If for example you write the value 0010H to TZDATAH L and OEH to T2CON the counter will increment until
89. IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 5 16 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP conta
90. Interrupts Ports 1 Figure 20 2 Input Timing for RESET ELECTRONICS 20 5 ELECTRICAL DATA 3C831B P831B Table 20 4 Input Output Capacitance TA 25 C to 85 C Vop 0V Input Cin f 1 MHz unmeasured pins capacitance are returned to Vss Output Cout capacitance I O capacitance Table 20 5 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 C Parameter Symbol Conditions supplv fe supply current Stop modal in LVR disables RESET Occurs Oscillation Y Stabilization 3 Stop Mode Time y Normal 4 Data Retention Mode gt Operating Mode Execution of STOP Instrction NOTE _ twar is the same as 4096 x 16 x 1 fxx Figure 20 3 Stop Mode Release Timing Initiated by RESET 20 6 ELECTRONICS 3C831B P831B ELECTRICAL DATA Oscillation Stabilization Time Y 3 Stop Mode 4 Idle Mode 4 Data Retention Mode Normal Execution of Operating Mode STOP Instruction Interrupt NOTE twarr is the same as 16 x 1 BT clock Figure 20 4 Stop Mode Release Timing Initiated by Interrupts Table 20 6 A D Converter Electrical Characteristics TA 25 to 85 C Vpp 2 7 V to 5 5 V Vss 0 V AD convening resouton bis A D conversion time NOTE Conversion clock fxx 50 fxx o oss NOTE A D Converter ne
91. L I O INTERFACE OVERVIEW Serial I O modules SIOO and SIO1 can interface with various types of external device that require serial data transfer The components of SIOO and SIO1 function block are 8 bit control register SIOOCON SIO1CON Clock selector logic 8 bit data buffer SIOODATA SIO1DATA 8 bit prescaler SIOOPS SIO1PS 3 bit serial clock counter Serial data I O pins 510 SOO 11 501 Serial clock input output pins SCKO SCK1 Serial data and clock output type selection PG2CON 7 6 The SIO modules can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps 1 Configure the I O pins at port SCK0 SIO SOO SCK1 SI1 SO1 by loading the appropriate value to the P3CONH and P3CONL register if necessary Configure the output type SCKO SOO SCK1 SO1 by manipulating PG2CON 7 6 if necessary Load an 8 bit value to the SIOOCON SIO1CON control registers to properly configure the serial I O modules In this operation SIOOCON 2 and SIO1CON 2 must be set to 1 to enable the data shifters respectively For interrupt generation set the serial I O interrupt enable bits SIOOCON 1 SIO1CON 1 to 1 respectively When you transmit data to the serial buffer write data to SIOODATA
92. Lcon 24 RW Jol l l Jojojojoj LCD mode register LMOD 242 RW 0 IF counter mode register IFMOD 243 RW Jol l Jojojojojoj IFcountert Fon 244 jojojo ojojo ojo countero Fono 245 Jojolojojojojojoj Location FAH is not mapped STOP control register STPCON 251 RW Jojojojojojojojoj Location FCH is not mapped Basic timer counter Brent 253 RW Jojojojojojojojoj Location FEH is not mapped Finteruptprorty register l 85 re mw x xIxIxIxIxIxD NOTE Refer to the corresponding register in this chapter 4 2 ELECTRONICS 3C831B P831B CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers nee asim we Decimal Hex zjejsjajsizjijoj Port 0 control register high byte POCONH 224 RW Jojojojojojojojoj Port 0 control register low byte POCONL 225 RW Jojojojojojojojoj Port 0 pull up resistors enable POPUR 226 E2H R W register Location E3H is not mapped Porti control register high byte PICONH 228 RW Jojojojojojojojoj Port 1 control register low byte PICONL 229 RW Jojojojojojojojoj Port 1 interrupt control register 230 RW Jojojojojojojojoj Port interrupt pending register PIPND 231 RW Jojojojojojojojoj Port 2 control register high byte P2CONH 232 RW Jojojojojojojojoj Port 2 con
93. MER 0 3C831B P831B Capture Mode In capture mode a signal edge that is detected at the TOCAP P0 2 pin opens a gate and loads the current counter value into the timer 0 data register You can select rising or falling edges to trigger this operation Timer 0 also gives you capture input source the signal edge at the TOCAP P0 2 pin You select the capture input by setting the values of the timer 0 capture input selection bits in the port O control register POCONL 5 4 set 1 bank 1 E1H When POCONL 5 4 is 00 the TOCAP input is selected Both kinds of timer 0 interrupts can be used in capture mode the timer 0 overflow interrupt is generated whenever a counter overflow occurs the timer 0 match capture interrupt is generated whenever the counter value is loaded into the timer 0 data register By reading the captured data value in TODATA and assuming a specific value for the timer 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the TOCAP pin see Figure 10 7 TOCON O TOOVF IRQO 8 Bit Up Counter INTPND O Overflow INT Interrupt Enable Disable TOCON 1 TOINT IRQO TOCAP input INTPND 1 Capture INT PO 2 Match Signal Pending TOCON 4 3 TOCON 4 3 Timer 0 Data Register Figure 10 7 Simplified Timer 0 Function Diagram Capture Mode 10 10 ELECTRONICS 3C831B P831B BASIC TIMER and TIMER 0 TOCON O OVF INTPND O IRQO Data BUS fxx 1024 gt
94. Mode 10 8 ELECTRONICS 3C831B P831B BASIC TIMER and TIMER 0 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TOPWM PO 3 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although you can use the match signal to generate a timer 0 overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TOPWM P0 3 pin is held to Low level as long as the reference data value is less than or equal to the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to x 256 see Figure 10 6 TOCON O Capture Signal Interrupt Enable Disable TOOVF IRQO TOCON 1 8 Bit Up Counter INTPND O Overflow INT TOINT IRQO INTPND 1 8 Bit Comparator INTPND 1 Match INT Pending TOPWM LI Output PO 3 Timer 0 Buffer Register TOCON 4 3 High level when Match Signal data gt counter TOCON 2 Timer 0 Data Register Lower level when data lt counter Figure 10 6 Simplified Timer 0 Function Diagram PWM Mode ELECTRONICS 10 9 BASIC TIMER and TI
95. NOTES 1 500Hz 250Hz 125Hz and 62 5Hz 2 The LCD display registers in the page 9 Figure 14 2 LCD Circuit Diagram 14 2 ELECTRONICS 3C831B P831B LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses 00H 13H of page 9 are used as LCD data memory When the bit value of a display segment is 1 the LCD display is turned on when the bit value is the display is turned off Display RAM data are sent out through segment pins SEGO SEG39 using a direct memory access DMA method that is synchronized with the f signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use III Soci 7 bit 6 bit 5 bit 4 903H 902H 901H 900H bit 3 bit 2 bit 1 bit 0 COM2 1 Figure 14 3 LCD Display Data RAM Organization ELECTRONICS 14 3 LCD CONTROLLER DRIVER 3C831B P831B LCD CONTROL REGISTER LCON F1H at BANK 0 of SET 1 Table 14 1 LCD Control Register LCON Organization If LMOD 3 1 a es sh COM and SEG signals in display mode LCON 6 4 Not used for the S3C831B l used for the S3C831B LCON 3 0 0000 Select LCD SEGO 39 0001 Select LCD SEGO 35 P4 0 4 3 as I O port LCON 7 0 LCD output is low and the current for dividing the resistors is cut off If LMOD 3 0 LCD display is turned off All LCD segments are off signal output 14 4 ELECTRONICS 3C831B P831B LCD CONTROLLER DRIVE
96. O 3 P4 P5 P6 P7 P8 0 8 3 as I O port 0 All O port P4 P8 ELECTRONICS 4 15 CONTROL REGISTERS S3C831B P831B LMOD LCD Mode Control Register F2H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only COM Signal Enable Disable Bit Enable COM signal Disable COM signal LCD Voltage Dividing Resistor Control Bit Internal voltage dividing resistors External voltage dividing resistors internal voltage dividing resistors are off LCD Clock LCDCK Frequency Selection Bits When fxx 4 5MHz 0 5 ___ o r o monrawcasw NOTE Ifthe main clock is 9MHz IFMOD 7 should be set to 1 Duty and Bias Selection for LCD Display 0 x x x LOD display off COM and SEG output ow 1 o o fo 14duy 13bas S 1 18 duy 13bas 0 0 pt fol ttt 18duy 1v2bas o 1 10 1170 12d 12bas S fi pijojojstaio 2 ELECTRONICS 3C831B P831B CONTROL REGISTER POCONH Port 0 Control Register High Byte EOH Set 1 Bank 1 Bit Identifier 8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 7 2 o o Jinputmode o 0 1 Output mode open drain o 1 0 Alternative function T2OUT Output mode push pull 5 4 6 2 a Fo
97. ON System Clock Control Register D4H Set 1 Bit Identifier o 0 0 RESET Value 0 Read Write R W R W R W Addressing Mode Register addressing mode only 7 Oscillator IRQ Wake up Function Bit Enable IRQ for main wake up in power down mode Disable IRQ for main wake up in power down mode 6 5 Not used for the S3C831B 4 3 CPU Clock System Clock Selection Bits note LOO mte o LO tede ooo 2 0 Not used for the S3C831B NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS 3C831B P831B FLAGS System Flags Register D5H Set 1 RESET Value X X X X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only N arry Flag Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Operation result is a non zero value 1 Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Q 5 1 Operation generates a negative number MSB 1 4 Overflow Flag V Operation result is lt 127 or gt 128 1 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D Add operation completed 1 Subtraction operation completed 2 Hal
98. PCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET 3C831B P831B CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes me mone aon at 0000 Always false 1000 Always true 0111 note Carry 1111 note No carry 0110 note Zero 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 1110 note Not equal note Il note OO l o N 1 Il ll O O a a O O a S S V V Z N 1 Il 1001 Greater than or equal 0001 1010 0010 1111 note 0111 note 1011 0011 NOTES Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal OR V 0 OR V 1 R S XOR V R S XOR V NN GD OO X OO Il Oo 1 ltindicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruc
99. PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS 3C831B P831B INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD dst src Operation IR IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst SIC 3 8 82 IR R Example Given Register OOH 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 200H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET 3C831B P831B PUSHUI Push user stack Incrementing PUSHUI Operation Flags Format
100. R LCD MODE REGISTER LMOD The LCD mode control register LMOD is mapped to RAM address F2H at bank 0 of set 1 LMOD controls these LCD functions Duty and bias selection LMOD 3 LMOD 0 LCDCK clock frequency selection LMOD 5 LMOD 4 LCD voltage dividing resistors selection LMOD 6 LCD common signal enable or disable selection LMOD 7 The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output This is also referred to as the frame frequency Since LCDCK is generated by dividing the watch timer clock fw the watch timer must be enabled when the LCD display is turned on RESET clears the LMOD register values to logic zero This produces the following LCD control settings Display is turned off LCDCK frequency is 62 5 Hz at fx 4 5 MHz from the watch timer clock The LCD display can continue to operate during idle mode Table 14 2 LCD Clock Signal LCDCK Frame Frequency LCDCK Frequency Static 1 2 Duty 1 3 Duty 1 4 Duty 62 5 Hz 62 5 Hz 31 3 Hz 20 8 Hz 15 6 Hz 125 Hz 125 Hz 62 5 Hz 41 7 Hz 31 3 Hz 250 Hz 250 Hz 125 Hz 83 3 Hz 62 5 Hz 500 Hz 500 Hz 250 Hz 166 7 Hz 125 Hz NOTE fx 4 5 MHz ELECTRONICS 14 5 LCD CONTROLLER DRIVER 3C831B P831B Table 14 3 LCD Mode Control Register LMOD Organization F2H at Bank 0 of Set 1 LMOD 7 COM Signal Enable Disable Bit 0 Enable COM signal Disable COM signal LMOD 6 LCD Voltage Dividing Resistors C
101. R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result in the destination register RO ELECTRONICS 6 87 INSTRUCTION SET 3C831B P831B NOTES 6 88 ELECTRONICS 3C831B P831B CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C831B by an external crystal can range from 0 4 MHz to 9 0 MHz The maximum CPU clock frequency is 9 0 MHz The Xy and Xgur pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON STOP control register STPCON CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx main clock fxt sub clock the fxt is not implemented in the S3C831B fxx selected system clock Figure 7 1 Main Oscillator Circuit Figure 7 2 Main Oscillator Circuit Crystal or Ceramic Oscillator External Oscillator ELECTRONICS 7 1 CLOCK CIRCUIT 3C831B P831B CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop
102. RQ1 IRQ2 P1 1 external interrupt S W P1 2 external interrupt S W P1 3 external interrupt S W P1 4 external interrupt S W P1 5 external interrupt S W P1 6 external interrupt S W P1 7 external interrupt S W IRQG CE interrupt S W IRQ7 IF interrupt S W NOTES 1 Within a given interrupt level the low vector address has high priority For example EOH has higher priority than E2H within the level IRQO The priorities within each level are set at the factory External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3C831B Interrupt Structure ELECTRONICS 5 3 INTERRUPT STRUCTURE 3C831B P831B INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C831B interrupt structure are stored in the vector address area of the first 256 bytes of the program memory ROM You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 65 535 64K byte Program Memory Area 100H t RESET FFH Address Interrupt Vector Address Area Figure 5 3 ROM Vector Address Area 5 4 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE Table 5 1 Interrupt Vectors Vector Address Interrupt Source Reque
103. Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer 0 overflow TOCON Timer 0 match capture TOCNT TODATA INTPND Timer 1 match T1CON TICNT T1DATA Timer 2 match T2CON T2CNTH T2CNTL T2DATAH T2DATAL SIOO interrupt SIOOCON SIO1 interrupt SIOODATA SIOOPS SIO1CON SIO1DATA SIO1PS E2H bank 0 EOH bank 0 E1H bank 0 E6H bank 0 E5H bank 0 E3H bank 0 E4H bankO FEH bank 1 FAH FBH bank 1 FCH FDH bank 1 E9H bank 0 EAH bank 0 EBH bank 0 ECH bank 0 EDH bank 0 EEH bank 0 IRQS WTCON bank 0 P1 3 external interrupt P1CONL P1 2 external interrupt P1INT P1 1 external interrupt P1PND P1 0 external interrupt P1 7 external interrupt P1CONH P1 6 external interrupt 1 5 external interrupt P1PND P1 4 external interrupt CE interrupt PLLMOD PLLREF PLLD1 PLLDO IF interrupt IRQ7 IFMOD IFCNT1 IFCNTO PLLMOD PLLREF 5 8 E5H bank 1 E6H bank 1 E7H bank 1 E4H bank 1 E6H bank 1 E7H bank 1 F8H bank 0 F9H bank 0 F6H F7H bank 0 F3H bank 0 F4H F5H bank 0 F8H bank 0 F9H bank 0 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 and SYM 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2
104. SING MODE Continued Register File REGISTER Example Instruction References OPCODE Points to Program 7 Peaster Pel 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS 3C831B P831B ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File Meee ee ae RPO or RP1 RPO or RP1 eee Selected RP points Program Memory to start fo i working register ee block dst i Working Register gt E Point to the ADDRESS Address Working Register tef ooo E MENTI Value used in OPERAND Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES 3C831B P831B INDIRECT REGISTER ADDRESSING MODE Concluded Register File 2 1 Selected RP points to start of working register Pew Program Memory 4 bit Working Register Address Register Next 2 bit Point Pair lil References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LDC R5 RR6 Program memory access LDE R3
105. TA EAH bank 0 SIOOCON 6 LSB MSB First Mode Select Figure 16 5 SIO0 Functional Block Diagram 3 Bit Counter SIO1CON 0 Clear Pending SIO1CON 1 SIO1CON 3 Interrupt Enable SIO1CON 7 SIO1CON 4 SIO1CON 2 Edge Select Shift Enable SIO1CON 5 5 Mode Select SIO1PS EEM bank CLK g Bit SIO1 Shift Buffer o ck SIO1DATA EDH bank 0 SIO1CON 6 LSB MSB First Mode Select Figure 16 6 SIO1 Functional Block Diagram ELECTRONICS 16 5 SERIAL I O INTERFACE 3C831B P831B SERIAL I O TIMING DIAGRAM 5100 SIO1 SCKO SCK1 510 511 Transmit IRQ2 N Complete I Set SIOOCON 3 or SIO1CON 3 Figure 16 7 Serial I O Timing in Transmit Receive Mode Tx at falling SIOOCON 4 or SIO1CON 4 0 SCKO SCK1 510 511 SO0 SO1 Transmit Complete T Set SIOOCON 3 or SIO1CON 3 Figure 16 8 Serial I O Timing in Transmit Receive Mode Tx at rising SIOOCON 4 or SIO1CON 4 1 16 6 ELECTRONICS 3C831B P831B LOW VOLTAGE RESET LOW VOLTAGE RESET OVERVIEW The low voltage reset block is useful for an system reset under the specific voltage of system The components of LVR block are LVRSEL pin Reference voltage generator Voltage divider Comparator Glitch filter LVREN PIN A LVREN pin is used to enable or disable LVR function The LVR function is disabled when the LVREN pin is connected to Vas and is enabled when the LVREN pin is conne
106. TO DIGITAL CONVERTER 3C831B P831B Conversion Data Register ADDATA FOH Set 1 Bank 0 Read Only Figure 15 2 A D Converter Data Register ADDATA INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range Vss to AVpp The AVpp pin is internally connected with Vpp Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AVpp BLOCK DIAGRAM ADCON 2 1 ADCON 4 6 l ADCON O Select one input pin of the assigned pins Clock To ADCON 3 Selector EOC Flag AD C Enable Analog S l Input Pins Comparator uccessive ADO AD7 Approximation P2 0 P2 7 Logic amp Register N ADCON O AD C Enable Upper 8 bit is loaded to A D Conversion Data Register P2CONH L Assign Pins to ADC Input 8 bit D A Result ADDATA FOH Converter Set 1 Bank 0 Figure 15 3 A D Converter Functional Block Diagram 15 4 ELECTRONICS 3C831B P831B 8 BIT ANALOG TO DIGITAL CONVERTER Reference Voltage Input It is the same voltage 10 HF with VDD only Analog ADO AD7 Input Pin S3C831B Figure 15 4 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 15 5 3C831B P831B SERIAL INTERFACE SERIA
107. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 0to F opc dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W W 1000H PC 1000H JP 00 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement 00 replaces the contents of the PC with the contents of the register pair OOH and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET 3C831B P831B JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc is true PC PC dst If the condition specified by the condition code cc is true the relative
108. V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 72 6 73 r Ir opc SIC dst 3 6 74 R R 6 75 R IR opc dst SIC 3 6 76 R IM Examples Given RO 0C7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H TM RO R1 gt RO 0C7H R1 02H Z 0 TM RO R1 gt RO 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H gt Register OOH 2BH register 01H 02H Z 0 00H 01H Register 00H 2BH register 01H 02H register 02H 23H Z 0 00H 54H gt Register 00H 2BH Z 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET 3C831B P831B WEI wait for Interrupt WFI Operation Flags Format Example 6 86 The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 The following sample program structure shows the
109. VERVIEW 3C831B P831B Table 1 1 S3C831B Pin Descriptions Continued Pin Pin Circuit Type Description Type FMIF AMIF FM AM intermediate frequency signal inputs B 81 80 79 78 ADO AD7 ADC input pins F 16 2 9 P2 0 P2 7 100 7 JO P3 4 sound at 4 5 MHz clock 510 vo merrowkopu ea su Pos 10 Jimer amkmut ea sme Poe INTO INT3 External interrupt input pins D 7 94 97 P1 0 P1 3 92 95 INT4 INT7 External interrupt input pins 98 1 P1 4 P1 7 96 99 NOTE The parentheses indicate pin number for 100 TQFP 1414 package 3 21 4 22 91 89 1 8 ELECTRONICS 3C831B P831B PRODUCT OVERVIEW PIN CIRCUITS P Channel Feedback Enable N Channel Pull down Enable Figure 1 4 Pin Circuit Type A Figure 1 7 Pin Circuit Type B 4 Up P Channel Out In gt o gt Down I N Channel Figure 1 5 Pin Circuit Type A 2 EO Figure 1 8 Pin Circuit Type B 5 CE Pull up Resistor Data P Channel Out Output N Channel Disable Schmitt Trigger Figure 1 6 Pin Circuit Type B RESET Figure 1 9 Pin Circuit Type C ELECTRONICS 1 9 PRODUCT OVERVIEW 3C831B P831B Open drain Enable Pull up Enable gt P Channel Data Output Disable Port Output Enable Disable PG2CON 4 Schmitt Trigger Figure 1 10 Pin Circuit Type D 7 P1 0 P1 3 Figure 1 12 Pin Circuit Type E 2 P3 Open drain Enable O Pull up Enable P
110. Voltage Selection Bit IFMODA Operation Voltage Selection for PLL IFC Select the PLL IFC operation voltage as 4 5V to 5 5V Select the PLL IFC operation voltage as 2 5V to 3 5V 19 2 ELECTRONICS 3C831B P831B INTERMEDIATE FREQUENCY COUNTER Table 19 1 IFMOD Organization Continued Pin Selection Bits Effect of Control BffetofControdlSeting ETIN is disabled FMIF AMIF are pulled down and FMIF AMIF s feed back resistor are off Enable IFC operation AMIF pin is selected FMIF is pulled down and FMIF s feed back resistor is off 1 Enable IFC operation FMIF is selected AMIF is pulled down and AMIF s feed back resistor is off Enable IFC operation Both AMIF and FMIF are selected Gate Time Select Bits IFMODO Select Gate Time 0 Gate time is 2 ms 1 Gate time is 8 ms o1 0 ate time is 16 ms IFC GATE FLAG REGISTER PLLREF 5 PLLREF 7 4 ULFG CEFG IFCFG POFG F9H at bank 0 of set 1 When IFC operation is started by setting IFMOD the IFC gate flag IFCFG is cleared to 0 After a specified gate time has elapsed the IFCFG bit is automatically set to 1 This lets you check whether a IFC counting operation has been completed or not The IFC interrupt can also be used to check whether or not a IFC counting operation is complete ELECTRONICS 19 3 INTERMEDIATE FREQUENCY COUNTER 3C831B P831B GATE TIMES When you write a value to IFMOD the IFC gate is opened for a 1 millisecond 4
111. ace In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 8 16 Bit Register Pair ELECTRONICS 2 11 ADDRESS SPACES 3C831B P831B Special Purpose Registers General Purpose Register l 7 tH Bank 1 Bank 0 Control Registers System Registers CFH Each register pointer RP can independently point Register Pointers to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE In the S3C831B microcontroller pages 0 9 are implemented Pages 0 9 contain all of the addressable registers in the internal register file Register Addressing Only All Indirect Register All Addressing Indexed Addressing Modes Addressing Modes Modes be Pointed by Register Pointer Can be Pointed by register Pointer Figure 2 9 R
112. address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL X 1FF7H JR C LABEL_X PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS 3C831B P831B INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 rC r r8 r dst 2 4 9 R r OtoF 2 4 C7 r D7 Ir E5 R dst src 3 6 E6 R D6 IR opc SIC dst 3 6 F5 IR 3 6 87 r opc 3 6 9 ELECTRONICS sre IM R x r 6 49 3C831B P831B INSTRUCTION SET LD Load LD Con
113. al To Internal Frequency Counter Figure 19 5 AMIF and FMIF Pin Configuration 19 8 ELECTRONICS 3C831B P831B INTERMEDIATE FREQUENCY COUNTER IFC DATA CALCULATION Selecting the FMIF pin for IFC Input First divide the signal at the FMIF pin by 2 and then apply this value to the IF counter This means that the IF counter value is equal to one half of the input signal frequency input frequency femm 10 7 MHz Gate time Tg 8 ms IFC counter value N 10 7 x 106 2 x 8 x 10 42800 A730H en e 3Io oI4 e I 14 9 T5 19 IFCNT IFCNT1 IFCNTO Selecting the AMIF Pin for IFC Input The signal at AMIF pin is directly input to the IF counter input frequency famir 450 kHz Gate time Tg 8 ms IFC counter value N fau X 450 x 103 x 8 x 10 3 3600 E10H Bn jojojojojiji jijojojojolijojojojo bee 11 0 IFCNT IFCNT1 IFCNTO ELECTRONICS 19 9 INTERMEDIATE FREQUENCY COUNTER 3C831B P831B NOTES 19 10 ELECTRONICS 3C831B P831B ELECTRICAL DATA OVERVIEW In this chapter S3C831B electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings D C electrical characteristics A C electrical characteristics Input output capacitance Data retention supply voltage in stop mode A D converter electrical characteristics PLL electrical characteristics Low
114. ate Time It gt Set IFMOD 1 IFMOD 0 1 Set non open gate time 2 8 16 ms by bit IFMOD 1 and IFMOD O Disable IFC operation by clearing bits IFMOD 3 and IFMOD 2 to 0 This method lets the gate remain open and stops the counting operation Gate Time 4 DY A _H Set IFMOD 1 IFMOD 0 1 Set IFMOD 3 IFMOD 2 0 IFC counting operation is stopped ELECTRONICS 19 5 INTERMEDIATE FREQUENCY COUNTER 3C831B P831B Gate Time Errors A gate time error occurs whenever the gate signals are not synchronized to the interval instruction clock That is the IFC does not start counter operation until a rising edge of the gate signal is detected even though the counter start instruction setting bits IFMOD 3 and IFMOD 2 has been executed Therefore there is a maximum 1 ms timing error see Figure 19 4 After you have executed the IFC start instruction you can check the gate state at any time Please note however that the IFC does not actually start its counting operation until stabilization time for the gate control signal has elapsed Instruction Execution IFMOD Setting LE 1ms gt T Ld Ld Le Actual Gate Signal 1 ms 2 2 22222222 U U U U U Resulting Gate Signal Gate Time Errors Actual Counting Period Figure 19 4 Gate Timing 1 ms Error Counting Errors The IF counter counts the rising edges of the input signal in order to determine the fr
115. ave the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine me qum Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS 5 15 INTERRUPT STRUCTURE 3C831B P831B GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 0 contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location o g P Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register
116. byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS 3C831B P831B INSTRUCTION SET CCF Complement Carry Flag CCF Operation C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET 3C831B P831B CLR Clear CLR dst Operation dst 0 Flags Format Examples 6 28 The destination location is cleared to O No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register OOH 4FH register 01H 02H and register 02H 5EH CLR OOH gt Register OOH OOH CLR 01H gt Register 01H 02H register 02H OOH In Register R addressing mode the stat
117. cally exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Flags IOZONO Format Bytes Cycles Opcode Addr Mode Hex dst src opc sbio sc 3 6 27 0 opc dst 3 6 27 Rb T NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 0000001 1B BXOR HR1 01H 1 gt R1 06H register 01H 03H BXOR 01H 2 R1 gt Register01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET 3C831B P831B CALL Call Procedure CALL Operation Flags Format Examples 6 26 dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt dst The current contents
118. ce A E MON NOE DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 12 R2 R1 IR2 R1 R1 IM ro Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 12 R2 R1 IR2 R1 R1 IM r2 b RA 4 DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 12 R2 R1 IR2 R1 R1 IM ro Rb 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 12 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x rl A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 112 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 112 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA r2 lrr1 IM IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 lrr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs ELECTRONICS 3C831B P831B INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued O
119. cles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r OtoF Example Given R1 02H and LOOP is the label of a relative address SRP 0 DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET 3C831B P831B El Enable Interrupts Operation Flags Format Example 6 40 SYM 0 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 OF Given SYM OOH EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM O is the enable bit for global interrupt process
120. cted to Vpp LVRSEL PIN A LVRSEL pin is used to select the criterion voltage of Low Voltage reset The criterion voltage is typical 3 7V for LVR when the pin is connected to 5 and is typical 2 4V for LVR when the pin is connected to Vpp BLOCK DIAGRAM Reference Voltage Generator Comparator Glitch Filter Voltage Figure 17 1 Low Voltage Reset Block Diagram ELECTRONICS 17 1 LOW VOLTAGE RESET 3C831B P831B NOTES 17 2 ELECTRONICS 3C831B P831B PLL FREQUENCY SYNTHESIZER PLL FREQUENCY SYNTHESIZER OVERVIEW The phase locked loop PLL frequency synthesizer locks medium frequency MF high frequency HF and very high frequency VHF signals to a fixed frequency using a phase difference comparison system As shown in Figure 18 1 the PLL frequency synthesizer consists of an input selection circuit programmable divider phase detector reference frequency generator and a charge pump PLLMOD PLLD 16 bit Swallow Counter Selector ee Phase eur Comparator PLLMOD 7 and 4 Reference Frequency Generator Unlock Detector PLLREF Figure 18 1 Block Diagram of the PLL Frequency Synthesizer ELECTRONICS 18 1 PLL FREQUENCY SYNTHESIZER 3C831B P831B PLL FREQUENCY SYNTHESIZER FUNCTION The PLL frequency synthesizer divides the signal frequency at the Vcoam or Vcorm pin using the programmable divider It then outputs the phase difference between the divided frequency and reference frequency at
121. cy by writing the appropriate values to the PLLREF register The frequency division value is fVcoaM 8x fp VcoaM When PLLMOD 7 and PLLMOD 4 00 N When PLLMOD 7 and PLLMOD 4 01 R where fVcoam is the input frequency at the Vcoam and fp is the reference frequency Example When PLLMOD 7 and PLLMOD 4 00 The following data are used to receive an AM band broadcasting station Receive frequency 1422 kHz Reference frequency 9 kHz Intermediate frequency 450 kHz The frequency division value N is calculated as follows fV 3 _ L COM _ 1422 450 x10 _ 208 fn i 9x108 ODOH hexadecimal decimal You would modify the PLL data register and PLLMOD 7 4 register as follows PLMOD 7 4 NOTE In the direct method the contents of PLLDO 3 PLLDO O and NF are not evaluated ELECTRONICS 18 9 PLL FREQUENCY SYNTHESIZER 3C831B P831B Pulse Swallow Method 1 Select the pulse swallow method by writing a 1 to PLLMOD 7 and PLLMOD 4 2 The VCOFM pin is configured for input when you select the pulse swallow method 3 Select the reference frequency by writing the appropriate value to the PLLREF register 4 Calculate the frequency division value as follows fVcorm 32N 45 2 When PLLMOD 7 and PLLMOD 4 11 R fVcoam 32N a TG When PLLMOD 7 and PLLMOD 4 10 R where fVcorm is the input frequency at the Vcorm and fp is the reference frequency is the quoti
122. d 8 4 ELECTRONICS 3C831B P831B RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 uA All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by external interrupts for more details see Figure 7 3 NOTE Do not use stop mode if you are using an external clock source because Xj input must be restricted internally to Vss to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock fxx 16 because CLKCON 3 and CLKCON 4 are cleared to 00 After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depe
123. d I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQO0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C831B interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C831B uses seventeen vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the
124. d shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a pr
125. d the timer 0 match capture interrupt TOINT TOOVF is belongs to interrupt level IRQO vector E2H TOINT also belongs to interrupt level IRQO but is assigned the separate vector address EOH A timer O overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND O interrupt pending bit However the timer 0 match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a to the INTPND 1 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register TODATA The match signal generates a timer 0 match interrupt TOINT vector EOH and clears the counter If for example you write the value 10H to TODATA the counter will increment until it reaches 10H At this point the timer 0 interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer 0 output pin is inverted see Figure 10 5 Interrupt Enable Disable TOCON 1 8 Bit Up Counter L nt TOINT IRQO 8 Bit Comparator Match INT Capture Signal TOOUT P0 3 Timer 0 Buffer Register TOCON 4 3 Timer 0 Data Register Figure 10 5 Simplified Timer 0 Function Diagram Interval Timer
126. ddition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 06 0 SBC 1 7 F 0 0 9 AO 60 1 1 6 1 6 9A 66 1 Flags C Set if there was a carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET 3C831B P831B DA Decimal Adjust DA Example 6 34 Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 RO C e H lt 0 Bits 4 7 3 bits 0 3 C R1 s 3CH DA R1 l R1 s 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination
127. ddress other pages Figure 2 3 Register Page Pointer PP PROGRAMMING Using the Page Pointer for RAM clear Page 0 Page 1 LD PP 00H Destination lt 0 Source 0 SRP OCOH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO RO 00H LD PP 10H Destination lt 1 Source lt 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR BRO DJNZ RO RAMCL1 CLR RO RO 00H NOTE You should refer to page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program ELECTRONICS 2 5 ADDRESS SPACES 3C831B P831B REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 EOH FFH contains 57 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The
128. ddressing only T 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C831B RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only T 3 Register Pointer 1 Address Value Register pointer 1 can independentiv point to one of the 256 bvte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 bvte working register slice C8H CFH 2 0 Not used for the S3C831B ELECTRONICS 4 35 CONTROL REGISTERS 3C831B P831B SIOOCON sio Control Register E9H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO 0 Shift Clock Selection Bit Internal clock P S clock 1 External clock SCKO 6 Data Direction Control Bit MSB first mode LSB first mode le 5 SIO 0 Mode Selection Bit eceive only mode 1 ransmit r
129. de Schmitt trigger input mode pull up o 1 Open drain output mode Push pull output mode P8 4 P8 7 SEG3 0 Mode Selection Bits Schmitt trigger input mode Schmitt trigger input mode pull up EN ERE Open drain output mode Push pull output mode CONTROL REGISTERS 3C831B P831B PLLMOD PLL Mode Register F8H Set 1 Bank 0 RESET Value note note note note 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 4 PLL Frequency Division Method Selection Bits 0 0 Direct method for VCOAM input 0 5 to 30MHz 0 1 Enable 3 bit counter for VCOAM input 0 5 to 30MHz 1 0 Pulse swallow method for VCOAM input 0 5 to 30MHz Pulse swallow method for VCOFM input 30 to 150MHz 6 PLL Enable Disable Bit 0 Disable PLL PLL Enable 5 Bit Value to be Loaded into PLLDO Register NF bit is loaded into the LSB of swallow counter 3 INTIF Interrupt Enable Bit 0 Disable INTIF interrupt Enable INTIF interrupt 2 INTIF Interrupt Pending Bit O Interrupt is not pending when read 0 Clear pending bit when write 1 Interrupt is pending when read Interrupt Enable Bit 0 Disable INTCE interrupt requests at the CE pin Enable INTCE interrupt requests at the CE pin 0 INTCE Interrupt Pending Bit O Interrupt is not pending when read Clear pending bit when write Interrupt is pending when r
130. dressing mode only 7 6 P6 0 P6 3 SEG23 20 Mode Selection Bits Schmitt trigger input mode Lo 4 Schmitt trigger input mode pull up 1 Open drain output mode Push pull output mode 5 4 P6 4 P6 7 SEG19 16 Mode Selection Bits Schmitt trigger input mode Lo 4 Schmitt trigger input mode pull up 1 Open drain output mode Push pull output mode 3 2 P7 0 P7 3 SEG15 12 Mode Selection Bits Fo o smmmwgermumoe Fo Sermin tigger nout mode pur 71129 open drain outputmode 1 0 P7 4 P7 7 SEG11 8 Mode Selection Bits Schmitt trigger input mode Schmitt trigger input mode pull up Open drain output mode Push pull output mode 4 30 ELECTRONICS S3C831B P831B CONTROL REGISTER PG2CON Port Group 2 Control Register EFH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode ELECTRONICS Register addressing mode only SI 1 Output Control Bit SO1 SCK1 output is selected as push pull 1 501 SCK1 output is selected as open drain 5100 Output Control Bit 500 SCKO output is selected as push pull 500 SCKO output is selected as open drain P1 4 P1 7 Input Enable Bits Port 1 4 1 7 input enable Port 1 4 1 7 input disable 1 P1 0 P1 3 Input Enable Bits Port 1 0 1 3 input enable Port 1 0 1 3 input disable 1 P8 0 P8 3 SEG7 4 Mode Selection Bits Schmitt trigger input mo
131. e System Registers Register Addressing Mode Working Registers Working Register Addressing Only 9 Prime Data Registers T All Addressing Modes LCD Display Register Los S3C831B P831B Page 0 Set 2 Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes Figure 2 2 Internal Register File Organization 2 4 ELECTRONICS 3C831B P831B ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3C831B microcontroller a paged register file expansion is implemented for LCD data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W Destination register page selection bits Source register page selection bits 0000 Destination Page 0 0000 Source Page 0 NOTE hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to a
132. e Hex dst src 2 4 62 ror 6 63 r Ir opc SIC dst 3 6 64 R R 6 65 R IR opc dst SIC 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register OOH 2BH register 01H 02H and register 02H 23H TCM RO R1 TCM RO R1 TCM 00H 01H TCM 00H 01H RO 0C7H R1 02H 2 1 RO 0C7H R1 02H register 02H 23H Z 0 Register OOH 2BH register 01H 02H 2 1 Register 00H 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register 00H 2BH Z 0 E gt EN In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS 3C831B P831B INSTRUCTION SET TM Test Under Mask TM dst src Operation dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise
133. e destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 52 6 53 r Ir opc SIC dst 3 6 54 R R 55 R IR opc dst SIC 3 6 56 R IM Given R1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H 03H AND 01H 02H gt Register 01H register 02H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS 3C831B P831B INSTRUCTION SET BAND Bit AND BAND dst src b BAND dst b src Operation dst O lt dst 0 AND src b or dst b lt dst b AND 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specif
134. e WTCON O interrupt pending bit After the watch timer starts and elapses a time the watch timer interrupt pending bit WTCON 0 is automatically set to 1 and interrupt requests commence in 50 ms 0 5 and 1 second intervals by setting Watch timer speed selection bits WTCON 3 2 The watch timer can generate a steady 1 kHz 1 5 kHz 3 kHz or 6 kHz signal to BUZ output pin for Buzzer By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 50 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller f Therefore if the watch timer is disabled the LCD controller does not operate Watch timer has the following functional components Real Time and Watch Time Measurement Using a Main System Clock Source only Clock Source Generation for LCD Controller f O pin for Buzzer Output Frequency Generator P3 0 BUZ Timing Tests in High Speed Mode Watch timer overflow interrupt IRQ3 vector F2H generation Watch timer control register WTCON set 1 bank 0 E8H read write ELECTRONICS 13 1 WATCH TIMER 3C831B P831B WATCH TIMER CONTROL REGISTER WTCON The watch timer control register WTCON is used to select the watch timer interrupt time and Buzzer signal to enable or disable the watch timer function It is located in set 1 bank 0 at
135. e are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 32 EL 6 33 r Ir opc SIC dst 3 6 34 R R 6 35 R IR opc dst SIC 3 6 36 R IM Examples Given R1 10H R2 1 register 01H 20H register 02H and register 03H OAH SBC R1 R2 SBC R1 R2 R1 OCH R2 03H R1 05H R2 register OAH SBC 01H 02H Register 01H 1CH register 02H SBC 01H 02H Register 01H 15H register 02H register OAH SBC O1H 8AH Register 01H 95H C S and V 1 gt gt gt gt In the first example if working register R1 contains the value 10H and register R2 the value 03H
136. e common area in set 1 COH CFH Slice 32 Slice 31 11111XXX Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 5 8 Byte Working Register Areas Slices 2 8 ELECTRONICS 3C831B P831B ADDRESS SPACES USING THE REGISTER POINTS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous ar
137. e end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex Opc 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS 3C831B P831B INSTRUCTION SET RL Rotate Left RL dst Operation C dst 7 dst 0 lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 4 91 IR Examples Giv
138. e timer 0 input clock frequency Clear the timer 0 counter TOCNT Enable the timer 0 overflow interrupt or timer 0 match capture interrupt Clear timer 0 match capture interrupt pending condition ELECTRONICS 10 5 BASIC TIMER and TIMER 0 3C831B P831B TOCON is located in set 1 bank 0 at address E2H and is read write addressable using Register addressing mode A reset clears TOCON to OOH This sets timer 0 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 0 interrupts You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 2 The timer 0 overflow interrupt TOOVF is interrupt level IRQO and has the vector address E2H When a timer 0 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer 0 match capture interrupt IRQO vector EOH you must write TOCON 1 to 1 To detect a match capture interrupt pending condition the application program polls INTPND 1 When a 1 is detected a timer 0 match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a to the timer 0 match capture interrupt pending bit INTPND 1 Timer 0 Control Register E2H Set 1 Bank 0 R W Timer 0 input clock selection bits 000 024 Timer 0 overflow in
139. ead NOTE system reset occurs during operation mode the current value contained is retained If a system reset occurs after power on the value is undefined 4 32 ELECTRONICS 3C831B P831B CONTROL REGISTER PLLREF PLL Reference Frequency Selection Register F9H Set 1 Bank 0 Bit Identifier RESET Value Read Write Addressing Mode 7 NOTES 7 e s 4 3 2 3 o 1 1 1 2 1 1 1 1 R R R R W R W R W R W R W Register addressing mode only PLL Frequency Synthesizer Locked Unlocked Status Flag PLL is currently in locked state PLL is currently in unlocked state CE Pin level Status Flag ofc E pin is currently low level CE pin is currently high level IF Counter Gate Open Close Status Flag EN Gate is currently open Gate is currently close Power on Flag 9 EA Clear power on flag bit when write Power on occurred when read Reference Frequency Selection Bits When fxx 4 5MHz 4 000 j0j tkHzsgnl 1 8KHzsgnl S 0 0 1 0j5KHzsgnl 0 fo 1 1 Je26kHzsigna S 10kHzsignal 0 4 ifofo alojo 0 125 k zsiona 1100 0 JSOkHzsignal o 1 If a system reset occurs during operation mode the current value contained is retained If a system reset occurs after power on the value is undefined 2 Ifa system reset occurs during operation mode the current value contained is retained If a system rese
140. eas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange lt 48H SRPO 0A0H RPO lt RP1 lt nochange CLR RPO RPO lt OOH lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 32 8 Byte Slices 00001XXX 8 Byte Slice 16 Byte EE Contiguous Working 00000XXX 8 Byte Slice Register block RPO Figure 2 6 Contiguous 16 Byte Working Register Block ELECTRONICS 2 9 ADDRESS SPACES 3C831B P831B 8 Byte Slice Register File 16 Byte Contains 32 Contiguous 11110 XXX 8 Byte Slices working Register block RPO 00000 XXX 8 Byte Slice RP1 Figure 2 7 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO R1 ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO ADC RO R4 RO lt RO R4 C A
141. eceive mode 4 Shift Clock Edge Selection Bit Tx at falling edges Rx at rising edges le Tx at rising edges Rx at falling edges 3 SIO 0 Counter Clear and Shift Start Bit No action 1 Clear 3 bit counter and start shifting 2 SIO 0 Shift Operation Enable Bit Disable shifter and clock counter 1 Enable shifter and clock counter SIO 0 Interrupt Enable Bit Disable SIO 0 Interrupt Enable SIO 0 Interrupt 1 0 SIO 0 Interrupt Pending Bit No interrupt pending Clear pending condition when write 1 Interrupt is pending 4 36 ELECTRONICS 3C831B P831B CONTROL REGISTER SIO1CON sio 1 Control Register ECH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO 1 Shift Clock Selection Bit Internal clock P S clock 1 External clock SCK1 6 Data Direction Control Bit MSB first mode LSB first mode le 5 SIO 1 Mode Selection Bit eceive only mode 1 ransmit receive mode 4 Shift Clock Edge Selection Bit Tx at falling edges Rx at rising edges le Tx at rising edges Rx at falling edges 3 SIO 1 Counter Clear and Shift Start Bit No action 1 Clear 3 bit counter and start shifting 2 SIO 1 Shift Operation Enable Bit Disable shifter and clock counter 1 Enable shifter and clock counter SIO 1 Interrupt Enable Bit Disable SIO 1 Interrupt Enable SIO 1 Interrupt 1 0 SIO 1 Interrupt Pend
142. eds at least 25us for conversion time ELECTRONICS 20 7 ELECTRICAL DATA 3C831B P831B Table 20 7 PLL Electrical Characteristics TA 25 C to 85 Vpp 2 5 V to 3 5 V 4 5 V to 5 5 V VCOFM VCOAM ViN Sine wave input FMIF and AMIF input voltage peak to peak Frequency fVcoam VCOAM mode sine wave 0 5 VCOFM mode sine wave input Viy 0 3Vp p AMIF AMIF mode sine wave input Viy 0 3Vp p FMIF mode sine wave input Viy 0 3Vp p Table 20 8 Low Voltage Reset Electrical Characteristics TA 25 to 85 C Symbol Detect voltage range VpET LVRSEL V V A Min Max www 22 27 _ EN LVR operating 10 u current 20 8 ELECTRONICS 3C831B P831B ELECTRICAL DATA Table 20 9 Synchronous SIO Electrical Characteristics TA 25 C to 85 C Vpp 2 2V to 5 5 V SCKO SCK1 cycle time toxy SCKO SCK1 high low tu tre 500 uM ee 4 SCKO SCK1 high SI hold time to iksi External SCKO SCK1 source SCKO SCK1 high Internal SCKO SCK1 source Output delay for External SCKO SCK1 source SCKO SCKI to SO Internal SCKO SCK1 source SCKO SCK1 510 511 Figure 20 5 Serial Data Transfer Timing ELECTRONICS 20 9 ELECTRICAL DATA 3C831B P831B Table 20 10 Main Oscillator Characteristics fx TA 25 to 85 C Vpp 2 2V to 5 5 V Oscillator Clock Circuit Test Condition
143. egister However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 2 18 ELECTRONICS 3C831B P831B ADDRESS SPACES S7 PROGRAMMING Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP ELECTRONICS SPL 0FFH PP RPO RP1 R3 R3 RP1 RPO PP SPL lt FFH Normally the SPL is set to OFFH by the initialization routine Stack address OFEH PP Stack address OFDH lt RPO Stack address OFCH lt Stack address OFBH lt R3 lt Stack address OFBH RP1 lt Stack address OFCH RPO lt Stack address OFDH lt Stack address 2 19 ADDRESS SPACES 3C831B P831B NOTES 2 20 ELECTRONICS 3C831B P831B ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used t
144. egister File Addressing 2 12 ELECTRONICS 3C831B P831B ADDRESS SPACES COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages LCD Data Registers Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH Figure 2 10 Common Working Register Area eu ELECTRONICS 2 13 ADDRESS SPACES 3C831B P831B PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Use working register addressing instead SRP OCOH LD R2 40H Invalid addressing model R2 C2H lt the value in location 40H 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP OCOH ADD R3 45H lt R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable
145. egister only Rn n 0 15 Bit b of working register Rn b n 0 15 b 0 7 Bit LSB of working register Rn n 0 15 Working register pair RRp p 0 2 4 14 Register or working register reg or Rn reg 0 255 n 0 15 Bit b of register or working register reg b reg 0 255 b 0 7 Register pair or working register pair reg or RRp reg 0 254 even number only where 0 2 14 Indirect addressing mode addr addr 0 254 even number only Indirect working register only Rn n 0 15 Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Indirect working register pair only RRp p 0 2 14 Indirect register pair or indirect working RRp or reg reg 0 254 even only where register pair 0 2 14 Indexed addressing mode reg Rn reg 0 255 n 0 15 Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 Indexed long offset addressing mode taddr RRp addr range 0 65535 where 0 2 14 Direct addressing mode addr addr range 0 65535 Relative addressing mode addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction Immediate addressing mode data data 0 255 Immediate long addressing mode data data range 0 65535 ELECTRONICS 6 9 INSTRUCTION SET 3C831B P831B Table 6 5 Opcode Quick Referen
146. ement CLR 00H clears the destination register 00H value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH ELECTRONICS 3C831B P831B INSTRUCTION SET COM Complement COM dst Operation dst NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa Flags C Unaffected Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM RI gt R1 OF8H COM QHi gt R1 O7H register 07H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET 3C831B P831B CP Compare CP Operation Flags Format Examples 6 30 dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate
147. en Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET 3C831B P831B RLC Rotate Left Through Carry RLC Operation dst dst 0 C C c dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples 6 72 C Set if the bit rotated from the most significant bit position bit 7 was 1 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H C 0 RLC 00H gt Register OOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2bEH C 0 In the first example if general reg
148. ent of fVcorm fVcorm 732 and M is the remainder Bi Wa Example When PLLMOD 7 and PLLMOD 4 11 The following data are used to receive an FM band broadcasting station Receive frequency 100 0 MHz Reference frequency 25 kHz Intermediate frequency 10 7 MHz The frequency division value N and M are calculated as follows fVcorw 100 0 10 7 x 106 R T CETT 4428 138 x 32 12 N 138 decimal 8AH hexadecimal M 12 decimal OC hexadecimal You would modify the PLL data register and PLLMOD 7 4 register as follows PLLDO PLLMOD 7 4 IEEE ERI gt JOJ NF 0 C 18 10 ELECTRONICS 3C831B P831B INTERMEDIATE FREQUENCY COUNTER INTERMEDIATE FREQUENCY COUNTER OVERVIEW The S3C831B uses an intermediate frequency counter IFC to counter the frequency of the AM or FM signal at FMIF or AMIF pin The IFC block consists of a 1 2 divider gate control circuit IFC mode register IFMOD and a 16 bit binary counter The gate control circuit which controls the frequency counting time is programmed using the IFMOD register Four different gate times can be selected using IFMOD register settings During gate time the 16 bit IFC counts the input frequency at the FMIF or AMIF pins The FMIF or AMIF pin input signal for the 16 bit counter is selected using IFMOD register settings The 16 bit binary counter IFCNT1 IFCNTO can be read by 8 bit register addressing mode only When the FMIF pin input signal
149. equency If the input signal is High level when the gate is open one additional pulse is counted When the gate is close however counting is not affected by the input signal status In other words the counting error is 1 0 19 6 ELECTRONICS 3C831B P831B INTERMEDIATE FREQUENCY COUNTER IF COUNTER IFC OPERATION IFMOD register bits 2 and 3 are used to select the input pin and to start or stop IFC counting operation You stop the counting operation by clearing IFMOD 2 and IFMOD 3 to 0 The IFC retains its previous value until IFMOD register values are specified Setting bits IFMOD 3 and IFMOD 2 starts the frequency counting operation Counting continues as long as the gate is open The 16 bit counter value is automatically cleared to OOOOH after it overflows at FFFFH and continues counting from zero The 16 bit count value IFCNT1 IFCNTO can be read by register addressing mode A reset operation clears the counter to zero When the specified gate open time has elapsed the gate closes in order to complete the counter operation At this time the IFC interrupt pending bit PLLMOD 2 is automatically set to 1 and an interrupt is generated The pending bit must be cleared to 0 by software when the interrupt is serviced The IFC gate flag IFCFG is set to 1 at the same time the gate is closed Since the IFCFG flag is cleared to 0 when IFC operation start you can check the IFCFG flag to determine when IFC operation
150. erflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an internal and an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an internal and an external interrupt When BTCNT 3 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts 2 Ifa power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an internal and external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows When a BTCNT 3 overflow occurs normal CPU operation resumes
151. es Interrupt Types 5 2 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE 3C831B INTERRUPT STRUCTURE The S3C831B microcontroller supports seventeen interrupt sources All seventeen of the interrupt sources have corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed Levels Vectors Sources Reset Clear RESET 100H Basic timer overflow H W EO0H Timer 0 match capture S W Timer 0 overflow H W S W Timer 2 match S W Timer 1 match S W SIO1 interrupt S W SIOO interrupt S W Watch timer S W P1 0 external interrupt S W IRQO I
152. f Carry Flag H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of bit or subtraction generated borrow into bit Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag BA Bank 0 is selected 1 Bank 1 is selected 4 8 ELECTRONICS 3C831B P831B CONTROL REGISTER IFMOD IF Counter Mode Register F3H Set 1 Bank 0 Bit Identifier RESET Value Read Write Addressing Mode NOTE ELECTRONICS 5 4 3 2 3 J 0 E 0 0 0 0 0 R W R W R W R W R W R W Register addressing mode only System Clock Control Bit for PLL Frequency Synthesizer IF Counter Watch Timer The supplied clocks are not divided The supplied clocks are divided by 2 Not used for the S3C831B Select the PLL IFC Operation Voltage Select the PLL IFC operation voltage as 4 5V to 5 5V 1 Select the PLL IFC operation voltage as 2 5V to 3 5V Interrupt Sampling Clock Selection Bits IFC is disabled FMIF AMIF are pulled down and FMIF AMIF s feed back resistor are off Enable IFC operation AMIF pin is selected FMIF is pulled down and FMIF s feed back resistor is off 1 Enable IFC operation FMIF pin is selected AMIF is pulled down and AMIF s feed back resistor is off Enable IFC operation Both AMIF and FMIF are selected Gate Time Selecti
153. f bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register iw RW Function Description Interrupt mask register IMR R W _ Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO IRQ7 Interrupt priority register R W Controls the relative processing priorities of the interrupt levels The eight levels of S3C831B are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W This register enables disables fast interrupt processing and dynamic global interrup
154. f general register OOH contains the value 9AH 10011010B the statement SRA 00H shifts the bit values in register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in destination register OOH ELECTRONICS 6 79 INSTRUCTION SET 3C831B P831B SRP SRPO SRPI set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 src src src If src 1 1 and src 0 Othen RPO 3 7 lt 3 7 If src 1 0 and src 0 1 then RP1 3 7 lt src 3 7 If src 1 0 and src 0 Othen RPO 4 7 lt 4 7 RPO 3 lt 0 RP1 4 7 lt src 4 7 RP1 3 e 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS 3C831B P831B INSTRUCTION SET STOP Stop Operation STOP Operation Flags Fo
155. flags are set accordingly The contents of both operands are unaffected by the comparison C Setif a borrow occurred src dst cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 A2 r r SIC 6 r Ir opc SIC dst 3 6 A4 R R A5 R IR opc dst SIC 3 6 A6 R IM 1 Given Ri 02H and R2 03H CP R1 R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS 3C831B P831B INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE dst src RA Operation If dst src 0 PC PC RA Ir 1 The source operand is compared to
156. gister Address Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory gt Register Point to Working Pair 8 Bits 16 Bits OPERAND Value used in mue ae a Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES 3C831B P831B DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte d t 0 1 LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory
157. he IPR register priority definitions see Figure 5 7 Group A IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ3 GroupC IRQS IRQ6 IRQ7 B21 B22 C21 C22 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A The setting 101B would select the relationship C gt B A The functions of the other IPR bit settings are as follows PR 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts ELECTRONICS 5 11 INTERRUPT STRUCTURE 3C831B P831B Interrupt Priority Register IPR FFH Set 1 Bank 0 R W Group priority 0 IRQO gt IRQ1 MON 1 IRQ1 gt IRQO 0 Undefined Group B 1 gt gt 0 IRQ2 gt IRQ3 IRQ4 0 A gt B gt C 1 IRQ3 IRQ4 gt IRQ2 1 B gt A gt C Subgroup B 0 C gt A gt B 0 IRQ3 gt IRQ4 1 gt gt 1 IRQ4 gt IRQ3 A gt C gt B Group C Undefined 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6
158. iately loaded into the two counters the new data are loaded into the two counters when the current count operation has been completed The contents of the data register undetermined after initial power on However the data register retains its current value when the reset operation is initiated by an external reset or a change in level at the CE pin The swallow counter is a 5 bit binary down counter the programmable counter is a 12 bit binary down counter The swallow counter is for FM mode only The swallow counter and programmable counter start counting down simultaneously When the swallow counter starts counting down the 1 33 prescaler is selected When the swallow counter reaches zero it stop operation and selects the 1 32 prescaler 18 2 ELECTRONICS 3C831B P831B PLL FREQUENCY SYNTHESIZER PLL DATA REGISTER PLLD The frequency division value of the swallow counter and programmable counter is set in the PLL data register PLLDO PLLD1 PLL data register configuration is shown in Figure 18 2 Programmable Counter Swallow Counter Upper 12 bits Lower 5 bits 16 15 14 13 12 11 109 8 7 6 5 J B II ne NF Loo JSE PLLD1 F6H Bank 0 Set 1 PLLDO F7H Bank 0 Set 1 Figure 18 2 PLL Register Configuration Direct Frequency Division and Pulse Swallow Formulas In the direct frequency division method the upper 12 bits are valid In the pulse swallow method all 16 bits are valid The upper 12 bit are
159. ice them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 8F Example Given SYM O1H DI If the value of the SYM register is 01H the statement DI leaves the new value OOH in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET 3C831B P831B DIV Divide Unsigned DIV dst src Operation dst src dst UPPER s REMAINDER dst LOWER QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags C Set if the V flag is set and quotient is between 28 and 29 41 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is at
160. ied bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Flags IOZONO Format Bytes Cycles Opcode Addr Mode Hex dst src 3 6 3 6 67 Rb r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 O6H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 000001 11B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit O value of register R1 destination leaving the value 06H 000001 10B in register R1 ELECTRONICS 6 17 INSTRUCTION SET 3C831B P831B BCP Bit Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared
161. ified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes even number for program memory an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 E2 Given R6 10H R7 33H R8 12H program memory location 1033H external data memory location 1033H ODDH LDCD R8 Q9 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS 3C831B P831B INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI dst src Operation dst lt src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to prog
162. ift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter SIO1 counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting It is selected SCK1 and 501 output type push pull or open drain by PG2CON 7 Figure 16 2 Serial I O Module Control Register SIO1CON ELECTRONICS 16 3 SERIAL I O INTERFACE 3C831B P831B SIO0 AND SIO1 PRE SCALER REGISTER SIOOPS SIO1PS The prescaler registers for serial I O interface modules SIOOPS and SIO1PS are located at EBH and EEH in set 1 bank 0 respectively The values stored in the SIOO and SIO1 pre scale registers SIOOPS and SIO1PS lets you determine the SIOO and SIO1 clock rate baud rate as follows respectively Baud rate Input clock fxx 4 Pre scaler value 1 or SCKO and SCK1 input clock SIOO Pre scaler Register SIOOPS EBH Set 1 Bank 0 R W Baud rate fxx 4 SIOOPS 1 Figure 16 3 SIOO Pre scaler Register SIOOPS SIO1 Pre scaler Register SIO1PS EEH Set 1 Bank 0 R W Baud rate fxx 4 SIO1PS 1 Figure 16 4 SIO1 Pre scaler Register SIO1PS 16 4 ELECTRONICS 3C831B P831B SERIAL I O INTERFACE SIO0 BLOCK DIAGRAM 3 Bit Counter SIOOCON 0 K Clear Pending SIOOCON 1 SIOOCON S Interrupt Enable SIOOCON 7 SIOOCON 4 SIOOCON 2 Edge Select Shift Enable SIOOCON 5 scko Mode Select Side Qe banka CLK s Bit SIOO Shift Buffer EN SIOODA
163. in or you can configure the following alternative functions Low nibble pins P0 1 P0 3 TOCLK TOCAP TOOUT TOPWM High nibble pins PO 4 PO 7 TIOUT T2CLK T2OUT Port 0 Control Register Port 0 has two 8 bit control registers POCONH for 4 0 7 and POCONL for 0 0 3 A reset clears the POCONH and POCONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port O control registers must also be enabled in the associated peripheral module Port 0 Pull up Resistor Enable Register POPUR Using the port O pull up resistor enable register POPUR E2H set 1 bank 1 you can configure pull up resistors to individual port 0 pins Port 0 Control Register High Byte EOH Set 1 Bank 1 R W i 4 T1CLK NN 5 T1OUT P0 6 T2CLK 7 1200 POCONH bit pair pin configuration settings Input mode T1CLK T2CLk Output mode open drain Alternative function T1OUT T2OUT Output mode push pull Figure 9 1 Port 0 High Byte Control Register POCONH 9 4 ELECTRONICS 3C831B P831B Port 0 Control Register Low Byte E1H Set 1 Bank 1 R W PO 1 TOCLK PO 2 TOCAP P0 3 TOOUT TOPWM POCONL bit pair pin configuration settings Input mode TOCAP TOCLK Ou
164. in the source s mode or control register 5 14 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software OQ Or gt The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SVM O 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register 5 0 to disable all subsequent interrupts S
165. ing ELECTRONICS 3C831B P831B INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 SP lt IP IP IP IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement Before After Address Address Data IP IP Address Address Data PC 40 Enter PC 40 Enter 1F 41 Address H 41 Address H 01 42 Address L 42 AddressL 10 SP 43 Address H SP 43 Address H 20 110 Routine 21 IPL 50 22 Data 22 Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET 3C831B P831B EXIT exit EXIT Operation Flags Format Example 6 42 IP lt SP SP lt SP 2 lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected
166. ing Bit No interrupt pending Clear pending condition when write 1 Interrupt is pending ELECTRONICS 4 37 CONTROL REGISTERS 3C831B P831B SPH stack Pointer High Byte D8H Set 1 Bit Identifier RESET Value Read Write Addressing Mode 85 4 3 2 4 j 9 X X X X X X X X R W R W R W R W R W R W R W R W Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 RESET Value x x X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 0 4 38 Register addressing mode only Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SPO The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset ELECTRONICS 3C831B P831B CONTROL REGISTER STPCON Stop Control Register FBH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction set th
167. initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register OOH The sign flag and overflow flag are both cleared to 0 ELECTRONICS 3C831B P831B INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET 3C831B P831B SB1 Select Bank 1 SB1 Operation BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex OpC 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS 3C831B P831B INSTRUCTION SET SBC subtract with Carry SBC dst src Operation dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the sourc
168. ins the starting address of the service routine and is later used to swap the program counter values and When a fast interrupt occurs the contents of the FLAGS register is stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3C831B microcontroller the service routine for any one of the eight interrupt levels IRQO IRQ7 can be selected for fast interrupt processing Procedure for Initiating Fast Interrupts To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced aor ON Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register 7 The fast interrupt status bit in FLAGS is cleared automatically
169. ins the value 07H 000001 11B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET 3C831B P831B BITR Bit Reset BITR Operation Flags Format Example 6 20 dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst 4 7 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITR R11 o R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS 3C831B P831B INSTRUCTION SET BITS Bit Set BITS dst b Operation dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst 4 7 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address
170. ion program polls pending bit T1CON 0 When 1 is detected a timer 1 interrupt is pending When the T1INT sub routine has been serviced the pending condition must be cleared by software by writing a O to the timer 1 interrupt pending bit T1 CON O Timer 1 Control Register E5H Set 1 Bank 0 R W Timer 1 input clock selection bits Timer 1 interrupt pending bit 000 fxx 256 0 No interrupt pending 001 fxx 64 0 Clear pending bit when write 010 fxx 8 1 Interrupt is pending 011 fxx 111 External clock T1CLK input Timer 1 interrupt enable bit 0 Disable interrupt Not used 1 Enable interrupt Timer 1 counter clear bit Timer 1 count enable bit 0 No affect 0 Disable counting operation 1 Clear the timer 1 counter 1 Enable counting operation when write Figure 11 1 Timer 1 Control Register T1CON 11 2 ELECTRONICS 3C831B P831B 8 BIT TIMER 1 BLOCK DIAGRAM Bits 7 6 5 Data Bus T1CLK _ PO 4 fxx 256 8 bit up Counter R fxx 64 xx 6 Read Only fxx 8 Pendin fxx 1 9 Timer 1 Buffer Register Counter clear signal T1 CON 3 only Timer 1 Data Register Read Write Data Bus NOTE be loaded T1DATA value to buffer register for comparing T1CON 3 bit must be set 1 Figure 11 2 Timer 1 Functional Block Diagram ELECTRONICS 11 3 8 BIT TIMER 1 3C831B P831B NOTES 11 4 ELECTRONICS 3C831B P831B 16 BIT TIMER 2 16 BIT TIMER 2 OVERV
171. is STPCON register as 10100101b Otherwise the STOP instruction will not execute as well as reset will be generated ELECTRONICS 4 39 CONTROL REGISTERS 3C831B P831B SYM System Mode Register DEH Set 1 RESET Value 0 E 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Not used But you must keep 0 6 5 Not used for the S3C831B 4 2 Fast Interrupt Level Selection Bits 7 1 Fast Interrupt Enable Bit 2 Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit 9 EJ Disable all interrupt processing Enable all interrupt processing NOTES 1 You can select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 3 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O 4 40 ELECTRONICS 3C831B P831B CONTROL REGISTER Timer 0 Control Register E2H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 0 Input Clock Selection Bits LO of 0 ftos o a a a 190600000002 1 0 1 External clock TOCLK falling edge 1 1 0 External clock TOCLK rising edge 4 3 Timer 0 Operating Mode Selection Bits
172. is selected the signal is divided by two When the AMIF pin input signal is directly connected to the IFC it is not divided By setting IFMOD register the gate is opened for 2 ms 8 ms or 16 ms periods During the open period of the gate input frequency is counted by the 16 bit counter When the gate is closed the counting operation is complete and an interrupt is generated ul s B is Selector IF Counter 16 bit AMIF Gate Control Data Bus Circuit IRQ7 Gate Signal Generator DataBus Bus 1kHz Internal Signal When fxx 4 5 MHz NOTE If the main clock is 9MHz IFMOD 7 should be set to 1 Figure 19 1 IF Counter Block Diagram ELECTRONICS 19 1 INTERMEDIATE FREQUENCY COUNTER 3C831B P831B IFC MODE REGISTER IFMOD The IFC mode register IFMOD is a 8 bit register that is used to select the input pin divider for Vcorm input frequency PLL IPC operation voltage clock divider for PLL IFC WT and gate time Setting IFMOD register reset IFC value and IFC gate flag value and starts IFC operation IFC operation starts when you select AMIF or FMIF as the IFC input pin A reset operation clears all IFMOD values to 0 IFMOD Table 19 1 IFMOD Organization PLL Frequency Synthesizer If Counter Watch Timer Clock Control Bit IFMOD 7 PLL IFC Watch Timer Clock Setting 0 IThetxxisnotdivided for PLL IFC WT clock 1 The fxx is divided by 2 for PLL IFC WT clock The PLL IFC Operation
173. isable 1 Pull up enable 4 P3 4 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 3 P3 3 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 2 P3 2 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 0 P3 0 Pull up Resistor Enable Bit Pull up disable Pull up enable 4 28 ELECTRONICS 3C831B P831B CONTROL REGISTER PGOCON Port Group 0 Control Register EDH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 4 0 4 3 5 39 36 Mode Selection Bits o o 0 1 Input mode pullup 000 0 1 Open drain output mode Push pull output mode 5 4 P4 4 P4 7 SEG35 32 Mode Selection Bits o o Jinputmode 0 1 Input mode pullup o ENE Open drain output mode Push pull output mode 3 2 P5 0 P5 3 SEG31 28 Mode Selection Bits fo fr 71129 open lt ran ouput mode 1 0 P5 4 P5 7 SEG27 24 Mode Selection Bits Input mode pull up Open drain output mode Push pull output mode ELECTRONICS 4 29 CONTROL REGISTERS 3C831B P831B PG1CON Port Group 1 Control Register EEH Set 1 Bank 1 Bit Identifier 8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register ad
174. ise Unaffected Unaffected Flags TOSONO Format Bytes Cycles dst opc 1 4 opc dst 2 4 Examples Given RO 1BH register OOH OCH and register 1BH OFH INC RO gt RO 1CH INC OOH gt Register 00H INC BRO gt RO 1BH register 01H 10H 3C831B P831B Opcode Addr Mode Hex dst rE r r to 20 R 21 IR In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register 00H assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H 6 44 ELECTRONICS 3C831B P831B INSTRUCTION SET INCW Increment Word INCW dst Operation dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one Flags C Unaffected Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR A1 IR Examples Given RO R1 02H register 02H OFH and register INCW RRO gt RO 1AH R1 03H
175. ister 00H has the value OAAH 10101010B the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS 3C831B P831B INSTRUCTION SET RR Rotate Right RR dst Operation C lt dst 0 dst 7 lt dst 0 dst lt dst n 1 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags C Set if the bit rotated from the least significant bit position bit zero was 1 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Examples Given Register OOH 31H register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of
176. it reaches 10H At this point the Timer 2 interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 12 1 16 BIT TIMER 2 3C831B P831B TIMER 2 CONTROL REGISTER T2CON You use the timer 2 control register T2CON to Enable the timer 2 operating interval timer Select the timer 2 input clock frequency Clear the timer 2 counter T2CNTH L Enable the timer 2 interrupt and clear timer 2 interrupt pending condition T2CON is located in set 1 bank 1 at address FEH and is read write addressable using register addressing mode A reset clears T2CON to 00H This sets timer 2 to disable interval timer mode and disables timer 2 interrupt You can clear the timer 2 counter at any time during normal operation by writing a 1 to T2CON 3 To enable the timer 2 interrupt IRQ1 vector E4H you must write T2CON 2 and T2CON 1 to 1 To detect an interrupt pending condition when 2 is disabled the application program polls pending bit TZCON O When a 1 is detected a timer 2 interrupt is pending When the T2INT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer 2 interrupt pending bit 2 0 Timer 2 Control Registers FEH Set 1 Bank 1 Timer 0 input clock selection bits Timer 2 interrupt pending bit 000 fxx 256 0 No interrupt pending 001 fxx 64 0 Clear pending bit when write 010 fxx 8 1 Interru
177. ks are required to complete an 8 bit conversion When fxx 8 is selected for conversion clock with an 4 5 MHz fxx clock frequency one clock cycle is 1 78 us Each bit conversion requires 5 clocks the conversion rate is calculated as follows 5 clocks bit x 8 bits set up time 50 clocks 50 clock x 1 78 us 89 us at 0 56 MHz 4 5 MHz 8 Note that A D converter needs at least 25 for conversion time A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located at address set 1 bank 0 It has three functions Analog input pin selection bits 4 5 and 6 End of conversion status detection bit 3 ADC clock selection bits 2 and 1 A D operation start or enable bit O After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADO AD7 can be selected dynamically by manipulating the ADCON 4 6 bits And the pins not used for analog input can be used for normal I O function A D Converter Control Register ADCON EFH Set 1 Bank 0 R W EOC bit is read only Always logic zero Start or enable bit 0 Disable operation l 1 Start operation A D input pin selection bits 6 5 4 A D input pin Clock Selection bit Conversion CLK End of conversion bit 0 Not complete Conversion 1 complete Conversion Figure 15 1 A D Converter Control Register ADCON ELECTRONICS 15 3 8 BIT ANALOG
178. l analog input 8 bit conversion resolution 1 2 3C831B P831B Two 8 bit Serial I O Interface 8 bit transmit receive mode e 8 bit receive mode e Selectable baud rate or external clock source PLL Frequency Synthesizer e Vy level 300mVpp minimum e AMVCO range 0 5 MHz 30 MHz 3 bit counter added e FMVCO range 30 MHz 150 MHz 16 Bit Intermediate Frequency IF Counter e Vy level 300mVpp minimum AMIF range 100 kHz 1 MHz e FMIF range 5 MHz 15 MHz LCD Controller Driver 40 segments 4 common terminals 4 4 3 2 common and static selectable Internal or external resistor circuit for LCD bias Low Voltage Reset LVR Low voltage check to make system reset Vi yp 2 4 3 7 V selectable Two Power Down Modes mode only CPU clock stops Stop mode system clock and CPU clock stop Oscillation Source Crystal or ceramic for system clock fx Instruction Execution Time 444 ns at 9 0 MHz minimum Operating Temperature Range e 25 C to 85 Operating Voltage Range e 2 2V to 5 5V at 0 4 MHz 4 5 MHz e 40V to 5 5 V at 0 4 MHz 9 0 MHz e 2 5V to 3 5V 4 5 V to 5 5 V in PLL IFC block Package Type e 100 QFP 1420C 100 TQFP 1414 ELECTRONICS 3C831B P831B BLOCK DIAGRAM P1 0 P1 7 RESET INTO INT7 CE gt lt AS PO 2 TOCAP Timer PO 1 TOCLK gt Countero P0 3 TOOUT TOPWM 4 POA4 TICLK 8 Bit Timer PO S TIOUT
179. lly during each conversion step The successive approximation block performs 8 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON O When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATA register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATA before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADO AD7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 15 1 8 BIT ANALOG TO DIGITAL CONVERTER 3C831B P831B 15 2 ELECTRONICS 3C831B P831B 8 BIT ANALOG TO DIGITAL CONVERTER CONVERSION TIMING The A D conversion process requires 5 steps 5 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 cloc
180. location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 31 0 leave the value 31 BCD in address 27H R1 ELECTRONICS 3C831B P831B INSTRUCTION SET DEC Decrement DEC dst Operation dst lt dst 1 The contents of the destination operand are decremented by one Unaffected Set if the result is 0 cleared otherwise Flags 2 S Set if result is negative cleared otherwise V D H Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 00 R 01 IR Examples Given R1 03H and register 03H 10H DEC R1 gt R1 02H DEC QR gt Register 03H OFH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET 3C831B P831B DECW Decrement Word DECW Operation Flags Format Examples NOTE 6 36 dst ds
181. member that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET 3C831B P831B BTJRT sit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24 dst src b If src b is a 1 then PC PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 3C831B P831B INSTRUCTION SET BXOR Bit XOR BXOR dst src b BXOR dst b src Operation dst 0 lt dst 0 XOR src b or dst b lt dst b src 0 The specified bit of the source or the destination is logi
182. mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers timer counters and watch timer Idle mode is released by a reset or by an external or internal interrupt Stop Release Q Main System Sub system Oscillator Oscillator Circuit Circuit STOP OSC 1 1 1 4096 Basic Timer inst p Timer Counters STPCON LCD Controller STPCON Frequency 5100 SIO1 Dividing A D Converter Circuit U 1 PLL Frequency Synthesizer 11 1 7 1 8 116 IF Counter IFMOD 7 NOTE Thefxtis not implemented in the S3C831B IDLE Instruction CPU Clock Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS 3C831B P831B CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the set 1 address D4H It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W TENERNE must keep always 0 must keep always 0 Oscillator IRQ wake up Divide by
183. n length Examples Given RO 06H and general register OOH 05H LDB R0 00H2 gt RO 07H register 05H LDB 00H 0 RO gt RO 06H register OOH 04H In the first example destination working register RO contains the value 06H and the source general register OOH the value 05H The statement LD R0 00H 2 loads the bit two value of the OOH register into bit zero of the RO register leaving the value 07H in register RO In the second example OOH is the destination register The statement LD 0OH O RO loads bit zero of register RO to the specified bit bit zero of the destination register leaving O4H in general register OOH ELECTRONICS 6 51 INSTRUCTION SET 3C831B P831B LDC LDE Load Memory LDC LDE dst src Operation dst src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or rr values an even number for program memory and odd an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 10 C3 r Irr dst src 2 opc 2 10 D3 Irr r 12 E7 r XS rr e dst src XS 12 F7 5 dst src XL XL 4 14 A7 r XL rr 6 opc src dst XL XL 4 14 B7 XL rr r 7 dst 0000 DA DA 4 14 A7 r DA 9 opc dst
184. nds on the microcontroller s current internal operating mode The external interrupts in the S3C831B interrupt structure that can be used to release Stop mode are External interrupts 1 0 1 7 INTO INT7 Please note the following conditions for Stop mode release f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register f you use an internal or external interrupt for stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed How to Enter into Stop Mode Handling STPCON register then writing Stop instruction keep the order LD STPCON 10100101B STOP NOP NOP NOP ELECTRONICS 8 5 RESET and POWER DOWN 3C831B P831B IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the
185. ng 3 P1 3 INT3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P1 2 INT2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P1 1 INT1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P1 0 INTO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending N ELECTRONICS 4 CONTROL REGISTERS 3C831B P831B P2CONH Port 2 Control Register High Byte E8H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 AD7 Schmitt trigger input mode Lo 4 Schmitt trigger input mode pull up 1 0 Alternative function ADC mode Output mode push pull 5 4 2 6 71 Fo 1 5 Cr vo Atmawetmeon Domod 3 2 P2 5 AD5 Co o Smmsweermumode Fo 1 Schmit tigger input mode pur 71 71129 ater 1 0 P2 4 AD4 Schmitt trigger input mode oja Schmitt trigger input mode pull up 1 0 Alternative function ADC mode Output mode push pull 4 24 ELECTRONICS
186. o determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES 3C831B P831B REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File 8 bit Register rie Address Tha dst_ e cou OPERAND d 7 OPCODE Register in Register L One Operand 4 File Instruction Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File o M RPO or RP1 RPO or RP1 Selected RP points to start of working Working Registe
187. o different wavs As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction To signal the end of the required oscillation stabilization interval after a reset or a stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 FDH read only Basic timer control register BTCON set 1 D3H read write ELECTRONICS 10 1 BASIC TIMER and TIMER 0 3C831B P831B BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clears BTCON to This enables the watchdog function and selects a basic timer clock frequency of fxx 4096 To disable the watchdog function you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for all timers input clock you write a 1 to 0 Basic Control Register D3H Set 1 R W Watchdog
188. of the S3C831B I O port functions ELECTRONICS 9 1 PORTS 3C831B P831B Table 9 1 S3C831B Port Configuration Overview Configuration Options 1 bit programmable I O port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull up Alternately PO 1 PO 7 can be used as TOCLK TOCAP TOOUT TOPWM T1CLK T1OUT T2CLK T2OUT 1 bit programmable I O port Input or push pull output mode selected by software software assignable pull up P1 0 3 Shmitt trigger input P1 4 7 Input 1 0 1 7 can be used as inputs for external interrupts INTO INT7 with noise filter and interrupt control 1 bit programmable I O port Schmitt trigger input or push pull output mode selected by software software assignable pull up Alternately P2 0 P2 7 be used as ADO AD7 1 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull up Alternately P3 0 P3 6 can be used as BUZ SCKO SOO SIO SCK1 SO1 511 4 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull up P4 0 P4 7 can alternately be used as outputs for LCD segment signals 4 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull up 5 0 5 7 can alternately be used as outputs for LCD segment signals 4 bit programmable I O p
189. ogram Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION 3C831B P831B Table 6 2 Flag Notation Conventions Flag C Z S V D H 0 1 6 8 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS 3C831B P831B INSTRUCTION SET Table 6 4 Instruction Notation Conventions Condition code See list of condition codes in Table 6 6 Working r
190. on Bits fxx 4 5 MHz note Gate opens 2 millisecond intervals fo 4 Gate opens in 8 millisecond intervals KNIEA Gate opens in 16 millisecond intervals Gate remains open continuously If the main clock is 9MHz IFMOD 7 should be set to 1 4 9 CONTROL REGISTERS 3C831B P831B IMR Interrupt Mask Register DDH Set 1 Bit Identifier o8 4 3 2 4 j 9 X X X X X X X RESET Value x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit IF Interrupt Disable mask 1 Enable unmask 6 Interrupt Level 6 IRQ6 Enable Bit CE Interrupt Disable mask 1 Enable unmask 5 Interrupt Level 5 IRQ5 Enable Bit P1 4 P1 7 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit P1 0 P1 3 Disable mask 1 Enable unmask 3 Interrupt Level 3 IRQ3 Enable Bit Watch Timer Disable mask 1 Enable unmask 2 Inte rupt Level 2 IRQ2 Enable Bit SIO 0 SIO 1 Interrupt Disable mask 1 Enable unmask rupt Level 1 IRQ1 Enable Bit Timer 1 Timer 2 Interrupt Disable mask Inte 1 Enable unmask rupt Level 0 IRQO Enable Bit Timer 0 Match Capture or Overflow Disable mask 1 Enable unmask 0 Inte NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU 4 10
191. ontrol Bit 0 Internal voltage dividing resistors External voltage dividing resistors Internal voltage dividing resistors are off o o o 1 esHran 45Mk 1 9 NOTE f the main clock is 9 0MHz IFMOD 7 should be set to 1 o x x x LOD splay ff LCD off signal o o 9 71 3 9 9 wwe 0 9 1 ioe reas 1 9 9 71 3 9 Table 14 4 Maximum Number of Display Digits per Duty Cycle LCD Duty LCD Bias COM Output Pins Maximum Seg Display COMO 40 M COMO COMI COMO COM2 18 1 198 cowo cow COMO COMS 14 6 ELECTRONICS 3C831B P831B LCD CONTROLLER DRIVER LCD DRIVE VOLTAGE The LCD display is turned on only when the voltage difference between the common and segment signals is greater than The LCD display is turned off when the difference between the common and segment signal voltages is less than V cp The turn on voltage Vi cp or Vi cp is generated only when both signals are the selected signals of the bias Table 14 5 shows LCD drive voltages for static mode 1 2 bias and 1 3 bias Table 14 5 LCD Drive Voltage Values LCD Power Supply 1 2 Bias 1 3 Bias NOTE The LCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal voltage Therefore always drive the LCD panel with AC voltage LC
192. or SIO1DATA and set SIOOCON 3 or SIO1CON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the 5100 and SIO1 pending bits SIOOCON O and SIO1CON 0 are set to 1 and SIO interrupt requests are generated respectively ELECTRONICS 16 1 SERIAL I O INTERFACE 3C831B P831B SIO0 AND SIO1 CONTROL REGISTERS SIOOCON SIO1CON The control registers for serial I O interface modules SIOOCON is located at E9H and SIO1CON is located at ECH in set 1 bank 0 They have the control settings for SIO modules respectively Interrupt enable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first Clock source selection internal or external for shift clock A reset clears the SIOOCON and SIO1CON values to 00H This configures the corresponding modules with an internal clock source at the SCKO and 5 selects receive only operating mode and clears the 3 bit counter respectively The data shift operation and the interrupt are disabled The selected data direction is MSB first 16 2 Serial I O Module Control Register SIOOCON E9H Set 1 Bank 0 R W SIOO shift clock selection bit 0 Internal clock P S Clock 1 External clock SCKO Data direction control bit 0 MSB first mode 1 LSB first mode 5100 mode selection bit
193. ort Schmitt trigger input or push pull open drain output mode selected by software software assignable pull up P6 0 P6 7 can alternately be used as outputs for LCD segment signals 4 bit programmable I O port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull up 7 0 7 7 can alternately be used as outputs for LCD segment signals 4 bit programmable I O port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull up P8 0 P8 7 can alternately be used as outputs for LCD segment signals 9 2 ELECTRONICS 3C831B P831B PORTS PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all nine S3C831B I O port data registers Data registers for ports 0 1 2 3 4 5 6 7 and 8 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name Mnemonic Decimal Hex Location RW Pero data regser Po xo Fo Ww Port 6 data register Pe 246 Seti Baki RW Port 8 data register 8 248 Set Banki RW ELECTRONICS 9 3 PORTS 3C831B P831B PORT 0 Port 0 is an 8 bit I O port with individually configurable pins Port 0 pins are accessed directly by writing or reading the port 0 data register PO at location FOH in set 1 bank 1 0 0 0 7 can serve inputs as outputs push pull or open dra
194. otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 O NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS 3C831B P831B INSTRUCTION SET BITC Bit Complement BITC dst b Operation dst b NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to O Undefined Unaffected Unaffected Flags TOSONO Format Bytes Cycles Opcode Addr Mode Hex dst 4 57 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R11 o R1 05H If working register R1 conta
195. p Initialization Chip Chip Initialization Vpp Vss Vpp Vss 15 16 13 14 Logic power supply pin VDD should be tied to 5 V during programming NOTE Parentheses indicate pin number for 100 TQFP 1414 package Table 22 2 Comparison of S3P831B and S3C831B Features Program Memory 64 Kbyte EPROM 64 Kbyte mask ROM Operating Voltage Vpp 2 2 V to 5 5 V 2 2 V to 5 5 V OTP Programming Mode Vpp 5 V Vpp TEST1 12 5 V Po Pin Configuration 100 QFP 100 TQFP 100 QFP 100 TQFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TESTI pin of the S3P831B the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 22 3 below Table 22 3 Operating Mode Selection Criteria sv 5v 0 00H 1 EPROMread 12 5 V 0 0000H oo EPROM program 12 5 V o 0000H EPROM verify 12 5 V OE3FH Po EPROM read protection NOTE 0 means Low level 1 means High level 22 4 ELECTRONICS 3C831B P831B S3P831B OTP Instruction Clock Main Oscillator Frequency 2 25 MHZ 1 125 MHZ 100 kHz 400 kHz 2 2V Supply Voltage V CPU Clock 1 4n x oscillator frequency n 1 2 8 16 When PLL IFC operation operating voltage range is 2 5 V to 3 5 V or 4 5 V to 5 5 V Figure 22 3 Operating Voltage Range ELECTRONICS 22 5
196. p disable Pull up enable 4 PO 4 Pull up Resistor Enable Bit Pull up disable Pull up enable 3 PO 3 Pull up Resistor Enable Bit Pull up disable Pull up enable 2 P0 2 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 1 PO 1 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 0 0 0 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable mi ELECTRONICS 4 CONTROL REGISTERS 3C831B P831B P1CONH Port 1 Control Register High Byte E4H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 7 INT7 Input mode pull up interrupt on falling edge Input mode interrupt on rising edge 1 Input mode interrupt on rising or falling edge Output mode push pull 5 4 P1 6 INT6 Lo o input mode pultupiierupt on taling edge 1 input mode iterunton ising edge 71179 input mode interpt on rising orfalingedge 3 2 P1 5 INT5 Input mode pull up interrupt on falling edge Input mode interrupt on rising edge 1 Input mode interrupt on rising or falling edge Output mode push pull 1 0 P1 4 INT4 Input mode pull up interrupt on falling edge 1 Input mode interrupt on rising edge Input mode interrupt on rising or falling edge 1 Output mode push pull 4 20 ELECTRONICS
197. perand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Setif a carry from the low order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 02 6 03 r Ir opc SIC dst 3 6 04 R R 05 R IR opc dst SIC 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H ADD 01H 25H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET 3C831B P831B AND Logical AND AND Operation Flags Format Examples dst src dst dst AND src The source operand is logically ANDed with the destination operand The result is stored in th
198. peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively An means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C831B Set 1 Ecc and Values after RESET ae Locations DOH D2H are not mapped Basic Timer ercon en o o e o e o o 6 Crock Register em ow o system Flags es osa x x x 5 Register Pointer high Bye Re ev 1 1 0 0 0 Register Pointer Low Bye Re es om 1 1 0 0 1 ImemptRemesRegse ma sm System Mode Register ee Register Page Poner Fe 8 2 ELECTRONICS 3C831B P831B RESET and POWER DOWN Table 8 2 S3C831B Set 1 Bank 0 E Values after RESET ELE ee Timer 0 Counter Register TOCNT 224 EOH 0 O JO J O O Timer 0 Control Register 226 EAH 0 Jo J O O Timer 1 Counter Register TICNT 227 E3SH o Timer 1 Control Register TICON 229 ESH 0 O O O O 0 Interrupt Pending Register
199. program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex ope 1 10 OF The following diagram shows one example of how to use the NEXT instruction Before After Data Address Address Data 43 Address H 43 Address H ozo 44 Address L 44 Address L 6 60 45 Address 45 Address 120 130 Routine ELECTRONICS 3C831B P831B INSTRUCTION SET NOP No Operation NOP Operation No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET 3C831B P831B OR Logical OR OR Operation Flags Format Examples 6 62 dst src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result
200. pt INT7 Enable Disable interrupt 1 Enable interrupt 6 P1 6 External Interrupt INT6 Enable Bit Disable interrupt 1 Enable interrupt 5 P1 5 External Interrupt INT5 Enable Bit Disable interrupt 1 Enable interrupt 4 P1 4 External Interrupt INT4 Enable Bit Disable interrupt 1 Enable interrupt 3 P1 3 External Interrupt INT3 Enable Bit Disable interrupt 1 Enable interrupt 2 P1 2 External Interrupt INT2 Enable Bit Disable interrupt 1 Enable interrupt 1 External Interrupt INT1 Enable Bit Disable interrupt 1 Enable interrupt 0 P1 0 External Interrupt INTO Enable Bit Disable interrupt 1 Enable interrupt 4 22 ELECTRONICS 3C831B P831B CONTROL REGISTER P1PND Port 1 Interrupt Pending Register E7H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 INT7 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 6 P1 6 INT6 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 5 P1 5 INT5 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 P1 4 INT4 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pendi
201. pt is pending 011 fxx 111 External clock T2CLK input Timer 2 interrupt enable bit 0 Disable interrupt 1 Enable interrupt Not used Timer 2 count enable bit 0 Disable counting operation 1 Enable counting operation Timer 2 counter clear bit 0 No affect 1 Clear the timer 2 counter when write Figure 12 1 Timer 2 Control Register T2CON 12 2 ELECTRONICS 3C831B P831B 16 BIT TIMER 2 BLOCK DIAGRAM Bits 7 6 5 Data Bus T2CLK _ PO 6 2 fxx 256 16 bit up Counter R fxx 64 Read Only fxx 8 Pendin fxx 1 g Timer 2 Buffer Register Counter clear signal T2CON 3 Timer 2 Data Register Read Write Data Bus NOTE To be loaded T2DATAH L value to buffer register for comparing T2CON 3 bit must be set 1 Figure 12 2 Timer 2 Functional Block Diagram ELECTRONICS 12 3 16 BIT TIMER 2 3C831B P831B NOTES 12 4 ELECTRONICS 3C831B P831B WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit 6 of the watch timer control register WTCON 6 to 1 And if you want to service watch timer overflow interrupt IRQ3 vector F2H then set the WTCON 1 to 1 The watch timer overflow interrupt pending condition WTCON 0 must be cleared by software in the application s interrupt service routine by means of writing a to th
202. r Program Memory L OPERAND E OPCODE Working Register Two Operand Pd et Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the curruntly selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS 3C831B P831B ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH set 1 using the Indirect Register addressing mode Program Memory Register File B bit Register HANE ET ADDRESS OPCODE Point ta WA Register in Register One Operand O File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES 3C831B P831B INDIRECT REGISTER ADDRES
203. r 16 bits intermediate frequency counter Two synchronous SIO modules Two 8 bit timer counters One 16 bit timer counter Low voltage reset A Dconverter with 8 selectable input pins OTP The S3C831B microcontroller is also available in OTP One Time Programmable version S3P831B The S3P831B microcontroller has an on chip 64K byte one time programmable EPROM instead of masked ROM The S3P831B is comparable to S3C831B both in function and in pin configuration ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM88RC CPU core Memory e 2576 bvte internal register file including LCD display RAM e 64K byte internal program memory area Instruction Set 78 instructions and Stop instructions 72 I O Pins e 32 normal I O pins 40 pins sharing with LCD segment signals Interrupts 8 interrupt levels and 17 internal sources Fast interrupt processing feature 8 Bit Basic Timer Watchdog timer function e of clock source Timer Counter 0 e Programmable 8 bit internal timer e External event counter function PWM and capture function Timer Counter 1 Programmable 8 bit interval timer External event counter function Timer Counter 2 Programmable 16 bit interval timer e External event counter function Watch Timer Interval Time 50ms 0 55 1 05 at 4 5 MHz 1 1 5 3 6 kHz buzzer output selectable Analog to Digital Converter e 8 channe
204. r 00H 01H register 01H 55H SP OOFCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET 3C831B P831B POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example 6 64 dst src dst src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 92 R IR Given Register OOH 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 200H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS 3C831B P831B INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI dst src Operation dst src IR IR 1 The POPUI instruction is used
205. ram memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 E3 Examples Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 is incremented by one RR6 lt RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET 3C831B P831B LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples 6 56 dst src m m 41 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes an even number for program memory and odd number for external data memory
206. registers RO R2 R3 no change 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 no change RO contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into external data memory location 0105H 01H 0104H RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H RO lt contents of program memory location 1104H RO 88H RO lt contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET 3C831B P831B LDCD LDED Load Memory and Decrement LDCD LDED dstsrc Operation Flags Format Examples 6 54 dst src ro m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is spec
207. rmat Example The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F The statement STOP halts all microcontroller operations NOP NOP NOP ELECTRONICS 6 81 INSTRUCTION SET 3C831B P831B SUB Subtract SUB Operation Flags Format Examples 6 82 dst src dst dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand C Set if a borrow occ
208. rt 1 High Byte Control Register PICONH Port 1 Control Register Low Byte P1CONL E5H Set 1 Bank 1 R W P1 3 INT3 P1CONL bit pair pin configuration Schmitt trigger input mode pull up interrupt on falling edge Schmitt trigger input mode interrupt on rising edge Schmitt trigger input mode interrupt on rising or falling edge Output mode push pull Figure 9 5 Port 1 Low Byte Control Register P1 CONL ELECTRONICS 9 7 VO PORTS 3C831B P831B Port 1 Interrupt Control Register P1INT E6H Set 1 Bank 1 R W errr eT Ty INT7 6 INT5 INT4 INT3 INT2 INTI INTO P1INT bit configuration settings 0 Disable interrupt Enable interrupt Figure 9 6 Port 1 Interrupt Control Register P1INT Port 1 Interrupt Pending Register P1PND E7H Set 1 Bank 1 R W To PND7 PND6 PND5 PND4 PND3 PND2 PND1 PNDO P1PND bit configuration settings Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 7 Port 1 Interrupt Pending Register P1PND 9 8 ELECTRONICS 3C831B P831B PORTS PORT 2 Port 2 is an 8 bit I O port that can be used for general purpose I O as A D converter inputs ADO AD7 The pins are accessed directiv bv writing or reading the port 2 data register P2 at location F2H in set 1 bank 1 To individually configure the port 2 pins P2 0 P2 7 you make bit pair settings in two control registers located in set 1 bank 1 P2CONL low byte
209. scribe the current status of CPU operations Four of these bits FLAGS 7 FLAGS A be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W Bank address status flag BA Carry flag C Fast interrupt Zero flag Z status flag FS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS 3C831B P831B INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate an
210. sequence of operations that follow WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS 3C831B P831B XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a bit is stored Unaffected Always reset to O Unaffected Unaffected IO cONO opc SIC dst opc dst SIC Set if the result is 0 cleared otherwise Setif the result bit 7 is set cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst 2 4 B2 r B3 r 3 6 B4 R B5 R 3 6 B6 R src r Given RO 0C7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H XOR RO R1 XOR RO R1 XOR 00H 01H XOR 00H 01H XOR 00H 54H gt 3 E RO 0C5H R1 02H RO OE4H R1 02H register 02H 23H Register OOH 29H register 01H 02H Register OOH 08H register 01H 02H register 02H Register OOH 7FH 28H In the first example if working register RO contains the value 0C7H and if register
211. set in the programmable counter and the lower 4 bits and the NF bit are set in the swallow counter The frequency division formulas for both methods as set in the PLL data register are shown below Direct frequency division AM is fV fr 92 When PLLMOD 7 and PLLMOD 4 are set to logic 00 fR 8xN When PLLMOD 7 and PLLMOD 4 are set to logic O1 Where the frequency division value N is 12 bits fVcoam input frequency at the Vcoam pin Pulse swallow system is fVcoam AM When PLLMOD 7 PLLMOD 4 are set to logic 10 FM fa COEM When PLLMOD 7 and PLLMOD 4 are set to logic 11 Nx32 M l e 7 4 5 9 l where the frequency division values and M 12 bits and 5 bits respectively fV copy input frequency at the Vcorm Pin ELECTRONICS 18 3 PLL FREQUENCY SYNTHESIZER 3C831B P831B REFERENCE FREQUENCY GENERATOR The reference frequency generator produce reference frequency which are then compared by the phase comparator As shown in Figure 18 3 the reference frequency generator divides a crystal oscillation frequency of 4 5 MHz and generates the reference frequency fp for the PLL frequency synthesizer Using the PLLREF register you can select from ten different reference frequencies Data Bus Frequency 6 25 kHz To Phase Divider Selector Detector IFMOD 7 Figure 18 3 Reference Frequency Generator 18 4 ELECTRONICS 3
212. st Reset Clear Decimal Hex Interrupt Priority in S W Value Value Level Level EE 100H Basic timer overflow RESET Timer 0 overflow ee Timer 1 match IRQ1 SIOO interrupt IRQ2 SIO1 bud P1 7 external interrupt IRQ5 P1 6 external interrupt 218 216 P1 5 external interrupt P1 4 external interrupt CE interrupt IRQ IF interrupt IRQ7 NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 ftwo or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware P1 3 external interrupt IRQ4 P1 2 external interrupt P1 1 external interrupt P1 0 external interrupt on ELECTRONICS 5 5 INTERRUPT STRUCTURE 3C831B P831B ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value o
213. subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 7 C row NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 03H and register 03H 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET 3C831B P831B CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example 6 32 dst src RA If dst src 0 lt PC RA Ir Ir 1
214. t 051 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 81 IR Given RO 12H R1 R2 register OFH and register 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS 3C831B P831B INSTRUCTION SET DI Disable Interrupts DI Operation SYM 0 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not serv
215. t dst x src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Flags C Set if result is gt 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H register 02H 09H register 06H MULT 00H 02H gt Register OOH 01H register 01H 20H register 02H 09H MULT 00H Q01H gt Register OOH OOH register 01H OCOH MULT OOH 30H gt Register OOH 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET 3C831B P831B NEXT next NEXT Operation Flags Format Example Address PC IP IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the
216. t occurs after power on the value is 1 3 The POF bit is read initially to check whether or not power has been turned on 4 Ifthe main clock is 9MHz IFMOD 7 should be set to 1 ELECTRONICS 4 33 CONTROL REGISTERS 3C831B P831B PP Register Page Pointer DFH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 0 0 0 0 Destination pageo PO 0 0 1 Destination paget 0 0 1 0 Destination page2 S PO ot 1 Destination page 4 ination O Destination page6 O Destination pageS 3 0 Source Register Page Selection Bits 00 00 JSouroerpageo S 0 0 0 t soucepaget S 101011 0 Jsouroerpagaz 0 0 1 f sourcepages 0 1 070 Sourcepages 0 25 0 i ot sourcepages Oi 170 sourcepages fjSoepage 7 o 1 0 070 soucepages 101011 soucepages 0 NOTE In the S3C831B microcontroller the internal register file is configured as ten pages Pages 0 9 The pages 0 8 are used for general purpose register file and page 9 is used for LCD data register or general purpose registers 4 34 ELECTRONICS 3C831B P831B CONTROL REGISTER RPO Register Pointer 0 D6H Set 1 RESET Value 1 1 0 0 0 x Read Write R W R W R W R W R W Addressing Mode Register a
217. t processing NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended 5 6 ELECTRONICS 3C831B P831B INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El S Q Interrupt Request Register Read only RESET R IRQO IRQ7 Interrupts Interrupt Prioritv Register Interrupt Interrupt Mask Register Global Interrupt Control El DI or SVM O manipulation Figure 5 4 Interrupt Function Diagram ELECTRONICS B 7 3C831B P831B INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data
218. tempted otherwise it takes 26 cycles Examples Given RO 10H R1 R2 40H register 40H 80H DIV RRO R2 gt RO R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO RI 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS 3C831B P831B INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ r dst Operation re rc 1 If r z0 PC PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location OCOH to OCFH with SRP SRPO or SRP1 instruction Flags No flags are affected Format Bytes Cy
219. tents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET 3C831B P831B LDW Load Word LDW Operation Flags Format Examples 6 58 dst src dst src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 C4 RR RR 8 C5 RR IR opc dst SIC 4 8 C6 RR IML 05H R7 02H register OOH Given R4 06H R5 1CH R6 03H and register O3H OFH register 01H 02H register 02H LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 00H 03H register 01H OFH register 02H 03H register 03H OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H OFH LDW RR6 1234H gt R6 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register 03H OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H 01H This leaves the value 03H in general register 00H and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS 3C831B P831B INSTRUCTION SET MULT multiply Unsigned MULT dst src Operation dst l
220. ternative function SCK1 out Output mode push pull NOTE The SO1 and SCK1 outputs are selected as push pull or open drain by PG2CON 4 26 ELECTRONICS 3C831B P831B CONTROL REGISTER P3CONL Port 3 Control Register Low Byte EBH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 SIO o o Imutmode SIO 0 1 Output mode open drain o 1 0 Not availabe 1110100000 5 4 P3 2 SO0 Fo 1 outputmede open drain 711290 Jateratvetuneton SO SSS 3 2 P3 1 SCKO 0 o input mode seko 1717111000 fo 4 Output mode open drain 1 0 Alternative function SCKO out Output mode push pull 1 0 P3 0 BUZ o o Jinputmode o 0 1 Output mode open drain 1111110000 1 0 Alternative function BUZ Output mode push pull NOTE The SOO and SCKO outputs are selected as push pull or open drain by PG2CON ELECTRONICS 4 27 CONTROL REGISTERS 3C831B P831B P3PUR Port Pull up Control Register ECH Set 1 Bank 1 Bit Identifier 8 4 3 2 4 j 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P3 7 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 6 P3 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 P3 5 Pull up Resistor Enable Bit Pull up d
221. terrupt enable bit 001 fxx 256 0 Disable overflow interrupt 010 fxx 64 1 Enable overflow interrupt 011 fxx 8 100 fxx Timer 0 match capture interrupt enable bit 101 External clock 0 Disable interrupt PO 1 TOCLK falling edge 1 Enable interrupt 110 External clock PO 1 TOCLK rising edge 111 Counter stop Timer 0 counter clear bit 0 No effect 1 Clear the timer 0 counter when write Timer 0 operating mode selection bits 00 Interval mode PO 3 TOOUT 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF and match interrupt can occur Figure 10 3 Timer 0 Control Register TOCON 10 6 ELECTRONICS 3C831B P831B BASIC TIMER and TIMER 0 Timer 0 Interrupt Pending Register INTPND E6H Set 1 Bank 0 R W Not used Timer 0 overflow interrupt pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Timer 0 match capture pending bit 0 Interrupt request is not pending pending bit clear when write O 1 Interrupt request is pending Figure 10 4 Timer 0 Interrupt Pending Register INTPND ELECTRONICS 10 7 BASIC TIMER and TIMER 0 3C831B P831B TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts IRQO Vectors EOH and E2H The timer 0 can generate two interrupts the timer 0 overflow interrupt TOOVF an
222. the EOO and EO pin NOTE The PLL frequency synthesizer operates only when the CE pin is High level When the CE pin is Low level the synthesizer is disable Input Selection Circuit The input selection circuit consists of the Vcoam pin and Vcorm pins an FM AM selector and two amplifiers The input selection circuit selects the frequency division method and the input pin of the PLL frequency You can choose one of two frequency division methods using the PLL mode register 1 direct frequency division method or 2 pulse swallow method The PLL mode register is also used to select the or Vcorm pin as the frequency input pin Programmable Divider The programmable divider divides the frequency of the signal from the Vcoam and Vcorm pins in accordance with the values contained in the swallow counter and programmable counter The programmable divider consists of prescalers a swallow counter and a programmable counter When the PLL operation starts the contents of the PLL data registers PLLDO PLLD 1 and the NF bit in the PLLMOD register are automatically loaded into the 12 bit programmable counter and the 5 bit swallow counter When the 12 bit programmable down counter reaches zero the contents of the data register are automatically reloaded into the programmable counter and the swallow counter for the next counting operation If you modify the data register value while the PLL is operating the new values are not immed
223. the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one aftera pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 15 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register D9H After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C831B the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data r
224. the addition of low order operands to be carried into the addition of high order operands C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Setif there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 2 4 12 EL 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 C flag 1 register 01H 20H register 02H and register 03H OAH ADC R1 R2 E R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H gt gt ADC 01H 02H Register 01H 2BH register 02H 03H ADC 01H 11H Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS 3C831B P831B INSTRUCTION SET ADD Add ADD dst src Operation dst dst src The source operand is added to the destination o
225. tination operand are swapped Flags C Undefined 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R 4 F1 IR Examples Given Register OOH register 02H 03H and register 03H OA4H SWAP OOH gt Register OOH OE3H SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value 1110001 1B ELECTRONICS 6 83 INSTRUCTION SET 3C831B P831B TCM rest Complement Under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mod
226. tinued Examples Given RO 01H R1 OAH register 00H 01H register 01H 20H register 02H 02H LOOP 30H and register OFFH LD LD LD LD LD LD LD LD LD LD LD LD 6 50 RO 10H R0 01H 01H RO R1 RO QRO R1 00H 01H 02H 00H 00H 0AH 00H 10H 00H 02H gt RO LOOP R1 gt LOOP RO R1 bobo tb bt bk 4 ol RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01H 20H Register 02H 20H register 01H Register OOH OAH Register 00H 01H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 OAH Register OAH RO 01H R1 OAH ELECTRONICS 3C831B P831B INSTRUCTION SET LDB Load Bit LDB dst src b LDB dst b src Operation dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc sbio sc 3 6 47 0 Rb opc dst 3 6 47 Rb NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit i
227. tion Z would probably be used after a CP instruction however EQ would probably be used 2 For operations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used ELECTRONICS 3C831B P831B INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET 3C831B P831B ADC Add with carry ADC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from
228. tions BUZ SCKO 500 610 5 1 501 SI1 Port 3 Control Registers Port has two 8 bit control registers PSCONH for P3 4 P3 7 and P3CONL for P3 0 P3 3 A reset clears the P3CONH and P3CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode enable pull up resistors and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port 3 Control Register High Byte PSCONH EAH Set 1 Bank 1 R W TOL P3 6 SI1 5 501 P3 4 SCK1 P3CONH bit pair pin configuration settings 00 Input mode SCK1 SI1 01 Output mode open drain 10 Alternative function SCK1 SO1 11 Output mode push pull NOTE The SO1 and SCK1 output are selected as push pull or open drain by PG2CON Figure 9 10 Port High Bvte Control Register PSCONH ELECTRONICS 9 11 VO PORTS Port 3 Control Register Low Byte P3CONL EBH Set 1 Bank 1 R W T n 0 BUZ P3 1 SCKO P3 2 500 P3 3 SIO P3CONL bit pair pin configuration settings Input mode SCKO SIO Output mode open drain Alternative function BUZ SCKO SOO Output mode push pull The SOO and SCKO output are selected as push pull or open drain by PG2CON Figure 9 11 Port 3 Low Byte Control Register PSCONL
229. tput mode open drain Alternative function TOOUT TOPWM Output mode push pull Figure 9 2 Port 0 Low Byte Control Register POCONL Port 0 Pull up Control Register E2H Set 1 Bank 1 R W TTTTTTTT PO7 PO 6 PO 5 PO 4 PO 3 PO 1 PO O POPUR bit configuration settings 0 Disable pull up resistor Enable pull up resistor NOTE corresponding pull up resistor is disabled automatically when a bit of port 0 is selected as output mode Figure 9 3 Port 0 Pull up Control Register POPUR ELECTRONICS PORTS 9 5 PORTS 3C831B P831B PORT 1 Port 1 is an 8 bit I O Port that you can use two ways General purpose I O External interrupt inputs for INTO INT7 Port 1 is accessed directly by writing or reading the port 1 data register P1 at location F1H in set 1 bank 1 NOTE The port 1 inputs can be disabled by PG2CON 5 4 when the port is selected as input mode Refer to the PG2CON register Port 1 Control Register P1CONH P1CONL Port 1 pins are configured individually by bit pair settings in two control registers located in set 1 bank 1 P1CONL low byte E5H and P1CONH high byte E4H When you select output mode a push pull circuit is automatically configured In input mode three different selections are available Input with interrupt generation on falling edges P1 0 3 Schmitt trigger input Input with interrupt generation on rising edges P1 0 3 Schmitt trigger
230. trol register low byte P2CONL 233 RW Jojojojojojojojoj Port control register high byte 24 RW Jojojojojojojojoj 25 RW Jojojojojojojojoj Port 3 pull up resistors enable P3PUR 236 ECH R W register Port group 0 control register PGOCON 27 RW 0 0 0 0 0 0 0 0 Port group 1 control register PGICON 288 RW 0jOjOj O O O O O Port group 2 control register PG2CON 289 erm RW 0 0 0 0 0 0 0 0 Port 0 data register 240 RW olololololololo Port 1 data register P 24 RW 0j0jojo ojo ojo Port 2 data register P2 242 RW olololololololo Port 3 data register P8 243 rn 0jOjOj O O O Port 4 data register P4 24 rm RW olololololololo Port 5 data register P5 245 r RW Jojojojojojojojo Port 6 data register Pe 246 re RW Jojojojojojojojo Pot7dataregster P7 24 FzH RW 0 0 0 0 0 0 0 0 Pot8dataregster Pae 248 RW Jojojo ojojo ojo Location F9H is not mapped Timer 2 counter high byte TaCNTH 250 FAH Jojoljojojojojojoj Timer 2 counter low byte TeCNTL 251 Jojojojojojojojoj Timer2contolregster TaCON 254 ren RW Jojojojojojojojoj eu ELECTRONICS 4 3 CONTROL REGISTERS Bit number s that is are appended to the register name for bit addressing Register ID FLAGS System Flags Register D5H
231. upt Timer 1 Interrupt Pending Bit No timer 1 interrupt pending when read Clear timer 1 interrupt pending condition when write T1 interrupt is pending NOTE When you write a 1 to T1CON 3 the timer 1 counter value is cleared to 00H Immediately following the write operation the T1CON 3 value is automatically cleared to O 4 42 ELECTRONICS 3C831B P831B CONTROL REGISTER T2CON Timer 2 Control Register FEH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 2 Input Clock Selection Bits ofofo External clock T2CLK input 4 Not used for the S3C831B er 2 Counter Clear Bit Note No effect 3 Ti 3 1 Clear the timer 2 counter when write 2 Timer 2 Counter Enable Bit Disable counting operation 1 Enable counting operation Timer 2 Interrupt Enable Bit Disable timer 2 interrupt 1 Enable timer 2 interrupt 0 Timer 2 Interrupt Pending Bit No timer 2 interrupt pending when read Clear timer 2 interrupt pending bit when write T2 interrupt is pending NOTE When you write a 1 to T2CON 3 the timer 2 counter value is cleared to OOH Immediately following the write operation the T2CON 3 value is automatically cleared to O ELECTRONICS 4 43 CONTROL REGISTERS 3C831B P831B WTCON watch Timer Control Register E8H Set 1 Bank 0 RES
232. uptrequestregister ma zo oon m e o e o o s o o zr ton ppp npe system mode register ze oen mw Regier page ime so bmc mw 0 019119151000 eu ELECTRONICS 4 1 CONTROL REGISTERS 3C831B P831B Table 4 2 Set 1 Bank 0 Registers Decimal Hex 7 6 5 4 2 1 0 Timer 0 counter register 224 jojojo ojojo ojo TimerOcontolregster 226 E2H RW 0 0 0 0 0 0 Timer 1 counter register 227 00 0 0 0 0 Timericontolregster TICON 229 RW jojojo ojojo ojo Interrupt pending register INTPND 230 RW 0 0 Location E7H is not mapped Watch timer control WTCON 232 RW l joljojojojojojoj SlO Ocontolregiser SIOOCON 233 RW Jojojojojojojojoj SIO 0 data register SIOODATA 24 EAH RW jojojo ojojo ojo SlO Oprescalerregster SiooPS 235 RW 00 SIO 1 control register SIOTCON 236 RW Jojojojojojojojoj SIO 1 dataregiser SIOIDATA 237 EDH RW Jojojojojojojojoj SIO 1 prescalerregister SiOtPS 238 RW Jojojojojojojojoj A D converter control register ADCON 239 RW l jojojojojojojoj ADconvererdataregister ADDATA 240 ron JjJx x x x x x x x LCD control register
233. urred cleared otherwise 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 22 r r SIC 6 23 r Ir opc SIC dst 3 6 24 R R 6 25 R IR opc dst SIC 3 6 26 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register 03 OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H 1EH register 02H 03H SUB 01H 02H gt Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H gt Register 01H OBCH C and S 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS 3C831B P831B INSTRUCTION SET SWAP Swap Nibbles SWAP dst Operation dst 0 3 lt gt dst 4 7 The contents of the lower four bits and upper four bits of the des
234. y NOTE f the main clock is 9MHz IFMOD 7 should be set to 1 ELECTRONICS 18 7 PLL FREQUENCY SYNTHESIZER 3C831B P831B PHASE DETECTOR CHARGE PUMP AND UNLOCK DETECTOR The phase comparator compare the phase difference between divided frequency fu output from the programmable divider and the reference frequency fp output from the reference frequency generator The charge pump outputs the phase comparator s output from error output pins EOO and 1 The relation between the error output pin divided frequency fy and reference frequency fp is shown below fa gt fu Low level output fa fy High level output fa fy Floating level A PLL operation starts when a value is loaded to the PLLMOD register The PLL unlock flag ULFG in the PLL reference register PLLREF provides status information regarding the reference frequency and divided frequency The unlock detector detects the unlock state of the PLL frequency synthesizer The unlock flag in the PLLREF register is set to 1 in an unlock state When ULFG 0 the PLL locked state is selected PLLREF7 4 ULFG cEFG IFCFG POFG FgHatbankOofseti The ULFG flag is set continuously at a period of reference frequency fp by the unlock detector You must therefore read the ULFG flag in the PLLREF register at periods longer than 1 1 of the reference frequency ULFG is reset wherever it is read PLL operation is controlled by the state of the CE chip enable

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