Application Note 2173 I2C Communication Over FPD
Contents
1. I2C Communication Over FPD Link Ill with Bidirectional Control Channel Introduction This application note describes communication between de vices using the FPD Link III SerDes with a bidirectional con trol channel using 12C The low latency bidirectional control interface allows the master I2C device to remotely control pe ripherals across the serial link I2C Overview The Inter Integrated Circuit 12C bus is a two wire bidirec tional bus that allows multiple devices to operate on the same bus Figure 7 The bus consists of master and slave devices which transmit data back and forth over the 12C interface Master devices control the bus and are typically microcon trollers FPGAs DSPs or other digital controllers The slave devices are controlled by a host controller 12C uses a master slave protocol when data is exchanged among devices Each device on the bus both master and slave can be a receiver MASTER National Semiconductor Application Note 2173 Dac Tran July 14 2011 and or transmitter The bus consists of two wires the SCL clock line and the SDA data line The two wires are open collector drain outputs and must be pulled high using an ex ternal pull up resistor A logic state low is transmitted by driving the output low A logic high state is transmitted by re leasing the output and allowing it to be pulled up externally The appropriate pull up resistor values will depend upon the total bus capaci2. RITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein Life support devices or systems are devices which a are intended for surgical implant into the body or b Support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation All other brand or product names may be trademarks or registered trademarks of their respective holders Copyright 2011 National Semiconductor Corporation For the most current product information visit us at www national com National Semiconductor National Semiconductor Europe National Semiconductor Asia National Semiconductor Japan Americas Technical Technical Support Center Pacific Technical Support Center Technical Support Center Support Center Email europe support nsc com Email ap support nsc com Email jon feedback nsc com Email support nsc com Tel 1 800 272 9959 www national com
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4. ctions across the bidirectional control link When ad dressing a remote peripheral or SerDes the slave proxy will forward any byte transactions sent by the Master controller to the target device The device will function as a master proxy device acts as a master on behalf of the 12C host controller HOST Controller LOCAL I C HOST I C 30168803 FIGURE 3 Typical FPD Link III Connection with 12C Bus www national com In order to communicate with remote devices on the 12C bus through the bidirectional control channel slave clock stretch ing must be supported by the 12C host controller The chipsets with a bidirectional control channel employ 12C clock stretch ing during remote data transmission as described in the CLOCK STRETCHING section During this phase the control channel is embedded on the link and then data is reconstruct ed on the remote bus Note the slave device will not control the clock and only stretches it until the remote peripheral has responded Response SCL p Low Delay Time START or repeated START condition a Slave Address _ 4 ___ __ACK _ Byte Data 30168804 FIGURE 4 Clock Stretch For Sent Byte Figure 4 shows an example of a remote access including the clock stretching period following the transmitted byte prior to completion of the acknowledge bit Since each byte trans ferred to the 12C slave must be acknowledged separately
5. des an overview of the I2C bus along with details describing the interface between FPD Link www national com Ill chipsets with a bidirectional control channel and 12C pe ripherals References 1 NXP UM102104 l2C bus specification and user manual Rev 03 19 June 2007 2 DS90UB901Q 902Q DS90UB903Q 904Q Datasheet 3 DS9NDUH925Q 926Q DS90UB925Q 926Q Datasheet www national com EZLC NV I2C Communication Over FPD Link Ill with Bidirectional Control Channel AN 2173 Notes For more National Semiconductor product information and proven design tools visit the following Web sites at www national com Amplifiers www national com webench i www national com appnotes Clock and Timing www national com refdesigns Data Converters www national com samples Interface www national com evalboards LVDS www national com packaging Power Management www national com quality green Switching Regulators www national com contacts LDOs www national com quality LED Lighting www national com feedback Voltage References www national com easy PowerWise Solutions www national com solutions Serial Digital Interface SDI www national com milaero Temperature Sensors www national com solarmagic PLL VCO www national com wireless PowerWise Design www national com training University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION NATIONAL PRODUCTS NATIONAL MAKES NO REPRESENTATION
6. e slave holds down SCL to prevent it from rising high again to delay the SCL clock rate and pause communication When the master attempts to make SCL high to complete the current clock pulse it should verify that SCL has really gone high If it is still low this indicates a slave is holding SCL low and the master must wait until SCL goes high before contin uing Bidirectional Control Channel Using 126 The FPD Link Ill Serializer Deserializer SerDes chipsets support full duplex transmission of high speed video data and REMOTE SLAVE i REMOTE I C 16 FPD Link III xX X X X Deserializer an embedded a bidirectional control channel referred as BCC concurrently over a single differential link The BCC in terface is 12C compliant according to the 12C standard The BCC interface provides access to programmable functions and registers on the local and remote device s Three types of operations are supported for 12C transactions with the bidi rectional control channel SerDes chipsets local remote and remote slave as shown in Figure 3 Each device can function as an 12C slave proxy or master proxy depending on the 12C mode of operation The SerDes interface acts as a virtual bridge between host controller and the remote device Local operations use standard master to slave operations to the lo cal Serializer or Deserializer Local 12C operations do not require any clock stretching by the slave and do not result in transa
7. each byte by pulling the SDA line low during the 9th clock pulse of SCL ACKs also occur on the bus when data is being transmitted When the master is writing data the slave ACKs after every data byte is successfully received When the master is read ing data the master ACKs after every data byte is received to let the slave know it is ready to receive another data byte When the master wants to stop reading it NACKs after the last data byte and terminates with a stop condition on the bus www national com JOUULYD OAJUOD JEUO HOOIIPIG YUM I XU Add 1940 YOHESIUNWWOD cl CLLC NV AN 2173 DATA OUTPUT BY TRANSMITTER No Acknowledge k Acknowledge Clock Pulse for Acknowledge 30168802 FIGURE 2 Acknowledge On The 12C Bus DATA OUTPUT BY RECEIVER SCL FROM MASTER START or REPEATED START Clock Stretching In general the 1200 master controls the SCL clock line This line provides timing of all transfers on the bus When the mas ter is reading from the slave the slave sends data on the SDA line but it is the master that controls the clock However there are situations where a slave device s is not ready to respond to the master or needs to slow down bus traffic The 12C pro tocol defines a mode for the slave to hold the SCL line Low This mechanism is known as Clock Stretching When the slave receives the write read command from the master it holds the clock line Low During any SCL low period th
8. it 9 FCdelay BCCdelay Data Throughput To Remote 12 Slaves Since the BCC buffers each 12C data byte and regenerates the 12C protocol on the remote side of the link the overall 12C throughput will be reduced The reduction is dependent on the operating frequencies of the local and remote interfaces The local 12C rate is based on the host controller clock rate while the remote rate depends on the settings for the proxy 12C master SCL frequency For purposes of understanding the effects of the BCC on data throughput from a host controller to a remote 12C master the Example of DS90UH925Q 926Q UB925Q UB926Q chipset For the 100 kbit s 100 kHz Host_bit 10us 100 kHz Remote_bit 13 5us default 74 kHz FCdelay 1us max BCCdelay 9us typical value Effective rate 9bits 9046 121us 1us 946 40 6 kbit s TABLE 1 Typical Achievable Bit Rates FPD Link lil SerDes Host I2C rate Remote I2C Rate Net bit rate DS90UH925Q 926Q DS90UB925Q 926Q 100 kbit s 74 kbit s default settings 40 6 kbit s 100 kbit s 100 kbit s 47 4 kbit s 400 kbit s 100 kbit s 73 5 kbit s DS90UB901Q 902Q DS90UB903Q 904Q Since the 12C protocol includes overhead for sending address information as well as START and STOP bits the actual data throughput depends on the size and type of transactions used Use of large bursts to read and write data will result in higher data transfer rates Conclusion This application note provi
9. tance and operating bus speed The 12C bus is a two wire serial interface These wires convey information to and from devices connected to the bus each of which is identified by a unique address Each device can either transmit data or receive data A device can operate as either a master or as a slave depending on whether it gen erates or receives the serial clock SCL A master initiates a data transfer by addressing slave device and generates START and STOP signals The 12C protocol allows for more than two devices to be connected to the bus and for multiple master slave relationships to exist 30168801 FIGURE 1 Example of 120 Bus Acknowledge From Slave Device To communicate with a particular device on the bus the con troller master sends the slave address and listens for a response from the slave This response is referred to as an Acknowledge ACK 1 or No Acknowledge NACK 0 The Acknowledge cycle consists of two signals the acknowl edge clock pulse the master sends with each byte transferred and the acknowledge signal sent by the receiving device All bytes transmitted on the SDA line consists of eight bits of data followed by an Acknowledge bit Each byte transferred effec tively requires 9 bits The ACK bit allows data to be sent in 2011 National Semiconductor Corporation 301688 one direction to one device on the bus and to indicate the data was received A device acknowledges a transfer of
10. the clock stretching will be done for each byte sent by the host controller For remote accesses the Response Delay shown is on the order of 5 10 us and 10 15 us for DS90UH925Q UH926Q UB925Q UB926Q and DS90UB901Q 902Q 903Q 904Q_ respectively The Re sponse Delay includes the latency time of the control channel packing and serialization protocol across the differential link to the remote peripheral The following diagrams Figures 5 6 show the timing relationships of the SCL clock and SDA data signals SLAVE R OFFSET HOST 120 ADDRESS SCL low ADDRESS SCL low gt SLAVE R s aooress w 1 REMOTE 1206 master to slave slave to master OO ADDRESS SCL low DATA SCL ow P OFFSET SCL low ADDRESS S Start A Acknowledge P Stop 30168805 FIGURE 5 Write Format To Remote 12C Slave www national com Z Le NV AN 2173 OFFSET SLAVE SCL low ADDRESS SCL low ADDRESS SLAVE R SLAVE R HOST 12C o L REMOTE 120 SCL low _ gt OFFSET A ADDRESS SCL low DATA1 SCL low DATA2 A P SLAVE ADDRESS DATA1 SCL low DATA2 SCL low S Start Sr Restart A Acknowledge A not acknowledge P Stop pie master to slave slave to master 30168806 FIGURE 6 Combined Format Read From Remote 12C Slave approximate bit rate including latency timings across the con trol channel can be calculated by the following 9 bits Host_bit 9 Remote_b
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