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TLL5000 - Electronic System Design Base Module

1. 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 6 To create a new source click on the New Source button fog New Project Wizard Create New Source i a Figure 5 6 Creating new source file 7 When the new source button is clicked give a file name for the input source code and select the file type from the left hand side list In this example it is a VERILOG HDL module E Xilinx ISE File Edt view Project Source Process Window Help DAAA G A DBX We VIPHKK SP EE R Elere Sources ai No project is open Q AS a MCh A R OO te kbddats owi O Select File gt Open Project FieSNew Project ES New Source Wizard Select Source Type pe IP Coregen amp Architecture Wizard D Schematic lt A State Diagram an Test Bench WaveForm User Document SEK LA Verilog Test Fixture Processes 9 Rg VHDL Module fuaddeny o O No flow available Location TE SXILINSSSS amples funE samples Full_adder E New Project Wizard Create New Source A Add to project Sf Processes x jca lt Beck iee C cme i E Console Eros _g Warnings Tcl Shell l R Find in Files start I RealPlayer Koi Ladki m TLLSOOO_Getting_ St EE Xilinx ISE untitled Paint Figure 5 7 Selecting file type 67 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting
2. e Switch ON the power supply on the TLL5000 with POWER ON OFF Switch e As the power is switched ON the LEDs near the power connector will turn ON e Now use the TLL5000 Hardware Manager utility typically included as a menu Selection in the TLL Design Center software please consult your local TLL partner for specific directions to configure This will bring up the following screen on the monitor EJ TLLS000 Monitor Controler Disconnected Board ID Choose Device J Ethernet Address EEE ELLE Status imnbormation anig eieae Figure 2 2 Hardware Manager 7 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 1 Click on the Choose device option in the step 5 screen options will be displayed as shown below EH TLL5000 Monitor Controler Connected Board ID LL 5000 Development Board Elhemet Choose Derice wider Bypassed Divider Bypassed 1 i JI Jd Staus information Board Powered Down Figure 2 3 Selection of target platform In the options above we shall see TLL5000 Development Board This option will be enabled only by connecting USB cable between TLL5000 base module and PC 8 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide
3. Boundary Scan e Ba Boundary Scan Ba SlaveSerial e Ba SelectMAP e Ba Desktop Configuration Tal Direct SPI Configuration o E SystemACE xcf32p xc9572xl xc3s1500 i E PROM File Formatter file file file H E Assign New Configuration File GaF Menporul iline91 baru_designs91 buffer_sch G C work Ga _ngo ca xst _xmsgs Figure 3 40 Selecting the target device 35 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 51 The Assign New Configuration File is place where the programming file will be browsed to the location and selected by clicking on the Open button But here DO NOT Select or configure the flash device and the CPLD So click on the Bypass button to bypass these components And finally when the FPGA is highlighted select the generated bit file and click Open xcTsa2p xCOSF xl 0321500 bypass bypass file 7 E Assign Hew Configuration File C work La _hga Lal wal _ m g EJ buffer sch bit File name bufter_sch bit Upen File type All Design Files bit rbt nky ise bed Cancel Cancel ll Bypass f None C Enable Programming of SPI Flash Device Attached to this FPGA C Enable Programming of BPI Flash Device Attached to this FPGA Figure 3 41 Selecting the bit file 52 After completing this process the bit file will be selec
4. 1 F MILINM E xCTS2p cos 72x c3 1500 bypass bypass butter sch bt 255 Progress Dialog 744 Executing command Tit 24 Figure 3 45 Downloading the file 56 Once the device is program is downloaded the Program Succeeded message appears 095 72x 03217500 bypass butter sch Program Succeeded Figure 3 46 Viewing status message 38 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Functional Test on the TLL5000 The design downloaded onto the TLL5000 is tested for correct functionality with the use of switches and LEDs available on the target TLL5000 TLL5000 Rev 1 1 se RAN a 2006 mt eee HAA ae jas REV SEL i es alel Age pm Tair TEAR REGAAL He ee ferain paja A Figure 3 47 Observing the outputs As the switches are toggled to ON OFF positions if the design is functioning correctly then the corresponding output LEDs will turn ON OFF to match the switch positions 39 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Chapter 4 Digital Design Using VHDL 1 To invoke the ISE 9 1 tool double click on the below shown icon on your desktop Alling SE 411 Figure 4 1 Invoking XILINX tool 2 Once the tool is invoked the below shown window will open ES Xilinx ISE File Edit View Project Source Process Window Help I
5. BS laveSerial e T2 SelectMAP z TA Desktop Configuration z 2A Direct SFI Configuration i E SystemACE xet32p wc9572x xc3s1500 ien z PROM File Formatter file file file se Assign New Configuration File Look im E F menporul ined test project a ee Ee ER work Jac ibraries Confi m E Sources m SnapsH D Libraries anng Ae wat _ m g File name File type All Design Files mes exo tec bad Cancel Cancel All Bypass f Hone Enable Programming of SPI Flash Device Attached to this FPGA Enable Programming of BPI Flash Device Attached to this FPGA AY Processes Configuration Operations Te 5 1 Design Summary butter_8 whd E Boundary Scan PROGRESS END End Operation Elapsed time 3 Bec if BATCH CHD identifyMPM Console ah i l Tcl Shell F Find in Files Configuration Plattorm Cable USB 6 MHz Figure 4 29 Detecting boundary scan devices 59 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 32 This window is to select the programming file for the CPLD Since we are not going to program that this can also be bypassed EE iling ISE F Amenporulaline 91 test_project test_project ise Boundary Scan File Edit View Project Source Process Operations Output Debug Window Help x DPBS S2SeXSSRPSXRPSSSneyvina Ao le GRA HIS Olle gt jen
6. Figure 3 21 Renaming the markers 23 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 21 Repeat the same for all the ports Save the schematic Next perform a Check Schematic function has to be done This same as check syntax process in the text based design entries Va AaB Check Schematic Figure 3 22 Checking the schematic 22 Observe the No error or warning is detected message in the console window as shown below x otart DRC MHo error orf warning is detected Console Figure 3 23 Observing console window 23 Then dock the floating window by clicking on the Dock Window button Figure 3 24 Docking the window 24 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 24 Then click on the Sources amp Process tabs in the ISE tool window Select the option as Behavioral Simulation in the Sources for window 5 Ailn ISE F nMenporul dines 1 baru designe91 buffe i File Edit View Project Source Process Add Tools Dx ag la g fl oe St St alo ollis ae a Eel avioral Simulation bee buffer ch el 63 xede1 SO0 4ig676 z e buffer ech buffer _ach sch J Libraries Symbols Processes for c31 500 4fg6r6 gt Cl Add Existing Source Ca Create New Source el Saeee Design Utilities i Se Desigt
7. This is the process that merges all the input files and the constraint file into a single netlist Map The process of mapping the logical components to the physical components is known as Map Logical components are nothing but the components that we have as per the design circuit diagram Physical components are the components that are there inside FPGA such as LUTs gates flip flops Place And Route This is the process of configuring the appropriate CLBs amp IOBs inside the FPGA and interconnecting them Also known as PAR 19 To do the implementation process the constraints file has to be given as another input file To create a new user constraint file ucf click on project from the ISE software and select new source Once that is completed the window shown below appears Select implementation constraint file and give the desired file in the file name field Then click on Next Next and Finish E New Source Wizard Select Source Type F BMM File IF Coregen amp Architecture Wizard A Implementation Constraints File File name full adder Location E ARILINANS ample funk samples sFull adder Add to project Figure 5 18 Applying input constraints 79 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 20 The above process will create an ucf file and automa
8. aol elk x b BalBoundary Scan 7 SlaveSerial Bi SelectMAF e TH Desktop Configuration 25 Direct SPI Configuration e E SystemACE t E PROM File Formatter _ megs x File name P a a File type All Design Files jed isc bed Cancel Cancel All Bypass Enable Programming of SPI Flash Device Attached to this FPGA i None Enable Programming of BPI Flash Device Attached to this FPGA ap Processes Configuration Operations S Design Summary h buffer_8 vhd c Boundary Scan x PROGRESS END End Operation al Elapsed time 3 sec ff BATCH CMD identifyMPM Console a Find in Files Configuration Platform Cable USB 6 MHz usb ls Figure 4 30 Selecting programming file 60 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 33 The third window is for the FPGA Please ensure that the FPGA is selected by being highlighted Then select the appropriate bit file and click on Open E Alling ISE F menporuA ilink Mtest_projecthtest_ project ise Boundary Scan E File Edit View Project Source Process Operations Output Debug Window Help IDPRSISIZSEXBSlDIPOEXXPAIAISETS FPM Kal amp zS Ee eree a legzuu g lasan ol TH Boundary Scan ADS laved erial e FA SelectMAP e Ta Desktop Configuration F Direct SPI Configuration e E System ACE i E PROM File Formatte
9. as Generate Programming File EM Stap Open without Updating HY Processes 22 Options at Properties x Started Launching Design Surmary Figure 3 36 Implementing design 45 During the project design of a digital system each process can be found in some of the following states Running the process is in the running phase Up to date Process is successfully executed without mistakes or warnings If the rapport is in this condition it means that it s up to date although it could happen that the tasks covered with this process have mistakes and warnings E Warnings reported the process is successfully executed but there are warnings Errors reported the process is finished with at least one error Out of Date signifies that there have been made some changes and that the process needs to be done again No icon In the case of there is no any of these icons the process hasn t been started 32 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 46 After the design implementation process is complete the programming file needs to be created to download into the FPGA to correctly configure it To generate the programming file run the process called Generate Programming File from the Process for window E Alling ISE F 4MenporulxilingS1 baru designz91ibulfer_schibuf le File Edit View Project Source Process Add Tools Window j
10. baru_designs91 bulf 3 File Edit View Project Source Process Add Tools jDe aad 1 New Source Add Source 1 abe aa dd Copy of Source Sources for Synthesis Cleanup Project Files 7 buffer_sch Toggle Paths E ga xc3e1 500 4fo6 a Archive a buffers Take Snapshot Make Snapshot Gurrent Goply Project Properties Source Cantral p Figure 3 31 Creating a new source for constraints file 35 Once the new source is selected the New Source Wizard window gets opened Here enter the file name and select the input file type as Implementation Constraints File and click on Next E Hew Source Wizard Select Source Type J IF Coregen amp Architecture Wizard MEM File Schematic P Implementation Constraints File gt State Diagram File name Test Bench WaveForm buwis OOOO O O User Document e Yerlog Module Location ahl Verlog Test Fisture ual VHDL Module FM enporahssilins g Sbaru designe butfer sch Pe WHOL Library P HDL Package w WHOL Test Bench W Add to project More Info lt Back ne Cancel Figure 3 32 Synthesizing the design 36 When the next button is clicked the Associate Source window gets opened Here select the appropriate entity file name If only one file is added to the project then by default the same is selected If more than one number files are there only then we need to select the file entity name 29
11. 4 a Xilinx PACE E XILINX SampleVfunExamples Full_adderVfull_adder ucf File Edit View IOBs Areas Tools Window Help JD eA Slole AU Eh eee S 4liaemeao KRaaran DOEEBO 8 Design Browser Bi x E Device Architecture for xc3s1500 4 fp676 10 Pins i E Global Logic i Logic als 170 Std i data input sw Input Y3 BANK LVCMOS3 M A _ Unknown cary in sw 3 Input 10 BANK LYCMOSS Unknown E eum output le Output AE ANE CVCMOSS N T2 kd Trknown OP cany_out_led_ Output JABS BANK LVCMUS3 N A 12 SLOW Unknown data _input_sw Input vs E j l y r 3 BANK LVCMOS3 M A Unknown Figure 5 20 Applying pin numbers 22 After entering the pin numbers in the LOC field save the file and exit the PACE tool Then in the Sources for window in ISE select the V file and run the Generating Programming File process This process will generate the bit file which can be downloaded onto the FPGA 81 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 This process will run all the other processes that are there before the generation of the programming file An individual process may also be run separately ES Xilinx ISE E IXILIHNHX Y Sam plefunExamplesi Fie Edit View Projeck Source Process Window He FD PAG SBtXk a BM Ma L SE af wl we Tat set SoS Ore E SoWces S Full adder S gA 40321 500 4fg676 E v ull a
12. Figure 3 25 Selecting the simulation option 25 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 25 By selecting the input file name in the Sources for window expand the ModelSim Simulator window from the Process for window and run the process called Simulate Behavioral Model This will invoke the simulator that we use to simulate the design Here ModelSim XE 6 2c is the simulator used i ModelSim XE III Starter 6 2c Custom Xilinx Yersion File Edit View Compile Simulate Add Wave Tools Layout Window Help wave default buffer ind buffer ing buffer ins buffer ind buffer ind buffer in buffer in L buffer ing LI buffer out Object Declaration Lefer E View Assertion EAE Cover Directive View buffer outd buffer_out bufferout6 buffer_out Cut buffer_oute Copy Paste bufferech Architecture buffer ini butbut Architecture buffer ine whe butbut Architecture buffer ins wl butbut Architecture buffer_ind mle 4 butbut Architecture buffer ino wh 5 butbut Architecture butter _inE wh 6 butbut Architecture buffer ini le butbut Architecture buffering wh butbut Architecture buffer_out yoomponents yoomponents Package bufferoute numeric_std numenc_std Package butter outs std_logic_1164 std logic_1 Package bufferoutd standard standard Package buffer_out6 bufferout6 bufferout Radix Format buffer
13. File gt Open Project or Enter a Mame and Location for the Project File gt Mer Project ORE POS Sa Project hare Project Lacation best_project F menporul gt lt ilins 31 Whesk_project KEA Select the Type of Top Level Source for the Project Ens Sources Top Level Source Type HEL m No flow available ap Processes More Info Back Cancel Figure 4 4 Entering project name 41 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 5 Let the Top Level Source Type be as HDL itself After giving the necessary inputs and clicking on Next the next window appears This is the place where the target hardware amp necessary tools are selected Key in the inputs as per the requirements Then click on Next EE New Project Wizard Device Properties Select the Device and Design Flow for the Project Property Name Product Categon Fami Device A Speed Il Top Level Source Type Synthesis Tool SST MHOLSYerilog Simulator ModelSim XE VHDL HOL z Preferred Language VHOL ial More Info lt Back Cancel Figure 4 5 Selecting target hardware Note 1 The Simulator Chosen ModelSim xXE Synthesis Tool XST this is the built in Webpack ISE Note 2 The device Package and speed are chosen based on the details of an FPGA chip on the TLL5000 XC381500 4fg676 XC Xilinx Component 3S Device Family in th
14. Ir Libraries Processes for tull _adder_ tb Add Existing Source Create Mew Source View Generated Test Bench 4s HOL Add Test Bench To Project Figure 5 16f Simulating the design g ES Xilinx ISE E XILINX Sample funExamples Full_adder Full_adder ise Simulation Sel File Edit View Project Source Process Test Bench Simulation Window Help EF X DAA Sif Bx OS YEP PKKS BAIS BOD SAK R EOD A e kbd cata vl Q Ega tetdi OOO ZIEL AAYAN EEA ACA OI E h o c Sources 941 6 Sources for Behavioral Simulatic eins oy tare nee 200 600 1000 5 Full_adder 1 1 1 lt gt 3 xc3s1500 4fg676 T acon EEE oO Carry_Ou full_adder_tbw full_add fula e1_tbw ful_adde oll sum_outp oll Carry_in ao o oll data_inp oll data_inp lt gt BIg Source pss Snapsh D Librarie Hierarchy of full_adder_tbw ia ful_adder_tbw full_adder_ lt gt lt gt full_ adder v Design Summary Gy full adder_tbw tbw fy Simulation lt Gt Processes E Sim Hierarchy Figure 5 16g Waveform after Simulation 77 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Synthesis of the Design 17 The next step after simulation is to synthesize the design Synthesis is the process which will generate the gate level netlist of the design In order to run the synthesis process the selection has to be
15. Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 TLL5000 Interfaces and Peripherals Audio Out Out PS2 Key Board PS2Mouse Mouse Ethemet amp USB Er MIC In S Video In NTSC PALIn NTSC PALOUT Figure 2 9 Various interfaces in TLL5000 13 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Chapter 3 Digital Design using Xilinx ISE In this section we will introduce the steps needed to create a digital design with the schematic entry method of circuit design Schematic entry is often a starting step in learning digital design prior to the Hardware Description Language approach to digital design but can also be used concurrently with HDL approaches when a block diagram or circuit view is the most natural method of specifying the design Now let us start with a basic design 1 Run the ISE application by double clicking on the shortcut icon for the ISE tool or selecting it from your Programs menu Figure 3 1 Invoking Xilinx ISE 2 When the tool is invoked the following windows will appear in the ISE tool File Edit View Project Source Process window Help IODRPaSe Sse exloe DIPSXXS BIASES TSA lows ale le g E Sea aa No project is open File gt Open Project File gt New Project No flow available Figure 3 2 XILINX welcome screen 14 Copyright 2008 The Learning Labs Inc
16. Source Wizard Select Source Type Fa BMM File J IP Coregen amp Architecture Wizard File name ful adder tbid Location EAXILINSAS amplesfunE xamples Full_adder P VHDL Package Maal WHOL Test Bench Add to project Figure 5 16a Create a Test bench file 74 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 b Click Next and ensure that you have added the file in the current project folder and also the right Verilog file is associated with it ES New Source Wizard Summary Project Navigator wall create a new skeleton source with the Following specifications Add to Project Yes Source Director E SSILINSSS ampleMtunE samples Full_ adder Source Type Test Bench VfaveForm Source Mame full adder thy thy Association Full adder Figure 5 16b Test bench file added to the current project directory c Now choose the type of clock Since we are implementing a combinational circuit we will choose combinational clock The frequency is set internally ES Initial Timing and Clock Wizard Initialize Timing Assign Check Assign Inputs Outputs Inputs Wait To Wait To check TA Assign Clock Timing Information Clack Information Single Clock Inputs are assigned at Input Setup Time and outputs are checke
17. Started Guide Ver3 4 8 After giving the file name amp file type the input and output port list of the design has to be given Port list is the top level entity of the design After giving the port names the directions of the ports can also be entered as per the design requirement If the port is a type of bus that can also be entered along with the number of bits specifying the width of the bus Xilinx ISE File Edit View Project Source Process Window Help ORBEA S 48BX Se MEPHPHKS BASHA ODA NEM kbd daa wli O fe Sheba wt Sources x No project is open Select File gt O pen Project 158 New Project Wizard Create New Source or are File gt New Project tee New Source Wizard Define Module Port Name Direction data_input_sw_1 input OG e n data_input_sw_2 input Big Sources g Snapshots P Librarie or F i a cary_in_sw_3 input Processes sum_output_led_1 output No flow available carty_out_led_2 joooocon0og ap Processes Figure 5 8 Enter the port list Note The Port names to be entered in the above window shall also be 1 bit for typical logical gate implementations 68 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 9 After giving those details click on Next amp Finish ES Xilinx ISE File Edit View Project Source Process Window Help OPA S548 BX be MEPHPHKKHS BASSES OMAN a kbd data
18. System Design Base Module Getting Started Guide Ver3 4 This process will run all the other processes that are there before the generation of the programming file An individual process may also be run separately ES Xilinx ISE F ymenporu Ailin test_project test_ pro Wd File Edit view Project Source Process Window H IO e Hg lla hx aaj 4 lee alee ser s S Olle Hels x 15 Sources for Synthesise l mplementation 16 17 p tesh_ project 16 G EA xe3s1 500 4fg676 19 le hese buffer Behavioral buffer _8 hd a0 h Pod buffer_S uck buffer8 uctl 21 2a ao a 4 25 2 6 a gt Libraries 20 ao 30 oul 32 Gas Create New Source 34 Add E sisting Source View Design Summary a5 Design Utilities a5 User Constraints a7 Sunthesize HST ciz 39 40 Implement Design Generate Progran Rerun at Processes Rerun All x Stop Started Open Without Updating Properties Figure 4 26 Generating bit file 57 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Programming TLL5000 29 After completing Generating Programming File process expand Generating Programming File process tab in the Process for window and run Configure Device IMPACT process When this process is executed the target board has to be connected with the appropriate cable connections Processes for buffer Behavioral AF
19. TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 3 Now a new project has to be created To create a new project click on the File menu and select New Project option ES Xilinx ISE File Edit Wiew Project Sou Mew Project Open Project pen Example Glose Project Save Project as New Ctrl h Open Ctrl a Close Ctrl 5 Dave AS Save 41 Print Preview Print Ctrl P Recent Files Figure 3 3 Creating a new project 4 When the new project option is selected the following window is seen In this window type a project name buffer_sch and specify a location Select Schematic as the Top Level Source Type And click Next E Hew Project Wizard Create Hew Project Enter a Name and Location for the Project Project Marne Project Location FAMenporulysiling 1 Sbaru_designe1 Sbuffersch l Select the Type of Top Level Source for the Project Top Level Source Type SB Schomie 2 More Info lt Back Cancel Figure 3 4 Entering the project name 15 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 5 After these inputs the tool will go to the next window Here select the target device and the tools that will be used in developing the design Then click Next Es Hew Project Wizard Device Properties Select the Device and Design Flow for the Project Pro
20. a Console Eros Warnings Tcl Shell iga Find in Files a RealPlayer Jadoo m TLLSOOO_Getting_St ES Xilinx ISE E XILIN S untitled Paint Figure 5 16d Set the inputs e From the Sources menu choose Behavior modeling option ES Xilinx ISE E XILINX Sample ViunExamples Full_adder Full_adder ise bA Y Fie Edit View Project Source Process Test Bench Simulation Window Help DAA Gt4 RBX ma M S PKAA RAL E E el W hoh ma L ELJAR Sure es Sources for Synthesis Implementation End Time S Full Synthesise plementation 1000 ns El Y Behavioral Simulation Serre E i Post Floute Simulation AM data_inp AN data_inp U cary in AN surn_outp AN carry_ou wae les napshote P Libraries Processes for c31 500 4fg6 76 P Add Existing Source h O Create New Source SF Design Utilities Figure 5 16e Behavior modeling 76 Copyright 2008 The Learning Labs In TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 f Choose the appropriate file for simulating In the process menu choose Xilinx ISE Simulator and run the simulation ES Xilinx ISE EAXILINX Sample funExamples Fu File Edit View Project Source Process Test Bench Sirm DPA Gt4eaex wae N SE ff wel stl eG Qed gt Sources for Behavioral Simulation S Full adder E gd eos Shiratgb 6 A full_ad er tow full adder_tbyy tb BRS Sources pa Snapshots
21. i O tee BAA Sources x No project is open Select ex ks New P ct Wi Jow S File gt Open Project iw New Project Wizard Create New Source or p File gt New Project tes New Source Wizard Summary Sousel E E XILINX S ample fun xamples Fulladder Source Type Verilog Module BZ Sources pu Snapshots Py Librariey Source Name full_adder v Module Name full_adder Processes Pott Defi iti No flow available data_input_sw_ 1 ap Processes Cer Figure 5 9 File summary 69 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 10 After clicking on Next the tool will ask for the confirmation of creating a new folder Simply Yes can be clicked This will create a folder named as the project name in the specified location And based on the information that is given a skeleton of the VERILOG HDL file is created which will have all the declaration parts of the file This is common for all the VERILOG HDL files E Xilinx ISE File Edit wiew Project Source Process Window Help DAHA SiXX Ba YEP PX KS BABS OHA sO Mlkeddte vl fee Beha st Sources x No project is open a E New Project Wizard Create New Source o r n File gt New Project tas New Source Wizard Summary Add to Project Yes n l Source Directory E XILIN S ample funE xamples Full_adder Source Type Verilog Module E Sources es Snapshots f Librarie Source Nam
22. outs Delete Insert Divider Insert Breakpoint Force NoForce Clock qi Library l sim Files E Memories alae aes Figure 3 26 Forcing the input signals 26 Force the selected input signals with the desired values and click on OK Ra Selected Signal Signal Mame sim buffer_sch buffer_int Value hl Kind f Freeze Drive Deposit Delay For lo Cancel After Figure 3 27 Docking the window 26 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 27 Then click on Run button in order to view the simulated results GHEY Ek P T x Rurilts Figure 3 28 Run simulation 28 The simulated results can be seen in the wave form window The vertical yellow bar is the cursor Wherever the cursor is placed the corresponding values will be displayed in the wave window as marked in the below shown figure Different inputs can be applied and the output can be viewed accordingly Once the satisfied output is got the simulator may be quitted buffer_in buffer ine buffer iri buther_ind buther ind buffer inb butter in buffering buffer_out buffer out buffer outs buffer outd buffer outt buffer outh buther_outy bufher outs Figure 3 29 Viewing the simulated output 29 The next step in the FPGA design flow is to synthesize the design Synthesis is the process that generates the equivalent gate l
23. the TLL5000 LEDs and Switches FE Xilinx PACE F menporul Xilinx 91 test_project buffer_8 uct File Edit View IOBs Areas Tools Window Help Design Browser AIl ig Package Pins for xc3s1500 4 fq676 l H IO Fins 9 Global Logic Logic Tap iew 1 2 3945 G6 7 8 8 WH 1 dd 15 16 17 1 18 a eo Md a DETE eee ee i Ce E ee ee ete jes BS ILRI A tettetttontet Design Object List 1 0 Pins 170 Name 170 Direction Loc Bank 170 Std _ asde Input YB BANKS O act aput YS BANKS O o ase o apt FTO BANKS O i O a3 o Input VT BANKS O o O ashe o lapat o 12 BANKS O ae o apt o wit BANKS O o ase o input wie BANKS ae o Input WIS BANKS bes Output JAB BANKS bel Output ABe BANKS b Output AB9 BANKS o be3s Output JAAS jJ BANKS o b d gt Output AATO YF BANKS o be5p Output AATT BANKS o be Mu eet Re Gt ii E EE Hei r ere TPR REET EE EEEE E a a i zE raer DnmMmo DAF EBEE esz gdacdanono zE razer nmo DAY 1234s grann i2 13 i 15 16 0 18 19 2 2 2 A ya OO Figure 4 25 Applying pin numbers 28 After entering the pin numbers in the LOC field save the file and exit the PACE tool Then in the Sources for window in ISE select the VHD file and run the Generating Programming File process This process will generate the bit file which can be downloaded onto the FPGA 56 Copyright 2008 The Learning Labs Inc TLL5000 Electronic
24. the project tt optional Only one new source can be created with the Mew Project Wizard Additional sources can be created and added to the project by using the Project gt New Source command Existing sources can be added on the next page More Info Back Cancel Figure 4 11 Creating new source 12 Since a new project is being created it is not required to add any existing source at this point of time So click on Next E Hew Project Wizard Add Existing Sources Add Existing Sources _ese aE ee Add Source en ee Adding existing sources is optional Additional sources can be added atter the project is created using the Project Add Source or Project4 dd Copy of Source commande More Info lt Back Cancel Figure 4 12 Adding existing file if any 46 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 13 The summary is created based on the information that is given so far Now click on Finish se New Project Wizard Project Summary Project Navigator will create a new project with the following specifications Project Project Name test project Project Path F menporul Xilinx91 test_project Top Level Source Type HDL Device Device Family Spartan Device xe3s1500 Package fq676 Speed 4 Synthesis Tool XST VHDL Verilog Simulator Modelsim SE VHDL Preferred Language VHDL Enhanc
25. there inside FPGA such as LUTs gates flip flops Place And Route This is the process of configuring the appropriate CLBs amp IOBs inside the FPGA and interconnecting them Also known as PAR 25 To do the implementation process the constraints file has to be given as another input file To create a new user constraint file ucf click on project from the ISE software and select new source Once that is completed the window shown below appears Select implementation constraint file and give the desired file in the file name field Then click on Next Next and Finish New Source Wizard Select Source Type J IP Coregen amp Architecture Wizard Schematic Implementation Constraints File State Diagram File name Test Bench waveform butter User Document Werlog Module Location Ab Verilog Test Fixture 7 rh VHDL Module F menporulxilinaS1 Shest project a y YHDOL Library P VHDL Package W VHDL Test Bench W Add to project More Info lt Back Cancel Figure 4 23 Applying input constraints 54 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 26 The above process will create an ucf file and automatically add it to the project By selecting the ucf file in sources for window Run Assign Package Pins process from Processes for window The details of the pin locations are for switches and LEDs availab
26. 1 5SO0 4fg676 EI DE butter sch buffer sch sch ha Pra buffer sch uct buffer sch uct Wesign UTMEs a Sp User Constraints H Pa f Sunthesize ST H PE lmplement Design PE Generate Programming File i Biv Programming File Generation Report EB Generate PROM ACE or JTAG File Configure Device iMPAgaie 4 af Processes 2 Options Options enun St Rerun ll x Process Configure eh stop Open Without Updating HP Properties Figure 3 38 Configuring the target device 48 Before running the process Generate Programming File right click on Generate Programming File and select Properties In the properties window select the start up Options and set the value as J TAG Clock in order to avoid the warning messages in the future 34 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 49 This opens another software tool called iMPACT Click on Finish button in this window E IMPACT Welcome to IMPACT E Automatically connect to a cable and identify Boundary Scan chain Figure 3 39 Checking for boundary scan devices 50 This process detects three different devices that are present on TLL5000 target The xcf32p is the flash device xc9572 is the CPLD device and xc3s1500 is the FPGA device E Xilinx ISE F Menporul Xilins91 baru_designs91 buffer_sch buffer_sch_ise
27. 31 Col 47 CAPS NUM SCRL Verilog RealPlayer Chaaye E TLLSOOO_Getting_St FES Xilinx ISE E ILIN S untitled Paint Qi 7a T 11 04 am Figure 5 14 Tool generated Verilog HDL file In the above code the functionality for Sum and Cary out are written 14 As per the design flow after design entry the 1 step is to simulate So to simulate the Simulation option has to be selected The steps for selecting it is shown in figure 5 15 73 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Behavioral Simulation of the Design 15 When the design is ready choose the Behavioral Simulation option This option is available on your top left hand corner of your ISE near Sources for Xilinx ISE F imenporulhilinsgS 1 test_project ttest_projyect_ise fa File Edit View Project Source Process Window Help Sources for Synthesis Implementation fo test Synthesis mplementation Behavioral Simulation L Post Translate Simulation Post Map Simulation Post A oute Simulation E Sources pa Snapshots Libraries Processes for buffer _S Behavioral Add Eststing Source Create New Source Wiew Design Summary Design Utilities User Constraints Figure 5 15 Selecting simulate operation 16 Now we will create a Test bench for testing the functionality of a full adder a We will create a Test bench Waveform file ES New
28. A Architecture View Figure 3 35 Assigning pin numbers 40 To give the pin constraints select the ucf file and expand the User Constraints in the Process for window and run the process Assign Package Pins This will invoke another XILINX built in tool called PACE Pinout Area Constraint Editor 41 Enter the pin numbers where the inputs and the outputs are supposed to be connected The details of these pin numbers may be found in the user manual 42 After entering the pin numbers the save the file and PACE tool may be exited 43 Then again select the design file in the Sources for window 31 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 44 The next step is to run the implementation process So right click on the Implement Design process and select Run from the pop up menu 5 Alling ISE F Menporulalins91 baru_designs91 buffer_schibulte fe File Edit View Project Source Process Add Tools Window alla BEM oe i cr OCC Be Ot JO Olly aye ww Fe Sources for Synthesis implementaton hae eee eS aos m fal buffer sch El Eg xc3s1 500 4fg676 ar ele buffer ech buffer sch sch ha Peg bufter_sch uct buffer sch uct EIS Sources fos Processes for buffersch ee Design Wtntes H ap User Constraints H CO Synthesize XST A Implement Design fF Translate OQ Map Rerun GP Place amp Route AY Rerun All
29. All Bypass gt None ag Processes Configuration Operations at gt Enable Programming of SPI Flash Device Attached to this FPG Enable Programming of BPI Flash Device Attached to this FPGA Figure 5 26 Selecting bit file 28 Now it can be observed that the FPGA is selected with the given bit file EE Xilinx ISE E XILINX Sample funExamples Full_adder Full_adder ise Boundary Scan Lok D File Edit View Project Source Process Operations Output Debug Window Help OHO 5 XRGX wa OPPAK B AE TANA T EET TEEN PE E r 30 oN Sources xij E pelBoundayy Scan SS SlaveSenal pgbelectMaP l a P Progam aA Desktop Configuration g po Verify BA Direct SPI Configuration ner on Get Device ID i 3 SysenACE vefa CISTA yeasts Get Device Signature Lsercode E PROM Fie Formater bores Nie fil ee ia Assign New Configuration File Figure 5 27 Programming selection 86 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Right click on the FPGA that is xc3s1500 and select program from the pop up menu Then the below shown window appears Click on OK in this window This will download the bit file onto the target device E Programming Properties Be Programming Properties Advanced PROM Frogramming Properties jn Revision Properties D Erase Before Programming Read Protect PROM CoolRunner Usercode 8
30. Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 37 Select the file entity name and click on Next E New Source Wizard Associate Source Select a source with which to associate the new source buffer sch More Info lt Back Cancel Figure 3 33 Selecting an associated source 38 Then again click on the Finish button If any changes are to be made click on Back and make the required changes E Hew Source Wizard Summary IOL ES Project Navigator will create a new skeleton source with the following specications Add to Project Yes Source Director F AMenpormhsihned baru designs91 Souter sch Source Type Implementation Constraints File Source Name butter ech uct Association buffer ach Figure 3 34 File summary 30 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 39 When this is completed the ucf file is created and added to the project To check this click on the sign beside the input file name in the Sources for window In this example design the pin constraints will be in the ucf E Xilinx PACE F Menporul Xilinx91 baru_designs91 buffer_sch buffer_sch ucf File Edit View IOBs Areas Tools Window Help Nik ee Input Input Input Input Output Output Output Output Package View
31. Design Utilities m ae User Constraints H PE Synthesize XST i PE Implement Design EI PE Generate Programing File j Biv Frogramming File Generation Report Gb Generate PROM ACE or JTAG File af Processes at Rerun All X Started Laji Stop Open Without Updating ap Properties Started Lav Figure 4 27 Configuring the target platform 30 Once the Configure Device IMPACT process is run the below shown below appears In this window just click on Finish E iMPACT Welcome to IMPACT Please select an action from the list below f Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File C Configure devices using Slave Serial mode Figure 4 28 Welcome screen of iMPACT 58 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 31 Once the Finish is clicked the IMPACT tool will detect the boundary scan devices on the target TLL5000 Here xcf32p is a flash prom amp xc9572 is a CPLD These devices will NOT be programmed Click Bypass on the following window ao Sean eee Jal y Sca au p File Edit View Project Source Process Boneh Output Debug Window Help Dono Gixeex ae BIP PXA ee A li a SXae Xoo BERE al Boundary Scan
32. Hex Digits F write Protect D Functional Test F OrnTheFi Pragam APLS UES Enter up tola characters Figure 5 28 Viewing programming properties 87 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 29 Once programming is successfully completed the Program Succeeded message appears as shown in the given figure ES Xilinx ISE E XXILINX Sample funExamples Full_adder Full_adder ise Boundary Scan Sle D File Edit View Project Source Process Operations Output Debug Window Help DARE SiXRRX Oe MIP HX SP BABA OMAN EM Mlmkeddt HR eA BRACA OO css K an i sao ce x E S8 Boundary Scan Sal SlaveSerial Ba SelectMAP S8 Desktop Configuration 23 Direct SPI Configuration SystemACE xc9572xl xc3s1500 B PROM File Formatter bypass full_adder bit Bg Sources ga Snapsk f Libraries Configuration M Get Device ID E Get Device Signature Usercode A Pr tis am SUC COG de d Check Idcode m O mm T mha aan re oes z aN af p Configuration Operations 2f Processes etme E Design Summary W Boundary Scan Figure 5 34 Programming status 88 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Functional Test on the TLL5000 30 The design downloaded onto the TLL5000 is tested for correct functionality with the use of switches and LEDs availa
33. OP RES SGIZEBEX Sal PIPSXXSPIPIAIS Ee m al Rw a R IE g a Ot ot ot or No project is open Select File gt Open Project or File gt New Project EIS Sources pe Snapshots I No flow available ay Processes ka Find in Files Figure 4 2 Tool welcome screen 40 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 3 To start a new project click on File tab and select New Project The same is shown in the below figure 4 3 FES Xilinx ISE File Edit View Project Source Process Window Help Mew Project Il PH Open Project E Open Example z lose Project Save Project 4s J New Ctrl h fe Open Ctrl o Close EA Save ft s Save OS Ep Save All Print Preview i Pring Ctrl F h Recent Files Recent Projects Exit Figure 4 3 Creating new project 4 When New Project is selected a new window is opened as shown in the figure In the Project Name field enter the desired project name Now it can be observed that a folder is created with the same name in the Project Location field This is for keeping track of all the input amp output files in the same location ISE File Edit Wiew Project Source Process Window Help DPA ea Silks a ex aae B Sexx 2 BAS 6 mn jA le g a amp Ot et 2k or Ho project is open Select FES New Project Wizard Create New Project
34. RAM or greater is useful Minimum 5 GB on Hard Disk The Webpack ISE requires around 3 5 GB for all its components DVD Drive SVGA Monitor with the resolution of 1024x768 Monitor resolutions has been kept at 1024x768 which is ideal e Windows 2000 or XP operating system with ServicePack 4 for Windows 2000 amp ServicePack 2 for WinXP e Three USB2 0 ports e One RS232 serial port e Ethernet Network Interface Card NIC The network interface card should have been configured on your system Make sure that you have configured the network card with a static IP address Software requirements The following software needs to be installed in the PC used for connecting to the TLL5000 Base Module e Xilinx Webpack ISE 9 x 10 x our limited experience is that the Xilinx ISE version 8 x should also work but we recommend that you use version 9 x If you are using the previous versions of ISE please update with the service packs for getting the drivers for the Xilinx Programming Cable This tool is provided with ISE simulator XST synthesizer PAR and downloads iMPACT applications e ModelSim XE the Simulation software for behavioral simulation One should also be able to do these exercises using the full ModelSim software from Mentor Graphics but there will be differences in methods and commands that this manual does not address Hardware requirements The following items are required to start using the system TLL5000 Base Modul
35. TLL5000 Electronic System Design Base Module Getting Started Guide Ver 3 4 TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 COPYRIGHT NOTICE The Learning Labs Inc TLL All rights reserved 2008 Reproduction in any form without permission is prohibited Disclaimer Information in this document is subject to change without notice and does not represent a commitment on the part of TLL TLL provides this document as is without warranty of any kind expressed or implied including but not limited to the particular purpose TLL may make improvements and or changes in this manual or in the products s and or the program s described in this manual at any time Information in this manual is intended to be accurate and reliable However TLL assumes no responsibility for its use or for any infringements of rights of other parties which may result from its use This document could include technical or typographical errors Changes are periodically made to the information herein these changes may be incorporated in new editions of the publication This manual is provided solely and exclusively for educational use and this information or related products should not be used nor relied upon for any purpose except for education and training Technical Support Please contact your local TLL authorized product representative for questions regarding hardware software or applications issues Any updates or
36. UU D Signal Marne kim buffer_8 a Value ar 010101 Kind Freeze Dive Deposit Delay For fo Cancel After D ps to 2050 ps Figure 4 19 Forcing the input signals 21 After forcing the input signal click on the run button The shortcut to the run button is encircled in red color in the below shown figure wave default File Edit Wiew Insert Format Tools Window sma BArik Raak Ee buffe 8ra UUUUUUUU O E buffe 8b UU O Figure 4 20 Run simulation 52 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 22 Once the simulation is run the output for the given input can be observed in the wave window This is Known as functional simulation in which only the software code is simulated prior to the design being implemented directly on the hardware wave default File Edit Wiew Insert Format Tools Window Gd S Se da i Alea A QA SHH E7 ELE eres butter oy 01010101 101010101 buffer 8b 01010101 foo Figure 4 21 Viewing the simulated waveform Synthesis of the Design 23 The next step after simulation is to synthesize the design Synthesis is the process which will generate the gate level netlist of the design In order to run the synthesis process the selection has to be changed as Synthesis I mplementation in the sources for window This netlist output file will be the input file for the imple
37. Ver3 4 2 Now click on the TLL5000 Development Board option in Step 6 The following screen appears on PC FH TLL5000 Monitor Controler Connected Board ID LL 5000 Development Board Ethemet Address Pigwer Yalures 4 citer Bead Td Pr ites Head Py ol ee Sh eee 00000 MHz sed Divider Bypassed Hoea a SGT UN one Me a i lerrante fy ji Th on cy I GET Bup sad eee H eranne amp NO OOO HHz Wegesiine G IORI MH for JE Dider bypassed WPSraihe S WOOO aH y i E Liter bypassed ILOORO MHz Dis Divider Bynacsed i Status inhoomation hoe von Board er Down Pead Wre Figure 2 4 Checking platform status e At this stage the screen displays the status as Board Powered Down see the Status information marked in blue in the above screen This means the platform is not powered up Once the Power ON button is clicked then the platform will get powered up e The power supplies for the various TLL5000 elements FPGA memories peripherals etc are started by clicking on POWER marked in the red color in the above screen Now the power supply is enabled for all the parts of the board and the screen is shown as below 9 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 3 The above screen provides monitoring of the TLL5000 onboard power supplies and configuration of the var
38. ble on the target TLL5000 M IL TLL5000 R copyright 2 H ole s Carry_output_led_2 ia i Sum_output_led_1 Data_input_sw_1 et Data_input_sw_2 Carry_in_sw_3 Figure 5 35 Observing outputs As the switches are toggled to ON OFF positions if the design is functioning correctly then the corresponding output LEDs will indicate the Sum and Carry bits END 89 Copyright 2008 The Learning Labs Inc
39. changed as Synthesis I mplementation in the sources for window This netlist output file will be the input file for the implementation process ES Xilinx ISE E XILINXampleVunExamples Full_adde iv File Edit View Project Source Process Test Bench Simulation DAA G 4 8Bx we NAE Ea a wit 2 xt he GO Ed gt FOUC al ra ae Ahula adder full adder EZ Sources fal Snapshots Libraries Processes for full adder 22 View Design summary 19 D Utilities BR aE p Rerun All FER Stop f Processes Open Without Updating This is v4 Properties SE Simulator Ea WARMING ftilitiesc I He ssace file Simul Figure 17 Selecting synthesis option The progress of the Synthesis process will be shown in the console of the ISE Left down corner In case of any errors the details of the errors will be displayed With any type of error the design will not proceed to the Implementation stage The synthesis generates the synthesis report RTL schematic Technology Schematics The user should verify these reports in order to understand the actual logical circuitry that will be configured in the FPGA 78 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Implementation of the Design 18 The implementation process has three different sub processes in it They are Translate Map and the third is Place amp Route Translate
40. d Existing Source Create New Source Wiew Design Summary Design Utilities User Constraints Figure 4 15 Selecting simulate operation 48 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 17 Then select the VHDL file in the source for window and run the Simulate Behavioral Model Function To run any process select the appropriate process and press enter or double click the process or right click on the process and select run option from the pop up menu FES Xilinx ISE F imenporul AilingS1 test_proyectt test_project ise butte File Edit Wiew Project Source Process Window Help SZABXxleaa l VP Pmys i at 4 EOE Or St IS Olle gt Reyision Sources for Behavioral Simulation Revision fddition p 3 test_project A E3 xc3s1500 4fg676 Pho buffer_8 Behavioral buffer _8 vhd ibrary TRE use IEEE ST use IEEE ST use IEEE ST Unecorn any Xi library U Ere Sources pe Snapshots gt Libraries use UNISI entity buff Processes for buffer_ Behavioral Port j E Add Existing Source P Create New Source Ee Sy MModelSim Simulator architectur ST Simulate Behavioral Model end buffer _ Rerun aL Rerun All at Stop Open Without Updating ae Processes aL Properties Figure 4 16 Simulating the design 49 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System D
41. d at Output valid Delay Multiple Clack Rising Edge Falling Edge Multiple Clocks Dual Edge DDR or DET Combinatorial or internal clack Clock High Time 20 Combinatorial Timing Information Figure 5 16c Chose the internal clock 75 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 d Set the inputs as shown below ES Xilinx ISE E XILINX Samptle VfunExamplestFull_addertFull_adder ise full_adder_tbw tbw fe e If x Fie Edit View Project Source Process Test Bench Simulation Window Help FO PREA Gta See wa Hi 2fPx a ls Se BS O Ch se RP 2 OO aa kbd data 2 A 3 N A eer EO O I Ge D gt 1000 ivns Fl Be Tt ECEE eE for Synthesis Implementation re Full_adder gA xc3s1500 4fg676 AN data_inp nm I ME ful adder Full_adder an data_inp AN carry_in AN sum_outp AN carry_ou Sources lex Snapshots Py Libraries Hierarchy of full_adder_tbw ul adder lt Li gt Sf Processes E Hierarchy full_ad N s u es full_adder v 5 Design Summary E full_adder_tbvy tbyu Started Launching Design Summary Sterted Creating Dar tiie Compiling werilog file E xXILINZX Sample funExamples Full add er full adder w Started Creating Thw file Compiling werilog file E xXILINZX Sample funExamples Full adder full adder w G lt
42. dder full_adder E Sources Pe Snapshots Py Libraries Processes far full _adder i foa Add Existing Source Create New Source EI Wiem Design Summary F Design Utilities User Constraints BR Bes 7 Rerun All if Processes Stop Open vVWwikhouk Updating hi Fatal Error c Properties Figure 5 21 Generating bit file 82 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Programming TLL5000 23 After completing Generating Programming File process expand Generating Programming File process tab in the Process for window and run Configure Device IMPACT process When this process is executed the target board has to be connected with the appropriate cable connections Processes for buffer Behavioral H E Design Utilities m ae Uzer Constraints H PE Synthesize XST H PE Implement Design El PE Generate Programming File Biv Frogramming File Generation Report er Generate PROM ACE or J TAG File Configure Di egies Si af Processes Rerun ST Rerun All X Started Lagi Stop Open Without Updating ap Properties Started Lav Figure 5 22 Configuring the target platform 24 Once the Configure Device iMPACT process is run the below shown below appears In this window just click on Finish E iMPACT Welcome to IMPACT Please select a
43. e Power supply for TLL5000 18volts 3 5 Amps USB cables 2 Nos Xilinx Platform Programming Cable newer versions use an USB interface but parallel cables will also work e CDs with User Documentations and Software 4 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 The CDs provided with the TLL5000 will typically contain the following items Please consult with your local TLL product partner for specific details as your configuration may be different from this table Various application utilities and Evease CHECK WIEN VOUL 1G TLL User Software i pP TLL partner to verify that the associated software and hardware and Manuals manuals and software are the manuals for the TLL5000 i most current versions As a convenience for the user this These tools will have a license CD has the freely downloadable duration determined by Xilinx Web downloadable oe ooe FPGA software from the Xilinx and they will provide updates Website The registration is done through their standard update online by the user mechanisms Notel The installation of Xilinx tools are self guided Click on the Setup exe in the directory and the installation starts Note2 Choose the option of cable drivers during the installation of Webpack ISE If these drivers are not chosen then the drivers for Platform cable USB will not be installed in the System Copyright 2008 The Learni
44. e full adder v Module Name full_adder Processes Port Definitions No flow available ata_input_sw_1 Pin data_input_sw_2_ Pin ty_in_sw_3 Pin input sum_output_led_1 Pin a input A Processes Figure 5 10a Verilog file Summary 70 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 ES Xilinx ISE File Edit View Project Source Process Window Help DAHA S408 K OS YEP PX SB ALS BOERNE lied MEY SSR ea SARS Sources x No project is open ise New Project Wizard Create New Source Select File Open Project i or File gt New Project ese New Source Wizard Summary Add to Project Yes oe Source Director EAXILINSSS ample funE xamples F ull adder Source Type Verilog Module gam Etg Sources ees Snapshots f Librarie Source Name full adder Baere Module Name full adder i The directory i Pott Definitions No flow available data _input_sw_ 1 EAXILINS I SampleifunExamplesiFull_adder data_input sw 2 cam insew 3 Pin does not exist Would you like to create it sum_output_led_1 camy_out_led_2 Pin ap Processes x iil E Console E Eros Warnings Wa Tcl Shell i Find in Files Transcript start i RealPlayer Koi Ladki Gh TLLS000 Getting St t untitled Paint Figure 5 11 Creating project directory 11 Click on Next in this window New Project Wizard Create New Source Create a N
45. e is also saved Xilinx ISE E XXILINX Sample funExamples Full_adder Full_adder ise full_adder v Sel File Edit view Project Source Process Window Help e DPaG SEX HRRX OS PEPHAHXKSP BABE OMEANPEMAletidt yi Ore ot OF ee GOies S2 EU 4arnow Description Sources for Synthesis Implementation i Full adder Dependencies a tgs aE f S xc3s1500 4fg676 t f Revision g a v full_adder full_ adder v Revision 0 01 File Created Additional Comments i tee eee eee eee ee eee eee module full adder data_input_sw_1 data_input_sw_2 carry_in_sw_3 sum output led 1 carr input data_input_ sw_1 input data_input_sw_2 EFES OA input carry in sw 3 BZ Sources py Snapshots P Libraries otc a Tie x output carry out led 2 Processes for ful_ adder assign sum output led 1 data_input_sw_l data_input_sw 2 i carry _in sw 3 assign carry _out_ led 2 data_input_sw_1 amp data_input_sw_z idata_input_sw_1 amp carry_in_sw_3 View Design Summary data_input sw 2 amp carry_in_sw_3 rs Design Utilities J E User Constraints endmodule Sunthesize xST lt ap Processes Add Existing Source Create New Source Be full_ adder w T Design Summary started Launching ISE Text Editor to edit full adder yv Started Launching Design Summary gt E Console Enos Wamings E Tcl Shell I Find in Files EE Transcript Ln
46. ed Design Summary enabled Message Filtering disabled xl lt Back Frin Cancel Figure 4 13 Viewing project summary 14 Figure 4 14 shows the VHDL file for the given design Normally whenever the file is generated it will contain the library declaration port declaration amp architecture declaration Only the functionality of the design has to be entered by the designer This simplifies the job of the designer and time is also saved ES Xilinx ISE F menporul Xilinx91 test_project test_project ise buffer_8 vhd M File Edit View Project Source Process Window Help JD BFA GISOexlwae DI PONXSAlAISE OA A Owl Aly la g a eral OWEE _ 2 Bt Annan MW x Revision Sources for Synthesis Implementation hd Revision 0 01 File Created Additional Comments S test_project E 3 xc3s1500 4f9676 aa buffer_8 Behavioral buffer_8 vhd library IEEE use IEEE STD_ LOGIC 1164 ALL use IEEE S5TD_ LOGIC ARITH ALL use IEEE STD_LOGIC UNSIGNED ALL Uncomment the following library declaration if instantiating any Xilinx primitives in this code library UNISIMN use UNISIN Components all entity buffer 6 is Port a in STD_LOGIC VECTOR 7 downto QO b out STD_LOGIC VECTOR 7 downto O end buffer 8 Processes for buffer_8 Behavioral Add Existing Source Create New Source View Design Summary architecture Behavioral of buffer 8 is Design Utilities User Con
47. esign Base Module Getting Started Guide Ver3 4 18 The simulator used here is ModelSim XE from Xilinx Once the process is started the simulator tool is invoked The simulator main window and the wave window are opened As shown in the below figure fe ModelSim SE PLUS 5 8c File Edit View Compile Simulate Tools Window Help T Workspace Tea Desinurittype OO Reading F Menporul FPGAdvBSLSP3 M odeltechtel vsim pref tel r Petals st ae HA ModelSim SE 5 8c Mar 01 2004 F buffer buffer_Sfbe Architecture it iy E td logic unsigned std_logic_un Package H Copyright Model Technology a Mentor Graphics Corporation company 2004 HY All Rights Reserved HY UNPUBLISHED LICENSED SOFTWARE B stc_logic_1164 std_logic_1 Package He CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE E standard standard Package 7 PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS Hi do buffer _8 fdot H Warning vlib 34 Library already exists at work Model Technology ModelSin SE voor 5 8c Compiler 2004 03 Mar 25 2004 Loading package standard Loading package std_logic_1164 Loading package std_logic_arth Loading package std_logic_unsigned Compiling entity butter Compiling architecture behavioral of butter 6 vam lib work t 1p butter 6 Loading F Menporul FPGAdv6SL5PS 4M odeltechwinse std standard Loading F Menporul FPGAdv6SL5P5 Modeltech wins eee std_logic_1164 body Loading F Menpor
48. evel netlist for the input design file The netlist is a text based file that contains the details of the devices and the interconnection network that are used in the design 30 In order to run the synthesize process select Synthesis Implementation option in the Source for tab and right click on the Synthesize XST process in Process for window and select Run from the pop up menu Once the synthesis is completed expand the synthesis process to view the synthesis report RTL Schematic amp Technology view of the given design 27 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 31 The above processes are shown below SS milin ISE Fiihenporulh ihn S thar designs 31 tbhuffer_ sc xs File Edit ee E e Project Source Process oo Tools we im IlO gt BA te a B B x e e El s le er A ee ot Srt at scl Ss lll w a5 a am Sources for Synthesis aiplementation boo bukFer_ sch G 63 xc32e1500 4Fo9676 Fane aot bukher_ech bukFer_szch schil SYS Sources hps Snapshots Libraries Symbols Processes For buffer _sch Create Mew Source Whew Design S ummary Design Utilities Llser Constraints Synthesize SS Implement Design Rerun rocesse St Options ai Rerun All 5h Step DRC Check hutter pem Wwreiook O p d sting wh hAl net List Cile FEE Praperties Figure 3 30 Synthesizing the design 32 The ne
49. ew Source New Source Source File Type T i lane Verlag Module Figure 5 12 Creating new source 71 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 12 Since a new project is being created it is not required to add any existing source at this point of time So click on Next The summary is created based on the information that is given so far Now click on Finish E New Project Wizard Project Summary Projact Navigator will create a new project with the following specitications Project Project Name Full adder Project Path E XILINX Sample funExamples Full adder Top Level Source Type HDL Device Device Family spartans Deyice xe3S1500 Package g ro speed 4 Synthesis Tool HST VHDL Verilog Simulator ISE Simulator VHDL Verilog Preferred Language Verilog Enhanced Design Summary enabled Message Filtering disabled e ee ee o Se es ee Figure 5 13 Viewing project summary 72 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 13 Figure 5 14 shows the VERILOG HDL file for the given design Normally whenever the file is generated it will contain port declaration Only the functionality of the design has to be entered by the designer This simplifies the job of the designer and tim
50. g Started Guide Ver3 4 15 From the Categories tab in left side of the window select buffer and select the desired symbol from the Symbols tab and place in the editor window as shown in the figure The editor can be zoomed in out as per the requirement Notice the grid positions as guides to drawing a neat layout la a 2a B4VaM PLM PA ad ae ae Ei A oe wee en eee bc E eee eee wel Options T Symbols Select Options When vou click on a branch i Select the entire branch Select the line segment When you move an object O keep the connections to other objects Break the connections to other objects When vou use the area select tool select the objects that Are enclosed by the area r Intersect the area When you use the area select Figure 3 16 Placing the components 16 After placing the components the wire has to be connected To connect the wires right click in the editor select Add select Wire Print Current Sheet Pop te alling chenm atic Previous Wie Mest W E Tut Ctrl e Zopy Ctrl c Paste t Paste Special Belete oaom Wet Blame Ctrl D Select and Clear P Bus Tap Ctrl e Object Properties A lt Enter Ifo Marker tri 5 Symbol trl r Instance Mame trl J ric Circle Line tril L Rectangle Text trl T Figure 3 17 Adding wires to the components 21 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base M
51. ign cc cece cece seen teense eeeeeeeeeeeeegeeeeseaaes 48 SVMUENCSIS Of ENG DESIGN iincwaiucisdedds tiv a ances anne daiwa 53 Implementation of the Design cece cece cece eect ee eee e teense eeeeeeeeeesneneeeenaaaes 54 Progr amnmung UELS000 sesar inara er S A stoma anatase aoenee 58 F nctonal Teston the TLELS0Q0O scicviesiesoitatadraiivadiaeeeavandna a a a ai 63 Digital Design USING Verilog AHD Laniaveiuteriinteiatensndia E E 64 Behavioral Simulation of the Design sssesssssssssrrrrrrrrrrrrrrrerrrrrererersrsreree 74 SyNtNESIS OF tne Desilo airera NE A O E EAEE 78 Implementation of the Design sesesesererererrrrrrrrrrrrrrrrrrrrrrrrrrrrerererersreree 79 Programming TEL5S0QO scisiicisugedisinladinnanatiawiwesanabalubedoudetadianavaenormieaganmeeakar 83 FUACEONal TESt On tne PLES 000 4s icitieaniaied nse Gereevaiuamnetienbenenidaidatiaewnks 89 3 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Chapter 1 Prerequisites System Requirements The following are the prerequisites for a computer to run the required software tools for doing basic digital designs on theTLL5000 Make sure that these components and minimum hardware are present e Personal Computer Pentium 1 GHz or higher Although lower processors will run the software tools the desired results are not guaranteed 512MB RAM for average applications larger designs a 1GB
52. ious user settable parameters such as the system clocks shown in the lower tables For example the expected voltages and the actual voltages will be displayed in the Power Values Monitor section in the upper left of the display screen E TLL5000 Monitor Controler Ethernet Test Connected Board ID Host IP 192 168 0 3 Test LL 5000 Development Board Ethernet EoadIP 192 i168 Oo D0 Not Done Address Power Vales ontu el CPLD RW Sree ee TC f Read Read 12 V 12 394 40M AA 33 E aay sey oxo0000000 reg ox00000000 gt reg g 25 25v 298V 262V Lev 1mY 16V 181V Piali pate 12 iay agay tony val oxo0000000 Read val oooo00000 Read Clocks Control JTAG Testing D9510 Registers Clock Inputs C k oo MH Scan chain Set Open SWF 1x i 00 j ca ckz f 100 0000 MHz wait TAP Reset p eoo R val 0x00 ad Clack Outputs LYPECL Output Frequency Divider Duty Cycle Phase Offset On Off Accessory Pot Clk 1 100 0000 MHz Divider Bypassed Divides Bypassed o Accessory Port Clk 2 100 0000 MHz Divider Bypassed Divider Bypassed o Sel Set LYPECL Mezzanine 4 100 0000 MHz Divider Bypassed Divider Bypassed 0 i LYPECL Mezzanine B 100 0000 MHz Divider Eypassed Divider Bypassed O LVDS and CMOS LVDS CMOS Mezzanine B 100 0000 MHz Divider Bypassed D
53. is example it is Spartan 3 Family 1500 Device Gate density As per this example 1500 kilo gates are present in this chip 4 Speed Grade FG Package type Fine pitch Ball Grid Array 676 Number of I Os on the chip 42 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 6 To create a new source click on the New Source button teens E New Project Wizard Create New Source Create a New Source Creating a new source to add to the project it optional Only one new source can be created with the New Project Wizard Additional sources can be created and added to the project by using the Project gt New Source command Existing sources can be added on the next page More Into lt Back Cancel Figure 4 6 Creating new source file 7 When the new source button is clicked give a file name for the input source code and select the file type from the left hand side list In this example it is a VHDL module E5 New Project Wizard Create New Source Wizard Select Source Type Oe x J IP Coregen amp Architecture Wizard z Schematic Py State Diagram Test Bench aver orm User Document Verilog Module File name At Verilog Test Fixture F VHDL Module ies VHDL Library Location P VHDL Package FAmenporulin31 test_piect P VHDL Test Bench F menporuhilneS test project nee W Add to project More Inf
54. ivider Bypassed 0 D Mezzanine 4 100 0000 MHz Divider Bypassed IE Divider Bypassed p amp FPGA 100 0000 MHz a Bypassed Divider Bypassed CPLO 33 3333 MHz Drider 3 J 39 HC 1 LC 2 J T J Status information Configuration file Clocks set OF Read Ve pie Figure 2 5 Platform power up 10 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Setup for Xilinx Platform Cable amp TLLS5000 Base Module Note Before connecting the Xilinx Platform Programming Cable from the PC to the target TLL5000 it is required to complete all the steps of TLL5000 Power ON and Configuration using the TLL5000 Hardware Manager as explained in the above section e When the Xilinx Platform Programming Cable is plugged into the system the hardware is identified This can be verified by right clicking on My Computer gt Properties gt Hardware gt Device Manager gt Programming cables H Computer Fd Disk drives aa Display adapters aS Floppy disk controllers Fy IDE ATA ATAPT controllers ae Imaging devices Fae Keyboards H Mice and other pointing devices t m Monitors H E Network adapters E gf Ports COM amp LPT Progr amming g ilins Platform Cable USE efi Sound video and game controllers ce System devices H Universal Serial Bus controllers Figure 2 6 Checking status of the platform USB cable e Now obse
55. le on TLL5000 board ES Xilinx ISE F imenporl xine 1 test projecttest_project ise buffer aal File Edit Wwiew Project Source Process Window Help IDe Aa SIKXBEBxlealP PLOunxXe Ia e a artara allo oles 22 SRI Rewision Sources for Synthesis Implementation sitesi N Addition pe besk project EA xcds1 500 4 gb76 EE Maleh butter _8 Behavioral Duffer _S shd library IEE he e buffer _8 ucf buffer _8 uct use IEEE STI use IEEE STI use IEEE 5STI Uncore Any Al library UI ERS Sources po Snapshots T Librari usze UNISII entity butte Port i end buffer i Processes for buffer _S uct gt Ps Add Existing Source Gal Create New Source Bl User Constraints architecture DER Create Timing Constraints Eg Assign Package Pins 3 Create 4rea Constraints Edit Constraints T ext Rerun Rerun 4ll Stop 4 af Processes Open Without Updating PROPERTIES Figure 4 24 Assigning package pins 55 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 27 Once Assign Package Pins process is run another built in tool from ISE will be opened called Pin out Area Constraint Editor PACE Enter the pin numbers in the LOC field as shown in the figure The pin number details in the figure below bottom left window labeled Design Object List O Pins are as needed for
56. ll create a new skeleton source with the following specications Add to Project Yes Source Directo F Menporul ned baru designe 1 Sbuther sch Source Type Schematic Source Name butter sch sch lt Back Cancel Moore Info Back Cancel Figure 3 7 Completing the new source wizard 8 In the next window click Yes to create the new project directory Project Navigator will create a new skeleton source with the following specifications Add to Project Yes Source Directo FAMenporulsilins g1 baru _designs91 buffer _sch Source Type Schematic Source Name buffer_sch gt The directory FAM enpormhelined baru designe buffer sch does not exist Would you like to create it More Info lt Back Cancel Figure 3 8 Confirming the project creation 17 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 9 Then click on Next in the New Project Wizard E New Project Wizard Create New Source Create a New Source Hew Source ieee Creating a new source to add to the project i optional Only one new source can be created with the New Project Wrizard Additional sources can be created and added to the project by using the Project gt New Source command Existing sources can be added on the next page More Info lt Back Cancel Figure 3 9 Creating a project 10 Again click on Next butt
57. max So la at fa Se HS olk x 22 Sources for Synthesis Implementation ea ed A fal buffer sch S Eg xc3s1 500 4196 76 DE butter sch butfersch sch han Pe bufter_sch uct butter_sch uct SYS Sources jes Snapshots gt Libraries 2 Symbols Processes for buffer_sch Design Umke H User Constraints E Fahy Synthesize 57 PYE lmplement Design H PE Translate HM i PE Place amp Route af Processes 20 Options Perim a Rerun All x Process Generate Fost ai stop Open Without Updating aL Properties Figure 3 37 Generating bit file This process will generate the programming file i e the bit stream file will be generated This is the file that will be downloaded onto the FPGA Once the file is generated the next step is to make the communication between the host system and the target TLL5000 33 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 47 Before starting this process Power ON the board as given previously To make the communication expand the Generate Programming File process and select the Configure Device IMPACT process Es Xilinx ISE F Menporul Ailing 1 baru_designs914bulffer_sch t le File Edit View Project Source Process Add Tools Windo amp 2B M 2 oo i Gat aE PE Ot EAE OI ly 5d ae 28 Z Sources for Synthesis plementation j buffer sch EA xo3s
58. mentation process E ilng ISE F menporulxilineg91 Atest _projecthtest_project is D File Edit View Project Source Process Window Help a Post Translate Simulation Post Map Simulation Post Aoute Simulation ET Sources pe Snapshots gt Libraries Processes for buffer_ Behavioral O Add Existing Source Figure 4 22 Selecting synthesis option The progress of the Synthesis process will be shown in the console of the ISE Left down corner In case of any errors the details of the errors will be displayed With any type of error the design will not proceed to the Implementation stage The synthesis generates the synthesis report RTL schematic Technology Schematics The user should verify these reports in order to understand the actual logical circuitry that will be configured in the FPGA 53 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Implementation of the Design 24 The implementation process has three different sub processes in it They are Translate Map and the third is Place amp Route Translate This is the process that merges all the input files and the constraint file into a single netlist Map The process of mapping the logical components to the physical components is known as Map Logical components are nothing but the components that we have as per the design circuit diagram Physical components are the components that are
59. n action from the list below f Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File C Configure devices using Slave Serial mode Cancel Figure 5 23 Welcome screen of iMPACT 83 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 25 Once the Finish is clicked the iMPACT tool will detect the boundary scan devices on the target TLL5000 Here xcf32p is a flash prom amp xc9572 is a CPLD These devices will NOT be programmed Click Bypass on the following window E Xilinx ISE EAXILINX Sample funExamples Full_adder Full_adder ise Boundary Scan E File Edit View Project Source Process Operations Output Debug window Ba age ERa Oo Ind a ao 8 S Ounces x l e 2a Boundary Scan o Ra SlaveS erial BA SelectMAP TA Desktop Configuration H BA Direct SPI Configuration p systemACE xCOS 2 C0321500 E PROM File Formatter s tile 7 _ file 7 jo file eek TOO Assign New Configuration File aapa aaa aa At Ej Sources gg Snapst I Libraries Configurat 7 C isim tmp_save 3 mot Processes Flenme SSCS File type All Design Files rnics exo ise Bed None O Enable Programming of SPI Flash Device Attached to this FPGA
60. ndow appears This is the place where the target hardware amp necessary tools are selected Key in the inputs as per the requirements Then click on Next ES Xilinx ISE File Edit View Project Source Process Window Help DPR S 488X BS YIEPHPHXKHSP BABS OMAK EM Blekeddts vi fF Re Bale a Sources x No project is open Select File gt Open Project EES New Project Wizard Device Properties TRAR Project Select the Device and Design Flow for the Project Propone Nam snes Product Category All Family Spartan3 Device 8C351500 Brg Sources eg Snapshots Py Librarie Bsa FG676 a Tea Speed Processes No flow available Top Level Source Type Synthesis Tool MSTIVHDLWerlog Ci Simulator ISE Simulator VHDLMVeiog OZ O Z oOooo Preferred Language veios O y Enable Enhanced Design Sumay Z Enable Message Filtering 4 E Bf Processes Display Incremental Messages C x Figure 5 5 Selecting target hardware Note 1 The Simulator Chosen ISE Simulator Synthesis Tool XST this is the built in Webpack ISE Note 2 The device Package and speed are chosen based on the details of an FPGA chip on the TLL5000 XC3S1500 4fg676 XC Xilinx Component 3S Device Family in this example it is Spartan 3 Family 1500 Device Gate density As per this example 1500 kilo gates are present in this chip 4 Speed Grade FG Package type Fine pitch Ball Grid Array 676 Number of I Os on the chip 66 Copyright
61. ng Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Chapter 2 Setting up TLL5000 Base Module The following picture shows the connections to be made between the PC and TLL5000 Base Module Please strictly follow the steps as per the manual to avoid any problems to the hardware The wrong sequence of applying power and connection sequence can cause damage to the system Power Supply 18v 3 5A Power Connector CON100 USB port for TLL5000 Connection CON801 USB Cable1 ji if 4 s iz A a T D j i Fg t n e i iz i M E E T ph Da Tei zatzy a i Sr oS o O 7 E i Eau ae ay i Li E pime eaa wi ie d A TLLS000 Rev 1 1 satik EEst E S a a a L a pee DER AE j vl n dli aie Fw ER is ie a a aia J i Sar i 7 Sl FODIITT LORIE ER th i E i h ae BETU CTAE ing a Xilinx Cable2 Kaaa FPGA J TAG port J TAG port CON1 Fom PC to TLL5000 14 pin CON1 Figure 2 1 TLL5000 platform setup 6 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Power ON and TLL5000 Configuration using System Controller Connect the power supply to the power supply connector CON100 e Connect the USB cablel between PC USB port amp CON801 This connection is used for communication and configuration of the TLL5000 from the PC using the TLL software provided with your system
62. nt Previa Ea Print Ctrl P m 3 Recent Files Recent Projects Exit Figure 5 3 Creating new project 4 When New Project is selected a new window is opened as shown in the figure In the Project Name field enter the desired project name Now it can be observed that a folder is created with the same name in the Project Location field This is for keeping track of all the input amp output files in the same location ES Xilinx ISE File Edit View Project Source Process Window Help FD Pae oiy oS EP PK SP ALJA S B O Eh amp R OO amp te _kba_data GF amp amp wh ef SO St Sources x No project is open Select p 4 File gt Open Project fen Mew Project Wizard Create New Project or File gt New Project Enter a Name and Location for the Project Project Name Project Location Full_adder E SXILINISS amples funE xamples Full_adder Erg Sources 5 R D E Select the Type of Top Level Source for the Project Top Level Source Type HDL Processes No flow available ag Processes Transcript RealPlayer Kab Tak ay TLLSO00 Getting_Sta Figure 5 4 Entering project name 65 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 5 Let the Top Level Source Type be as HDL itself After giving the necessary inputs and clicking on Next the next wi
63. o 4 Back ne Cancel More Info lt Back Cancel Figure 4 7 Selecting file type 43 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 8 After giving the file name amp file type the input and output port list of the design has to be given Port list is the top level entity of the design After giving the port names the directions of the ports can also be entered as per the design requirement If the port is a type of bus that can also be entered along with the number of bits specifying the width of the bus FES New Project Wizard Create New Source E New Source Wizard Define Module Entity Hame butfer_ Architecture Mame i Pest Nome ben e d b More Info More Info Figure 4 8 Enter the port list Note The Port names to be entered in the above window shall also be 1 bit for typical logical gate implementations In the above design we have taken an input port of 8 bits O to 7 amp output port of 8 bits 0 to 7 44 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 9 After giving those details click on Next amp Finish E New Source Wizard Summary Project Navigator will create a new skeleton source with the following specifications Add to Project Yes Source Directory F nenporulsalined 7 Stest_ project Source Type WHOL Module S
64. odule Getting Started Guide Ver3 4 17 Now as shown in the below given figure add the wires to the components in the editor window Figure 3 18 Placing wires 18 After adding wires to the components the IO markers are to be added to the wires which Should be used for applying the inputs and monitoring the outputs To add IO markers again right click in the schematic editor select Add and select I O Marker Print Current Sheet Pop to Calling Schematic Previous View ext View Cut Ctri Copy Ctrl C Paste erly Paste Special Delete Wire zoom Met Name Select and Clear Bus Tap Object Properties Alt Enter rO Marker Symbol Figure 3 19 Adding I O marker 22 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 19 Place the IO markers as shown in the figure While placing the input marker select Add an input maker and for the output marker Add an output marker in the options window on the left hand side of the window NTE NED Na eee EEXTIRED SS ON 12 gt ee 115 XLXN 105 T EXLXN 9 gt i Figure 3 20 Renaming I O markers 20 To edit the object properties of the IO markers in the name field delete the existing name and give the desired name and click OK Fa Object Properties Category Hets New Marne Burfer_ir Edit Traits Delete PortPolarity Input T gt 2
65. on on the Add Existing Sources window since at this point of time there are no existing source designs E Hew Project Wizard Add Existing Sources Add Existing Sources Add Source Remove Adding existing sources is optional Additional sources can be added after the project is created using the Project gt Add Source or Project 4dd Copy of Source commands More Info z Back Cancel Figure 3 10 Adding an existing file 18 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 11 Click Finish on the Project Summary window to create the project or click Back to go back and make some changes if any E Hew Project Wizard Project Summary Project Navigator will create a new project with the following specifications Project Project Mame butter sch Project Path F Menporul XilineS1 baru desiqnsd1 bhuttfer sch Top Level Source Type Schematic Dew ice Device Family Spartans Dewice xOeSS1500 Package g Speed 4 Synthesis Tool XST VHDL Verilog Simulator Modelsim ZE VHDL Preferred Language VHDL Enhanced Design Summary enabled Message Filtering disabled x Figure 3 12 Viewing the project summary 12 Once the finish button is clicked the project is created and the design summary is also given in the ISE tool window as shown below And click on the file name tab to edit the file as shown in
66. ource Mame butter 6 vhd Entity Name buffer Architecture Hame Behavioral Port Definitions a Bus lt 0 ih b Bus z out Back Cancel More Info Cancel Figure 4 9 File summary 10 After clicking on Next the tool will ask for the confirmation of creating a new folder Simply Yes can be clicked This will create a folder named as the project name in the specified location And based on the information that is given a skeleton of the VHDL file is created which will have all the declaration parts of the file This is common for all the VHDL files Wizard Create New Source ioj x iail Project Navigator will create a new skeleton source with the following specifications Add to Projack Yes Source Director F menporul saline test project Source Type YHOL Module Source Name buffer_B vhd Entity Name buffer 3 ce The directory Architecture Mame Behavioral Port Definitions FAmenporuhssiins g test project a Bus lt 0 b Bus ZO does not esist Would you like to create it lt Back Cancel More Info Back Cancel Figure 4 10 Creating project directory 45 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 11 Click on Next in this window E New Project Wizard Create New Source Create a New Source Hew Source ie buffer amp vhd VHOL Module Remove Creating a new source to add to
67. patches will be sent to you automatically as long as your registration is current The TLL products are designed to be supported remotely by allowing viewing of the user s desktop It is highly recommended that the PC from which you are using TLL products is connected to an Internet link that allows Web browser access In this way our technical support staff can view your desktop and work with you to understand and solve technical issues 2 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Table of Contents PECCOOUISILGS ix aiica tan puchentoa vase nacneniaa naw pisos obadcchbmna cn A dana auch olan eanenatapetad 4 SY Sei REGUIFCIICIIT Shelia cacanasniteis NA AA ANA 4 SOftware FEQUIFEIMEN TS seirena EA E A E 4 Hardware reguremeNn tS lt csasieeewasdnataraderadsasailetans TA 4 Setting Up TLL3000 Base MOGUIC espressero ar E 6 Power ON and TLL5000 Configuration using Hardware Manager 000008 7 Setup for Xilinx Platform Cable amp TLL5000 Base Module cece eee ee ee eee 11 TLL5000 Interfaces and PeripheralS cccccccseeeeeeeseeeeeeeeeaeeeteeueeeseegenegs 13 Digital Design USING Xilinx ISE ccc cece cece cece eee eee eee eeeeaeeetsenaeeesesaeeetsegenegs 14 Functional Teston the TEES O00 orrena eA AAO NOAN 39 Digital Design USING VAD vicrisiadionntatrasnraaaatendatadtadaiadsraacenniaimaneeatanbesated 40 Behavioral Simulation of the Des
68. perty Name ee Product Categor C3351500 a GEG nal oy E Family Es Device Tn Package Ja S peed Top Level Source Type 4 sot VHOL Verilog Modelsim lt E WHOL Synthesis Toal 4 Simulator Preferred Language Enable Enhanced Design Summa Enable Message Filtering FELL EE Display Incremental Messages 2 Ti T il Figure 3 5 Selecting of a device 6 In the next window click on New Source tab In the New Source Wizard window give the file name and select the input file type as schematic E Hew Project Wizard Create New Sour E Hew Source Wizard Select Source Type tj IF Coregen amp Architecture Wizard Schematic 2A State Diagram Test Bench WaveForm User Document Verilog Module File name Ah Verilog Test Fixture Jufiersch tt lt i Ss S T VHDL Module vet I VHDL Library Location VHDL Pack g VHDL a os FM enporulhilined 1 bar designed Sbuthersch pon IY Add to project More Info Back Cancel More Info lt Back Cancel Figure 3 6 Selecting a source type 16 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 7 When the Next button is clicked the New Source Wizard summary window will be seen Click on Finish here sE Hew Project Wizard C 5 New Source Wizard Summary Project Navigator wi
69. ples Full adder D C izim tmp_save ngo sst C smeg eo re All Design Files jed ise bed Look ir File type we Cancel All O Enable Programming of SPI Flash Device Attached to this FPGA None O Enable Programming of BPI Flash Device Attached to this FPGA Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 27 The third window is for the FPGA Please ensure that the FPGA is selected by being highlighted Then select the appropriate bit file and click on Open EES Xilinx ISE EXILIM Sam ple funExamplestFull_addert Full_ adder ise Boundary Scan Ss File Edit View Project Source Process Operations GQukpuk Debug Window Help PO Pla Stet eeax eae Mt PLS A BLASS BS OCH eS RP 2 OO lat kbd date sE E Gl Soe St oe tS an MR Ete te ae ae O ce KN Sources SS Boundary Scan oo SS Slaves erial BE SelecthaP j BAD esktop Configuration H RE Direct SPI Configuration o S SystemACE xots2p lt COSF 22 xeSe1 500 a E PROF File Formatter bypass bypass file 7 Assien Mew Configuration File Look in 9 E x ILINS 4S ample funk xamples Full_adder j Tl Jj ere Sources peg Snaps TT ia Libraries Configuration he Ea IO isim tmp_save C _ngo m E C _xmsgs ex Full adder bit File name Full adder bit Open Processes File type t Cancel Cancel
70. r Bl Sources g Snaps fY Libraries Configuration M x File name buffer 8 bit File type All Design Files bit rbt nky tse bed Cancel All C Enable Programming of SFI Flash Device Attached to this FPGA f None C Enable Programming of BFI Flash Device Attached to this FPGA Bf Processes Configuration Operations Design Summary 4 buffer8 vhd i Boundary Scan x PROGRESS END End Operation Elapsed time 3 Sec f ttt BATCH CMD identifyMPM Console i ig Find in Files Configuration Platform Cable USE 6 MHz usbfs Figure 4 31 Selecting bit file 61 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 34 Now it can be observed that the FPGA is selected with the given bit file E Xilinx ISE F AmenporulilingS1 test_project test_project ise Boundary Scan File Edit View Project Source Process Operations Output Debug Window Help JOP RE BIIZSEXlsal PPSXR SS AlAS SOG F vm le e alg m aala o AP EEEE EESE H Boundary Scan Hh Slaves erial m T S electMAP F2 Desktop Configuration 23 Direct SPI Configuration E SystemACE CAST 2x xe3s1 500 PROM File Formatter file 7 buffer_ amp bit Libraries Configuration Wl Figure 4 32 Programming selection 7 Right click on the FPGA that is xc3s1500 and select program from the pop up menu Then the below shown window appear
71. rve the color of the status LED on the Platform cable USB box It will be orange The status will remain orange till the other end of Platform cable USB a 14 pin Flat ribbon connector is connected to the TLL5000 Status LED 14 pin FRC connector goes to TLL 5000 board aa i This end goes to CON1 PC USB port Figure 2 7 Checking status checking 11 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 e Now connect the Xilinx Platform Programming Cable to the JTAG 14 pin FRC connector labeled CON1 on the lower right of the TLL5000 this is non reversible connector with a notch on the connector long side Please refer to the following diagram for connections F SS MM PEATE l de RM TLES000 Rev 1 1 1 Mee O priba 20DE a E paundaee a B ikenet Thal Figure 2 8 TLL5000 platform J TAG connector e When the Xilinx Platform Programming Cable is connected to the TLL5000 the status LED of the Platform Programming Cable will turn GREEN indicating that the JTAG communication is successful with target board Note If the TLL5000 Power ON and Configuration using the TLL5000 Hardware Manager are not followed then the reference voltage for J TAG will not be available on CON1 of TLL5000 and the status LED will remain ORANGE Until the status LED turns GREEN the bit file cannot be downloaded onto the target Platform 12 Copyright 2008 The Learning
72. s Click on OK in this window This will download the bit file onto the target device E Programming Properties x Category B Programming Properties Advanced PROM Frogramming Properties jn Revision Properties Wery General CPLD And PROM Properties Erase Before Programming Fead Protect PROM CoolRunner Weercode e Hes Digits CPLO Specific Properties Write Protect P Functional Test P On The Fly Program P SPLA UES Enter up to 13 characters PROM Specific Properties Load FEGA P ParallelMode P Wee Dt torr FPGA Device Specihic Programming Properties Pulse PROG Program key Spartans4h Programming Properties Data Protect Date Lockdown Cancel Apply Help E Figure 4 33 Viewing programming properties 62 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 35 Once programming is successfully completed the Program Succeeded message appears as Shown in the given figure fr Oe ot Ot HO Olli gt 214 3 0 Wee Ke in p Scan rial AP Configuration Configuration CE xc9572xl 0381500 ile Formatter file 7 file buffer _5 bit Program Succeeded ions are Figure 4 34 Programming status Functional Test on the TLL5000 36 The design downloaded onto the TLL5000 is tested for correct functionality with the use of switches and LEDs available on the target TLL5000 TLL5000 Re
73. straints Synthesize XST Implement Design Generate Programming File gt 41 end Behavioral 4 A Processes x Started Launching ISE Text Editor to edit buffer _ 8 whd Started Launching Design Summary Console D l Tcl Shell a Find in Files Ln 41 Cal 16 CAPS INUMISCALIVHDL Figure 4 14 Tool generated VHDL file 47 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 In the above window the IEEE libraries are included by default the design b lt a Is entered by the user This code will act as a buffer where the value of a is loaded to b all the 8 bits 15 As per the design flow after design entry the 1 step is to simulate So to simulate the Simulation option has to be selected The steps for selecting it is shown in figure 4 15 Behavioral Simulation of the Design 16 When the design is ready choose the Behavioral Simulation option This option is available on your top left hand corner of your ISE near Sources for Fs Xilinx ISE F imenporulhilinsgS 1 test_project ttest_projpect_ ise fa File Edit View Project Source Process Window Help Sources for Sonthesis lmplementatiorn bo test Sunthesis Implementation Behavioral Simulation i Post Translate Simulation Post Map Simulation Post A oute Simulation E Sources pa Snapshots P Libraries Processes tor butter_8S Behavioral Ad
74. ted for the FPGA to be programmed xcos fos 03217500 bypass butter ech bt Figure 3 42 Selecting the bit file 36 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 53 Now right click on the FPGA and select Program from the pop up menu verify xcoS 7 zzl O32 Sl Get Device ID bypass butter _ c Basta Get Device Signature Usercode 45sign New Configuration File Figure 3 43 Programming the device 54 In the Programming Properties window just click on OK Programming Properties Category se Programming Properties Advanced PROM Prograrniming Properties i Revision Properties Verify General CPLD And PROM Properties Erase Before Programming Read Protect PROM GoalRunrnerd Usercode E Hes Digits CPLD Specific Properties P write Protect P Functional Test P Orn The Fly Program P PLS UES Enter up to 13 characters PAUM Specific Properties Load FEGA P Parallelode P Wee D4 for CF FPGA Device Specific Programming Properties Fuke PROG P Program kep Spartand N Programming Properties Data Protect Data Lockdown Cancel Apply Help 2 Figure 3 44 Programming the device 37 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 55 The program status can be observed by the viewing the Progress Dialog box
75. the red circle on the figure E Xilinx ISE F Menporul XilinxS1 baru_designs91 buffer_sch buffer_sch_ise Design Summary 3 File Edit View Project Source Process Window Help IDPaeSa SIZSEX vae DPSOHXKX SPAS es nole roa Ale i fl ee Ot St Ot Ft 1S Olly ay ee wb Sle s BUFFER_SCH _ buffer_sch ise Categories Design Overview lt All Symbols gt p Summary Arithmetic pe LJ IOB Properties Ruffer i i pO Timing Constraints xc3s1500 4fg676 Symbols E Pinout Report J ISE 91i Up Mon Apr 23 13 36 44 2007 accl6 acc4 acca zi Symbol Name Filter Sages i Detailed Reports buffer_sch i Bee F Clock Report E Errors and Warnings BUFFER_SCH Partition Summary pe C Synthesis Messages No partition information was found P Place and Route Messages beneral gt d Errors URU eee Orientation i C Timing Mos TA essages Rotate 0 v i C Bitgen Messages Synthesis Report Symbol Info i A All Current Messages zi Translation Report Project Properties Map Report Erg Sources Snapshots D Libraries 2 Symbols i Enable Enhanced Design Summary Place and Route Report i O Enable Message Filtering i Display Incremental Messsages Enhanced Design Summary Contents Bitgen Report No flow available Show Partition Data i O Show Errors H O Show Warnings H O Show Failing Constraints i C Sho
76. tically add it to the project By selecting the ucf file in sources for window Run Assign Package Pins process from Processes for window The details of the pin locations are for switches and LEDs available on TLL5000 board ES Xilinx ISE E AILINXampleVuntxamples F ull_adde E File Edit View Project Source Process Window Help DPA iS BEX BS Wi Ps ead Shad iO O oo a T FPGA Des sources for Synthesis Implementation Design Ov fea Full adder Su EA xc3s1500 4fg676 B lol vf full adder full_adder v C Tir feg full_adder ucf full_adder ucf C Fir b Cle oy Errors and tS Sources eg Snapshots A Libranes A Sy Processes Tn Processes for tull_adder uct C M m Add Existing Source LJP Create New Source E O fir s User Constraints Project Propert PR Create Timing Constraints M Enabl E3 Create Area Constraints Rain Edit Constraints T ext ay Risin All Figure 5 19 Assigning package pins 21 Once Assign Package Pins process is run another built in tool from ISE will be opened called Pin out Area Constraint Editor PACE Enter the pin numbers in the LOC field as Shown in the figure The pin number details in the figure below bottom left window labeled Design Object List I O Pins are as needed for the TLL5000 LEDs and Switches 80 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3
77. ul FPGAdv6SL5PS Modeltech wins eee std_logic_anth body Loading F Menporul FPGAdvESL5PS Modeltechwinsey eee std_logic_unsigned bod Loading work buffer behavioral H wave E stc_logic_arith std_logic_arith Package wave default File Edt Wiew Insert Format Tools Window SOS 2 BOA bh Kes a QO Bed e buffer Gita HUUUUUUL U buffer eb UUUUUULL U Hio Cursor GEST F Now 100 ps Delta O sim buffer_ 8 Opstoins Figure 4 17 Compiling and simulating 50 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 19 Now maximize the wave window and right click on the input signal and select Force from the pop up menu fail wave default SEIE File Edit Wiew Inset Format Tools Window i buffer_8 a HILAL U Object Declaration T Radis Format Cut Lopy Paste Delete Insert Divider Insert Breakpoint Force NoForce Clock Properties Now 100 p 4 OE th Ops to 2060 ps Figure 4 18 Selecting Force option 51 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 20 When in the Force Selected Signal enter the desired value for the input signal s and click OK wave default gt File Edit wiew Insert Format Tools EF Baa buffer Bia UUUUUUUL D buffer _8 b UUUUUU
78. v 1 1 x yy al 2006 m i Wisi a ARA 3 RAELE na im b REV SEL Fle EAR jc lo E Taiz TERT LALitt LEDs dil ait a Figure 4 35 Observing outputs As the switches are toggled to ON OFF positions if the design is functioning correctly then the corresponding output LEDs will turn ON OFF to match the switch positions 63 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 Chapter 5 Digital Design Using Verilog HDL 1 To invoke the ISE 9 1 tool double click on the below shown icon on your desktop Z Alling SE 411 Figure 5 1 Invoking XILINX tool 2 Once the tool is invoked the below shown window will open No project is open File gt Open Project or File gt New Project No flow available A Processes xj 4 E Console Ewors Wamings TclShell ig Find in Files Figure 5 2 Tool welcome screen 64 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 3 To start a new project click on File tab and select New Project The same is shown in the below figure 5 3 FES Xilinx ISE File Edit View Project Source Process Window Help New Project gt om Op Gee p Open Project Open Example Glose Project Save Project 4s L New Ctrl N el Open Ctrl o Close H Save Etits Save As g Save All Pri
79. w Clock Report Sf Processes a X Design Summary g E buffer_sch sch D xi started Launching Schematic Editor to edit buffer sch sch Static Timing Report Started Launching Design Summary Console Warnings igg Find in Files 20 2736 Figure 3 13 Viewing project Summary in HTML format 19 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 13 Click on the Float Window button to get a better view of the schematic editor This is the Same as an undocking feature o o Figure 3 14 Undocking the window 14 Once the schematic editor is undocked i e the window is floated the following window can be observed Fy buffer_sch sch File Edit View Add Tools Window COCTEL PEKKAA ur 2 sho oanaalyj asaan to Options Categories Symbol Marne Filter Orientation Rotate 0 ieee edeeouds beer cows oe oe ees ue ea ee ee be op yay eee eee eee Pye oe oe tees a ees Symbol Info fie Sd Soo AB Gg Ale Gh oe EROR ee E Chem Och On alia Adee emo il di ean od Ete cea ge he eee A ae yess oi eee Og naar Figure 3 15 Selecting the components In this window click on Symbols tab in order to get the various components under different component categories in the left side of the window 20 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Gettin
80. x ld Putt ing dewice in ISF O Enable Programming of BPI Flash Device Attached to this FPGA Maximum TCE operating freq TIa li datina ehair P Processes Configuration Operations aey Figure 5 24 Detecting boundary scan devices 84 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 26 This window is to select the programming file for the CPLD Since we are not going to program that this can also be bypassed E Xilinx ISE EAXLINX Sample funtxamples F ull_adder Full_adder ise Boundary Scan D Fie Edit View Project Source Process Operations Output Debug Window Help DAHA St4R8BxX Oe YEP PN 2 BAB BOs OO im kbd daa mt fH a Bel st O O iss x x i eso SOUICES oo Boundary Scan e BE SlaveSerial B SelectMAP Ha Desktop Configuration j TA Direct SPI Configuration E SystemA CE E PROM File Formatter ERS Sources le Snapst D Libraries Configuration M Processes x EYP Processes Configuration Operations T N Design 1 Putting device in ISF mode done Maximum TCK operating frequency for thi Validating chain RBowndarw serean mhain wselidared sureessFi Figure 5 25 Selecting programming file 85 xcg5r xl file 7 wee 500 file 7 Assign New Configuration File E E ILI NS amplefunE xam
81. xt process is the implementation process This process has three major steps under it They are a Translate b Map and c Place And Route Translate Translate is the process that merges all the input files and the constraint file into a single netlist Map Map is the process that maps the logical components to the physical components Logical components are the ones which are there that according to the circuit diagram And the physical components are the ones that are physically present inside the FPGA Place And Route PAR The map output file will be taken as the input file for the PAR process The map file will contain how many CLBs amp IOBs are required to implement the design And also it will have the details of which are the CLBs amp IOBs that are used in the design implementation Based on that information those particular CLBs and IOBs will be configured This process is called as placing and the routing is the process which makes the interconnection CLBs and or IOBs 33 Before going to the process of implementation it is necessary to write the user constraints ucf file This is the file where the designer can give the constraints for the design to be implemented 28 Copyright 2008 The Learning Labs Inc TLL5000 Electronic System Design Base Module Getting Started Guide Ver3 4 34 To enter an ucf file click on Project menu and select New Source option ES Xilinx ISE F AMenporulxilineS 1

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