Using M68HC16 Digital Signal Processing To Build An Audio
Contents
1. Digital processing algorithm ED 2 transfer Eacc to Dacc SUBD XN2_125 6 Dacc x n x n 2 STD X 2 125 6 store Dacc to x n x n 2 addr LDD XN1 125 6 load Dacc with x n 1 STED XN1 125 8 store x n to x n 1 and store x n 1 to x n 2 AC 252 12 gamma 1 Macc Macc AC 2 2 12 beta 2 AC 242 12 alpha x n x n 2 Macc Macc ER 6 transfer Macc to Eacc round for converg ASLE 2 multiply Eacc by 2 Get LED encode value from look up table E 2 transfer Eacc to Dacc STAA LD125 3 6 Dacc high byte gt instruction ldaa 03 NOP 2 no operation due to CPU pipeline NOP 2 no operation due to CPU pipeline LDAA ED TBL 6 load Aacc with the encoded LED value from scaled peak LED table Update peak value if needed CMPA PK_125 6 compare value to previous peak value BLS DN125 6 2 branch if not more than peak value STAA PK 125 6 store new peak value STAA TR4 1 6 store new value to 125 qspi tran ram Update y n 1 and y n 2 LDD YN1_125 6 load Dacc with y n 1 STED YN1_125 8 store Eacc to y n 1 Dacc to y n 2 Start of the 500 Hz DSP routine CLRM 2 clear Macc DE AD 6 load Eacc with AD Digital processing algorithm ED 2 transfer Eacc to Dacc SUBD XN2 500 6 Dacc x n x n 2 STD X 2 500 6 store Dacc to x n x n 2 addr LDD XN1 500 6 load Dacc with x n 1 STED XN1 500 8 store x n to x n 1 and store x2. 10 12 5 25 FREQ FS 2 FS kHz AN1233 F7 Figure 7 AFA Aliasing Without Filter For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Voltage Attenuation dB 20 log 1 2ADCres Where ADCres A D converter resolution System bandwidth is 10 kHz and at a 25 kHz sampling frequency components above 12 5 kHz will alias Therefore the signal must be attenuated 48 dB to eliminate all aliasing components Accordingly the filter must have a minimum drop off slope of 96 dB per octave To insure that this requirement is met a roll off of 100 dB per octave is used Using these values with the MAX274 design software resistor values for an eighth order 0 5 dB passband ripple Chebyshev filter were obtained Lower passband ripple was sacrificed to gain steeper roll off The anti aliasing filter response programmed into the MAX274 is shown in Figure 8 MAGNITUDE dB 50 10 12 5 15 25 FREQ FS 2 FS kHz AN1233 F8 Figure 8 AFA Anti Aliasing Filter Roll Off ADC Input Biasing The MC68HC16Z1 ADC module can convert analog data into six different digital representations Digital data can have 8 bit or 10 bit resolution can be signed or unsigned and can be left or right justified These formats are shown in Figure 9 15 8 7 0 RESULT For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 10 shows hexadecimal represen
3. This function implements an IIR bandpass function with characteristics defined by the coefficients a and In an RLC bandpass filter circuit resistors capacitors and inductors would characterize filter response In the digital implementation of the filter the a B and y coefficients determine the response in much the same way The basic parameters that define digital filter response are the Q the sampling frequency Fs and the cen ter frequency Fo The Q value defines the sharpness of the filter and is equal to the center frequency di vided by the bandwidth between the 3 dB points The specified sampling frequency is 24 95 kHz the center frequency is 1 kHz and Q value is 1 5 Figure 21 illustrates these relationships Table 3 shows the way in which coefficients are stored in memory MAGNITUDE DB 3dB BANDWIDTH Fo BANDWIDTH Fo Fs FREQ For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Equations that define the coefficients are shown below Coefficient values are also given in the code listing 0 2 Fo Fs 0 2 If X gt 4 then X 0 75398 0 5 1 tan 09 1 tan y 0 5 D cos a 0 5 B 2 Where Fo 1 kHz Fs 24 95 kHz Q 1 5 For more information concerning these equations refer to Motorola Application Note Digital Stereo 10 Band Generator APR2 D Once coefficient values have been obtained th
4. turn on ADC 8 bit set sample period Initialize the extension registers for the internal ram in bank F Set up the extension registers to point to bank F LDD 8000 STD RO STAA R3 1 LDD 0080 STD R1 CLRD STD R2 STD R4 LDD 0400 STD SPCR2 ADC Initialization LDD 0000 STD ADCMCR LDD 0003 STD ADCTLO LDAB SOF BEK TBXK TBYK TBZK JMP RAM Start of Internal 1K RAM ORG F0000 CLR CNT CLR PK_1K Initialization for DSP ORP 0010 CLRD TDMSK LDY COEFBS LDX YTRMBS CLRD STD ADCTL1 Divide input x n LDAA LJSRRO ASRA STAA AD load b with 0F transfer Bacc to transfer Bacc to transfer Bacc to transfer Bacc to Zk jump to internal ram for speed N A A NK gt ii clear LED update counter clear 1K peak value Set saturation mode for Macc clear no modulo addressing load y with the coef base addr load x with the yterm base addr 2 clear Dacc 6 single 4 conversion single channel ADO writing to the ADCTL1 reg starts conv no overflow problem 6 load Aacc with left jus signed ADC value 2 divide by 2 6 store divide by 2 adc value away Check if LEDs need updating LDAA CNT ADDA 1 STAA CNT 6 load Aacc with count 2 add 1 to Aacc 6 store new count For More Information On This Product Go to www freescale com LD1K DN1K KAKAK KAKAK KAKAK WAIT KAKAK KAKAK KAKAK I
5. LEFT gt A RIGHT gt LED DRIVER AN1233 Figure 3 Audio Frequency Analyzer System Diagram AFA Hardware Familiarity with the AFA hardware helps to understand the code used to implement the analyzer Figure 4 is a schematic of the analog front end of the AFA and Figure 5 is a schematic of the display logic For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5VA Li 10uH C8 C9 C1 C2 c3 C4 AUDIO INPUT C6 R16 1 0uF LF jour O14uF L Pee 10 133KQ LEFT i hd NE C7 R14 GND 10uF 133KQ AGND GND EY 5VA AGND ARE ADO AGND 17 R17 90 9KQ 2 V ANA R7 20ko ee R20 665kQ 6 BPip 22 3 U9 19 R4 196 R18 aoo R21 66 5ka ND 3 AAA RB 453ka i Fa R5 40 2KQ R19 107KQ 9 RE LPOC R22 2 7 ee R1 232 LPIC N V R2 226 R23 332KQ BPIB 5VA nc H4 R3 162KQ R15 12 cio L R12 Fo GND 4 7ur 4 O tu
6. AFA Software Even though hardware is required to build the AFA software running on the CPU16 performs most of the actual work Five tutorial programs must be integrated to complete the project Each program demonstrates specific functions of the AFA and each is discussed in a separate section Since this is a DSP project tuto rial discussion focuses on signal processing tasks Each of the tutorial programs must be modified in order to complete the AFA The software steps to the AFA design are listed below Acquisition of data QSPI to MC14489 interface Periodic interrupt timer routine Peak detector 1 kHz bandpass filter routine O O 5 band audio frequency analyzer AFA software is listed in Table 2 Each of the first six programs in the table corresponds to one of the soft ware steps listed above In order to organize and streamline the project each program has been designed according to a standard template for the M68HC16Z1EVB Figure 12 shows the template Table 2 AFA Project Software ADC ASM QSPI LED ASM INT TEST ASM PEAK ASM 1K FLTR ASM 5BAND SA ASM EQUATES ASM ORGO00000 ASM INITSYS ASM INITRAM ASM OUTVAL1 ASM OUTVAL2 ASM OUTVAL1 ASM and OUTVAL2 ASM are lookup tables for the LED display routines They contain values that correspond to the number of LEDs needed to reflect a given peak value For More Information On This Product Go to www free
7. 5 QUEUED TRANSMISSIONS ADC INITIALIZATION For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LOCATION F0000 CLEAR LED UPDATE COUNTER CLEAR PEAK VALUE START THE ADC READ ADC VALUE READ LED UPDATE COUNTER CHECK IF LEDS ADD 1 TO LED COUNTER NEED TO BE UPDATED TURN ON QSPI STORE ADC VALUE THE READ LED TABLE INSTRUCTION THE ADC VALUE IS USED AS THE OFFSET WHEN READING THE LED ENCODE VALUE FROM TUE LED TABLE READ LED ENCODE PEAK VALUE FROM THE LED TABLE OFFSET BY THE ADC VALUE STORE AWAY NEW ENCODED PEAK STORE NEW ENCODED PEAK TO QSPI TRANSMIT RAM For More Information On This Product Go to www freescale com Freescale Semiconductor Inc A 1 kHz Bandpass Filter 1K_FLTR ASM This code is similar in function to the peak detector except that it executes a 1 kHz IIR bandpass filter on the input signal The peak is detected and displayed on an LED bar in real time The focus is on using the MC68HC16Z1 to implement the digital filter Figure 22 is a flowchart of 1K_FLTR ASM The objective is to take incoming sampled data x n and run the bandpass filter function on the sample to produce output y n Again this is the basic black box concept of electrical engineering excite the input and watch the output change The function in the black box is defined below y n 2 fa x n x n 2 y y n 1 B y n 2
8. MOSI gt AN1233 SCHEM P2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The Analog Front End The analog front end contains all of the circuitry to condition the signal for analog to digital conversion and subsequent digital signal processing It consists of the summing circuitry for the stereo signal the anti alias ing filter and the biasing circuitry for the ADC A MAX274 low pass filter chip manufactured by the Maxim Corporation of Sunnyvale California is used to implement all of these functions The MAX274 is an eighth order programmable continuous time active filter The chip consists of four in dependent cascadable second order filter sections Each filter section can implement any all pole bandpass or lowpass filter characterized as a Butterworth Bessel or Chebyshev response Each second order sec tion is programmable with four external resistors A second order section is illustrated in Figure 6 Maxim provides an evaluation board and a software package that calculates resistor values from response speci fications input by the user This makes the MAX274 very flexible and easy to use when implementing high order anti aliasing filters LOWPASS A R2 OUTPUT BANDPASS NN INPUT RX 79 575 PF INPUT IN RY R1 amp gt R3 R4 NAN BANDPASS OUTPUT AN1233 F6 For More Information On This Product Go to www fr
9. NEW 125 Hz PEAK STORE NEW 125 Hz PEAK TO QSPI 125 Hz TRANSMIT RAM READ 500 Hz FILTER PEAK VALUE NO CLEAR C BIT IN ROTATE 500 Hz PEAK TO THE RIGHT STORE AWAY NEW 500 Hz PEAK STORE NEW 500 Hz PEAK TO QSPI 500 Hz TRANSMIT RAM READ 1 kHz FILTER PEAK VALUE 9 ROTATE 1 kHz PEAK TO THE RIGHT STORE AWAY NEW 1 kHz PEAK STORE NEW 1 kHz PEAK TO QSPI 1 kHz TRANSMIT RAM READ 4 kHz FILTER PEAK VALUE lt NO CLEAR C BIT IN CCR ROTATE 4 kHz PEAK TO THE RIGHT STORE AWAY NEW 4 kHz PEAK STORE NEW 4 kHz PEAK TO QSPI 4 kHz TRANSMIT RAM READ 10 kHz FILTER PEAK VALUE NO CLEAR C BIT IN CCR Y ROTATE 10 kHz PEAK TO THE RIGHT STORE AWAY NEW 10 kHz PEAK For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CONCLUSION This application note is intended to give designers some insight concerning the use of digital signal process ing algorithms with a microcontroller The finished project is flexible enough to permit experimenting with different filters and LED output displays DSP allows the experimenter to make on the fly changes in filter response by changing the coefficients REFERENCES The following Motorola documents are referred to in this application note e M68HC16Z1EVB User s Manual M68HC16Z1EVB D e MC68HC 1621 User s Manual MC68HC16Z1UM D CPU16 Reference Manual CPU16RM AD QSM Reference Manua
10. a 256 byte lookup table to convert an ADC reading to a LED value that can be transmitted to the 14489 ultiplies by two and Encodes to a scale of 6 3 0 35 6 9 12 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc START RAGE THESE INCLUDE FILES CONTAIN THE FOLLOWING UDE EOUATES ASM AN EQUATE FILE WITH ALL THE 21 REGISTERS DEFINED INCLUDE ORG00000 ASM RESET VECTOR INITIALIZATION INCLUDE TNITSYS ASM SYSTEM INITIALIZATION FOR THE 71 INITIALIZE INTERNAL RAM AT LOCATION F0000 STACK AT FO2FE INITIALIZE LEVEL 6 AUTOVECTOR ADDRESS INITIALIZE PIT REQUEST LEVEL 6 FILL QSPI COMMAND RAM FOR MC14489 CONFIG REGS FILL QSPI TRANSMIT RAM THIS FIRST TRANSFER INITIALIZES THE FOR MC14489 CONFIG REGS INTERNAL CONFIGURATION REGISTERS OF THE MC14489 TO HANDLE 40 LEDS TURN ON QSPI PIT VECTOR 16 15 6 mS INTERRUPT QSPI PORT INITIALIZATION ASSIGN PORT PINS TO OUTPUT QSPI SIGNALS YES FILL QSPI COMMAND RAM FOR MC14489 DISPLAY REGS QSPI INITIALIZATION MASTER MODE 16 BIT 2 10 MHz SERIAL BAUD RATE 4 QUEUED TRANSMISSIONS FILL QSPI TRANSMIT RAM FOR MC14489 DISPLAY REGS CHANGE QSPI TO 5 QUEUED TRANSMISSIONS ADC INITIALIZATION For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LOCATION F0000 CLEAR LED UPDATE COUNTER CLEAR PEAK VALUE SET SATURATION MODE INITIALIZE
11. as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e 2 freescale semiconductor For More Information On This Product Go to www freescale com
12. either the left or right AFA input The display is calibrated to the output of a CD player The CD player puts out a line level signal with 775 Vrms equal to 0 aB If the sound source is not a CD player adjust the output of the sound source so that the dynamic range of the signal is fully displayed PEAK ASM Code Listing INCLUDE EQUATES ASM table of EQUates for common register addr INCLUDE ORG00000 ASM initialize reset vector Temporary variable storage PK EQU 0200 bank FE CNT EQU 0201 bank F ORG 0200 Initialization Routines INCLUDE INITSYS ASM initially set EK F XK 0 YK 0 ZK 0 Set sys clock at 16 78 MHz disable COP RAM and Stack Initialization LDD SOOFF STD RAMBAH Store high ram array bank F LDD 0000 STD RAMBAL j store low ram array 0000 CLR RAMMCR enable ram LDAB SOF TREK Set SK to bank F for system stack LDS 02FE put SP in 1k internal SRAM Initialize level 6 autovector address LDAB 00 BEK jek extension pointer LDD JMPINT load Dacc with interrupt vector addr STD 002C Store addr to level 6 autovector KERER Initialize the PIT KERER LDAB SOF BEK jek extension pointer bankf LDD 0616 For More Information On This Product Go to www freescale com KAKAK KAKAK KAKAK GO SPIWT KAKAK KAKAK KAKAK KAKAK KAKAK KAKAK STAA STAA L
13. originating in the internal RAM will now be correctly loaded into the MC68HC16Z1 PEAK ASM reads values from a look up table in memory The file OUTVAL2 ASM contains the table Be sure this file is in the same directory as PEAK ASM before assembly 2 5 2 187 VOLTS 1 548 1 096 0 776 0 549 0 389 0 275 0 195 0 0 gt 0 195 TIME 0 275 0 389 0 549 0 776 1 096 1 548 2 187 2 5 AN1233 F19 Figure 19 Analog Input vs Peak Display Level After initializing the SRAM the ADC the QSPI and the PIT the code jumps to internal RAM at location For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Using a PIT interrupt to decrement the peak value causes the LED display to decrease slowly like a capac itor discharging when the input signal decreases rapidly This gives the display a more fluid appearance when rapidly changing peak values are measured If the display jumped from peak to peak the discontinuity would lower the aesthetic appeal In fact most commercial audio analyzers show the relative peak differ ences of the frequency spectrum rather than attempt to display the peak signal precisely To test the code hook up the system as shown in Figure 11 Input a known signal and observe the display Apply an audio signal from the sound source and watch the peak detector execute in real time If there is only one sound source output connect it to
14. 0 base addr of x n filter terms XN1_1K EQU XTRMBS 0 x n 1 XN2 1K EQU XTRMBS 2 x n 2 ORG SFO2A0 dc w 0000 lk Hz x n 1 dc w 0000 lk Hz x n 2 WEKA Addresses of filter terms for the y n terms and initialization YTRMBS EQU 02C0 base addr of y n filter terms YN1_1K EQU YTRMBS 0 y n 1 YN2_1K EQU YTRMBS 2 iy n 2 X_2_1K EQU YTRMBS 4 x n 2 stored here for mac ORG SF02CO dc w 0000 lk y n 1 dc w 0000 lk y n 2 dc w 0000 zik px xn 2 1 KERTOA Addresses of various temporary variables and initialization PKRES EQU 02E0 base addr of filter result storage PK 1K EQU PKRES S0 peak value for 1k Hz CNT EQU PKRES 1 count value for LED qspi update routine For More Information On This Product Go to www freescale com KAKAK KAKAK KAKAK KAKAK KAKAK KAKAK KAKAK KAKAK Freescale Semiconductor Inc RAM and Stack Initialization LDD SOOFF STD RAMBAH LDD 0000 STD RAMBAL CLR RAMMCR LDAB SOF TBSK LDS 02FE LDAB 00 BEK LDD JMPINT STD 002C Initialize the PIT LDAB 0F BEK LDD 0616 STD PICR LDD 0101 STD PITR ANDP SFF1F QSPI Initialization LDAA 508 STAA OPDR LDAA SOF STAA OPAR LDAA SFE STAA ODDR LDD 8004 STD SPCRO LDD 0300 STD SPCR2 LDAA SCO STAA CRO STAA CR1 STAA CR2 LDAA 40 STAA CR3 Fill LDAA 3F STD R0 1 STD R2 STD R3 1 store high ram array bank F j store low ram arra
15. 10K NOP JMP LP from look up table ithm transfer Eacc to Dacc Dacc x n x n 2 store Dacc to x n x n 2 addr load Dacc with x n 1 store x n to x n 1 and store x n 1 to x n 2 me Ne Ne me S 712 gamma 1 712 beta 2 712 alpha x n x n 2 Macc Macc 2 transfer Macc to Eacc truncate 2 multiply Eacc by 2 2 transfer Eacc to Dacc 2 no operation due to CPU pipeline 2 no operation due to CPU pipeline 6 load Aacc with the encoded LED value from scaled peak LED table me me Ne me me 6 compare value to previous peak value 6 2 branch if not more than peak value 6 store new peak value 6 store new value to 10k qspi tran ram me Ne me me 7 6 load Dacc with y n 1 9 store Eacc to y n 1 Dacc to y n 2 6 jump back to start another conversion For More Information On This Product Go to www freescale com 6 Dacc high byte gt instruction ldaa 03 KAKAK KAKAK KAKAK INT RT CK125 CK500 CK1K CK4K CK10K UPDATE DONE KAKAK JMPINT KAKAK KAKAK KAKAK KAKAK Freescale Semiconductor Inc Exceptions Interrupts PE EER This interrupt is used to decrement each LED bar value representing the peak value of each filter band PSHM DECR Stack Dac
16. 200 Initialization Routines KAKAK INCLUDE INITSYS ASM initially set EK F XK 0 YK 0 ZK 0 Set sys clock at 16 78 MHz disable COP INCLUDE INITRAM ASM initialize and turn on SRAM Set stack SK 1 SP 03FE QSPI Initialization BERR LDAA 08 STAA QPDR output 0 55 to 0 when asserted LDAA SOF STAA assign QSM port pins to qspi module LDAA SFE STAA QDDR jassign all QSM pins as outputs except miso LDD 8004 mstr womq cpol cpha 0 STD SPCRO 16 bits 2 10MHz serial baud rate LDD 0300 no interrupt generated no wrap mode STD SPCR2 newqp 0 endqp 3 queued for 4 trans Fill QSPI Command ram to write the config registers of the 14489 LDAA 5 0 STAA CRO cont 1 bitse 1 pcs0 0 no delays needed STAA CR1 STAA CR2 LDAA 40 STAA CR3 cont 0 bitse 1 pcs0 0 no delays needed Fill QSPI Transmit ram to write the config registers of the 14489 LDAA 3F STD R0 1 store 3F to tran ram registers For More Information On This Product Go to www freescale com KAKAK KAKAK Freescale Semiconductor Inc Fill QSPI Transmit ram for display registers of the 14489 The beginning LI LDD 8000 STD RO STAA R3 1 LDD 0080 STD R1 CLRD STD R2 STD R4 LDD 0400 TD SPCR2 Load up the various LED LDAA SOF STAA R4 1 LDAA 3F STAA R4 LDAA FF STAA R2 1 LDAA 3F STAA R2 LDAA 03 STAA R1 LDD 8404 STD SPCR1 BGND B
17. C ASM In order to perform digital signal processing a digital representation of the analog signal must be available The MC68HC16Z1 contains a programmable ADC module The ADC has a number of automatic conver sion modes Only four registers are needed to control the ADC Refer to the ADC Reference Manual ADCRM AD for more detailed information ADC ASM initializes the ADC module then goes into a continuous loop repeating the programmed con For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ADC ASM Code listing KAKAK ORG KAKAK KAKAK LOOP SCFSET INCLUDE EQUATES ASM INCLUDE ORG00000 ASM ORG 0200 Initialization Routines INCLUDE INITSYS ASM INCLUDE INITRAM ASM 0200 ADC Initialization LDD 0000 STD ADCMCR LDD 0003 STD ADCTLO ADC Start LDD 0000 STD ADCTL1 LDAA 80 BITA ADSTA BEQ SCFSE BRA LOOP table of EQUates for common register addr initialize reset vector KAKAK initially set EK F XK 0 YK 0 ZK 0 Set sys clock at 16 78 MHz disable COP initialize and turn on SRAM set stack SK 1 SP 03FE KAKAK turn on ADC 8 bit set sample period KAKAK j single 4 conversion single channel ADO writing to the ADCTL1 reg starts conversion check for the Sequence Complet complete if not check again go get another sample
18. DAA STAA C Fill QSPI LDAA STD STD STD Turn on t of the MC LDD STAA S LDAA S ANDA CMPA BNE S Fill QSPI LDAA STAA STAA LDAA STAA STAA LDAA STAA C 3 Freescale Semiconductor Inc R1 R2 40 R3 cont 0 bitse 1 pcs0 0 no delays needed Transmit ram to write the config registers of the 14489 5 RO 1 store 3F to tran ram registers R2 R3 the OSPI this will write to the config registers 14489 drivers 8404 PCR1 turn on spi PSR after sending data we wait until the 80 spif bit is set before we can send mor 80 check for spi done PIWT Command ram to write the display registers of the 14489 CO RO cont 1 bitse 1 pcs0 0 no delays needed R1 40 cont 0 bitse 1 pcs0 0 no delays needed R2 R4 80 cont 1 bitse 0 pcs0 0 no delays needed R3 Fill QSPI Transmit ram for display registers of the 14489 he beginning LED values will be 00 all of the LEDs will be off LDD 8000 STD RO TRO 8000 STAA R3 1 TR1 0080 LDD 0080 TR2 0000 STD R1 XX80 CLRD TRA 0000 STD R2 STD R4 LDD 0400 display registers need 5 transmissions STD SPCR2 newqp 0 endqp 4 ADC Initialization ARK sk LDD 0000 STD ADCMCR turn on ADC LDD 0003 STD ADCTLO 8 bit set sample period Initialize the extension registers for the internal ram in bank F Set up the extension registers to
19. DIGITAL SIGNAL PROCESSING FIVE INFINITE IMPULSE RESPONSE FILTERS WILL BE EXECUTED ON EACH SAMPLE WITHIN THE SAMPLING PERIOD BAND ANALYSIS EACH BAND MAGNITUDE WILL BE UPDATED WITH THE LATEST PROCESSED MAGNITUDE QSPI gt LED DISPLAY THE DATA REPRESENTING EACH BAND WILL BE SENT OUT TO THE LED ARRAY VIA QSPI AN1233 F13 Figure 13 AFA System Software Flowchart All processing must be completed within one period of the 24 95 kHz sampling frequency As shown below For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figure 14 shows the relationship between sampling periods and real time digital signal processing All cal culations and internal external housekeeping must be taken care of within the given sample period STREAM OF SAMPLING PERIODS o WRITE PEAK VALUES TURN ON QSPI GET ADC RUN 5 IIR DETECT PEAK OF TO QSPI OUTPUT PEAK VALUES VALUE DSP ROUTINES EACH FILTER TRANSMIT RAM TO LED ARRAY 668 SYSTEM CLOCK CYCLES AN1233 F14 Figure 14 AFA Sampling Period Software Design Implementation The following sections examine AFA software in detail For each of the programs there is a discussion of design and implementation a code listing and appropriate flow charts In the interest of brevity the stan dard template headers have been omitted from the listings and redundant portions of flowcharts are repro duced only once Analog to Digital Data Acquisition AD
20. E VALUES THAT ARE LOADED AND YES STORED INTO THE QSPI TRANSMIT RAM TO EXPERIMENT FILL QSPI COMMAND RAM WITH THE LED ARRAY AND THE QSPI FOR MC14489 DISPLAY REGS TO RUN THE ROUTINE AGAIN TYPE GO IN THE DEBUG WINDOW OF EVB16 FILL QSPI TRANSMIT RAM FOR MC14489 DISPLAY REGS For More Information On This Product Go to www freescale com The periodic interrupt timer PIT is an internal timer that be programmed to make an interrupt service request at specific intervals One application of the PIT is to configure it to interrupt the processor every sec Freescale Semiconductor Inc The Periodic Interrupt Timer INT_TEST ASM ond so that an interrupt service routine can update a clock INT TEST ASM produces a square wave on the port F pins of the MC68HC16Z1 The square wave has a set frequency determined by the PIT timeout period The program uses the level six autovector and the PIT times out at 15 6 ms Port F is initialized for discrete output then the code enters a wait loop until the pro grammed interval elapses The interrupt service routine creates the square wave Figure 17 is a flowchart of INT_TEST ASM For detailed information concerning interrupts the PIT and port F refer to the MC68HC 16Z1 User s Man ual MC68HC16Z1UM D the SIM Reference Manual SIMRM AD and the CPU16 Reference Manual CPU16RM AD INT_TEST ASM Code Listing KAKAK KAKAK KAKAK KAKAK INCLUDE EQ
21. F lt 10KQ 20 C13 amp C11 R13 4 7uF lt 10KQ 2M hd 45V eir R6 AGND 1 0KQ 1 2 1 2 3 4 l VRHP 3 4 VRLP 5 6 C5 5 6 7 8 1 otuF 7 8 9 10 eM 9 10 11 12 766 ADO 11 12 1 14 1 14 lt Fcsoss is 16 T 16 17 18 17 18 SCK a 19 20 19 20 4 P3 Senn AGND P2 GND MATES WITH P6 ON EVB E MATES WITH P7 ON EVB ES For More Information On This Product Go to www freescale com AN1233 SCHEM P1 Freescale Semiconductor Inc 125 Hz 500 Hz 1 kHz 4 kHz 10 kHz 1 16 1 16 1 16 1 16 1 16 2 15 2 15 2 15 2 15 2 15 3 M 1 3 w 1 3 M 1 3 4 1 1 4 138 4 138 1 4 138 14 4 4 LE 5 12 ts Ty gt l5 12 ts Ly gt Le lm 415 11 16 Ly L1 161 L1 Q 4 i 7 y 0 1 4 10 4 1 Lo 7 4 8 9 8 gt 9 4 8 9 8 gt 9 6 8 J 9 4 U1 U3 U4 U6 7 HLMP6658 HLMP6658 HLMP6658 HLMP6658 HLMP6658 e RX RX RX A B C D E F G H m O O D gt A B C D E F G H d 4 CLOCK 4 i ENABLE PCSOSS gt SCK
22. Flag START INCLUDE EQUATES ASM INCLUDE 0RG00000 ASM INCLUDE INITSYS ASM INCLUDE INITRAM ASM THESE INCLUDE FILES CONTAIN THE FOLLOWING AN EQUATE FILE WITH ALL THE Z1 REGISTERS DEFINED RESET VECTOR INITIALIZATION SYSTEM INITIALIZATION FOR THE Z1 INTERNAL RAM INITIALIZATION FOR THE Z1 Y ADC INITIALIZATION For More Information On This Product Go to www freescale com Freescale Semiconductor Inc QSPI TO MC14489 Interface QSPI_LED ASM This program illustrates QSPI serial timing and data format which must be understood in order to program the QSPI to talk to the MC14489 The QSM Reference Manual QSMRM AD and the MC 14489 data sheet are needed to understand the code QSPI_LED ASM initializes the QSPI module and the three MC14489 drivers to handle 40 LEDs After this it updates the LED array by writing to the MC14489 display registers then gives control back to the EVB16 development software Values being sent to the array may be changed either by modifying the memory locations that hold the transmitted data or by reassembling the lines that load these memory locations Fig ure 16 is a flowchart of QSPI_LED ASM QSPI_LED ASM Code Listing KAKAK KAKAK KAKAK KAKAK INCLUDE EQUATES ASM table of EQUates for common register addr INCLUDE ORG00000 ASM initialize reset vector ORG 0
23. Freescale Semiconductor Order this document by AN1233 D Using M68HC16 Digital Signal Processing To Build An Audio Frequency Analyzer By Mark Glenewinkel INTRODUCTION This application note demonstrates the use of a microcontroller unit MCU with integrated DSP capabilities The MC68HC16Z1 is a high performance 16 bit MCU that includes on chip peripheral modules and a CPU module CPU16 The CPU16 instruction set simplifies the use of digital signal processing algorithms and makes it easy to implement low bandwidth filter and control oriented applications OBJECTIVES The goal of this application note is for an engineer to learn the MC68HC16Z1 well enough to design and build an audio frequency analyzer AFA The following intermediate objectives have been defined to help reach this goal Learning the CPU16 instruction set Becoming familiar with MC68HC16Z1 modules Learning basic MCU I O hardware and software Understanding DSP system concepts with the frequency analyzer Understanding and implementing common DSP algorithms with an MCU This is a tutorial design project that follows a hands on approach to using DSP It provides concrete hard ware software applications that are used to understand and design an MCU based system utilizing DSP al Z freescale Freescale Semiconductor Inc 2004 All rights reserved semiconductor For More Information On This Product Go to www freescale com Freescale Semicond
24. INTERNAL CPU NO MODULO ADDRESSING REGISTERS FOR DSP OPERATIONS OADY REG WITH COEFF ADDRESS LOAD X REG WITH Y TERMS ADDRESS START THE ADC READ ADC VALUE DIVIDE BY 2 STORE AWAY NEW VALUE AS AD READ LED UPDATE COUNTER ADD 1 TO LED COUNTER CHECK IF LEDS STORE AWAY LED COUNTER NEED TO BE UPDATED TURN QSPI LOAD UP AND I REGISTERS For More Information On This Product Go to www freescale com Freescale Semiconductor Inc CLEAR ACCM READ AD VALUE Z X N X N 2 X N 1 X N THE DIGITAL PROCESSING ALGORITHM X N 2 X N 1 GAMMA Y N 1 MACC BETA Y N 2 MACC ALPHA 7 MACC 2 STORE DSP FILTER VALUE TO THE SELF MODIFYING CODE THE ADC VALUE IS USED AS THE OFFSET WHEN READING THE LED ENCODE VALUE READ LED ENCODE PEAK VALUE FROM THE LED TABLE FROM THE LED TABLE OFFSET BY THE ADC VALUE STORE AWAY NEW ENCODED PEAK STORE NEW ENCODED PEAK TO QSPI TRANSMIT RAM WAIT UNTIL THE 40 08 MS SAMPLING PERIOD EXPIRES For More Information On This Product Go to www freescale com Freescale Semiconductor Inc THIS INTERRUPT WILL DECREASE THE LED ENCODED PEAK VALUE FOR EACH FILTER THE DECREASED PEAK START LEVEL 6 INTERRUPT STACK D AND C REG VALUE IS THEN TRANSMITTED TO UPDATE THE LED ARRAY READ 125 Hz FILTER PEAK VALUE NO CLEAR C BIT IN CCR ROTATE 125 Hz PEAK TO THE RIGHT STORE AWAY
25. LIZE PORT F DISCRETE OUTPUT ONLY INITIALIZE PIT REQUEST LEVEL 6 PIT VECTOR 16 15 6 mS INTERRUPT NO OPERATION START LEVEL 6 INTERRUPT STACK D C AND K REG INFINITE LOOP WAITING FOR PIT INTERRUPT LEVEL 6 ONE S COMPLEMENT CREATES A SQUARE WAVE PORT F ON PORT F For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Peak Detector PEAK ASM The signal peak detector graphically measures and displays the peak amplitude of a signal in real time An audio signal is sampled at 24 95 kHz The peak amplitude of the signal is detected then a value that rep resents the peak on a bar of eight light emitting diodes LED is generated A reference value of 0 775 Vrms equivalent to 0 dB is used to relate the digital peak value to the LED display The LED bar can display a signal in the range 15 dB to 6 dB in 3 dB steps Figure 18 shows relationships between the LED bar decibels Vrms and Vp Figure 19 shows the relationship between an analog input signal and the peak val ues displayed Figure 20 is a flowchart of PEAK ASM LED BAR dB VRMS VPEAK g 6 1 548 2 187 g 3 1 096 1 548 g 0 0 775 1 096 g 3 0 549 0 775 g 6 0 389 0 549 g 9 0 275 0 389 g 12 0 195 0 275 g 15 0 138 0 195 Vin dB 20 e log 7775 OdB gt Vref 0 775Vrms Vpeak A2 e Vrms AN1233 F18 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The code
26. NT RT Freescale Semiconductor Inc Digital processing algorithm ED 2 transfer Eacc to Dacc SUBD XN2_1K 6 Dacc x n x n 2 STD X 2 6 store Dacc to x n x n 2 addr LDD XN1 1K 6 load Dacc with x n 1 STED XN1_1K 8 store x n to x n 1 and store x n 1 to x n 2 AC 252 12 gamma 1 Macc Macc AC 2 2 712 beta yn2 Macc Macc 4 4 712 alpha x n x n 2 Macc Macc ET 2 transfer Macc to Eacc truncate ASLE 2 multiply Eacc by 2 Get LED encode value from look up table E 2 transfer Eacc to Dacc STAA LD1K 3 6 Dacc high byte gt instruction ldaa 03 NOP 2 no operation due to CPU pipeline NOP 2 no operation due to CPU pipeline LDAA ED TBL 6 load Aacc with the encoded LED value from scaled peak LED table Update peak value if needed CMPA PK_1K 6 compare value to previous peak value BLS DN1K 6 2 branch if not more than peak value STAA PK 1K 6 store new peak value STAA 2 1 6 store new value to lk qspi tran ram Update y n 1 and y n 2 LDD YN1_1K 6 load Dacc with y n 1 STED YN1_1K 8 store Eacc to y n 1 Dacc to y n 2 Loop to generate calculated delay Clocks 6 8 N 1 N gt 1 is the number put into the B accumulator LDAB 3D 61 this loop will create an extra delay DECB to make a 24 95kHz sampling rate BNE WAIT 7 or a 668 cycle s
27. NTERRUPT STACK D AND C REG THIS INTERRUPT WILL DECREASE THE LED ENCODED PEAK VALUE THE DECREASED PEAK VALUE IS THEN TRANSMITTED TO UPDATE THE LED ARRAY READ PEAK VALUE YES NO CLEAR C BIT IN CCR ROTATE PEAK TO THE RIGHT STORE AWAY NEW PEAK STORE NEW PEAK TO QSPI TRANSMIT RAM TURN ON QSPI PULL D AND C REG RETURN FROM LEVEL 6 INTERRUPT AN1233 F20C Figure 22 1K_FLTR ASM Flowchart Sheet 4 of 4 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The 5 Band Audio Frequency Analyzer 5BAND_SA ASM The final design of the AFA is simple because of the groundwork that has already been done Figure 23 is a flowchart of 5BAND_SA ASM Notice that five iterations of the IIR bandpass filter are executed before control passes to the interrupt routine The five bands and their values are 125 Hz 0 5 500 Hz 1 0 1 kHz 1 5 4 kHz 1 0 and 10 kHz 0 5 Coefficient values are in the area labeled Address of coefficients at the beginning of the listing The specified Q values were chosen because they produce an appealing frequency display If sharp filters with high Q values were used the display would not show the relative differences between the bass midrange and treble frequency ranges Energy associated to one particular frequency is not the primary concern of the AFA design but rather the energy of an entire frequency band Test
28. R4 LDD 0400 display registers need 5 transmissions STD SPCR2 newqp 0 endqp 4 ADC Initialization KR KK LDD 0000 STD ADCMCR turn on ADC LDD 0003 STD ADCTLO 8 bit set sample period Initialize the extension registers for the internal ram in bank F Set up the extension registers to point to bank F LDAB SOF load b with 0F BEK transfer Bacc to Ek TBXK transfer Bacc to Xk TBYK transfer Bacc to Yk TBZK transfer Bacc to Zk JMP RAM jump to internal ram for speed Start of Internal 1K RAM ORG F0000 CLR CNT clear LED update counter CLR PK_125 clear 125 peak value CLR PK 500 clear 500 peak value CLR PK 1K clear lk peak value CLR PK AK clear 4k peak value CLR PK 10K clear 10k peak value CLRW AD clear AD Initialization for DSP ORP 50010 Set saturation mode for Macc CLRD clear Dacc TDMSK no modulo addressing LDY COEFBS 4 load with the coef base addr LDX YTRMBS 4 load x with the yterm base addr LDHI 8 load h and i multiplier and multiplicand CLRD 2 clear Date STD ADCTL1 6 single 4 conversion single channel ADO writing to the ADCTL1 reg starts conv Divide input x n by 2 no overflow problem LDAA LJSRRO 6 load Aacc with left jus signed ADC value ASRA 2 divide by 2 For More Information On This Product Go to www freescale com 10125 DN125 KAKAK F500 Freescale Semiconductor Inc
29. RA T125 ED values will be 00 all of the LEDs will be off TRO 8000 TR1 0080 TR2 0000 TR3 XX80 TR4 0000 display registers need 5 transmissions newqp 0 endqp 4 bands for experimentation 7 125 Hz band 7900 Hz band 1k Hz band 74k Hz band 10k Hz band load up d turn on QSPI go back to EVB16 software reassemble code for T125 to T10K experiment with different values branch back to TR125 line For More Information On This Product Go to www freescale com Freescale Semiconductor Inc START THESE INCLUDE FILES CONTAIN THE FOLLOWING AN EQUATE FILE WITH ALL THE Z1 REGISTERS DEFINED RESET VECTOR INITIALIZATION SYSTEM INITIALIZATION FOR THE Z1 INTERNAL RAM INITIALIZATION FOR THE Z1 INCLUDE EQUATES ASM INCLUDE ORG00000 ASM INCLUDE INITSYS ASM INCLUDE INITRAM ASM QSPI PORT INITIALIZATION ASSIGN PORT PINS TO OUTPUT QSPI SIGNALS QSPI INITIALIZATION MASTER MODE 16 BIT 2 10 MHz SERIAL BAUD RATE 4 QUEUED TRANSMISSIONS LOAD AND STORE VALUES TO FILL QSPI COMMAND RAM THE QSPI S TRANSMIT RAM TO FOR MC14489 CONFIG REGS EXPERIMENT WITH THE LED ARRAY FILL QSPI TRANSMIT RAM FOR MC14489 CONFIG REGS TURN ON QSPI THIS FIRST TRANSFER INITIALIZES THE INTERNAL CONFIGURATION REGISTERS OF THE MC14489 TO HANDLE 40 LEDS TURN ON QSPI ENTER BACKGROUND MODE Y NO WHEN BACKGROUND MODE IS ENTERED CONTROL IS GIVEN BACK TO THE EVB16 SOFTWARE CHANGE TH
30. T PSHM D CCR Stack Dacc and CCR on stack LDAA PK load Aacc with peak value BEQ DONE equal to 0 then done ANDP SFEFF clear C bit RORA rotate right once decrease peak value STAA R1 Store Aacc to all qspi tran ram STAA R2 STAA R2 1 STAA R4 STAA R4 1 STAA PK j store Aacc to peak value LDD 8404 load up Dacc STD SPCR1 turn on OSPI send LED data out DONE PULM Db CCR pull Dacc and CCR from stack RTI return from interrupt For More Information On This Product Go to www freescale com Freescale Semiconductor Inc START RAGE THESE INCLUDE FILES CONTAIN THE FOLLOWING UDE EOUATES ASM AN EQUATE FILE WITH ALL THE 21 REGISTERS DEFINED INCLUDE ORG00000 ASM RESET VECTOR INITIALIZATION INCLUDE TNITSYS ASM SYSTEM INITIALIZATION FOR THE 71 INITIALIZE INTERNAL RAM AT LOCATION F0000 STACK AT FO2FE INITIALIZE LEVEL 6 AUTOVECTOR ADDRESS INITIALIZE PIT REQUEST LEVEL 6 FILL QSPI COMMAND RAM FOR MC14489 CONFIG REGS FILL QSPI TRANSMIT RAM THIS FIRST TRANSFER INITIALIZES THE FOR MC14489 CONFIG REGS INTERNAL CONFIGURATION REGISTERS OF THE MC14489 TO HANDLE 40 LEDS TURN ON QSPI PIT VECTOR 16 15 6 mS INTERRUPT QSPI PORT INITIALIZATION ASSIGN PORT PINS TO OUTPUT QSPI SIGNALS YES FILL QSPI COMMAND RAM FOR MC14489 DISPLAY REGS QSPI INITIALIZATION MASTER MODE 16 BIT 2 10 MHz SERIAL BAUD RATE 4 QUEUED TRANSMISSIONS FILL QSPI TRANSMIT RAM FOR MC14489 DISPLAY REGS CHANGE QSPI TO
31. The signal is buffered by an op amp driver and is sent directly to the ADC module pins from the MAX274 The ADC can now properly sam ple the signal The Digital Back End The digital back end shown in Figure 5 contains all of the circuitry required to output digitally processed information to the LED array When digital signal processing is complete encoded energy levels for each band are loaded into QSPI transmit RAM then the QSPI is activated and the data is transmitted serially to the MC14489 LED drivers For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Three MC14489 drivers are used in the AFA There are five 8 bit LED arrays Two of the MC14489 chips control four banks of four diodes each and one controls two banks of four diodes each Drive current for diodes in each bank is supplied by pins A B C and D of the MC14489 The cathodes of each bank of di odes are tied together and a bank select pin sinks the current for that bank Please refer to the MC14489 Data Sheet for more information The M68HC16Z1 EVB and Development Environment The M68HC16Z1 Evaluation Board provides the capability to test and debug the audio frequency analyzer Table 1 shows development software supplied with the EVB Table 1 Development Software MASM16 EXE MASM EXE HEX EXE MASM16 HLP EVB16 EXE MASM16 software is used to edit and assemble code and EVB16 software is used to downl
32. U YTRMBS A x n 2 stored here for mac EQU YTRMBS C y n 1 EQU YTRMBS SE y n 2 EQU YTRMBS 10 x n 2 stored here for mac EQU YTRMBS 12 y n 1 EQU YTRMBS 14 y n 2 EQU YTRMBS 16 x n x n 2 stored here for mac EQU YTRMBS 18 n 1 EQU YTRMBS S1A y n 2 EQU YTRMBS 1C x n x n 2 stored here for mac ORG F02C0 dc w 0000 7125 Hz y n 1 dc w 0000 125 Hz y n 2 dc w 0000 125 Hz x n x n 2 dc w 0000 500 Hz y n 1 dc w 0000 500 Hz y n 2 dc w 0000 500 Hz x n x n 2 dc w 0000 Plk Hz y n 1 dc w 0000 lk Hz y n 2 dc w 0000 lk Hz x n x n 2 dc w 0000 74k Hz y n 1 dc w 0000 74k Hz y n 2 dc w 0000 4k Hz x n x n 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Initialization Routines INCLUDE INITSYS ASM initially set EK F XK 0 YK 0 ZK 0 Set sys clock at 16 78 MHz disable COP KORR RAM and Stack Initialization LDD 00FF STD RAMBAH Store high ram array bank F LDD 0000 STD RAMBAL Store low ram array 0000 CLR RAMMCR enable ram LDAB SOF TBSK Set SK to bank F for system stack LDS 02FE put SP in 1k internal SRAM EFTER Initialize level 6 autovector address LDAB 00 BEK jek extension pointer LDD JMPINT load Dacc with interrupt vector addr STD 002C Store addr to level 6 autovect
33. UATES ASM INCLUDE ORG Initialization Routines ORG00000 ASM 0200 INCLUDE INITSYS ASM INCLUDE INITRAM ASM table of EQUates for common register addr initialize reset vector Start program after interrupt vectors KAKAK initially set 0 YK 0 ZK 0 EK F XK Set sys clock at 16 78 initialize and turn on SRAM SP 03FE set stack SK 1 Initialize level 6 autovector address LDAB BEK LDD STD LDAB BEK LDAB STAB LDAA STAA STAA 00 INT_RT 002C Initialize PortF SOF 00 PFPAR SFF DDRF PORTFO Initialize the PIT LDD STD 50616 PICR extension pointer load Dacc with interrupt vector addr j store addr to level 6 autovector KAKAK jek extension pointer HZ bankf disable COP define port f as discrete i o define port f as all output store ff to port f KAKAK pirgl 6 piv 16 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc START INCLUDE HOUATES THESE INCLUDE FILES CONTAIN THE FOLLOWING AN EQUATE FILE WITH ALL THE 21 REGISTERS DEFINED INCLUDE 0RG00000 ASM RESET VECTOR INITIALIZATION INCLUDE INITSYS ASM SYSTEM INITIALIZATION FOR THE Z1 INCLUDE INITRAM ASM INTERNAL RAM INITIALIZATION FOR THE Z1 INITIALIZE LEVEL 6 AUTOVECTOR ADDRESS INITIA
34. ZATION For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LOCATION F0000 CLEAR LED UPDATE COUNTER CLEAR PEAK VALUE SET SATURATION MODE INITIALIZE INTERNAL CPU NO MODULO ADDRESSING REGISTERS FOR DSP OPERATIONS OADY REG WITH COEFF ADDRESS LOAD X REG WITH Y TERMS ADDRESS START THE ADC READ ADC VALUE DIVIDE BY 2 STORE AWAY NEW VALUE AS AD READ LED UPDATE COUNTER ADD 1 TO LED COUNTER CHECK IF LEDS STORE AWAY LED COUNTER NEED TO BE UPDATED TURN QSPI LOAD UP AND I REGISTERS For More Information On This Product Go to www freescale com SELF MODIFYING CODE THE ADC VALUE IS USED AS THE OFFSET WHEN READING THE LED ENCODE VALUE FROM THE LED TABLE Freescale Semiconductor Inc CLEAR ACCM READ AD VALUE Z X N X N 2 X N 1 X N THE DIGITAL PROCESSING ALGORITHM X N 2 1 GAMMA Y N 1 MACC BETA Y N 2 MACC ALPHA Z 2 MACC STORE DSP FILTER VALUE THE READ LED TABLE INSTRUCTION READ LED ENCODE PEAK VALUE FROM THE LED TABLE OFFSET BY THE ADC VALUE STORE AWAY NEW ENCODED PEAK STORE NEW ENCODED PEAK TO QSPI TRANSMIT RAM Y N 1 Y N Y N 2 Y N 1 WAIT UNTIL THE 40 08 MS SAMPLING PERIOD EXPIRES For More Information On This Product Go to www freescale com Freescale Semiconductor Inc START LEVEL 6 I
35. ampling period 486 cycles OP 2 212 JMP LP 6 jump back to start another conversion Exceptions Interrupts PEREK This interrupt is used to decrement the LED bar value representing the peak value of the 1k filter band PSHM D CCR stack and CCR on stack LDAA PK_1K load Aacc with 1K peak value BEQ DONE equal to 02 then done ANDP SFEFF clear C bit For More Information On This Product Go to www freescale com Freescale Semiconductor Inc START RAGE THESE INCLUDE FILES CONTAIN THE FOLLOWING UDE EOUATES ASM AN EQUATE FILE WITH ALL THE 21 REGISTERS DEFINED INCLUDE ORG00000 ASM RESET VECTOR INITIALIZATION INCLUDE TNITSYS ASM SYSTEM INITIALIZATION FOR THE 71 INITIALIZE INTERNAL RAM AT LOCATION F0000 STACK AT FO2FE INITIALIZE LEVEL 6 AUTOVECTOR ADDRESS INITIALIZE PIT REQUEST LEVEL 6 FILL QSPI COMMAND RAM FOR MC14489 CONFIG REGS FILL QSPI TRANSMIT RAM THIS FIRST TRANSFER INITIALIZES THE FOR MC14489 CONFIG REGS INTERNAL CONFIGURATION REGISTERS OF THE MC14489 TO HANDLE 40 LEDS TURN ON QSPI PIT VECTOR 16 15 6 mS INTERRUPT QSPI PORT INITIALIZATION ASSIGN PORT PINS TO OUTPUT QSPI SIGNALS YES FILL QSPI COMMAND RAM FOR MC14489 DISPLAY REGS QSPI INITIALIZATION MASTER MODE 16 BIT 2 10 MHz SERIAL BAUD RATE 4 QUEUED TRANSMISSIONS FILL QSPI TRANSMIT RAM FOR MC14489 DISPLAY REGS CHANGE QSPI TO 5 QUEUED TRANSMISSIONS ADC INITIALI
36. c and CCR on stack LDAA PK_125 load Aacc with 125 peak value BEQ CK500 equal to 02 then CK500 ANDP SFEFF clear C bit RORA rotate right once decrease peak value STAA TR4 1 store Aacc to 125 Hz qspi tran ram STAA PK_125 store Aacc to 125 Hz peak value LDAA PK_500 load Aacc with 500 peak value BEQ CK1K equal to 02 then 1 ANDP SFEFF clear C bit RORA rotate right once decrease peak value STAA R4 j store Aacc to 500 Hz qspi tran ram STAA PK_500 store Aacc to 500 Hz peak value LDAA PK_1K load Aacc with 1k peak value BE CK4K equal to 02 then CK4K ANDP SFEFF clear C bit RORA rotate right once decrease peak value STAA R241 Store Aacc to 1k Hz qspi tran ram STAA PK 1K Store Aacc to 1k Hz peak value LDAA PK AK load Aacc with 4k peak value BE CK10K equal to 0 then CK10K ANDP SFEFF clear C bit RORA rotate right once decrease peak value STAA TR2 store Aacc to 4k Hz qspi tran ram STAA PK_4K Store Aacc to 4k Hz peak value LDAA PK_10K load Aacc with 10k peak value BE UPDATE equal to 02 then UPDATE ANDP SFEFF clear C bit RORA rotate right once decrease peak value STAA TR1 store Aacc to 10k Hz qspi tran ram STAA PK_10K store Aacc to 10k Hz peak value LDD 58404 load up Dacc STD SPCR1 turn on OSPI send LED data out PULM D CCR pull Dacc and CCR from stack RTI return from interrupt Location of start of level 6 interrupt has to be in bank 0 ORG A000 JMP INT RT OUTVAL1 is
37. eescale com Freescale Semiconductor Inc Freescale Semiconductor Inc Anti Aliasing Filter When a signal of a given frequency is sampled at too low a rate it appears as a totally different lower fre quency at the output of the sampler This phenomenon is referred to as aliasing Aliasing occurs at a point called the folding frequency which is one half the sampling frequency In order for the frequency analyzer to be accurate sampling frequency must therefore be at least two times the highest frequency component to be sampled The ideal solution to this problem is to raise the sampling rate as high as possible but real world designs generally have a fixed upper limit on sampling frequency The most practical solution is to attenuate high frequency components of the input signal so that aliasing does not occur The anti aliasing filter correctly attenuates the high frequency components of the signal so that they are not present within the sample bandwidth The AFA has a 25 kHz sampling frequency Fs and a processing bandwidth of 10 kHz If no filter is used signal components with a frequency higher than 12 5 kHz alias at lower frequencies and the digitized sam ples represent invalid information Figure 7 shows these relationships Fs 2 is the folding frequency 12 5 kHz Frequencies that will not alias with a 25 kHz sampling frequency are to the left of Fs 2 while frequen cies that will alias are to the right of Fs 2 MAGNITUDE dB
38. ef Q 0 5 dc w 01 4 j 125 Hz alpha coef 0 0 5 dc w 7114 500 Hz gamma coef Q 1 0 dc w C798 500 Hz beta coef Q 1 0 dc w 03CB 500 Hz alpha coef Q 1 0 dc w 7257 1k Hz gamma coef Q 1 5 For More Information On This Product Go to www freescale com SZ P P 0 PS z z z z z z 2 Z zu zu zz zz WNEDNEDNWNE N H 2 2 WNE PA C4 lt PA lt lt lt HS PX lt KADA lt lt Freescale Semiconductor Inc Addresses of filter terms for the x n terms and initialization EQU 02A0 base addr of x n filter terms EQU XTRMBS 0 x n 1 EQU XTRMBS 2 x n 2 EQU XTRMBS 4 x n 1 EQU XTRMBS 6 x n 2 EQU XTRMBS 8 x n 1 EQU XTRMBS SA x n 2 EQU XTRMBS C x n 1 EQU XTRMBS SE x n 2 EQU XTRMBS 10 x n 1 EQU XTRMBS 12 x n 2 ORG SFO2A0 dc w 0000 7125 Hz X n 1 dc w 0000 125 Hz x n 2 dc w 0000 500 Hz x n 1 dc w 0000 500 Hz x n 2 dc w 0000 lk Hz x n 1 dc w 0000 lk Hz x n 2 dc w 0000 lk Hz x n 1 dc w 0000 lk Hz x n 2 dc w 0000 lk Hz x n 1 dc w 0000 lk Hz x n 2 Addresses of filter terms for the y n terms and initialization EQU 02C0 base addr of y n filter terms EQU YTRMBS 0 y n 1 EQU YTRMBS 2 y n 2 EQU YTRMBS 4 x n 2 stored here for mac EQU YTRMBS 6 7y n 1 EQU YTRMBS 8 y n 2 EQ
39. ey must be encoded The assembler does not understand fractional decimal numbers so fractional values are converted into signed 16 bit hexadecimal values When using two s complement arithmetic the most significant bit bit 15 is the sign bit and the fraction is con tained in bits 14 to 0 Fifteen bits can represent the decimal numbers from 0 to 32 767 Multiply the decimal fraction by 32 768 then convert the value to the hexadecimal equivalent Make certain that hexadecimal equivalents of negative values are in two s complement form An example is given below Decimal fraction 0 5 Multiply fractional decimal value by 32 768 0 5 32 768 16 384 Change decimal value to hexadecimal and binary values 16 384 dec 4000 hex 0100 0000 0000 0000 bin 4000 hex is the 16 bit fractional value CPU16 multiply and add instructions are used to implement the function Processing is streamlined so that in the final AFA design five filters can be implemented in the 40 08 us sampling period For a more thorough discussion of the DSP instruction set and related CPU16 architecture please consult Chapter 11 in the CPU16 Reference Manual CPU16RM AD The processing sequence is as follows The ADC value x n is divided by two to prevent overflow For More Information On This Product Go to www freescale com Freescale Semiconductor Inc As mentioned earlier the 1 kHz bandpass filter is very similar to the peak detector design Once the DSP is f
40. hether it is feasible to drill This project focuses on the frequency analysis of an audio signal A frequency analyzer is often used in au dio systems and recording studios It filters out energy levels of specific audio frequencies and displays them to indicate the frequency content of the audio signal Audio frequency analyzers are also used in con junction with equalizers to help the user define and shape the spectral characteristics of a sound source Figure 1 is a generic system diagram of a frequency analyzer based on bandpass filters The input signal is split and sent to all the filters The filters pass only specific frequency components of the input signal After filtration the strength of each passed signal is analyzed and the amount of energy in each band is repre For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1ST BAND s BANDPASS FILTER PEAK DETECT LED DRIVERS 8 COMPARISON PEAK DETECT LED DRIVERS e amp e COMPARISON ANALOG SIGNAL Af gt e NTH BAND e e BANDPASS FILTER PEAK DETECT LED DRIVERS e amp e PA COMPARISON AN1233 F1 Figure 1 Frequency Analyzer System Diagram MAGNITUDE 0048 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5V STEREO SUMMING AMPLIFIER uui ANTEACIASING Hered
41. inished on the input x n sample the peak detect algorithm is executed The include file OUTVAL1 ASM is used to encode the DSP output with an LED display value multiplied by two Be sure this file is in the same directory as 1K_FLTR ASM during assembly The best way to test this program is to connect a signal generator with sine wave sweep capability to the AFA inputs then set it to sweep from 0 to 15 kHz The 1 kHz LED bar should display the amplitude of a pure 1 kHz tone and the routine should filter out higher and lower frequency signals Since Q is equal to 1 5 some side lobe frequencies in the pass band should be evident For instance if a 2 kHz pure signal is sent into the filter the side lobe response of the 1 kHz bandpass will pass an attenuated level of the 2 kHz tone 1K_FLTR ASM Code Listing INCLUDE EQUATES ASM table of EQUates for common register addr INCLUDE ORG00000 ASM initialize reset vector KERKE Addresses of coefficients for the IIR Filters and initialization COEFBS EQU 0280 base addr of coefficients GAM_1K EQU COEFBS 0 jaddr of the gamma coef BETA_1K EQU COEFBS 2 addr of the beta coef ALPH_1K EQU COEFBS S4 addr of the alpha coef ORG SF0280 dc w 7257 lk Hz gamma coef Q 1 5 dc w C9F0 elk Hz beta coef Q 1 5 dc w 04F7 1k Hz alpha coef Q 1 5 REESE Addresses of filter terms for the x n terms and initialization XTRMBS EQU 02A
42. l QSMRM AD ADC Reference Manual ADCRM AD MC14489 Data Sheet MC14489 D These items can be obtained through a Motorola Sales Office or Literature Distribution Center Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use
43. n 1 to x n 2 MAC 2 2 12 gamma 1 MAC 2 2 12 beta yn2 Macc Macc MAC 2342 12 alpha x n x n 2 Macc Macc ET 2 transfer Macc to Eacc truncate ASLE 2 multiply Eacc by 2 Get LED encode value from look up table E 2 transfer Eacc to Dacc STAA LD500 3 6 Dacc high byte gt instruction ldaa 03 NOP 2 no operation due to CPU pipeline NOP 2 no operation due to CPU pipeline For More Information On This Product Go to www freescale com LD1K DN1K KAKAK F4K Digital processing algor Freescale Semiconductor Inc ithm ED 2 transfer Eacc to Dacc SUBD XN2_1K 6 Dacc x n x n 2 STD X 2 6 store Dacc to x n x n 2 addr LDD XN1_1K 6 load Dacc with x n 1 STED XN1_1K 8 store x n to x n 1 and store x n 1 to x n 2 AC 252 12 gamma 1 Macc Macc AC 2 2 712 beta yn2 Macc Macc 242 12 alpha x n x n 2 Macc Macc ET 2 transfer Macc to Eacc truncate ASLE 2 multiply Eacc by 2 Get LED encode value from look up table E 2 transfer Eacc to Dacc STAA LD1K 3 6 Dacc high byte gt instruction ldaa 03 NOP 2 no operation due to CPU pipeline NOP 2 no operation due to CPU pipeline LDAA ED TBL 6 load Aacc with the encoded LED value from scaled peak LED table Update peak
44. oad code to the EVB and run it EVB16 software also has debug capabilities such as trace and breakpoint Please refer to the M68HC16Z1EVB User s Manual for a list of debug features Assembling the Development Environment Assembling the development system with the AFA is simple Hook up the system as shown in Figure 11 The AFA project board connects to the M68HC16Z1EVB via P7 and P6 Use the DB25 cable to connect the parallel port of the PC to the parallel port connector of the EVB After connecting the 5 volt power supply to the M68HC16Z1EVB connect the audio signal source A CD player is the recommended source for a high quality output Split the audio source outputs so that both the AFA board and the speakers receive the sig nals audio splitters can be found at most stereo and electronics stores For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 VOLT POWER SUPPLY SERIAL CABLE a SERIAL COMM PORT EVALUATION BOARD TEES INE ASSEMBLED ami ke du AFA PROTOTYPE m ny BOARD ES 3 z M68HC16Z1EVB F lt B CD PLAYER TO LEFT AND RIGHT SPEAKERS AN1233 9 Figure 11 AFA Development System Setup For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
45. or KERER Initialize the PIT KEKER LDAB SOF BEK extension pointer bankf LDD 0616 STD PICR pirql 6 piv 16 LDD 0101 STD PITR set the periodic timer at 62 5msec ANDP SFFIF set interrupt priority to 000 Hd 3 OSPI Initialization LDAA 08 STAA QPDR output 0 55 to 0 when asserted LDAA 0F STAA jassign QSM port pins to qspi module LDAA SFE STAA QDDR assign all QSM pins as outputs except miso LDD 8004 mstr womq cpol cpha 0 STD SPCRO 16 bits 2 10MHz serial baud rate LDD 0300 no interrupt generated no wrap mode STD SPCR2 newqp 0 endqp 3 queued for 4 trans Fill QSPI Command ram to write the config registers of the 14489 LDAA 5 0 STAA CRO cont 1 bitse 1 pcs0 0 no delays needed STAA CR1 STAA CR2 LDAA 40 STAA CR3 cont 0 bitse 1 pcs0 0 no delays needed Fill QSPI Transmit ram to write the config registers of the 14489 LDAA 3F STD R0 1 store 3F to tran ram registers For More Information On This Product Go to www freescale com KAKAK KAKAK KAKAK KAKAK KAKAK KAKAK RAM LP Freescale Semiconductor Inc Fill QSPI Transmit ram for display registers of the 14489 The beginning LED values will be 00 all of the LEDs will be off LDD 8000 STD RO TRO 8000 STAA R3 1 TR1 0080 LDD 0080 TR2 0000 STD R1 XX80 CLRD TR4 0000 STD R2 STD
46. point to bank F LDAB SOF load b with SOF BEK transfer Bacc to Ek TBXK transfer Bacc to Xk For More Information On This Product Go to www freescale com Freescale Semiconductor Inc LDD 58404 6 load up d STD SPCR1 6 turn on OSPI send LED data out Get LED encode value from look up table TRAN E 2 transfer Eacc to Dacc STAA LD 3 6 Dacc high byte instruction ldaa 03 NOP 2 no operation wait for CPU pipeline NOP 2 no operation wait for CPU pipeline LD LDAA ED TBL 6 load Aacc with the encoded LED value from scaled peak LED table Update peak value if needed CMPA PK 6 compare value to previous peak value BLS DN 6 2 branch if not more than peak value STAA PK 6 store new peak value STAA R1 6 store new value to all 5 qspi tran rams STAA R2 46 STAA R2 1 106 STAA R4 6 STAA R4 1 6 Loop to generate calculated delay KEREK Clocks 6 8 N 1 N gt 1 OSD is the number put into the B accumulator DN LDAB 4B 75dec this loop will create an extra delay WAIT DECB to make a 24 95kHz sampling rate BNE WAIT or a 668 cycle sampling period 598 cycles JMP LP 6 jump back to start another conversion ERREN Exceptions Interrupts A This interrupt is used to decrement each LED bar value KZK representing the peak value of the audio signal INT_R
47. scale com Freescale Semiconductor Inc MOTOROLA INC Advanced MCU Division Austin Texas Title HC16 SOF E File Name TEMPLATE AS Description This program provides a template for all designers to use with the HC16Z1 An equate table is given The reset vector is initialized The CPU and RAM are also initialized The user can put his code in the user area block of this template History 06 05 91 Created 10 02 91 Modified comments Note This program is written for the M68HC16Z1EVB ck ck Ck ck k k ck Ck lt ck Ck k x K ck ck ck k k ck K ck x k k x ck ck ck k k ck lt x ck k k x k ck ck ck ck k k lt lt lt x k k x lt lt lt k k X lt lt k k Sk k k k k k ko ko ko INCLUDE EQUATES ASM table of EQUates for common register addr INCLUDE ORG00000 ASM initialize reset vector ORG 0200 Start program after interrupt vectors KAKAK Ini ization Routines INCL INITSYS ASM initially set EK F XK 0 YK 0 ZK 0 Set sys clock at 16 78 MHz disable COP INCL INITRAM ASM initialize and turn on SRAM set stack SK 1 SP 03FE KARK Start of user program area Figure 12 AFA Software Template For More Information On This Product Go to www freescale com Freescale Semiconductor Inc START A D DATA AQUISITION INCOMING ANALOG SIGNAL WILL BE CONTINUOUSLY SAMPLED AT A RATE OF 24 95 kHz
48. tations of signed and unsigned ADC data For 8 bit conversions there are 256 possible values Unsigned formats assume the zero voltage point is at the low ADC reference voltage with 256 steps from low to high reference Signed formats assume that the zero voltage point is halfway between the low and high ADC reference voltages The most significant bit indicates a positive or negative value 128 values represent positive voltages and 128 two s complement values represent neg ative voltages 00 represents the midpoint and FF represents midpoint minus one count SFE 5 0V 7F 5 0V CO 40 SBF 3 75V 3F 3 75V 80 00 7F 2 5V 2 5V 40 0 3F 1 25V 1 25V 00 80 ov UNSIGNED SIGNED HEXADECIMAL HEXADECIMAL REPRESENTATION REPRESENTATION AN1233 F10 Figure 10 Hexadecimal Representation of 8 Bit ADC Data The AFA uses signed 8 bit left justified ADC data The analog signal must be biased at 2 5 vdc centered between the 0 vdc and 5 vdc ADC reference voltages in order to use this representation The MAX274 is used to bias the signal The MAX274 requires two power connections Biasing circuitry consists of a voltage divider R12 R13 and decoupling capacitors C10 C13 connected to one of the MAX274 supplies The V pin is connected to analog ground The V pin is connected to the 5 volt supply The GND pin is connected to 2 5 volts This splits the supply and causes the analog signal to have a 2 5 volt DC offset
49. the code as before with the 1 kHz filter Sweep a sinusoidal tone across the frequency and watch the appropriate LED array display signal energy Apply a real time audio signal Notice the differences between the high and low ends of the audio spectrum the visible contrast between a bass drum and a cymbal 5BAND_SA ASM Code Listing INCLUDE EQUATES ASM table of EQUates for common register addr INCLUDE ORG00000 ASM initialize reset vector KZ Addresses of coefficients for the IIR Filters and initialization COEFBS EQU 0280 base addr of coefficients GAM 125 EQU 5 50 jaddr of the gamma coef BET_125 EQU COEFBS 2 addr of the beta coef ALP_125 EQU COEFBS 4 addr of the alpha coef GAM 500 EQU COEFBS S6 addr of the gamma coef BET 500 EQU COEFBS 8 addr of the beta coef ALP_500 EQU COEFBS SA addr of the alpha coef 1K EQU COEFBS SC addr of the gamma coef BET 1K EQU COEFBS SE addr of the beta coef ALP_1K EQU COEFBS 1 addr of the alpha coef EQU COEFBS 12 addr of the gamma coef BET_4K EQU COEFBS 14 addr of the beta coef ALP_4K EQU COEFBS 16 addr of the alpha coef GAM_10K EQU COEFBS 18 jaddr of the gamma coef BET_10K EQU COEFBS S1A addr of the beta coef ALP_10K EQU COEFBS 1C addr of the alpha coef ORG SF0280 dc w SCOT 125 Hz gamma coef Q 0 5 dc w C3E9 125 Hz beta co
50. uctor Inc EQUIPMENT REQUIRED The following items are needed to build and test the audio frequency analyzer AFA An IBM PC compatible computer with a parallel printer port The M68HC16Z1EVB A prototyping or wire wrap board One straight DB25 cable male on one end female on the other A 5 volt power supply An audio sound source preferably a CD player Two Y connectors to split the stereo sound source with audio cables A sinusoidal waveform generator optional O O Q gt Oscilloscope for debugging optional All of the components needed to build the AFA are shown in Figure 4 and Figure 5 the AFA schematics THE AUDIO FREQUENCY ANALYZER Spectral analysis is a method of determining the specific frequency content of a signal and the energy levels of these frequencies This information is processed by either Fourier Transform methods or by specific fil tering of the signal The information is tabulated for more analysis or displayed in a visual format One example of spectral analysis is found in oil exploration An engineer sends a known signal into the earth and then calculates the frequency content of the reflected signal This is a classic input output black box The transfer function of the black box the earth in this case yields clues to the structure beneath the sur face Different frequency responses correspond to different types of rock With spectral analysis the engi neer can decide w
51. value if needed CMPA PK_1K 6 compare value to previous peak value BLS DN1K 6 2 branch if not more than peak value STAA PK 1K 6 store new peak value STAA 2 1 6 store new value to lk qspi tran ram Update y n 1 and y n 2 LDD YN1_1K 6 load Dacc with y n 1 STED YN1_1K 8 store Eacc to y n 1 Dacc to y n 2 Start of the 4k Hz routine CLRM 2 clear Macc DE AD 6 load Eacc with AD Digital processing algorithm ED 2 transfer Eacc to Dacc SUBD XN2 4K 6 Dacc x n x n 2 STD X 2 AK 6 store Dacc to x n x n 2 addr LDD XN1 AK 6 load Dacc with x n 1 STED XN1 AK 8 store x n to x n 1 and store 1 to x n 2 MAC 2 2 712 gamma 1 Macc Macc MAC 2 2 712 beta yn2 Macc Macc MAC 2 2 12 alpha x n x n 2 Macc Macc E 2 transfer Macc to Eacc truncate ASLE 2 multiply Eacc by 2 Get LED encode value from look up table E 2 transfer Eacc to Dacc STAA LD4K 3 6 Dacc high byte gt instruction ldaa 03 NOP 2 no operation due to CPU pipeline For More Information On This Product Go to www freescale com LD10K Digital processing algor Freescale Semiconductor Inc ED SUBD XN2_10K STD X_2_10K LDD XN1_10K STED XN1_10K 2 2 2 2 2 2 ASLE Get LE ncode valu STAA _ LD10K 3 NOP NOP LDAA ED TBL Update peak value CMPA PK 10K BLS DN10K STAA PK 10K STAA TRI Update 1 and LDD YN1_10K STED YN1_
52. y 0000 enable ram set SK to bank F for system stack put SP in 1k internal SRAM Initialize level 6 autovector address jek extension pointer load Dacc with interrupt vector addr Store addr to level 6 autovector KAKAK jek extension pointer bankf pirql 6 piv 16 set the periodic timer at 62 5msec set interrupt priority to 000 KAKAK output 0 55 to 0 when asserted assign QSM port pins to qspi module assign all QSM pins as outputs except miso mstr womq cpol cpha 0 16 bits 2 10MHz serial baud rate no interrupt generated no wrap mode newqp 0 endqp 3 queued for 4 trans Fill QSPI Command ram to write the config registers of the 14489 cont 1 bitse 1 pcs0 0 no delays needed cont 0 bitse 1 pcs0 0 no delays needed OSPI Transmit ram to write the config registers of the 14489 store 3F to tran ram registers Turn on the QSPI this will write to the config registers of the MC14489 drivers For More Information On This Product Go to www freescale com KAKAK KAKAK KAKAK KAKAK KAKAK KAKAK RAM LP Freescale Semiconductor Inc Fill QSPI Transmit ram for display registers of the 14489 he beginning LED values will be 00 all of the LEDs will be off TRO 8000 TR1 0080 TR2 0000 TR3 XX80 TR4 0000 display registers need 5 transmissions newqp 0 endqp 4 KAKAK
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