Home

78K0R Microcontrollers User`s Manual for Instructions

1. C tai a sR saddr saddr byte lt saddr A addr16 A A HL N C2 M C2 C2 N I N N A HL byte lt A HL lt A HL A ES addr16 lt A ES HL A A ES HL byte A ES HL B A lt A ES HL A ES HL C A A ES HL C Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 Exceptr A a a gt o N N N Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register CKO 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus int
2. R01US0029EJO600 Rev 6 00 71 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 18 30 Operands ES HL 0 CY ES HL 1 CY ES HL 2 CY ES HL 8 CY ES HL 4 CY ES HL 5 CY ES HL 6 CY ES HL 7 CY CY 0 CY 1 CY saddr 2 CY saddr 3 CY saddr 4 CY saddr 5 CY saddr 6 CY saddr 7 CY sfr 0 CY sfr 1 CY sfr 2 CY sfr 3 CY sfr 4 CY sfr 5 CY sfr 6 CY sfr 7 CY A 0 CY 2 4 5 CY 6 CY A 7 CY PSW 0 CY PSW 1 CY PSW 2 CY PSW 3 CY PSW 4 CY PSW 5 CY PSW 6 CY PSW 7 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 72 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic CY HL O Table 5 6 List of Instruction Formats 19 30 Operands CY HL 1 CY HL 2 CY HL CY HL 4 CY HL 5 CY HL 6 CY HL 7 CY ES HL 0 CY ES HL 1 CY ES HL 2 CY ES HL 3 CY ES HL 4 CY ES HL 5 CY ES HL 6 CY ES HL 7 CY saddr 0 CY saddr 1 CY saddr
3. RO1US0029EJ0600 Rev 6 00 64 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 11 30 Mnemonic Operands saddr laddr16 HL HL byte laddr16 byte A ES addr16 A ES HL A ES HL byte A ES HL B A ES HL C ES laddr16 byte saddr laddr16 ES laddr16 X HL byte X ES HL byte AX word AX AX AX BC AX DE AX HL AX saddrp AX addr16 AX HL byte AX ES laddr16 AX ES HL byte AX word AX BC AX DE AX HL AX saddrp AX laddr16 AX HL ebyte AX ES laddr16 AX ES HL byte RO1US0029EJ0600 Rev 6 00 65 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 12 30 Operands AX word AX BC AX DE AX HL AX saddrp AX laddr16 AX HL byte AX ES laddr16 AX ES HL byte LL Ojmi iG gt saddr laddr16 HL byte ES laddr16 ES HL byte XLIII O mi mz O gt saddr laddr16 HL byte ES laddr16 ES HL byte
4. V 9 9 24 5 Sct L eni 9 2 2 Internal Program Memory Space U U u u u u u u 10 C C 5 10 2 2 2 Vector table area 11 2 2 3 CALLT instruction table area u nene ns 11 2 3 Internal Data Memory Internal RAM Space u u 12 2 4 Special Function Register SFR Area uu u u u 12 2 5 Extended SFR Second SFR Area U U U U U u u uu u u u 12 2 6 External Memory Space U u u u u u u u 13 CHAPTER 3 REGISTERS 5 14 3 1 Control Registers uuu u Sc a S uu ii 14 34 1 Program Counter I 14 31 2 Program status M 14 I 15 3 2 General Purpose Registers U 17 33 ES 3 d CS Registers eee 19 34 Sp
5. R01US0029EJ0600 Rev 6 00 62 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 9 30 Operands A saddr A laddr16 A HL A HL byte A HL B A HL C A ES addr16 A ES HL A ES HL byte A ES HL B A ES HL C A byte saddr byte A B D L H E A D A saddr laddr16 HL HL byte A ES addr16 A ES HL A ES HL byte A ES HL B A ES HL C R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 63 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 10 30 Mnemonic Operands A byte saddr byte X A A B A E D A L A H X A A A C A B A D A A saddr A laddr16 A HL A HL byte HL B A HL C A ES addr16 A ES HL A ES HL byte A ES HL B A ES HL C A byte saddr byte A X A E A D A L A H X A A A C A B A D A
6. R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 66 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 13 30 Operands AX BC DE HL saddrp laddr16 HL byte ES laddr16 ES HL byte AX BC DE HL saddrp laddr16 HL byte ES laddr16 ES HL byte A 1 A gt A 4 A 5 A 6 A 7 AX 1 AX 2 AX 3 AX 4 AX 5 AX 6 AX 7 AX 8 AX 9 AX 10 AX 11 AX 12 AX 13 AX 14 AX 15 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 67 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 14 30 Mnemonic Operands R01US0029EJ0600 Rev 6 00 68 Jan 31 2011 2ENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 15 30 Mnemonic Operands AX 3 AX 4 AX 5 AX 6 AX 7 AX 8 AX 9 AX 10 AX 11 AX 12 AX 13 AX 14 AX 15 1 1 1 1 1 1 CY saddr 0 CY saddr 1 CY saddr 2 CY saddr 3 CY
7. A ES addr16 nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte Note Exceptr A Description e The source operand src specified by the 2nd operand and the CY flag are subtracted from the destination operand dst specified by the 1st operand and the result is stored in the destination operand dst The CY flag is subtracted from the least significant bit This instruction is mainly used for subtraction of two or more bytes e If the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e f the subtraction generates a borrow out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 e f the subtraction generates a borrow for bit 3 out of bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example SUBC A HL The HL register address contents and the CY flag are subtracted from the A register and the result is stored in the A register R01US0029EJO600 Rev 6 00 109 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS And Logical Product of Byte Data Instruction format AND dst src Operation dst lt dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A HL B saddr byte A HL C A r A ES addr16
8. sfr bit 0 A bit 0 addr16 bit 0 PSW bit 0 HL bit 0 ES addr16 bit 0 ES HL bit 0 CY 1 CY CY 0 CY CY Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed N N O I M C2 C2 C2 M C2 gt M C2 C2 C2 N wo G Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by system clock control register CKO 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US
9. MOV1 A 7 CY MOV1 CY A 7 AND1 CY A 7 OR1 CY A 7 XOR1 CY A 7 SJ9 O41U090J9 A M0M94 9 HdldVHO 195 NOILONYLSNI LLOZ Le 00 9 eH 0090f36200SflL0H SVS3N32 68 BTCLR saddr 0 addr20 BTCLR A 0 addr20 BT saddr 0 addr20 BT A 0 addr20 Table 5 10 Instruction Map 4th MAP BF saddr 0 addr20 BF A 0 addr20 BTCLR saddr 1 addr20 BTCLR A 1 addr20 BT saddr 1 addr20 BT A 1 addr20 BF saddr 1 addr20 BF A 1 addr20 BTCLR saddr 2 addr20 BTCLR A 2 addr20 BT saddr 2 addr20 BT A 2 addr20 BF saddr 2 addr20 BF A 2 addr20 BTCLR saddr 3 addr20 BTCLR A 3 addr20 BT saddr 3 addr20 BT A 3 addr20 BF saddr 3 addr20 BF A 3 addr20 BTCLR saddr 4 addr20 BTCLR A 4 addr20 BT saddr 4 addr20 BT A 4 addr20 BF saddr 4 addr20 BF A 4 addr20 BTCLR saddr 5 addr20 BTCLR A 5 addr20 BT saddr 5 addr20 BT A 5 addr20 BF saddr 5 addr20 BF A 5 addr20 BTCLR saddr 6 addr20 BTCLR A 6 addr20 BT saddr 6 addr20 BT A 6 addr20 BF saddr 6 addr20 BF A 6 addr20 BTCLR saddr 7 addr20 BTCLR A 7 addr20 BT saddr 7 addr20 BT A 7 addr20 BF saddr 7 addr20 BF A 7 addr20 BTCLR sfr 0 addr20 BTCLR HL 0 addr20 BT sfr 0 addr20 BT HL 0 addr20 BF sfr 0 addr20 BF HL 0 addr20 BTCL
10. 5191101002021 YOMSZ 9 HdldVHO 195 NOILONYLSNI LLOZ Le 00 9 eH 0090 962 005 109 SVS3N32 48 ADD ADD E A Table 5 8 Instruction Map 2nd MAP ADD ADD ADD ADDW D A LA H A AX HL byte ADDC ADDC ADDC ADDC ADDC D A LA H A SUB SUB SUB SUB SUB SUBW D A LA H A AX HL byte SUBC XA SUBC SUBC SUBC SUBC D A LA HA CMP CMPW D A LA H A AX HL byte AND AND AND AND AND INC D A LA H A HL byte OR XA OR 08 OR OR OR DEC D A LA H A HL byte XOR XA XOR XOR E A IMCVV D A L A H A HL byte ADD A HL B ADD CALLT 0080h CALLT CALLT CALLT DECW 0090h 00 00B0h HL byte ADDC A HL B ADDC A HL C CALLT 0082h CALLT CALLT CALLT 0092h 00A2h 00B2h SUB A HL B SUB A HL C CALLT 0084h CALLT CALLT CALLT XCH XCH 0094h 00A4h 00B4h A saddr A HL C XCH A addr16 XCH A HL byte XCH A DE byte SUBC A HL B SUBC A HL C CALLT 0086h CALLT CALLT CALLT MOV XCH 0096h 00 6 00B6h ES saddr A HL B CMP A HL B BH addr20 CALLT 0088h CALLT CALLT CALLT skc MOV 0098h 00A8h 00B8h A HL B Movs HL b
11. nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte Note Exceptr A Description e Bit wise logical product is obtained from the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and the result is stored in the destination operand dst e If the logical product shows that all bits are 0 the Z flag is set 1 In all other cases the Z flag is cleared Description example AND FFEBAH 11011100B Bit wise logical product of FFEBAH contents and 11011100B is obtained and the result is stored at FFEBAH RO1US0029EJ0600 Rev 6 00 110 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Or Logical Sum of Byte Data Instruction format OR dst src Operation dst dst v src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A HL B saddr byte A HL C A r A ES addr16 nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte Note Exceptr A Description e The bit wise logical sum is obtained from the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and the result is stored in the destination operand dst e If the logical su
12. Description e The data of the register specified by the source operand src is saved to the stack Description example PUSH AX register contents are saved to the stack SUS REPE SSS SS Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Pop POP Pon Instruction format POP dst Operation When dst rp When dst PSW rp lt SP PSW lt SP 1 lt SP 1 SP lt SP 2 SP SP 2 Operand POP PSW rp Flag dst rp dst PSW Description e Data is returned from the stack to the register specified by the destination operand dst e When the operand is PSW each flag is replaced with stack data e None of interrupts are acknowledged between the POP PSW instruction and the subsequent instruction Description example POP The stack data is returned to the AX register R01US0029EJ0600 Rev 6 00 157 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS MOVW SP src Move wor MOVW AX SP Word Data Transfer with Stack Pointer Instruction format MOVW dst src Operation dst lt src Operand Mnemonic Operand dst src SP word SP AX AX SP HL SP BC SP Flag Description e This is an instruction to manipulate the stack pointer contents e The source operand src specified by the 2nd operand is stored in the destination operand dst specified by the
13. Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY 8 bit data XCH A ES addr16 5 3 _ A ES addr16 transfer A ES DE 3 3 lt ES DE A ES DE byte 4 3 A lt 5 DE byte A ES HL 3 3 A lt ES HL A ES HL byte 4 3 A gt ES HL byte A ES HL B 3 3 A lt gt 5 HL B A ES HL C 9 3 A lt gt ES HL C ONEB A 1 1 A lt 01H x 1 1 _ X lt 01H 1 1 _ B lt 01H 1 1 C 01H saddr 2 1 saddr lt 01H laddr16 3 1 addr16 01H ES laddr16 4 2 ES addr16 01H CLRB A 1 1 lt 00H x 1 1 _ X lt 00H B 1 1 B 00H 1 1 C lt 00H saddr 2 1 saddr 00H laddr16 3 1 addr16 00H ES laddr16 4 2 ES addr16 00H MOVS HL byte X 3 1 HL byte X x x ES HL byte X 4 2 ES HL byte X x x 16 bit MOVW rp word 3 1 word data saddrp word 4 1 _ saddrp word IPS sfrp word 4 1 _ sfrp word AX saddrp 2 1 _ AX lt saddrp saddrp AX 2 1 _ saddrp AX AX sfrp 2 1 _ AX lt sfrp sfrp AX 2 1 _ sfrp AX AX rp Nene 1 1 lt rp mee 1 1 rp AX Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 Except rp Remarks 1 One instruction clock cycle is one cycle of the CPU clock se
14. A byte A HL B saddr byte A HL C A ES addr16 nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte Note Exceptr A Description e The destination operand dst specified by the 1st operand the source operand src specified by the 2nd operand and the CY flag are added and the result is stored in the destination operand dst and the CY flag The CY flag is added to the least significant bit This instruction is mainly used to add two or more bytes If the addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e f the addition generates a carry out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared e f the addition generates a carry for bit 4 out of bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example ADDC HL B The A register contents and the contents at address HL register B register and the CY flag are added and the result is stored in the A register R01US0029EJO600 Rev 6 00 107 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Subtract Byte Data Subtraction Instruction format SUB dst src Operation dst lt dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A b
15. CPU conirol instructions SEL RBn 181 NOP 182 EI 183 DI 184 HALT 185 STOP 186 SIL a Y Jan 31 2011 RENESAS 78 Microcontrollers APPENDIX B INSTRUCTION INDEX MNEMONIC IM ALPHABETICAL ORDER APPENDIX B INSTRUCTION INDEX MNEMONIC IN ALPHABETICAL ORDER A ADD 106 ADDC 107 ADDW 117 ADDW SP byte 159 AND 110 AND1 142 B 8C 164 171 BH 168 BNC 165 BNH 169 BNZ 167 BR 162 151 170 BTCLR 172 BZ 166 CALL 149 CALLT 150 146 CLRB 97 CLRW 104 CMP 113 CMPO 114 CMPS 115 CMPW 119 D DEC 124 DECW 126 DI 184 E El 183 R01US0029EJ0600 Rev 6 00 Jan 31 2011 H HALT 185 INC 123 INCW 125 M MOV 93 141 MOVS 98 MOVW 100 MOVW AX SP 158 MOVW SP src 158 MULU 121 N 182 NOTI 144 96 ONEW 103 OR 111 OR1 143 P POP 157 PUSH 156 R RET 152 RETB 154 RETI 153 ROL 136 ROLC 138 ROLWC 139 193 RENESAS 78 Microcontrollers APPENDIX B INSTRUCTION INDEX MNEMONIC IM ALPHABETICAL ORDER ROR 142 RORC 137 S SAR 132 SARW 133 SEL RBn 181 SET1 145 SHR 128 SHRW 129 SHL 130 SHLW 131 SKC 174 SKH 178 SKNC 1
16. N N AX rp rp AX AX 0001H BC BC lt 0001H AX AX 0000H BC BC 0000H 8 bit operation A byte A CY A byte saddr byte saddr CY lt saddr byte A CY lt lt A lt A saddr A A addr16 A CY lt HL rA A saddr laddr16 A HL A HL byte A HL B A HL C A ES addr16 A ES HL A ES HL byte A CY HL byte A CY A HL B A CY A HL C A CY ES addr16 A CY A ES HL A CY lt ES HL byte A ES HL B A CY A ES HL B A ES HL C A CY A ES HL C When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access When the program memory area is accessed Except rp 17 Except r jas rR KR RT HR N S N Remarks 1 One m clock cycle is one cycle of the CPU clock selected by the system clock control register 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area
17. R01US0029EJ0600 Rev 6 00 60 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 7 30 Operands L A H A A saddr A addr16 A HL A HL byte A HL B A HL C A ES addr16 A ES HL A ES HL byte A ES HL B A ES HL C A byte saddr byte A B L H D A L A H A A saddr A laddr16 A HL A HL byte A HL B A HL C A ES laddr16 A ES HL A ES HL byte A ES HL B A ES HL C R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 61 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 8 30 Mnemonic Operands A byte saddr byte A X D L A A D A A saddr A addr16 A HL A HL byte A HL B A HL C A ES addr16 A ES HL A ES HL byte A ES HL B A ES HL C A byte saddr byte A X D L H X A A A C A B A E A D A
18. rp SP word SP AX AX SP HL SP BC SP DE SP SP byte SP byte Unconditio AX nal branch addr20 addr20 laddr16 lladdr20 Conditional addr20 branch addr20 addr20 addr20 addr20 addr20 saddr bit addr20 sfr bit addr20 A bit addr20 PSW bit addr20 HL bit addr20 ES HL bit addr20 SP lt word SP AX AX SP HL SP BC SP DE SP SP lt SP byte SP lt SP byte 3 lt CS 3 PC lt PC 2 jdisp8 3 PC lt PC 3 jdisp16 3 3 PC lt 0000 addr16 PC lt addr20 294 PC lt PC 2 jdisp8 if CY 1 2 4 PC lt PC 2 jdisp8 if CY 0 PSD PC lt PC 2 jdisp8 if Z 1 jme PC lt PC 2 jdisp8 if Z 0 20 lt PC 3 jdisp8 if Z v CY 0 paie lt PC 3 jdisp8 if Z v CY 3 5 PC lt PC 4 jdisp8 if saddr bit 1 ga PC 4 jdisp8 if sfr bit 1 85 PC lt PC 3 jdisp8 if A bit 1 gj PC lt PC 4 jdisp8 if PSW bit 1 oe PC lt PC 3 jdisp8 if HL bit 1 ales PC lt PC 4 jdisp8 if ES HL bit 1 Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 This indicates the number of clocks when condition is met when condition is met Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the
19. CALLT addr5 Description e This is a subroutine call for call table reference e The start address PC 2 of the next instruction is saved in the stack and is branched to the address indicated with the word data of a call table specify the even addresses of 00080H to OOOBFH with the higher 4 bits of the address fixed to 0000B and the lower 16 bits indicated with addr5 Description example CALLT 80H Subroutine call to the word data addresses 00080H and 00081H Remark Only even numbered addresses can be specified odd numbered addresses cannot be specified addr5 Immediate data or label from 0080H to even numbered addresses only 16 bit even addresses of 0080H to OOBFH with bits 15 to 6 fixed to 0000000010B bit 0 fixed to OB and the five bits of bits 5 to 1 varied R01US0029EJO600 Rev 6 00 150 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Break Software Vectored Interrupt Instruction format BRK Operation SP 1 lt PSW SP 2 lt PC 2 s SP 3 lt 2 SP 4 lt PC 2 L PCs lt 0000 PCH lt 0007FH PCL lt 0007FH SP lt SP 4 IE lt 0 None Flag Description e This is a software interrupt instruction e PSW and the next instruction address PC 2 are saved to the stack After that the IE flag is cleared 0 and the saved data is branched to the address indicated with the word data a
20. Internal expansion RAM area is 14 KB max fetch Second SFR area name changed is 2 KB max enabled from F0000H to F07FFH Area 1 area 2 and area 3 are from F800H to Supports external expansion memory FAFFH fixed The external expansion memory space can be Supports external expansion memory allocated from the product mounted flash memory area to EDFFFH R01US0029EJ0600 Rev 6 00 9 Jan 31 2011 RENESAS lt R gt 78KOR Microcontrollers 2 2 Internal Program Memory Space CHAPTER 2 MEMORY SPACE In the 78KOR microcontrollers the program memory space s address range is from 00000 to EFFFFH For description of the internal ROM flash memory maximum size refer to the user s manual for each product Caution Do not use relative addressing in branch instructions from internal program memory space to RAM space or external memory space 2 2 1 Mirror area In the 78KOR microcontrollers the data flash areas from 00000H to OFFFFH when 0 and from 10000H to 1FFFFH when MAA 1 are mirrored to the addresses from F0000H to FFFFFH By reading data from F0000H to FFFFFH an instruction that does not have the ES registers as an operand can be used and thus the contents of the data flash can be read with the shorter code However in this case the data flash area is not mirrored to the SFR extended SFR second SFR RAM and use prohibited areas Mirror areas can only be read and instruction f
21. MOV sfr A MOV addr16 A 16 IMCVV X IMCVV laddr16 INCW BC INC saddr INCW DE INCW saddrp MOVW AX SP byte MOVW AX DE MOVW AX DE byte MOVW AX HL MOVW AX HL byte MOVW AX saddrp MOVW AX sfrp MOVW AX addr16 DEC 16 DECW AX DECW laddr16 DECW BC DEC saddr DECW DE DECW saddrp MOVW SP byte AX MOVW DE AX MOVW DE byte AX MOVW HL AX MOVW HL byte AX MOVW saddrp AX MOVW sfrp AX MOVW 16 PUSH AX POP BC PUSH BC POP DE PUSH DE POP HL MOV SP byte byte MOVW saddrp word MOV DE byte byte MOVW sfrp word MOV HL byte byte MOV saddr byte MOV sfr byte MOV addr16 byte CMPO CMPO A CMPO C saddr CMP0 laddr16 MULU x MOV X saddr MOV X addr16 MOVW BC saddrp MOVW BC addr16 BC addr20 BZ addr20 BNC addr20 BNZ addr20 ONEB ONEB ONEB ONEB saddr ONEB laddri 6 ONEW AX MOV B saddr MOV B addr16 MOVW DE saddrp MOVW DE addr16 BR 20 BR laddr16 BR 20 8 20 CL 8 saddr CLRB laddr16 CLRW AX MOV C saddr MOV C addri6 MOVW HL saddrp MOVW HL addr16 CALL 20 CALL laddr16 CALL addr20
22. SUBC saddr byte SUBC A saddr SUBC A byte SUBC A HL SUBC A HL byte SUBC A addr16 CMP addr16 byte MOV ES byte CMPW AX addr16 CMPW AX BC CMPW AX word CMPW AX DE CMPW AX saddrp MOV word BC A MOV A word BC CMP saddr byte CMP A saddr CMP A byte A HL CMP A HL byte CMP A addr16 MOV X byte MOV A byte MOV C byte MOV B byte MOV E byte MOV D byte MOV L byte MOVW word B AX MOVW AX word B AND saddr byte AND A saddr AND A byte AND A HL AND A HL byte AND A addr16 MOV A X 2nd MAP MOV MOV M0V M0V A D MOV A L MOVW word C AX MOVW AX word C OR saddr byte OR A saddr OR A byte OR A HL OR A HL byte OR A addr16 MOV MOV M0V B A MOV MOV DA MOV MOVW word BC AX MOVW AX word BC XOR saddr byte XOR A saddr XOR A byte XOR A HL XOR A HL byte XOR A addr16 INC INC A INC C IMC 8 IMC E INC D INC L MOV A SP byte MOV A DE MOV A DE byte MOV A HL MOV A HL byte MOV A saddr MOV A sfr MOV A addr16 DEC A DEC C DEC B DEC E DEC D DEC L MOV SP byte A MOV DE A MOV DE byte A MOV HL A MOV HL byte A MOV saddr A
23. ES HL C A ES word B byte A ES word B ES word B A ES word C byte A ES word C ES word C A ES word BC byte A ES word BC ES word BC A B ES laddr16 C ES laddri6 X ES laddr16 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 93 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Flag PSW byte and PSW A operands All other operand combinations Description e The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand e No interrupts are acknowledged between the MOV PSW byte instruction MOV PSW A instruction and the next instruction Description example MOV A 4DH 4DH is transferred to the A register SU Rer rv sOsNO z lt Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Exchange Byte Data Transfer Instruction format XCH dst src Operation dst lt gt src Operand Mnemonic Operand dst src Mnemonic Operand dst src HL C A ES laddr16 A sfr A ES DE A laddr16 A ES DE byte A DE A ES HL A DE byte A ES HL byte A HL A ES HL B A HL byte A ES HL C A HL B Note Exceptr A Flag Description e Th
24. M C2 C2 N gt N N N A A x HL byte A lt HL B A A x HL C A lt ES addr16 A A x ES HL A lt A x ES HL byte A ES HL B lt A x ES HL B A ES HL C A lt A x ES HL C Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 Exceptr A a a gt o N N N Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register CKO 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access
25. 4 2 8 Based indexed 32 4 2 9 Stack addressing u U u 33 R01US0029EJ0600 Rev 6 00 Jan 31 2011 st eN6 s lt sAS CHAPTER 5 INSTRUCTION SET U U U U u uu uuu 34 5 1 Operand Identifiers and Description 34 5 2 Symbols in Operation Column U u uu uu uu 36 5 3 Symbols in Flag Column 37 37 5 5 Operation Sr E 38 5 6 Instruction Format reete tre een ERN RENIMAE 55 5 7 Instruction Maps q 85 CHAPTER 6 EXPLANATION OF INSTRUCTIONS J nennen nnn nnne nn nnne 90 6 1 8 bit Data Transfer Instructions u u 92 6 2 16 bit Data Transfer Instructions u J 99 6 3 8 bit Operation Instructions J u u nnne u nnn u u u u J J 105 6 4 16 bit Operation
26. 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Multiply Unsigned Unsigned Multiplication of Data Instruction format MULU src Operation AX lt Axsrc Operand Flag Description e The A register contents and the source operand src data are multiplied as unsigned data and the result is stored in the AX register Description example MULU X The A register contents and the X register contents are multiplied and the result is stored in the AX register R01US0029EJO600 Rev 6 00 121 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 6 Increment Decrement Instructions The following instructions are increment decrement instructions INC 123 DEC 124 INCW 125 DECW 126 SI a a n Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Increment Byte Data Increment Instruction format INC dst Operation dst dst 1 Operand Mnemonic Operand dst r saddr laddr16 HL byte ES laddr16 ES HL byte Description e The destination operand dst contents are incremented by only one e If the increment result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 f the increment generates a carry for bit 4 out of bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 e Because this instruction is frequently u
27. B 2 2 lt HL B A HL C 2 2 A gt HL C Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 Exceptr A Remarks 1 One instruction clock cycle is one cycle of the CPU clock selected by the system clock control register 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data RO1US0029EJ0600 Rev 6 00 40 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 4 17
28. CLKOUT Wait Cycles fctx 3 clocks ICLM 2 5 or 6 clocks ICLM 3 7 to 9 clocks ICL 4 9 to 12 clocks lt R gt Caution The flash memory and external memory are located in consecutive spaces but start fetching in the external memory space by using a branch instruction CALL or BR excluding the relative addressing in the flash memory or RAM memory Remark 1 clock 1 CPU clock R01US0029EJ0600 Rev 6 00 Jan 31 2011 2 gt 1 189 78 Microcontrollers CHAPTER 7 PIPELINE 7 2 5 Hazards related to combined instructions If the data of the register contents is indirectly accessed immediately after the writing to the register that is to be used for the indirect access a one clock wait is inserted Register Name Previous Instruction Next Instruction Operand or Instruction DE Write instruction to D register DE DE byte Write instruction to E register Write instruction to DE register SEL RBn Note HL Write instruction to H register HL HL byte HL B HL C HL bit Write instruction to L register Write instruction to HL register Note SEL B Write instruction to B register Word B HL B SEL RBn Write instruction to C register Word C HL C SEL 8C Write instruction to B register Word BC HL B HL C Note Write instruction to C register Write instruction to BC register Note SEL RBn SP MOVW SP wor
29. In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJO600 Rev 6 00 43 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 7 17 Instruction Mnemonic Operands Clocks Operation Group Note 1 Note 2 8 bit A byte A CY A byte CY operation saddr byte saddr CY saddr byte CY A r A CY amp A r CY r A r CY lt r A CY A saddr A saddr CY A laddr16 addr16 CY HL A CY lt HL CY A HL byte A CY A HL byte CV A HL B A CY A HL B CY A HL C A CY A HL C CY A ES addr16 A CY A ES addr16 CV A ES HL A CY A ES HL CY A ES HL byte A CY A ES HL byte A ES HL B A CY A ES HL B CV A ES HL C A CY A ES HL C CY A byte A CY A byte saddr byte
30. Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if Not Zero Conditional Branch with Zero Flag Z 0 Instruction format BNZ addr20 Operation PC lt PC 2 jdisp8 if Z 0 Operand Operand addr20 Description e When Z 0 data is branched to the address specified by the operand When Z 1 no processing is carried out and the subsequent instruction is executed Description example CMP A 55H BNZ 00A39H If the A register is not 55H data is branched to 00A39H with the start of this instruction set in the range of addresses 009B8H to 00AB7H R01US0029EJO600 Rev 6 00 167 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS BH Branch if Higher than Conditional branch by numeric value comparison Z v CY 0 Instruction format BH addr20 Operation PC lt PC 3 jdisp8 if Z v CY 0 Operand Operand addr20 Description e When Z v CY 0 data is branched to the address specified by the operand When Z v CY 1 no processing is carried out and the subsequent instruction is executed e This instruction is used to judge which of the unsigned data values is higher It is detected whether the first operand is higher than the second operand in the CMP instruction immediately before this instruction Description example CMP A C BH 00356H Branch to address 00356H when the A register contents are greater th
31. Modification of Example 1 2 in 2 2 1 Mirror area Modification of Note in Table 5 5 Operation List Modification of operand description order of CALL and BR instructions in Table 5 5 Operation List CHAPTER 2 MEMORY SPACE CHAPTER 5 INSTRUCTION SET Addition of operands to DEC instruction in CHAPTER 6 EXPLANATION OF INSTRUCTIONS Modification of operand description order of CALL and BR instructions in CHAPTER 6 EXPLANATION OF INSTRUCTIONS Modification of Instruction format of BR instruction in CHAPTER 6 EXPLANATION OF INSTRUCTIONS CHAPTER 6 EXPLANATION OF INSTRUCTIONS Ath edition Addition of description to 2 4 Special Function Register SFR Area Addition of description to 2 5 Extended SFR Second SFR Area CHAPTER 2 MEMORY SPACE Addition of addr5 to Table 5 2 Symbols in Operation Column Modification of Remarks 1 in Table 5 5 Operation List Change of operation in CALLT instruction CHAPTER 5 INSTRUCTION SET Change of Operation Description and Remark in CALLT instruction Change of Description and Caution in RETI instruction CHAPTER 6 EXPLANATION OF INSTRUCTIONS R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 196 78KOR Microcontrollers APPENDIX C REVISION HISTORY Edition 5th edition Description Chapter Change of 2 2 1 Mirror area CHAPTER 2 Change of description in 2 3 Internal Data Memory Internal RAM Space
32. ONEW 103 CLRW 104 8 bit operation instructions ADD 106 ADDC 107 SUB 108 SUBC 109 AND 110 OR 111 XOR 112 CMP 113 114 CMPS 115 16 bit operation instructions ADDW 117 SUBW 118 CMPW 119 R01US0029EJ0600 Rev 6 00 Jan 31 2011 Multiply instruction MULU 121 Increment decrement instructions INC 123 DEC 124 INCW 125 DECW 126 Shift instructions SHR 128 SHRW 129 SHL 130 SHLW 131 SAR 132 SARW 133 Rotate Instructions ROR 135 ROL 136 RORC 137 ROLC 138 ROLWC 139 Bit manipulation instructions MOV1 141 AND1 142 OR1 143 XOR1 144 145 CLR1 146 147 Call return instructions CALL 149 CALLT 150 BRK 151 RET 152 RETI 153 RETB 154 191 RENESAS 78 Microcontrollers APPENDIX INSTRUCTION INDEX MNEMONIC BY FUNCTION Stack manipulation instructions PUSH 156 POP 157 MOVW SP src 158 MOVW AX SP 158 ADDW SP byte 159 SUBW SP byte 160 Unconditional branch instruction BR 162 Conditional branch instructions 164 BNC 165 BZ 166 BNZ 167 BH 168 BNH 169 170 BF 171 BTCLR 172 Conditional skip instructions SKC 174 SKNC 175 SKZ 176 SKNZ 177 SKH 178 SKNH 179
33. Operation List 3 17 Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY 8 bit data MOV A ES HL 2 2 5 A ES HL transfer ES HL A 2 2 ES lt ES HL byte byte 4 2 _ ES HL byte byte A ES HL byte 3 2 5 lt ES HL byte ES HL byte A 3 2 _ ES HL byte A A ES HL B 8 2 5 ES HL B ES HL 3 2 _ ES HL B A A ES HL C 3 2 5 lt ES HL C ES HL C A 3 2 _ ES HL C A ES word B byte 5 2 _ ES B word byte A ES word B 4 2 5 lt ES B word ES word B A 4 2 _ ES B word A ES word C byte 5 2 _ ES C word byte A ES word C 4 2 5 lt ES C word ES word C 4 2 _ ES C word A ES word BC byte 5 2 _ ES BC word byte A ES word BC 4 2 5 A lt ES word ES word BC A 4 2 _ ES BC word A ES laddr16 4 2 B ES addr16 C ES laddr16 4 2 5 lt ES addr16 X ES addr16 4 2 5 X lt ES addr16 XCH we n 1 Accor 2 other than saddr 3 2 _ lt saddr sfr 3 2 _ lt sfr A addr16 4 2 lt addr16 2 2 _ lt DE DE byte 3 2 _ lt DE byte A HL 2 2 gt HL A HL byte 3 2 _ A HL byte A HL
34. PC Program counter SP Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag 0 Memory contents indicated by address register contents parentheses XL 16 bit registers higher 8 bits XL lower 8 bits Xs XL 20 bit registers Xs bits 19 to 16 XH bits 15 to 8 XL bits 7 to 0 A Logical product AND v Logical sum OR Exclusive logical sum exclusive Inverted data addr5 16 bit immediate data even addresses only in 0080H to 00BFH addr16 16 bit immediate data addr20 20 bit immediate data jdisp8 Signed 8 bit data displacement value jdisp16 Signed 16 bit data displacement value R01US0029EJ0600 Rev 6 00 36 Jan 31 2011 st eN6 s lt sAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET 5 3 Symbols in Flag Column The change of the flag value when the instruction is executed is shown in the Flag column using the following symbols Table 5 3 Symbols in Flag Column Symbol Change of Flag Value Unchanged Cleared to 0 Setto 1 Set cleared according to the result Previously saved value is restored 5 4 PREFIX Instruction Instructions with ES have a PREFIX operation code as a prefix to extend the accessible data area to the 1 MB space 00000H to FFFFFH by adding the ES register value to the 64 KB space fr
35. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers o
36. saddr CY lt saddr byte A r A CY A r rA CY r A saddr A CY A saddr A laddr16 A CY A addr16 A HL A CY A HL A HL byte A CY A HL byte A HL B A CY lt A HL B A HL C A CY A HL A ES laddr16 A CY A ES addr16 A ES HL A CY A ES HL A ES HL byte A CY A ES HL byte A ES HL B A CY lt A ES HL B A ES HL C A CY A ES HL C Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 Exceptr A C a O gt N C2 M C2 N I N N C a gt gt o N N N Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register CKO 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to t
37. 00000H Memory R01US0029EJ0600 Rev 6 00 28 Jan 31 2011 st eN6 s lt sAS 78 Microcontrollers CHAPTER 4 ADDRESSING 4 2 7 Based addressing Function Based addressing uses the contents of a register pair specified with the instruction word as a base address and 8 bit immediate data or 16 bit immediate data as offset data The sum of these values is used to specify the target address Operand format Identifier Description HL byte DE byte SP byte only the space from F0000H to FFFFFH is specifiable word B word C only the space from F0000H to FFFFFH is specifiable word BC only the space from F0000H to FFFFFH is specifiable ES HL byte ES DE byte higher 4 bit addresses are specified by the ES register ES word B ES word C higher 4 bit addresses are specified by the ES register ES word BC higher 4 bit addresses are specified by the ES register Figure 4 14 Example of SP byte FFFFFH OP code F0000H byte Memory lt R gt Caution In HL byte DE byte word B word C and word BC an added value must not exceed FFFFH In ES HL byte ES DE byte ES word B ES word C and ES word BC an added value must not exceed FFFFFH For SP byte an SP value must be within RAM space and the added value of SP byte must be FFEDFH or less in RAM space R01US0029EJ0600 Rev 6 00 29 Jan 31 2011 st eN6 s lt sAS
38. 2 CY saddr 3 CY saddr 4 CY saddr 5 CY saddr 6 CY saddr 7 CY sfr 0 CY sfr 1 CY sfr 2 CY sfr 3 CY sfr 4 CY sfr 5 CY sfr 6 CY sfr 7 CY 0 CY CY 2 CY CV 4 CY A 5 CY A 6 CY A 7 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 73 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 20 30 Operands CY PSW 0 CY PSW 1 CY PSW 2 CY PSW 3 CY PSW 4 CY PSW 5 CY PSW 6 CY PSW 7 CY HL O CY HL 1 CY HL 2 CY HL 3 CY HL 4 CY HL 5 CY HL 6 CY HL 7 CY ES HL 0 ES HL 1 CY ES HL 2 CY ES HL 3 CY ES HL 4 CY ES HL 5 CY ES HL 6 CY ES HL 7 CY 0 CY 1 CY saddr 2 CY saddr 3 CY 4 CY saddr 5 CY saddr 6 CY saddr 7 CY sfr O CY sfr 1 CY sfr 2 CY sfr 3 CY sfr 4 CY sfr 5 CY sfr 6 CY sfr 7 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 74 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 21 30 Mnemonic Operands CY A 0
39. 2 of port 2 is 0 data is branched to address 01549H with the start of this instruction set in the range of addresses 014C6H to 015C5H RO1US0029EJ0600 Rev 6 00 171 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if True and Clear Conditional Branch and Clear by Bit Test Byte Data Bit 1 Instruction format BTCLR bit addr20 Operation PC lt PC b jdisp8 if bit 1 then bit lt 0 Operand Mnemonic Operand bit addr20 b Number of bytes saddr bit addr20 sfr bit addr20 A bit addr20 PSW bit addr20 HL bit addr20 ES HL bit addr20 Flag bit PSW bit In all other cases z x s Description e If the 1st operand bit contents have been set 1 they are cleared 0 and branched to the address specified by the 2nd operand If the 1st operand bit contents have not been set 1 no processing is carried out and the subsequent instruction is executed e When the 1st operand bit is PSW bit the corresponding flag contents are cleared 0 e All interrupt requests are not acknowledged between the BTCLR PSW bit addr20 instruction and the next instruction Description example BTCLR PSW 0 00356H When bit 0 CY flag of PSW is 1 the CY flag is cleared to 0 and branched to address 00356H with the start of this instruction set in the range of addresses 002D4H to 003D3H RO1US0029EJ0600 Rev 6
40. 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Exclusive Or Single Bit 1 Bit Data Exclusive Logical Sum Instruction format XOR1 dst src Operation dst dst src Operand Mnemonic Operand dst src CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY ES HL bit Flag Description e The exclusive logical sum of bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand is obtained and the result is stored in the destination operand dst e The operation result is stored in the CY flag because of the destination operand dst Description example XOR1 CY 7 The exclusive logical sum of the A register bit 7 and the CY flag is obtained and the result is stored in the CY flag R01US0029EJO600 Rev 6 00 144 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Set Single Bit Carry Flag 1 Bit Data Set Instruction format SET1 dst Operation dst lt 1 Operand Mnemonic Operand dst saddr bit sfr bit A bit laddr16 bit PSW bit HL bit ES laddr16 bit ES HL bit Flag dst PSW bit dst CY In all other cases Description e The destination operand dst is set 1 e When the destination operand dst is CY or PSW bit only the correspondin
41. 3 addr20 PSW 4 addr20 PSW 5 addr20 PSW 6 addr20 PSW 7 addr20 HL 0 addr20 HL 1 addr20 HL 2 addr20 HL 3 addr20 HL 4 addr20 HL 5 addr20 HL 6 addr20 HL 7 addr20 ES HL 0 addr20 ES HL 1 addr20 ES HL 2 addr20 ES HL 3 addr20 ES HL 4 addr20 ES HL 5 addr20 ES HL 6 addr20 ES HL 7 addr20 saddr 0 addr20 saddr 1 addr20 saddr 2 addr20 saddr 3 addr20 saddr 4 addr20 saddr 5 addr20 saddr 6 addr20 saddr 7 addr20 RO1US0029EJ0600 Rev 6 00 81 Jan 31 2011 RENESAS 78KOR Microcontrollers Mnemonic CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 28 30 Operands sfr 0 addr20 sfr 1 addr20 sfr 2 addr20 sfr 3 addr20 sfr 4 addr20 sfr 5 addr20 sfr 6 addr20 sfr 7 addr20 A 0 addr20 A 1 addr20 A 2 addr20 A 3 addr20 A 4 addr20 A 5 addr20 A 6 addr20 A 7 addr20 PSW 0 addr20 PSW 1 addr20 PSW 2 addr20 PSW 3 addr20 PSW 4 addr20 PSW 5 addr20 PSW 6 addr20 PSW 7 addr20 HL 0 addr20 HL 1 addr20 HL 2 addr20 HL 3 addr20 HL 4 addr20 HL 5 addr20 HL 6 addr20 HL 7 addr20 E
42. 78K0R Microcontrollers CHAPTER 4 ADDRESSING Figure 4 15 Example of HL byte DE byte FFFFFH rp HL DE Memory Figure 4 16 Example of word B word C FFFFFH OP code F0000H Low Addr High Addr Memory Figure 4 17 Example of word BC FFFFFH OP code F0000H Low Addr High Addr Memory R01US0029EJ0600 Rev 6 00 30 Jan 31 2011 st eN6 s lt sAS 78K0R Microcontrollers CHAPTER 4 ADDRESSING Figure 4 18 Example of ES HL byte ES DE byte FFFFFH 4 Y 00000H Figure 4 19 Example of ES word B ES word C FFFFFH i 00000H Memory Figure 4 20 Example of ES word BC FFFFFH n 00000H RO1US0029EJ0600 Rev 6 00 31 Jan 31 2011 ztENESAS 78K0R Microcontrollers CHAPTER 4 ADDRESSING 4 2 8 Based indexed addressing Function Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address and the content of the B register or C register similarly specified with the instruction word as offset address The sum of these values is used to specify the target address Operand format Identifier Description HL B HL C only the space from F0000H to FFFFFH is specifiable ES HL B ES HL C higher 4 bit addresses are specified by the ES register Figure 4 21 Example of HL B HL C FFFFFH F0000H Memory Figure 4 22 Example of
43. A bit CY PSW bit CY HL bit CY CY ES HL bit ES HL bit CY CY lt saddr bit CY lt sfr bit CY lt A bit CY lt PSW bit CY lt HL bit saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY CY ES HL bit ES HL bit lt CY CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY ES HL bit CY lt CY saddr bit CY lt CY sfr bit CY CY A bit CY lt CY PSW bit CY lt CY HL bit CY lt CY ES HL bit CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY ES HL bit CY CY v saddr bit CY lt CY v sfr bit CY CY v A bit CY lt CY v PSW bit CY lt CY v HL bit CY lt CY v ES HL bit IN IN OO N N N IN IN N SN Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed Remarks 1 2 One instruction clock cycle is one cycle of the CPU clock selected by the system clock control register CKC This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximu
44. ABQ 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Select Register Bank Register Bank Selection SEL RBn Instruction format SEL RBn Operation 8850 8851 lt n n 0 to 3 Operand Mnemonic Operand RBn Description e The register bank specified by the operand RBn is made a register bank for use by the next and subsequent instructions e RBn ranges from RBO to RB3 Description example SEL RB2 Register bank 2 is selected as the register bank for use by the next and subsequent instructions ILS a s Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS No Operation NO P No Operation Instruction format NOP Operation no operation Operand None Description e Only the time is consumed without processing SUS Rer SS ES Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Enable Interrupt Interrupt Enabled Instruction format El Operation IE 1 Operand None Description e The maskable interrupt acknowledgeable status is set by setting the interrupt enable flag IE to 1 e No interrupts are acknowledged between this instruction and the next instruction e f this instruction is executed vectored interrupt acknowledgment from another source can be disabled For details refer to the description of interrupt functions in the user s manual for each p
45. AX 155EH and CY 1 1010 1010 1111 0101B 0 AX 20101 0101 0111 1010B 1 1time AX 20010 1010 1011 11018 CV 0 2times AX 20001 0101 0101 11108 1 3times R01US0029EJO600 Rev 6 00 129 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Shift Left Logical Shift to the Left Instruction format SHL dst cnt Operation CY lt dstz dstm lt dstm 1 dsto lt 0 x cnt Operand Mnemonic Operand dst cnt Description e The destination operand dst specified by the first operand is shifted to the left the number of times specified by cnt e 0 is entered to the LSB bit and the value shifted last from bit 7 is entered to CY e cnt can be specified as any value from 1 to 7 CY 7 0 a C Description example SHL A 3 When the A register s value is 5DH E8H and CY 0 CY 0 A 0101_1101B 0 1011 1010 1 time CY 1 0111 0100 2times 0 0110 10008 3times RO1US0029EJ0600 Rev 6 00 130 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Shift Left Word Logical Shift to the Left Instruction format SHLW dst cnt Operation CY lt dstis lt dstm 1 dsto lt 0 x cnt Operand Operand dst cnt Description e The destination operand dst specified by the first operand is shifted to the left the number of times specified by cnt e 0 is
46. ES lt byte ES saddr 3 1 ES lt saddr A ES 2 1 lt ES ESTA 2 1 ES A CS byte 3 1 CS lt byte A CS 2 1 A CS CS A 2 1 CS A A DE 1 1 4 A DE DE A 1 1 DE A DE byte byte 9 1 DE byte byte A DE byte 2 1 4 A lt DE byte DE byte A 2 1 DE byte A A HL 1 1 4 A lt HL HL A 1 1 HL A HL byte byte 3 1 HL byte byte Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 Exceptr A Remarks 1 One instruction clock cycle is one cycle of the CPU clock selected by the system clock control register CKC 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is acc
47. HL HL AX 1 1 HL lt lt AX AX HL byte 2 1 4 AX lt HL byte HL byte AX 2 1 HL byte lt AX AX word B 3 1 4 AX lt B word word B AX 3 1 lt word C 8 1 4 lt C word worq C AX 8 1 _ C word AX AX word BC 3 1 4 lt word word BC AX 3 1 BC word AX AX SP byte 2 1 AX lt SP byte SP byte AX 2 1 SP byte AX BC saddrp 2 1 BC lt saddrp BC laddr16 3 1 4 BC lt addr16 DE saddrp 2 1 DE lt saddrp DE addr16 3 1 4 DE lt addr16 HL saddrp 2 1 _ HL lt saddrp HL laddr16 3 1 4 HL lt addr16 AX ES laddr16 4 2 5 AX lt ES addr16 ES laddr16 AX 4 2 ES addr16 AX ES DE 2 2 lt ES DE ES DE AX 2 2 ES DE AX AX ES DE byte 3 2 5 AX lt ES DE byte ES DE byte AX 3 2 ES DE byte AX AX ES HL 2 2 5 AX lt ES HL ES HL AX 2 2 5 HL AX Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register 2 CKO This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of
48. INSTRUCTIONS Add Byte Data Addition Instruction format ADD dst src Operation dst lt dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A HL B saddr byte A HL C A r A ES addr16 nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte Note Exceptr A Description e The destination operand dst specified by the 1st operand is added to the source operand src specified by the 2nd operand and the result is stored in the CY flag and the destination operand dst e If the addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 f the addition generates a carry out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 e f the addition generates a carry for bit 4 out of bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example ADD CR10 56 56H is added to the CR10 register and the result is stored in the CR10 register R01US0029EJO600 Rev 6 00 106 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Add with Carry Addition of Byte Data with Carry Instruction format ADDC dst src Operation dst CY dst src CY Operand Mnemonic Operand dst src Mnemonic Operand dst src
49. Instructions J J u u u u u uu uu uu J 116 6 5 Multiply U U u uu u u u uu u 120 6 6 Increment Decrement Instructions J U U nennen nennen nn nnne nnn 122 _ 127 6 8 Rotate amp amp 134 6 9 Bit Manipulation Instructions l U u u u uu 140 6 10 Call Return Instructions nero oe n u u Du Y u 148 6 11 Stack Manipulation Instructions U U nnnm u u u u nennen nnn 155 6 12 Unconditional Branch Instruction U 161 6 13 Conditional Branch 5 2 444 4 4 4 163 6 14 Conditional Skip Instructions J u u u u u uu u u 173 6 15 CPU Control Instructions ssania anena IIIa 180 CHAPTER 7 PIPELINE iire _ 187 EMIT a T ua A 18
50. MEMORY SPACE Change of description in 2 5 Extended SFR Second SFR Area Addition of Caution to 3 1 3 Stack pointer SP CHAPTER 3 REGISTERS Addition of Remark in Table 5 1 Operand Identifiers and Description Methods CHAPTER 5 Addition of description to 5 4 PREFIX Instruction Change of Remarks 2 in Table 5 5 Operation List Change of Clocks of BT instruction in Table 5 5 Operation List 16 17 Change of Clocks of BF instruction in Table 5 5 Operation List 17 17 Change of Clocks of BTCLR instruction in Table 5 5 Operation List 17 17 INSTRUCTION SET Addition of Description to MOV1 instruction Addition of Description to SET1 instruction Addition of Description to CLR1 instruction Modification of Description example to MOVW SP src and MOVW AX SP instruction Addition of Description to BTCLR instruction Addition of Description to SKC instruction Addition of Description to SKNC instruction Addition of Description to SKZ instruction Addition of Description to SKNZ instruction Addition of Description to SKH instruction Addition of Description to SKNH instruction CHAPTER 6 EXPLANATION OF INSTRUCTIONS Addition of 7 2 3 Instruction fetch from RAM Change of 7 2 4 Instruction fetch from external memory CHAPTER 7 PIPELINE R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 197 78KOR Microcontrollers User s Manual Inst
51. None Description e When Z 0 the next instruction is skipped The subsequent instruction is a NOP and one clock of execution time is consumed However if the next instruction is a PREFIX instruction indicated by ES two clocks of execution time are consumed e When Z 1 the next instruction is executed e All interrupt requests are not acknowledged between this instruction and the next instruction Description example MOV A 55 SKNZ ADD A 55H The A register s value when Z 1 and 55H when Z 0 01050029 0600 Rev 6 00 177 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Skip if Higher than Skip with numeric value comparison Z v CY 0 Instruction format SKH Operation Next instruction skip if Z v CY 0 Operand None Description e When Z v CY 0 the next instruction is skipped The subsequent instruction is a NOP and one clock of execution time is consumed However if the next instruction is a PREFIX instruction indicated by ES two clocks of execution time are consumed e When Z v CY 1 the next instruction is executed e All interrupt requests are not acknowledged between this instruction and the next instruction Description example CMP A 80H SKH CALL TARGET When the A register contents are higher than 80H the CALL instruction is skipped and the next instruction is executed When the A register contents
52. OF INSTRUCTIONS 6 10 Call Return Instructions The following instructions are call return instructions CALL 149 CALLT 150 151 RET 152 RETI 153 RETB 154 R01US0029EJ0600 Rev 6 00 148 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Call Subroutine Call Instruction format CALL target Operation SP 2 lt PC n s SP 3 lt SP 4 lt PC n L SP lt SP 4 PC lt target Remark nis 4 when using addr20 when using addr16 or addr20 and 2 when using AX BC DE or HL Operand Mnemonic Operand target AX BC DE HL laddr20 laddri16 lladdr20 Flag Description e This is a subroutine call with a 20 16 bit absolute address or a register indirect address e The start address PC n of the next instruction is saved in the stack and is branched to the address specified by the target operand target Description example CALL 3E000H Subroutine call to 3E000H R01US0029EJ0600 Rev 6 00 149 Jan 31 2011 st eN6 s lt sAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Call Table Subroutine Call Refer to the Call Table Instruction format CALLT addr5 Operation SP 2 lt 2 5 SP 3 lt 2 SP 4 lt PC 2 L PCs lt 0000 PCH lt 0000 addr5 1 PCL lt 0000 addr5 SP lt SP 4 Operand Operand addr5
53. Word Data Increment Instruction format INCW dst Operation dst dst 1 Operand Mnemonic Operand dst rp saddrp laddr16 HL byte ES laddr16 ES HL byte Flag Description e The destination operand dst contents are incremented by only one e Because this instruction is frequently used for increment of a register pointer used for addressing the Z AC and CY flag contents are not changed Description example INCW HL The HL register is incremented R01US0029EJO600 Rev 6 00 125 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Decrement Word Word Data Decrement Instruction format DECW dst Operation dst dst 1 Operand Mnemonic Operand dst rp saddrp laddr16 HL byte ES laddr16 ES HL byte Flag Description e The destination operand dst contents are decremented by only one e Because this instruction is frequently used for decrement of a register pointer used for addressing the Z AC and CY flag contents are not changed Description example DECW DE The DE register is decremented R01US0029EJO600 Rev 6 00 126 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 7 Shift Instructions The following instructions are shift instructions SHR 128 SHRW 129 SHL 130 SHLW 131 SAR 132 SARW 13
54. a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device 6 INPUT OF SIGNAL DURING POWER OFF STATE not input signals or an I O pull up power supply while the device is not powered current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Target Readers Purpose Organization How to Read This Manual Conventions How to Use This Manual This manual is intended for users who wish to understand the functions of 78KOR microcontrollers and to design and develop its application systems and programs This manual is intended to give users an understanding of the various kinds of instruction functions of 78K0R microcontr
55. addresses only FFFOOH to FFFFFH saddr saddrp FFE20H to FFF1FH Immediate data or labels FFE20H to FF1FH Immediate data or labels even addresses only addr20 addr16 addr5 00000H to FFFFFH Immediate data or labels 0000H to FFFFH Immediate data or labels only even addresses for 16 bit data transfer instructions 0080H to 00BFH Immediate data or labels even addresses only Noe word byte bit 16 bit immediate data or label 8 bit immediate data or label 3 bit immediate data or label RBn RBO to RB3 Note Bit 0 when an odd address is specified Remark special function registers can be described to operand sfr as symbols The extended special function registers can be described to operand addr16 as symbols R01US0029EJ0600 Rev 6 00 35 Jan 31 2011 RENESAS 78K0R Microcontrollers CHAPTER 5 INSTRUCTION SET 5 2 Symbols in Operation Column The operation when the instruction is executed is shown in the Operation column using the following symbols Table 5 2 Symbols in Operation Column Symbol Function A A register 8 bit accumulator x X register B B register C C register D D register E E register H H register L L register ES ES register C5 CS register AX AX register pair 16 bit accumulator BC BC register pair DE DE register pair HL HL register pair
56. are 80H or lower the next CALL instruction is executed and execution is branched to the target address R01US0029EJ0600 Rev 6 00 178 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Skip if not Higher than Skip with numeric value comparison Z v CY 1 Instruction format SKNH Operation Next instruction skip if Z v CY 1 Operand None Description e When Z v CY 1 the next instruction is skipped The subsequent instruction is a NOP and one clock of execution time is consumed However if the next instruction is a PREFIX instruction indicated by ES two clocks of execution time are consumed e When Z v CY 0 the next instruction is executed e All interrupt requests are not acknowledged between this instruction and the next instruction Description example CMP A 80 SKNH CALL TARGET When the A register contents are 80H or lower the CALL instruction is skipped and the next instruction is executed When the A register contents are higher than 80H the next CALL instruction is executed and execution is branched to the target address 01050029 0600 Rev 6 00 179 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 15 CPU Control Instructions The following instructions are CPU control instructions SEL RBn 181 NOP 182 El 183 DI 184 HALT 185 STOP 186 RO1USO029EJO600 RevV6 00
57. are exchanged Description example XCHW AX BC The memory contents of the AX register are exchanged with those of the BC register r Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS One Word Word Data 0001 Set Instruction format ONEW dst Operation dst 0001H Operand ONEW AX Flag Description 0001H is transferred to the destination operand dst specified by the first operand Description example ONEW AX 0001H is transferred to the AX register R01US0029EJO600 Rev 6 00 103 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Clear Word Word Data Clear Instruction format CLRW dst Operation dst lt 0000H Operand CLRW AX Flag Description e 0000H is transferred to the destination operand dst specified by the first operand Description example CLRW AX OOOOH is transferred to the AX register R01US0029EJO600 Rev 6 00 104 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 3 8 bit Operation Instructions The following instructions are 8 bit operation instructions ADD 106 ADDC 107 SUB 108 SUBC 1090 AND 110 OR 111 XOR 112 CMP 113 114 CMPS 115 RO1USO029EJ0600 RevV6 00 L __ K 105 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF
58. area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register CKC 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data RO1US0029EJ0600 Rev 6 00 52 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 16 17 Instruction Mnemonic Operands Clocks Operation Group Note 1 Note 2 Stack SP 1 PSW SP 2 00H manipulate SP lt SP 2 SP 1 lt SP 2 lt SP SP 2 PSW lt SP 1 SP lt SP 2 rp lt lt SP 1 SP SP 2 N
59. assembler s program the address must be changed whenever RAM contents within the stack pointer are manipulated The stack size should be increased slightly to accommodate the depth of multiple CALLs or multiple interrupts The CALLT table s address range has been changed from 0040H to 007FH to 0080H to OOBFH Consequently the CALLT table s address should be changed Among the programs used for the 78KO microcontroller s bank switching the assembler program must be rewritten Address changes are made when using the expansion RAM Be sure to change these addresses If instructions are executed from expansion RAM since memory space addresses have been changed change BR addr16 to BR addr20 and CALL addr16 to CALL addr20 There are no IMS or IXS registers registers used to set memory space The programs that use these registers should be deleted if external memory is not being used If external memory is being used the specifications for the MM MEM register external memory setting register have been changed so check the user s manual for each product and change the settings accordingly R01US0029EJ0600 Rev 6 00 N Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 1 OUTLINE 9 The following instructions are deleted and the alternative code is output resulting in code size increases Even when these instructions are used they are automatically replaced during assembly Instruction Operand Remarks The al
60. be executed Caution Be sure to use the RETI instruction for restoring from the non maskable interrupt R01US0029EJ0600 Rev 6 00 153 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Return from Break Return from Software Vectored Interrupt Instruction format RETB Operation lt SP PCH lt 1 PCs lt SP 2 PSW lt SP 3 lt SP 4 Operand None Description e This is a return instruction from the software interrupt generated with the BRK instruction e The data saved in the stack returns to the PC and the PSW and the program returns from the interrupt servicing routine e None of interrupts are acknowledged between this instruction and the next instruction to be executed SUS REPE Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 11 Stack Manipulation Instructions The following instructions are stack manipulation instructions PUSH 156 POP 157 MOVW SP src 158 MOVW AX SP 158 ADDW SP byte 159 SUBW SP byte 160 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 155 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Instruction format PUSH src Operation When src rp When src PSW SP 1 lt SP 1 lt PSW SP 2 lt rp SP 2 lt 00H SP lt SP 2 SP lt SP 2 Operand Mnemonic Operand src PUSH Flag
61. bit CY A bit CY PSW bit CY HL bit CY ES HL bit Flag Description Logical product of bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand is obtained and the result is stored in the destination operand dst e The operation result is stored in the CY flag because of the destination operand dst Description example AND1 CY FFE7FH 3 Logical product of FFE7FH bit 3 and the CY flag is obtained and the result is stored in the CY flag R01US0029EJO600 Rev 6 00 142 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Or Single Bit 1 Bit Data Logical Sum Instruction format OR1 dst src Operation dst dst v src Operand Mnemonic Operand dst src CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY ES HL bit Flag Description e The logical sum of bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand is obtained and the result is stored in the destination operand dst e The operation result is stored in the CY flag because of the destination operand dst Description example OR1 CY P2 5 The logical sum of port 2 bit 5 and the CY flag is obtained and the result is stored in the CY flag R01US0029EJO600 Rev 6 00 143 Jan 31
62. clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 42 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Instruction Group 16 bit data transfer Mnemonic Operands Clocks Operation Table 5 5 Operation List 6 17 Note 1 Note 2 AX ES HL byte ES HL byte AX AX ES word B ES word B AX AX ES word C ES word C AX AX ES word BC ES word BC AX BC ES addr16 N AX lt ES HL byte ES HL byte AX AX lt ES B word ES B word AX AX lt ES C word ES word lt lt ES BC word ES BC word AX BC lt ES addr16 DE ES laddr16 DE lt ES addr16 HL ES addr16 HL lt ES addr16 T 2T gt gt I IL Jojo N IN N IN
63. entered to the LSB bit and the value shifted last from bit 15 is entered to CY e cnt can be specified as any value from 1 to 15 15 0 I Description example SHLW 3 When the BC register s value is C35DH BC 1AE8H and CY 0 CY 0 1100_0011_0101_1101 CY 1 1000 0110 1011 10108 1 time CY 1 0000 1101 0111 01008 2times CY 0 0001 1010 1110 10008 3times R01US0029EJ0600 Rev 6 00 131 Jan 31 2011 st eN6 s lt sAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Shift Arithmetic Right Arithmetic Shift to the Right Instruction format SAR dst cnt Operation lt dsto dstm 1 dstm dst7 dstz x cnt Operand Operand dst cnt Description e The destination operand dst specified by the first operand is shifted to the right the number of times specified by cnt e The same value is retained in the MSB bit 7 and the value shifted last from bit 0 is entered to CY e cnt can be specified as any value from 1 to 7 7 0 CY Description example SAR A 4 When the A register s value is 8CH A F8H and CY 1 A 1000_1100B CY 0 A 1100_0110B CY 0 1 time A 1110_0011B CY 0 2times 1111 0001 CY 1 3times A 1111_1000B CY 1 4times RO1US0029EJ0600 Rev 6 00 132 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Shift Arithmetic Right Word Arithmetic Shift to the Right Instruction for
64. granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
65. saddr 3 CY SET1 saddr 3 CLR1 saddr 3 MOV1 CY saddr 3 AND1 CY saddr 3 OR1 CY saddr 3 XOR1 CY saddr 3 CLR1 16 3 M0V1 sfr 3 CY MOV1 CY sfr 3 AND1 CY sfr 3 OR1 CY sfr 3 XOR1 CY sfr 3 SET1 laddr16 4 MOV1 saddr 4 CY SET1 saddr 4 CLR1 saddr 4 MOV1 CY saddr 4 AND1 CY saddr 4 OR1 CY saddr 4 XOR1 CY saddr 4 CLR1 laddr16 4 MOV1 sfr 4 CY MOV1 CY sfr 4 AND1 CY sfr 4 OR1 CY sfr 4 XOR1 CY sfr 4 SET1 addr16 5 MOV1 saddr 5 CY SET1 saddr 5 CLR1 saddr 5 MOV1 CY saddr 5 AND1 CY saddr 5 OR1 CY saddr 5 XOR1 CY saddr 5 CLR1 16 5 M0V1 sfr 5 CY MOV1 CY sfr 5 AND1 CY sfr 5 OR1 CY sfr 5 XOR1 CY sfr 5 SET1 addr16 6 MOV1 saddr 6 CY SET1 saddr 6 CLR1 saddr 6 MOV1 CY saddr 6 AND1 CY saddr 6 OR1 CY saddr 6 XOR1 CY saddr 6 CLR1 16 6 M0V1 sfr 6 CY MOV1 CY sfr 6 AND1 CY sfr 6 OR1 CY sfr 6 XOR1 CY sfr 6 SET1 laddr16 7 MOV1 saddr 7 CY SET1 saddr 7 CLR1 saddr 7 MOV1 CY saddr 7 AND1 CY saddr 7 OR1 CY saddr 7 XOR1 CY saddr 7 CLR1 laddr16 7 MOV1 sfr 7 CY MOV1 CY sfr 7 AND1 7 OR1 CY sfr 7 XOR1 CY sfr 7 SET1 M0CV1 HL 0 CY SET1 HL O CLR1 HL O MOV1 CY HL O AND1 CY HL 0 OR1 CY HL 0 XOR1 CY HL 0 CLR1 CV M0V1 0 MOV1 CY A 0
66. saddr 4 CY saddr 5 CY saddr 6 R01US0029EJ0600 Rev 6 00 69 Jan 31 2011 steNnesAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 16 30 Mnemonic Operands CY saddr 7 CY sfr 0 CY sfr 1 CY sfr 2 CY sfr 3 CY sfr 4 CY sfr 5 CY sfr 6 CY sfr 7 CY A 0 CY A 1 CY A 2 CY CY 4 CY A 5 CY PSW 0 CY PSW 1 CY PSW 2 CY PSW 3 CY PSW 4 CY PSW 5 CY PSW 6 CY PSW 7 CY HL O CY HL 1 CY HL 2 CY HL 3 CY HL 4 CY HL 5 CY HL 6 CY HL 7 saddr 0 CY saddr 1 CY saddr 2 CY saddr 3 CY saddr 4 CY saddr 5 CY saddr 6 CY saddr 7 CY RO1US0029EJ0600 Rev 6 00 70 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 17 30 Mnemonic Operands 7 CY PSW 0 CY PSW 1 CY PSW 2 CY PSW 3 CY PSW 4 CY PSW 5 CY PSW 6 CY PSW 7 CY HL 0 CY HL 1 CY HL 2 CY HL 8 CY HL 4 CY HL 5 CY HL 6 CY HL 7 CY CY ES HL 0 CY ES HL 1 CY ES HL 2 CY ES HL 3 CY ES HL 4 ES HL 5 CY ES HL 6 CY ES HL 7
67. the AX register contents and the result is stored in the AX register RO1US0029EJ0600 Rev 6 00 118 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Compare Word Word Data Comparison Instruction format CMPW dst src Operation dst src Operand Mnemonic Operand dst src AX word AX BC AX DE AX HL AX saddrp AX laddr16 AX HL byte AX ES laddr16 AX ES HL byte Description e The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand The subtraction result is not stored anywhere and only the Z AC and CY flags are changed e If the subtraction result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e f the subtraction generates a borrow out of bit 15 the CY flag is set 1 In all other cases the CY flag is cleared 0 e As a result of subtraction the AC flag becomes undefined Description example CMPW AX ABCDH ABCDH is subtracted from the AX register and only the flags are changed comparison of the AX register and the immediate data RO1US0029EJ0600 Rev 6 00 119 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 5 Multiply Instruction The following instruction is multiply instruction MULU 121 SIL erg s n Jan 31 2011 RENESAS
68. to external memory contents as data R01US0029EJ0600 Rev 6 00 46 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 10 17 Clocks Note 1 Note 2 Instruction Mnemonic Group Operands Operation 8 bit operation A byte A byte saddr byte saddr byte A r saddr laddr16 HL HL byte A HL B A HL C laddr16 byte A ES addr16 A ES HL A HL C addr16 byte A ES addr16 A ES HL A ES HL byte A ES HL byte A ES HL B A ES HL B A ES HL A ES HL alt al asyaqay ys HR alo C2 IO I ES laddr16 byte A ES addr16 byte A 00H X 00H B B 00H C 00H saddr saddr 00H laddr16 addr16 00H ES laddr16 ES addr16 00H X HL byte X HL byte X ES HL byte X ES HL byte When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed 3 Exceptr A X Notes 1 Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register CKO 2 This number of clocks i
69. word AX CY AX word AX BC AX CY AX BC AX DE AX CY AX DE AX HL AX CY AX HL AX saddrp AX CY lt AX saddrp AX laddr16 AX CY AX addr16 AX HL byte AX CY AX HL byte AX ES laddr16 AX CY AX ES addr16 AX ES HL byte AX lt AX ES HL byte AX word AX word AX BC AX BC AX DE AX DE AX HL AX HL AX saddrp AX saddrp AX laddr16 AX addr16 AX HL byte AX ES laddr16 ES addr16 AX ES HL byte zi AX HL byte ES HL byte Multiply x AX Ax X Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed INSTRUCTION SET Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register CKC 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the
70. 00 172 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 14 Conditional Skip Instructions The following instructions are conditional skip instructions SKC 174 SKNC 1752 SKZ 176 SKNZ 177 SKH 178 SKNH 179 SU erg a gt 35 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Skip if CY Skip with Carry Flag CY 1 Instruction format SKC Operation Next instruction skip if CY 1 Operand None Description e When CY 1 the next instruction is skipped The subsequent instruction is a NOP and one clock of execution time is consumed However if the next instruction is a PREFIX instruction indicated by ES two clocks of execution time are consumed e When CY 0 the next instruction is executed All interrupt requests are not acknowledged between this instruction and the next instruction Description example MOV A 55 SKC ADD A 55 The A register s value when CY and 55H when CY 1 01050029 0600 Rev 6 00 174 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Skip if not CY Skip with Carry Flag CY 0 Instruction format SKNC Operation Next instruction skip if CY 0 Operand None Description e When CY the next instruction is skipped The subsequent instruction is a NOP and one clock o
71. 0029EJ0600 Rev 6 00 51 Jan 31 2011 2 gt 1 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 15 17 Instruction Mnemonic Operands Clocks Operation Group Note 1 Note 2 Call SP 2 lt PC 2 s SP 3 lt PC 2 return SP 4 lt PC 2 L PC lt CS rp SP SP 4 addr20 SP 2 lt PC 3 s SP 3 lt PC SP 4 PC 3 PC PC 3 jdisp16 SP lt SP 4 laddr16 SP 2 lt PC 3 s SP 3 lt PC SP 4 lt PC 3 L PC lt 0000 addr16 SP lt SP 4 mm SP 2 lt PC 4 s SP 3 lt 4 SP 4 lt PC 4 addr20 SP lt SP 4 addr5 SP 2 lt PC 2 s SP 3 lt PC 2 SP 4 lt PC 2 PCs 0000 PCH 0000 addr5 1 PC lt 0000 addr5 SP SP 4 SP 1 PSW SP 2 lt PC 2 SP 3 lt PC 2 SP 4 lt PC 2 PCs lt 0000 lt 0007FH PC lt 0007EH SP SP 4 IE 0 PC lt SP lt SP 1 PCs lt SP 2 SP lt SP 4 PC lt SP PCH lt SP 1 PCs lt SP 2 PSW lt SP 3 lt 5 4 PC lt SP lt SP 1 PCs SP 2 PSW lt SP 3 lt SP 4 Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory
72. 011 2 gt 1 78 Microcontrollers CHAPTER 7 PIPELINE 7 24 Instruction fetch from external memory When data is fetched from the external memory the instruction queue becomes empty because reading from the external memory is late So the CPU waits until the data is set to the instruction queue During fetch from the external memory the CPU also waits if there is external memory access The minimum and maximum numbers of execution clocks of each instruction when fetching instructions from the external memory are as follows for the number of clocks when instructions are fetched from the flash memory area No of Instruction Execution Clocks When Fetching Instructions from External Memory When Fetching Instructions from flash memory Area Minimum No of Execution Clocks 2 2 x Wait Maximum No of Execution Clocks 5 3 x Wait 6 2 x Wait 7 6 x Wait 4 2 x Wait 8 8 x Wait 8 2 x Wait 10 10 x Wait 6 2 x Wait 12 9 x Wait 10 5 x Wait 14 11 x Wait Note Number of clocks when the internal RAM area SFR area or expanded SFR area has been accessed or when an instruction that does not access data is executed Furthermore the number of waits is as follows depending on the clock selected for the CLKOUT pin Table 7 2 CPU Wait When Fetching Data from External Memory Clock for Selecting External Extension Clock Output
73. 1st operand Description example MOVW SP FE20H FE20H is stored in the stack pointer R01US0029EJO600 Rev 6 00 158 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Add stack pointer ADDW SP byte Addition of Stack Pointer Instruction format ADDW SP src Operation SP lt SP src Operand Mnemonic Operand src SP byte Description e The stack pointer specified by the first operand and the source operand src specified by the second operand are added and the result is stored in the stack pointer Description example ADDW SP 12H Stack pointer and 12H are added and the result is stored in the stack pointer R01US0029EJO600 Rev 6 00 159 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Sub stack pointer Subtraction of Stack Pointer SUBW SP byte Instruction format SUBW SP src Operation SP lt SP src Operand SUBW SP byte Flag Description e Source operand src specified by the second operand is subtracted from the stack pointer specified by the first operand and the result is stored in the stack pointer Description example SUBW SP 12H 12H is subtracted from the stack pointer and the result is stored in the stack pointer R01US0029EJO600 Rev 6 00 160 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 12 Unconditional Branch Instructio
74. 24 NE SAS C 7 D ens lt 0 o 78KOR Microcontrollers User s Manual Instructions 16 Bit Single Chip Microcontrollers All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com Renesas Electronics www renesas com Rev 6 00 Jan 2011 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is
75. 3 SU er n T Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Shift Right Logical Shift to the Right Instruction format SHR dst cnt Operation CY lt dsto dstm 1 lt dstm dst7 lt 0 x cnt Operand Operand dst cnt Flag Description e The destination operand dst specified by the first operand is shifted to the right the number of times specified by cnt e 0 is entered to the MSB bit 7 and the value shifted last from bit 0 is entered to CY e cnt can be specified as any value from 1 to 7 Description example SHR A 3 When the A register s value is F5H and CY 1 A 1111_0101B CY 0 A 0111_1010B CY 1 1 time A 0011_1101B CY 0 2times A 0001_1110B CY 1 3times R01US0029EJO600 Rev 6 00 128 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Shift Right Word Logical Shift to the Right Instruction format SHRW dst cnt Operation CY lt dsto dstm 1 lt dstm dstis lt 0 x cnt Operand Operand dst cnt Description e The destination operand dst specified by the first operand is shifted to the right the number of times specified by cnt e 0 is entered to the MSB bit 15 and the value shifted last from bit 0 is entered to CY e cnt can be specified as any value from 1 to 15 15 0 CV JE Description example SHRW 3 When the AX register s value is AAF5H
76. 4 1 2 Immediate addressing Function Immediate addressing stores immediate data of the instruction word in the program counter and specifies the program address to be used as the branch destination For immediate addressing CALL addr20 or BR addr20 is used to specify 20 bit addresses and CALL addr16 or BR addr16 is used to specify 16 bit addresses 0000 is set to the higher 4 bits when specifying 16 bit addresses Figure 4 2 Example of CALL addr20 BR addr20 Low Addr High Addr Seg Addr Figure 4 3 Example of CALL addr16 BR addr16 PC Low Addr High Adar 0000 4 1 3 Table indirect addressing Function Table indirect addressing specifies a table address in the CALLT table area 0080H to OOBFH with the 5 bit immediate data in the instruction word stores the contents at that table address and the next address in the program counter PC as 16 bit data and specifies the program address Table indirect addressing is applied only for CALLT instructions In the 78KOR microcontrollers branching is enabled only to the 64 KB space from 00000H to OFFFFH Figure 4 4 Outline of Table Indirect Addressing OP code Low Addr 00000000 10 High Addr Table address PC R01US0029EJO600 Rev 6 00 22 Jan 31 2011 ztENESAS 78K0R Microcontrollers CHAPTER 4 ADDRESSING 4 1 4 Register direct addressing Function Register direct addressing stores in the program cou
77. 6 List of Instruction Formats 5 30 Operands word B AX INSTRUCTION SET AX word C word C AX AX word BC word BC AX AX SP byte SP byte AX BC saddrp BC addr16 DE saddrp DE addr16 HL saddrp HL addr16 AX ES laddr16 ES laddr16 AX AX ES DE ES DE AX ES DE byte ES DE byte AX AX ES HL ES HL AX AX ES HL byte ES HL byte AX AX ES word B ES word B AX AX ES word C ES word C AX AX ES word BC ES word BC AX BC ES laddr16 DE ES laddri 6 HL ES laddri 6 AX BC AX DE AX HL AX BC AX BC R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 59 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 6 30 Mnemonic Operands A byte saddr byte A X A A B A E A D A L A H X A A A C A B A E A D A A saddr A laddr16 A HL A HL byte A HL B A HL C A ES addr16 A ES HL A ES HL byte A ES HL B A byte saddr byte A X A C A B A E A D A L H X A A A C A B A E A D A
78. 6 8 2 _ addr16 lt addr16 1 HL byte 8 2 _ HL byte HL byte 1 ES laddr16 4 3 _ ES addr16 ES addr16 1 ES HL byte 4 3 _ ES HL byte ES HL byte 1 DECW rp 1 1 _ rp lt rp 1 saddrp 2 2 _ saddrp lt saddrp 1 laddr16 3 2 _ addr16 addr16 1 HL byte 3 2 _ HL byte HL byte 1 ES laddr16 4 3 _ ES addr16 ES addr16 1 ES HL byte 4 3 _ ES HL byte ES HL byte 1 Shift SHR A cnt 2 1 _ lt Ao Am 1 lt Am A lt 0 x cnt x SHRW AX cnt 2 1 _ CY lt AXo AXm 1 5 lt 0 x cnt x SHL A cnt 2 1 CY lt Az Am Am 1 Ao lt 0 x cnt x B cnt 2 1 CY lt Br Bm Bm 1 Bo lt 0 x cnt x C cnt 2 1 CY lt C7 lt Cm Co lt 0 x cnt x SHLW AX cnt 2 1 CY lt AXi5 AXm 1 AXo lt 0 x cnt x BC cnt 2 1 _ lt 8C15 BCm lt 8C I BCo lt 0 x cnt x SAR A cnt 2 1 _ CY lt Ao Am 1 lt Am A7 lt A7 cnt x SARW AX cnt 2 1 CY lt AXm 1 lt AX 5 lt x cnt x Notes 1 When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access 2 When the program memory area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock selected by the system clock control register 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetch
79. 7 7 2 Number of Operation Clocks J u u uuu u u T 188 7 2 1 Access to flash memory contents as data eee cess ener 188 7 2 2 Access to external memory contents as data 188 7 2 3 Instruction fetch from RAM u u u u u uuu eaea ea 188 7 2 4 Instruction fetch from external 189 7 2 5 Hazards related to combined instructions 190 APPENDIX A INSTRUCTION INDEX MNEMONIC BY FUNCTION 191 APPENDIX B INSTRUCTION INDEX MNEMONIC IN ALPHABETICAL ORDER 193 R01US0029EJ0600 Rev 6 00 Jan 31 2011 st eN6 s lt sAS 44 NESAS 78KOR Microcontrollers RO1US0029EJ0600 RENESAS MCU Rev 6 00 Jan 31 2011 CHAPTER 1 OVERVIEW 1 1 Differences from 78 0 Microcontrollers for Assembler Users 1 Use of pipeline processing reduces the number of processing clock cycles for all instructions Existing programs must be re evaluated All instruction code maps have been modified Reassemble them using the assembler When reassembling the code size is likely to increase as new instructions are added but in some cases the overall code size may shrink if old instructions are replaced with new ones The memory space was changed from 64 KB to 1 MB and the total stack area was also increased Within the
80. 75 SKNH 179 SKNZ 177 SKZ 176 STOP 186 SUB 108 SUBC 109 SUBW 118 SUBW SP byte 160 IX XCH 95 XCHW 102 XOR 112 XOR1 144 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 194 78KOR Microcontrollers APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY C 1 Major Revisions in This Edition Description Classification CHAPTER 1 OVERVIEW p 8 Addition of explanation to 1 1 Differences from 78KO Microcontrollers c CHAPTER 2 MEMORY SPACE p 10 Addition of Caution to 2 2 Internal Program Memory Space c p 11 Addition of Caution to 2 3 Internal Data Memory Internal RAM Space c p 13 Addition of Caution to 2 6 External Memory Space c CHAPTER 4 ADDRESSING p 21 Addition of Caution to 4 1 1 Relative addressing c p 29 Addition of Caution to 4 2 7 Based addressing c p 32 Addition of Caution to 4 2 8 Based indexed addressing c CHAPTER 7 PIPELINE p 189 Change of Caution in 7 2 4 Instruction fetch from external memory c Remark Classification in the above table classifies revisions as follows a Error correction b Addition change of specifications c Addition change of description or note d Addition change of package part number or management division e Addition change of related documents R01US0029EJ0600 Rev 6 00 Jan 31 2011 ztENESAS 195 78KOR Microcontrollers APPENDIX C REVISION HISTO
81. A D A L A H X A C A A D A L A H A A saddr saddr A A sfr sfr A A addri6 laddr16 A PSW byte A PSW PSW A ES byte ES saddr A ES ES A CS byte R01US0029EJ0600 Rev 6 00 55 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 2 30 Mnemonic Operands A CS CS A A DE DE byte byte A DE byte DE byte A HL HL A HL byte byte A HL byte HL byte A A HL B HL B A A HL C HL C A word B byte A word B word B word C byte A word C word C word BC byte A word BC word BC A SP byte byte A SP byte SP byte A B saddr B addr16 C saddr C laddr16 X saddr X addr16 ES laddr16 byte A ES laddr16 ES addr16 A ES DE ES DE A ES DE byte byte A ES DE byte ES DE byte A A ES HL R01US0029EJ0600 Rev 6 00 56 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 3 30 Mnemonic Operands ES HL A ES HL byte byte A ES HL byte ES HL byt
82. AND1 CY A 0 OR1 CY A 0 XOR1 CY A 0 MOV1 HL 1 CY SET1 HL 1 CLR1 HL 1 MOV1 CY HL 1 AND1 CY HL 1 OR1 CY HL 1 XOR1 CY HL 1 MOV1 MOV1 1 AND1 1 0 1 1 X0 1 1 M0CV1 HL 2 CY SET1 HL 2 CLR1 HL 2 MOV1 CY HL 2 AND1 CY HL 2 OR1 CY HL 2 XOR1 CY HL 2 MOV1 A 2 CY MOV1 2 AND1 CY A 2 OR1 CY A 2 XOR1 CY A 2 MOV1 HL 3 CY SET1 HL 3 CLR1 HL 3 MOV1 CY HL 3 AND1 CY HL 3 OR1 CY HL 3 XOR1 CY HL 3 MOV1 A 3 CY MOV1 CY A 3 AND1 CY A 3 OR1 CY A 3 XOR1 CY A 3 MOV1 HL 4 CY SETI HL 4 CLR1 HL 4 M0V1 CY HL 4 AND1 CY HL 4 OR1 CY HL 4 XOR1 CY HL 4 MOV1 A 4 CY MOV1 4 AND1 4 0 1 4 X0 1 4 MOV1 HL 5 CY SET1 HL 5 CLR1 HL 5 MOV1 CY HL 5 AND1 CY HL 5 OR1 CY HL 5 XOR1 CY HL 5 MOV1 A 5 CY MOV1 5 AND1 5 OR1 5 X081 CV 5 M0V1 HL 6 CY SET1 HL 6 CLR1 HL 6 MOV1 CY HL 6 AND1 CY HL 6 OR1 CY HL 6 XOR1 CY HL 6 MOV1 A 6 CY MOV1 CY A 6 AND1 CY A 6 OR1 6 1 6 M0CV1 HL 7 CY SET1 HL 7 CLR1 HL MOV1 CY HL 7 AND1 CY HL 7 OR1 CY HL 7 XOR1 CY HL 7
83. APTER 6 EXPLANATION OF INSTRUCTIONS Compare 00H Byte Data Zero Comparison Instruction format dst Operation dst 00H Operand Mnemonic Operand dst laddr16 ES laddr16 Description e 00H is subtracted from the destination operand dst specified by the first operand e The subtraction result is not stored anywhere and only the Z AC and CY flags are changed f the dst value is already OOH the Z flag is set 1 In all other cases the Z flag is cleared 0 e The AC and CY flags are always cleared 0 Description example CMPO A The Z flag is set if the A register value is 0 R01US0029EJO600 Rev 6 00 114 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Compare Byte Data Comparison Instruction format CMPS dst src Operation dst src Operand Operand dst src X HL byte X ES HL byte Description e The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand The subtraction result is not stored anywhere and only the Z AC and CY flags are changed e f the subtraction result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e When the calculation result is not 0 or when the value of either register A or dst is 0 then the CY flag is set 1 In all other cases the CY flag is cleared 0 e If t
84. CY A 1 CY A 2 CY A 3 CY A 4 CY A 5 CY A 6 CY A 7 CY PSW 0 CY PSW 1 CY PSW 2 CY PSW 3 CY PSW 4 CY PSW 5 CY PSW 6 CY PSW 7 CY HL O CY HL 1 CY HL 2 CY HL 3 CY HL 4 CY HL 5 CY HL 6 CY HL 7 CY ES HL O CY ES HL 1 CY ES HL 2 CY ES HL 3 CY ES HL 4 CY ES HL 5 CY ES HL 6 CY ES HL 7 saddr 0 saddr 1 saddr 2 saddr 3 saddr 4 saddr 5 saddr 6 saddr 7 RO1US0029EJ0600 Rev 6 00 75 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 22 30 Operands A 7 laddr16 0 laddr16 1 laddr16 2 laddr16 3 laddr16 4 laddr16 5 laddr16 6 laddr16 7 PSW 0 PSW 1 PSW 2 PSW 3 PSW 4 PSW 5 PSW 6 PSW 7 HL O HL 1 HL 2 HL 3 HL 4 HL 5 HL 6 HL 7 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 76 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 23 30 Operands ES laddr16 0 ES laddr16 1 ES laddr16 2 ES laddr16 3 ES laddr16 4 ES laddr16 5 ES laddr16 6
85. DRP are used to describe the values of addresses FE20H to FF1FH with 16 bit immediate data higher 4 bits of actual address are omitted and the values of addresses FFE20H to FFF1FH with 20 bit immediate data Regardless of whether SADDR or SADDRP is used addresses within the space from FFE20H to FFF1FH are specified for the memory R01US0029EJ0600 Rev 6 00 26 Jan 31 2011 2 gt 1 78 Microcontrollers CHAPTER 4 ADDRESSING 4 2 5 SFR addressing Function SFR addressing directly specifies the target SFR addresses using 8 bit data in the instruction word This type of addressing is applied only to the space from FFF00H to FFFFFH Operand format SFR SFR name SFRP 16 bit manipulatable SFR name even address only Figure 4 11 Outline of SFR Addressing FFFFFH SFR FFFOOH Memory R01US0029EJ0600 Rev 6 00 27 Jan 31 2011 RENESAS 78K0R Microcontrollers CHAPTER 4 ADDRESSING 4 2 6 Register indirect addressing Function Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address Operand format DE HL only the space from F0000H to FFFFFH is specifiable ES DE ES HL higher 4 bit addresses are specified by the ES register Figure 4 12 Example of DE HL FFFFFH F0000H Memory Figure 4 13 Example of ES DE ES HL FFFFFH 4 7
86. ES DE ES DE A 2 2 ES DE lt A ES DE byte byte 4 2 _ ES DE byte byte A ES DE byte 3 2 5 lt DE byte ES DE byte 3 2 5 DE byte lt A Notes 1 access 2 When the program memory area is accessed When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register CKC 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 39 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5
87. ES HL B ES HL C FFFFFH ES rp HL C Y 00000H r B C Memory lt R gt Caution In HL B and HL C an added value must not exceed FFFFH In ES HL B and ES HL C an added value must not exceed FFFFFH R01US0029EJO600 Rev 6 00 32 Jan 31 2011 ztENESAS 78K0R Microcontrollers CHAPTER 4 ADDRESSING 4 2 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved restored upon generation of an interrupt request Stack addressing is applied only to the internal RAM area Operand format Identifier Description PUSH AX BC DE HL POP AX BC DE HL CALL CALLT RET BRK RETB Interrupt request generated RETI R01US0029EJ0600 Rev 6 00 33 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET CHAPTER 5 INSTRUCTION SET This chapter lists the instructions in the 78KOR microcontroller instruction set The instructions are common to all 78KOR microcontrollers Remark shaded parts of the tables in 5 5 List of Operations and 5 6 List of Instruction Formats indicate the operation or instruction format that is newly added for the 78KOR microcontrollers 5 1 Operand Identifiers and Description Methods Operands are described in the Operand column of each instruct
88. ES laddr16 7 ES HL 0 ES HL 1 ES HL 2 ES HL 3 ES HL 4 ES HL 5 ES HL 6 ES HL 7 saddr 0 saddr 1 saddr 2 saddr 3 saddr 4 saddr 5 saddr 6 saddr 7 sfr 0 sfr 1 sfr 2 sfr 3 sfr 4 sfr 5 sfr 6 sfr 7 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 77 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 24 30 Mnemonic Operands laddr16 0 laddr16 1 laddr16 2 laddr16 3 laddr16 4 laddr16 5 laddr16 6 laddr16 7 PSW 0 PSW 1 PSW 2 PSW 3 PSW 4 PSW 5 PSW 6 HL 1 HL 2 HL 3 HL 4 HL 5 HL 6 HL 7 ES addr16 0 ES addr16 1 ES laddr16 2 ES addr16 3 ES addr16 4 ES addr16 5 ES addr16 6 ES laddr16 7 ES HL O ES HL 1 RO1US0029EJ0600 Rev 6 00 78 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 25 30 Mnemonic Operands AX BC DE HL addr20 laddr16 lladdr20 0080h 0082h 0084h 0086h 0088h 008Ah 008Ch 008Eh 0090h 0092h 0094h 0096h 0098h 009Ah 009Ch 009Eh 00A0
89. L 1 addr20 ES HL 2 addr20 ES HL 3 addr20 ES HL 4 addr20 ES HL 5 addr20 ES HL 6 addr20 ES HL 7 addr20 El DI HALT STOP PREFIX RO1US0029EJ0600 Rev 6 00 84 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET 5 7 Instruction Maps Tables 5 7 to 5 10 show instruction maps R01US0029EJ0600 Rev6 00 BG Jan 31 2011 RENESAS LLOZ Le 00 9 eH 0090f36200SflL0H SVS3N32 98 NOP ADDW AX AX ADDW AX addr16 ADDW AX BC ADDW AX word ADDW AX DE Table 5 7 Instruction Map 1st MAP ADDW AX saddrp XCH A X MOV A word B ADD saddr byte ADD A saddr ADD A byte ADD A HL ADD A HL byte A addr16 ADDW SP byte PREFIX MOVW BC AX MOVW AX BC MOVW DE AX MOVW AX DE MOVW HL AX MOV word B A MOV word B byte ADDC saddr byte ADDC A saddr ADDC A byte ADDC ADDC A HL byte ADDC A addr16 SUBW SP byte SUBW AX addr16 SUBW AX BC SUBW AX word SUBW AX DE SUBW AX saddrp MOV word C A MOV A word C SUB saddr byte SUB A saddr SUB A byte SUB SUB A HL byte SUB A addr16 MOVW AX word 4th MAP MOVW BC word XCHW AX BC MOVW DE word XCHW AX DE MOVW HL word MOV word C byte MOV word BC byte
90. MORY SPACE CHAPTER 2 MEMORY SPACE 21 Memory Space While the 78K0 microcontroller s memory space is only 64 KB this has been expanded to 1 MB in the 78K0R microcontroller Figure 2 1 Memory Maps of 78K0 Microcontrollers and 78K0R Microcontrollers Z8K0 microcontrollers 78 microcontrollers ne FFFFFH I 7 addressing SFR addressing FF20H __ Special function r egister SFR FFF20H Special functionregister SFR s FF1FH 256 x 8 bits FFF1FH 256 x 8 bits FFOOH FFFOOH General purpose register General purpose register 32 x 8 bits Short direct addressing FEEEOH 32 x 8 bits direct addressing FEDFH FFEDFH _ nemalhghrspeed RAM _ FFE20H FE1FH 1024 x 8 bits FFE1FH 61 75 K x 8 bits max FBOOH FAFFH Area 1 FAOOH F9FFH Area 2 F0800H F900H FO7FFH F8FFH Area3 Special function register 2nd SFR 2 Kx8bits F0000H Internal expansion RAM EFFFFH 14 K x 8 bits max EE000H EDFFFH Supporting external expansion memory Supporting external expansion memory Flash memory 60 K x 8 bits max Flash memory 960 K x 8 bits max 0000H 00000H Program memory space is 60 KB max Program memory space is 960 KB max Internal high speed RAM area is 1 max stack RAM space is 61 75 KB max stack enabled fetch enabled enabled
91. PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used ILI5 recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions 5 POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as
92. R sfr 1 addr20 BTCLR HL 1 addr20 BT sfr 1 addr20 BT HL 1 addr20 BF sfr 1 addr20 BF HL 1 addr20 BTCLR sfr 2 addr20 BTCLR HL 2 Saddr20 BT sfr 2 addr20 BT HL 2 addr20 BF sfr 2 addr20 BF HL 2 addr20 BTCLR sfr 3 addr20 BTCLR HL 3 addr20 BT sfr 3 addr20 BT HL 3 addr20 BF sfr 3 addr20 BF HL 3 Saddr20 BTCLR sfr 4 addr20 BTCLR HL 4 addr20 BT sfr 4 addr20 BT HL 4 addr20 BF sfr 4 addr20 BF HL 4 addr20 BTCLR sfr 5 addr20 BTCLR HL 5 addr20 BT sfr 5 addr20 BT HL 5 addr20 BF sfr 5 addr20 BF HL 5 addr20 BTCLR sfr 6 addr20 BTCLR HL 6 addr20 BT sfr 6 addr20 BT HL 6 addr20 BF sfr 6 addr20 BF HL 6 Saddr20 BTCLR sfr 7 addr20 BTCLR HL 7 addr20 BT sfr 7 addr20 BT HL 7 Saddr20 BF sfr 7 addr20 BF HL 7 addr20 5191101002001 HH039Z 9 HdldVHO 195 NOILONYLSNI 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS CHAPTER 6 EXPLANATION OF INSTRUCTIONS This chapter explains the instructions of 78KOR microcontrollers R01US0029EJ0600 Rev6 00 00 31 2011 RENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS DESCRIPTION EXAMPLE Mnemonic Full name Move Byte Data Transfer Meaning of instruc
93. RK RETB Figure 3 4 shows the data saved by various stack operations in the 78KOR microcontrollers Figure 3 4 Data to Be Saved to Stack Memory PUSH rp PUSH PSW instruction instruction 2 byte stack 2 byte stack SP 5 2 t SP gt CALL and CALLT instructions Interrupt and 4 byte stack BRK instructions 4 byte stack SP SP 4 SP lt SP 4 SP gt SP gt Stack pointers can be specified only within internal RAM The target address range is from FOOOOH to FFFFFH be sure not to exceed the internal RAM space If an address outside the internal RAM space is specified write operations to that address will be ignored and read operations will return undefined values R01US0029EJO600 Rev 6 00 16 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 3 REGISTERS 3 2 General Purpose Registers On chip general purpose registers are mapped at addresses FFEEOH to FFEFFH of the RAM These registers consist of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H The bank to be used when an instruction is executed is set by the CPU control instruction SEL RBn In addition that each register can be used as an 8 bit register two 8 bit registers in pairs can be used as a 16 bit register In programming general purpose registers can be described in terms of functional names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Caution
94. RY C 2 Revision History of Preceding Editions Here is the revision history of the preceding editions Chapter indicates the chapter of each edition Edition 2nd edition Description Addition of Caution to 2 6 External Memory Space Chapter CHAPTER 2 MEMORY SPACE Addition of description method and Remark in 4 2 4 Short direct addressing CHAPTER 4 ADDRESSING Addition of Remark in Table 5 5 Operation List Addition of operands ADDW SUBW CMPW INC DEC INCW and DECW in Table 5 5 Operation List Addition of BH and BNH instructions of conditional branch in Table 5 5 Operation List Addition of SKH and SKNH instructions of conditional skip in Table 5 5 Operation List Addition of operands MOV ADDW SUBW CMPW INC DEC INCW and DECW in Table 5 6 List of Instruction Formats Addition of BH BNH SKH and SKNH instructions in Table 5 6 List of Instruction Formats Addition of operands ADDW SUBW CMPW INC DEC INCW and DECW in Table 5 8 Instruction Map 2nd MAP CHAPTER 5 INSTRUCTION SET Addition of operands MOV ADDW SUBW CMPW INC INCW and DECW in CHAPTER 6 EXPLANATION OF INSTRUCTIONS Addition of BH and BNH instructions in 6 13 Conditional Branch Instructions Addition of SKH and SKNH instructions in 6 14 Conditional Skip Instructions CHAPTER 6 EXPLANATION OF INSTRUCTIONS Addition of APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY 3rd edition
95. S HL 0 addr20 ES HL 1 addr20 ES HL 2 addr20 ES HL 3 addr20 ES HL 4 addr20 ES HL 5 addr20 ES HL 6 addr20 ES HL 7 addr20 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 82 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 29 30 Operands saddr 0 addr20 saddr 1 addr20 saddr 2 addr20 saddr 3 addr20 saddr 4 addr20 saddr 5 addr20 saddr 6 addr20 saddr 7 addr20 sfr 0 addr20 sfr 1 addr20 sfr 2 addr20 sfr 3 addr20 sfr 4 addr20 sfr 5 addr20 sfr 6 addr20 sfr 7 addr20 A 0 addr20 A 1 addr20 A 2 addr20 A 3 addr20 A 4 addr20 A 5 addr20 A 6 addr20 A 7 addr20 PSW 0 addr20 PSW 1 addr20 PSW 2 addr20 PSW 3 addr20 PSW 4 addr20 PSW 5 addr20 PSW 6 addr20 PSW 7 addr20 HL 0 addr20 HL 1 addr20 HL 2 addr20 HL 3 addr20 HL 4 addr20 HL 5 addr20 HL 6 addr20 HL 7 addr20 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 83 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 30 30 Mnemonic Operands ES HL 0 addr20 ES H
96. Use of the general purpose register space FFEEOH to FFEFFH as the instruction fetch area or stack area is prohibited 01050029 0600 Rev 6 00 17 Jan 31 2011 RENESAS 78K0R Microcontrollers CHAPTER 3 REGISTERS Table 3 2 List of General Purpose Registers Common to 78K0 Microcontrollers Register Bank Name Functional Name Absolute Name 16 bit Processing 8 bit Processing I 16 bit Processing 8 bit Processing Absolute Address FFEFFH FFEFEH FFEFDH FFEFCH FFEFBH FFEFAH FFEF8H FFEF7H FFEF6H FFEF5H FFEF4H FFEF3H FFEF2H FFEF1H FFEFOH FFEEFH FFEEEH FFEEDH FFEECH FFEEBH FFEEAH FFEE9H FFEE8H FFEE7H FFEE6H FFEESH FFEE4H 2 O mi II C IL L X gt O x gt C C II I II I L_ gt olv II 1 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 18 78 Microcontrollers CHAPTER 3 REGISTERS 3 3 ES and CS Registers The 78K0R microcontrollers have additional ES and CS registers Data access can be specified via the ES register and higher addresses for execution of branch instructions can be specified via the CS register For description of how these registers are
97. ace to flash memory space or RAM space R01US0029EJ0600 Rev 6 00 13 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 3 REGISTERS CHAPTER 3 REGISTERS 31 Control Registers The control registers control the program sequence statuses and stack memory A program counter PC a program status word PSW and a stack pointer SP are the control registers 3 1 1 Program counter PC The program counter is a 20 bit register that holds the address information of the next program to be executed Figure 3 1 Program Counter Configuration 19 0 PC 3 1 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution The ISP1 flag is added as bit 2 in products that support interrupt level 4 The contents of the program status word are automatically stacked when an interrupt request occurs and a PUSH PSW instruction is executed and are automatically restored when an RETB or RETI instruction and a POP PSW instruction is executed The PSW value becomes 06H when a reset signal is input Figure 3 2 Program Status Word Configuration 7 6 5 4 3 2 1 0 1 Interrupt enable flag IE This flag controls the interrupt request acknowledgement operations of the CPU When IE 0 the IE flag is set to interrupt disable DI and interrupts other than non maskable interrupts are all disabled When IE 1 the IE flag is set to interrupt e
98. an the C register contents start of the BH instruction however is in addresses 002D4H to 003D3H R01US0029EJO600 Rev 6 00 168 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if Not Higher than Conditional branch by numeric value comparison Z v CY 1 Instruction format BNH addr20 Operation PC lt PC 3 jdisp8 if Z v CY 1 Operand Operand addr20 Description e When Z v CY 1 data is branched to the address specified by the operand When Z v CY 0 no processing is carried out and the subsequent instruction is executed e This instruction is used to judge which of the unsigned data values is higher It is detected whether the first operand is not higher than the second operand the first operand is equal to or lower than the second operand in the CMP instruction immediately before this instruction Description example CMP A C BNH 00356H Branch to address 00356H when the A register contents are equal to or lower than the C register contents start of the BNH instruction however is in addresses 002D4H to 003D3H R01US0029EJO600 Rev 6 00 169 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if True Conditional Branch by Bit Test Byte Data Bit 1 Instruction format BT bit addr20 Operation PC lt PC b jdisp8 if bit 1 Operand Mnemonic Operand bit addr20 b Number of byt
99. bit manipulation instructions MOV1 141 AND1 142 OR1 143 XOR1 144 145 146 147 R01US0029EJ0600 6 00 Jan 31 2011 RENESAS 140 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Move Single Bit 1 Bit Data Transfer Instruction format MOV1 dst src Operation dst lt src Operand Mnemonic Operand dst src Mnemonic Operand dst src CY saddr bit sfr bit CY CY sfr bit A bit CY CY A bit PSW bit CY CY PSW bit HL bit CY CY HL bit CY ES HL bit saddr bit CY ES HL bit CY Flag dst CY dst PSW bit In all other cases Description e Bit data of the source operand src specified by the 2nd operand is transferred to the destination operand dst specified by the 1st operand e When the destination operand dst is CY or PSW bit only the corresponding flag is changed e All interrupt requests are not acknowledged between the MOV1 PSW bit CY instruction and the next instruction Description example MOV1 P3 4 CY The CY flag contents are transferred to bit 4 of port 3 R01US0029EJO600 Rev 6 00 141 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS And Single Bit 1 Bit Data Logical Product Instruction format AND1 dst src Operation dst dst src Operand Mnemonic Operand dst src CY saddr bit CY sfr
100. d addr16 bit This manipulation can also be specified with an address 8 bit manipulation Describe the symbol reserved by the assembler for the 8 bit manipulation instruction operand laddr16 This manipulation can also be specified with an address e 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand laddr16 When specifying an address describe an even address R01US0029EJ0600 Rev 6 00 12 Jan 31 2011 RENESAS lt R gt 78K0R Microcontrollers CHAPTER 2 MEMORY SPACE 2 6 External Memory Space The external memory space that can be accessed by setting the memory expansion mode register This memory space is allocated from flash memory to EDFFFH As the external pins in separate mode 28 pins A19 to A0 and D7 to D0 are available In multiplexed mode 20 pins A19 to A8 and AD7 to AD0 are available For pin settings when using external memory refer to the chapter describing port functions in the user s manual for each product Cautions 1 When fetching the instructions in an external memory area start the execution by the branch instructions CALL or BR in flash memory or RAM memory areas and end the execution by return instructions RET RETB or RETI in an external memory area While flash memory area is adjacent to an external memory area serial program can not be executed 2 Do not use relative addressing in branch instructions from external memory sp
101. d SP byte MOVW SP AX CALL instruction CALLT instruction BRK ADDW SP byte instruction SOFT instruction RET instruction SUBW SP byte RETI instruction RETB instruction interrupt PUSH instruction POP instruction C5 MOV CS byte CALL rp MOV CS A BR AX AX Write instruction to A register BR AX Write instruction to X register Write instruction to AX register SEL RBn AX Write instruction to A register CALL rp BC Write instruction to X register DE Write instruction to B register HL Write instruction to C register Note Write instruction to D register Write instruction to E register Write instruction to H register Write instruction to L register Write instruction to AX register Write instruction to BC register Write instruction to DE register Write instruction to HL register SEL RBn Note Note Note Note Note Register write instructions also require wait insertions when overwriting the target register values during direct addressing short direct addressing register indirect addressing based addressing or based indexed addressing R01US0029EJO600 Rev 6 00 190 Jan 31 2011 ztENESAS 78 Microcontrollers APPENDIX INSTRUCTION INDEX MNEMONIC BY FUNCTION APPENDIX A INSTRUCTION INDEX MNEMONIC BY FUNCTION 8 bit data transfer instructions MCV 93 XCH 95 ONEB 96 CL 8 97 MOVS 98 16 bit data transfer instructions MOVW 100 XCHW 102
102. d C AX AX word BC word BC AX AX SP byte Note Only when rp BC DE or HL Operand dst src SP byte AX BC saddrp BC addr16 DE saddrp DE addr16 HL saddrp HL laddri6 AX ES laddr16 ES laddr16 AX AX ES DE ES DE AX AX ES DE byte ES DE byte AX AX ES HL ES HL AX AX ES HL byte ES HL byte AX AX ES word B ES word B AX AX ES word C ES word C AX AX ES word BC ES word BC AX BC ES laddr16 DE ES laddri 6 HL ES laddri 6 R01US0029EJ0600 Rev 6 00 Jan 31 2011 100 RENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Flag Description e The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand Description example MOVW AX HL The HL register contents are transferred to the AX register Caution Only an even address can be specified An odd address cannot be specified SUL a LSS S Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Exchange Word Word Data Exchange Instruction format XCHW dst src Operation dst lt gt src Operand Operand dst src Note Only when rp BC DE or HL Description The 1st and 2nd operand contents
103. der certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas El
104. e A A ES HL B ES HL B A A ES HL C ES HL C A ES word B byte A ES word B ES word B A ES word C byte A ES word C ES word C A ES word BC byte A ES word BC ES word BC A B ES laddr16 C ES laddr16 X ES laddr16 A X A C A D A L A H A saddr A sfr laddr16 DE DE byte HL HL byte HL B HL C A ES laddr16 A ES DE A ES DE byte A ES HL A ES HL byte A ES HL B A ES HL C RO1US0029EJ0600 Rev 6 00 57 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 4 30 Mnemonic Operands saddr laddr16 ES laddr16 A X B C saddr laddr16 ES laddr16 HL byte X ES HL byte X AX word BC word DE word HL word saddrp word sfrp word AX saddrp saddrp AX AX sfrp sfrp AX AX BC AX DE AX HL BC AX DE AX HL AX AX addr16 laddr16 AX AX DE DE AX AX DE byte DE byte AX AX HL HL AX AX HL byte HL byte AX AX word B RO1US0029EJ0600 Rev 6 00 58 Jan 31 2011 ztENESAS 78KOR Microcontrollers Mnemonic CHAPTER 5 Table 5
105. e 1st and 2nd operand contents are exchanged Description example XCH A FFEBCH The A register contents and address FFEBCH contents are exchanged R01US0029EJO600 Rev 6 00 95 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS One byte Byte Data 01H Set Instruction format ONEB dst Operation dst 01H Operand Mnemonic Operand dst A X B C saddr laddr16 ES laddr16 Description e 01H is transferred to the destination operand dst specified by the first operand Description example ONEB Transfers 01H to the A register R01US0029EJO600 Rev 6 00 96 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Clear byte Byte Data Clear Instruction format CLRB dst Operation dst lt 00H Operand Mnemonic Operand dst A X 8 C saddr laddr16 ES laddr16 Description OOH is transferred to the destination operand dst specified by the first operand Description example CLRB A Transfers to the A register R01US0029EJO600 Rev 6 00 97 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Move and change PSW Byte Data Transfer and PSW Change Instruction format MOVS dst src Operation dst lt src Operand Operand dst src HL byte X ES HL byte X Description The cont
106. eN6 s lt sAS 78 Microcontrollers CHAPTER 4 ADDRESSING 42 3 Direct addressing Function Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address Operand format ADDR16 Label or 16 bit immediate data only the space from F0000H to FFFFFH is specifiable ES ADDR16 Label or 16 bit immediate data higher 4 bit addresses are specified by the ES register Figure 4 8 Example of ADDR16 FFFFFH OP code Low Addr High Adar F0000H Memory Figure 4 9 Example of ES ADDR16 FFFFFH EH Low Addr High Adar Y 00000H Memory R01US0029EJO600 Rev 6 00 25 Jan 31 2011 ztENESAS 78K0R Microcontrollers CHAPTER 4 ADDRESSING 4 2 4 Short direct addressing Function Short direct addressing directly specifies the target addresses using 8 bit data in the instruction word This type of addressing is applied only to the space from FFE20H to FFF1FH Operand format Identifier Description Label FFE20H to FFF1FH immediate data or OFE20H to 0FF1FH immediate data only the space from FFE20H to FFF1FH is specifiable SADDRP Label FFE20H to FFF1FH immediate data or 0FE20H to 0FF1FH immediate data even address only only the space from FFE20H to FFF1FH is specifiable Figure 4 10 Outline of Short Direct Addressing OP code FFF1FH saddr FFE20H Memory Remark SADDR and SAD
107. ecial Function Registers SFRS 20 3 4 1 Processor mode control register PMC u 20 CHAPTER 4 ADDRESSINGQ J J J J J J J J J J QU J J da J J 21 4 1 Instruction Address Addressing l J J J J J 21 4 1 1 Relative addressing I l U ____________ _ __ __ _ _ _ _ _ 21 41 2 Immediate addressing uuu 22 4 1 3 Table indirect addressing 1 U U uuu uu 22 44 4 Register direct 2 aad DESETE NEon 23 42 Addressing for Processing Data Addresses J 24 24 4 2 2 Register addressing iniret esie eds edic dv dte ebd dele oe 24 4 2 3 Direct addressing 25 4 2 4 Short direct addressing u 26 4 2 5 SER addressing cti f ett tatiana dll e ie oe ras 27 4 2 6 Register indirect 28 427 Based addressirnig i ood 29
108. ectronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3
109. el 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jln Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2011 Renesas Electronics Corporation All rights reserved Colophon 1 0 78KOR Microcontrollers 2 1 Renesas Electronics Corporation Previous Number U17792EJ5V0UM00
110. ents of the source operand specified by the second operand is transferred to the destination operand dst specified by the first operand f the src value is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 f the register A value is 0 or if the src value is 0 the CY flag is set 1 In all other cases the CY flag is cleared 0 Description example MOVS HL 2H X When HL FEOOH X 55H A OH X 55H is stored at address FE02H Z flag 0 CY flag 1 since A register 0 R01US0029EJ0600 Rev 6 00 98 Jan 31 2011 ztENESAS 78KOR Microcontrollers 6 2 16 bit Data Transfer Instructions CHAPTER 6 EXPLANATION OF INSTRUCTIONS The following instructions are 16 bit data transfer instructions MOVW 100 XCHW 102 ONEW 103 CLRW 104 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 99 78K0R Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Move Word Word Data Transfer Instruction format Operation Operand Mnemonic MOVW dst src dst src Operand dst src Mnemonic rp word saddrp word sfrp word AX saddrp saddrp AX AX sfrp sfrp AX AX rp rp AX AX addr16 laddr16 AX AX DE DE AX AX DE byte DE byte AX AX HL HL AX AX HL byte HL byte AX AX word B word B AX AX word C wor
111. erface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJ0600 Rev 6 00 45 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 9 17 Instruction Mnemonic Operands Clocks Operation Group Note 1 Note 2 8 bit A byte A A v byte operation saddr byte saddr saddr v byte A r A lt Avr saddr laddr16 HL HL byte A HL B A HL C A ES addr16 A ES HL A ES HL byte A ES HL B A ES HL C A byte saddr byte saddr laddr16 HL HL byte A HL B A HL C A ES addr16 A ES HL A ES HL byte rervA A lt Av saddr lt Av addr16 A lt A v HL lt A v HL byte lt A v HL A lt A v HL C A A v ES addr16 A A v ES HL A A v ES HL byte A A v ES HL A v ES HL C A x byte 0 saddr saddr x byte lt rervA lt A x A A x addr16 A A x HL N C2
112. es BT saddr bit addr20 4 sfr bit addr20 A bit addr20 HL bit addr20 4 3 PSW bit addr20 4 3 4 ES HL bit addr20 Description e If the 1st operand bit contents have been set 1 data is branched to the address specified by the 2nd operand addr20 If the 1st operand bit contents have not been set 1 no processing is carried out and the subsequent instruction is executed Description example BT FFE47H 3 0055CH When bit 3 at address FFE47H is 1 data is branched to 0055CH with the start of this instruction set in the range of addresses 004DAH to 005D9H R01US0029EJO600 Rev 6 00 170 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if False Conditional Branch by Bit Test Byte Data Bit 0 Instruction format BF bit addr20 Operation PC lt PC b jdisp8 if bit 0 Operand Mnemonic Operand bit addr20 b Number of bytes saddr bit addr20 sfr bit addr20 A bit addr20 PSW bit addr20 HL bit addr20 ES HL bit addr20 Flag Description e If the 1st operand bit contents have been cleared 0 data is branched to the address specified by the 2nd operand addr20 If the 1st operand bit contents have not been cleared 0 no processing is carried out and the subsequent instruction is executed Description example BF P2 2 01549H When bit
113. essed For the number of waits refer to 7 2 2 Access to external memory contents as data RO1US0029EJ0600 Rev 6 00 38 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 2 17 Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY 8 bit data MOV A HL byte 2 1 4 A lt HL byte transfer HL byte 2 1 HL lt A HL B 2 1 4 A lt HL B HL B A 2 1 HL B lt A A HL C 2 1 4 A lt HL O HL C A 2 i HL C lt A word B byte 4 1 _ B word byte A word B 3 1 4 lt B word word B 8 1 _ B word A word C byte 4 1 _ C word byte A word C 3 1 4 lt C word word C 3 1 _ C word lt lt A word BC byte 4 1 BC word lt byte A word BC 3 1 4 lt BC word word BC A 3 1 BC word A SP byte byte 3 1 SP byte byte A SP byte 2 1 SP byte SP byte A 2 1 _ SP byte A B saddr 2 1 _ B lt saddr B addr16 3 1 4 B addr16 C saddr 2 1 _ lt saddr C laddr16 3 1 4 C lt addr16 X saddr 2 1 X lt saddr X laddr16 3 1 4 X lt addr16 ES laddr16 byte 5 2 ES addr16 lt byte A ES addr16 4 2 5 A lt ES addr16 ES laddr16 4 2 ES addr16 A A ES DE 2 2 5 A
114. etch is not enabled The following show examples Specifications vary for each product so refer to the user s manual for each product Example 1 FFFFFH FFF00H FFEFFH FFEDFH FF900H FF8FFH F8000H F7FFFH F1000 FOFFF F0800 FO7FF F0000H EFFFFH 08000H 07FFFH 01000H OOFFFH 00000H Flash memory 32 KB RAM 1 5 KB Setting MAA 0 Special function register SFR 256 bytes General purpose register 32 bytes RAM 1 5 KB Reserved Flash memory same data as 01000H to 07FFFH Reserved Special function register 2nd SFR 2KB Mirror For example 02345H is mirrored to F2345H Data can therefore be read by MOV A 2345H instead of MOV ES 00 and MOV A ES 2345H Flash memory Flash memory Example 2 FFFFFH FFFOOH FFEFFH FFEEOH FFEDFH F8700H F86FFH F1000H FOFFFH F0800H 7 F0000H EFFFFH 80000H 7FFFFH 18700H 186FFH 11000H 10FFFH 00000H Flash memory 512 KB RAM 30 KB Setting MAA 1 Special function register SFR 256 bytes General purpose register 32 bytes RAM 30 KB Flash memory same data as 11000H to 186FFH Reserved Special function register 2nd SFR 2KB Mirror For example 15432H is mirrored to F5432H Data can therefore be read by MOV A 5432H instead of MOV ES 01 and MOV A ES 5432H Flash me
115. f execution time is consumed However if the next instruction is a PREFIX instruction indicated by ES two clocks of execution time are consumed e When CY 1 the next instruction is executed All interrupt requests are not acknowledged between this instruction and the next instruction Description example MOV A 55H SKNC ADD A 55H The A register s value when CY 1 and 55H when CY 0 R01US0029EJ0600 Rev 6 00 175 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Skip if Z Skip with Zero Flag Z 1 Instruction format SKZ Operation Next instruction skip if Z 1 Operand None Description e When Z 1 the next instruction is skipped The subsequent instruction is a NOP and one clock of execution time is consumed However if the next instruction is a PREFIX instruction indicated by ES two clocks of execution time are consumed e When Z 0 the next instruction is executed All interrupt requests are not acknowledged between this instruction and the next instruction Description example MOV A 55H SKZ ADD A 55H The A register s value when Z 0 and 55H when Z 1 R01US0029EJ0600 Rev 6 00 176 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Skip if not Z Skip with Zero Flag Z 0 Instruction format SKNZ Operation Next instruction skip if Z 0 Operand
116. ffice equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions un
117. g PMC is prohibited except for initial settings 2 After setting PMC wait for at least one instruction and access the mirror area RO1US0029EJ0600 Rev 6 00 20 Jan 31 2011 ztENESAS lt R gt 78K0R Microcontrollers CHAPTER 4 ADDRESSING CHAPTER 4 ADDRESSING Addressing is divided into two types addressing for processing data addresses and addressing for program addresses The addressing modes corresponding to each type are described below 4 1 Instruction Address Addressing 41 1 Relative addressing Function Relative addressing stores in the program counter PC the result of adding a displacement value included in the instruction word signed complement data 128 to 127 or 32768 to 32767 to the program counter PC s value the start address of the next instruction and specifies the program address to be used as the branch destination Relative addressing is applied only to branch instructions Figure 4 1 Outline of Relative Addressing OP code C DISPLACE 8 16 bits Caution Do not use relative addressing in the following branch instructions Branching from internal program memory space to RAM space or external memory space Branching from RAM space to internal program memory space or external memory space Branching from external memory space to internal program memory space or RAM space R01US0029EJ0600 Rev 6 00 21 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 4 ADDRESSING
118. g flag is set 1 e All interrupt requests are not acknowledged between the SET1 PSW bit instruction and the next instruction Description example SET1 FFE55H 1 Bit 1 of FFE55H is set 1 R01US0029EJ0600 Rev 6 00 145 Jan 31 2011 2 gt 1 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Clear Single Bit Carry Flag 1 Bit Data Clear Instruction format CLR1 dst Operation dst 0 Operand Mnemonic Operand dst saddr bit sfr bit A bit laddr16 bit PSW bit HL bit ES laddr16 bit ES HL bit Flag dst PSW bit dst CY In all other cases Description e The destination operand dst is cleared 0 e When the destination operand dst is CY or PSW bit only the corresponding flag is cleared 0 e All interrupt requests are not acknowledged between the CLR1 PSW bit instruction and the next instruction Description example CLR1 P3 7 Bit 7 of port 3 is cleared 0 R01US0029EJO600 Rev 6 00 146 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Not Single Bit Carry Flag 1 Bit Data Logical Negation Instruction format NOT1 dst Operation dst lt dst Operand Flag Description e The CY flag is inverted Description example NOT1 CY The CY flag is inverted SU a s F TL Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION
119. gister R01US0029EJO600 Rev 6 00 112 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Compare Byte Data Comparison Instruction format CMP dst src Operation dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A HL C saddr byte laddr16 byte A r A ES addr16 nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte ES laddr16 byte A HL B Note Exceptr A Description e The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand The subtraction result is not stored anywhere and only the Z AC and CY flags are changed e If the subtraction result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 f the subtraction generates a borrow out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 e f the subtraction generates a borrow for bit 3 out of bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example CMP FFE38H 38H 38H is subtracted from the contents at address FFE38H and only the flags are changed comparison of contents at address FFE38H and the immediate data R01US0029EJO600 Rev 6 00 113 Jan 31 2011 ztENESAS 78KOR Microcontrollers CH
120. h 00A2h 00A4h 00A6h 00A8h OOAAh OOACh OOAEh 00B0h 00B2h 00B4h 00B6h 00B8h OOBAh OOBCh OOBEh RO1US0029EJ0600 Rev 6 00 79 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET Mnemonic Table 5 6 List of Instruction Formats 26 30 Operands AX BC DE HL SP word SP AX AX SP BC SP DE SP HL SP SP byte SP byte AX addr20 laddr20 laddr16 lladdr20 addr20 addr20 addr20 addr20 addr20 addr20 saddr 0 addr20 saddr 1 addr20 saddr 2 addr20 saddr 3 addr20 saddr 4 addr20 saddr 5 addr20 saddr 6 addr20 saddr 7 addr20 sfr 0 addr20 sfr 1 addr20 sfr 2 addr20 sfr 3 addr20 sfr 4 addr20 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 80 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 6 List of Instruction Formats 27 30 Mnemonic Operands sfr 5 addr20 sfr 6 addr20 sfr 7 addr20 A 0 addr20 A 1 addr20 A 2 addr20 A 3 addr20 A 4 addr20 A 5 addr20 A 6 addr20 A 7 addr20 PSW 0 addr20 PSW 1 addr20 PSW 2 addr20 PSW
121. he number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJ0600 Rev 6 00 44 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 8 17 Instruction Mnemonic Operands Clocks Operation Group Note 1 Note 2 8 bit A byte A CY A byte CY operation saddr byte saddr CY saddr byte CY A r A CY A r CY LA CY r A CY A saddr A CY A saddr CY A laddr16 A CY A addr16 CY A HL A CY A HL CY A HL byte A CY A HL byte CY A HL B A CY lt A HL B CY A HL C A CY A HL C CY A ES addr16 A CY A ES addr16 CY A ES HL A CY A ES HL CY A ES HL byte A CY lt A ES HL byte CY A ES HL B A CY lt A ES HL B CY A ES HL C A CY A ES HL C CY A byte A byte saddr byte saddr laddr16 HL A HL byte A HL A HL C A ES laddr16 A ES HL A ES HL byte
122. he subtraction generates a borrow out of bit 4 to bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example CMPS X HL F0H When HL FD12H The value of X is compared with the contents of address FFEO2H and the Z flag is set if the two values match The value of X is compared with the contents of address FFEO2H and the CY flag is set if the two values do not match The CY flag is set when the value of register A is 0 The CY flag is set when the value of register X is O The AC flag is set by borrowing from bit 4 to bit 3 similar to the CMP instruction R01US0029EJO600 Rev 6 00 115 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 4 16 bit Operation Instructions The following instructions are 16 bit operation instructions ADDW 117 SUBW 118 CMPW 119 SU erg M s Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Add Word Word Data Addition Instruction format ADDW dst src Operation dst lt dst src Operand Mnemonic Operand dst src AX word AX AX AX BC AX DE AX HL AX saddrp AX laddr16 AX HL byte AX ES laddr16 AX ES HL byte Description e The destination operand dst specified by the 1st operand is added to the source operand src specified by the 2nd operand and the result is stored
123. in the destination operand dst e If the addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e f the addition generates a carry out of bit 15 the CY flag is set 1 In all other cases the CY flag is cleared 0 e As a result of addition the AC flag becomes undefined Description example ADDW AX ABCDH ABCDH is added to the AX register and the result is stored in the AX register R01US0029EJO600 Rev 6 00 117 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Subtract Word Word Data Subtraction Instruction format SUBW dst src Operation dst CY dst src Operand Mnemonic Operand dst src AX word AX BC AX DE AX HL AX saddrp AX laddr16 AX HL byte AX ES laddr16 AX ES HL byte Description e The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand and the result is stored in the destination operand dst and the CY flag e If the subtraction shows that dst is O the Z flag is set 1 In all other cases the Z flag is cleared 0 f the subtraction generates a borrow out of bit 15 the CY flag is set 1 In all other cases the CY flag is cleared 0 e As a result of subtraction the AC flag becomes undefined Description example SUBW AX ABCDH ABCDH is subtracted from
124. ing an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 cnt indicates the bit shift count 4 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01USO0029EJ0600 Rev 6 00 49 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Instruction Mnemonic Operands Clocks Operation Group Rotate Table 5 5 Operation List 13 17 Note 1 Note 2 A 1 Ao 1 lt Am x 1 1 Az 1 An x 1 A 1 CY Az amp CY Ami lt Am x 1 A 1 8C 1 CY lt 55 lt CY 1 x 1 lt BCis lt 1 lt 22 1 CY lt CV 1 Am x 1 manipulate CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit saddr bit CY sfr bit CY
125. ion and functions as a bit accumulator during bit manipulation instruction execution 3 1 3 Stack pointer SP This is a 16 bit register that holds the start address of the memory stack area Only the internal RAM area can be set as the stack area Figure 3 3 Stack Pointer Configuration The SP is decremented ahead of write save to the stack memory and is incremented after read restored from the stack memory Since reset signal generation makes the SP contents undefined be sure to initialize the SP before using the stack In addition the values of the stack pointer must be set to even numbers If odd numbers are specified the least significant bit is automatically cleared to 0 In the 78KOR microcontrollers since the memory space is expanded the stack address used for a CALL instruction or interrupt is 1 byte longer and 2 byte or 4 byte stack size is used because the RAM for the stack is 16 bits long refer to Table 3 1 Caution Itis prohibited to use the general purpose register FFEEOH to FFEFFH space as a stack area R01US0029EJO600 Rev 6 00 15 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 3 REGISTERS Table 3 1 Stack Size Differences Between 78K0 Microcontrollers and 78K0R Microcontrollers Save Instruction Restore Stack Size of 78K0 Stack Size of 78KOR Instruction Microcontrollers Microcontrollers PUSH rp POP rp PUSH PSW POP PSW CALL CALLT RET Interrupt RETI B
126. ion in accordance with the description method of the instruction operand identifier refer to the assembler specifications for details When there are two or more description methods select one of them Alphabetic letters in capitals and the symbols and ES are keywords and are described as they are Each symbol has the following meaning e Immediate data specification I 16 bit absolute address specification e 20 bit absolute address specification e _ 8 bit relative address specification e 16 bit relative address specification e Indirect address specification e ES Extension address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and ES symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description R01US0029EJ0600 Rev 6 00 34 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 1 Operand Identifiers and Description Methods Identifier Description Method r rp sfr sfrp X RO A R1 C R2 B E R4 D R5 L 86 R7 AX RPO BC RP1 DE RP2 HL RP3 Special function register symbol SFR symbol FFFOOH to FFFFFH Special function register symbols 16 bit manipulatable SFR symbol Even
127. ion is met Remarks 1 One instruction clock cycle is one cycle of the CPU clock ICL selected by the system clock control register 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area n indicates the number of register banks n 0 to 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJO600 Rev 6 00 54 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET 5 6 Instruction Format Instructions consist of fixed opcodes followed by operands Their formats are listed below Table 5 6 List of Instruction Formats 1 30 Mnemonic Operands X byte A byte C byte B byte E byte D byte L byte H byte saddr byte sfr byte laddr16 byte X A A B A E
128. lected by the system clock control register 2 This number of clocks is for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data RO1US0029EJ0600 Rev 6 00 41 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 5 17 Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY 16 bit MOVW AX addr16 3 1 4 AX lt addr16 data laddr16 AX 3 1 addr16 vee AX DE 1 1 4 lt DE DE AX 1 1 DE AX AX DE byte 2 1 4 AX lt DE byte DE byte AX 2 1 DE byte AX AX HL 1 1 4 AX lt
129. m except when branching to the external memory area In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJ0600 Rev 6 00 50 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 14 17 Instruction Mnemonic Operands Clocks Operation Group Note 1 Note 2 Bit CY saddr bit manipulate CY sfr bit lt saddr bit lt CY sfr bit CY lt CY x A bit lt CY x PSW bit CY lt CY x HL bit CY lt CY x ES HL bit saddr bit 1 CY A bit CY PSW bit CY HL bit CY ES HL bit saddr bit sfr bit A bit laddr16 bit PSW bit HL bit ES laddr16 bit ES HL bit sadar bit sfr bit A bit laddr16 bit PSW bit HL bit ES laddr16 bit ES HL bit CY sfr bit 1 A bit 1 addr16 bit 1 PSW bit 1 HL bit 1 ES addr16 bit 1 ES HL bit lt 1 saddr bit 0
130. m shows that all bits are 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 Description example OR A FFE98H The bit wise logical sum of the A register and FFE98H is obtained and the result is stored in the A register R01US0029EJO600 Rev 6 00 111 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Exclusive Or Exclusive Logical Sum of Byte Data Instruction format XOR dst src Operation dst dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A HL B saddr byte A HL C A ES addr16 nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte Note Exceptr Description e The bit wise exclusive logical sum is obtained from the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and the result is stored in the destination operand dst Logical negation of all bits of the destination operand dst is possible by selecting 0FFH for the source operand src with this instruction f the exclusive logical sum shows that all bits are O the Z flag is set 1 In all other cases the Z flag is cleared 0 Description example XOR A L The bit wise exclusive logical sum of the A and L registers is obtained and the result is stored in the A re
131. mat SARW dst cnt Operation lt dsto dstm 1 lt dstm dstis lt 05115 x cnt Operand Operand dst cnt Description e The destination operand dst specified by the first operand is shifted to the right the number of times specified by cnt e The same value is retained in the MSB bit 15 and the value shifted last from bit 0 is entered to CY e cnt can be specified as any value from 1 to 15 15 0 CY Description example SAR AX 4 When the AX register s value is A28CH AX FA28H and CY 1 AX 1010 0010 1000 11008 CY 0 21101 0001 0100 0110B CY 0 1 time AX 21110 1000 1010 0011B CY 0 2times AX 21111 0100 0101 0001B CV 1 3times AX 21111 1010 0010 10008 CV 1 4times R01US0029EJO600 Rev 6 00 133 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 8 Rotate Instructions The following instructions are rotate instructions ROR 135 ROL 136 RORC 137 ROLC 138 ROLWC 139 D SS EE Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Rotate Right Byte Data Rotation to the Right Instruction format ROR dst cnt Operation CY dst lt dsto dstm 1 x one time Operand Operand dst cnt Flag Description e The destination operand dst contents specified by the 1st operand are rotated to the right just once e The LSB bit 0 contents are simultaneou
132. mbers of clocks are listed in 5 5 Operation List 7 2 1 Access to flash memory contents as data When the content of the flash memory is accessed as data the pipeline operation is stopped at the MEM stage Therefore the number of operation clocks is increased from the listed number of clocks For details refer to 5 5 Operation List 7 2 2 Access to external memory contents as data When the content of the external memory is accessed as data the CPU is set to wait mode Therefore the number of operation clocks is increased from the listed number of clocks For the number of increased clocks refer to Table 7 1 below Table 7 1 CPU Wait During Read Write from to External Memory Clock for Selecting External Extension Clock Output CLKOUT Wait Cycles fouk 3 clocks ICLM 2 5 or 6 clocks ICLM 3 7 to 9 clocks ICL 4 9 to 12 clocks Remark 1 clock 1 ICLX CPU clock 7 2 3 Instruction fetch from RAM When data is fetched from RAM the instruction queue becomes empty because reading from RAM is late So the CPU waits until the data is set to the instruction queue During fetch from RAM the CPU also waits if there is RAM access The number of clocks when instructions are fetched from the internal RAM area is twice the number of clocks plus 3 maximum except when branching to the external memory area when fetching an instruction from the internal ROM flash memory area R01US0029EJ0600 Rev 6 00 188 Jan 31 2
133. mory Flash memory Remark MAA Bit 0 of the processor mode control register PMC for details refer to 3 4 1 Processor mode control register PMC R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 10 lt R gt 78KOR Microcontrollers CHAPTER 2 MEMORY SPACE 2 2 2 Vector table area In the 78KOR microcontrollers the 128 byte area from 0000H to 007FH is reserved as the vector table area The number of interrupts is calculated as 61 maximum RESET vector on chip debugging vector software break vector Since there are only 2 bytes of vector code the interrupt branch destination start address is 64 KB from 00000H to OFFFFH While in the 78K0 microcontrollers addresses from 0040H to 007FH are used for the CALLT table in the 78KOR microcontrollers these have been changed to vector addresses 2 2 3 CALLT instruction table area In the 78KOR microcontrollers the 64 byte area from 0080H to OOBFH is reserved as the CALLT instruction table area While single byte CALL instructions are used in the 78KO microcontrollers the 78KOR microcontrollers use 2 byte CALL instructions Addresses have also been changed accordingly Since the address code is only 2 bytes long the interrupt branch destination start address is 64 KB from 00000H to OFFFFH 2 3 Internal Data Memory Internal RAM Space The 78K0 microcontrollers include internal high speed RAM and internal expansion RAM whereby the internal high speed RAM is
134. n The following instruction is an unconditional branch instruction BR 162 SIS a SSS SS Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch Unconditional Branch Instruction format BR target Operation PC lt target Operand Mnemonic Operand target AX addr20 laddr20 laddr16 lladdr20 Flag Description e This is an instruction to branch unconditionally e The word data of the target address operand target is transferred to PC and branched Description example BR 12345H Branch to address 12345H R01US0029EJ0600 Rev 6 00 162 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 13 Conditional Branch Instructions The following instructions are conditional branch instructions BC 164 BNC 165 BZ 166 BNZ 167 BH 168 BNH 169 BT 170 171 BTCLR 172 R01US0029EJ0600 Rev 6 00 Jan 31 2011 RENESAS 163 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if Carry Conditional Branch with Carry Flag CY 1 Instruction format BC addr20 Operation PC lt PC 2 jdisp8 if CY 1 Operand Operand addr20 Flag Description e When CY 1 data is branched to the address specified by the operand When CY 0 no processing is carried out and the subsequent instruction is executed Descripti
135. nable El and interrupt request acknowledgement is controlled by an interrupt mask flag for various interrupt sources and a priority specification flag This flag is reset 0 upon DI instruction execution or interrupt request acknowledgment and is set 1 upon execution of the LI instruction 2 Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases R01US0029EJO600 Rev 6 00 14 Jan 31 2011 ztENESAS 78K0R Microcontrollers CHAPTER 3 REGISTERS 3 Register bank select flags RBS0 and RBS1 These are 2 bit flags used to select one of the four register banks In these flags the 2 bit information that indicates the register bank selected by SBL RBn instruction execution is stored 4 Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 lt is reset 0 in all other cases 5 In service priority flags ISP0 and ISP1 This flag manages the priority of acknowledgeable maskable vectored interrupts The vectored interrupt requests specified as lower than the ISPO and ISP1 values by the priority specification flag register PR are disabled for acknowledgment Actual acknowledgment for interrupt requests is controlled by the state of the interrupt enable flag IE 6 Carry flag CY This flag stores an overflow or underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execut
136. ncluding the CY flag R01US0029EJO600 Rev 6 00 137 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Rotate Left with Carry Byte Data Rotation to the Left with Carry Instruction format ROLC dst cnt Operation lt dst dsto lt CY dstm 1 lt x one time Operand Mnemonic Operand dst cnt Description e The destination operand dst contents specified by the 1st operand are rotated just once to the left with carry CY 7 0 Description example ROLC A 1 The A register contents are rotated to the left by one bit including the CY flag R01US0029EJ0600 Rev 6 00 138 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Rotate Left word with Carry Word Data Rotation to the Left with Carry Instruction format ROLWC dst cnt Operation CY lt dstis dsto CY dstm 1 x one time Operand Operand dst cnt Flag Description e The destination operand dst contents specified by the 1st operand are rotated just once to the left with carry CY 15 0 Description example ROLWC 1 The BC register contents are rotated to the left by one bit including the CY flag R01US0029EJ0600 Rev 6 00 139 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 9 Bit Manipulation Instructions The following instructions are
137. nter PC the contents of a general purpose register pair AX BC DE HL and CS register of the current register bank specified with the instruction word as 20 bit data and specifies the program address Register direct addressing can be applied only to the CALL AX BC DE HL and BR AX instructions Figure 4 5 Outline of Register Direct Addressing PG R01US0029EJ0600 Rev 6 00 23 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 4 ADDRESSING 4 2 Addressing for Processing Data Addresses 4 2 1 Implied addressing Function Instructions for accessing registers such as accumulators that have special functions are directly specified with the instruction word without using any register specification field in the instruction word Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Implied addressing can be applied only to MULU X Figure 4 6 Outline of Implied Addressing A register Memory 4 2 2 Register addressing Function Register addressing accesses a general purpose register as an operand The instruction word of 3 bit long is used to select an 8 bit register and the instruction word of 2 bit long is used to select a 16 bit register Operand format X A C B E D L H AX BC DE HL Figure 4 7 Outline of Register Addressing OP code Memory R01US0029EJ0600 Rev 6 00 24 Jan 31 2011 st
138. number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data RO1US0029EJ0600 Rev 6 00 48 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Table 5 5 Operation List 12 17 Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 Z AC CY Increment INC r 1 1 _ lt I 1 x x decrement saddr 2 2 _ saddr lt saddr 1 x x laddr16 3 2 _ addr16 addr16 1 HL byte 3 2 HL byte HL byte 1 x x ES laddr16 4 3 _ ES addr16 ES addr16 1 x X ES HL byte 4 3 _ ES HL byte ES HL byte 1 x x DEC r 1 1 rer 1 X x saddr 2 2 _ saddr saddr 1 x x laddr16 3 2 _ addr16 lt addr16 1 x x HL byte 3 2 HL byte lt HL byte 1 x x ES laddr16 4 3 _ ES addr16 ES addr16 1 x xX ES HL byte 4 3 ES HL byte ES HL byte 1 x x INCW rp 1 1 lt rp 1 2 2 _ saddrp lt saddrp 1 laddr1
139. ocontrollers CHAPTER 7 PIPELINE CHAPTER 7 PIPELINE 7 1 Features The 78K0R microcontroller uses three stage pipeline control to enable single cycle execution of almost all instructions Instructions are executed in three stages instruction fetch IF instruction decode ID and memory access MEM Figure 7 1 Pipeline Execution of Five Typical Instructions Example Elapsed time state Internal system clock HH LL te es 1 1 I L Concurrent processing by CPU lt gt lt gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 I I End of End of End of End of End of i instruc instruc instruc instruc instruc I 1 tion2 tion3 1 tion4 tion5 i e IL instruction fetch Instruction is fetched and fetch pointer is incremented e 10 instruction decode Instruction is decoded and address is calculated MEM memory access Decoded instruction is executed and memory at target address is accessed R01US0029EJ0600 Rev 6 00 187 Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 7 PIPELINE 7 2 Number of Operation Clocks Although a problem in which the count clocks cannot be counted occurs in some other pipeline microcontrollers the 78KOR microcontroller solves this problem by maintaining operation at the same number of clocks and thus stable programs can be provided These nu
140. ollers This manual is broadly divided into the following sections CPU functions Instruction set Explanation of instructions It is assumed that readers of this manual have general knowledge in the fields of electrical engineering logic circuits and microcontrollers e To check the details of the functions of an instruction whose mnemonic is known Refer to APPENDICES A and B To check an instruction whose mnemonic is not known but whose general function is known Find the mnemonic in CHAPTER 5 INSTRUCTION SET and then check the detailed functions in CHAPTER 6 EXPLANATION OF INSTRUCTIONS e To learn about the various kinds of 78KOR microcontroller instructions in general Read this manual in the order of CONTENTS e To learn about the hardware functions of 78KOR microcontrollers See the user s manual for each microcontroller Data significance Higher digits on the left and lower digits on the right Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary XXXX or XXXXB Decimal XXXX Hexadecimal XXXXH CONTENTS CHAPTER 1 OVERVIEW 7 1 1 Differences from 78K0 Microcontrollers for Assembler 7 CHAPTER 2 MEMORY SPAGE
141. om F0000H to FFFFFH When a PREFIX operation code is attached as a prefix to the target instruction only one instruction immediately after the PREFIX operation code is executed as the addresses with the ES register value added A interrupt and DMA transfer are not acknowledged between a PREFIX instruction code and the instruction immediately after Table 5 4 Use Example of PREFIX Operation Code Instruction MOV laddr16 byte MOV ES addr16 byte MOV A HL MOV A ES HL Caution Set the ES register value with MOV ES A etc before executing the PREFIX instruction R01US0029EJO600 Rev 6 00 37 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 5 INSTRUCTION SET 5 5 Operation List Table 5 5 Operation List 1 17 Instruction Mnemonic Operands Clocks Operation Group Note 1 Note 2 8 bit data MOV r byte 2 1 _ r lt byte transfer saddr byte 3 1 saddr byte sfr byte 3 1 _ sfr byte laddr16 byte 4 1 _ addr16 byte ee 1 1 lAcr r A me 1 1 lt saddr 2 1 _ lt saddr saddr 2 1 _ saddr A A sfr 2 1 _ A lt sfr sfr A 2 1 sfr lt A A laddr16 3 1 4 lt addr16 laddr16 3 1 _ addr16 A PSW byte 3 3 _ PSW lt byte x x x A PSW 2 1 _ A PSW PSW A 2 3 _ PSW lt A x x x ES byte 2 1 _
142. on example BC 00300H When CY 1 data is branched to 00300H with the start of this instruction set in the range of addresses 0027FH to 0037EH SU a a Oo EO O Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if Not Carry Conditional Branch with Carry Flag CY 0 Instruction format BNC addr20 Operation PC lt PC 2 jdisp8 if CY 0 Operand Operand addr20 Flag Description e When CY 0 data is branched to the address specified by the operand When CY 1 no processing is carried out and the subsequent instruction is executed Description example BNC 00300H When CY 0 data is branched to 00300H with the start of this instruction set in the range of addresses 0027FH to 0037EH R01US0029EJO600 Rev 6 00 165 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Branch if Zero Conditional Branch with Zero Flag Z 1 Instruction format BZ addr20 Operation PC lt PC 2 jdisp8 if Z 1 Operand Operand addr20 Flag Description e When Z 1 data is branched to the address specified by the operand When Z 0 no processing is carried out and the subsequent instruction is executed Description example DEC B BZ 003C5H When the B register is 0 data is branched to 003C5H with the start of this instruction set in the range of addresses 00344H to 00443H SU a
143. p8 if A bit 0 PSW bit addr20 g pes PC lt PC 4 jdisp8 if PSW bit 0 HL bit addr20 85 PC lt PC 3 jdisp8 if HL bit 0 ES HL bit addr20 6 PC PC 4 jdisp8 if ES HL bit 0 saddr bit addr20 209 lt PC 4 jdisp8 II saddr bit 1 then reset saddr bit sfr bit addr20 3 5 lt PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr20 spec PC lt PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr20 3 5 PC lt PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr20 aie PC lt PC 3 jdisp8 if HL bit 1 then reset HL bit ES HL bit addr20 4 6 PC c PC 4 jdisp8 if ES HL bit 1 then reset ES HL bit Conditional skip Next instruction skip if CY 1 Next instruction skip if CY 0 Next instruction skip if Z 1 Next instruction skip if Z 0 Next instruction skip if 7 V CY Next instruction skip if Z v CY 1 CPU control Notes 1 2 3 RBS 1 0 n No Operation IE 1 Enable Interrupt IE O Disable Interrupt Set HALT Mode Set STOP Mode When the internal RAM area SFR area or extended SFR area is accessed or for an instruction with no data access When the program memory area is accessed This indicates the number of clocks when condition is not met when condit
144. roduct SIS a s Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Disable Interrupt Interrupt Disabled Instruction format DI Operation IE lt 0 Operand None Description e Maskable interrupt acknowledgment by vectored interrupt is disabled with the interrupt enable flag IE cleared 0 e No interrupts are acknowledged between this instruction and the next instruction e For details of interrupt servicing refer to the description of interrupt functions in the user s manual for each product SL a aa SS EE Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Halt HALT Mode Set Instruction format HALT Operation Set HALT Mode Operand None Description e This instruction is used to set the HALT mode to stop the CPU operation clock The total power consumption of the system can be decreased with intermittent operation by combining this mode with the normal operation mode SUS Rer T Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Stop Stop Mode Set Instruction format STOP Operation Set STOP Mode Operand None Description e This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system Power consumption can be minimized to only leakage current SIS a Jan 31 2011 RENESAS 78 Micr
145. ructions Publication Date Rev 6 00 Jan 31 2011 Published by Renesas Electronics Corporation 24 NE SAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5444 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 7F No 363 Fu Shing North Road Taipei Taiwan T
146. s CHAPTER 6 EXPLANATION OF INSTRUCTIONS Instruction format Operation Operand Mnemonic Operand dst src r byte MOV dst src dst src saddr byte sfr byte laddr16 byte A r saddr A A sfr sfr A A laddr16 laddr16 A PSW byte A PSW PSW A ES byte ES saddr A ES ES A CS stbyte A CS CS A A DE DE A DE byte byte A DE byte DE byte A A HL Note Exceptr A Mnemonic Operand dst src HL A HL byte byte A HL byte HL byte A A A A word B byte A word B word B word C byte A word C word C A word BC byte A word BC word BC A SP byte byte A SP byte SP byte A B saddr B laddr16 C saddr C laddr16 X saddr X laddr16 ES laddr16 byte A ES laddr16 Mnemonic Move Byte Data Transfer Operand dst src ES laddr16 A A ES DE ES DE A ES DE byte byte A ES DE byte ES DE byte A A ES HL ES HL A ES HL byte byte A ES HL byte ES HL byte A A ES HL B ES HL4B A A ES HL C
147. s for when the program is in the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data R01US0029EJ0600 Rev 6 00 47 Jan 31 2011 st eN6 s lt sAS 78KOR Microcontrollers Instruction Group 16 bit operation Mnemonic Operands AX word CHAPTER 5 Table 5 5 Operation List 11 17 Clocks Note 1 Note 2 Operation AX CY AX word AX AX AX CY lt AX AX AX BC AX CY AX BC AX DE AX CY AX DE AX HL AX CY AX HL AX saddrp AX CY lt AX saddrp AX laddr16 AX CY AX addr16 AX HL byte AX CY AX HL byte AX ES laddr16 AX CY AX ES addr16 AX ES HL byte AX CY lt AX ES HL byte AX
148. sed for increment of a counter for repeated operations and an indexed addressing offset register the CY flag contents are not changed to hold the CY flag contents in multiple byte operation Description example INC B The B register is incremented RO1US0029EJ0600 Rev 6 00 123 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Decrement Byte Data Decrement Instruction format DEC dst Operation dst dst 1 Operand Mnemonic Operand dst r saddr laddr16 HL byte ES laddr16 ES HL byte Description e The destination operand dst contents are decremented by only one e If the decrement result is the Z flag is set 1 In all other cases the Z flag is cleared e f the decrement generates carry for bit 3 out of bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 e Because this instruction is frequently used for a counter for repeated operations the CY flag contents are not changed to hold the CY flag contents in multiple byte operation e If dst is the B or C register or saddr and it is not desired to change the AC and CY flag contents the DBNZ instruction can be used Description example DEC FFE92H The contents at address FFE92H are decremented R01US0029EJO600 Rev 6 00 124 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Increment Word
149. sly rotated to the MSB bit 7 and transferred to the CY flag CY 7 0 Description example ROR A 1 The A register contents are rotated to the right by one bit R01US0029EJ0600 Rev 6 00 135 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Rotate Left Byte Data Rotation to the Left Instruction format ROL dst cnt Operation CY dsto lt dsto dstm 1 dstm x one time Operand Operand dst cnt Flag Description e The destination operand dst contents specified by the 1st operand are rotated to the left just once e The MSB bit 7 contents are simultaneously rotated to the LSB bit 0 and transferred to the CY flag CY 7 0 oj 1 Description example ROL A 1 The A register contents are rotated to the left by one bit R01US0029EJ0600 Rev 6 00 136 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Rotate Right with Carry Byte Data Rotation to the Right with Carry Instruction format RORC dst cnt Operation CY lt dsto dst lt CY dstm 1 dstm x one time Operand Operand dst cnt Flag Description e The destination operand dst contents specified by the 1st operand are rotated just once to the right with carry CY 7 0 Description example RORC A 1 The A register contents are rotated to the right by one bit i
150. ssembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describe the symbol reserved by the assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address e 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address describe an even address Although the 78KOR microcontrollers SFR has the same specifications as in the 78KO microcontrollers some registers differ from the 78KO in cases where addresses are fixed Refer to the user s manual for each product for details 2 5 Extended SFR Second SFR Area Unlike a general purpose register each extended SFR 2nd SFR has a special function Extended SFRs are allocated to the FOOOOH to FO7FFH area SFRs other than those in the SFR area FFFOOH to FFFFFH are allocated to this area An instruction that accesses the extended SFR area however is 1 byte longer than an instruction that accesses the SFR area Extended SFRs can be manipulated like general purpose registers using operation transfer and bit manipulation instructions The manipulable bit units 1 8 and 16 depend on the SFR type Each manipulation bit unit can be specified as follows e 1 bit manipulation Describe the symbol reserved by the assembler for the 1 bit manipulation instruction operan
151. stack enabled while the internal expansion RAM is fetch enabled By contrast the 78KOR microcontrollers have just one RAM area that enables both stack and fetch The higher limit of the address range is fixed to FFEFFH and the range can be extended downward according to the product s mounted RAM size The maximum size is 61 75 KB For a description of the range s lower limit refer to the user s manual for each product The saddr space and general purpose register area from FFEEOH to FFEFFH have the same addresses in the 78KO microcontrollers Cautions 1 Specify the address other than the general purpose register area address as a stack area It is prohibited to use the general purpose register area for fetching instructions or as a stack area 2 Do use relative addressing in branch instructions from RAM space to internal program memory space or external memory space R01US0029EJO600 Rev 6 00 11 Jan 31 2011 ztENESAS 78K0R Microcontrollers CHAPTER 2 MEMORY SPACE 2 4 Special Function Register SFR Area SFRs have specific functions unlike general purpose registers The SFR space is allocated to the area from FFFOOH to FFFFFH SFRs can be manipulated like general purpose registers using operation transfer and bit manipulation instructions The manipulable bit units 1 8 and 16 depend on the SFR type Each manipulation bit unit can be specified as follows e 1 bit manipulation Describe the symbol reserved by the a
152. system clock control register 2 This number of clocks is for when the program is the internal ROM flash memory area When fetching an instruction from the internal RAM area the number of clocks is twice the number of clocks plus 3 maximum except when branching to the external memory area 3 In products where the external memory area is adjacent to the internal flash area the number of waits is added to the number of instruction execution clocks placed in the last address 16 byte max in the flash memory in order to use the external bus interface function This should be done because during pre reading of the instruction code an external memory wait being inserted due to an external memory area exceeding the flash space is accessed For the number of waits refer to 7 2 2 Access to external memory contents as data gt G gt gt C2 IO INIT IN O O O N IN R01US0029EJ0600 Rev 6 00 53 Jan 31 2011 2 gt 1 5 78 Microcontrollers CHAPTER 5 INSTRUCTION SET Instruction Group Conditional branch Mnemonic Operands Clocks Operation Table 5 5 Operation List 17 17 Note 1 Note 2 saddr bit addr20 852 lt PC 4 jdisp8 if saddr bit 0 sfr bit addr20 PC lt PC 4 jdisp8 if sfr bit 0 A bit addr20 gines PC lt PC 3 jdis
153. t the vector address 0007EH 0007FH Because the IE flag is cleared 0 the subsequent maskable vectored interrupts are disabled e The RETB instruction is used to return from the software vectored interrupt generated with this instruction SU a D Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Return Return from Subroutine Instruction format RET Operation PCL lt SP PCH lt SP 1 PCs lt SP 2 SP lt SP 4 Operand None Flag Description e This is a return instruction from the subroutine call made with the CALL and CALLT instructions e The word data saved to the stack returns to the PC and the program returns from the subroutine h soO c Jan 31 2011 RENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Return from Interrupt Return from Hardware Vectored Interrupt Instruction format RETI Operation lt SP PCH lt SP 1 PCs lt SP 2 PSW lt SP 3 SP44 Operand None Description e This is a return instruction from the vectored interrupt e The data saved to the stack returns to the PC and the PSW and the program returns from the interrupt servicing routine e This instruction cannot be used for return from the software interrupt with the BRK instruction e None of interrupts are acknowledged between this instruction and the next instruction to
154. ternative instruction executes a division with shifting so the execution time is longer than DIVUW It is recommended to change this instruction to the added shift instruction HL The execution time of the alternative instruction is longer than ROR4 It is recommended to change this instruction to the added shift instruction HL The execution time of the alternative instruction is longer than ROL4 It is recommended to change this instruction to the added shift instruction None The execution time of the alternative instruction is longer than ADJBA No instruction is added for substitution None The execution time of the alternative instruction is longer than ADJBS No instruction is added for substitution laddr1 1 CALLF is automatically changed to a 3 byte instruction CALL addr16 This can be used without modification B addr16 This instruction is divided into two DEC B DEC C DEC saddr and BNZ addr20 C addr16 These can be used without modification saddr addr16 lt R gt 10 Memory space has changed from 64KB to 1MB and addressing by using ES register and addressing of word BC etc are added Be sure not to assign any address over maximum memory space Especially in based addressing and based indexed addressing an added value must not exceed FFFFH without ES register or FFFFFH with ES register R01US0029EJO600 Rev 6 00 8 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 2 ME
155. tion Instruction format MOV dst src Indicates the basic description format of the instruction Operation dst src Indicates instruction operation using symbols Operand Indicates operands that can be specified by this instruction Refer to 5 2 Symbols in Operation Column for the description of each operand symbol Mnemonic Operand dst src Mnemonic Operand dst src MOV r byte MOV A PSW A saddr IHL A saddr A HL byte 25 PSW byte HL C A Flag Indicates the flag operation that changes by instruction execution Each flag operation symbol is shown in the conventions Conventions Description Unchanged Cleared to 0 Set to 1 Set or cleared according to the result Previously saved value is restored Description Describes the instruction operation in detail e The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand Description example MOV A 4DH 4DH is transferred to the A register RO1US0029EJ0600 Rev 6 00 91 Jan 31 2011 ztENESAS 78 Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS 6 1 8 bit Data Transfer Instructions The following instructions are 8 bit data transfer instructions MCV 93 95 ONEB 96 CLRB 97 MOVS 98 R01US0029EJ0600 Rev 6 00 Jan 31 2011 92 RENESAS 78K0R Microcontroller
156. used referto CHAPTER 4 ADDRESSING After reset the initial value of ES is 0FH and the initial value of CS is 00H Figure 3 5 Configuration of ES and CS Registers 7 6 5 4 3 2 1 0 10 ess ese es 7 6 5 4 3 2 1 0 o ool es ee ori R01US0029EJ0600 Rev 6 00 19 Jan 31 2011 RENESAS 78 Microcontrollers CHAPTER 3 REGISTERS 3 4 Special Function Registers SFRs Table 3 3 describes fixed address SFRs in the 78K0R microcontrollers Table 3 3 List of Fixed SFRs Address Register Name FFFF8H SPL FFFF9H SPH FFFFAH PSW FFFFBH Reserve FFFFCH CS FFFFDH ES FFFFEH FFFFFH 3 41 Processor mode control register PMC This is an 8 bit register that is used to control the processor modes For details refer to 2 2 Internal Program Memory Space PMC s initial value after reset is OOH Figure 3 6 Configuration of Processor Mode Control Register Address FFFFEH After reset R W Symbol 7 6 5 4 3 2 1 0 ew o o o o o o o MA Selection of flash memory space for mirroring to area from FOOOOH to FFFFFH o 00000H to 0FFFFH is mirrored to F0000H to FFFFFH 10000H to 1FFFFH is mirrored to F0000H to FFFFFH Note SFR and RAM areas are also allocated to the range from F0000H to FFFFFH and take priority over other items for the overlapping areas Cautions 1 Set the PMC register only once for initial settings Rewritin
157. yte X AND A HL B AND A HL C BNH addr20 CALLT 008Ah CALLT CALLT CALLT M0V 009Ah 00 00 HL B A CMPS X HL byte OR A HL B OR A HL C SKH CALLT 008Ch CALLT CALLT CALLT 009Ch 00ACh 00BCh A HL C ROLWC AX 1 XOR A HL B XOR A HL C SKNH CALLT 008Eh CALLT CALLT CALLT MOV 009Eh 00AEh 00BEh HL C A ROLWC BC 1 SJ9 041U090J9 A YOMSZ 9 HdldVHO 195 NOILONYLSNI LLOZ Le 00 9 eH 0090f36200SflL0H SVS3N32 88 SET1 addr16 0 MOV1 saddr 0 CY SET1 0 CLR1 saddr 0 MOV1 CY saddr 0 AND1 CY saddr 0 Table 5 9 Instruction Map 3rd MAP OR1 CY saddr 0 XOR1 CY saddr 0 CLR1 16 0 M0V1 sfr 0 CY MOV1 CY sfr 0 AND1 CY sfr 0 OR1 CY sfr 0 XOR1 CY sfr 0 SET1 laddr16 1 MOV1 saddr 1 CY SET1 saddr 1 CLR1 saddr 1 MOV1 CY saddr 1 AND1 CY saddr 1 OR1 CY saddr 1 XOR1 CY saddr 1 CLR1 laddr16 1 MOV1 sfr 1 CY MOV1 CY sfr 1 AND1 CY sfr 1 OR1 CY sfr 1 XOR1 CY sfr 1 SET1 laddr16 2 MOV1 saddr 2 CY SET1 saddr 2 CLR1 saddr 2 MOV1 CY saddr 2 AND1 CY saddr 2 OR1 CY saddr 2 XOR1 CY saddr 2 CLR1 laddr16 2 MOV1 sfr 2 CY MOV1 CY sfr 2 AND1 CY sfr 2 OR1 CY sfr 2 XOR1 CY sfr 2 SET1 laddr16 3 MOV1
158. yte A HL B saddr byte A HL C A r A ES addr16 nA A ES HL A saddr A ES HL byte A laddr16 A ES HL B A HL A ES HL C A HL byte Note Exceptr A Description e The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand and the result is stored in the destination operand dst and the CY flag The destination operand can be cleared to 0 by equalizing the source operand src and the destination operand dst e f the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 e f the subtraction generates a borrow out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 e f the subtraction generates a borrow for bit 3 out of bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example SUB D A The A register is subtracted from the D register and the result is stored in the D register R01US0029EJO600 Rev 6 00 108 Jan 31 2011 ztENESAS 78KOR Microcontrollers CHAPTER 6 EXPLANATION OF INSTRUCTIONS Subtract with Carry Subtraction of Byte Data with Carry Instruction format SUBC dst src Operation dst lt dst src CY Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A HL B saddr byte A HL C

78K0R Microcontrollers User`s Manual for Instructions

Contents

Download Pdf Manuals

Related Search

Related Contents