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eZ80F91 Development Kit User Manual

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1. es 0 1uF MODEM s ND 2 MOD DIS DO NOT USE J6 17 AND J6 35 MAS 4 MAO MATO MA3 SND 4 DD MAO 2 MAB 5 6 MAT MAT 4 vec MAIS 7 8 MAS MAZ 6 voc yO 1 2 MATS 9 m MATA MAS B 9 3 4 lD 2 MAIS 11 42 MATS MAG 11 He 5 8 ID 1 102 MATS 48 14 MAS 13 m GND T 8 iD 0 gD MAZ 15 16 MAT MAG 15 9 10 E MATT 17 18 MAT2 MAT 17 MOD_DIS lt 11 12 o C N DIS MAS 19 20 MAZO MWAIT amp 13 14 MAS 21 2 MAT 1 EM_DO 4 15 16 E 23 24 7 e css 7 18 GA _DIs_ET gt SS EH 25 26 DIS TL psr E 19 20 MAZ 27 28 MAZA EM D7 2 22 22PD7 RIO M CEU 29 30 M CS1 EM D6 23 24 amp PD6 DCDO MCCS 31 m MI EM D5 25 26 22PD5 DSRO MDT 33 34 MDZ EM D4 27 28 amp PD4 DTRO MD3 35 36 MDa MAS 2 EM D3 22 29 30 gt gt PD3_CTSO MDS 37 38 MAS 1 EM D2 31 3 K PD2 RTSO MD 39 40 MDS MATO 3 EM D1 33 34 22PD1 RXDO 4 42 M TORQ MATT GND 35 36 ono lt lt PD0 TxDO 43 44 RD MATZ TH 37 38 PB7 MOSI 45 46 INSTRD MATS 13 PCT RIKE 39 40 PBG
2. Trios R6 10K Ferrite Core VDD U10 CS2 afn EL CS EX IN M TI FL DIS 1 en 512 uot He MEM EN2 MEM_CEN1 P4 13 1102 i MEM CEN2 4 A23 MEM CEN E n 1 R33 H 103 49 MEM CENK MEM CEN3 A i Jn A21 15 1 04 MEM CENA 3 5825 6 os 23 EN RD P 413 A19 17 1 06 25 DISER r 4 M8 321 tor 28 2 Is SIDACTOR P3100SB Ruta AT a Per J20 A16 16 no 1109 un 28 VDD 2 vec M RING EX_FL_DIS EX FL DIS 2 UH AND VDD 22V10A LCC or Sour O4u ca C4 10K R7 0 001uF 0 001uF U12 D 7 0 GND DO CT4 Di i DO Qo E CTs D 7 bs a 6 CT U13 D3 8153 s PL CTT _JP4 1 sot VDD VDD Dt a3 03 af CTO TRIG1 a A DD 5D Be 14 ps as H5 MRESET RESET 39 OVERR N MUX O H4 De 17 16 TRIG1 B Hop bp D5 4 13 GND D7 18 28 Q6 Fag TRIGZ Pin2 H MIN A MUX SEL 13 D7 Q7 8 M IN B M OUT A 44 Se r pH eet pies MINC MOUT B 1 CT WR ick vec 22 VoD e fi MIND M OUT c 22 li al omo A O 42 A GND M_OUT_D AHHH Fina PCA8550 0 1uF 74HCT374 GND 2 K DIS_1 voro y D AN1 44 A 4 A iS oe Be be Be J CS0 a a 4444 n CS1 exp j T rmn 2 eS gt CON_DIS 11 3 MOD DIS E 12221 AN3 PHI En 2 c D PHI 2 7 ha r r r r TQ74LVT125 TQ74LVT125 h GND npn amp AAAA 00 Ik SE EIU i 20 VDD 3 SDA SDA 10 ANS 5 d DCS Ex L cs x E SCL g 30 O 1uF MEM CENZ 6 5 cs2 gt 282 74HCT374 gt gt DIS_IRDA AMEM CENS 8 7 ES VDD GND N6 6
3. 110 49 Figure 14 illustrates the bottom layer silkscreen of the eZ80F91 Module UMO14210 1003 NN O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O OJO o DJP 2002 Thess IL JP1 o 2 O O oo aqd O OO OO oo WE C O O O e gio OQ rm O l9 9 oo oo 0000 sf o dku R o O O O dT TReso T Tess o ike CE O O le O ks amp dran lr O O e Lose dry d Der di les O O C44 Ucas cas Te O O e OO C lo C amp o o OO l Ll o Oo c34 cs 0 LI I caa ONA 2 JOO caso U 1 I T c29 o o OO o 88 d se 9e 8 o u 8 ES ot O O o p o 9 49 O O o ca2 o 9o do L o oo SFIFR i BEJ eo O C38 e loo g Wve ooh 8 83eL C28 o o o O O e o o ol tks oo o O O i R26 l Ty 023 er s O e LY pmi es O PR7 o T6 0000 pocoo oge o dooooooo Je o RI ee o o ollo o o OO 30 ooo o Q9 oo o o o R12 9 m cA ql I V 9 O R o O O Tks o 605 o e o o e g OO c2 MADE IN U S A o j oo OO ZiLOG FAB 9860879 001 REV Figure 14 eZ80F91 Module Bottom Layer
4. eZ80F91 Development Kit User Manual 26 110 The GPIO Data Register receives inputs or provides outputs for each of the seven GPIO lines depending on the configuration of the port See Table 9 Table 9 GPIO Data Register Function Bit 7 6 5 4 3 2 1 0 GPIO DO X GPIO D1 X GPIO D2 X GPIO D3 X GPIO D4 X GPIO D5 X GPIO D6 X GPIO D7 X Modem Reset The Modem Reset signal MRESET is used to reset an optional socket modem This signal is controlled by bit 5 in the register shown in Table 14 The MRESET signal is available at the embedded modem socket interface J9 Pin 1 Setting this bit Low places the optional socket modem into a reset state The user must pull this bit High again to enable the socket modem Reference the appropriate documentation for the socket modem to reset timing requirements User Triggers Two trigger output pins are provided on the eZ80 Development Plat form Labeled J21 Trig2 and J22 Trig1 these pins allow the user a way to trigger external equipment to aid in the debug of the system See Figure 8 for trigger pin details Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 27 J21 J22 r Ground 5 i 7 Trigger output Trig2 Trig Figure 8 Trigger Pins J21 and J22 Bits 6 and 7 in Table 14 are the control bits for the user triggers If either bit is a 1 the corresponding Trig1 and Trig2 signals are driven High
5. 10K _RMB Beaute PC5 DSRKK 2 riouT Riin PDSR1 RH B RUNE 18 R20UT Rain S Rit 1 Pc7_RI lt REN 2 pc3_ctsi lt 11 gaour Rain cTs1 ____ e z RxD Hesder 3 PC1 RXDI RAOUT RAIN L8 DCD pce_pcpK 1 amp RsoUT RSIN DCD1 a F4 o i MAX3245CAI UM014210 1003 eZ80F91 Development Kit User Manual 64 riL E GND 9VDC __ ovpc U23 pp MZ805C TO220005A 5v vec li No 1 iN vcc RXE160 a He 2 c20 c19 5 ol E HEADER 5 oid Teno J13 D6 4 N Ei A see 41 A RESET 1 m PWR JACK L 275 C23 gt gt RESET 0 1 Zur sw4 oe vin vout H2 VDD gt pp GND p2 Ho LT1086 3 3 TO220 _Ixpo____2 CTSO 7 RXDO Ea c29 ES 5 1 4 Pd 0 1 Ha REDA CONSOLE GREEN J15 DB9 Female 3 3 OK 1 gt gt GND H2 gt gt DIS_0 RS485_1_EN R17 10K u26 1 PD1 RXDO Oro wH vec RE 7 R23 lt RE BP c J17 PD2_RTSO 3 pe ALS Our 120 15 1 DI GND 1 bd 1 DS1487 1 3 RT_1 GND 4 5 u27 1 1 PC1 RXDi O s wH 1 8 2d RE B pZ con8 PC2_RTS1 3 6 cts DE A 0 1uF R22 PCO_TXD1 4 Ls GND DI GND ae 120 DS1487 P3 1 DCD1 4 DSRI 6 RDI 215 J1
6. CS3 sa gt B VDD EX SEL R LTP 757 Tramos 7 13 10K R10 R11 R12 10K 10K 10K U15 2 GND DIS EM 1 3 4 m EM RD mE EM Dh EM p7 EMEN 4 EM WR 21 MD Ll swt A 5 is pee Lum Ba 20 EM D3 EM De o o 3 PBO TO B A 14 1103 AN We B4 H9 EM DIS EM D4 s A a s 1 04 gt DIS_ETH es H ate EM po SWPUSPBUTTON 16 1 05 B6 EMDR EM AS B r 1 06 CS3 B7 18 ENDS EM D1 sw2 A 12 l vor A6 B8 9 EM_DO t o o gt gt PB1_T1_I A5 13 4o 1109 AT SW PUSHBUTTON MEMRO 164 41 VDD sya IORQ Men EM WR OE 143 uS IORQ gt 2 cLk l0 GND c 2 OEAB vcc o o gt gt PB2_SS O 1uF DEBA AND SW PUSHBUTTON 22V10A LCC 0 ND VDD L CEAB VDD D CEBA GND UM014210 1003 Figure 19 ez80 Development Platform Schematic Diagram 2 of 5 74LCX543 SO GND PRELIMINARY Schematic Diagrams A 23 0 DI7 0 DI 0 gt Ua MEM CEN1 MEM_CEN2 MEM_CEN3 MEM_CEN4 UM014210 1003 e ESSE VDD VDDO voz T vsso 10 SNQ AS7C34096 C9 0 1uF D 7 O po LZ Do Dy Fg DT 1F D2 B EP D3 25 D4 Da HS Ds 20 D pz H0 d A 23 0 U18 VDD vppo 24 yop E225 MEM CEN2 3 GE T on E 0 1uF OE vsso 10 S84 vss1 28 AS7C34096 A 23 0 DJ u19 po A D1 11 D2 D2 uz D3 3 25 D4 pa 25 DS Fe DS pe 30 7 VDDO vg VDD1 c11 0 1uF vsso Sy VSS1
7. RH ms ES TCK TDI TRSTN d RESET WP MILCRS MILCOL MILRXER MILRXDV MILRXD3 04 MII_RXD2 MILRXD1 MILRXDO MILRXCLK MIL TXCLK Y2 C8 200k C9 ti 3 3jiH 5pF 10pH C10 0 1uF VCC RTC vop 9 755 vcc CR1 1N5817 R28 220 pares vu a R38 10M FILT_IN XIN XOUT 22 RTC_VDD 2 j RTC_XOUT c11 12pF GND C12 12pF UM014210 1003 61 RTC_XIN EZ80F91 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 MII_TXD3 MIL_TXD2 MILTXD1 MII_TXDO MII TXEN MILTXER Mil MDC MII MDIO TORQ MRQ RD WR BUSACK cso cst CS2 CS3 SCL SDA PA7 PWM3 PAG PWM2 EC1 PA5 PWM1 TOUT1 PA4 PWMO TOUTO PA3 PWM3 OC3 PA2 PWM2 OC2 PA1 PWM1 OC1 PAO_PWM0_OCO SoL MCSCL IICSDA E B PAT PB7 PC7 A 0 23 R18 10K VCC u6 vec PCSB ISODEF Iso REFCLK BURN IN RST PWRDN PHYAD4 ORXD PHYAD3_10RXD PHYAD2_10TXD PHYAD1_10TXD PHYADO_10TXD GPIO0_10TXD GPIO1 TP125 MDIO MDC RXCLK RXD3 RXD2 RXD1 RXDO RXDV RXER_RXD4 TXCLK PCSBPCLK TXD3 TXD2 TXD1 TXDO TXEN TXER TXD4 COL CRS AM79C874 PA O 7 c4 C50 O 1pF 0 1jF GND Put caps between pairs of U6 10 11 51 52 59 65 and 71 73 as close to the pins as possible PB 0 7 PLLVCC OVDD1 VDD1 VDD2 OVDD2 CRVVCC ADOVCC 8
8. ZiLOG eZ80F91 Development Kit User Manual PRELIMINARY UMO14210 1003 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com eZ80F91 Development Kit User Manual Z Diog This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www zilog com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2003 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is not authorized
9. 0 0 0 0 KK KK 21 GPIO Connector J6 aoc hee et 22 CPU Bus Connector J8 2 2 reri cia cias Ek al ku 24 LED and Port Emulation Addresses 25 LED Anode GPIO Output Control Register 25 GPIO Data Register 0 0 0 KK KK KK KK KK eee 26 Connectot J5 4 cise ney hee pais 28 Connector J9 2 5 eser ke ERR Recien gaj 28 Connector Jl i2 eeu ees ee ee eh ee ee 29 Chip Select Wait States 0 0 0 0 0 000 000 0048 33 Bit Access to the LED Cathode Modem and Triggers 34 J2 DIS_IrDA J kk kk kk eed obe kena 36 J3 DIS_EM ira kk k kk k kk k kk k k k 36 J7 FlashWE Off Chip kk kK KK RR KK gt 37 J11 EN_FLASH Off Chip WR KK K8 37 J12 5VDC 3 3VDC for an Embedded Modem 38 JI4 RI ie ee nm ker eR hee k 38 JI5 RS485 1 EN 24 a sl a K W n na E ees 39 J16 RS485 2 EN 2345333 20 34803230 Weka a k di xane ee 39 JIT RT D j nay k ek K n ne k HE Ki ewan 40 JIS RE 2 siyay a ea Cere hea 40 Jl 9 EX_SEL ef ebb Gb pa darl db ii k a dibn du 41 PRELIMINARY List of Tables ix x eZ80F91 Development Kit User Manual 110 Table 26 J20 EX_FL_DIS hs kk KK KK KK RIA 41 Table 27 I C Addresses List of Tables PRELIMINARY UMO14210 1003 eZ80F91 Development Kit Introduction User Manual 110 The eZ80F91 Development Kit provides a general purpose platform for evaluating the capabilities and op
10. 8 8 f RD o ol o foj e RESET E E o ol o lol o susack B B o o EX TRIG2 RIGI NMI S S o ol M FL_DIS GND E E o ol 00000001 o ol o o p o ol TV P o ol min oonan o2 HEMED HEHE Ms 00000001 Hu ln 0 12 pedi E PB2 o RESET plo ol aie 9 oO Bun m Blo o o ol Y 5 1mm gt lt 165 1 mm Figure 5 Physical Dimensions of the eZ80 Development Platform UM014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual 10 Diog Operational Description The eZ80 Development Platform can accept any eZ80 core based modules provided that the module interfaces correctly to the eZ80 Development Platform The purpose of the eZ80 Development Platform is to provide the application developer with a tool to evaluate the features of the eZ80F91 device and to develop an application without building additional hardware eZ80F91 Module Interface The eZ80 Development Platform provides an easy interface for connect ing each of the development modules in the eZ80 family including the eZ80F91 Module The eZ80F91 Module interface consists of two 50 pin receptacles JP1 and JP2 a third receptable JP3 enables the program ming of internal on chip Flash memory Each is described in the pages that follow Almost all of these receptacles signals are connected directly to the CPU Five input signals in particular offer options to the application developer by disabling certain
11. CMOS technology LVC drivers I O Functionality The eZ80 Development Platform provides I O functionality These func tions are memory mapped with an address decoder based on the Generic Array Logic GAL22IV 10D U15 device manufactured by Lattice Semi conductor and a bidirectional latch U16 Additionally U15 is used to decode addresses for access to the 7x5 LED matrix Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Am 110 Table 7 lists the addresses of registers that allow access to the above func tions The register at address 800000h controls GPIO Output Control and LED Anode register functions The register at address 800001h controls the register functions for the LED cathode modem reset and user triggers Address 800002h contains GPIO data Table 7 LED and Port Emulation Addresses Address Register Function Access 800000h LED Anode GPIO Port output control WR 800001h LED Cathode Modem Trig WR 800002h GPIO Data RD WR GPIO Emulation GPIO is emulated with the use of the GPIO Output Control Register and the GPIO Data Register Table 8 lists the multiple functions of the register Table 8 LED Anode GPIO Output Control Register Bit Function 7 6 5 4 3 2 1 0 Anode Col 1 X Anode Col 2 X Anode Col 3 X Anode Col 4 X Anode Col 5 X Anode Col 6 X Anode Col 6 X GPIO Output X UM014210 1003 PRELIMINARY eZ80 Development Platform
12. MISO 47 48 BUSREQ MATA 15 Pc6_DGD1 gt 4 42 PBE TS O 49 50 MATS 17 Pcs_DSRK PBA T O Header 25x2 PC4_DTR1Y PB3 SCK Rt dn R2 a PBi Tij PB7_MOSI PB6_MISO Pc1_RxD PB1_T11 1 2 PBATIO PCO_TXD1 gt PBO_TO ypp PBI SCK 3 4 PBZ SS VDD PBI TI 5 6 PBO TOT GND 7 8 T RIT pcs DeD 9 10 Pcs DSRT PCA_DTRT a PC3_CTST MA16 2 PC2_RTS1 13 14 MATT 4 FGO TXDT 15 46 PD7 RIO MATS 6 71 17 18 GND MA19 8 VDD GND PDS DSRO 19 20 PD4 DTRO 11 PD3 CTS0 21 2 PD2_RTSO MA21 13 PD1 RXDO 23 2 PDO TXDO MA22 15 TDO 25 28 TDI MA23 17 aT 2 TRIGOUT GND i 1 GND TCK i TM 1 ED 1314 M VDD Rye VoD as 34 M PHE eno 19120 GND A10 ATT L GND Ai2 15 16 A13 DA 35 36 Ait HERB A15 R3 FLASHWE 37 38 GND 19 20 GND 10k M_C53 39 40 DIS_IRDA A16 2 24 AIT RESET 5 B gt MWAIT A18 A19 A20 25 28 A21 HALT SIP 45 46 NWI A22 27 28 A23 DD 47 48 VDD 29 30 DD 49 50 31 3 Ry ag M WR Header 25x2 Rig ESE 35 36 INSTRD von BUSACK 37 38 PHI 3 BUSREO wW aw HEADER NMI TRD 39 40 GND PHI DO 4t X2 D1 10K D2 A 4 D3 Da 45 46 D5 D 47 48 D7 ZDI GND 4e so GND a 51 52 a INTERFACE CS0 53 54 CS1 E 55 56 e B ER TA MEMRO YD 57 58 ORQ GND 59 60 Header 30x2 Header 3x2 UD VDD E NN USA Tok DCD la a reser n 2 1 1 4 2 VDD TC74LVC08 RX D2 U8A LODS 2 GND P1 GND R5 TDI pa DTR 1K TDO 1 2 i 55 2 TC74LVT125 TCK 3 4 GND 5 6 TX ET TVCC_RESETn 7 8 T s La 4 2 HEADER 9 HEADER 32 a 19 PRSTA MODEM CONNECTOR
13. 110 eZ80F91 Module Memory Wk kK KK KK KK KK KK KK KK 50 Reset Generator X sk al a al Eek n a LP edere 51 IrDA Transceiver 2er seras prada Danana d des 51 Flash Loader Utility kk kK KK KK KK KK KK KK KK KK KK KK KK KK 53 Mounting the Module k KK KK KK KK KK KK KK KK KK KK KK KK k 53 Changing the Power Supply Plug KK KK KK KK KK KK 54 Agde ai rr 56 ZDI Target Interface Module KK KK KK K KK RR KK KK ee 56 JTAG icd suben enbevex4 r ml mm 56 Application Modules 0 0 KK KK KK KK KK KK KK KK KK ene 56 ZDS TL i cu heh nak he Hek bee bd dank la SER eed Ee Gul des 57 RN 57 Troubleshootifig i san cio dia a e LAE ee Rea ay 59 OVVIE W ia ae a 59 Cannot Download Code WAW KK KK KK KK KK KK KK KK KK KK KK KK kk 59 IrDA Port Not Working 0 0 0 0 kK KK KK KK KK KK KK KK KK K 59 Contacting ZiLOG Customer Support Xa K K KKR KK KK 59 Schematic Diagrams 61 eZ80 Development Platform 0 0 00 e KK KK 61 eZS0F91 Module ss eae ae ea AGA Tee a k d Wa 66 Appendix Avi sin walk kan kelk a ka ee W k Ee ED ea ae ee 69 General Array Logic Equations 0 0 00 e KK KK KK KK 69 U10 Address Decoder 0 0 0 KK KK KK KK KK KK KK KK KK IK 69 U15 Address Decoder 4 5y Jc KL AWE rr eR eme 72 Customer Feedback Form Wak kk kK kk KK KK KK KK KK KK KK KK KK KK TI Table of Contents PRELIMINARY UMO14210 1003 eZ
14. AS7C34096 GND usc TC74LVCOB 1 ji 8 ji 10 e U9B z TC74LVC08 4a 4 5 y U9D z TC74LVC08 42 Lo an m Figure 20 ez80 Development Platform Schematic Diagram 3 of 5 PRELIMINARY 0 eZ80F91 Development Kit User Manual TiLog D 7 0 A 23 0 U20 7 Do Dora DT p2 H1 D2 D3 12 D3 Da 28 pa ps 26 D5 D6 29 D6 p 30 D7 VDD vppo 3 4 vpp1 221 MEM_CEN4 c12 OE vsso 12 S401 vss1 281 AS7C34096 Schematic Diagrams 63 VDD C13 0 1uF U22 2 Lr _ ly YM Z M y C14 Cie 8 V 24 p 3 i c1 v 1 0 1 cz c16 c17 2 35 O1uF O tuF L9 TXDO_ PDO TXD09 tn T1OUT GND 13 raN T20ur H0 PD2 RTSQ Tai Taour LL RTSO CON DIS gt 22 FORCEOFF VDD RIA A 23 FORCEON INVALID 21 10K 20 R20UTB 12 R our rn H4 18_ ReouT R2IN 3 OND PD3 CTS0 177 R30uT Rain 3 C130 PD1 RXDO 16 R4oUT Rain L 8RXDO L8 157 RsouT RSIN a o MAXSZASCAI c21 VDD 0 1 U24 cog Hcr g v 24 z cas ol en v 1 14 c2 tra ak c2 PC0_TXDI gt 2 4 4 TiN T1OUT PCA4 DTRT Y T2IN T20UT E PC2 RTST 2 T3IN Taour 11 RTS VED MOD_DIS Dj 22 FORCEOFF y FORCEON INVALID Z1 RMB 20
15. CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power con sumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deacti vated via software in the eZ80F91 s Peripheral Power Down Register UM014210 1003 PRELIMINARY eZ80 Development Platform 16 eZ80F91 Development Kit User Manual Z Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP11 Continued Pin Symbol Signal Direction Active Level eZ80F91 Signal 46 RD Bidirectional Low Yes 47 WR Bidirectional Low Yes 48 INSTRD Input Low Yes 49 BUSACK Input Pull Up 10KO Low Yes 50 BUSREQ Output Pull Up 10KO Low Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F91 device 3 Additional note external capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power con sumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deacti vated via software in the eZ80F91 s Peripheral Power Down Register Operational Description P
16. Development Kit User Manual 72 z wire nDIS FL nFL DIS nEXP_EN nFL_DIS Ej wire nDIS FL nFL DIS nEXP is 0 Flash is disabled N if either of them assign nCS EX nEX FL DIS nEXP EN nEX FL DIS jw ll assign nL RI nmemen1 0 nmemen2 0 nmemen3 0 nmemen4 0 nEM_EN 0 nCS EX 0 assign nmemen4 nCS2 0 amp A7 A6 A5 A4 A3 5 h17 assign nmemen3 nCS2 0 amp A7 A6 A5 A4 A3 5 h16 assign nmemen2 nCS2 0 amp A7 A6 A5 A4 A3 5 h15 assign nmemenl nCS2 0 amp A7 A6 A5 A4 A3 5 h14 assign nEM EN nCS2 0 A7 A6 A5 A4 A3 A2 A1 A0 8 h80 endmodule U15 Address Decoder def ine anode 8 h00 def ine cathode 8 h01 define latch 8 h02 FOR eZ80 Development Platform Rev B This PAL generates signals that control Expansion Module access LED and Port A emulation This device is a GAL22LV10 5JC 5ns tpd or equivalent with Package 28 pin PLCC General Array Logic Equations PRELIMINARY UMO14210 1003 module F92_em_pal input UMO14210 1003 nDIS_EM nEM EN A0 AT A2 A3 M AS A6 A7 AO Al A2 A3 A4 synt synt synt synt synt synt synt hesis hesis hesis hesis hesis hesis
17. If either bit is O the corresponding Trig and Trig2 signals are driven Low Embedded Modem Socket Interface The eZ80 Development Platform features a socket for an optional 56K modem a modem is not included in the kit Connectors J1 J5 and J9 provide connection capability The modem socket interface provided by these three connectors is shown in Figure 9 Tables 10 through 12 identify the pins for each connector The embedded modem utilizes UART1 which is available via the Port C pins UM014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual 28 Diog Figure 9 Embedded Modem Socket Interface J1 J5 and J9 Table 10 Connector J5 Pin Symbol Description 1 M TIP Telephone Line Interface TIP 2 M RING Telephone Line Interface RING Table 11 Connector J9 Pin Symbol Description 1 MRESET Reset active Low 50 100 ms Closure to GND for reset 3 GND Ground Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 29 Table 11 Connector J9 6 D1 DCD indicator can drive an LED anode without additional circuitry 7 D2 RxD indicator can drive an LED anode without additional circuitry 8 D3 DTR indicator can drive an LED anode without additional circuitry 9 D4 TxD indicator can drive an LED anode without additional circuitry Table 12 Connector J1 Pin Symbol Description 2
18. PRELIMINARY eZ80F91 Module eZ80F91 Development Kit User Manual 50 110 Operational Description The purpose of the eZ80F91 Module as a feature of the eZ80F91 Devel opment Kit is to provide the application developer with a plug in tool to evaluate such features of the eZ80F91 device as on chip EMAC SRAM Flash etc eZ80F91 Module Memory Static RAM The eZ80F91 Module features 512 KB of fast SRAM Access speed is typically 12ns allowing zero wait state operation at 50 MHz With the CPU at 50MHz SRAM can be accessed with zero wait states in eZ80 mode CS1_CTL CS1 can be set to 08h no wait states Flash Memory The eZ80F91 Module features 256 KB of on chip Flash memory which can be programmed a single byte at a time or in bursts of up to 128 bytes Write operations can be performed using either memory or I O instruc tions Erasing bytes in Flash memory returns them to a value of FFh Both the MASS ERASE and PAGE ERASE operations are self timed by the Flash controller leaving the CPU free to execute other operations in par allel Upon power up the on chip Flash memory is located in the address range 000000h 03FFFFh Four wait states are programmed in Flash control register F8h On chip Flash memory is prioritized over all external Chip Selects can be enabled or disabled power on enabled and can be programmed within any 256KB address space in the 16MB address range The eZ80F91 Module features the following me
19. RESET BESET o o o UIE GND FLAsHWE gt ELASHWE 11 wP 74LCX04 TSS0P14 Figure 25 eZ80F91 Module Schematic Diagram 3 of 3 Module Memory PRELIMINARY eZ80F91 Development Kit User Manual TiLog Schematic Diagrams 68 Appendix A eZ80F91 Development Kit User Manual 110 69 General Array Logic Equations This appendix shows the equations for disabling the Ethernet signals pro vided by the U10 and U15 General Array Logic GAL devices U10 Address Decoder l de ineidle2 D00 l definestatel2 b01 l definestate22 b11 de inestate32 b10 FOR eZ80 Development Platform Rev B This PAL generates 4 memory chip selects module f92 decod nCS EX Enables Extension Module s Memory when Low nFL DIS When Low Module Flash is disabled nDIS FI 0 When High nDIS FL depends upon state of nmemenX neso Al A23 A6 A22 A5 A21 A4 A20 A3 A19 A2 A18 Al A17 AO A16 UMO14210 1003 PRELIMINARY Appendix A eZ80F91 Development Kit User Manual Likog nCS2 nEX_FL_DIS nEM_EN nDIS FL nL RD nmemenl nmemen2 nmemen3 nmemen4 input nFL DIS nCS0 nCS2 A7 A6 A5 A4 A3 A2 A1 AO nEX_FL_DIS General Array Logic Equations disables Flash on the expansion module when Low enables Development Platform LED and Port A emulation circuit disables Module Flash when Low enables lo
20. The eZ80F91 Development Kit allows off chip Flash memories between 1MB and 4MB This Flash memory is entirely located on the eZ80F91 Module as footprint only as shipped from the factory external Flash is not installed Memory Map A memory map of the eZ80 Development Platform and the eZ80F91 Module is illustrated in Figure 10 Flash memory and SRAM on the eZ80F91 Module are addressed when CSO and CS1 are active Low SRAM on the eZ80 Development Platform is addressed when CS2 is active Low Please refer to the eZ80F91 Product Specification PS0192 for more details about controlling on chip Flash memory and SRAM UMO14210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual Z 32 110 On chip FFFFFFh SRAM FFE000h Available Address Space DFFFFFh SRAM Memory up to 2 MB CS1 Platform Expansion SRAM Memory up to 4 MB CS2 80FFFFh 800000h 7FFFFFh Off module Expansion Module Flash memory Flash Memory up to 4 MB 400000h 3FFFFFh Expansion Module Flash Memory up to 4 MB CSO 8 MB Off chip 120000h Flash memory on the module 11FFFFh Up to 4 MB Flash Memory 040000h On chip O3FFFFh Flash memory 000000h Figure 10 Memory Map of the eZ80 Development Platform and eZ80F91 Module Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Z 110 Chip Selects and Wait States As seen in the memory map in Figure 10 Flash memor
21. UMO14210 1003 eZ80F91 Development Kit User Manual Tiig Physical Dimensions The dimensions of the eZ80 Development Platform PCB is 177 8mm x182 9mm The overall height is 38 1 mm See Figure 5 lt 175 3 mm gt lt 43 2 mm gt lt 114 3 mm gt 2 epno nnpunj PI 8 o o SN else Sa e o Jo ol o o o 9 oo 3 2 o OWN o ofa o 0 0 3 3v CONS VOLT SELECT lo o E K R Ji x SIE S loo o ol IEXANT SOCKETMODEM Ra SF56D SP bs o o lo ofp J9 000000000 RI d y RA o o o ol c lo ol Ajo o o ol o oj 157 5 mm o oja o o o ol ag AM loo 167 6 mm GND o ol C20 A16 o ol OO aie o ol UD A20 o ol O C29 A22 o ol vo o
22. eZ80F91 device 3 Additional note external capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power con sumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deacti vated via software in the eZ80F91 s Peripheral Power Down Register UM014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual 14 z Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP11 Continued Pin Symbol Signal Direction Active Level eZ80F91 Signal 16 GND 17 A2 Bidirectional Yes 18 A1 Bidirectional Yes 19 A11 Bidirectional Yes 20 A12 Bidirectional Yes 21 A4 Bidirectional Yes 22 A20 Bidirectional Yes 23 A5 Bidirectional Yes 24 A17 Bidirectional Yes 25 DIS_ETH Output Low No 26 EN_Flash Output Low No 27 A21 Bidirectional Yes 28 Vpp 29 A22 Bidirectional Yes 30 A23 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F91 device 3 Additional note external capacitive loads on RD WR IORQ MREQ D
23. encoder decoder block Bit 1 if it is set enables received data to pass into the UARTO Receive FIFO data buffer Bit 2 is a test function that provides a loopback sequence from the TxD pin to the RxD input Bit 1 the Receive Enable bit is used to block data from filling up the Receive FIFO when the eZ80F91 Module is transmitting data Because IrDA signal passes through the air as its transmission medium transmit ted data can also be received This Receive Enable bit prevents this data from being received After the eZ80F91 Module completes transmitting this bit is changed to allow for incoming messages Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 53 The code that follows provides an example of how this function is enabled on the eZ80F91 Module Init_IRDA Make sure to first set PD2 as a port bit an output and set it Low PD ALT1 amp OxFC PDO uart0tx PD1 uart0_rx PD_ALT2 0x03 Enable alternate function UART_LCTLO 0x80 Select dlab to access baud rate generator BRG_DLRLO 0x2F Baud rate Masterclock 16 baudrate BRG DLRH0 0x00 High byte of baud rate UART LCTL020x00 Disable dlab UART_FCTLO 0xC7 Clear tx fifo enable fifo UART_LCTLO 0x03 8bit N 1 stop IR_CTL 0x03 enable IRDA Encode decode and Receiv enable bit IRDA Xmit IR CTL 0x01 Disable receive Put
24. functions of the eZ80F91 Module These five input signals are e Enable Flash EN_Flash Flash Write Enable FlashWE e Disable IrDA DIS IrDA F9 WE e RIC Vpp A description of these five signals follows 1 These input signals are only used if external Flash memory is present on the eZ80F91 Module As shipped from the factory external Flash is not installed Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual AP 110 Enable Flash When active Low the EN_Flash input signal enables the Flash chip on the eZ80F91 Module Flash Write Enable When active Low the FlashWE input signal enables write operations on the Flash boot block of the eZ80F91 Module Disable IrDA When the DIS_IrDA input signal is pulled Low the IrDA transceiver located on the eZ80F91 Module is disabled As a result UARTO can be used with the RS232 or the RS485 interfaces on the eZ80 Development Platform F91_WE When the F91_WE signal is active Low internal Flash on the eZ80F91 Module is enabled for writing This signal is inverted from the WP signal of on the eZ80F91 Module RTC Vpp RT C_Vpp is a test point for the Real Time Clock power sup ply UM014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual Z 12 110 Peripheral Bus Connector Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the 50 pin header located at position JP
25. is used for power savings To enable the IrDA trans ceiver DIS_IRDA is left floating and PD2 is pulled Low The RxD and TxD signals on the transceiver perform the same functions as a standard RS232 port However these signals are processed as IrDA 3 16 coding pulses sometimes called IrDA encoder decoder pulses When the IrDA function is enabled the final output to the RxD and TxD pins are routed through the 3 16 pulse generator Another signal that is used in the eZ80F91 Module s IrDA system is Shut_Down SD The SD pin is connected to PD2 on the eZ80F91 Mod UMO14210 1003 PRELIMINARY eZ80F91 Module 52 eZ80F91 Development Kit User Manual Diog ule The IrDA control software on the user s wireless device must enable this pin to wake the IrDA transceiver The SD pin must be set Low to enable the IrDA transceiver On the eZ80F91 Module a two input OR gate is used to allow an external pin to shut down the IrDA transceiver Both pins must be set Low to enable this function Figure 15 highlights the eZ80F91 Module IrDA hardware connections External Disable ezsorg1 PP2 IR_SD Device PD1 RxD PDO TxD Figure 15 IrDA Hardware Connections The eZ80F91 Module features an Infrared Encoder Decoder register that configures the IrDA function This register is located at address 0BFh in the internal I O register map The Infrared Encoder Decoder register contains three control bits Bit 0 enables or disables the IrDA
26. problem report please follow these simple steps If a hardware failure is suspected con tact a local ZiLOG representative for assistance Cannot Download Code If you are unable to download code to RAM using ZDS make sure to press and release the Reset button on the eZ80 Development Platform prior to selecting Build gt Debug gt Reset Go in ZDS IrDA Port Not Working If you plan on using the IrDA transceiver on the eZ80F91 Module make sure the hardware is set up as follows Jumper J2 must be OFF to enable the control gate that drives the IrDA device e Set port pin PD2 Low When this port pin and Jumper J2 are turned OFF the IrDA device is enabled e Install a jumper on connector J6 across pin names con dis and GND to disable the console serial port driver Contacting ZiLOG Customer Support For additional troubleshooting solutions see ZDS II Online Help For valuable information about hardware and software development tools visit ZiLOG Customer Support online Download the latest released ver sion of ZiLOG Developer Studio UMO14210 1003 PRELIMINARY Troubleshooting eZ80F91 Development Kit User Manual 60 Tito Get the latest software updates from ZiLOG as soon as they are available Contacting ZiLOG Customer Support PRELIMINARY UMO14210 1003 Schematic Diagrams eZ80 Development Platform Figures 18 through 22 diagram the layout of the eZ80 Development Platform
27. 0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power con sumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deacti vated via software in the eZ80F91 s Peripheral Power Down Register Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 15 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP11 Continued 1 Pin A Symbol Signal Direction Active Level eZ80F91 Signal 31 CSO Input Low Yes 32 CS1 Input Low Yes 33 CS2 Input Low Yes 34 DO Bidirectional Yes 35 D1 Bidirectional Yes 36 D2 Bidirectional No 37 D3 Bidirectional Yes 38 D4 Bidirectional Yes 39 D5 Bidirectional Yes 40 GND 41 D7 Bidirectional Yes 42 D6 Bidirectional Yes 43 MREQ Bidirectional Low Yes 44 IORQ Bidirectional Low Yes 45 GND Notes For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 68 The Power and Ground nets are connected directly to the eZ80F91 device Additional note external capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80
28. 1 on the eZ80 Development Plat form Table 2 identifies the pins and their functions A6 AO A10 x A3 GND EXT gt V3 3 EXT A8 Ea E AT A13 E A9 A15 i E A14 A18 E E A16 A19 A E GND_EXT A2 x E A1 A11 E E A12 A4 E A20 A5 si x A17 DIS ETH zi E DIS FLASH A21 x V3 3 EXT A22 E E A23 CS0 A E CS1 CS2 a E DO D1 m x D2 D3 5 D4 D5 a GND EXT D7 E D6 MREQ E E JOREO GND_EXT A x RD WR a E INSTRD BUSACK a gt BUSREQ HEADER 25X2 IDC50 Figure 6 eZ80 Development Platform Peripheral Bus Connector Pin Configuration JP1 Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual mia 13 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Pin Symbol Signal Direction Active Level eZ80F91 Signal 1 A6 Bidirectional Yes 2 AO Bidirectional Yes 3 A10 Bidirectional Yes 4 A3 Bidirectional Yes 5 GND 6 Vpp 7 A8 Bidirectional Yes 8 AT Bidirectional Yes 9 A13 Bidirectional Yes 10 A9 Bidirectional Yes 11 A15 Bidirectional Yes 12 A14 Bidirectional Yes 13 A18 Bidirectional Yes 14 A16 Bidirectional Yes 15 A19 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the
29. 12 PD6 29 Q GND Ad A20 PD5 PD4 PA 0 7 C mina mmm A r rad BS ml MMA 0204 abled 5 DIS FLASH PD1 6 PDO Pal A21 8 V TDO g TDI lt gt Ie A22 9 40 A23 GND 9 40 TRIGOUT POD CS0 41 42 CS1 TCK 41 42 TMS IRDA SD PD 0 7 lt gt CS2 4 44 DO RTC VD 44 EZBOCLK s vcc D1 4 4g D2 IICSCL 4 46 PD1 RESET RESET 9 D3 4 48 D4 IICSDA 4 4s GND D5 49 Q CND FLASHWug RD RD D7 D6 E DIS IRDA WR FR WR MREQ 4 JOREQ RESET 4 WAIT GND 6 RD VCC 6 GND IOREQ IOREQ R6 WR 8 INSTRD HALT SIP 8 NMI MREQ 22K BUSACK 59 60 BUSREQ V 60 MREQ INSTRD INSTRD c3 C WAIT waT lt C Hat stp gt HALT SIP HEADER 30x2 SM HEADER 30x2 SM BusREQ C JEUSE BUSACK gt NM KOM vcc U1B R20 TDO TRIGOUT TRIGOUT 10K S 74LCX04 74LCX32 TSSOP14 TSSOP14 TRSTN U1F R9 vec 4 7K o vec 74LCX04 74LCX32 TSSOP14 TSSOP14 GND GND vo D DIS IRDA DISABLE IRDA c2 RESET IRDA SD 0 1pF open drain PD2 IR SD 74LCX04 TSSOP14 74LCX32 MAX6328UR29 E TSSOP14 SOT 23 L3 0 01pF alternative vcc Maxim MAX6802UR29D3 vo Memory vec GND Ep GND Figure 23 eZ80F91 Module Schematic Diagram 1 of 3 Connectors and Miscellaneous UM014210 1003 PRELIMINARY Schematic Diagrams D o7 N55 344 WAIT wAT BUSREQ BUSREQ MI NMI e TMS TCK Tol gt TRSIN RESET gt gt 9 we gt RESET C6 GND 0 056pF R26 c5 499 220pF F91 WP U5 DO D1 D2 D4 D5 D6 D7 d WAIT d BUSREQ 2q NMI
30. 18 J11 EN_FLASH Off Chip Shunt Status Function Affected Device IN All access to external Flash memory on the External Flash memory on the eZ80190 Module is enabled eZ80190 Module OUT All access to external Flash memory on the External Flash memory on the eZ80190 Module is disabled eZ80190 Module Note As shipped from the factory external Flash memory is not installed UM014210 1003 PRELIMINARY eZ80 Development Platform 38 eZ80F91 Development Kit User Manual Diog Jumper J12 The J12 jumper connection controls the selection of a 5 V or 3 VDC power supply to the embedded modem if an embedded modem is used See Table 19 Table 19 J12 5VDC 3 3VDC for an Embedded Modem Shunt Status Function Affected Device 1 2 5VDC is provided to power the embedded modem Embedded modem 2 3 3 3VDC is provided to power the embedded modem Embedded modem Jumper J14 The J14 jumper connection controls the polarity of the Ring Indicator See Table 20 Table 20 J14 RI Shunt Status Function Affected Device 1 2 The Ring Indicator for UART1 is inverted UART1 2 3 The Ring Indicator for UART1 is not inverted UART1 Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Zi 110 Jumper J15 The J15 jumper connection controls the selection RS485 circuit along with UARTO When the shunt is placed the RS485 circuit is enabled See Table 21 RS485 functionality will be available
31. 6 RTS1_7 mora e RT_2 CIST 8 1 I o BIR to 2 Yosa slo o J MODEM RS485 2 EN DB9 Male Figure 21 ez80 Development Platform Schematic Diagram 4 of 5 PRELIMINARY Schematic Diagrams eZ80F91 Development Kit User Manual zi L pg nm 65 MATES WITH AMP 749268 1 P1 LENGTH 5 WIRES 28 AWG Figure 22 eZ80 Development Platform Schematic Diagram 5 of 5 RS 485 Cable UMO14210 1003 PRELIMINARY Schematic Diagrams eZ80F91 Development Kit User Manual eZ80F91 Module f Figures 23 through 25 diagram the layout of the eZ80F91 Module Ethernet circuiting devices are not loaded on the z ras 66 eZ80F91 Module However these devices appear in the following schematics for reference purposes VCCVCC o 0 A O 23 DO az nde D 0 7 lt O an ze Ri CS 0 3 miii e 47 connector 1 connector 2 id R2 4 7K JP1 JP2 F91_WP r E PA7__ PA6 74LCX04 lCSDA lt T gt ICSDA ZI 4 PA R37 TSSOP14 awcscL PS ECS TRSTN 6 6 y 10K F91 WE 8 PA g PAD CLK OUT EZ80CLK 9 2 v V 9 Q GND CLK OUT AG A0 PB7 PB6 vec DIS FLASH p ATO 14 A3 PBS 4 PB4 0 DIS FLASH ib amp VOC PBS 8 PB2 2b A8 8A7 PB1 8 PBO c1 A 9 Q A9 GND 19 0 PC7 A 21 A14 PC6 PCS li ELASHWE WR EN A8 4 A16 PC4 4 PC3 R4 FLASHWE lt I T ATS GND PEZ a PCI 390nF RTC VDD AZ 8 A PCO 8 PD7 2R7 rro_voD A 9 Q A
32. 80F91 Development Kit User Manual List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 UMO014210 1003 110 eZ80 Development Platform Block Diagram with eZ80F91 Mod l iy A ede a k A tka ean Da eign 4 The eZ809 Development Platform 5 The eZ80F91 Module KK KK KK KK KK KK KK eee 6 Basic eZ80 Development Platform Block Diagram 8 Physical Dimensions of the eZ80 Development Platform 9 eZ809 Development Platform Peripheral Bus Connector Pin Configuration JP1 SL KK KK KK KK KK K KK 12 eZ80 Development Platform I O Connector Pin Configuration JP2 0 0 ee eee eee 17 Trigger Pins J21 and J22 0 0 eee eee 27 Embedded Modem Socket Interface J1 J5 and J9 28 Memory Map of the eZ80 Development Platform and eZ80F91 Module sw a eyal eh ah ee eee 32 Possible Bus Contention without Fast Buffer 45 Physical Dimensions of the eZ80F91 Module 47 eZ80F91 Module Top Layer SK KK 48 eZ80F91 Module Bottom Layer 49 IrDA Hardware Connections 0 004 52 9VDC Universal Power Supply Components 54 Inserting a New Plug Configuration 55 eZ80 Development Platform Schematic Diagram HL OLD sia en
33. 8358 INTR ge99 TECH_SEL2 Gyre TECH SEL1 2 TECH SELO ANEGA IBREF RPTR LEDSPDO LEDBTA FXSEL LECOL SCRAMEN LEDRX LEDSEL LEDTX LEDBTB LEDLNK LED 10LNK LESPD1 LEDTXA CLK25EN LEDDPX LEDTXB TEST3_SDI TEST2 TEST1_FXR TESTO_FXR FXT FXT XTL XTL TX TX RX RX REFGND TGND2 eZ80F91 Development Kit User Manual 67 TiLog El I R25 10K C4 18pF v1 25MHz C7 4gpy HFJT1 2450E L11 LEDLNK n vec G31 c C43 0 001uF 0 001uF 0 001uF 80 PD7 PC 0 7 GND PDE B PD rr PAS c8 C19 C30 E P 0 1jF 0 1uF O 1uF 0 1jF 0 1jiF O 1pF 0 1jF 0 1uF O 1pF O 1pF O 1uF O 1uF 0 1jF PD PD vcc PDO lt gt PD 0 7 po lt __ HALT_SLP vec lt C CLK_OUT vec o vec Pan NERD e ro GND Les TRIGouT LL jew Figure 24 eZ80F91 Module Schematic Diagram 2 of 3 CPU and PHY PRELIMINARY Schematic Diagrams UM014210 1003 w gt vec c13 0 001pF 512kx8 SRAM SOJ36 400 D 0 7 0 23 DFLASHO DFLASHI DFLASHZ 6 28 DFLASHS gt gt gt DFLASHA DFLASHS vec 4 DFLASHG 6 DFLASHT 9 0 G14 0 001pF CSFLASH TACBTLV3384 5024 300 ovcc Flash 1Mx8 3 3V TSOP40 20MM MT28F008B3VG u1D CSFLASH pis FLASH DIS FLASH FLASH EN TALCX32 RD gt o 74LCX04 TSSOP14 TSSOP14 an Cpm __ vec vec cso gt vec
34. Controller EMAC Ethernet port IrDA port Real Time Clock with battery backup Two headers compatible with the eZ80 Development Platform e ZPAKII Debug Tool e eZ80 Software and Documentation CD ROM Hardware Specifications Table 1 lists the specifications of the eZ80 Development Platform Table 1 eZ80 Development Platform Hardware Specifications Operating Temperature 20 C 5 C Operating Voltage 9 VDC Kit Features PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 eZ80F91 Development Kit Overview The purpose of the eZ80F91 Development Kit is to provide the developer with a set of tools for evaluating the features of the eZ80F91 microcon troller and to be able to develop a new application before building appli cation hardware The eZ80 Development Platform is designed to accept a number of application specific modules and eZ80 based add on modules including the eZ80F91 Module featured in this kit The eZ80 Development Platform together with its plugged in eZ80F91 Module can operate in stand alone mode with Flash memory or interface via the ZPAKII Debug Tool to a host PC running ZiLOG Developer Stu dio II Integrated Development Environment ZDS IDE software The address bus data bus and all eZ80F91 Module control signals are buffered on the eZ80 Development Platform to provide sufficient drive capability A block diagram of the eZ80 Development Platform and t
35. L SRAM and Bus Contention further explains this bus contention issue Functional Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Zi Digg Physical Dimensions The footprint of the eZ80F91 Module PCB is 63 5mmx78 7cm With an RJ 45 Ethernet connector the overall height is 25mm See Figure 12 gt r 56 0 mm eZ80F91 MODULE A R15 2 R23 R16 R24 vu ZiLOG PCA 99C0879 001 COPYRIGHT ZiLOG XTOOLS 2002 00000000000000000000000000000lo Jet AOILEANN H VL1 o o o o WITHTHE oo oo ees O O O O O O O O O O O O O O O O O O O O O O O O Q O O O O OOOOOOOOO0O0OO0O0OOOOOOOOOOOOO0O0O000 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O o e 78 7 mm Zj gk go E d e Zp e A o o lo 0 Po amp w o o _Fb N o p o YU OOO 96 9 ES j oo e o o C226 995 o Ya R37 c 2 Ll OO 1 ey UI mo mp e re TP i U Ip o ca2 di Tp m JU mo dT TI y Y 63 5 mm Figure 12 Physical Dimensions of the eZ80F91 Module UMO14210 1003 PRELIMINARY eZ80F91 Module 48 eZ80F91 Development Kit User Manual Z 110 Figure 13 illustrates the
36. MOD_DIS Modem disable active Low 4 Vec 5 VDC or 3 3 VDC input 24 GND Ground 25 PC4_DTR1 DTR interface TTL levels 26 PC6_DCD1 DCD interface TTL levels 27 PC3_CTS1 CTS interface TTL levels 28 PC5 DSR1 DSR interface TTL levels 29 PC7 RI Ring Indicator interface TTL levels 30 PCO TXD1 TxD interface TTL levels 31 PC1 RXD1 RxD interface TTL levels 32 PC2_RTS1 RTS interface TTL levels Components P4 T1 C3 C4 and U11 provide the phone line interface to the modem On the eZ809 Development Platform LEDs D1 D2 D3 and D4 function as status indicators for this optional modem The phone line connection for the modem is for the United States only Connecting the modem outside of the U S requires modification UM014210 1003 PRELIMINARY eZ80 Development Platform 30 eZ80F91 Development Kit User Manual Diog The tested modem for this eZ80F91 Development Kit is a MultiTech Sys tems formerly Conexant socket modem part number SC56H1 Either the 3 3 V or the 5 0 V version of the modem can be used However jumper J12 should be configured accordingly see Table 19 Information about this modem and its interface is available in the SocketModem data sheet from www multitech com eZ80 Development Platform Memory Memory space on the eZ80 Development Platform consists of onboard SRAM and additional SRAM footprints Onboard SRAM The eZ80 Development Platform features 512KB SRAM at U20 This SRAM provides the bas
37. No licenses are conveyed implicitly or otherwise by this document under any intellectual property rights PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Z iaga HI Safeguards The following precautions must be observed when working with the devices described in this document Z N Caution Always use a grounding strap to prevent damage resulting from electrostatic discharge ESD UMO14210 1003 PRELIMINARY Safeguards eZ80F91 Development Kit User Manual IV 110 PRELIMINARY UMO14210 1003 eZ80F91 Development Kit Table of Contents Safeguards List of Figures List of Tables Introduction Kit Features Hardware Specifications eZ80F91 Development Kit Overview eZ80 Development Platform Functional Description Physical Dimensions Operational Description eZ80F91 Module Interface Application Module Interface VO Functionality sees Embedded Modem Socket Interface UMO14210 1003 ez80 Development Platform Memory J mpets ese mm lm rb mm ConfiectOfS cce e ey ere e e ee es Consol serv yu k e a y k dhok j Modem c n ee al ar ala ed aes PC Devices eZ80F91 Module Functional Description Fast Buiter 4 gt 6 s et su res Physical Dimensions Operational Description PRELIMINARY User Manual Table of Contents eZ80F91 Development Kit User Manual v
38. RELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Ar 110 1 O Connector Figure 7 illustrates the pin layout of the I O Connector in the 50 pin header located at position JP2 on the eZ80 Development Platform Table 3 identifies the pins and their functions PB7 PB6 O O PA D bB2 PB1 ja H PBO GND EXT P PC7 PC6 E PC5 PC4 z PC3 PC2 9 P PC PCO m E PD7 PD6 e P GND EXT PD5 B PD4 PD3 J P PD2 PD1 P PDO TO 9 P TDI e D GND EXT z gt TRIGOUT TCK TMS RTC VDD Y E EZ80CLK IICSCL 9 P IICSDA 5 5 enD ExT FLASHWE j AI 233 DIS_IRDA e Oo _ _ VERE 3 E END EXT HALTSLP c x NMI V33 D O P HEADER 25X2 IDC50 Figure 7 eZ80 Development Platform I O Connector Pin Configuration JP2 UM014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual 18 ies Table 3 eZ80 Development Platform I O Connector Identification JP2 Pin Symbol Signal Direction Active Level eZ80F91 Signal 1 PB7 Bidirectional Yes 2 PB6 Bidirectional Yes 3 PB5 Bidirectional Yes 4 PB4 Bidirectional Yes 5 PB3 Bidirectional Yes 6 PB2 Bidirectional Yes 7 PB1 Bidirectional Yes 8 PBO Bidirectional Yes 9 GND 10 PC7 Bidirectional Yes 11 PC6 Bidirectional Yes 12 PC5 Bidirectional Yes 13 PC4 Bidirectional Yes 14 PC3 Bidirectional Yes 15 PC2 Bidirectional Yes 16 PC1 Bidirectional Yes 17 PCO Bidirectional Yes 18 PD7 Bidirectional
39. S TRIGOUT 13 44 con 7x2 UM014210 1003 eZ80F91 Development Kit User Manual 61 TiLog u2 o 11 sm LA SDA Sv A ay a VDD SCL asp E 1 GND Hi a WP NC AT24C128 tion lt K DIS_IRDA GND HEADER 2 J7 FLASHWE 2 END U21 HEADER 2 mcso 2 23 Moi RM Y CS0 MORO A3 Y3 CS2 a YA DAS IORQ WR A5 YS MEMRQ maHa ve H WR mes RAT Yr HZ Ro mpa as Ya H __ csa MPH 10 y 10 a9 ve 13 35 PHI Qs vo lor 24 VDD SET vec Ly YOO Sw 43 GEz cno 12M cn 74LVC827 80 OAAuF vec d4 VDD g 2 q 3 Header 3 u7 MDZ 4 A2 MD3 ma 3 Mb5 54 MD6 AS wb o AT M RD 1 DIR L_RD gt 29 o TAL CRAG RO Sn 0 1uF gt gt MDI7 0 MDO vec Yee a vDD VDD 2 GND H 7 Figure 18 ez80 Development Platform Schematic Diagram 1 of 5 PRELIMINARY Schematic Diagrams eZ80F91 Development Kit User Manual 62
40. Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F91 device Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Table 3 eZ80 Development Platform I O Connector Identification JP2 Continued Pin Symbol Signal Direction Active Level eZ80F91 Signal 19 PD6 Bidirectional 20 GND 21 PD5 Bidirectional Yes 22 PD4 Bidirectional Yes 23 PD3 Bidirectional Yes 24 PD2 Bidirectional Yes 25 PD1 Bidirectional Yes 26 PDO Bidirectional Yes 27 TDO Input Yes 28 TDI ZDA Output Yes 29 GND 30 TRIGOUT Input High 31 TCK ZCL Output Yes 32 TMS Output High Yes 33 RTC_Vpp 34 EZ80CLK Input Yes 35 SCL Bidirectional Yes 36 GND Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F91 device UM014210 1003 PRELIMINARY eZ80 Development Platform 20 eZ80F91 Development Kit User Manual 1104 Table 3 eZ80 Development Platform I O Connector Identification JP2 Conti
41. ZDI please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0020 and the eZ80F91 Module Product Specification PS0193 Connector P1 is the JTAG connector on the eZ80 Development Plat form JTAG will be supported in the next offering of eZ80 products Application Modules ZPAKII ZiLOG offers the Thermostat Application module which can be used for evaluating and developing process control and simple I O applications The Thermostat Application module is equipped with an LCD display that can be used to display process control and other physical parameters For additional reading about the Thermostat application please see the Java Thermostat Demo Application Note AN0104 on zilog com PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 57 ZDS II ZiLOG Developer Studio II ZDS II Integrated Development Environ ment is a complete stand alone system that provides a state of the art development environment Based on the Windows Win98SE NT4 0 SP6 Win2000 SP2 WinXP user interfaces ZDS II integrates a language sensitive editor project manager C Compiler assembler linker librarian and source level symbolic debugger that supports the eZ80F91 device UMO14210 1003 PRELIMINARY ZDS Il eZ80F91 Development Kit User Manual 58 Diog PRELIMINARY UM014210 1003 eZ80F91 Development Kit User Manual 110 59 Troubleshooting Overview Before contacting ZiLOG Customer Support to submit a
42. cal data bus to be read by CPU synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis loc loc loc loc loc loc loc loc loc loc loc loc p4 P5 P3 P6 p7 PON P10 P11 P12 P13 P16 panay was 23 input 7 0 A upper part of Address Bus of F92 A23 A7 A22 A6 A21 A5 A20 A4 A19 A3 A18 A2 A17 A1 A16 A0 PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 71 output nCS_EX synthesis loc P17 enables memory on the Expansion Module nmemen1 synthesis loc P18 enables memory on the Development Platform nmemen2 synthesis loc P19 nmemen3 synthesis loc P20 nmemen4 synthesis loc P21 nEM EN synthesis loc P24 enables LED and Port A emulation nDIS FL synthesis loc P25 nL RD synthesis loc P23 wire nCS EX nmemenl nmemen2 nmemen3 nmemen4 wire MOD DIS nmemen1 0 nmemen2 0 nmemen3 0 nmemen4 0 if any of the signals is Low Flash on the Module will be disabled if nDIS FL is High wire nEXP EN nCS0 0 A7 0 A6 1 expansion module Flash enabled if this is 0 UMO14210 1003 PRELIMINARY Appendix A eZ80F91
43. char 0xb0 Output a byte to the uart0 port Flash Loader Utility The Flash Loader utility integrated within ZDS II allows the user a conve nient way to program on chip Flash memory Please refer to the ZiLOG Developer Studio eZ80Acclaim User Manual UMO144 for more details Mounting the Module The eZ80F91 Module features 2 60 pin connectors However the eZ 809 Development Platform contains 50 pin sockets for this module When mounting the eZ80F91 Module onto the eZ80 Development Platform check its orientation to the platform to ensure a correct fit Observe the underside of the module to note that pin 60 of the JP2 connector is removed and that its corresponding socket on the eZ80 Development Platform is plugged UMO14210 1003 PRELIMINARY eZ80F91 Module eZ80F91 Development Kit User Manual 54 Diog Pin 60 of the eZ80F91 Module s JP1 connector must align with the pin 50 socket on the eZ80 Development Platform s JP1 connector pin 60 of the eZ80F91 Module s JP2 connector must align with pin 50 of the eZ80 Development Platform s JP2 socket When the module is mounted cor rectly it will overhang the edge of the eZ80 Development Platform by 10 pins Changing the Power Supply Plug The universal 9VDC power supply offers three different plug configura tions and a tool that aids in removing one plug configuration to insert another as shown in Figure 16 Figure 16 9VDC Universal Power Supply Components T
44. dears cee sien Sank a Epi ee 61 eZ809 Development Platform Schematic Diagram BLOE EC 62 eZ809 Development Platform Schematic Diagram Ard T 63 PRELIMINARY List of Figures vii viii eZ80F91 Development Kit User Manual Diog List of Figures Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 ez80 Development Platform Schematic Diagram Ga dye doy era aww ded aoa 64 eZ80 Development Platform Schematic Diagram 5 of 5 RS 485 Cable SK RR RR KK KK KK 65 eZ80F91 Module Schematic Diagram 1 of 3 Connectors and Miscellaneous KK KK KK KK ee KK KK KK KK 66 eZ80F91 Module Schematic Diagram 2 of 3 CPU and A rrr Dn 67 eZ80F91 Module Schematic Diagram 3 of 3 Module MeM Ory xk 05 40 SUE e FOIE ER eis 68 PRELIMINARY UM014210 1003 eZ80F91 Development Kit User Manual Z List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 UM014210 1003 za eZ80 Development Platform Hardware Specifications 2 eZ80 Development Platform Peripheral Bus Connector Identification JP11 3 AR RR RR RR KK K KK KK 13 eZ80 Development Platform I O Connector Identification JP2 T barton tia 3o Ed Geet bem eid ahaa aaah 18 Jumper eZ80F91 Module
45. eration of ZiLOG s eZ80F91 microcon troller The eZ80F91 is a member of ZiLOG s eZ80Acclaim product family which offers on chip Flash capability The eZ80F91 Development Kit features two primary boards the eZ80 Development Platform and the eZ80F91 Module This arrangement provides a full development plat form when using both boards It can also provide a smaller sized refer ence platform with the eZ80F91 Module as a stand alone development tool Kit Features The key features of the eZ80F91 Development Kit are UMO14210 1003 eZ80 Development Platform Up to 2MB fast SRAM 12ns access time 1 MB factory installed with 512KB on module 512KB on platform Embedded modem socket with a U S telephone line interface PC EEPROM PC configuration register GPIO logic circuit and memory headers Supported by ZiLOG Developer Studio II and the eZ80 C Compiler LEDs including a 7x5 LED matrix Platform configuration jumpers Two RS232 connectors console modem RS485 connector with cable assembly ZiLOG Debug Interface ZDI PRELIMINARY Introduction 2 eZ80F91 Development Kit User Manual Diog JTAG Debug Interface 9VDC power connector Telephone jack eZ80F91 Module eZ80F91 device operating at 50MHz with 256KB of internal Flash memory and 8KB of internal SRAM memory 512KB of off chip SRAM memory 1MB of off chip Flash memory footprint On chip Ethernet Media Access
46. es are configured as outputs Table 14 indicates the multiple register functions of the LED cathode modem and triggers This table shows the bit configuration for each cath ode bit Bits 5 6 and 7 do not carry any significance within the LED matrix These three bits are control bits for the modem reset Trig1 and Trig2 functions respectively Table 14 Bit Access to the LED Cathode Modem and Triggers Bit Function 7 6 5 4 3 2 1 0 Cathode Row 5 X Cathode Row 4 X Cathode Row 3 X Cathode Row 2 X Cathode Row 1 X Modem RST X Trig 1 X Trig 2 X An LED display sample program is shipped with the eZ80F91 Develop ment Kit Please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0020 or to the Tutorial section in the ZiLOG Developer Studio eZ80Acclaim User Manual UMO144 Data Carrier Detect The Data Carrier Detect DCD signal at D1 indicates that a good carrier signal is being received from the remote modem Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual AP 110 RX The RX signal at D2 indicates that data is received from the modem Data Terminal Ready The Data Terminal Ready DTR signal at D3 informs the modem that the PC is ready TX The TX signal at D4 indicates that data is transmitted to the modem Push Buttons The eZ80 Development Platform provides user controls in the form of push buttons These push but
47. g 7 8 CS EX is decoded in the CS2 memory space and is Application module located in the address range B00000h B7FFFFh addressing Jumper J20 The J20 jumper connection controls the selection of the external chip select in the external application module When the shunt is placed the external chip select signal CS_EX is disabled See Table 26 Table 26 J20 EX_FL_DIS Shunt Status Function Affected Device IN The jumper for EX_FL_DIS is IN The chip select on the application module is disabled OUT The jumper for EX_FL_DIS is OUT The chip select on the application module is enabled UM014210 1003 PRELIMINARY eZ80 Development Platform 42 eZ80F91 Development Kit User Manual Diog Connectors A number of connectors are available for connecting external devices such as the ZPAKII Debug Tool PC serial ports external modems the console and LAN telephone lines J6 and J8 are the headers or connectors that provide pin outs to connect any external application module such as ZiLOG s Thermostat Applica tion Module Connector J6 The J6 connector provides pin outs to make use of GPIO functionality Connector J8 The J8 connector provides pin outs to access memory and other control signals Console Connector P2 is the RS232 terminal which can be used for observing the console output P2 can be connected to the PC running HyperTerminal if required Modem Connector P3 provides a terminal fo
48. he eZ80F91 Module is shown in Figure 1 UMO14210 1003 PRELIMINARY Introduction eZ80F91 Development Kit User Manual Z 4 110 A eZ80 Address Bus LIT weu J_I Data Bus Interface Data Bus eZ80F91 RS232 0 Console SRAM C 612KB ES up to 2 MB RS232 1 Modem RS485 0 1 Connect IT TT E ETI ji ma matri Embedded Modem GPIO and Address Decoder Application Module Headers Application Module Headers Headers Econ T External Battery eZ80F91 Module Figure 1 eZ80 Development Platform Block Diagram with eZ80F91 Module eZ80F91 Development Kit Overview PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Figure 2 is a photographic representation of the eZ80 Development Plat form segmented into its key blocks as shown in the legend for the figure Note Key to blocks A E A Power and serial communications B eZ80F91 Module interface C JTAG and ZDI debug interfaces Figure 2 The eZ80 Development Platform D Application module interfaces E GPIO and LED with Address Decoder UMO14210 1003 PRELIMINARY Introduction eZ80F91 Development Kit User Manual 6 Diog Figure 3 is a photographic representation of the eZ80F91 Module seg mented into its key blocks as shown in the legend for the figure Note Key to blocks A C A eZ80F91 Module interfaces B eZ80F91 CPU C 10 100BaseT Ethernet Interface D I
49. hesis loc loc loc loc loc loc loc PRELIMINARY eZ80F91 Development Kit B3 p4 pol P6 P10 P11 P12 User Manual 110 Appendix A 73 eZ80F91 Development Kit User Manual 74 Likog A5 synthesis loc P13 A6 synthesis loc P27 A7 synthesis loc P26 nIORO synthesis loc P2 nRD synthesis loc P7 nCS synthesis loc P25 CS3 for CS9800 nWR synthesis loc P9 nMREQ synthesis loc P16 output nEM RD synthesis loc P17 nEM WR synthesis loc P18 nCT WR synthesis loc P19 nAN WR synthesis loc P20 nDIS ETH synthesis loc P21 parameter anode 8 h00 parameter cathode 8 h01 parameter latch 8 h02 wire 7 0 address A7 A6 A5 A4 A3 A2 A1 A0 assign nEM WR nDIS_EM 1 nWR 0 nEM EN 0 address latch assign nEM_RD nDIS EM 1 nRD 0 amp nEM EN 0 address latch assign nAN WR nDIS EM 1 nWR 0 nEM EN 0 address anode General Array Logic Equations PRELIMINARY UM014210 1003 eZ80F91 Development Kit User Manual 110 75 assign nCT_WR nDIS_EM 1 nWR 0 amp nEM EN 0 address cathode assign nDIS_ETH nCS endmodule UMO14210 1003 PRELIMINARY Appendix A eZ80F91 Development Kit User Manual 76 110 Ge
50. ic memory requirement for small applications development This SRAM is in the address range B80000h BFFFFFh With the 512KB of SRAM on the eZ80F91 Module this addressing structure provides 1 MB of contiguous SRAM for immediate use The Chip Select 2 CS2 signal is used to access the 512KB of SRAM on the eZ80 Development Platform Additional SRAM The amount of eZ80 Development Platform memory can be extended if required by adding SRAM devices U19 U18 and U17 provide this capa bility However the user should be aware that additional SRAM must be installed in the following order 1 U19 address range B00000h B7FFFFh 2 U18 address range A80000h AFFFFFh 3 U17 address range A00000h A7FFFFh If SRAM memory is installed in a different order than the above sequence SRAM will not be contiguous unless the user is able to change the address decoder U10 Memory access decoding is performed by this Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 31 address decoder implemented in the Generic Array Logic device GAL22LV 10D U10 On Chip SRAM The eZ80F91 device on the eZ80F91 Module contains 8KB of on chip SRAM Upon power up this SRAM is enabled and mapped to address FFCOOOh Using the RAM Address Register this 8KB memory can be mapped to the top of any 64KB block It can also be disabled Please see the eZ80F91 Product Specification PS0192 for more information Flash Memory
51. in future eZ80 devices Table 21 J15 RS485_1_EN Shunt Status Function Affected Device IN The RS485 circuit is enabled on UARTO IrDA UARTO CONSOLE The UARTO CONSOLE interface and IrDA are interface RS485 interface disabled OUT The RS485 circuit is disabled on UARTO IrDA UARTO CONSOLE interface RS485 interface Note To enable the RS485 circuit the corresponding IrDA RS232 circuit must be disabled Jumper J16 The J16 jumper connection controls the selection of the RS485 circuit However UART1 MODEM interface and the socket modem interface are disabled if the RS485 circuit is enabled When the shunt is placed the RS485 circuit is enabled See Table 22 Table 22 J16 RS485_2_EN Shunt Status Function Affected Device IN The RS485 circuit is enabled on UART1 The UART1 MODEM interface UART1 MODEM interface and the Socket Socket Modem Interface and Modem interface are disabled RS485 interface OUT The RS485 circuit is disabled on UART1 UART1 MODEM interface Socket Modem Interface and RS485 interface UM014210 1003 PRELIMINARY eZ80 Development Platform 40 eZ80F91 Development Kit User Manual Zik Jumper J17 The J17 jumper connection controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 23 Table 23 J17 RT 1 Shunt Status Function Affected Device IN The Termination Resi
52. m A block diagram representing both of these boards is shown in Figure 1 on page 4 Despite its small footprint the eZ80F91 Module provides a CPU Flash memory Ethernet interface SRAM an IrDA transceiver and a real time clock with a back up battery This module is powered by the eZ80F91 microcontroller a new member of ZILOG s eZ80 product family The eZ80F91 Module can also be used as a stand alone development tool when provided with an external power source Fast Buffer A Fast Buffer is located on the data bus to Flash memory The purpose of this Fast Buffer is to avoid bus contention that can exist due to the slow turn off time of Flash memory and the fast bus turn around time of the eZ80F91 device a generic feature of the eZ80 family when is used in native mode The discussion that follows references Figure 11 Bus contention can occur when two or more devices drive a common bus CS0 on the eZ80F91 device drives the Flash CE Upon accessing Flash memory CS0 is driven High a maximum of 8 8ns after the next rising edge of the CPU Clock T6 please refer to the External Memory Read eZ80F91 Module PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 45 Timing diagram in the eZ80F91 Product Specification PS0192 for assis tance The Flash turn off time Top is 25ns the duration from OE or CE going High to Flash output drivers in a high impedance state For fur ther information see the MT28F008 data shee
53. mory configurations e On chip SRAM 8KB e Off chip SRAM 512KB On chip Flash 256KB Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual za 51 Reset Generator An onboard supervisory chip is connected to the eZ80F91 Reset input pin It performs reliable Power On Reset functions generating a reset pulse with a duration of 200ms if the power supply drops below 2 93 V This reset pulse ensures that the board always starts in a defined condi tion The RESET pin on the I O connector reflects the status of the RESET line It is a bidirectional pin for resetting external peripheral com ponents or for resetting the eZ80F91 Development Kit with a low imped ance output e g a 100 Ohm push button IrDA Transceiver An onboard IrDA transceiver ZiLOG ZHX1810 is connected to PDO TX PD1 RX and PD2 Shutdown IR_SD The IrDA transceiver is of the LED type 870nm Class 1 The IrDA transceiver is accessible via the IrDA controller attached to UARTO on the eZ80F91 device While using the IrDA transceiver the user must disable the console port on the eZ80 Development Platform See Table 5 on page 22 To use the UARTO as a console or to save power the transceiver can be disabled by the software or by an off board signal when using the proper jumper selection The transceiver is disabled by setting PD2 IR_SD High or by pulling the DIS_IRDA pin on the I O connector Low The shutdown feature
54. neral Array Logic Equations PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Diipa 77 Customer Feedback Form If you note any inaccuracies while reading this User Manual please copy and complete this form then mail or fax it to ZiLOG see Return Information below We also welcome your sugges tions eZ80F91 Development Kit Serial or Board Fab Rev Software Version Document Number Host Computer Description Type Customer Information Name Country Company Phone Address Fax City State Zip E Mail Return Information ZiLOG System Test Customer Support 532 Race Street San Jose CA 95126 Phone 408 558 8500 Fax 408 558 8536 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem include all steps leading up to the occurrence of the problem Attach additional pages as necessary UM014210 1003 PRELIMINARY Customer Feedback Form
55. nued Pin Symbol Signal Direction Active Level eZ80F91 Signal 37 SDA Bidirectional Yes 38 GND 39 FlashWE Output Low No 40 GND 41 CS3 Input Low Yes 42 DIS IrDA Output Low No 43 RESET Bidirectional Low Yes 44 WAIT Output Pull Up 10KQ Low Yes 45 Vop 46 GND 47 HALT_SLP Input Low Yes 48 NMI Output Low Yes 49 Vpp 50 Reserved Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F91 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F91 device Op erational Description PRELIMINARY UM014210 1003 eZ80F91 Development Kit User Manual AR 110 Internal On Chip Flash Memory To program internal on chip Flash memory the JP3 shunt must be installed Table 4 lists the setting for the JP3 jumper that is resident on the eZ80F91 Module A sample project provided with ZDS II Led DemoFlash pro can only be programmed into on chip Flash memory Table 4 Jumper eZ80F91 Module Shunt Symbol Jumper Name Status Function Affected Device JP3 Write Enable In On chip Flash is enabled for On chip Flash WR EN writing Out On chip Flash memory is write On chip Flash protected UM014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual 22 Diog Application Module Interface An Application Module Interface is
56. o exchange one plug configuration for another perform the following steps 1 Place the tip of the removal tool into the round hole at the top of the current plug configuration 2 Press down to disengage the keeper tab and push the plug configura tion out of its slot 3 Select the plug configuration appropriate for your location and insert it into the slot formerly occupied by the previous plug configuration Changing the Power Supply Plug PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual 110 55 4 Push the new plug configuration down until it snaps into place as indicated in Figure 17 Figure 17 Inserting a New Plug Configuration UMO14210 1003 PRELIMINARY eZ80F91 Module 56 eZ80F91 Development Kit User Manual Diog ZPAKII ZPAK II is a debug tool used to develop and debug hardware and soft ware Itis a networked device featuring an Ethernet interface and an RS232 console port ZPAKII is shipped with a preconfigured IP address that can be changed to suit the user on a local network For more informa tion about using and configuring ZPAKII please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0020 and the ZPAKII Product User Guide PUGOO15 ZDI Target Interface Module JTAG The ZDI Target Interface Module provides a physical interface between ZPAK II and the eZ80 Development Platform The TIM module supports ZDI functions For more information on using the TIM module or
57. provided to allow the user to add an application specific module to the eZ80 Development Platform ZiLOG s Thermostat Application Module not provided in the kit is an example of an application specific module that demonstrates an HVAC control sys tem Implementing an application module with the Application Module Interface requires that the eZ80F91 Module also be mounted on the eZ80 Development Platform because the eZ80F91 device controls the applica tion To mount an application module use the two male headers J6 and J8 Connector J6 carries the General Purpose Input Output ports GPIO and connector J8 carries memory and control signals To design an application module the user should be familiar with the architecture and features of the eZ80F91 Module currently installed Tables 5 and 6 list the signals and functions related to each of these connectors by pin Power and ground signals are omitted for the sake of simplicity Table 5 GPIO Connector J6 Signal Pin Function Direction Notes SCL 5 12C Clock IN OUT SDA 7 12C Data IN OUT MOD DIS 9 Modem Disable IN If a shunt is installed between pins 6 and 9 the modem function on the eZ80 Development Platform is disabled MWAIT 13 WAIT signal for IN the CPU EM DO 15 Emulated BitO IN OUT Note All of the signals are driven directly by the CPU Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Man
58. r J3 The J3 jumper connection controls GPIO emulation mode and communi cation with the 7x5 LED When the shunt is placed GPIO emulation is disabled See Table 16 Table 16 J3 DIS_EM Shunt Status Function Affected Device IN Application Module Communication with 7x5 LED and Port emulation Hardware Disabled circuit is disabled OUT Application Module Communication with 7x5 LED and Port A emulation Hardware Enabled circuit is enabled Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Ar 110 Jumper J7 The J7 jumper connection controls Flash boot loader programming When the shunt is placed overwriting of the Flash boot loader program is enabled See Table 17 Table 17 J7 FlashWE Off Chip Shunt Status Function Affected Device OUT The Flash boot sector of the eZ80F91 Flash boot sector of the eZ80F91 Module is write protected Module IN The Flash boot sector of the eZ80F91 Flash boot sector of the eZ80F91 Module is enabled for writing or Module overwriting Note As shipped from the factory external Flash memory is not installed Note Jumper J11 The J11 jumper connection controls access to the off chip Flash memory device When the shunt is placed access to this Flash device is enabled See Table 18 The silk screened label on the eZ80 Development Platform for jumper J11 is incorrect Currently it reads DIS_FLASH The correct label is EN_FLASH Table
59. r connecting an external moden if used with the eZ80F91 Development Kit IC Devices I2C Devices The two PC devices on the eZ80 Development Platform are the U2 EEPROM and the U13 Configuration register The EEPROM provides 16KB of memory The Configuration register provides access to control the configuration of an application specific function at the Application Module Interface Neither device is utilized by the eZ80F91 Development PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Zi 110 Kit software The user is free to develop proprietary software for these two devices The addresses for accessing these devices are listed in Table 27 Table 27 IC Addresses Device Bit 7 6 5 4 3 2 1 0 EEPROM U10 1 0 1 0 0 A1 A0 R W Configuration Register U13 1 0 0 1 1 1 0 RW Note EEPROM address bits AO and A1 are configured for 0s UMO014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual Diog eZ80F91 Module This section describes the eZ80F91 Module hardware its interfaces and key components including the CPU real time clock IrDA transceiver and memory Functional Description The eZ80F91 Module is a compact high performance module specially designed for the rapid development and deployment of embedded sys tems Additional devices such as serial ports LED matrices GPIO ports and I C devices are supported when connected to the eZ80 Development Platfor
60. rDA transceiver Figure 3 The eZ80F91 Module The structures of the eZ80 Development Platform and the eZ80F91 Module are illustrated in the Schematic Diagrams starting on page 61 eZ80F91 Development Kit Overview PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Zi 110 eZ60 Development Platform This section describes the eZ80 Development Platform hardware its key components and its interfaces including programming information such as memory maps and register definitions Functional Description The eZ80 Development Platform consists of seven major hardware blocks These blocks listed below are diagrammed in Figure 4 e eZ80F91 Module interface 2 female headers Power supply for the eZ80 Development Platform the eZ80F91 Module and application modules e Application Module interface 2 male headers e GPIO and LED matrix Two RS222 serial communications ports Two RS485 ports Embedded modem interface e PC devices UM014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual Z 8 110 Module Interface Data Bus RS232 0 Console 512 KB up to 2 MB RS232 1 Modem RS485_0 1 Connect A mai Embedded Modem GPIO and Pc elm s bs T Application Module Headers Headers Address Decoder Figure 4 Basic eZ80 Development Platform Block Diagram Functional Description PRELIMINARY
61. stor for RS485 1 is IN RS485 interface OUT The Termination Resistor for RS485_1 is OUT RS485 interface Note Before enabling the termination resistor ensure that the device is located at the end of the interface line Jumper J18 The J18 jumper connection controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 24 Table 24 J18 RT_2 Shunt Status Function Affected Device IN The Termination Resistor for RS485 2 is IN RS485 interface OUT The Termination Resistor for RS485_2 is OUT RS485 interface Note Before enabling the termination resistor ensure that the device is located at the end of the interface line Operational Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual AZ 110 Jumper J19 The J19 jumper connection selects the range of memory addresses for the external chip select signal CS_EX to the application module See Table 25 Table 25 J19 EX_SEL Shunt Status Function Affected Device 1 2 CS EX is decoded in the CSO memory space and is Application module located in the address range 400000h 7FFFFFh addressing 3 4 CS_EX is decoded in the CS2 memory space and is Application module located in the address range A00000h A7FFFFh addressing 5 6 CS_EX is decoded in the CS2 memory space and is Application module located in the address range A80000h AFFFFFh addressin
62. t on www micron com CPU Clock CS0 eZ80F91 Data Bus Figure 11 Possible Bus Contention without Fast Buffer Essentially after the eZ80F91 device accesses Flash memory a time duration of 8 8ns 25ns 33 8ns can transpire before Flash memory stops driving the data bus At that time the eZ80F91 device is well into the next bus cycle Assuming this next cycle is the Memory Write cycle then the data output of the eZ80F91 device is valid not later than T3 7 5ns and the write pulse is asserted not later than 4 5ns after the falling edge of the CPU Clock 14 5ns from the rising edge if the CPU Clock is 50MHz The duration of bus contention Tcon is 33 8ns UMO14210 1003 PRELIMINARY eZ80F91 Module eZ80F91 Development Kit User Manual 46 Diog 7 5ns 26 3ns Refer to the External Memory Write Timing diagram in the eZ80F91 Product Specification PS0192 for assistance With the addition of a Fast buffer Flash turn off time is reduced from 25ns to 5 5ns Bus contention can still occur but the amount of time it consumes is not Tcon 26 3ns but rather Tcoy 8 8ns 7 5ns 5 5ns 6 8ns At this faster rate data that is being written does not become corrupted because the write pulse is not yet asserted As of the date of publication of this document ZiLOG has not completed an analysis of the effect that this 6 8 ns period of bus contention has on the design An Application Note from Cypress Semiconductor titled NoB
63. tons serve as input devices to the eZ80F91 device The programmer can use them as necessary for application devel opment All push buttons are connected to the GPIO Port B pins PBO The PBO push button switch SW1 is connected to bit 0 of GPIO Port B This switch can be used as the port input if required by the user PB1 The PB1 push button switch SW2 is connected to bit 1 of GPIO Port B This switch can be used as the port input if required by the user PB2 The PB2 push button switch SW3 is connected to bit 2 of GPIO Port B This switch can be used as the port input if required by the user RESET The Reset push button switch SW4 resets the eZ80 CPU and the eZ80 Development Platform UM014210 1003 PRELIMINARY eZ80 Development Platform 36 eZ80F91 Development Kit User Manual Diog Jumpers The eZ80 Development Platform provides a number of jumpers that are used to enable or disable functionality on the platform enable or disable optional features or to provide protection from inadvertent use Jumper J2 The J2 jumper connection enables disables IrDA transceiver functionality When the shunt is placed IrDA communication is disabled See Table 15 Table 15 J2 DIS_IrDA Shunt Status Function Affected Device IN IrDA on eZ80F91 UARTO is configured to work with the RS232 or the Module disabled RS485 interfaces OUT IrDA on eZ80F91 IrDA is enabled to work with UARTO on the eZ80F91 Module enabled device Jumpe
64. top layer silkscreen of the eZ80F91 Module JP1 o eZ80F91 MODULE JP2 O O 2 OO OO 1 O O ris l IP dl Iria OO m5 L1 Trot O O O O O x rie IP dl Uris O O re Ld IjR49 29 D o ms Al 1 Ihe O eb O O oo P O O O O oo OO P o o o o o U6 OO O O TUER LLLIH a o O o ft oe o ca O O ze e a O O Oo T2 ore 5 E O O JP3 Ris 111 o S O O O Ol med B 8 O O O O iso mac go oo et O O O O mo Ll le l l o gg JO 9 OO Cu 8 O O OO III 00 0 0 e 35 o OE OO o ol amp o o Jo o o TA B an ed d o oP 3 42 ef afar oo O O LEBEN j 936 E O joo oo p Sn o O O ool de a O O ool M ERE Jo o O O o o 9 loo 00 E AS o O O 96 gl 0000 Ss oo e s 8 CU o e OO QQ oo Ya vs 2090 RT B 5 3 O O ool cr dTI O O a Y o o O O OO ep d o E cx oo O O re IT g i JI o he Rio ta OO Quo cs dl B IT dye iL OO 00 o __ o R29 LJ U3 o O o7 Figure 13 eZ80F91 Module Top Layer Functional Description PRELIMINARY UMO14210 1003 eZ80F91 Development Kit User Manual Z
65. ual Lia 23 Table 5 GPIO Connector J6 Continued Signal Pin Function Direction Notes CS3 17 Chip Select 3 of OUT This signal is also present on the CPU the J8 EM D 7 1 21 23 25 Emulated Bit IN OUT 27 29 31 7 1 33 Reserved 35 PC 7 0 39 41 43 Port C Bit 7 0 IN OUT 45 47 49 51 53 ID_ 2 0 6 8 10 eZ80 OUT Development Platform ID CON_DIS 12 Console Disable IN If a shunt is installed between pins 12 and 14 the Console function on the eZ80 Development Platform is disabled Reserved 16 18 PD 7 0 22 24 26 Port D Bit 7 0 IN OUT 28 30 32 34 36 PB 7 0 40 42 44 Port B Bit 7 0 IN OUT 46 48 50 52 54 Note All of the signals are driven directly by the CPU UMO14210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual 24 aa a Table 6 CPU Bus Connector J8 Signal Pin Function Direction A 0 7 3 10 Address Bus Low Byte OUT A 8 15 13 20 Address Bus High Byte OUT A 16 23 23 30 Address Bus Upper Byte OUT RD 33 READ Signal OUT RESET 35 Push Button Reset OUT BUSACK 37 CPU Bus Acknowledge Signal OUT NMI 39 Nonmaskable Interrupt IN D 0 7 43 50 Data Bus IN OUT CS 0 3 53 56 Chip Selects MREQ 57 Memory Request OUT WR 34 Write Signal OUT INSTRD 36 Instruction Fetch OUT BUSREQ 38 CPU Bus Request signal PHI 40 Clock output of the CPU OUT Note All of the signals except BUSACK and INSTRD are driven by low voltage
66. y is enabled by CSO on module SRAM is enabled by CS1 and the remainder of the resources are enabled by CS2 The number of wait states N for each Chip Select are indicated in Table 13 Table 13 Chip Select Wait States Memory Type CS0 CS1 CS2 CS3 Flash N 7 i E On module SRAM N 1 eZ80 Development Platform SRAM N 2 and other resources Note Not applicable for these resources LEDs As stated on page 29 LEDs D1 D2 D3 and D4 function as status indica tors for an optional modem This section describes each LED and the LED matrix device LED Matrix The 7x5 LED matrix device on the eZ80 Development Platform is a memory mapped device that can be used to display information such as programmed alphanumeric characters For example the LED display sample program that is shipped with this kit displays the alphanumeric message ez80 To illuminate any LED in the matrix its respective anode bit must be set to 1 and its corresponding cathode bit must be set to 0 Bits 0 6 in Table 8 are LED anode bits They must be set High 1 and their corresponding cathode bits bits 0 4 in Table 14 must be set Low 0 to illuminate each of the LED s respectively UMO014210 1003 PRELIMINARY eZ80 Development Platform eZ80F91 Development Kit User Manual 34 Diog If bit 7 in the GPIO Output Control Register is 1 all of the GPIO lines are configured as inputs If this bit is 0 all of the GPIO lin

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