PXI-8320 User Manual
Contents
1. MTBF Contact factory Weight 0 18 kg 0 41 Ib typical no DRAM installed Electrical Source Typical Direct Current Max 5 VDC 2 2 A 3 5 A Performance MXI Transfer Rate Peak 33 MB s Sustained 23 MB s National Instruments Corporation A 3 PXI 8320 User Manual MXI 2 Connector This appendix describes the MXI 2 connector on the PXI 8320 module The MXI 2 connector is a 144 pin female connector manufactured by Meritec Meritec part number 182800A 01 The mating cable assembly is National Instruments part number 182801 A xxx where xxx is the length in meters Figure B 1 shows the MXI 2 connector on the PXI 8320 The drawing shows the pinout assignments for each pin which are described in Table B 1 O A35 A33 A31 A29 A27 A25 A23 A21 A19 A17 A15 A13 A11 AQ A7 AS AB Al A36 A34 A32 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A8 AG A4 A2 B35 B33 B31 B29 B27 B25 B23 B21 A19 B17 B15 B13 B11 B9 B7 B5 B3 B1 B36 B34 B32 B30 B28 B26 B24 B22 B20 B18 B16 B14 B12 B10 B8 B6 B4 B2 C35 C33 C31 C29 C27 C25 C23 C21 C19 C17 C15 C13 C11 C9 C7 C5 C3 C1 C36 C34 C32 C30 C28 C26 C24 C22 C20 C18 C16 C14 C12 C10 C8 C6 C4 C2 D35 D33 D31 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D9 D7 D5 D3 D1 D36 D34 D32 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D8 D6 D4 D2 Figure B 1 MXI 2 Connector Table B 1 lists the signal assignments for the MXI 2 connector Table B2. PXI 8320 Registers o A24 A32 Decoder LA Decoder MXI Bus 4 M MXIbus Slave ea State Machine a MXlIbus Terminate MXlIbus System Controller Functions MXibus Bus Timeout Unit Interrupt Circuitry gt Trigger Circuitry gt Utility Signal ra Circuitry PXI 8320 User Manual PCI Bus Slave State Machine Base Address Registers Figur 2 2 e 2 1 PXI 8320 Block Diagram This state machine monitors the output of the window decoders and responds to PCI bus cycles intended for the PXI 8320 The cycles may map to the PXI 8320 registers the onboard DRAM or the MXIbus The PXI 8320 is a medium speed PCI decoder that accepts both configuration and memory cycles The interface logic ensures that the PXI 8320 meets the loading driving and timing requirements of the PCI specification The PXI 8320 uses PCI registers BARO to BAR3 to decode PCI memory space The final destination of PCI cycles that match the base address registers is determined by the programmable outward windows National Instruments Corporation e Programmable Outward Windows MXIbus Master State Machine PCI Bus Master State Machine DMA Controllers National Instruments Corporation 2 3 Chapter 2 Functional Overview The PXI 8320 has multiple programmable outward windows These windows direct the PCI slave
3. MXIbus Termination Option PXI 8320 User Manual The MXIbus requires that the first and last devices in the daisy chain have a termination network The PXI 8320 has the ability to terminate the MXIbus signals on the interface board using terminating resistor networks in single inline packages SIPs You should terminate only the first and last devices in the MXIbus daisy chain The onboard termination option lets you install or remove terminating resistor networks from their sockets on the PXI 8320 board The board is shipped from the factory with these terminating resistor networks installed If your PXI 8320 is to be the first or last device in the MXIbus daisy chain leave these internal resistor terminators in place Also leave the jumper on the pins at W1 in place when the PXI 8320 is an end device If you do not make the PXI 8320 an end device on the MXIbus daisy chain remove the jumper from the pins at W1 as well as all of the internal terminating resistor networks from their sockets Store them in a safe place in case you later decide to change the MXIbus system configuration When reinstalling the resistor networks ensure that they are plugged firmly into their respective sockets Figure 3 3 shows the location of the terminating resistors and the W1 jumper The figure shows the resistors and the jumper installed for use as an end device col Lom a m7 MG 1 1 1 1 1 7 am on O PEEEETT
4. write posting PXI 8320 User Manual VXI Resource Editor program a part of the NI VXI bus interface software package Used to configure the system edit the manufacturer name and ID numbers edit the model names of VXI and non VXI devices in the system as well as the system interrupt configuration information and display the system configuration information generated by the Resource Manager A program in the NI VXI bus interface software package that initializes the board interrupts shared RAM VXI register configurations and bus configurations The simplest required communication protocol supported by message based devices in a VXIbus system It utilizes the A16 communication registers to transfer data using a simple polling handshake method A mechanism that signifies that a device will immediately give a successful acknowledge to a write transfer and place the transfer in a local buffer The device can then independently complete the write cycle to the destination G 10 National Instruments Corporation Index A A24 A32 decoder 2 4 base address registers 2 2 bulletin board support C 1 C cables optional 1 3 to 1 4 configuration 3 1 to 3 6 configuration EEPROM 3 2 to 3 3 electrostatic discharge damage warning 3 1 fixing invalid EEPROM configuration 3 5 to 3 6 MXlIbus termination option 3 4 onboard DRAM 3 3 parts locator diagram 3 2 configuration EEPROM 3 2 to 3 3 factory configuration half
5. signals interrupt trigger and utility signal circuitry 2 6 MXI 2 connector signal assignments table B 1 to B 3 signal characteristics table B 3 slave state machine MXIbus 2 5 PCI bus 2 2 software optional 1 4 to 1 5 specifications A 1 to A 3 electrical A 3 environmental A 3 MXIbus capability descriptions A 1 PCI functionality A 2 performance A 3 National Instruments Corporation Index physical A 3 requirements A 2 state machines MxXIbus master state machine 2 2 MxXlIbus slave state machine 2 5 PCI bus master state machine 2 3 PCI bus slave state machine 2 2 System Controller functions MXIbus 2 5 T technical support C 1 to C 2 telephone and fax support numbers C 2 termination option MXIbus 2 5 3 4 timeout unit MXIbus 2 5 trigger signals 2 6 U utility signals 2 6 V VXledit configuration utility 3 5 PXI 8320 User Manual
6. 3 2 fixing invalid EEPROM configuration 3 5 to 3 6 operation figure 3 3 restoring factory configuration figure 3 6 Switch 1 FOV 3 2 TST switch 1 switch 2 3 3 user configuration half 3 2 controllers DMA controllers 2 3 MXIbus System Controller functions 2 5 customer communication viii C 1 to C 2 National Instruments Corporation D DMA controllers 2 3 documentation conventions used in manual vii viii organization of manual vii related documentation viii DRAM See onboard DRAM E e mail support C 2 EEPROM See configuration EEPROM electrical specifications A 3 electronic support services C 1 to C 2 environmental specifications A 3 equipment optional 1 3 to 1 4 F fax and telephone support numbers C 2 Fax on Demand support C 2 FTP support C 1 installation See also configuration electrostatic discharge damage warning 3 1 procedure 3 5 protection from electrical hazard warning 3 5 interrupt signals 2 6 PXI 8320 User Manual Index L LabVIEW software 1 4 LabWindows CVI software 1 4 to 1 5 logical address decoder 2 4 manual See documentation master state machines MXIbus master state machine 2 3 PCI bus master state machine 2 3 memory specifications A 2 See also onboard DRAM MXI 2 connector B 1 to B 3 pinout assignments figure B 1 signal assignments table B 1 to B 3 signal characteristics table B 3 MXIbus capability descriptions A 1 master
7. 5422 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity FTP Support To access our FTP site log on to our Internet host ftp natinst com aS anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation C 1 PXI 8320 User Manual Fax on Demand Support Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone at 512 418 1111 E Mail Support Currently USA Only You can submit technical support questions to the applications engineering team through e mail at the Internet address listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions support natinst com Telephone and Fax Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Country Australia Austria Belgium Brazil Canada Ontario Canada Quebec Denmark Finland
8. 8320 Configuration and Installation If this situation occurs after you change the configuration on the PXI 8320 follow these steps to reconfigure the PXI 8320 1 Turn off your chassis Ip Warning To protect both yourself and the chassis from electrical hazards leave the chassis off while changing the settings on the PXI 8320 module 2 Remove the PXI 8320 from your PXI CompactPCI chassis 3 Change switch 1 FOV on U6 to the ON position as shown in Figure 3 4 to restore the factory configuration TST Cc pos CE e cT pect Figure 3 4 Restoring the Factory Configuration t Note If you have to remove the PXI 8320 module to access switch 1 follow the installation instructions given in the previous section to re install the PXI 8320 module 4 Replace the PXI 8320 5 Turn on the chassis The computer should boot this time because it is using the factory default configuration to initialize the PXI 8320 module 6 Use the T amp M Explorer utility in NI VXI to re adjust the configuration of your PXI 8320 For information on the software including optional settings use T amp M Explorer and its online help Use the Windows Start menu to open the NI VXI program group and select T amp M Explorer To access the T amp M Explorer online help open the Help menu and select Help Topics 7 After saving the configuration exit Windows and turn off the chassis Remove the PXI 8320 Change switc
9. Commander and Servant mappings and self test and diagnostic management An acknowledge by a destination that signifies that the cycle did not complete and should be repeated seconds A device controlled by a Commander there are message based and register based Servants A communication protocol that uses a block of memory that is accessible to both a client and a server The memory block operates as a message buffer for communications A functional part of a MXI VME V XIbus device that detects data transfer cycles initiated by a VMEbus master and responds to the transfers when the address specifies one of the device s registers A device is in slave mode it if is responding to a bus cycle A device configured for installation in Slot 0 of a VXIbus mainframe This device is unique in the VXIbus system in that it performs the VMEbus System Controller functions including clock sourcing and arbitration for data transfers across the backplane Installing such a device into any other slot can damage the device the VXIbus backplane or both Small Outline Dual Inline Memory Module A device whose logical address cannot be set through software that is it is not dynamically configurable A VMEbus signal that is used by a device to indicate an internal failure A failed device asserts this line In VXI a device that fails also clears its PASSed bit in its Status register A VMEbus signal that is used by a device to indicate a syst
10. France Germany Hong Kong Israel Italy Japan Korea Mexico Netherlands Norway Singapore Spain Sweden Switzerland Taiwan United Kingdom United States PXI 8320 User Manual Telephone 03 9879 5166 0662 45 79 90 0 02 757 00 20 011 288 3336 905 785 0085 514 694 8521 45 76 26 00 09 725 725 11 01 48 14 24 24 089 741 31 30 2645 3186 03 6120092 02 413091 03 5472 2970 02 596 7456 5 520 2635 0348 433466 32 84 84 00 2265886 91 640 0085 08 730 49 70 056 200 51 51 02 377 1200 01635 523545 512 795 8248 C 2 Fax 03 9879 6277 0662 45 79 90 19 02 757 03 11 011 288 8528 905 785 0086 514 694 4399 45 76 26 02 09 725 725 55 01 48 14 24 14 089 714 60 35 2686 8505 03 6120095 02 41309215 03 5472 2977 02 596 7455 5 520 3282 0348 430673 32 84 86 00 2265887 91 640 0533 08 730 43 70 056 200 51 55 02 737 4644 01635 523154 512 794 5678 National Instruments Corporation Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additio
11. Q PXI 8320 interface board Q MXI 2 cable Optional Equipment National Instruments Corporation Type M1 MXI 2 Cables Straight point connector to straight point connector 1 2 4 8 or 20m Type M2 MXI 2 Cables Straight point connector to right angle daisy chain connector 1 2 4 8 or 20m Type M3 MXI 2 Cables Right angle point connector to right angle daisy chain connector 1 2 4 8 or 20m Type M4 MXI 2 Cables Straight point connector to reverse right angle daisy chain connector 1 2 4 8 or 20m Type MB 1 MXI 2 Cables Standard right angle point connector to wall mount bulkhead exit connector 1 2 4 or8m Type MB 2 MXI 2 Cables Straight bulkhead exit connector to straight bulkhead entry connector 1 2 4 0 8m Type MB 3 MXI 2 Cables Wall mount bulkhead entry connector to straight right angle daisy chain connector 1 2 4 or8m Type MB 4 MXI 2 Cables Standard right angle point connector to straight bulkhead entry connector 1 2 4 or8m 1 3 PXI 8320 User Manual Chapter 1 Introduction e Type MB 5 MXI 2 Cables Standard right angle daisy chain connector to straight bulkhead exit connector 1 2 4 or8m e Type MB 6 MXI 2 Cables Reverse right angle daisy chain connector to wall mount bulkhead exit connector 1 2 4 or8m Onboard DRAM 4or16MB Optional Software PXI 8320 User Manual You can order the National Instruments NI VXI bus interface software for
12. VMEbus backplane The DTB is used by a bus master to transfer binary data between itself and a slave device Dual Inline Package Direct Memory Access a method by which data is transferred between devices and internal memory without intervention of the central processing unit Dynamic RAM A region of PCI address space that is decoded by the PXI 8320 for use by the NI VXI software Data Acknowledge signal See Data Transfer Bus A method of automatically assigning logical addresses to VXIbus devices at system startup or other configuration times A device that has its logical address assigned by the Resource Manager A VXI device initially responds at Logical Address 255 when its MODID line is asserted A MXIbus device responds at Logical Address 255 during a priority select cycle The Resource Manager subsequently assigns it a new logical address which the device responds to until powered down Emitter Coupled Logic Electronically Erasable Programmable Read Only Memory An intelligent CPU controller interface plugged directly into the VXI backplane giving it direct access to the VXIbus It must have all of its required VXI interface capabilities built in Electromechanical Compliance G 4 National Instruments Corporation EMI expansion ROM external controller F fair requester hex IC IEEE in interrupt interrupt handler interrupt level T O IRQ National Instruments Corporation G 5
13. in this manual LF This icon to the left of bold italicized text denotes a note which alerts you to important information AN This icon to the left of bold italicized text denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash National Instruments Corporation vil PXI 8320 User Manual About This Manual AX bold italic italic monospace This icon to the left of bold italicized text denotes a warning which advises you of precautions to take to avoid being electrically shocked Bold italic text denotes a note caution or warning Italic text denotes emphasis a cross reference or an introduction to a key concept Text in this font denotes text or characters that you should literally enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments taken from programs Related Documentation The following documents contain information that you may find helpful as you read this manual e ANSI TEEFE Standard 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus e ANSI TEEFE Standard 1155 1993 IEEE VMEbus Extensions for Instrumentation VXIbus e ANSI VITA 1 1994 VME64 e Multisystem Extension Interface Bus Sp
14. safeguard human health and safety in medical or clinical treatment Compliance FCC DOC Radio Frequency Interference Class A Compliance This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual may cause interference to radio and television reception Classification requirements are the same for the Federal Communications Commission FCC and the Canadian Department of Communications DOC This equipment has been tested and found to comply with the following two regulatory agencies Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Notices to User Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules This device complies
15. state machine to route incoming cycles to local registers onboard DRAM or the MxXiIbus This state machine generates MXIbus master data transfer cycles when directed to do so by the PCI bus slave state machine thus allowing PCI bus cycles to map to the MXIbus The PXI 8320 can generate D64 D32 D16 and D08 EO single block and RMW cycles on MXIbus in A32 and A24 space performing the D64 transfers by doing successive D32 transfers The PXI 8320 can also generate data transfers in A16 space with the exception of D64 and block transfers The MXIbus master state machine also checks MXIbus parity on read data received and stores an error status when a parity error is detected The transceivers ensure that the PXI 8320 meets the loading driving and timing requirements of the MXIbus specification for the AD 3 1 0 AM 4 0 and CONVERT signals This state machine generates PCI bus master data transfer cycles when directed to do so by the MXIbus slave state machine or one of the DMA controllers on the PXI 8320 The PXI 8320 can generate 8 16 and 32 bit memory read and write cycles both single and multiple The PXI 8320 does not generate unaligned PCI bus data transfers The interface logic ensures that the PXI 8320 meets the loading driving and timing requirements of the PCI specification The PXI 8320 has two independent onboard DMA controllers The DMA controllers can transfer data at maximum speeds between any combin
16. the PXI 8320 The NI VXI software includes a Resource Manager graphical and text based versions of an interactive VXI resource editor program a comprehensive library of software routines for VXI VME programming and graphical and text based versions of an interactive control program for VXI VME You can use this software to seamlessly program multiple mainframe configurations and have software compatibility across a variety of VXI VME controller platforms In addition to NI VXI you can order the National Instruments LabVIEW and LabWindows CVI application programs and instrument drivers to ease your programming task These standardized programs match the modular virtual instrument capability of VXI and can reduce your VXI VMEbus software development time These programs are fully VXIplug amp play compliant and feature extensive libraries of VXI instrument drivers written to take full advantage of direct VXI control LabVIEW is a complete programming environment that departs from the sequential nature of traditional programming languages and features a graphical programming environment LabWindows CVI is an interactive C development environment for building test and measurement and instrument control systems It includes interactive code generation tools and a graphical editor for building custom user interfaces LabVIEW and LabWindows CVI include all the tools needed for instrument control data acquisition analysis and presentation When y
17. with the FCC rules only if used with shielded interface cables of suitable quality and construction National Instruments used such cables to test this device and provides them for sale to the user The use of inferior or nonshielded interface cables could void the user s authority to operate the equipment under the FCC rules If necessary consult National Instruments or an experienced radio television technician for additional suggestions The following booklet prepared by the FCC may also be helpful Interference to Home Electronic Entertainment Equipment Handbook This booklet is available from the U S Government Printing Office Washington DC 20402 Canadian Department of Communications This Class A digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe A respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Contents About This Manual Organization of This Manual 0 cece eeeceeceeeecneeeeeneees Conventions Used in This Manual ccccesscccccesseseeeees Related Documentation ccccccccesssssecececessatececessnaeeeeeeens Customer Communication c ccccccccsessceccecsessseeecesesseeeeeees Chapter 1 Introduction PXI 8320 OvervieW ciiise tenisie erik i e MXZ Descriptio mn eii e E E E E E What You Need to Get Started sseeeseseeeesseeereerereerereerseres Optional Equ
18. 00 Boe Bae 899999 i trie fi 800000 O o 2 moi Booooe pigs Besese iecisBE 699999 BBB 8880 Ma Bosse A oE gpa D99999 m TT Th jooo000 l cis us o s Gruegoson TIONAL INSTRUMENTS CORP COPYRIGHT 1997 assvigdieaa OL Px1 8320 J m 1 Termination Circuitry 2 Serial Number 3 DRAM 5 Product Name 7 Wi 4 U6 6 Assembly Number Figure 3 1 PXI 8320 Parts Locator Diagram Configuration EEPROM PXI 8320 User Manual The PXI 8320 has an onboard EEPROM which stores default register values that are loaded at power on The EEPROM is divided into two halves a factory configuration half and a user configuration half so you can modify the user configurable half while the factory configured half stores a back up of the default user settings The factory configuration is a minimal configuration that can boot your PXI 8320 regardless of the changes made to the user configuration Use switch 1 FOV of the four position switch at location U6 to control the operation of the EEPROM Switch 1 determines whether the PXI 8320 boots from the factory configured half or the user configurable half In its default setting the PXI 8320 boots from the user configurable half This switch is useful for restoring the user configured half of the EEPROM to the factory configuration values in the event that it becomes corrupted in 3 2 National Instruments Corporation Chapter 3 PXI 8320 Configuration and Installa
19. 1 MXI 2 Connector Signal Assignments Pin a Pin Signal Name Pin Signal Name Pin Signal Name Al AD 31 B1 AD 14 Cl AM 4 D1 BUSY A2 GND B2 GND C2 GND D2 GND A3 AD 30 B3 AD 13 C3 AM 3 D3 IRQ 1 A4 GND B4 GND C4 GND D4 GND AS AD 29 B5 AD 12 c5 AM 2 D5 IRQ 2 A6 GND B6 GND C6 GND D6 GND A7 AD 28 B7 AD 11 C7 AM 1 D7 IRQ 3 National Instruments Corporation B 1 PXI 8320 User Manual Appendix B MXI 2 Connector Table B 1 MXI 2 Connector Signal Assignments Continued Pin ne Pin Signal Name Pin Signal Name Pin Signal Name A8 GND B8 GND C8 GND D8 GND A9 AD 27 B9 AD 10 C9 AM 0 D9 IRQ 4 A10 GND B10 GND C10 GND D10 GND A11 AD 26 B11 AD 9 C11 WR D11 IRQ 5 A12 GND B12 GND C12 GND D12 GND A13 AD 25 B13 AD 8 C13 SIZE D13 IRQ 6 A14 GND B14 GND C14 GND D14 GND A15 AD 24 B15 AD 7 C15 DISBTO D15 IRQ 7 A16 GND B16 GND C16 GND D16 GND A17 AD 23 B17 AD 6 C17 ACFAIL D17 TRG 0 A18 GND B18 GND C18 GND D18 TRG 0 A19 AD 22 B19 AD 5 C19 SYSRESET D19 TRG 1 A20 GND B20 GND C20 GND D20 TRG 1 A21 AD 21 B21 AD 4 C21 SYSFAIL D21 TRG 2 A22 GND B22 GND C22 GND D22 TRG 2 A23 AD 20 B23 AD 3 C23 BERR D23 TRG 3 A24
20. GND B24 GND C24 GND D24 TRG 3 A25 AD 19 B25 AD 2 C25 DTACK D25 TRG 4 A26 GND B26 GND C26 GND D26 TRG 4 A27 AD 18 B27 AD 1 C27 DS D27 TRG 5 A28 GND B28 GND C28 GND D28 TRG 5 A29 AD 17 B28 AD 0 C29 AS D29 TRG 6 A30 GND B30 GND c30 GND D30 TRG 6 A31 AD 16 B31 CONVERT C31 BREQ D31 TRG 7 A32 GND B32 GND C32 GND D32 TRG 7 PXI 8320 User Manual B 2 National Instruments Corporation Appendix B MXI 2 Connector Table B 1 MXI 2 Connector Signal Assignments Continued Signal Pin Name Pin Signal Name Pin Signal Name Pin Signal Name A33 AD 15 B33 PAR C33 GIN D33 CLK10 A34 GND B34 GND C34 GND D34 CLK10 A35 5V B35 TERMPOWER C35 GOUT D35 MXISC A36 5V B36 TERMPOWER C36 GND D36 ENDDEV Table B 2 lists additional characteristics of the MXIbus signals Table B 2 MXIbus Signal Characteristics Signal Voltage Max Frequency Category Range Current Range Each single ended 0 to 3 4 V 60 mA DC to 10 MHz signal Each differential Oto5 V 80 mA DC to 10 MHz signal D17 D34 Each 5 V A35 A36 5 V 1 75 A fused DC Each 3 4 V 1 75 A fused DC TERMPOWER B35 B36 Note The characteristic impedance of all the MXIbus signals is 120 Q National Instruments Corporation B 3 PXI 8320 User M
21. Glossary Electromagnetic Interference An onboard EEPROM that may contain device specific initialization and system boot functionality In this configuration a plug in interface board in a computer is connected to the VXI mainframe via one or more VXIbus extended controllers The computer then exerts overall control over VXIbus system operations A MXIbus master that will not arbitrate for the MXIbus after releasing it until it detects the bus request signal inactive This ensures that all requesting devices will be granted use of the bus Hexadecimal the numbering system with base 16 using the digits 0 to 9 and letters A to F hertz cycles per second Integrated Circuit Institute of Electrical and Electronics Engineers inches A means for a device to request service from another device A VMEbus functional module that detects interrupt requests generated by Interrupters and responds to those requests by requesting status and identify information The relative priority at which a device can interrupt input output the techniques media and devices used to achieve communication between machines and users Interrupt signal PXI 8320 User Manual Glossary KB L LED logical address m master master mode operation MB MBLT message based device MITE MODID MTBF MXI 2 PXI 8320 User Manual Kilobytes of memory Light Emitting Diode An 8 bit number that uniquely identifies each VXIbus dev
22. PCI bus or onboard DRAM SODIMM This address decoder monitors the MXIbus for A16 accesses to the PXI 8320 MXIbus configuration space registers based on the VXIbus logical address of the PXI 8320 A subset of the PXI 8320 registers is accessible in this region National Instruments Corporation e MXIbus Slave State Machine e MXIbus Terminate e MXIbus System Controller Functions MXIbus Bus Timeout Unit National Instruments Corporation 2 5 Chapter 2 Functional Overview This state machine monitors the output of the address decoders and responds to MXIbus cycles intended for the PXI 8320 Cycles that map to the Logical Address decoder access the PXI 8320 registers while cycles that map to the A24 A32 decoder access either the PXI 8320 registers or the onboard DRAM SODIMM The PXI 8320 can accept D32 D16 and DO8 EO single and RMW MXIbus cycles in A32 A24 and A16 space The PXI 8320 can also accept synchronous and block MXIbus cycles in A32 and A24 space The MXIbus slave state machine checks for MXIbus parity errors If it detects a parity error during the address phase of a cycle the PXI 8320 ignores the cycle If it detects a parity error during the data phase of a write cycle the MXIbus slave state machine responds with a BERR on the MXIbus The transceivers ensure that the PXI 8320 meets the loading driving and timing requirements of the MXIbus specification for the AD 31 0 AM 4 0 and CONVERT s
23. PXI PXI 8320 User Manual instruments December 1997 Edition is the Instrument Part Number 321717A 01 Internet Support E mail support natinst com FTP Site ftp natinst com Web Address http www natinst com Bulletin Board Support BBS United States 512 794 5422 BBS United Kingdom 01635 551422 BBS France 01 48 65 15 59 Fax on Demand Support 512 418 1111 Telephone Support USA Tel 512 795 8248 Fax 512 794 5678 International Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 288 3336 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin Texas 78730 5039 USA Tel 512 794 0100 Copyright 1997 National Instruments Corporation All rights reserved Important Information Warranty Copyright Trademarks The PXI 8320 is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at it
24. PXI 8320 User Manual vi National Instruments Corporation About This Manual The PXI 8320 User Manual describes the functional physical and electrical aspects of the PXI 8320 and contains information concerning its operation and programming Organization of This Manual The PXI 8320 User Manual is organized as follows Chapter 1 Introduction describes the PXI 8320 lists the contents of your PXI 8320 kit lists optional equipment and software and introduces the concepts of MXI 2 Chapter 2 Functional Overview contains functional descriptions of each major logic block on the PXI 8320 Chapter 3 PXI 8320 Configuration and Installation contains the instructions to configure and install the PXI 8320 module Appendix A Specifications lists various module specifications of the PXI 8320 such as physical dimensions and power requirements Appendix B MXI 2 Connector describes the MXI 2 connector on the PXI 8320 module Appendix C Customer Communication contains forms you can use to request help from National Instruments or to comment on our products and manuals The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes and symbols The ndex contains an alphabetical list of key terms and topics in this manual including the page where you can find each one Conventions Used in This Manual The following conventions are used
25. YEEEETTEEETN oPPoPoPo OPoPoPaPoPaPo oPo OPoPo o O20 2000 000700000000000 0 g 9090590904900940 Oo _ jooooooooon oNeNoXoXeXeNeXoXe oXeXeNeXeXeXoXoKelis 200000000 pooco ODO CMYSOOOOOOOOD i 0000000000 0000000000 0000000000 0000000001 008 oO i 3862 3862 3862 l 3862 p 3862 2 t400 a N 7 A03 SINAWNNISNI TWNOILY 2 Rri 000000000 C0000000 000o oE o tO ll 0000000 ooooooon ooooooog ooooooog 00ooooog E SI a Ri gt 3662 3662 p 3662 p 3662 p 3662 Hiig Y z noooooooos ooooo0000 ooooo000 cfooooo00n 000000001 g Egitto Soodoootfooo000 o00000 000000050000000 ESR i mpoooo0ooDTy O 2 o mmm M ae on Se g 0 BBE Z a Re me 1 W1 2 Termination Circuitry Figure 3 3 Terminating Resistors and Jumper W1 3 4 National Instruments Corporation Chapter 3 PXI 8320 Configuration and Installation Install the PXI 8320 This section contains general installation instructions for the PXI 8320 Consult your computer user manual or technical reference manual for specific instructions and warnings 1 Plug in your PXI or CompactPCI chassis before installing the PXI 8320 The power cord grounds the chassis and protects it from electrical damage while you install the module Ip Warning To protect both yourself and the computer from electrical hazards leave the chassis off until you finish i
26. acteristic Specification PCI Initiator Master Capability Supported PCI Target Slave Capability Supported Data Path 32 bits Card Voltage Type 5 V only 32 bit 3U size card Parity Generation Checking Error Reporting Supported Target Decode Speed Medium 1 clock Target Fast Back to Back Capability Supported Resource Locking Supported as a master and slave PCI Interrupts Interrupts passed on INTA signal Base Address Registers BAR 0 dedicated to local registers BAR 1 3 size configurable from 256 B to 4 GB Expansion ROM 8 KB PCI Master Performance Ideal Maximum 132 MB s 16 Dwords max PCI Slave Performance Ideal Maximum 33 MB s to local registers PXI 8320 User Manual Characteristic Specification Memory Space 32 KB minimum programmable A 2 National Instruments Corporation Environmental Appendix A Specifications Characteristic Specification Temperature 0 to 55 C operating 40 to 85 C storage Relative Humidity 0 to 95 noncondensing operating 0 to 95 noncondensing storage EMI FCC Class A Verified Physical Characteristic Specification Board Dimensions 160 by 100 mm 6 3 by 3 94 in Connectors Single fully implemented MXI 2 connector Slot Requirements Single CompactPCI PXI Peripheral Slot
27. am American National Standards Institute A process in which a potential bus master gains control over a particular bus Not synchronized not controlled by time signals bytes An assembly typically a printed circuit board with 96 pin connectors and signal paths that bus the connector pins A C size VXIbus system will have two sets of bused connectors called J1 and J2 A D size VXIbus system will have three sets of bused connectors called J1 J2 and J3 Bus error signal A numbering system with a base of 2 Basic Input Output System BIOS functions are the fundamental level of any PC or compatible computer BIOS functions embody the basic operations needed for successful use of the computer s hardware resources G 2 National Instruments Corporation block mode transfer BTO unit bus master CLK10 CMOS Commander CompactPCI configuration registers Glossary An uninterrupted transfer of data elements in which the master sources only the first address at the beginning of the cycle The slave is then responsible for incrementing the address on subsequent transfers so that the next element is transferred to or from the proper storage location In VME the data transfer may have no more than 256 elements MXI does not have this restriction Bus Timeout Unit a functional module that times the duration of each data transfer and terminates the cycle if the duration is excessive Without the termination capabilit
28. anual Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a fax on demand system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794
29. ation of the PCI bus onboard DRAM or MXIbus PXI 8320 User Manual Chapter 2 Functional Overview e MXIbus Parity Check and Generation Onboard DRAM SODIMM e PXI 8320 Registers e A24 A32 Decoder e Logical Address Decoder PXI 8320 User Manual The MXIbus parity check generation circuitry checks for even parity anytime the PXI 8320 is receiving the AD 3 1 0 signals If parity is not even the circuitry signals the appropriate MXIbus state machine The MXIbus master state machine is signaled for a parity error during the data phase of a MXIbus master read cycle while the MXIbus slave state machine is signaled for a parity error during the address phase of any MXIbus slave cycle and the data phase of a MXIbus slave write cycle Even parity is also generated and sent to the MXIbus with master address and write data as well as slave read data This logic block represents the DRAM SODIMM socket on the PXI 8320 If DRAM is installed it is accessible in the PXI 8320 A24 A32 memory space This logic block represents all registers on the PXI 8320 Both the PCI bus and MXIbus can access the registers All registers are available from the PCI bus while a subset is accessible in the PXI 8320 MXIbus A16 configuration area This address decoder monitors the MXIbus for access to the PXI 8320 A24 A32 memory space All resources located on the PXI 8320 are accessible in this region The decoded region can be routed to the
30. d Installation This chapter contains the instructions to configure and install the PXI 8320 module hp Warning Electrostatic discharge can damage several components on your PXI 8320 module To avoid such damage in handling the module touch the antistatic plastic package to a metal part of your chassis before removing the PXI 8320 from the package Configure the PXI 8320 This section describes how to configure the following options on the PXI 8320 e Configuration EEPROM e Onboard DRAM e 8320 termination Figure 3 1 shows the PXI 8320 The drawing shows the location and factory default settings on the module National Instruments Corporation 3 1 PXI 8320 User Manual Chapter 3 PXI 8320 Configuration and Installation D000 0 8 OO Ra Ore ra ma 0 aa x og tovodo000000 is aI ng gt CY7B9910 ee Sooongonp00 a o Ci g RD foi 2 0 css Bit it iong nee See c oo pa oe 900004 K FOV TS P sz mi 0000001 3662 RRR ROR ET 0 07676 7770 0 6 6757575770 0 20202020202020202020209020202020 PoP PoPoPaPoPoPoPoMoPoPoPoPoPeo ERERSRSRSROKR RONEN iooooooooon KXAN NALS CKLKLA LAN 5 5 00000 Bescce 699999 progg 689999 fees B99999 Beresescs EO EE casos 5000 l 0000
31. e of video board installed Operating system version Operating system mode Other MXIbus devices in system Other VXIbus devices in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards VXIbus MXIbus Resource Manager make model version software version Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title PXI 8320 User Manual Edition Date December 1997 Part Number 321717A 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address E Mail Address Phone Fax Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin Texas 78730 5039 Glossary Prefix Meanings Value n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 Symbols a degrees Q ohms percent A A amperes A16 space VXIbus address space equivalent to the VME 64 KB short address space In VXI
32. ecification Version 2 0 available from National Instruments Corporation e VXI 6 VXIbus Mainframe Extender Specification Rev 1 0 VXIbus Consortium Customer Communication PXI 8320 User Manual National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix C Customer Communication at the end of this manual viii National Instruments Corporation Introduction This chapter describes the PXI 8320 lists the contents of your PXI 8320 kit lists optional equipment and software and introduces the concepts of MXI 2 PXI 8320 Overview The PXI 8320 is a 32 bit 3U style CompactPCI compatible plug in circuit board that plugs into one of the peripheral slots of your PXI or CompactPCI chassis It links your PXI CompactPCI based computer directly to the MXlIbus and vice versa Because the PXI 8320 uses the same communication register set that other VXIbus message based devices use other MXIbus devices view the PXI 8320 as a VXIbus device The PXI 8320 can also function as the MXIbus System Controller and can terminate the MXIbus signals directly on the PXI 8320 In addition you can install up to 16 MB of onboard DRAM on the PXI 8320 that the board can eit
33. em reset or power up condition G 8 National Instruments Corporation System RAM T trigger TTL U user window V v VDC VIC or VICtext VME VMEbus System Controller VXIbus National Instruments Corporation G 9 Glossary RAM installed on your personal computer and used by the operating system as contrasted with onboard RAM which is installed on the PXI 8320 Either TTL or ECL lines used for intermodule communication Transistor Transistor Logic A region of PCI address space reserved by the PXI 8320 for use via the NI VXI low level function calls MapVxIAddress uses this address space to allocate regions for use by the vXIpeek and VXIpoke macros volts volts direct current VXI Interactive Control Program a part of the NI VXI bus interface software package Used to program VXI devices and develop and debug VXI application programs Versa Module Eurocard or IEEE 1014 A device configured for installation in Slot 0 of a VXIbus mainframe or Slot 1 of a VMEbus chassis This device is unique in the VMEbus system in that it performs the VMEbus System Controller functions including clock sourcing and arbitration for data transfers across the backplane Installing such a device into any other slot can damage the device the VMEbus V XIbus backplane or both VMEbus Extensions for Instrumentation PXI 8320 User Manual Glossary VXledit or VXItedit VXiinit W Word Serial Protocol
34. f the National Instruments MXIbus product line The MXIbus is a general purpose 32 bit multimaster system bus on a cable MXI 2 expands the number of signals on a standard MXI cable by including VXI triggers all VXI interrupts CLK10 and all of the utility bus signals SYSFAIL SYSRESET and ACFAIL Because MXI 2 incorporates all of these new signals into a single connector you can extend the triggers interrupts and utility signals not only to other mainframes but also to the local CPU in all MXI 2 products using a single cable Thus with the MXI 2 CPU interface boards such as the PXI 8320 perform as though they were plugged directly into the VXI VME backplane In addition MXI 2 surpasses the data throughput of previous generation MXIbus products by defining new high performance protocols MXI 2 is a superset of MXI All accesses initiated by MXIbus devices work with MXI 2 devices However MXI 2 defines synchronous MXI block data transfers that surpass previous block data throughput benchmarks The new synchronous MXI block protocol increases MXI 2 throughput to a maximum of 33 MB s between two MXI 2 devices All National Instruments MXI 2 boards can initiate and respond to synchronous MXI block cycles i Note In the remainder of this manual the term MXIbus refers to MXI 2 PXI 8320 User Manual 1 2 National Instruments Corporation Chapter 1 Introduction What You Need to Get Started Q PXI or CompactPCI chassis
35. h 1 FOV on U6 to the OFF position 10 Replace the PXI 8320 11 Turn on the chassis If the computer does not boot with this configuration you will have to repeat these steps modifying your configuration until a final configuration is reached PXI 8320 User Manual 3 6 National Instruments Corporation Specifications This appendix lists various module specifications of the PXI 8320 such as physical dimensions and power requirements MXIbus Capability Descriptions e Master mode A32 A24 and A16 addressing e Master mode block transfers and synchronous block transfers e Slave mode A32 A24 and A16 addressing e Slave mode block transfers and synchronous block transfers e Master mode D32 D16 and DO8 data sizes e Slave mode D32 D16 and DO8 data sizes e Optional MXIbus System Controller e Can be a fair MXIbus requester e Can lock the MXIbus for indivisible transfers e Can terminate the MXIbus e MXIbus master retry support e MX Ibus slave retry support e Interrupt handler for levels 7 to 1 e Interrupt requester for levels 7 to 1 e MXIbus D32 D16 DO8 O interrupt handler e MXIbus D32 D16 DO8 O interrupter e Release on Acknowledge or Register Access interrupter e MXIbus bus timer programmable limit e Automatic MXIbus System Controller detection National Instruments Corporation A 1 PXI 8320 User Manual Appendix A Specifications PCI Functionality Requirements Char
36. her share with the MXIbus and VXI VMEbus or use as a dedicated data buffer The PXI 8320 achieves high performance block transfer rates by integrating the MITE custom ASIC a sophisticated dual channel DMA controller with standard interfaces for VXI VME MXI and PCI By using MITE DMA to transfer data and commands to and from devices the MITE frees up a computer s microprocessor to perform other tasks such as data analysis and presentation In addition to DMA the MITE incorporates both the new Synchronous MXI protocol and VME64 MBLT 8 byte block transfers in which both the address bus and data bus are used to transfer data directly into the ASIC to perform the fastest transfer operation to instruments The PXI 8320 has the following features e Interfaces the PXI CompactPCI bus to the MXIbus 32 bit Multisystem eXtension Interface bus e Supports D64 block and synchronous MXI cycles for high performance data transfer National Instruments Corporation 1 1 PXI 8320 User Manual Chapter 1 Introduction e Directly controls MXIbus interrupt levels utility signals TTL triggers and CLK10 e Allows for optional or user installable onboard DRAM up to 16 MB which can be shared with the MXIbus e Conforms to CompactPCI Specification Revision 2 0 PXI Specification e Conforms to Multisystem Extension Interface Bus Specification Version 2 0 e Supports MXIbus termination MXI 2 Description MXI 2 is the second generation o
37. ice in a system It defines the A16 register address of a device and indicates Commander and Servant relationships meters A functional part of a MXI VME V XIbus device that initiates data transfers on the backplane A transfer can be either a read or a write A device is in master mode if it is performing a bus cycle which it initiated Megabytes of memory Eight byte block transfers in which both the Address bus and the Data bus are used to transfer data An intelligent device that implements the defined VXIbus registers and communication protocols These devices are able to use Word Serial Protocol to communicate with one another through communication registers A National Instruments custom ASIC a sophisticated dual channel DMA controller that incorporates the Synchronous MXI and VME64 protocols to achieve high performance block transfer rates Module Identification lines Mean Time Between Failure The second generation of the National Instruments MXIbus product line MXI 2 expands the number of signals on a standard MXIbus cable by including VXI triggers all VXI interrupts CLK10 SYSFAIL SYSRESET and ACFAIL G 6 National Instruments Corporation MXIbus MXIbus System Controller NI VXI Non Slot 0 device 0 Onboard RAM P PCI propagation PXI R register based device RESMAN National Instruments Corporation G 7 Glossary Multisystem eXtension Interface Bus a high performance com
38. ignals The PXI 8320 has onboard MXIbus termination to terminate the MXIbus signals if it is at either end of the cable If the PXI 8320 is a middle device on the MXIbus disable the termination The PXI 8320 can act as the MXIbus system controller When acting as the system controller the PXI 8320 provides the MXIbus arbiter priority selection daisy chain driver and bus timeout unit The PXI 8320 automatically detects from the MXIbus cable whether it is the system controller The PXI 8320 has a MXIbus bus timeout unit which terminates with BERR any MXIbus cycle in which DTACK or BERR are not asserted in a prescribed amount of time after DS is asserted The duration of the timeout is programmably selectable in the range of 30 us to 500 ms PXI 8320 User Manual Chapter 2 Functional Overview PXI 8320 User Manual e Interrupt Trigger and Utility Signal Circuitry 2 6 This circuitry handles mapping of the interrupt trigger and utility signals to the MXIbus The utility signals include SYSRESET SYSFAIL and ACFAIL This circuitry also generates interrupts from other conditions on the PXI 8320 and allows generation of the trigger or utility signals The transceivers ensure that the PXI 8320 meets the loading driving and timing requirements of the MXIbus specification for the IRQ 7 1 TRIG 7 0 SYSRESET SYSFAIL and ACFAIL signals National Instruments Corporation PXI 8320 Configuration an
39. ipment eee eee cseeseecreesaeceecnseeeeeeeeeees Optional Software 0 eee cece eeeeeseeceeceeeseceseesecneeeseeeeeeeeees Chapter 2 Functional Overview PXI 8320 Functional Description eee eseeee ete eneees Chapter 3 PXI 8320 Configuration and Installation Configure the PXIS3 20v Configuration EEPROM 00 0 eeeeeeceeeeees Onboard DRAM vrsio p espenh MXIbus Termination Option eee eects Install the PXI 832 0hari Fixing an Invalid EEPROM Configuration 00 0 Appendix A Specifications Appendix B MXI 2 Connector Appendix C Customer Communication National Instruments Corporation v PXI 8320 User Manual Contents Glossary Index Figures Figure 2 1 PXI 8320 Block Diagram 00 oe eeeeeeceeeecceseeeeeeseecneceeesecnseeeseeeeeeees 2 2 Figure 3 1 PXI 8320 Parts Locator Diagram 0 eee eee eeesee ce ceee cee ceseeeeeseeseees 3 2 Figure 3 2 EEPROM Operation eneee ieser eroi E Eas 3 3 Figure 3 3 Terminating Resistors and Jumper W1 sssseessseessessreessreerrsreresreersreereees 3 4 Figure 3 4 Restoring the Factory Configuration eee ee cee eesceeeeeeeseeeeeeneeene 3 6 Figure B l MXT 2 Connector sesiet ri erie rrp EEEn shee B 1 Tables Table 3 1 PXI 8320 DRAM Configurations seseesesseeeseseeresrerrsreerrressrrresererseeeesee 3 3 Table B 1 MXI 2 Connector Signal Assignments esseeeseseeeeseserrrrseereserserersere B 1 Table B 2 MXIbus Signal Characteristics
40. munication link that interconnects devices using round flexible cables A functional module that has arbiter daisy chain driver and MXIbus cycle timeout responsibility Always the first device in the MXIbus daisy chain The National Instruments bus interface software for VME V XIbus systems A device configured for installation in any slot in a VXIbus mainframe other than Slot 0 Installing such a device into Slot 0 can damage the device the VXIbus backplane or both The optional RAM installed into the SIMM slots of the PXI 8320 board Peripheral Component Interconnect The PCI bus is a high performance 32 bit or 64 bit bus with multiplexed address and data lines The transmission of signal through a computer system PCI Extensions for Instrumentation A Servant only device that supports VXIbus configuration registers Register based devices are typically controlled by message based devices via device dependent register reads and writes The name of the National Instruments Resource Manager in NI VXI bus interface software See Resource Manager PXI 8320 User Manual Glossary Resource Manager retry S S Servant Shared Memory Protocol slave slave mode operation Slot 0 device SODIMM statically configured device SYSFAIL SYSRESET PXI 8320 User Manual A message based Commander located at Logical Address 0 which provides configuration management services such as address map configuration
41. nal pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse ___ yes __no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products PXI 8320 module part number Serial number Revision number MXIbus terminators and W1 jumper installed or removed EEPROM operation U6 switches 1 and 2 DRAM SIMMs installed National Instruments software Other Products Computer make and model Mainframe make and model Microprocessor Clock frequency or speed Typ
42. not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation CVI LabVIEW MITE NI VXI and PXI are trademarks of National Instruments Corporation Product and company names listed are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or
43. nstalling the PXI 8320 module 2 Select any available PXI or CompactPCI peripheral slot 3 Locate the metal bracket that covers the slot of the chassis that you have selected Remove and save the bracket retaining screw and the bracket cover 4 Touch the metal part of the case to discharge any static electricity that might be on your clothes or body 5 Line up the PXI 8320 with the card guides on the slot of the PXI CompactPCI peripheral slot Press down on the PXI 8320 until it seats in the chassis 6 Screw in bracket retaining screws to secure the PXI 8320 to the chassis 7 Check the installation Fixing an Invalid EEPROM Configuration VXIedit is the software configuration utility in the NI VXI software You can use this utility to edit the configuration of the PXI 8320 Some of these settings are stored in files that are read by the NI VXI software while other settings are stored directly in the PXI 8320 EEPROM Certain EEPROM configurations can cause your PXI CompactPCI computer to lock up while in its boot process Generally only the size and location of the memory windows can cause problems with the PXI 8320 locking up your system For example many PCI based computers will not boot if a board in the system requests more memory space than the computer can allocate If you encounter this situation reduce the size of the PXI 8320 user window National Instruments Corporation 3 5 PXI 8320 User Manual Chapter 3 PXI
44. or any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Under the copyright laws this publication may
45. ou order the LabVIEW VXI Development System for Windows or the 1 4 National Instruments Corporation Chapter 1 Introduction LabWindows CVI VXI Development System for Windows you also get more than 500 complete instrument drivers which are modular source code programs that handle the communication with your instrument to speed your application development National Instruments Corporation 1 5 PXI 8320 User Manual Functional Overview This chapter contains functional descriptions of each major logic block on the PXI 8320 PXI 8320 Functional Description In the simplest terms you can think of the PXI 8320 as a bus translator that converts PCI bus signals into appropriate MXIbus signals From the perspective of the MXIbus the PXI 8320 implements a MXIbus interface to communicate with other MXIbus devices From the perspective of the PCI bus the PXI 8320 is an interface to the outside world Figure 2 1 is a functional block diagram of the PXI 8320 Following the diagram is a description of each logic block shown National Instruments Corporation 2 1 PXI 8320 User Manual Chapter 2 PXI CompactPCl Bus Functional Overview PCI Bus Slave State Machine Base Address Registers PCI Bus Master State Machine Onboard DRAM SIMM Programmable Outward Windows MXIbus Master State Machine i MXIbus Parity Check and Generation
46. s option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable f
47. state machine 2 2 MXI 2 description 1 2 parity check and generation 2 4 slave state machine 2 5 System Controller functions 2 5 termination option 2 5 3 4 timeout unit 2 5 NI VXI bus interface software 1 4 0 onboard DRAM configuration table 3 3 SODIMM socket 2 4 PXI 8320 User Manual l 2 P parity check and generation MXIbus 2 4 parts locator diagram 3 2 PCI bus master state machine 2 3 PCI bus slave state machine 2 2 PCI functionality specifications table A 2 performance specifications A 3 physical specifications A 3 pinout assignments MXI 2 connector figure B 1 programmable outward windows 2 3 PXI 8320 features 1 1 to 1 2 functional overview 2 1 to 2 to 2 6 A24 A32 decoder 2 4 base address registers 2 2 block diagram 2 2 DMA controllers 2 3 interrupt trigger and utility signal circuitry 2 6 logical address decoder 2 4 MXlIbus master state machine 2 3 MXIbus parity check and generation 2 4 MxX Ibus slave state machine 2 5 MXIbus System Controller functions 2 5 MxXiIbus terminate 2 5 MXiIbus timeout unit 2 5 onboard DRAM SODIMM 2 4 PCI bus master state machine 2 3 PCI bus slave state machine 2 2 programmable outward windows 2 3 registers 2 4 optional equipment 1 3 to 1 4 optional software 1 4 to 1 5 overview l 1 to 1 2 requirements for getting started 1 2 National Instruments Corporation R registers base address registers 2 2 for PXI 8320 2 4 S
48. the upper 16 KB of A16 space is allocated for use by VXI devices configuration registers This 16 KB region is referred to as VXI configuration space A24 space VXIbus address space equivalent to the VME 16 MB standard address space A32 space VXIbus address space equivalent to the VME 4 GB extended address space ACFAIL A VMEbus backplane signal that is asserted when a power failure has occurred either AC line source or power supply malfunction or if it is necessary to disable the power supply such as for a high temperature condition National Instruments Corporation G 1 PXI 8320 User Manual Glossary address address modifier address space address window ANSI arbitration asynchronous B B backplane BERR binary BIOS PXI 8320 User Manual Character code that identifies a specific location or series of locations in memory One of six signals in the VMEbus specification used by VMEbus masters to indicate the address space in which a data transfer is to take place A set of 2 memory locations differentiated from other such sets in VXI VMEbus systems by six addressing lines known as address modifiers nis the number of address lines required to uniquely specify a byte location in a given space Valid numbers for n are 16 24 and 32 In VME VXI because there are six address modifiers there are 64 possible address spaces A portion of address space that can be accessed from the application progr
49. tion such a way that the PXI 8320 boots to an unusable state See Fixing an Invalid EEPROM Configuration later in this chapter for more details on using switch 1 The TST switch switch 2 of U6 lets you change the default factory configuration settings by permitting writes to the factory settings section of the EEPROM This switch serves as a safety measure and should not be needed under normal circumstances When this switch is off its default setting the factory configuration of the EEPROM is protected so any writes to the factory area will be ignored The factory area is protected regardless of the setting of switch 1 of U6 Figure 3 2 shows the default configuration settings for EEPROM operation J Caution Do not alter the settings of switches 3 and 4 of U6 Leave these switches as shown in Figure 3 2 unless specifically directed by National Instruments Onboard DRAM FOV O N Zz POS J gt 5 cr ZY Figure 3 2 EEPROM Operation The PXI 8320 can accommodate one DRAM SODIMM Table 3 1 lists the SODIMM s you can use The PXI 8320 can hold up to 16 MB of onboard memory The PXI 8320 supports DRAM speeds of 80 ns or faster Table 3 1 PXI 8320 DRAM Configurations National Instruments SODIMM Total DRAM Option 0 1M x 32 4 MB YES 4M x 32 16 MB YES National Instruments Corporation 3 3 PXI 8320 User Manual Chapter 3 PXI 8320 Configuration and Installation
50. y of this module a bus master attempt to access a nonexistent slave could result in an indefinitely long wait for a slave response A device that is capable of requesting the Data Transfer Bus DTB for the purpose of accessing a slave device Celsius A 10 MHz 100 ppm individually buffered to each module slot differential ECL system clock that is sourced from Slot 0 of a VXIbus mainframe and distributed to Slots 1 through 12 on P2 It is distributed to each slot as a single source single destination signal with a matched delay of under 8 ns Complementary Metal Oxide Semiconductor a process used in making chips A message based device which is also a bus master and can control one or more Servants A set of registers through which the system can identify a module device type model manufacturer address space and memory requirements In order to support automatic system and memory configuration the VXIbus specification requires that all VXIbus devices have a set of such registers National Instruments Corporation G 3 PXI 8320 User Manual Glossary D daisy chain Data Transfer Bus DIP DMA DRAM driver window DTACK DTB dynamic configuration dynamically configured device E ECL EEPROM embedded controller EMC PXI 8320 User Manual A method of propagating signals along a bus in which the devices are prioritized on the basis of their position on the bus DTB one of four buses on the
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