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TP3420A S Interface Device (SID) User`s Guide

1. 010730 72 FIGURE 29 Local Activation Subroutine 6 4 TP3420A Internal F State Machine Diagram Figure 30 is the internal F State Machine in the TP3420A when the device is programmed to be in TEM or TES mode Each box corresponds to an equivalent of an 1 430 F state F1 to F8 There is an extra internal state F2 1 not to be found in 1 430 states This is the Low Power mode Most of the state transitions take 250 us and are sented by the thin lines The other three transitions take 2 ms and represented by the thick lines A specified stimulus that causes a state jump is written in the transition line before the or by itself The returned status is written after the slash Not every transition has a returned status 31 www national com F1 Power Power Off 000 Inactive Up PUP IO amp AR DR DI F4 Awaiting 011 Sending INFO1 12 14 or DR DI 14 Al FS Identifying 100 Sending INFOO 10 DR DI 14 Al F6 Synchronized 101 Sending INFO3 7 0 NETWORK TERMINATION SOFTWARE DRIVER CONSIDERATIONS Topics are covered as the following NT G States The 1 430 Activation Deactivation Requirements for NT Suggested flowchart to implement X Activation Deactivation procedure for NT TP3420A Internal State Machine 7 1 The G States The States are defined in CCITT reco
2. B2D BEX LINE INTERFACE 1 0 BDIR BIE BEX CLOSED IF D TX SLOT CLOSED IF B2 TX SLOT B2E BDIR 820 Internal Control Signals B1 Tx Rx Slot B2 Tx Rx Slot Referenced to 1 430 line interface Lo Li time slot D Tx Rx Slot B1 Slot B2 Slot Referenced Digital System Interface Bx Br time slot D Slot Note For NT TES modes FSa and FSb inputs have to be same phase Note No B CH data loopback from Bx to Br External Command Status LBB1 Loopback B1 towards system interface if LBB1 1 LBB2 Loopback B2 towards system interface if LBB2 1 CAL Clear all loopbacks BDIR B CH mapped direct B1 to B1 B2 to B2 BEX B CH exchanged B1 to B2 B2 to B1 B1E B1 CH enabled B2E CH enabled B1D B1 CH disabled B2D B2 CH disabled Al Activation Indication LBB1 0 CLOSED IF D SLOT 2 0 9 CLOSED IF D SLOT CLOSED IF B1 SLOT CLOSEB IF B2 SLOT CLOSED IF B1 SLOT CLOSED IF B2 SLOT 1881 1 LBB2 1 SYSTEM INTERFACE 1 0 CLOSED IF Al 0 B1 SLOT Al 1 CLOSED IF B2 SLOT 010730 57 FIGURE 39 TP3420A System Loopback Function Diagram LBB1 LBB2 8 4 Line Loopack Mode LBL1 LBL2 LBL1 and LBL2 commands are used independently to select line loopback mode as shown in the function diagram of Fig ure 40 when B1 and or B2 are to be looped back to the line interface from Li to Lo while at the same time B1 B2 and D data to the system interface
3. 1 SLOT Lo CLOSED IF D TX SLOT CLOSED IF D SLOT CLOSED IF CLOSED IF B2 TX SLOT B2 SLOT Internal Control Signals B1 Tx Rx Slot B2 Tx Rx Slot Referenced to 1 430 Line Interface Lo Li time slot D Tx Rx Slot 1 Slot B2 Slot Referenced to Digital System Interface Bx Br time slot D Slot External Command Status BDIR B CH mapped direct B1 to B1 B2 to B2 BCX B CH exchanged B1 to B2 B2 to B1 B1C B1 CH enabled B2C B2 CH enabled B1D B1 CH disabled B2D B2 CH disabled Al Activation Indication o B2D BEX FIGURE 37 Normal Data Paths Diagram No Loopbacks Al 1 SYSTEM INTERFACE 1 0 2x AN010730 55 39 www national com BDIR BIE CLOSED IF B1 RX SLOT Li CLOSED IF D RX SLOT CLOSED IF B2 RX SLOT BDIR LINE INTERFACE 1 0 BIE CLOSED IF B1 TX SLOT Lo CLOSED IF D TX SLOT CLOSED IF B2 TX SLOT Le Internal Control Signals B1 Tx Rx Slot B2 Tx Rx Slot Referenced to 1 430 line interface Lo Li time slot D Tx Rx Slot 1 Slot B2 Slot Referenced to Digital System Interface Bx Br time slot D Slot Note For NT TES modes FSa and FSb inputs have to be same phase External MICROWIRE Command Status LBS Loopback 2B D towards system interface CAL Clear all loopbacks BDIR B CH mapped direct B1 to B1 B2 to B2 BEX B CH exchanged B1 to B2 B2 to B1 B1E B1 CH enabled B2E B2 CH enabled B1D B1 CH disabled B2D B2 CH disabled A
4. p 910N 39V J831NI 4 KE 4 ALON cOLBION 30079 3300230 35 XL Il 1810 53 ddog AS JO LEHO ed 6 10 9 ownd 2 e1oN k 310N Al 310N 91024 ALY ILON LS vS0 dl 19 ALY po A AS DSI in this application Besides the voice channel should al The diagram of Figure 14 shows the connection between the ways be in B1 slot of the DIF FORMAT1 for this setup to work If the network assigns the B2 channel to a voice call it TP3420A and TP3076 in the implementation of an ISDN phone TP3420A SID is programmed for DIF1 format at the 14 www national com has to be switched into the B1 slot in the DSI frame format using the command BEX in the TP3420A control register The FSx FSr pins on the TP3076 are connected to the Fs pin on the TP3420A MCLK BCLK on the TP3076 are nected to BCLK on the TP3420A and Dx DR signals on the TP3076 are connected to Bx and Br signals respectively on the TP3420A SID Under these conditions and assuming p law is chosen for proper operation the control register on the TP3076 is programmed as follows TP3076 Control Register Contents L 9 9 ER 0 In this case the TP3076 is non delayed timing and the time slot always begins with the leading edge of frame sync input FSx F
5. uy anal ais 9 seioN 4 lt 0OJNI Z EL L4 OH 0O3NI P II HdW O3NI L3 P II HdW JIG HdW P II HdW 0O3NI Sd JIG HdW P II HdW 74 21 15 Ld P ll HdIN 0O3NI 1senbed 19v Hd L S Jo eouegeeddesiq 2 S 10 uonoeijeq pue uo 195 OdNI 24 91 15 84 1507 payeanoy IV ais peziuoiyouAS dV ais yndu jeuBis peieAnoeag 9181S 108 015 Buisues AWIS sniels pue SJL 104 XIE 215 9 318VL 26 www national com NOTATIONS SID command 8 bit command sent to the TP3420A These command can be found in the TP3420A Data Sheet SID interrupt Internal interrupt of the TP3420A They can be found in the TP3420A Data Sheet EE No change no action Impossible by the definition of layer 1 service ss P Impossible situation a b Fn Issue pri
6. Power Up Power Down Low Power Mode AR near end 61 000 Deactivated Sending INFOO 11 far end G1 1 001 INFO1 Received Sending INFOO 61 2 010 Awaiting INFO3 Sending INFO2 G2 1 011 Pending Activation Sending INFO2 I3 amp AR AI 65 111 Activated Sending INF04 AN010730 79 FIGURE 35 Internal G State Machine Diagram www national com 36 Process SID Activation Flags and respond Reset AP Flag Reset Al Flag PDN Reset DI Flag Reset El Flag Filtering False LSD PUP AR ST T1 RS t Reset LSD_FILTERED Flag ST Aen Set LSD_FILTERED Flag isp Reset LSD_FILTERED Fla Expired 9 tinro4 Expired AR No RS Reset Timer ST Start Timer 010730 78 FIGURE 36 Main Task for the Software Driver 37 www national com 8 0 SID TEST LOOPBACK MODES The TP3420 and TP3421 provide three classes of loopback modes namely Full 2B D loopback at the system interface LBS Individual B channel loopback at the line interface LBL1 LBL2 Individual channel loopback at the system interface 1 LBB2 These loopbacks may be activated via MICROWIRE com mands into TP3420 or Monitor Channel commands in the TP3421 Using the loopback modes provided in the device various system loopbacks recommended in the CCITT 1 430 may be implemented In order to use SID loopback modes effectively in implement ing t
7. FIGURE 12 Digital System Interface Formats Mode 11 www national com Figure 11 illustrates the four Digital Interface Formats for the NT and TES modes of the SID device and Figure 12 show these formats for the TEM mode Table 2 presents the BCLK rates of the four DIF formats in both the Master and Slave modes TABLE 2 DSI Format Rates BCLK as BCLK as DSI Master DSI Slave 2 048 MHz 2 56 kHz 4 096 MHz 256 kHz Format 512 kHz 2 56 MHz 3 2 TP3420A SID Digital System Interface and HPC16400E Connection TP3420A SID can be used with a number of popular HDLC devices These are MC68302 MC145488 Zilog AMD 85C30 NSC HPC16400E please see TP3420A data sheet and AN 931 Interconnecting NSC TP3420A SID to Motorola SCP HDLC devices for more information TP3420A SID when used with National s 16400 Mi crocontroller provides an elegant ISDN solution for TE and Line card architectures While the SID implements all the S interface functions Layer 2 and 3 signaling and protocol layer procedures may be implemented in the HPC16400E by connecting the D channel to HDLC7 via the Digital System Interface At the same time one of the B channels may be routed to HDLC 2 on the HPC16400E for data protocol implementations The Serial Decoder block of the HPC16400E provides a means of flexible configuration of the device for various ap plications Figure 3 illustrates a simple block diagram func tional descr
8. Li to Br may be allowed Also at the same time B2 or B1 and D channel data may be allowed from the system interface to the line interface Bx to Lo Of course once again the transfers across the inter faces are conditional upon Al 1 and the appropriate chan nels being enabled For example when LBL1 is chosen the B1 channel from the line interface is looped back Notice at the same time B1 B2 and D channels are transferred to the Br pin of the system in terface and also B2 and D channels from the system inter face are transferred to the Lo pin of the line interface Figure 41 illustrates the simplified loopback functions that the device can be configured into 41 www national com B1D BDIR 07 CLOSED IF B1 RX SLOT CLOSED IF ARO B1 SLOT Br 1 Li CLOSED IF D RX SLOT CLOSED IF D SLOT CLOSED IF CLOSED IF B2 RX SLOT B2 SLOT LBL1 LBL2 9 n LBL1 0 LBL2 0 820 79 xs BEX LBL2 1 amp CLOSED IF CLOSED IF amp 82 SLOT 82 SLOT oi LBL1 1 o o KERE CLOSED IF B1 TX SLOT CLOSED IF B1 SLOT o 7 op A 2 Lo CLOSED IF D TX SLOT CLOSED IF D SLOT CLOSED IF B2 SLOT CLOSED IF B2 TX SLOT LBL2 0 9 B2E LBL2 1 B2D BEX Internal Control Signals B1 Tx Rx Slot B2 Tx Rx Slot Referenced to 1 430 Line Interface Lo Li time slot D Tx Rx Slot B1 Slot B2 Slot Referenced to Digital System Interface Bx Br time slot
9. NT HPC NT INFOO PUP AR LM LSD PUP e EI m Dp e ACTIVATED ACTIVATED 010730 30 FIGURE 21 Activation Initiated by 5 3 S Interface Loop Deactivation Initiated from the NT Side An activated S interface may be deactivated by generating a DR command in the NT as shown in Figure 22 This will force the transmitter of the TP3420A to send INFOO on the line The SID in the TE side of the loop detects INFOO and sup plies DI status to the local management entity and also forces INFOO on its transmitter output The SID on the NT side will detect the INFOO and informs the local manage ment entity via DI status The local controllers on both TE and NT may optionally power down the SID to save power HPC TE SID TE 5 interface 50 NT am INFOO es AN010730 31 FIGURE 22 Deactivation Initiated by NT 5 4 D Channel Request and Flow Control TP3420A On interface no TE can use channel until it is as signed by the network via the D channel Therefore there is never a contention problem in a B channel The D channel however carries multiple logical links to and from multiple physical end points TE s Therefore packets from different TE s may contend for the use of the D channel towards the network This multiple access contention is resolved on the S interface by making use of the layer 2 HDLC framing rules Figure 23 TP3420A implements the D c
10. WITH THEIR LAST TRANSMITTED 010730 32 FIGURE 23 D Channel Access Control 23 www national com 7 1 Abort Packet Immediately Open New Flag to Re Transmit 84175 OK to Start Sending If a Signaling Message and b Normal Priority a Signaling Message and b Low Priority 10 1 5 OK to Start Sending If a Data Packet and b Normal Priority 114175 OK to Start Sending If CLOSING FLAG 01111110 111111 1 1 OK to Start Sending If D ECHO BITS Opening Flag Starts with a Data Packet and b Low Priority 0 Reset 1 5 Counter the C Counter Number of Consecutive 1 s in the D ECHO E Channel Priority Goes Normal Low after Successfully Sending a Packet Priority Goes Back to Normal when C 9 or 11 1 5 010730 80 FIGURE 24 D Channel Flow Control Priority Counting 5 5 Software Driver Considerations for the TP3420A The following paragraphs discuss the software driver imple mentation for the TP3420A in both NT mode and TE mode The software driver functions include Activation Deactivation Procedure D Channel Access and Multiframe Channel Data Access S Loop Activation and Deactivation The software driver guides the SID through the activation process to suit a vari ety of applications These applications could be for a Termi nal Equipment and NT1 a Linecard a trunk
11. 68 FIGURE 25 Software Driver Flowchart for 6 3 1 Initialization Subroutine This is the first to run in the Layer 1 driver software upon a system power up or a system reset It configures the SID to be in either TEM or TES mode The Digital Interface format must be selected for the intended target system The TP3420A will enter state F2 1 from state F2 after the applica tion of the PDN command State F2 1 is the SID Low Power mode Please consult TP3420A Data Sheet for a complete list of commands INITIALIZE SID PDN DIF1 810 820 AL MIE EIE TEM TES 010730 33 FIGURE 26 Initialization Subroutine for 6 3 2 Interrupt Service Subroutine This is called whenever a SID interrupt occurs In this sub routine the local microprocessor sends NOP FF H to the SID to read its status and sets the flags accordingly These flags are Activation Pending AP Deactivation Indication DI Activation Indications Al Error Indication El SID INTERRUPT SERVICE ROUTINE SEND NOP COMMAND FF TO SERVICE SID DECODER STATUS AND SET APPROPRIATE FLAGS e g LSD DI AP AP RETURN FROM INTERRUPT 010730 35 FIGURE 27 Interrupt Service Subroutine Flowchart for TE 6 3 3 Main Subroutine This is used to process the flags set by the Interrupt Service Subroutines and performs appropriate actions such as pass ing primitive indications to the upper layers or sending com mands to
12. D Slot Note For NT TES modes FSa to FSb inputs have to be same phase Note No D CH data loopback from Li to Lo External Command Status LBL1 Loopback B1 towards line interface if LBL1 1 LBL2 Loopback B2 towards line interface if LBL2 1 CAL Clear all loopbacks BDIR B CH mapped direct B1 to B1 B2 to B2 BEX B CH exchanged B1 to B2 B2 to B1 B1E B1 CH enabled B2E B2 CH enabled B1D B1 CH disabled B2D B2 CH disabled Al Activation Indication FIGURE 40 TP3420A System Loopback Function Diagram LBL1 LBL2 SYSTEM INTERFACE 1 0 010730 58 www national com 42 Normal Operation 010730 59 LBL2 Loopback 1 82 0 LBL1 Loopback 1 82 0 010730 60 LBL1 2 Loopback 1 82 0 010730 64 2 B1 B2 D B1 B2 D 010730 65 FIGURE 41 TP3420A Test Loopback Summary 9 0 ADDITIONAL TEST FEATURES The TP3420A SID devices also include several system fea tures intended for system test and system instrumentation purposes namely the external local analog loopback and monitor mode activation as explained below 9 1 External Local Analog Loopback External local analog loopback is physically accomplished by connecting the line output signals after the transmit trans former to the line input signals before the receive trans former as shown in Figure 42 The SID is set in NTA or NTF mode and the local loop is activated with the f
13. circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to 5 terms and conditions of sale supplied at the time of order acknowledgment warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with 5 standard warranty Testing and other quality control techniques are used to the extent Tl deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards does not warrant or represent that any license either express or implied is granted und
14. does this application require the device to cope with arbitrary phase relationships between the 1 430 receive frame and the 8 kHz Fs but also the possibility of slips arises A slip may occur when the frame phase relationships across the device are not fixed but jitter sufficiently to cause loss of data and frame sync At frequencies below 10 Hz this form of jitter is called wander and CCITT specification Q 502 shows that wander up to 18 us peak peak may arise over a 24 Hour pe riod An elastic store is included in both the transmit and re ceive paths of the SID for two reasons 1 To allow complete flexibility for any time slot to be as signed at the digital interface regardless of the phase of the receive 1 430 frame In addition separate FS inputs for transmit and receive allow them to have independent frame and time slot alignments 2 To absorb wander between the frame phases across the device up to the limits specified in Q 502 Each elastic store in conjunction with some control circuitry is used to adjust the output timing requirements gradually for error free transmission performance Figure 16 shows the general mechanism supported by the SID in either direction which utilizes a serial to parallel converter a buffer and a parallel to serial converter The incoming data 2B D is transferred into the register as each word is accumulated in the serial to parallel converter Some time later data in the buffer is
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16. relate to the 1 430 states and primitives They are located in the lower part of the boxes The TP3420A commands and status have the prefix SID after which the SID command is enclosed in pair of brackets to distinguish it from its returned status not enclosed by brackets For example SID AR is the TP3420A Activation Request command whereas SID LSD in the Signal Line Detection interrupt The SID returned status and the applied commands should occur in such the writing order In addition there are a few timers associated with this table and are described in the footnotes below the table 25 www national com 84 HA HA 1501 44 EL He oi Ha 1 dv dls 94 zI3 HdlN C 10 05 10 05 10 05 d 4 IG HdN IV GIS 441 HS IW Hd IO HdlA iq ais ust ais SION E4 44 EL HS IW Hd 4 IC HdN p 4461 H S IW HdIN Iv Hd p 94 ee 5 4 13 EL IV Hd uvi ais dv dis WE IV ais lavras dv dls landl ais 051 015 _ L3 IV HdW IV Hd 9 II HdIN OJNI uvi ais av ais 15 asrais 94 9 II HdIN OJNI
17. the TP3420A as needed to follow the 1 430 Activation Deactivation procedure for TE The Flowchart for this is shown in Figure 28 Loop start up either from the re mote end or the local end is handled in this routine by simply responding to status change interrupts from the SID with ap propriate commands back to the SID Transient such as lightening surge across the telephone line may cause false triggering of the Line Signal Detect LSD interrupt in the SID during the idle period which would cause unexpected loop activation Software routines can be devel oped to filter out such transient triggers An example of this is described below After a wait of 5 ms on the first occurrence of the LSD inter the tLSD timer is activated and the LSD__ FILTERED flag is set this flag must be reset on system power up or system reset condition These are followed by a PDN com mand If this is a true Remote Activation Request from the far end NT a second LSD interrupt will occur right after this PDN command In this case the set condition of the LSD __ FILTERED flag indicates that there is a continuous INFO signal on the line Otherwise the expiration of the tLSD timer signifies that this is a false alarm The value of t gp timer can be from 5 ms to 10 ms www national com 28 There few timers associated with the 1 430 Activation Deactivation Recommendation and are described in the notes below the Table 1 Two o
18. the status regis ter may be read upon the INT signal going low NT TP3420A SID 010730 27 2 Fixed Timing locked to TX CLK and phased at 4 us after TX edges Used in NT mode for passive bus only The NT TE bits select both the timing mode and the state machines for activation control FIGURE 18 TP3420A Receive Timing Circuitry www national com HPC16400E DIGITAL SYSTEM INTER FACE TP3420A SID WIRE INTERFACE 010730 28 FIGURE 19 TP3420A SID Line Signal Detect Circuit Connection to 16400 5 0 ACTIVATION AND DEACTIVATION USING TP3420A SID AND HPC16400E TP3420A SID and HPC16400E combination makes an ideal system solution for ISDN terminals TE s When this hard ware combination is used in a system implementing CCITT recommended activation and deactivation procedures is simplified considerably Assuming both the TE and NT ends of the system employ the TP3420A and HPC16400E combi nation the activation deactivation procedures for specific cases are explained below 5 1 S Interface Loop Activation Initiated from the TE End Figure 20 illustrates various commands and status indica tions and the resultant INFO signals for a successful activa tion of the S interface for the case when has initiated the activation procedure This discussion however does not indicate the timers that are required in an activation proce dure see Section 6 The following sequence of events
19. to settle down The software driver then sends an AR com mand to bring the SID to state G2 at the same time starts the timer T1 and waits for INFO3 The SID generates AP in terrupt once it detects INFO3 from the far end TE Another AR command sent to the SID will bring it to fully activated state state G3 If the timer is expired during the local ac tivation process the software driver sends a DR command to the SID to bring it back to state G2 Notice that there is no state G4 involved in this activation process for the reason mentioned above Otherwise the timer TI is reset in state G3 The S bus can only be deactivated by the NT The software driver simply sends a DR command to perform this task Start Local Activation Deactivation Deactivation 010730 77 FIGURE 34 Software Driver Flowchart for Activation PUP Wait 2ms AR Start Timer T1 7 3 4 Subroutine This software module is used to process the flags set by the interrupt Service Routines and performs appropriate actions such as passing primitive indications to the upper layers or send commands to the TP3420A as needed to follow the 1 430 Activation Deactivation procedure for NT The Flow chart for this is shown in Figure 36 Loop start up either from the remote end or the local end is handled in this routine by simply responding to status change interrupts from the SID with appropriate commands back to the SID Transient no
20. to F5 TO assure that a TE will go to state F5 when receiving a signal to which it can not synchronize operation of TEs should be verified where the received signal is any bit pattern containing at least three ZEROs in each frame interval to which TEs conforming to 7 3 1 2 are not able to synchronize Note 5 INFOO shall not be detected until at least 48 continuous binary ONEs have been received and the TE shall perform the actions specified in this table For conformance test purposes when in the states F6 and F7 with a sinusodial signal having a voltage of 100 mV peak to peak superimposed on the received signal the TE shall react to INFOO by transmitting INFOO within a period of time 250 us to 25 ms It is recognized that the action in states F2 and F8 is the passing of primi tives and that this can not be observed or verified at the interface Note A provision for the immediate reaction to INFOO following the reciept of 48 continuous ONEs may cause the release of ongoing communications in response to spurious interface signal interruptions A persistence check should be considered to minimized such a possibility but the total reaction time shall not exceed 25 ms Note 6 To avoid disruption of on going communication caused by spurious effects a timer may be started when leaving the state F7 or F8 upon reception of INFOO The corresponding PH DI will be delivered to layer 2 only if layer 1 does not re enter state F7 before expiry of this timer Th
21. 0 67 FIGURE 43 Monitor Mode Application LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI CONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or sys 2 Acritical component is any component of a life support tems which a are intended for surgical implant into device or system whose failure to perform can be rea the body or 0 support or sustain life and whose fail sonably expected to cause the failure of the life support ure to perform when properly used in accordance device or system or to affect its safety or effectiveness with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 49 0 1 80 530 85 86 Response Group Tel 81 3 5639 7560 Tel 1 800 272 9959 Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Fax 1 800 737 7018 Deutsch Tel 49 0 1 80 530 85 85 Fax 65 2504466 Email support nsc com English Tel 49 0 1 80 532 78 32 Email sea support nsc com Frangais Tel 49 0 1 80 532 93 58 www national com Italiano Tel 49 0 1 80 534 16 80 National does not assume any responsibility for use of any
22. 0 kHz 2 MHz 100mV 100 010730 6 TP3420 SID 1 430 Specification Differential Distance Differential Distance Meters Meters 275 25 to 50 275 250 100 50 FIGURE 5 SID Extended Passive Bus Range Measurement www national com 6 70 1600 45 75 1600 6uS 80 16006uS FUNCTION1 200 6 mVOLTS DIV TIMEBASE 1 00 uS DIV 10730 7 FIGURE 6 SID Output Pulse Shape and Amplitude vs Mask 500 249 710 mS 249 715 mS 249 729 mS CH 1 299 5 0115 DIV 1 00 uS DIV 010730 8 FIGURE 7 SID Output Pulse Shape and Amplitude vs Mask 4000 7 www national com 12 12 SID TRANSMITTER OUTPUT IMPEDANCE CURVE TE CABLE LENGTH 25 FT TE CABLE CAPACITANCE 300 pF TE MODE INACTIVE gt Jm mc TRANSFORMER TYPE PE64995 8842 IP TRANSFORMER RATIO 2 1 N EHE TE SID TRANSMITTER OUTPUT IMPEDANCE CURVE TE CABLE LENGTH 25 FT TE CABLE CAPACITANCE 300 pF TE MODE INACTIVE TRANSFORMER TYPE PE64995 8842 IP TRANSFORMER RATIO 2 1 FREQUENCY KHz FIGURE 8 SID Receiver Input Impedance Curve FREQUENCY KHz FIGURE 9 SID Transmitter Output Impedance Curve T S 010730 9 1000 010730 10 www natio
23. 2 2 3 Printed Circuit Board Layout Considerations Taking care of the pcb layout in the following ways will help prevent noise injection into the receiver front end and maxi mize the transmission performance place the transformer and TP3420A on the same ground plane keep short connections between the transformer and TP3420A keep short connections from the transmission lines to the transformer minimize crosstalk between the transmit and receive pairs minimize crosstalk from the crystal into the transmit and re pairs www national com 2 2 4 Line Transformer Manufacturers Pulse Engineering Phone number 619 674 8130 Part number PE64995 2 1 single transformer package Part number PE65495 2 1 dual transformer package Valor Phone number 619 537 2500 Part number PT 5055 2 1 dual transformer package Part number PT 5001 2 1 single transformer package MID COM Phone number 800 643 2661 Part number 671 6322 Vernitron Phone number 813 347 2181 Part number 328 0044 VAC Phone number Germany 49 6181 38 2544 USA 908 4494 3530 Part number ZKB402 ZKB409 Note Surface mount transformer are also available from Pulse Engineering and Valor 2 3 External Protection Circuitry Precautions are to be taken to ensure that the TP3420A is protected against electrical surges and other interferences due to electromagnetic fields power line faults and lightning discharges that may occur in the transmissio
24. AL TEST FEATURES 9 1 External Local Analog Loopback 9 2 Monitor Mode Activation Implement RELATED MATERIAL This manual assumes that the user is familiar with the ISDN Basic Rate Interface and its applications Other applicable documents include TP3420A S Interface Device SID Data Sheet TP3076 COMBO II Data Sheet HPC16400E Communications Controller Data Sheet e HPC16400E User s Manual CCITT 1 430 Basic Access Interface Layer 1 Specification ANSI T1 605 Specification TP3420A Line Interface Circuit Considerations AN 872 e Interconnecting NSC TP3420A SID to Motorola SCP HDLC Device AN 931 User Network 1 0 INTRODUCTION The TP3420A SID S Interface Device is a complete mono lithic transceiver for data transmission on twisted pair sub scriber loops All functions specified in CCITT recommenda tion 1 430 for ISDN basic access at the S and T interfaces are provided and the device can be configured to operate ei ther in a TE Terminal Equipment in an NT 1 or NT 2 Net work Termination or as PABX line card device MICROWIRE COMBO II MICROWIRE PLUS and HPC are trademarks of National Semiconductor Corporation www national com SPINS 5 1951 GIS a2puaul S WOZVEdL Table of Contents Continued As specified in 1 430 full duplex transmission at 192 kb s is provided on separate transmit and receive twisted pair wires using Alternate Mark Inversio
25. Activation and Deactivation on the S Interface These are known as the F states The software drivers rec ommended for the TP3420A implement additional internal states as described below F1 Power supply is turned off TE not plugged into the power source F2 The power supply is ON however the receiver has not yet processed the signal received TE Connected F3 Deactivated state F4 The activation of layer 1 was initiated by the TE INFO1 The TE waits for an INFO2 Awaiting Signal F5 Once the signal is received the TE stops transmitting INFO1 and processes the receive signal INFO2 or INFO4 Synchronizing F6 The TE recognized receipt of an INFO2 and waits for INFO4 Synchronized F7 Activated State of the TE Activated F8 The TE lost the frame synchronization and is trying to resynchronize itself Lost Framing Additional States for SID INITIALIZE TP3420 SID initialization POWER TP3420A SID in Power Down mode In this DOWN mode the SID will detect the present of a sig nal on the line but not be able to identify it This state is also called state F2 1 in this docu ment 6 2 1 430 Activation Deactivation Requirements for TE The Activation Deactivation procedure for TE is defined in the 1 430 document It is summarized in a Finite State Matrix Table A modified version of this is shown in Table 1 where the internal commands states of the TP3420A are superim posed in the table where appropriate to
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27. RAE Bit RX1 D B1 B1 B2 B2 REN1 B1 TABLE 5 HDLC Enable Signals for Channel 2 1 0 0 0 B1 B1 2 0 0 1 B2 B2 3 0 1 0 TEN2 8 REN2 amp B1 B1 4 0 1 1 TEN2 8 REN2 amp B2 B2 5 1 0 X 1 1 6 1 1 D TEN2 REN2 3 2 1 TP3420A SID and HPC16400E Connection for D Channel Figure 14 shows the connection of TP3420A SID s Digital System Interface signals to the HPC16400E serial decoder and HDLC Controllers 1 and 2 for the D channel and B channel respectively For D channel selection into the HDLC 1 the FSa signal on the DSI has to be connected to the REN1 pin DO signal on the serial decoder HDLC 1 In this application Case 1 of HDLC enable signals for channel 1 in Table 4 is used 3 2 2 TP3420A SID and HPC16400E Connection for B Channel For B channel selection into the HDLC 2 Case 1 or Case 2 of the HDLC enable signals for channel 2 for B1 or B2 channel respectively is used from Table 5 3 3 TP3420A SID Digital System Interface and TP3076 COMBO Connection When one of the B channels in the ISDN stream is PCM coded voice an ideal solution is to connect this B channel to TP3076 National s PCM for ISDN The TP3076 is second generation combined PCM CODEC and filter devices optimized for digital telephone applications The device is A law and programmable and employ a conventional serial PCM interface capable of being clocked up to 4 096 MHz A
28. Sr 3 4 NT 2 Synchronization TP3420A The NT 2 typically a PBX has a number of S interfaces on the customer s side and if it uses Basic Access to the net Work each trunk is a T interface to an NT 1 as shown in Fig ure 15 Functionally the S and T interfaces are identical i e both conform to 1 430 Thus the SID can operate on the S in terface side with NT more selected either fixed or adaptive receive sampling as appropriate for the wiring and on the T interface side the SID operates like a terminal in TE mode However the complete NT 2 must have all its clocking and data interfaces synchronized to the network This requires a system clock at typically 2 048 MHz to be phase locked to one of the T interfaces The SID includes this PLL with an SCLK output on the DENx pin when used in TE mode DSI Slave TES only Any one of the SID s can provide this clock but all will take their BCLK and Fs timing from the same one i e they are slaved to the network clock and syn chronized to each other In this way clocking is synchronized all the way from the network to the terminal 3 5 Slave Slave Mode and Elastic Buffers TP3420A When SID is used in TE mode TES it is a timing slave to the network but the digital interface is also in a slave mode Le Fs and BCLK are inputs and is referred to as slave slave mode A typical slave slave application is on the net work side of an NT 2 or PBX at the T interface Not only
29. TP3420 TP3420A S Interface Device SID User s Guide 0 5 INSTRUMENTS Literature Number SNOA821 TP3420A 5 Interface Device SID User s Guide Table of Contents 1 0 INTRODUCTION 2 0 LINE INTERFACE AND TRANSMISSION PERFOR MANCE 2 1 Master Clock Source 2 1 1 Crystal Oscillator 2 1 2 External Oscillator Configuration 2 1 3 List of Recommended Crystal Manufacturers 2 2 Line Transformer Requirements 2 2 1 Line Transformer Ratio 2 2 2 Line Transformer Electrical Parameters 2 2 3 Printed Circuit Board Layout Considerations 2 2 4 Line Transformer Manufacturers 2 3 External Protection Circuitry 2 3 1 DC Bias Capacitors for Analog Reference 2 4 Transmission Performance 3 0 TP3420A DIGITAL INTERFACE 3 1 Digital System Interface Formats 3 2 TP3420A SID Digital System HPC16400E Connection 3 2 1 TP3420A SID and HPC16400E Connection for D Channel 3 2 2 TP3420A SID and HPC16400E Connection for B Channel 3 3 TP3420A SID Digital System Interface and TP3076 COMBO Connection 3 4 NT 2 Synchronization TP3420A 3 5 Slave Slave Mode and Elastic Buffers TP3420A 4 0 DIGITAL CONTROL INTERFACE 4 1 The MICROWIRE Bus 4 2 TP3420A SID to HPC16400E MICROWIRE Connec tion 4 3 TP3420A SID COMMAND and STATUS Bytes 4 4 TP3420A Receive Timing Recovery 4 5 TP3420A Line Signal Detect LSD and Wake Up Signal for uP 5 0 ACTIVATION AND DEACTIVATION USING THE TP3420A SID AND HPC16400E 5 1 S Interface Loop Activati
30. a local activation procedure If this timer is expired before the Activation Pending in terrupt the micro controller should send a Deactivation Request DR command followed by a Power Down PDN command to bring the SID to the Low Power mode 2 tinroa Note 4 of the 1 430 Table 7 is used to delay the transmission of INFO4 after the NT reaches Activation Pending state G2 upon the reception of INFO3 from the TE This timer is started once the NT reaches state G2 Upon the expiration of this timer layer 1 driver sends an AR command to bring the SID to state G3 The following Al interrupt indicates that the SID s been send ing out INFO4 and Layer 1 now can send MPH AI to the upper layers This is to allow the U inter face loop to acquire synchronization Please also see the TP3410 user s manual for additional signal flow dia grams for NTI application The value of this timer is 100 ms 7 4 TP3420A Internal G State Machine Diagram Figure 35 is the internal G State Machine in the TP3420A when the device is programmed to be in NTA or NTF mode There are 3 1 430 equivalent states namely G1 G2 and G3 and other intermediate states Stated GO is the low power mode A specified stimulus that causes a state jump is writ ten in the transition line before the slash or by itself The returned status is written after the slash Not every transi tion has a returned status 35 www national com Power
31. atus register occur INT returns to the high impedance state on the rising edge of CCLK after CS goes low The TP3420A will revert to the ALTERNATE MICROWIRE mode to communicate with the Motorola SCP master de vices Please see TP3420A Data Sheet and AN 931 Inter connecting NSC TP3420A SID to Motorola SCP HDLC De vices for more details Note When reading an interrupt from SID a NOP hex FF must be loaded into Cl 4 2 TP3420A SID to HPC16400E MICROWIRE Connection The MICROWIRE PLUS interface on HPC16400E has an 8 bit parallel loaded serial shift register using SI as the input and SO as output SK is the clock for the serial shift register SIO SK clock can be provided from an internal HPC timer or from an external source and the internal clock is program mable by the DIVBY register A DONE flag indicates when the 8 bit data shift is completed The HPC16400E should be configured in the Master mode for operations in this case A control bit in the IRCD register determines whether the HPC16400E is in master or slave mode for MICROWIRE PLUS applications Figure 14 illus trates the use of HPC MICROWIRE PLUS in controlling the TP3420A MICROWIRE interface 4 3 TP3420A SID COMMAND and STATUS Bytes The control commands and status indication functions sup ported by the TP3420A allow it to be flexibly used in various system applications with relative ease The command con trols are in distinct groups of functions and in most o
32. ble which has approximately 90 nF km capaci tance and 180 O km resistance This cable has a loss of 7 8 dB km at 96 kHz Performance was measured with three different configurations namely 1 Point to Point 2 Short Passive Bus 3 Extended Passive Bus In all these tests noise sources recommended by the 1 430 ANSI standard per Section 8 6 2 1 were complied with The setups are shown in Figures 3 4 and Figure 5 along with the tables showing the actual range measured versus the 1 430 recommended range Noise sources were located close to the NT receiver and injected via two 1 resistors to avoid affecting the loop impedance significantly Activation and error free transmission could be accomplished on either end of the S interface in the case of the point to point configura tion and from any one of the TEs in the case of both passive bus configurations The error rate was measured in a channel in these tests The TEs and NT in all these configurations used TP3420A SIDs The NT device in the point to point and extended pas sive bus cases was in NTA mode while the short passive bus used NTF mode The results tabulated show that the SID ex ceeds the 1 430 and ANSI range requirements Pulse Shape and Impedance Templates As shown in Figure 6 and Figure 7 the TP3420A SID trans mitter output pulse shape and amplitude comply with the specified pulse masks for both the 500 and 4000 test load impedance cases Plots in Figure 8 an
33. card or a com bination of above The SID handles all the critical activation functions and the software needs to simply respond to sta tus change interrupts with activation control commands in collaboration with maintenance times appropriate for the ap plication SID Command Status Servicing The TP3420A is con trolled by a local microprocessor via the MICROWIRE port A TP3465 can be used to convert the parallel data from a micro processor bus to the MICROWIRE serial format for up to 8 TP3420A devices if that micro processor does not sup port such compatible serial interface see TP3465 data sheet for this application The microprocessor sends one byte commands to the SID via the Cl pin At the same time the SID sends a one byte status back to the microprocessor via the CO pin A returned byte of 00 indicates that the SID sta tus has not changed Otherwise it returns the updated sta tus The SID requests an interrupt service from the microproces sor by pulling the INT pin low The microprocessor can ac cess the changed status in the SID by sending NOP com mand FFHex In some applications interrupt handling may not be available then a periodic polling method for the SID status by sending a NOP command can also be imple mented It is possible that while the software driver is send ing a normal command SID a SID interrupt occurs but is ignored because it may have been masked off temporarily In this case the SID wil
34. d Figure 9 show the receiver input impedance and output impedance These tests were done with the recommended Pulse Engineering transformers The SID output drivers are specifically de signed with controlled rising and falling transitions for mini mal pulse overshoot and undershoot with a wide range of transformer designs Furthermore the following figures show the transmit and receive impedance templates are met with the specified cable connected and the protection net works shown in Section 2 3 The device has been success fully tested for pulse shape and impedance with various other manufacturers transformers www national com 2 1 TP3420A SID 5V ex not connected 010730 2 Not normally required if TE is used only on internal wiring FIGURE 2 External Protection Circuit TE Application www national com 1000 1000 TERMINATION TERMINATION TP3420A SID TP3420A SID TE NT 200 KHz 2 MHz 100mV 100 mV TP3420 SID 1 430 Specification 1800m 1000m FIGURE 3 SID Point to Point Range Measurement 1000 RAN GE 1000 TERMINATION TERMINATION TP3420A SID 5 010730 4 TP3420A SID NT 200 KHz 2 MHz 100mV 100 TP3420 SID 1 430 Specification 100m 200m FIGURE 4 SID Short Passive Bus Range Measurement 1000 RANGE 1000 TERMINATION TERMINATION DIFFERENTIAL DISTANCE y TP3420A SID NT 010730 5 TP3420A SID TE S 20
35. e value of this timer may be in the range of 500 ms to 10000 ms Note 7 Timer 3 T3 is a supervisory timer which has to take into account for the overall time to activate This time includes the time it takes to activate both the ET NT and the NT TE portion of the customer access Note 8 Terminal may momentarily enter state F3 at this point and return to state F6 if INFO2 is still being received the term momentarily means up to a maximum of 5 frames 27 www national com 6 3 Suggested Software Flowchart to Implement Activation Deactivation Procedure for TE The layer 1 Task software can be divided in 4 parts Initializa tion subroutine to bring up the SID in the desired ready state the Interrupt Service Subroutine to response to interrupts is sued by the SID read the status of the SID and then set ap propriate software flags the Main Subroutine to check the status of these flags to control the state flow of the SID so as to adhere to the 1 430 Layer 1 Activation Deactivation Re quirements and the Local Activation Subroutine to detect a hook switch state or a Activation Request from the upper layers to start a local activation A delay of 2 ms is recom mended after the device is powered up by the PUP com mand Doing this allows the SID internal circuitry to have enough time to settle down Management Entity Layer 2 TE INITIALIZE PH AR Start Local Activation Interrupt Service Subroutine 010730
36. ents for Layer 1 Activation Deactivation State Name Deactivated Pending Active Pending Activation Deactivation G4 Note 13 NFO Sent en w we State Number INFOO Start Timer T1 Start Timer T1 SID SC 3p TAG SID AR Start Timer T2 Start Timer T2 PH DI G4 PH DI G4 Note 10 Note 10 Start Timer T2 PH DI G4 ES Note 10 G2 Note 11 G1 SID EI Start Timer T1 G2 SID LSD SID PUP SID AP SID AR Receiving INFO3 Stop Timer T1 MPH AI G3 Note 12 SID AP SID AR SID Al Lost Framing MPH DI 2 NOTATIONS p s a b Gn PH DI MPH AI MPH DI Note 11 SID EI No state change Impossible by the definition of peer to peer physical layer procedures or system internal reasons Impossible by the definition of physical layer service Issue primitives a and b then go to state Gn Primitive PH Active Indication Primitive PH Deactivate Indication Primitive MPH Activation Indication Primitive MPH Deactivate Indication Primitive MPH Error Indication 33 www national com SID command 8 command sent to the TP3420A They can be found in the TP3420A Data Sheet SID interrupt TP3420A internal interrupt They can be found in the TP3420A Data Sheet Note Primitives are signals in a conceptual queue and wil
37. ents must take place for the NT initiated activation of the S interface NT SIDE TP3420A SID is first powered up and then the AR byte in the command register is sent to ini tiate the S interface activation procedure This causes the NT SID to send INFO2 frames on the S interface Upon detecting the received signals across the S interface the TE SID issues an interrupt to the local HPC indicating LSD The HPC16400E pow ers up the TP3420A which then detects valid INFO2 frames and issues AP status indication to the HPC16400E HP16400E responds to this by issuing an AR command causing the TP3420A SID to send INFO3 frames on the S interface Upon detecting the INFO3 pattern on the S inter face the NT SID alerts the local processor by setting the AP interrupt The NT side processor responds by issuing an AR command causing the NT SID to send INFO4 frames on the S inter face Also at this time SID indicates a successful activation of the S interface by issuing an Al sta tus to the local HPC16400E The TE SID upon recognizing the INFO4 frames indicates to the local HPC the state of successful activation via the Al interrupt TE SIDE NT SIDE TE SIDE 21 www national com HPC TE SID TE S interface SID NT HPC NT LSD INFOO 150 INFO2 INFOO CON AP AR INFO4 Le E e ACTIVATED ACTIVATED 010730 29 FIGURE 20 Activation Initiated by HPC TE SID S interface SID
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39. er is used both at the transmit and the receive end of the loop These notes specify the tolerances of a transformer that is employed with the SID to meet the CCITT recommendation on output pulse mask and impedance requirements 2 2 1 Line Transformer Ratio The transmit amplifier if a 1 2 Np Ns transformer Its pri mary is connected to the S loop while the secondary is con nected to the device The same transformer or optionally a 1 1 transformer can be used for the receive side However the 2 1 transformer is highly recommended per AN 872 to obtain the best longitudinal performance The primary is con nected to the S loop while the secondary is connected to the device with the SID pin Li connected to the center tap 2 2 2 Line Transformer Electrical Parameters The tolerance on the electrical parameters of the 1 2 line transformer are tabulated in Table 7 below www national com Table of Contents Continued TABLE 1 Line Transformer Electrical Parameters Parameter Min Typ Max Units Ns Np 1 98 2 2 02 Lp 22 30 37 5 mH Ls 80 120 150 mH Rp 4 Q Rs 5 16 uH LLs 32 uH The parameter mnemonics and their significance are explained in the para graphs below The total capacitance looking into the primary winding when the secondary is open circuit should be lt 220 pF Line Transformer Winding Inductance Lp Ls The total inductance looking into the terminal from the S loop should be greater
40. es that do not run parallel when in close proximity to minimize coupling between adjacent pins On multi layered boards a ground layer should be used to pre vent coupling from signals on adjacent board layers Ground traces on either side of the high frequency trace also helps isolate the noise pickup 2 1 2 External Oscillator Configuration An external 5V drive clock source may be connected to the MCLK pin 5 input pin of the SID as shown in Figure 1 The nominal frequency should be 15 36 MHz with a tolerance of 80 ppm The SID provides a load of about 7 pF at the MCLK input pin 2 1 3 List of Recommended Crystal Manufacturers Monitor Products Co Inc 502 Via Del Monte Oceanside CA 92504 619 433 4510 Part No MM 38A 15 36 MHz N Freq Tolerance Total 60 ppm XTAL2 MCLK 33pF TP3420A TP3420A 33pF XTAL2 XTAL2 010730 1 This includes the trace and lead capacitance the board FIGURE 1 Clock Circuits 2 2 Line Transformer Requirements The electrical characteristics of the pulse transformer for the ISDN 8 interface are defined to meet the output and input signal and the line impedance characteristics as defined in CCITT recommendation 1 430 The transformer provides iso lation for the line card or terminal from the line it also pro vides a means to transfer power to the terminal over the S loop via the phantom circuit created by center tapping the line side windings A transform
41. f these only one function my be active from each group at a time Listed below are some various control functions and status indication functions Please refer to the TP3420A SID Data Sheet for additional commands and indications Activation Deactivation LSD AP DI Device Modes Se NTA NTF TES Digital Interface Formats Comm Se DIF1 DIF2 DIF3 DIF4 B1 B2 Channel Control Command Status B1E B2E B1D B2D BDIR BEX D Channel Access Command Status End of Message Interrupt Command Status EIE EID Multiframe ___ Soe MFT MFR MIE MID www national com Loopback Tests Command ___ ____5 4 4 TP3420A Receive Timing Recovery The TP3420A has two receive clock timing options available in its system implementations as shown in the conceptual diagram of Figure 18 In adaptive timing mode the DPLL is locked to timing in the received bit stream This mode is used in TE applications for both point to point short and extended passive bus configu rations whereas in NT mode this is used for point to point and extended passive bus configurations only For application in the NT of a short passive bus only the mul tiple TE s with different round trip delays cause wide varia tions in the zero crossings so that a DPLL cannot generate a clean clock reliably Therefore the receive sampling DPLL is b
42. f these MUST be imple mented in the firmware while others are already taken care of in the TP3420A 1 tsPunious timer Note 6 of the 1 430 Table 5 is needed to avoid disruption of an on going communication caused by spurious effects This timer is activated upon entering F2 state Deactivation Indication Primitive PH DI will be delivered to layer 2 only upon the expira tion of this timer The value of this timer may vary from 500 ms to 1000 ms 2 TE Supervisory Timer T3 Note 7 of the 1 430 Table 5 Supervisory timer T3 is usually 15 seconds for applica tions where a TE is connected via an NT 1 to the Central Office over an S Interface loop followed by a U Interface loop If this timer expires and if the SID is in state F4 or F5 indicat ing that the U link failed to activate the local microproces sor must send a DR command to bring the SID to state F3 Deactivated However if the TE is in state F6 indicating that U interface is synchronized but is not transparent to data the SID should remain in state F6 or is allowed to mo mentarily go to F3 and return to F6 within 5 frames This is specified by Note 8 in the 1 430 Activation Deactivation Table The suggested technique is this At the expiry of the T3 timer the local microprocessor can acquire the SID inter nal state machine status by sending ENST command fol lowed by DISST command and then decoding the status byte according to the table given in the TP3420A data
43. hannel access control via a collision detection mechanism as described in 1 430 Section 6 1 for both TE and NT modes Figure 24 D channel flow control refers to the way the uP transfers a layer 2 frame or packet to the SID transmit buffer and from there onto the S interface in a terminal When the layer 2 wants to transmit a packet it does not know if another TE is already occupying the D channel since all D channel moni toring and contention resolution is done by the SID To trans mit its packet the following sequence of events takes place the HDLC controller primes its transmit buffer ready to send byte 1 the uP sends a DREQ D channel request over MICROW IRE to the TP3420A DREQ messages must also indicate if the pending packet is high priority for signaling use DREQ1 or low priority for other types of data use DREQ2 50 starts pulsing DENx to the HDLC is gated with the BCLK in the HPC16400E so 2 D channel bits are INFOO PDN 7 www national com 22 clocked from the HDLC into SID s transmit buffer every 125 us across the DSI No D channel bits are transmitted on the S interface yet SID senses when the opening flag 01111110 from the HPC is in its buffer It then stops pulsing DENx SID now tests to see if the D channel towards the NT is in use by another TE by checking the number of consecutive 1 s counted in the D echo channel When the access algo rithm allows SID starts transmitting D chan
44. he 1 430 loopbacks an explanation of each test loop back mode is in order here In the explanation below we re fer to the B1 B2 and D Tx and Rx slots and B1 B2 and D slots as shown in Figure 37 8 1 Normal Data Mode No Loopbacks SID is powered up with clear all loopbacks CAL mode In this mode the function diagram of the device is as illustrated in Figure 37 This shows normal data paths when no test loopbacks are in effect The switches are positioned accord ing to the state of the device selected through commands 8 2 System Loopback Mode LBS Figure 38 shows a schematic diagram illustrating the system loopback function LBS Upon writing the LBS command into the command register various internal switches are po sitioned as in Figure 38 if B1 and B2 channels are enabled Bx data may be output onto the Lo pins of the line interface at the valid slots of the B1 D and B2 data periods on the Digital System Interface pin Bx and Br for the Format se lected If the DENx Signal is used to strobe the D Channel transient data it is necessary to force the DENx to pulse every 8 kHz This can be done by writing the DACCD while in TEM or TES mode www national com 38 B1D BDIR CLOSED IF B1 RX SLOT CLOSED IF B1 SLOT Li CLOSED IF D RX SLOT CLOSED IF D SLOT CLOSED IF B2 RX SLOT Ge o oO gt B2D e 25 B1D o BDIR z PERS CLOSED IF B1 TX SLOT CLOSED IF
45. indings to ensure that the transmit pulse mask requirements are met 2 3 1 DC Bias Capacitors for Analog Reference Two decoupling capacitors 0 1 pF mica and 10 uF electro lytic are connected between pin 19 of the device and its ground connection These capacitors decouple the midpoint of a two resistor potential divider inside the device and pro vide an internally buffered reference for the analog circuitry 2 4 Transmission Performance The TP3420A SID is designed with the goal of substantially exceeding the transmission performance requirements as specified in the 1 430 This is made possible in the design by employing complex signal processing techniques in the re ceiver front end design For example in the receive path an analog prefilter removes gt 200 kHz noise signals which is then followed by an adaptive line equalizer to correct for the attenuation of loops in excess of 1 5 km in length with supe rior performance A continuously tracking adaptive threshold circuit optimizes the slicing levels in the detection circuits for correct detection of received data even on long lossy loops Finally a digital filter discriminates against in band noise This architecture results in longer range error free transmis sion in point to point applications and greater spread of ter minals in extended passive bus applications than simpler first generation tranceivers The SID transmission performance was measured on 24 AWG PIC ca
46. iption of the serial decoder and the various sig nals associated with it The serial decoder is controlled by the contents of the SERDEC register of the HPC16400E Because the TP3420A has four different formats for multi plexing B and D channels on its Digital System Interface it is important to setup the HPC16400E in the correct mode for compatibility with the chosen digital interface format from the TP3420A as shown in Table 3 below TABLE 3 Relationship between the HPC Serial Mode and the SID DIF Format HPC Serial Mode SID DIF Format This is done by the upper 3 bits of the SERDEC register in the HPC16400E The serial decoder of the HPC16400E in conjunction with the ENABLE SELECT logic provides the enable signal for data multiplexing The serial decoder services the 2 HDLC channels for a detailed discussion on the Serial decoder please refer to the HPC16400E data sheet For each HDLC channel there are two ENABLE SIGNALS one for the Re ceiver and one for the TRANSMITTER Each HDLC channel ENABLE signal can be connected to the EXTERNAL RECEIVER TRANSMITTER ENABLE REN1 TEN1 REN2 and TEN2 or the Internally Generated Enable strobe signals B1 B2 and D or can be used for ANDing of the EXTERNAL ENABLE and INTERNAL channel strobe signal The HDLC Channel Enable Signals are selected by setting the 5 lower SERDEC register bits as shown in Table 4 and Table 5 TABLE A HDLC Enable Signals for Channel 1 pam
47. ise such as lightening surge across the tele phone line may cause false triggering of the Line Signal De tect LSD interrupt in the SID during the idle period which would cause unexpected loop activation Software routines can be developed to filter out such transient triggers An ex ample of this is described below After a wait of 5 ms on the first occurrence of the LSD inter rupt the tLSD timer is activated and the LSD FILTERED flag is set this flag must be reset on system power up or System reset condition These are followed by a PDN com mand If this is a true Remote Activation Request from the far end NT a second LSD interrupt will occur right after this PDN command In this case the set condition of the LSD FILTERED flag indicates that there is a continuous INFO signal on the line Otherwise the expiration of the tLSD timer signifies that this is a false alarm The value of tLSD timer can be from 5 ms to 10 ms There are a few timers associated with the 1 430 Activation Deactivation Recommendation for NT and are described in the notes below the Table 7 Two of these MUST be imple mented in the firmware while others are already taken care of in the TP3420A 1 T1 timer Note 1 of the 1 430 Table 7 can be as long as 15 seconds for applications where a TE is connected to NT 1 device to the Central Office via a U interface loop This timer is started after an occurrence of the LSD inter rupt or at the beginning of
48. ivation Deactivation INITIALIZE SID PDN DIF1 B1D B2D CAL MIE El E NTA NTF 010730 45 FIGURE 32 Initialization Subroutine for 7 3 2 Interrupt Service Subroutine This is called whenever a SID interrupt occurs In this sub routine the local microprocessor sends NOP FF H to the SID to read its status and sets the flags accordingly These flags are Activation Pending AP Deactivation Indication DI Activation Indications Al Error Indication El etc SID INTERRUPT SERVICE ROUTINE Interrupt SEND NOP COMMAND Service Subroutine TO SERVICE SID 010730 74 FIGURE 31 Software Driver Flowchart for DECODE STATUS AND SET APPROPRIATE FLAGS e g LSDG AP Al 7 3 1 Initialization Subroutine This software routine is the first to run in the layer 1 driver RETURN FROM software upon a system power up or a system reset It con INTERRUPT figures the SID to be in either NTA or NTF mode Typically 010730 47 NTA mode is used for point to point applications and NTF FIGURE 33 Interrupt Service Subroutine for NT mode is used for passive bus applications where up to 8 TEs www national com 34 7 3 3 Local Activation Deactivation Subroutine Management Entity or Layer 2 can request a Local activation by issuing a MPH AR or PH AR while the SID is in state F3 Deactivated This assumes the SID has been powered up at least 2 ms so that the internal circuitry has enough time
49. l Activation indication 820 CLOSED IF D SLOT CLOSED IF D SLOT CLOSED IF 1 SLOT CLOSED IF B2 SLOT CLOSED IF B1 SLOT CLOSED IF D SLOT CLOSED IF B2 SLOT SYSTEM INTERFACE 1 0 CLOSED IF B1 SLOT Bx CLOSED IF B2 SLOT 010730 56 FIGURE 38 TP3420A System Loopback Function Diagram LBS 8 3 System Loopback Mode LBB1 LBB2 Figure 39 shows a schematic diagram when LBB1 or LBB2 system loopbacks are used LBB1 and LBB2 loopback modes may be chosen independently when B1 and or B2 re spectively are to be looped back to the system interface from Bx to Br while at the same time B1 B2 and D data to the line interface Bx to Lo may be allowed Also at the same time B2 or B1 and D channel data may be allowed from the line interface to the system interface Li to Br Data transfers across line interface and system interface are pos sible only when SID is in the activated state Al 1 For example in Figure 39 when LBB1 is enabled the B1 channel from the system interface is looped back assuming B1 is enabled At this time B1 B2 and D channels may be transferred across the interfaces if Al is true also B2 and D channels may be transferred from Li to Br www national com 40 BDIR LBB1 1 o B1D T aid CLOSED IF B1 RX SLOT Li CLOSED IF D RX SLOT CLOSED IF B2 RX SLOT CLOSED IF B1 TX SLOT B2E No
50. l be cleared on recognition while the INFO signals are continuous signals that are available all the time Note 9 Timer 1 T1 is a supervisory timer that has to take into account the overall time to activate This time includes the time it takes to activate both the ET NT and the NT TE portion of the customer access ET is the exchange termination Note 10 Timer T2 prevents unintentional reactivation Its value is greater than 25 ms and smaller than 100 ms This implies that a TE has to recognize INFOO and to react on it within 25 ms If the NT is able to unambiguously recognize INFO1 then the value of timer 2 may be 0 and an MPH Deactivate Request would cause a direct transition from state G2 or G3 to state G1 It should be noted that unambiguous detection of INFO1 may not be possible in passive bus configurations considering all possible TE implementations Note 11 These notifications MPH DI MPH EI need not be transferred to management entity at the NT Note 12 As an implementation option to avoid premature transmission of information i e INFO4 layer 1 may not initiate transmission of INFO4 or send the primi tives PH Activate Indication and MPH Activate Indication to layer 2 and management respectively until a period of 100 ms has elapsed since the receipt of INFOS Such delay should be noted in ET if required Note 13 INFOO shall not be detected until at least 48 continuous binary ONEs have been received and the NT shall perfor
51. l send the updated status byte in ex change for the Command it receives and the INT condition by pulling the pin back to tri state The software driver must always look at the received status byte and if it is not 00 hex it may decide to take appropriate action D Channel Access The layer 2 HDLC driver communi cates with the layer 1 driver when D Channel packets are to be transmitted in the TE mode by means of the DREQ1 Sig naling packet and DREQ2 Data packet commands The EOM or CON status must be communicated to the layer 2 for either successful or failed transfer of the packet In the NT mode the D Channel packets are transferred to SID without interacting with a layer 1 driver In all modes the receive D Channel packets are passed straight to the layer 2 driver without interaction with the layer 1 driver Multiframe Channel Date Multiframe maintenance channel received data interrupt MFRxxxx and transmit data com mand MTFxxxx are transferred directly to the Management Entity task to process and take appropriate action 6 0 TERMINAL EQUIPMENT TE SOFTWARE DRIVER CONSIDERATIONS Topics are covered as the followings TEF States The 1 430 Activation Deactivation Requirements for TE e Suggested Flowchart to Implement X Activation Deactivation Procedure for NT www national com 24 TP3420A Internal State Machine 6 1 TE F States CCITT defines states that a TE would go through during the process of
52. m the actions specified in this table For conformance test purposes when in the state G3 with a sinusoidal signal having a voltage of 100 mV peak to peak superimposed on the received signal the NT shall react to INFOO by transmitting INFO2 after a period of time equal to or greater than 250 us It is recognized that the action in state G4 can not be observed or verified at the interface 7 3 Suggested Software Flowchart to Implement can connect to the same S bus It sets the SID in low power Activation Deactivation Procedure for NT mode by the PDN command The Digital Interface format The layer 1 Task software can be divided in 4 parts Initializa must be selected for the intended target system tion subroutine to configure the SID in a desired ready state the Interrupt Service Subroutine to response to interrupts is sued by the SID read the status of the SID and then set ap propriate software flags the Main Subroutine to check the status of these flags to control the state flow of the SID so as to adhere to the 1 430 Layer I Activation Deactivation Re quirements and the Local Activation Subroutine to detect a hook switch state or a Activation Deactivation Request from the upper layers to start a local activation A delay of 2 ms is recommended after the device is powered up by the PUP command Doing this allows the SID internal circuitry to have enough time to settle down Management Entity Layer 2 NT INITIALIZE PHAR Start Local Act
53. mitives a and the go to state Fn PH Al Primitive PH Activation Indication PH DI Primitive PH Deactivation Indication MPH AI Primitive MPH Activation Indication MPH DI Primitive MPH Deactivation Indication Primitive MPH Error Indication reporting error 12 Primitive MPH Error Indication reporting recovery from error MPH II c Primitive MPH Information Indication connected Primitive MPH Information Indication disconnected ST T3 Start time T3 Primitives are signals in a conceptual queue and will be cleared on recognition while the INFO signals are continuous signals that are available all the time Note 1 The term power could be the full operational power or backup power Backup power is defined such that it is enough to hold the value in memory and maintain the capability of receiving and transmitting lay 2 frames associated with procedures Note 2 The procedures described in this table require the provision of power source 1 and power source 2 to enable their complete operation A TE that determines it is connected to an NT not providing power source 1 or 2 should default to the procedures described in Table C 1 1 430 Note 3 This event reflects the case where a signal is received and the TE has not yet determined whether it is INFO2 or INFO4 Note 4 If INFO2 or INFO4 is not recognized within 5 ms after the appearance of a signal TE shall go
54. mmendation 1 430 as the state that an NT would go through to Activate Deactive the S interface loop The software driver may need additional internal states as described below G1 Deactivated condition Idle state i e layer 1 is not ready to transmit data G2 The activation of layer 1 was initiated by TE or NT the NT is waiting for INFO3 from a TE Pending Activa tion G3 Active state of NT Activated G4 When the NT wishes to deactivate it may wait for a timer to expire before returning to the deactivated F2 1 PowerDown Low Power Mode Deactivated 001 Sending INFOO PDN 12 or 14 F3 up Acknowledge 010 Sending INFOO AR 12 AR IA amp AR AI 74 10 DR DI F7 Activated 110 Sending INFO3 10 or DR DI 14 Al F8 Lost Framing 111 Sending INFOO 010730 73 FIGURE 30 Internal State Machine Diagram state G1 to prevent unintentional reactivation 1 430 in Note 2 of NT Activation Deactivation also specifies that the value of this timer namely T2 can be 0 sec onds if the NT is able to unambiguously recognize INFO1 The TP3420A in NT mode satisfies this condi tion hence state G4 is equivalent to state G1 Additional State for SID INITIALIZE SID initialization for NT mode POWER TP3420A is in Power Down mode In this DOWN mode the SID will detect the present of a sig nal on the line b
55. must take place for the TE initiated activation of the S interface SIDE TP3420A SID is first powered up and then the AR command is sent This forces INFO1 pattern onto the S interface towards the NT The TP3420A on the NT side senses the INFO1 and issues an LSD interrupt to the local control ler On powering up the SID the AP byte in the status register is set and the local HPC must re spond by sending the AR command This causes the NT SID to send INFO2 frames on the S inter face The TE SID upon recognition of INFO2 frames sends frames on the 5 interface NT SIDE Upon recognizing INFO3 frames the NT SID is sues an Al interrupt to the processor to indicate pending activation Now the HPC repeats the AR command in the TP3420A control register and SID sends INFO4 frames on the S interface TE SIDE The TE SID now receives INFO4 frames and is NT SIDE sues an Al indication to the local processor NT SIDE The SID issues an Al indication to the local pro cessor At this point the S interface is activated 5 2 S Interface Loop Activation Initiated from the NT End Figure 21 illustrates various commands and status indica tions and resultant INFO signals for a successful activation of the S interface for the case when a NT has initiated acti vation procedure This discussion however does not indicate the timers that are required in an activation procedure see Section 6 The following sequence of ev
56. n AMI line coding Various channels are combined to form the 192 kb s aggregate rate including 2 B channels each of 64 kb s and 1 D channel at 16 kb s In addition the 800 b s multiframe channels for layer 1 maintenance is provided All 1 430 wiring configurations are supported by the SID in cluding the Passive Bus for up to 8 TE s distributed within 200 meters of low capacitance cable and point to point con nections up to at least 1500 meters Adaptive signal process ing enables the device to operate with low bit error rates on any of the standard types of cable pairs commonly found in premise wiring installations This user s guide is intended to complement the device data sheets and is primarily aimed at ISDN TE NT1 NT2 and TA designs that incorporate SID S T transceivers The user should refer to the TP3420A TP3076 ISDN COMBO and HPC16400E data sheets for specific functions supported by these devices 2 0 LINE INTERFACE AND TRANSMISSION PERFORMANCE The components that are integral parts of the system design around the S T interface and work in conjunction with the SID are dealt with in this section Choice of the appropriate components will lead to reliable equipment design and supe rior performance 2 1 Master Clock Source The clock source for TP3420A may be provided with a com mercially available crystal or an external clock source meet ing the frequency requirements as explained in the following sectio
57. n medium Pro tection circuits that are external to the device are recom mended on both the primary and secondary sides of the line transformer Figure 2 provides a full protection circuit for the SID in TE mode The diode stacks at the Lo and Li pins of the device are primarily provided to offer low impedance paths to electrical surges On the transmit side in a TE they also avoid the clamping of the signals from other TE s and ensure that the minimum output impedance requirements are met even if Vcc is lost In NT LT applications only a single diode from each Lo pin to is required External resistors in the receive path of the SID limit the surge current through the di odes and also form part of the low pass noise limiting input filter This circuit can withstand at least 1000V pulses on the S interface All the diodes in this circuit are of the type 1N4004 Low capacitance diodes are necessary to avoid ex ceeding the maximum allowed capacitance for the complete connecting cord and circuit impedance For surge protection on exposed wiring interfaces a low ca pacitance gas discharge tube should be added across the terminals as shown in Figure 2 In addition to surge protec tion the transformer must be protected against power line faults by the addition of fuses or low value lt 100 fusible re sistors The series resistance of the protection must how ever be taken into account when specifying the resistance of the transformer w
58. nal com 3 0 TP3420 DIGITAL INTERFACE To retain the flexibility of interfacing the TP3420A with a va riety of other products two digital interfaces are provided on this device The first interface is called the Digital System In terface DSI and is for synchronous transfer of B and D channel information in one of the several popular schemes which encompass proprietary frame structures such as COMBO IOM SLD and IDL The second interface is Nation al s popular MICROWIRE PLUS interface which provides a means for synchronous serial data transfer between a micro controller and one or more peripheral devices and is used for device mode control purposes This interface can work in the ALTERNATE MICROWIRE mode which is compatible with the Motorola SCP See TP3420A Data Sheet for details 3 1 Digital System Interface Formats The Digital System Interface DSI combines B1 B2 and D channel data onto common pins Br and Bx to provide maximum flexibility At this interface phase skew between transmit and receive directions may be accommodated at TE Mode DSI Master TEM 2B D IN 2B D OUT 8 KHz FRAME SYNC DENx 010730 11 the line card or 1 2 end since separate frame sync inputs FSa and FSb are provided Each of these synchronizes a counter which gates the transfer of B1 and B2 channels in consecutive time slots across the digital interface The serial shift rate is determined by the BCLK input and may be any frequency fr
59. nel bits from its buffer beginning with the opening flag The SID also now restarts pulsing DENx to fetch further D channel bits from the HDLC to the SID transmit buffer al ways 2 bits per 125 us frame D channel data now flows from the HDLC through SID onto the S interface until either e BITS TEg E s Ki BIT COLLISIONS OCCUR IN D CHANNEL ONLY X BITS TE TO NT Times SID detects that it has lost a collision with another so it stops pulsing DENx transmits 1 s in the following D bit posi tions on the S interface and interrupts the uP with a CON message or the SID detects the closing flag passing through onto the S interface forces 1 s into the D channel after the closing flag stops pulsing DENx and sends an EOM interrupt to the UP Note that the uP cannot follow immediately with another packet because the successful TE must now decrement its priority and check that no other TE starts using the D channel the SID does this automatically Thus TE s wait ing to send signaling packets all succeed in order first and data packets are only sent when no TE has a signaling packet pending NT FROM NETWORK TO NEWWORK TE D BITS NT TO TE EE CHO DECISION Eod 27 O s BEAT 1 s 1 s ARE TRI STATE YES SEND NEXT D BIT STOP PACKET SEND 15 JOIN THE QUEUE COUNT CONSECUTIVE 1 s ALL TRANSMITTING TE s COMPARE
60. ns 2 1 1 Crystal Oscillator The SID clock source may be either a quartz crystal operat ing in parallel mode or an external signal source at 15 36 MHz The complete oscillator crystal plus the oscillator cir cuit must meet a frequency tolerance specification of 100 ppm total to comply with the CCITT 1 430 specification for TE applications The frequency tolerance limits span the condi tions of full operating temperature range commercial or in dustrial and effects due to aging and part to part parameter variations The crystal is connected between pin 5 MCLK XTAL and pin 6 XTAL2 with a 33 pF total capacitance from each pin to ground as shown in Figure 1 The external capacitors must be mica or high Q ceramic type The use of NPO Negative Positive Zero coefficient capacitors is highly rec ommended to ensure tight tolerance over the operating tem perature range The 33 pF capacitance includes the external capacitor plus any trace and lead capacitance on the board Crystal Requirements Nominal frequency of 15 360 MHz frequency tolerance ac curacy temperature and aging less than 60 ppm with Rg lt 1500 C 20 pF parallel mode CO shunt capacitance lt 7 pF An external circuit may be driven directly from the pin XTAL2 pin 6 provided that the load presented is greater than 50 shunted by a total of 33 pF of capacitance Crystal oscillator board layout is critical and should be de signed with short trac
61. number of programmable functions in cluding the transmit and receive gains may be controlled via a serial control port Please refer to TP3076 data sheet for more details www national com SZ TEN1 PX CFLG1 XMTENABLE SX RHCK1 HDLC1 RX1 RCVENABLE XI XMTENABLE RX2 TEN2 HDLC1 RCVENABLE REN2 RHCK2 010730 21 Note All switches are independent This diagram does not show ANDing of internal and external enables FIGURE 13 HPC16400E Serial Decoder Block 13 www national com 40 pue 3 ui uoneorddy jeoid pt 34n5lJ uod 3HIMOHOIIN esn s10sseooJdoJolu 089 JO 98X Dun 6 910N 01 10 seot ep O10H dOS LIION 01 GIS OSN 166 995 8 SION JO PNOO eur vOZr d 1 228 998 e pue 1euuojsuej 7522 BION eui snq 3HIMOHOIIN eui 12euuoo 920641 ueuM 9 NON 22 06 010 ALON 11049 ol 3951 ak VOUrEdL 3183 02 90 9 310N adog ZHN 96251 AS uonoejoJg eoepeju eur 995 G BION jo INN eui si YAMS e jesseoeu
62. ollowing com mand sequence NTA or NTF PUP AR Receive status AP AR receive sta tus Al The B channels are enabled B1E B2E to transfer data on the B channels Data can be sent or received on the D chan nel at 16 kbps B and D channel data fed in at the Bx input is returned on the Br output after being looped at the external line interface BCLK and FS signals need to be supplied to the SID operating in NT mode 9 2 Monitor Mode Activation The SID device may be configured for applications where D and or B channels may be monitored in the upstream direc tion on an S interface pair as shown in Figure 43 The SID is to be first configured into TEM mode for this application and then MMA is written into the command register This puts the TP3420A into a psuedo NT mode in which it receives and activates on the incoming INFO3 frames Note that in this application of the device only the receiver section is actively connected to the S interface This feature is targetted at ap plications where B and D channels are monitored for net work analysis as in protocol analyzers and line testers Line monitoring in the downstream direction requires another de vice operating normally in TE Mode 43 www national com TP3420A 5 Interface Device SID User s Guide TP3420 1 NT MODE 010730 66 FIGURE 42 External Loopback Activation 5420 1 Lo i 5420 1 FN TP3420 1 TEM MMA 01073
63. om 256 kHz to 4 096 MHz Thus for applications on a PABX line card in NT mode the B1 B2 and D channel slots can be interfaced to a TDM bus and assigned to a time slot At the TE end FSa is an output indicating the start of both the transmit and receive B channel data transfers BCLK is also an output at the serial data shift rate which is depen dent on the DSI format selected Figure 10 illustrates the di rections of BCLK FSa and FSb clocks depending on the de vice mode TEM and TES or NT mode respectively Four multiplexed formats of B1 B2 and D channel data are supported by TP3420A SID and selection of these formats is via the control register NT Mode DSI Slave NTA or NTF and TE Mode DSI Slave TES TP3420A SS TP3420A 2B D OUT 8 KHz TE FRAME SYNC BCLK NT BCLK SCLK 010730 12 FIGURE 10 TP3420 SID Digital System Interface www national com Format 1 0 010730 13 Format 2 O09 010730 14 3 ee s Format 4 2277 D O 077774 DEN l FS 1 8 FIGURE 11 Digital System Interface Formats NT and TES Modes www national com 10 Format 1 CR o 5 270 O OAN Format 2 UUW BCLK FS 5 ER O j EEN Format 3 BCLK FS xj 77 9 777777 5 Format A XK morc 010730 20
64. on Initiated from the TE End 5 2 S Interface Loop Activation Initiated from the NT End 5 3 S Interface Loop Deactivation Initiated from the NT Side 5 4 D Channel Request and Flow Control TP3420A 5 5 Software Driver Considerations 6 0 TERMINAL EQUIPMENT TE SOFTWARE DRIVER CONSIDERATIONS 6 1 TE F States 6 2 1 430 Activation Deactivation Requirements for Interface and COMBO is a registered trademark of National Semiconductor Corporation 1999 National Semiconductor Corporation 010730 National Semiconductor Application Note 665 R Paripatyadar C Stacey Victor Thang Van July 1994 6 3 Suggested Software Flowchart to Activation Deactivation Procedure for TE 6 3 1 Initialization Subroutine 6 3 2 Interrupt Service Subroutine 6 3 3 Main Subroutine 6 3 4 Local Activation Subroutine 6 4 TP3420A Internal F State Machine Diagram 7 0 NETWORK TERMINATION NT SOFTWARE DRIVER CONSIDERATIONS 7 1 The G States 7 2 1 430 Activation Deactivation Requirements for NTs 7 3 Suggested Software Flowchart to Implement Activation Deactivation Procedures for NT 7 3 1 Initialization Subroutine 7 3 2 Interrupt Service Subroutine 7 3 3 Local Activation Deactivation Subroutine 7 3 4 Main Subroutine 7 4 TP3420A Internal G State Machine Diagram 8 0 SID TEST LOOPBACK MODES 8 1 Normal Data Mode No Loopbacks 8 2 System Loopback Mode LBS 8 3 System Loopback Mode LBB1 LBB2 8 4 Line Loopback Mode LBL1 LBL2 9 0 ADDITION
65. otal Capacitance at the Network End At the network end there is no cord specified but the 25000 minimum impedance limit extends up to 106 kHz The total capacitance must therefore be 600 pF hence 25 8 x 4 Cd lt 600 pF which gives Cd lt 468 pF By restricting the Cd for the transformer to be lt 220 pF suf ficient margin is allowed for miscellaneous capacitances and flexibility in the protection circuit arrangement Line Transformer Winding Resistance Rp and Rs Since the device output driver is a voltage limited current source type the value of the DC resistance of the trans former secondary is not critical The DC resistance of the primary side of the transformer does affect the load seen by the current source driver and hence needs to be constrained in order to meet the overall specification of 10 maximum variation of the output pulse height when terminated into 500 Line Transformer Leakage Inductance Unlike competing devices the TP3420A controls the output pulse transition times and hence the leakage inductance is not critical Overshoot and ringing are within the pulse mask for values in excess of 50 pH Longitudinal Balance The longitudinal balance specification is as follows 10 kHz to 300 kHz gt 54 dB 300 kHz to 1 MHz Value decreasing at 20 dB per decade Bifilar windings on the line side are necessary to meet these requirements The transformer must connect to the TP3420A as shown in AN 872
66. sheet If the status indicates the F6 state do nothing how ever if the state is still F4 or F5 write a DR command to SID to abort the activation attempt 29 www national com Processing SID Activation Flags AR RS T3 Reset A Flag RS tspurious Reset RS tspurious ST tspurious Reset DI Flag Reset El Flag Filtering False LSD vus PUP wait 2ms AR ST T3 Reset 150 FILTERED Reset LSD I Flag I ST hen Set LSD_FILTERED I Flag I t Expired Reset LSD_FILTERED Flag L tspurious MPH DI PH DI Expired PDN RS Reset Timer ST Start Timer 010730 71 FIGURE 28 Main Task for the Software Driver www national com 30 6 3 4 Local Activation Subroutine Management Entity or Layer 2 can request a local activation by issuing a MPH AR or PH AR while the SID is in state F3 Deactivated This assumes the SID has been powered up at least 2 ms so that the internal circuitry has enough time to settle down The software driver then sends an AR com mand to bring the SID to state F4 Awaiting signal and at the same time start the timer T3 The SID waits for either INFO2 to bring it to state F6 Identifying Input or INFO4 to directly bring it to state F7 Activated Suggested actions af ter T3 expiry are indicated above Start Local Activation PUP Wait 2ms AR MPH
67. than 22 mH gt 2 5 between 20 kHz and 80 kHz This is necessary to meet the low fre quency output impedance specification in 1 430 of gt 25000 for frequencies 20 kHz The primary winding of the trans former the main component of inductance should therefore have greater than 22 mH of inductance Lp The secondary winding inductance Ls is generally 4 Lp for the 1 2 trans former and Ls Lp for the 1 1 transformer Total Capacitance at the Terminal End 1 430 specifies that the impedance into the Transmitter and Receiver must be gt 25000 for frequencies lt 80 kHz in a TE The capacitance dominates this impedance and must be limited to 795 pF There are various contributors to this output capacitance The TE cord 300 pF for the 7m length capacitance or 350 pF for the 10m length the device driver pins 10 pF 25 pF The protection circuit consisting of shunt ing diodes 8 pF The 1 2 transformer multiplies the capacitance on its sec ondary connections by 4 when observed from the line side An allowable maximum for other distributed stray capaci tances Cd is given by 7m Cord Case 25 8 x 4 Cd 300 lt 800 pF which gives Cd lt 368 pF 10m Cord Case 25 8 x 4 Cd 350 800 pF which gives Cd lt 316 pF This is the most stringent case and determines the maximum allowable distributed capacitance Cd for the transformer and other miscellaneous capacitances T
68. tic Buffer TX Side 17 www national com 5 MOIN OZPEdL 21 SHNDIS 92 0 Z0LONV INI 94 02 24 59 WEN ISS LS SOHy 199 18 www national com 4 0 DIGITAL CONTROL INTERFACE The digital control interface for the TP3420A SID is compat ible with National s industry standard MICROWIRE PLUS interface This approach provides easy integration into al ready existing microcontroller applications 4 1 The MICROWIRE Bus The MICROWIRE compatible interface on the TP3420A is provided for microprocessor control of various functions in the device MICROWIRE is used for slow speed control and status data while all the real time user data in B and D channels is routed the DSI so that speed of response to interrupts is not a critical issue In the MICROWIRE control interface implementation in the TP3420A with reference to the control interface timing shown in Figure 17 the following actions take place Data transfers consist of a single byte shifted into the control register of SID via the CI pin while a single byte is shifted out from the status register of SID via the CO pin CS is to be pulled low for 8 clock cycles of CCLK Data waiting to be received into Cl is clocked on rising edge of CLK Data waiting to be transmitted out of CO is clocked out on the falling edge of CCLK INT goes low to alert the microprocessor when changes in the st
69. transferred to the output parallel to serial converter as a complete word is shifted out The wander detector cir cuit controls the transfers to the parallel to serial converter in such a way as to absorb wander by varying delays through the elastic store The SID is designed to absorb the CCITT wander specified over 24 hours which can be up to 18 us peak to peak TP3420A will optionally generate a Slip interrupt to indicate clock slip condition in the Tx or Rx directions Please see TP3420 Data Sheet for more information www national com CLOCK MASTER CLOCK SCLK TP3420A SOURCE SELECT FSa b TES MODE BCLK TRUNK LINES BCLK TO CENTRAL e g 2 048 MHz SCLK TP3420A OFFICE S 8 kHz FSa b TES MODE T INTERFACE BCLK N TRUNKS SCLK TP3420A FSa b TES MODE BCLK SWITCH MAIRIE TP3420A AND NTS MODE CONTROL SUBSCRIBER LINES TP3420A S INTERFACE NTS MODE i M LINES AN010730 23 Note 10 FSa b to each device are offset to indicate the time slot to be used Note 11 SCLK frequency is set by selecting DIF format e g Format 1 SCLK 2 048 MHz FIGURE 15 TP3420A Showing NT 2 Synchronization www national com 16 WANDER DETECTOR AND ELASTIC E BUFFER CONTROL Bx ELASTIC DSI FORMATTER 1 430 MUX BUFFER 1 430 CIRCUITS 010730 24 125 uSECS 24 HOUR FRAME SYNC WANDER Rei 9 LSECS LIMITS OF CCITT 0 502 SPECS 010730 25 FIGURE 16 TP3420A Slave Slave Mode and Elas
70. ut not be able to identify it 7 2 1 430 Activation Deactivation Requirements for NTs The Activation Deactivation procedure for NT is defined by the 1 430 document It is summarized in a Finite State Matrix Table Table 7 is a modified version where the internal commands states of the TP3420A are superimposed in the table where appropriate to relate to the 1 430 states and primitives They are located in the lower part of the boxes The TP3420A commands and status have the prefix SID after which the SID command is enclosed in a pair of brack ets to distinguish from its returned status not enclosed by brackets For example SID AR is the TP3420A Activation www national com Request command whereas SID LSD is the Signal Line De tection interurpt The SID returned status and the applied commands should occur in the order indicated In addition there are a few timers associated with this table and are de scribed in the notes below the table The TP3420A can uniquely identify an INFO1 signal hence T2 timer is not needed This implies that state G4 can be ig nored or is replaced with state G1 In this case a MPH Deactivate Request would cause a direct transition from state G2 or G3 to state G1 TABLE 7 Event PH Act Request Note 13 MPH Deact Request Note 13 Expiry 1 Note 9 Expiry T2 Notes 9 13 Receiving INFOO Note 13 Receiving INFO1 Finite State Matrix for NTs to Reflect the Requirem
71. ypassed in this mode by selecting the NTF command In Fixed timing mode the DPLL is locked to TXCLK and TE TP3420A SID TP3420A SID has 2 RX CLK Timing Options 1 DPLL Adaptive timing locked to RX data Used in TE mode always Used in NT mode for point point only 15 36 MHz phased at 4 us with respect to the leading edge of the de rived clock Also in the fixed timing mode the equalizer is disabled 4 5 TP3420A Line Signal Detect LSD and Wake Up Signal for The Line Signal Detect circuit in the SID is active when the device is in the power down state Upon detecting a valid sig nal the LSD pin on the device is pulled low from its normally high impedance state and also the LSD bit in the Status Register is set The LSD pin may be used for waking up lo cal microprocessor from a low power idle mode and subse quently powering up SID itself The LSD pin goes into the high impedance state upon powering up PUP the SID and the LSD circuit in the device is disabled in powered up mode Figure 19 shows a simple concept of using the LSD pin on the TP3420A SID in waking up HPC16400E the local micro controller The LSD signal is tied to the NMI pin of the HPC16400E When a remote activation request is sensed by the SID it pulls the LSD pin low and the NMI pin detects the inverted LSD signal to wake up the HPC16400E The INT signal on the TP3420A SID may also be used for these wake up procedures because the LSD bit in

TP3420A S Interface Device (SID) User`s Guide

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