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NXP P89LPC924, P89LPC925 User`s Manual

1. Mnemonic Description Bytes Cycles Hex code ORL A Ri OR indirect memory to A 1 1 46 to 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 to 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to 1 1 66 to 67 A XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62 XRL dir data Exclusive OR immediate to direct 3 2 63 byte CLRA Clear A 1 1 E4 CPLA Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 Rotate A right RRA 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 to EF MOV A dir Move direct byte to A 2 1 E5 Move indirect memory to A MOV A Ri 1 1 E6 to E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 to FF MOV Rn dir Move direct byte to register 2 2 A8 to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct 2 2 86 to 87 byte MOV dir data Move immediate to direct byte 3 75 MOV Ri A Move A to indirect memory 1 F6 to F7 MOV Ri dir Move direct byte to indirect 2 2 A6 to A7 memory MOV Ri
2. gt chip reset Power on detet _ UART break detect EBAR AUXR1 6 __ _ Brownout detect reset BOPD Peono d Fig 12 Block diagram of reset 002aaa918 Table 29 Reset Sources register RSTSRC address DFh bit allocation Bit 6 5 4 3 2 1 0 Symbol BOF POF R_BK R_WD R_SF R_EX Reset x 1 1 0 0 0 0 1 The value shown is for a power on reset Other reset sources will set their corresponding bits Table 30 Reset Sources register RSTSRC address DFh bit description Bit Symbol 0 REX Description external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic 0 to the bit or a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set R_SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 R_WD Watchdog timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 3 R_BK break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software by writing a logic 0 to the bit or on a Power on reset 4 POF Power on Detect Flag When Power on Detect is activated the POF flag is set to indicate an initial power
3. Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 49 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual TX clock fl fl fl fl fl fl fl fl write to I SBUF shift ji fl fl i ji ji fl fl fl transmit start TD bt A DO X D1 X D2 X D3 X D4 X D5 X De X D7 X stop bit RX clock fl l l l fl fl fl l fl fl fl fl start shift l l l RI receive 002aaa926 Fig 21 Serial Port Mode 1 only single transmit buffering case is shown 10 12 More about UART Modes 2 and 3 Reception is the same as in Mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF TX clock fl fl fl fl I fl fl fl fl write to l SBUF shift I transmit start mm bit DO X DI X 02 X D3 X D4 X Ds X D6 X D7 K TBs Y stop bit A E INTLO 0 INTLO 1 RX clock J l l l I Il I I Il I Il star RxD 16 reset bit K DO X DI X D2 X D3 X D4 X D5 X 06 X D7 X _RB8 X stop bit shift Il Il C
4. 9 1 Real time clock source RTCS1 0 RTCCON 6 5 are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock then the RTC will use CCLK as its clock source 9 2 Changing RTCS1 0 RTCS1 0 cannot be changed if the RTC is currently enabled RTCCON O0 1 Setting RTCEN and updating RTCS1 0 may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 42 of 105 Philips Semiconductors UM10108 9 3 9 4 P89LPC924 925 User manual Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 6 0 and EA IENO 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the Watchdog timer It can also be a source to wake up the device Reset sources affecting the Real time clock Only power on reset will reset the Real time Clock and its associated SFRs to their default state Table 37 Real time Clock System Timer clock sources RTCS1 RTCSO FOSC2 FOSC1 FOSCO RTCS1 CPU clock source RTCCON 6 RTCCON 5 UCFG1 2 UCFG1 1 UCFG1 0 RTCCON 6 x X 0 0 CCLK 0 High frequency crystal x x
5. P89LPC924 925 User manual Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and the A D or DAC has been enabled Pins selected in ADINS will be 3 V tolerant provided that the A D is enabled and the device is not in power down otherwise the pin will remain 5 V tolerant 3 7 Power down and idle mode In idle mode the A D converter if enabled will continue to function and can cause the device to exit idle mode when the conversion is completed if the A D interrupt is enabled In Power down mode or Total Power down mode the A D does not function If the A D is enabled it will consume power Power can be reduced by disabling the A D Table 10 A D Control register 1 ADCON1 address 97h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENBI1 ENADCI1 TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 Reset 0 0 0 0 0 0 0 0 Table 11 A D Control register 1 ADCON1 address 97h bit description Bit Symbol Description 0 ADCS10 A D start mode bits 11 10 1 ADCS11 00 Timer Trigger Mode when TMM1 1 Conversions starts on overflow of Timer 0 Stop mode when TMM1 0 no start occurs 01 Immediate Start Mode Conversions starts immediately 10 Edge Trigger Mode Conversion starts when edge condition defined by bit EDGE1 occurs 2 ENADC1 Enable A D channel 1 When set 1 enables ADC1 Must also be set for D A operation of
6. 00000001cc 02 Miscellaneous Write Functions 02xxxx02ssddcc Where XXXX required field but value is a don t care ss subfunction code dd data cc checksum Subfunction codes 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 OC Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 OA Clear Configuration Protection Example 020000020347cc Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 89 of 105 Philips Semiconductors UM10108 Table 83 P89LPC924 925 User manual In system Programming ISP hex record formats Record type Command data function 03 Miscellaneous Read Functions 01xxxx03sscc Where XXXX required field but value is a don t care ss subfunction code cc checksum Subfunction codes 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 OC Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Manufacturer Id 11 Device Id 12 Derivative Id Example 0100000312cc 04 Erase Sector Page 03xxx
7. Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output PCLK Clock for the various peripheral devices and is CCLK 2 Oscillator Clock OSCCLK The P89LPC924 925 provides several user selectable oscillator options This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the FLASH is programmed and include an on chip Watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration When using an oscillator frequency above 12 MHz the reset input function of P1 5 must
8. 41 Real time clock system timer 41 Real time clock source 42 Changing RTCS1 0 42 Real time clock interrupt wake up 43 Reset sources affecting the Real time clock 43 UART ici were caaeatepe serie seine aps heal ee gle camer 44 Mode Orso eles ce ra e enue decd wise ae heave ae oa 44 Model is Akiak ore es pie ds AOR 44 Mode 2 rrar oe n ace puter Pantani 44 Mode 3 2ii jib bebe oti E aE 45 SFR space 202s eee eee eee 45 Baud Rate generator and selection 45 Updating the BRGR1 and BRGRO SFRs 45 Framing ClfOl sc cae ccke ead we eee es 46 Break detect 20000220 eee 46 More about UART Mode O 48 More about UART Mode 1 49 More about UART Modes 2 and3 50 Framing error and RI in Modes 2 and 3 with OM 2S Winco ia toe te alates ete en ae nonce 50 Break detect 20000020 eee 51 Double buffering 0000 51 Double buffering in different modes 51 Transmit interrupts with double buffering enabled Modes 1 2 and 3 0000 eee ee 51 The 9th bit bit 8 in double buffering Modes 1 2 and3 0000 52 Multiprocessor communications 53 Automatic address recognition 54 I C interface 000 c cece eee eee 55 I C Data register 0 0000 eee 56 I2C Slave Address register 56 I2C Control register 0005 56 I2C
9. If SMODO 1 it is set near the middle of the stop bit see SM2 SCON 5 for exceptions Must be cleared by software 1 Tl Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO bit in SSTAT register in the other modes Must be cleared by software 2 RB8 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired REN Enables serial reception Set by software to enable reception Clear by software to disable reception 5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 6 SMi With SMO defines the serial port mode see Table 46 SMO FE_ The use of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is read and written as SMO which with SM1 defines the serial port mode If SMODO 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART mode bits SMO and SM1 should be programmed when SMOD0 is logic 0 default m
10. Rev 02 2 March 2005 82 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual update flag for that location will be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 6 Bytes loaded into the page register do not have to be continuous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL 7 6 are used to select a page of code memory for the erase program function When the erase program command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either comp
11. SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be logic 0 in Mode 1 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 53 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 10 20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature
12. SMODO 0 SMOD0 1 receive 002aaa927 Fig 22 Serial Port Mode 2 or 3 only single transmit buffering case is shown 10 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 50 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 49 FE and RI when SM2 1 in Modes 2 and 3 Mode PCON 6 RB8 RI FE SMODO 2 0 0 No RI when RB8 0 Occurs during STOP bit 1 Similar to Figure 22 with SMODO 0 RI occurs during Occurs during STOP bit RB8 one bit before FE 3 1 0 No RI when RB8 0 Will NOT occur 1 Similar to Figure 22 with SMODO 1 RI occurs during Occurs during STOP bit STOP bit 10 14 Break detect A break is detected when 11 consecutive bits are sensed LOW and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 and 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device and force the device into ISP mode This occurs if the UART is enabled and the the EBRR bit AUXR1 6 is set and a break occurs 10 15 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be
13. register data if no error else error status Carry set on error clear on no error Erase Sector Page requires key Input parameters ACC 04h R7 OOH erase page or 01H erase sector R4 sector page address MSB R5 sector page address LSB Return parameter s R7 status Carry set on error clear on no error Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 95 of 105 Philips Semiconductors UM10108 Table 85 IAP function calls P89LPC924 925 User manual IAP function Read Sector CRC IAP call parameters Input parameters ACC 05h R7 sector address Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read Global CRC Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code Input parameters ACC 07h R4 address MSB R5 address LSB Return parameter s R7 data 16 16 User configuration bytes A number of user configurable features of the P89LPC924 925 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured t
14. 2 March 2005 77 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 77 Watchdog timeout vales PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in Watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK 2 Watchdog Nominal Clock 100 0 513 1 28 ms 85 5 us 255 131 073 327 7 ms 21 8 ms 101 0 1 025 2 56 ms 170 8 us 255 262 145 655 4 ms 43 7 ms 110 0 2 049 5 12 ms 341 5 us 255 524 289 1 315 87 4 ms 111 0 4097 10 2 ms 682 8 ms 255 1 048 577 2 62 s 174 8 ms 14 3 Watchdog clock source The Watchdog timer system has an on chip 400 KHz oscillator The Watchdog timer can be clocked from either the Watchdog oscillator or from PCLK refer to Figure 33 by configuring the WDCLK bit in the Watchdog Control Register WDCON When the Watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU After changing WDCLK WDCON 0 switching of the clock source will not immediately take effect As shown in Figure 35 the selection is loaded after a Watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the presca
15. 2004 All rights reserved User manual Rev 02 2 March 2005 25 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Fig 7 RTCCON 1 7 gt EX0 EX1 Pa on EBO RTCF KBIF WAKE UP ae A IF IN POWER DOWN ADONE EWDRT CMF2 CMF1 EC EA IEO 7 me ETO ET1 TI amp RI RI ES ESR TI INTERRUPT EST TO CPU s J H El2C ee a ADCI1 BNDI1 EAD 002aaa792 Interrupt sources interrupt enables and power down wake up sources 5 I O ports The P89LPC924 925 has three I O ports Port 0 Port 1 and Port 3 Ports 0 and 1 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 20 Table 20 Number of I O pins available Clock source Reset option Number of I O pins On chip oscillator or Watchdog No external reset except during power up 26 oscillator External RST pin supported 25 External clock input No external reset except during power up 25 External RST pin supported 24 Low medium high speed oscillator No external reset except during power up 24 external crystal or resonator External RST pin supported 23 1 Required for operation above 12 MHz Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 26 of 105 Philips Semiconduct
16. If the Active Write Enable AWE bit is a logic 1 then the state of the internal WE flag can be controlled by the user The WE flag is SET by writing the Set Write Enable 08H command to FMCON followed by a key value 96H to FMDATA MOV FMCON 08H MOV FMDATA 96H The WE flag is CLEARED by writing the Clear Write Enable OBH command to FMCON followed by a key value 96H to FMDATA or by a reset MOV FMCON 0BH MOV FMDATA 96H The ISP function in this device sets the WE flag prior to calling the IAP routines The IAP function in this device executes a Clear Write Enable command following any write operation If the Write Enable function is active user code which calls IAP routines will need to set the Write Enable flag prior to each IAP write function call Configuration byte protection In addition to the hardware write enable protection described above the configuration bytes may be separately write protected These configuration bytes include UCFG1 BOOTVEC and BOOTSTAT This protection applies to both ISP and IAP modes and does not apply to ICP or parallel programmer modes Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 92 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual If the Configuration Write Protect Writ CWP bit in BOOTSTAT 6 is a logic 1 writes to the configuration bytes are disabled If the Configuration Write Protect
17. The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock CCLK or the XTAL1 2 oscillator provided that the XTAL1 2 oscillator is not being used as the CPU clock If the XTAL1 2 oscillator is used as the CPU clock then the RTC will use CCLK as its clock source regardless of the state of the RTCS1 0 in the RTCCON register There are three SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload HIGH bits 22 15 RTCL Real time Clock counter reload LOW bits 14 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0O bit The Real time Clock is a 23 bit down counter initialized to all 0 s when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with logic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RTCF RTCCON 7 will be set Power on reset XTAL2 XTAL1 RTC Reset Reload on underflow 23 bit down counter LOW FREQ MED FREQ HIGH FREQ CCLK internal oscillators Wake up from power down hei RTCF Interrupt if enabled l shared with WDT ERG RTC underflow flag RTC enable RTC clk select 002aaa924 Fig 18 Real time clock system timer block diagram
18. e DAC output to a port pin with high output impedance e Clock divider Power down mode Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 18 of 105 Philips Semiconductors UM1 01 08 3 2 3 2 1 3 2 2 3 2 3 3 2 4 P89LPC924 925 User manual A D operating modes Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel See Table 6 An interrupt if enabled will be generated after the conversion completes The input channel is selected in the ADINS register This mode is selected by setting the SCAN1 bit in the ADMODA register Table 6 Input channels and Result registers for fixed channel single auto scan single and autoscan continuous conversion modes Result register Input channel Result register Input channel AD1DATO AD10 AD1DAT2 AD12 AD1DAT1 AD11 AD1DAT3 AD13 Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the four result registers Table 7 An interrupt if enabled will be generated after every four conversions Additional conversion results will again cycle through the four result registers overwriting the previous results Continuous conversions cont
19. is stable Table 74 Watchdog timer configuration WDTE UCFG1 7 WDSE UCFG1 4 FUNCTION 0 xX The Watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect The Watchdog reset is enabled The user can set WDCLK to choose the clock source The watchdog reset is enabled along with additional safety features 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once 3 WDRUN is forced to 1 and cannot be cleared by software Watchdog oscillator PCLK PRE2 PRE1 PREO WDCLK after a Watchdog feed sequence DECODE Fig 33 Watchdog prescaler TO WATCHDOG DOWN COUNTER after one prescaler count delay 002aaa938 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 75 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 14 2 Feed sequence The Watchdog timer control register and the 8 bit down counter See Figure 34 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a Watchdog reset the Watchdog timer n
20. operation If the factory default setting for the Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H VDD ae tRH RST t RL 002aaa912 Fig 36 Forcing ISP mode In system programming ISP In System Programming is performed without removing the microcontroller from the system The In System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC924 925 through the serial port This firmware is provided by Philips and embedded within each P89LPC924 925 device The Philips In System Programming facility has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXD RXD and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Koni
21. page address MSB R5 page address LSB R7 pointer to data buffer in RAM F1 0h use IDATA Return parameter s R7 status Carry set on error clear on no error Read Version Id Input parameters ACC 01h Return parameter s R7 IAP code version id Misc Write requires key Input parameters ACC 02h R5 data to write R7 register address 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 OC Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 OA Clear Configuration Protection Return parameter s R7 status Carry set on error clear on no error Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 94 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual Table 85 JAP function calls IAP function IAP call parameters Misc Read Input parameters ACC 03h R7 register address 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 OC Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 Return parameter s R7
22. the user code should check the carry flag after each erase programming or CRC operation to see if an error occurred If the operation was aborted the user s code will need to repeat the operation Table 84 IAP error status Bit Flag Description 0 Ol Operation Interrupted Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle 1 SV Security Violation Set if program or erase operation fails due to security settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted 3 VE Verify error Set during IAP programming of user code if the contents of the programmed address does not agree with the intended programmed value IAP uses the MOVC instruction to perform this verify Attempts to program user code that is MOVC protected can be programmed but will generate this error after the programming cycle has been completed 4 7 unused reads as a logic 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 93 of 105 Philips Semiconductors UM10108 Table 85 IAP function calls P89LPC924 925 User manual IAP function Program User Code Page requires key IAP call parameters Input parameters ACC 00h R3 number of bytes to program R4
23. used as a standard port pin or a clock output When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at powerup until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage XTAL1 High freq XTAL2 Med freq gt RTC o lt Low freq m c y LK LK Jee s oeu a OSCILLATOR 7 3728 MHz D f l N WATCHDOG gt OSCILLATOR 400 kHz PCLK lS 3 TIMER 0 and TIMER 1 BAUD RATE 12C GENERATOR y UART 002aaa790 fH Fig 5 Block diagram of oscillator control Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 16 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 2 7 Oscillator Clock OSCCLK wake up delay The P89LPC924 925 has an internal wake up timer that delays the clock until it stabilizes depending to the clock source used If the clock source is any of the three crystal selections the delay is 992 OSCCLK cycles plus 60 us to 100 us If the clock source is either the internal RC oscillato
24. written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out 10 16 Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 10 17 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when double buffering is enabled the TX interrupt is generated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a TX interrupt is generated immediately 4 If there is more data go to 6 else continue 5 If there is no more data then If DBISEL is logic 0 no more interrupts will occur Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 51 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual If DBISEL is logic
25. 0 Switched to not addressed SLA mode no recognition of own SLA or General call address no I2DAT action or Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR O 1 no I2DAT action or ae Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action i Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free C8H Last data byte in I2DAT has been transmitted AA 0 ACK has been received No I2DAT action or Switched to not addressed SLA mode no recognition of own SLA or General call address no I2DAT action or Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR O 1 no I2DAT action or Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action i Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free 12
26. 1 l XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the FLASH configuration It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the real time clock system timer Vss 5 l Ground 0 V reference Vpop 15 l Power Supply This is the power supply voltage for normal operation as well as Idle and Power down modes 1 Input Output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 6 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual CODE FLASH 256 BYTE i 4 kB 8 kB i DATA RAM PORT 3 CONFIGURABLE I Os PORT 1 CONFIGURABLE I Os PORT 0 CONFIGURABLE I Os KEYPAD INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER CONFIGURABLE OSCILLATOR CRYSTAL OR RESONATOR Fig 2 P89LPC924 925 block diagram HIGH PERFORMANCE ACCELERATED 2 CLOCK 80C51 CPU z INTERNAL BUS gt gt gt gt ANALOG COMPARATORS CPU CLOCK ADC1 DAC1 ON CHIP RC OSCILLATOR POWER ON RESET BROWNOUT RESET I I I I I i I POWER MONITOR i I ji I I I I I I 002aaa786 Koninklijke Philips Electronics N V
27. 1 and INTLO is logic 0 a TX interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a TX interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a TX interrupt is generated already with the UART not knowing whether there is any more data following 6 If there is more data the CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a TX interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a TX interrupt will occur at the end of the STOP bit of the data currently in the shifter Gotos3 write to SBUF Tx interrupt TxD write to SBUF Tx interrupt TxD write to SBUF Tx interrupt Fig 23 Transmission with and without double buffering Single buffering DBMOD SSTAT 7 0 early interrupt INTLO SSTAT 6 0 is shown LETT LE LEE Lo i f i j i f i I I I I I I I l Double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown no ending Tx interrupt DBISEL SSTAT 4 0 i i Double buffering DBMOD SSTAT 7 1 early
28. A with carry 2 1 35 ADDC A Ri Add indirect memory to A with 1 1 36 to 37 carry ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with 1 1 98 to 9F borrow SUBB A dir Subtract direct byte from A with 2 1 95 borrow SUBB A Ri Subtract indirect memory from A 1 1 96 to 97 with borrow SUBB A data Subtract immediate from A with 2 1 94 borrow INCA Increment A 1 1 04 INC Rn Increment register 1 1 08 to OF INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DEC A Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DA A Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 to 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 to 57 ANL A data AND immediate to A 2 1 54 ANL dir A AND A to direct byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 to 4F ORL A dir OR direct byte to A 2 1 45 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 99 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual Table 96 Instruction set summary
29. Analog comparators Two analog comparators are provided on the P89LPC924 925 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 69 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 12 1 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Table 67 The overall connections to both comparators are shown in Figure 31 There are eight possible configurations for each comparator as determined by the control bits in the corresponding CMPn register CPn CNn and OEn These configurations are shown in Figure 32 When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared befor
30. C bus may operate as a master and as a slave In the slave mode the 2C bus hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I2C bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer logic 0 write logic 1 read E from Master to Slave C1 from Slave to Master Fig 29 Format of Slave Transmitter mode seems A fom AT DA data transferred n Bytes acknowledge A acknowledge SDA LOW A not acknowledge SDA HIGH S START condition P STOP condition 002aaa933 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 62 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual KL o I2ADR ADDRESS REGISTER P1 3 SDA OUTPUT STAGE AN P1 2 SCL OUTPUT TIMER 1 OVERFLOW I2CON I2SCLH I2SCLL STATUS BUS I2STAT Fig 30 I2C serial interface block diagram BIT COUNTER ARBITRATION SERIAL CLOCK GENERATOR SCL DUTY CYCLE REGISTERS INTERNAL BUS SHIFT REGISTER
31. CIN2B KBI1 AD10 P0 2 CIN2A KBI2 AD1 1 P0 3 CIN1B KBI3 AD12 P0 4 CIN1A KBI4 AD13 DAC1 P0 5 CMPREF KBI5 XTAL1 P3 1 6 Vpp CLKOUT XTAL2 P3 0 P0 6 CMP1 KBI6 P89LPC924FDH P89LPC925FDH INT1 P1 4 8 PO 7 T1 KBI7 SDA INTO P1 3 9 P1 0 TXD SCL TO P1 2 10 P1 1 RXD 002aaa787 Fig 1 TSSOP20 pin configuration Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 3 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 1 Pin description Symbol Pin Type Description PO 0 to PO 7 1 0 Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below 1 1 0 P0 0 Port 0 bit 0 O CMP2 Comparator 2 output l KBIO Keyboard input 0 20 1 0 P0 1 Port O bit 1 l CIN2B Comparator 2 positive input B l KBI1 Keyboard input 1 l AD10 ADC1 channel 0 analog input 19 V0 P0 2 Port 0 bit 2 l CIN2A Comparator 2 positive inp
32. Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description 0 TOM2 Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the Timer 0 mode see Table 34 1 3 reserved 4 T1M2 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Table 34 The following timer modes are selected by timer mode bits TnM 2 0 000 8048 Timer TLn serves as 5 bit prescaler Mode 0 001 16 bit Timer Counter THn and TLn are cascaded there is no prescaler Mode 1 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TLn when it overflows Mode 2 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits see text Timer 1 in this mode is stopped Mode 3 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see Section 8 5 111 Reserved User must not configure to this mode 5 7 reserved 8 1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 13 shows Mode 0 operation In this mode the Timer register is configured as a 1
33. ENBI1 ENADCI TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000 1 ADINS A D input select A3H ADI13 ADI12 ADI11 ADI10 00 00000000 ADMODA A D mode register A COH BNDI1 BURST1 SCC1 SCAN1 00 00000000 ADMODB A D mode register B A1H CLK2 CLK1 CLKO ENDAC1 BSA1 00 000x0000 AD1BH A D_1 boundary HIGH C4H FF 11111111 register AD1BL A D_1 boundary LOW BCH 00 00000000 register AD1DATO A D_1 data register 0 D5H 00 00000000 AD1DAT1 A D_1 data register 1 D6H 00 00000000 AD1DAT2 A D_1 data register 2 D7H 00 00000000 AD1DAT3 A D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS ool 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 BRGROI Baud rate generator rate BEH 00 00000000 LOW BRGR1 2 Baud rate generator rate BFH 00 00000000 HIGH BRGCON Baud rate generator control BDH SBRGS BRGEN 00 XXXXXX00 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 OE1 CO1 CMF1 ooi xx000000 CMP2 Comparator 2 control register ADH CE2 CP2 CN2 OE2 CO2 CMF2 oo xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer HIGH 83H 00 00000000 DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H 00 00000000 s1O ONPUOTIWAS sd jiyd Jenuew 13SN S26 7e6Dd 168d SOLOLINN jenuew Jesp S002 Yue Z 20 ASH paniased SIYGH IY 700 A N SO U
34. Keypad Interrupt 7 KBMASK 7 When set enables PO 7 as a cause of a Keypad Interrupt 1 The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective 14 Watchdog timer WDT The Watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The Watchdog timer can only be reset by a power on reset 14 1 Watchdog function The user has the ability using the WDCON and UCFG1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow In addition there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of the WDTE bit The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WOCON need to be followed by a feed sequence see Section 14 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler Koninklijke Philips Electronics N V 2004 All rights reserve
35. R4 get high address MOV FMADRL R5 get low address MOV A R7 i MOV R0 A get pointer into R0 LOAD_PAGE MOV FMDAT R0 write data to page register INC RO point to next byte DJNZ R3 LOAD_PAGE do until count is zero MOV FMCON EP else erase and program the page MOV R7 FMCON copy status for return MOV A R7 read status ANL A 0FH save only four lower bits INZ BAD CLR c clear error flag if good RET sand return BAD SETB C set error flag RET sand return A C language routine to load the page register and perform an erase program operation is shown below include lt REG931 H gt unsigned char idata dbytes 64 data buffer unsigned char Fm_stat status result bit PGM_USER unsigned char unsigned char bit prog_fail void main prog_fail PGM_USER 0x1F 0xC0 bit PGM_USER unsigned char page_hi unsigned char page_lo define LOAD0x00 clear page register enable loading define EP0x68 erase and program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page_hi FMADRL page_lo write my page address to addr regs for i 0 1 lt 64 1 i 1 FMDATA dbytes i Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 85 of 105 Philips Semiconductors UM1 01 08 16 4 16 5 16 6 16 7 P89LPC924 925 User manual FMCON EP erase and prog page command Fm_stat FMCON read the
36. START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 55 12C Control register I2CON address D8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA CRSEL Reset x 0 0 0 0 0 Xx 0 Table 56 12C Control register IZCON address D8h bit description Bit Symbol Description 0 CRSEL SCL clock selection When set 1 Timer 1 overflow generates SCL when cleared 0 the internal SCL generator is used base on values of I2SCLH and I2SCLL reserved The Assert Acknowledge Flag When set to 1 an acknowledge LOW level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The own slave address has been received 2 The general call address has been received while the general call bit GC in I2ADR is set 3 A data byte has been received while the 12C interface is in the Master Receiver Mode 4 A data byte has been received while the 12C interface is in the addressed Slave Receiver Mode When cleared to logic 0 an not acknowledge HIGH level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the 2C interface is in the Master Receiver Mode 2 A data byte has been received while the I2C interface is in the addressed Slave Receiver Mode 12C Interrupt Flag This bit is s
37. This should be taken into consideration when system power consumption is an issue To minimize power consumption the user can power down the comparators by disabling the comparators and setting PCONA 5 to logic 1 or simply putting the device in Total Power down mode CINnA CINNA COn CMPREF O COn CMPREF O cmen 002aaa618 002aaa620 a CPn CNn OEn 000 b CPn CNn OEn 001 CINNA CINnA COn Vrer 1 23V O con Vrer 1 23 V O CMER 002aaa621 002aaa622 c CPn CNn OEn 010 d CPn CNn OEn 01 1 CINnB CINnB COn CMPREF C COn CMPREF O CMen 002aaa623 002aaa624 e CPn CNn OEn 100 f CPn CNn OEn 101 CINnB CINnB COn vVper 1 23V O COn Vrer 1 23 V O CMe 002aaa625 002aaa626 g CPn CNn OEn 110 h CPn CNn OEn 111 Fig 32 Comparator configurations 12 5 Comparators configuration example The code shown below is an example of initializing one comparator Comparator 1 is configured to use the CIN1A and CMPREF inputs outputs the comparator result to the CMP1 pin and generates an interrupt when the comparator output changes CMPINIT MOV PTOAD 030h Disable digital INPUTS on pins CIN1A CMPREF ANL POM2 0CFh Disable digital OUTPUTS on pins that are used ORL PO0M1 030h for analog functions CINIA CMPREF MOV CMP1 020h Turn on comparator 1 and set up for Positive input on C
38. Timer Counter Control register TCON address 88h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset 0 0 0 0 0 0 0 0 Table 36 Timer Counter Control register TCON address 88h bit description Bit Symbol Description o ITO Interrupt O Type control bit Set cleared by software to specify falling edge LOW level triggered external interrupts 1 IEO Interrupt 0 Edge flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when the interrupt is processed or by software 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge LOW level triggered external interrupts Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 39 of 105 UM10108 P89LPC924 925 User manual Philips Semiconductors Table 36 Timer Counter Control register TCON address 88h bit description Bit Symbol Description 3 sIE1 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 where it is cleared in hardware 6 TRI Timer 1 Run contr
39. UM1 01 08 5 7 P89LPC924 925 User manual Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Figure 10 Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins PO 1 through PO 5 of Port 0 respectively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as logic 0 by any instruction that accesses the port On any reset PTOAD bits 1 through 5 default to logic Os to enable the digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1 5 may be configured by software e Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC924 925 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC924 925 data sheet for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Table 22 Port output confi
40. When cleared 0 the TX interrupt is issued at the beginning of the stop bit When set 1 the TX interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that in the case of single buffering if the TX interrupt occurs at the end of a STOP bit a gap may exist before the next start bit 7 DBMOD Double buffering mode When set 1 enables double buffering Must be logic 0 for UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering 10 10 More about UART Mode 0 In Mode 0 a write to SBUF will initiate a transmission At the end of the transmission TI SCON 1 is set which must be cleared in software Double buffering must be disabled in this mode Reception is initiated by clearing RI SCON 0 Synchronous serial transfer occurs and RI will be set again at the end of the transfer When RI is cleared the reception of the next character will begin Refer to Figure 20 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 48 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual s1 S16 st 16 s1 16 s1 16 s1 16 s1 16 S1 16 s1 16 S1 Stefsi 16 s1 16 s1 16 s1 s16 write to SBUF stooo ht i O a O aO O O A yo transmit RXD data out Do X 21 X D2 X D3 X D4 X D5 X Ds X 07 TXD shift clock l TI
41. and selection 10 3 Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved The baud rate is programmable to either 1 46 or 122 of the CCLK frequency as determined by the SMOD1 bit in PCON Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 44 of 105 Philips Semiconductors UM1 01 08 10 4 10 5 10 6 10 7 P89LPC924 925 User manual Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection on page 45 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming star
42. cleared by hardware Koninklijke Philips Electronics N V 2004 All rights reserved 56 of 105 User manual Rev 02 2 March 2005 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual CRSEL determines the SCL source when the I2C bus is in master mode In slave mode this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master 12C device When CRSEL 1 the 12C interface uses the Timer 1 overflow rate divided by 2 for the 12C clock rate Timer 1 should be programmed by the user in 8 bit auto reload mode Mode 2 Data rate of the I2C bus Timer overflow rate 2 PCLK 2 256 reload value If fosc 12 MHz reload value is 0 to 255 so the C bus data rate range is 11 72 Kbit sec to 3000 Kbit sec When CRSEL 0 the 12C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 The STA bit is START flag Setting this bit causes the I2C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode The STO bit is STOP flag Setting this bit causes the I C interface to transmit a STOP condition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I C bus if it is in master mode and transmits a
43. continuous conversion mode for ADC1 BURST1 when 1 selects auto scan continuous conversion mode for ADC1 BNBI1 ADC1 boundary interrupt flag When set indicates that the converted result from ADC 1 is outside of the range defined by the ADC1 boundary registers Table 14 A D Mode Register B ADMODB address Ath bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLK2 CLK1 CLKO ENDAC1 BSA1 Reset 0 0 0 0 0 0 0 0 Table 15 A D Mode Register B ADMODB address Ath bit description Bit Symbol Description 0 reserved 1 BSA1 ADC1 Boundary Select All When 1 BNDI1 will be set if any ADC1 input exceeds the boundary limits When 0 BNDI1 will be set only if the AD10 input exceeded the boundary limits 2 reserved 3 ENDAC1 When 1 selects DAC mode for ADC1 when 0 selects ADC mode 4 B reserved 5 CLKO Clock divider to produce the ADC clock Divides CCLK by the value indicated below 6 CLK1 The resulting ADC clock should be 3 3 MHz or less A minimum of 0 5 MHz is required to maintain A D accuracy A D start mode bits a oe CLK2 0 divisor 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 Table 16 A D Input Select register ADINS address A3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol AIN13 AIN12 AIN11 AIN10 Reset 0 0 0 0 0 0 0 0 Table 17 A D Input Select register ADINS address A3h bit description Bit Symbo
44. could be used to select slaves 1 and 2 while excluding slave 0 Table 51 Slave 0 1 2 examples Example 1 Example 2 Example 3 Slave 0 SADDR 1100 0000 Slave 1 SADDR 11100000 Slave 2 SADDR 11000000 SADEN 1111 1001 SADEN 11111010 SADEN 11111100 Given 1100 Given 1110 0X0X Given 1110 00XX OXX0 In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit O 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 54 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do
45. currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a TX interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a TX interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a TX interrupt is generated already with the UART not knowing whether there is any more data following 10 19 Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8 The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With
46. ff WRITE to SCON clear Rl S To RI shift I RXD DO T D1 T D2 T D3 D4 D5 D6 T D7 data in TxD shift clock l receive 002aaa925 Fig 20 Serial Port Mode 0 double buffering must be disabled 10 11 More about UART Mode 1 Reception is initiated by detecting a 1 to 0 transition on RXD RXD is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide by 16 counter is immediately reset Each bit time is thus divided into 16 counter states At the 7th 8th and 9th counter states the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated
47. is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A DPTR Move data byte the accumulator to data memory relative to DPTR MOVX DPTR A Move data byte from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC924 925 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section or auxiliary data XDATA memory Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 16 Flash memory The P89LPC924 925 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The Sector and Page Erase functions can erase any Flash sector 1 kB or page 64
48. level triggered mode Keyboard Interrupt Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is logic 1 Note Using the internal RC oscillator to clock the RTC during power down may result in relatively high power consumption Lower power consumption can be achieved by using an external low frequency clock when the Real time Clock is running during power down Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 33 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 25 Power Control register PCON address 87h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO Reset 0 0 0 0 0 0 0 0 Table 26 Power Control register PCON address 87h bit description Bit Symbol Description 0 PMODO Power Reduction Mode see Section 6 3 PMOD1 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation 3 GF1 General Purpose Flag 1 May be read or written by user software but has no effect on operation 4 BOI Brownout Detect Interrupt Enable When logic 1 Brownout Detection will generate a interrupt When logic 0 Brownout Detection will cause a reset 5 BOPD Brownout Detect power down When logic 1 Brownout Detect is powered down and therefore disabled When logic 0 Brownout D
49. next cycle interrupt request flag IEn in TCON is set causing an interrupt request Since the external interrupt pins are sampled once each machine cycle an input HIGH or LOW level should be held for at least one machine cycle to ensure proper sampling If the external interrupt is edge triggered the external source has to hold the request pin HIGH Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 24 of 105 Philips Semiconductors UM10108 4 2 P89LPC924 925 User manual for at least one machine cycle and then hold it LOW for at least one machine cycle This is to ensure that the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated If the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive it simply tracks the input pin level If an external interrupt has been programmed as level triggered and is enabled when the P89LPC924 925 is put into Power down or Idle mode the interrupt occurrence will cause the processor to wake up and resume operation Refer to Section 6 3 Power reduction mode
50. not make use of this feature 11 12C interface The I C bus uses two wires serial clock SCL and serial data SDA to transfer information between devices connected to the bus and has the following features e Bidirectional data transfer between masters and slaves e Multimaster bus no central master e Arbitration between simultaneously transmitting masters without corruption of serial data on the bus e Serial clock synchronization allows devices with different bit rates to communicate via one serial bus e Serial clock synchronization can be used as a handshake mechanism to suspend and resume Serial transfer The I C bus may be used for test and diagnostic purposes A typical I2C bus configuration is shown in Figure 24 Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus e Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte e Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not ackn
51. register 6 The only reset source that affects these SFRs is power on reset s1O ONPUOTIWAS sdijiud jenuew 13SN S26 7e6Dd 168d SOLOLINN Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 1 3 Memory organization FFOOh FFEFh 1FFFh 1E00h 1C00h 1BFFh 1800h 17FFh 1400h 13FFh 1000h OFFFh oCoOoh OBFFh 0800h O7FFh 0400h O3FFh 0000h TASE T IAP calls only l FFEFh ently points for SPECIAL FUNCTION pada e E FF1Fh 128 BYTES ON CHIP 51 ASM code A REGISTERS DATA MEMORY STACK Lao FFOOh DIRECTLY ADDRESSABLE AND INDIR ADDR SECTOR ti data memory SECTOR 5 as supplied UART SECTOR 4 user defined SECTOR 3 SECTOR 2 SECTOR 1 SECTOR 0 Note ISP code is located at the end of Sector 4 on the LPC924 and at the end of Sector 7 on the LPC925 Fig 3 P89LPC924 925 memory map Read protected DATA 128 BYTES ON CHIP 1FFFh ISP serial loader DATA MEMORY STACK DIRECT AND INDIR ADDR 4 REG BANKS R 7 0 entry points for UART auto baud l2C SPI etc Flexible choices DATA IDATA Philips libraries 002aaa948 The various P89LPC924 925 memory spaces are as follows DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space OOh FFh acce
52. status register 200 58 12C SCL duty cycle registers I2SCLH and PSC Estee e een econ eee Rae ee 58 I2C operation modes 04 59 Analog comparators 2 20 05 69 Comparator configuration 70 Internal reference voltage 71 Comparator interrupt 71 Comparators and power reduction modes 71 Comparators configuration example 72 Keypad interrupt KBI 0 005 73 Watchdog timer WDT 2 2 05 74 continued gt gt Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 104 of 105 Philips Semiconductors UM10108 14 1 Watchdog function 0 74 14 2 Feed sequence 0 200 0e eee 76 14 3 Watchdog clock source 78 14 4 Watchdog timer in Timer mode 79 14 5 Power down operation 80 14 6 Periodic wake up from power down without an external oscillator 80 15 Additional features 00 eee eee 80 15 1 Software reset 0 0 0 0 cece eee eee 80 15 2 Dual Data Pointers 81 16 Flash memory 0000 e eee eee eee 81 16 1 Features erari eier rt awh amis ROE 81 16 2 Flash programming and erase 82 16 3 Using Flash as data storage IAP Lite 82 16 4 In circuit programming ICP 86 16 5 ISP and IAP capabilities of
53. to the selected input channel See Table 6 An interrupt if enabled will be generated after all selected channels have been converted The process will repeat starting with the first selected channel Additional Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 19 of 105 Philips Semiconductors UM1 01 08 3 2 5 3 2 6 3 2 7 P89LPC924 925 User manual conversion results will again cycle through the result registers of the selected channels overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the BURST1 bit in the ADMODA register Dual channel continuous conversion mode Any combination of two of the four input channels can be selected for conversion The result of the conversion of the first channel is placed in the first result register The result of the conversion of the second channel is placed in the second result register The first channel is again converted and its result stored in the third result register The second channel is again converted and its result placed in the fourth result register See Table 8 An interrupt is generated if enabled after every set of four conversions two conversions per channel This mode is selected by setting the SCC1 bit in the ADMODA register Table 8 Result registers and conversion results for dual channel continuous conversion
54. voltage range e Read Programming Erase using ISP IAP IAP Lite e Any flash program operation in 2 ms 4 ms for erase program e Programmable security for the code in the Flash for each sector e gt 100 000 typical erase program cycles for each byte e 10 year minimum data retention Flash programming and erase The P89LPC924 925 program memory consists 1 kB sectors Each sector can be further divided into 64 byte pages In addition to sector erase and page erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Five methods of programming this device are available e Parallel programming with industry standard commercial programmers e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application e Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to I AP Lite e A factory provided default serial loader located in upper end of user program memory providing In System Programming ISP via the serial port Using Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite in addition to standard IAP functions Any byte in a no
55. 0 0 1 CCLK Medium frequency crystal x x 0 1 0 Low frequency CCLK crystal 0 0 0 1 1 High Internal RC oscillator frequency crystal 0 1 Medium frequency crystal 1 0 Low frequency crystal 1 1 CCLK 0 0 1 0 0 High Watchdog oscillator frequency crystal 0 1 Medium frequency crystal 1 0 Low frequency crystal 1 1 CCLK x x 0 1 1 undefined undefined xX xX 1 1 0 undefined undefined xX x 1 1 1 CCLK External clock input Table 38 Real time Clock Control register RTCCON address D1h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCF RTCS1 RTCSO ERTC RTCEN Reset 0 1 1 x x X 0 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 43 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 39 Real time Clock Control register RTCCON address D1h bit description Bit Symbol Description O RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and disable this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the Watchdog timer Note that if the user configuration bit WOTE UCFG1 7 is logic 0 the Watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time Clock c
56. 0N98 5 Sdiliyd Oxf PUIUCY SOL 40 OL Table 2 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash control Read E4H BUSY HVE SV Ol 70 01110000 Program Flash control Write E4H FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD 7 2 1 0 FMDATA Program Flash data E5H 00 00000000 I2ADR I2C slave address register DBH I2ADR 6 I2ADR 1 I2ADR 0 GC 00 00000000 Bit address DF DA D9 D8 I2CON 12C control register D8H AA CRSEL 00 x00000x0 I2DAT 12C data register DAH I2SCLH Serial clock generator SCL DDH 00 00000000 duty cycle register HIGH I2SCLL Serial clock generator SCL DCH 00 00000000 duty cycle register LOW I2STAT I2C status register D9H STA 4 0 0 0 F8 11111000 Bit address AF AA AQ A8 IENO Interrupt enable 0 A8H EA EX1 ETO EX0 ooi 00000000 Bit address EF EA E9 E8 IEN1 Interrupt enable 1 E8H EAD EC EKBI El2C joo 00x00000 Bit address BF BA B9 B8 IPO Interrupt priority O B8H PX1 PTO PXO ooi x0000000 IPOH Interrupt priority O HIGH B7H PX1H PTOH PXOH 0011 x0000000 Bit address FF FA F9 F8 IP1 Interrupt priority 1 F8H PAD PC PKBI Pl2c ool 00x00000 IP1H Interrupt priority 1 HIGH F7H PADH PCH PKBIH PI2CH 004 00x00000 KBCON Keypad control register 94H PATN KBI
57. 1 Clock divider n nananana anaa 21 I O pins used with A D converter functions 21 Power down and idle mode 22 Interrupts lt cccarersssrissaanar ninnan ee 24 Interrupt priority structure 24 External Interrupt pin glitch suppression 25 VO ports sic ce cect eree ete etdecew nies 26 Port configurations 00 27 Quasi bidirectional output configuration 27 Open drain output configuration 28 Input only configuration 29 Push pull output configuration 29 Port O analog functions 29 Additional port features 30 Power monitoring functions 31 Brownout detection 31 Power on detection 2 55 32 Power reduction modes 32 Reset it icaeivad Madea tke EREE dees 35 Reset vector 0 0200 0 eee ee eee 36 Timers O and 1 1 2 cece eee eee 37 Mod O reeter eda ed heelnee oe eee oes 38 Modell soet bade ci ey adie EA 38 MO dee ios a sth cntus 5 Adon d cee eas eon Rat conta ats 39 Moda Z i ceteeciwetdedeadee ene takes 39 Mode G cs scctceene aad ap antes ere Rua ae 39 8 6 9 9 1 9 2 9 3 9 4 10 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 11 11 1 11 2 11 3 11 4 11 5 11 6 12 12 1 12 2 12 3 12 4 12 5 13 14 Timer overflow toggle output
58. 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Please refer to the P89LPC924 925 data sheet Dynamic characteristics for glitch filter specifications port latch data Fig 8 Quasi bidirectional output 2 CPU CLOCK DELAY a 2 e Q pee lt oO 3 Y z oO Q a input data glitch rejection 002aaa914 5 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp The pull down for this mode is the same as for the quasi bidirectional mode The open drain port configuration is shown in Figure 9 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC924 925 data sheet Dynamic characteristics for glitch filter specifications port TT pin port latch in data input data glitch rejection 002aaa915 Fig 9 Open drain output Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 28 of 105 Philips Semiconductors UM1 01 08 5 4 5 5 5 6 P89LPC924 925 User manual Input only configuration The input port
59. 2 2 March 2005 73 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 71 Keypad Control register KBCON address 94h bit description Bit Symbol Access Description 0 KBIF R W Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing logic 0 1 PATN_SEL R W Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt 2 7 reserved Table 72 Keypad Interrupt Mask register KBMASK address 86h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBMASK 7 KBMASK 6 KBMASK 5 KBMASK 4 KBMASK 3 gt KBMASK 2 KBMASK 1 KBMASK 0 Reset 0 0 0 0 0 0 0 0 Table 73 Keypad Interrupt Mask register KBMASK address 86h bit description Bit Symbol Description 0 KBMASK O When set enables P0 0 as a cause of a Keypad Interrupt 1 KBMASK 1 When set enables P0 1 as a cause of a Keypad Interrupt 2 KBMASK 2 When set enables PO 2 as a cause of a Keypad Interrupt 3 KBMASK 3 When set enables P0 3 as a cause of a Keypad Interrupt 4 KBMASK 4 When set enables P0 4 as a cause of a Keypad Interrupt 5 KBMASK 5 When set enables P0 5 as a cause of a Keypad Interrupt 6 KBMASK 6 When set enables P0 6 as a cause of a
60. 2004 All rights reserved User manual Rev 02 2 March 2005 7 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 1 2 Special function registers Remark Special Function Registers SFRs accesses are restricted in the following ways e User must not attempt to access any SFR locations not defined e Accesses to any defined SFR locations must be strictly for the functions for the SFRs e SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 8 of 105 GOO YW 2 Z0 ASH jenuew sasn SOL J0 6 paniased s YGH Ily Y0OZ A N 91u0149813 Sdiliyd Jfiyuuoy Table 2 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 ADCON1 A D control register 1 97H
61. 25 User manual When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled setting AA logic 1 The appropriate action to be taken for each of these status codes is shown in Table 62 mas Da logic 0 write L data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW 1 from Master to Slave A not acknowledge SDA HIGH Q from Slave to Master S START condition P STOP condition 002aaa929 Fig 25 Format in the Master Transmitter mode 11 6 2 Master Receiver mode In the Master Receiver Mode data is received from a slave transmitter The transfer started in the same manner as in the Master Transmitter Mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to the 12C Data Register I2DAT The SI bit must be cleared before the data transfer can continue When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 64 for details Epe om Ta STD l
62. 3 bit register As the count rolls over from all logic 1s to all logic Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either TNGATE 0 or INTn 1 Setting TnGATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Table 36 The TNGATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 13 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 8 2 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 14 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 38 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 8 3 Mode 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 15 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 8 4 Mode 3 When Timer 1 is in
63. 5 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 28 Power Control register A PCONA address B5h bit description Bit Symbol Description 5 VCPD Analog Voltage Comparators power down When logic 1 the voltage comparators are powered down User must disable the voltage comparators prior to setting this bit 6 reserved RTCPD Real time Clock power down When logic 1 the internal clock to the Real time Clock is disabled 7 Reset The P1 5 RST pin can function as either an active LOW reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at powerup until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage NOTE During a power on sequence The RPE selection is overridden and this pin will always functions as a reset input An external circuit connected to this pin should not hold this pin LOW during a Power on sequence
64. CCLK TIMING AND CONTROL LOGIC D SYNC LOGIC INTERRUPT CONTROL REGISTERS AND STATUS DECODER STATUS REGISTER 8 Ji T gt NA 002aaa421 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 63 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual Table 62 Master Transmitter mode Status code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO JSI AA 08H A START Load SLA W x 0 0 x SLA W will be transmitted condition has ACK bit will be received been transmitted 10H A repeat START LoadSLA Wor x 0 0 x As above SLA W will be condition has Load SLA R transmitted the I C bus been transmitted switches to Master Receiver Mode 18h SLA W has been Load data byte or 0 0 0 x Data byte will be transmitted transmitted ACK ACK bit will be received has been received no 2DAT action or 1 0 0 x Repeated START will be transmitted no I2DAT action or 0 1 0 x STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W has been Load data byte or 0 0 0 x Data byte will be transmitted transmitted ACK bit will be received NOT ACK has no I2DAT action or 1 0 0 X R
65. CRC a secured sector or page FMCMD 1 W Command byte bit 1 2 HVE R High voltage error Set when an error occurs in the high voltage generator FMCMD 2 W Command byte bit 2 3 HVA R High voltage abort Set if either an interrupt or a brown out is detected during a program or erase cycle Also set if the brown out detector is disabled at the start of a program or erase cycle FMCMD 3 W Command byte bit 3 4 7 R reserved 4 7 FMCMD 4 W Command byte bit 4 4 7 FMCMD 5 W Command byte bit 5 4 7 FMCMD 6 W Command byte bit 6 4 7 FMCMD 7 W Command byte bit 7 An assembly language routine to load the page register and perform an erase program operation is shown below skkxkxkxk k kxkxkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 1 pgm user code skkxkxkxkkxkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkx oe Inputs R3 number of bytes to program byte f R4 page address MSB byte is R5 page address LSB byte R7 pointer to data buffer in RAM byte Outputs z R7 status byte x C clear on no error set on error i KKK KKK KKK KERR KKK RK KR KEKE RK KER RK RRR KERR KKK KEKE KEKKEKEKE 1 LOAD EQU 00H EP EQU 68H Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 84 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual PGM_USER MOV FMCON LOAD load command clears page register MOV FMADRH
66. Erase Disable ISP Disables the ability to perform an erase of sector x in ISP or IAP mode When programmed this bit and sector x can only be erased by a global erase command using a commercial programmer This bit and sector x CANNOT be erased in ISP or IAP modes 3 7 reserved Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 97 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual Table 91 Effects of Security Bits EDISx SPEDISx MOVCDI Effects on Programming Sx 0 0 None 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a security violation 0 1 x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed 1 x x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed 16 18 Boot Vector register Table 92 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTVO Factory default 0 0 0 1 1 1 1 1 value Table 93 Boot Vector BOOTVEC bit description Bit Sym
67. F OO xxxxxx00 _SEL KBMASK Keypad interrupt mask 86H 00 00000000 register KBPATN Keypad pattern register 93H FF 11111111 s1O ONPUOTIWAS sdijiud Jenuew 13SN S26 7e6Dd 168d SOLOLINN G00e yen 2 ZO ASH jenuew sasn SOL JO LL paniased S Y U IY 700 A N S91u0149813 Sdiliyd Oxf PUIUOY Table 2 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address 87 86 85 84 83 82 81 80 PO Port 0 80H T1 KB7 CMP1 CMPREF CINIA CIN1B CIN2A CIN2B CMP2 0l KB6 KB5 KB4 KB3 KB2 KB1 KBO Bit address 97 96 95 94 93 92 91 90 P1 Port 1 90H RST INT1 INTO TO SCL RXD TXD 0l SDA Bit address B7 B6 B5 B4 B3 B2 B1 BO P3 Port 3 BOH XTAL1 XTAL2 0l POM1 Port 0 output mode 1 84H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FF 11111111 POM2 Port 0 output mode 2 85H POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 00 00000000 P1M1 Port 1 output mode 1 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D30 11x1xx11 P1M2 Port 1 output mode 2 92H P1M2 7 P1M2 6 z P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00l 00x0xx00 P3M1 Port 3 output mode 1 B1H P3M1 1 P3M1 0 030 XXXXXX 11 P3M2 Port 3 output mode 2 B2H P3
68. INIA Negative input from CMPREF pin Output to CMP1 pin enabled CALL delayl0dus start up for at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 72 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual SETB EC Enable the comparator interrupt The priority is left at the current value SETB EA Enable the interrupt system if needed RET Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF1 in this case before returning 13 Keypad interrupt KBI The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks There are three SFRs used for this function The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated
69. M2 1 P3M2 0 Oo XXXXXX00 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD ADPD I2PD SPD ool 00000000 Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV F1 P 00H 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00H xx00000x RSTSRC _ Reset source register DFH BOF POF R_BK R_WD R_SF R_EX 3 RTCCON Real time clock control D1H RTCF RTCS1 RTCSO ERTC RTCEN eos RTCH Real time clock register HIGH D2H ool l 00000000 RTCL Real time clock register LOW D3H ool l 00000000 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer 99H XX XXXXXXXX register Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 s1o ONPUOTIWAS Ssdijiud Jenuew 19Sf S26 7e6Dd 168d SOLOLINN g00 e yen 2 ZO ASH jenuew ssn SOL JO ZL pansased S YGH IY 700 A N S91u0149813 Sdiliyd OHI PUIUOY Table 2 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary SSTAT Serial port extended status BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 register SP
70. Mode 3 it is stopped The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 16 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC924 925 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt 8 5 Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 17 Its structure is similar to mode 2 except that e TFn n 0 and 1 for Timers O and 1 respectively is set and cleared in hardware e The LOW period of the TFn is in THn and should be between 1 and 254 and e The HIGH period of the TFn is always 256 THn e Loading THn with 00h will force the TX pin HIGH loading THn with FFh will force the TX pin LOW Note that interrupt can still be enabled on the LOW to HIGH transition of TFn and that TFn can still be cleared in software like in any other modes Table 35
71. NCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Reset 0 0 Bits 5 0 loaded with factory stored value during reset Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 15 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 5 On chip RC oscillator trim register TRIM address 96h bit description Bit Symbol TRIM O TRIM 1 Description Trim value Determines the frequency of the internal RC oscillator During reset these bits are loaded with a stored factory calibration value When writing to either bit 6 or bit 7 of this register TRIM 2 TRIM 3 care should be taken to preserve the current TRIM value by reading this register modifying bits 6 or 7 as required and writing the result to this register TRIM 4 TRIM 5 ENCLK when 1 CCLK 2 is output on the XTAL2 pin provided the crystal oscillator is not being used NO ao BR wo MM Oo RCCLK when 1 selects the RC Oscillator output as the CPU clock CCLk 2 5 2 6 Watchdog oscillator option The Watchdog has a separate oscillator which has a frequency of 400 kHz This oscillator can be used to save power when a high clock frequency is not needed External clock input option In this configuration the processor clock is derived from an external source driving the XTAL1 P3 1 pin The rate may be from 0 Hz up to 18 MHz The XTAL2 P3 0 pin may be
72. ON address A7h bit description Bit Symbol Description 0 WDCLK Watchdog input clock select When set the Watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the Watchdog is disabled if WDCLK 0 see Section 14 5 Note If both WDTE and WDSE are set to 1 this bit is forced to 1 Refer to Section 14 3 for details 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In Watchdog mode a feed sequence will clear this bit It can also be cleared by writing logic 0 to this bit in software 2 WDRUN Watchdog Run Control The Watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to logic 1 Watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to 1 3 4 reserved PREO 6 PRE1 Clock Prescaler Tap Select Refer to Table 77 for details 7 PRE2 Table 77 Watchdog timeout vales PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in Watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK 2 Watchdog Nominal Clock 000 0 33 82 5 us 5 50 us 255 8 193 20 5 ms 1 37 ms 001 0 65 162 5 us 10 8 us 255 16 385 41 0 ms 2 73 ms 010 0 129 322 5 us 21 5 us 255 32 769 81 9 ms 5 46 ms 011 0 257 642 5 us 42 8 us 255 65 537 163 8 ms 10 9 ms Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02
73. P condition followed by a START condition will be transmitted STO flag will be reset 38H Arbitration lostin No I2DAT action 0 0 0 x The I2C bus will be released SLA R W or data or not addressed slave will be bytes entered No I2DAT action 1 0 0 X A START condition will be transmitted when the bus becomes free Table 63 Master Receiver mode Status code Status of the I C Application software response Next action taken by the I C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI STA 08H A START Load SLA R x 0 0 x SLA R will be transmitted ACK bit condition has will be received been transmitted 10H A repeat START Load SLA R or x 0 0 Xx As above condition has Load SLA W SLA W will be transmitted the been transmitted 12C bus will be switched to Master Transmitter Mode 38H Arbitration lostin no I2DAT action or 0 0 0 x The I2C bus will be released it will NOT ACK bit enter a slave mode no I2DAT action 1 0 0 x A START condition will be transmitted when the bus becomes free 40h SLA R has been no I2DAT action or 0 0 0 0 Data byte will be received NOT ACK transmitted ACK bit will be returned has been received no 2DAT action or 0 0 0 1 Data byte will be received ACK bit will be returned 48h SLA R has been Nol2DAT action 1 0 0 xX Repeated START will be transmitted transmitted NOT or ACK has been no I2DAT action or 0 1 0 x STOP condition will be transmitted received STO flag will be reset no I2DAT action or 1 1 0 x STOP condition fo
74. Stack pointer 81H 07 00000111 TAMOD Timer 0 and 1 auxiliary mode 8FH T1M2 TOM2 00 XXX0XXX0 Bit address 8F 8E 8D 8c 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 00000000 THO Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TLO Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H TIGATE T1C T T1iM1 TiMO TOGATE TOC T TOM1 TOMO 00 00000000 TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM5 TRIM4 TRIM3 TRIM 2 TRIM 1 TRIM O 5 6 WDCON Watchdog control register A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK 4 6 WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H 1 All ports are in input only high impedance state after power up 2 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable 3 The RSTSRC register reflects the cause of the P89LPC924 925 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 4 After reset the value is 111001x1 i e PRE2 PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 5 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM
75. U S A
76. UM10108 P89LPC924 925 User manual Rev 02 2 March 2005 Semiconductors User manual E Document information Info Content Keywords P89LPC924 P89LPC925 Abstract Technical information for the P89LPC924 and P89LPC925 devices PHILIPS Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Revision history Rev Date Description 02 20050302 Updated to include 18 MHz information 01 20040628 Initial version 9397 750 13338 Contact information For additional information please visit http www semiconductors philips com For sales office addresses please send an email to sales addresses www semiconductors philips com Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 2 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 1 Introduction The P89LPC924 925 are single chip microcontrollers designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC924 925 is based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC924 925 in order to reduce component count board space and system cost 1 1 Pin Configuration KBIO CMP2 P0 0 1 P0 1
77. V 2004 All rights reserved User manual Rev 02 2 March 2005 20 of 105 Philips Semiconductors UM1 01 08 3 3 3 3 1 3 3 2 3 3 3 3 3 4 3 4 3 5 3 6 P89LPC924 925 User manual Trigger modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all A D operating modes This mode is selected by the TMM1 bit and the ADCS11 and ADCS10 bits See Table 11 Start immediately Programming this mode immediately starts a conversion This start mode is available in all A D operating modes This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register See Table 11 Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the conversion has completed The edge triggered start mode is available in all A D operating modes This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register See Table 11 Boundary limits interrupt The A D converter has both a HIGH and LOW boundary limit register After the four MSBs have been converted these four bits are compared with the four MSBs of the boundary HIGH and LOW registers If the four MSBs of the conversion are outside the limit an interrupt will be generat
78. WDL 0FFh New count to be loaded to 8 bit down counter CLR EA disable interrupt OV WDCON ACC write back to WDCON after the watchdog is enabled a feed must occur immediately OV WFEED1 0A5h do watchdog feed part 1 OV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the control register every CCLK cycle no feed sequence is required to load the control register but a feed sequence is required to load from the WDL SFR to the 8 bit down counter before a time out occurs The number of Watchdog clocks before timing out is calculated by the following equations telks 207 woL 1 1 1 where Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 76 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual PRE is the value of prescaler PRE2 to PREO which can be the range 0 to 7 and WDL is the value of Watchdog load register which can be the range of 0 to 255 The minimum number of tclks is telks 2 04 1 4 1 33 2 The maximum number of tclks is 5 7 telks 2 255 1 1 1048577 3 Table 77 shows sample P89LPC924 925 timeout values Table 75 Watchdog Timer Control register WDCON address A7h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PRE2 PRE1 PREO WDRUN WDTOF WDCLK Reset 1 1 1 xX xX 1 1 0 1 Table 76 Watchdog Timer Control register WDC
79. Writ CWP bit in BOOTSTAT 6 is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection function in IAP or ISP The Clear Configuration Protection command can be disabled in ISP or IAP mode by programming to a logic 1 the Disable Clear Configuration Protection DCCP bit in BOOTSTAT 7 When DCOP is set the CCP command may still be used in ICP or parallel programming modes This bit is cleared by writing the Clear Configuration Protection command in either ICP or parallel programming modes 16 15 IAP error status It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory During an IAP erase program or CRC the CPU enters a program idle state The CPU will remain in this program idle state until the erase program or CRC cycle is completed These cycles are self timed When the cycle is completed code execution resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP error condition will be flagged by setting the carry flag and status information returned The status information returned is shown in Table 84 If the application permits interrupts during erasing programming or CRC cycles
80. X CCLK 16 0 1 0 0 CCLK 256 TH1 64 1 0 CCLK 256 TH1 32 X 1 CCLK BRGR1 BRGRO 16 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 45 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 41 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON 1 Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 1 0 0 X CCLK 32 1 X CCLK 16 1 1 0 0 CCLK 256 TH1 64 1 0 CCLK 256 TH1 32 xX 1 CCLK BRGR1 BRGR0O 16 Table 42 Baud Rate Generator Control register BRGCON address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS BRGEN Reset Xx xX xX xX xX xX 0 0 Table 43 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol 0 BRGEN Description Baud Rate Generator Enable Enables the baud rate generator BRGR1 and BRGRO can only be written when BRGEN 0 1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and 3 see Table 41 for details reserved Timer 1 Overflow SBRGS 0 J Ahh PCLK based o 1 Baud Rate Modes 1 and 3 SMOD1 0 p SBRGS 1 Baud Rate Generator CCLK based 002aaa419 Fig 19 Baud rate generation for UART Modes 1 3 10 8 Framing error A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status re
81. allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Table 50 Slave 0 1 examples Example 1 Example 2 Slave 0 SADDR 11000000 Slave 1 SADDR 11000000 SADEN 11111101 SADEN 11111110 Given 110000X0 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following
82. as this will keep the device in reset After power on this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power on reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit NOTE During a power cycle Vpp must fall below Vpor See P89LPC924 925 data sheet Static characteristics before power is reapplied in order to ensure a power on reset Reset can be triggered from the following sources see Figure 12 e External reset pin during power on or if user configured via UCFG1 Power on Detect Brownout Detect e Watchdog timer e Software reset e UART break detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a logic 0 to the corresponding bit More than one flag bit may be set e During a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset any previously set flag bits that have not been cleared will remain set Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 35 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual RPE UCFG1 6 e D WDTE UCFG1 7 Watchdog timer reset J Software reset SRST AUXR1 3
83. ator is disabled the comparator s output COx goes HIGH If the comparator output was LOW and then is disabled the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator Comparators and power reduction modes Either or both comparators may remain enabled when power down or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 71 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in power down and Idle modes as well as in the normal operating mode
84. aused the interrupt 2 4 reserved RTCSO Real time Clock source select see Table 37 6 RTCS1 RTCF Real time Clock Flag This bit is set to logic 1 when the 23 bit Real time Clock reaches a count of logic 0 It can be cleared in software 10 UART The P89LPC924 925 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC924 925 does include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect automatic address recognition selectable double buffering and several interrupt options The UART can be operated in four modes as described in the following sections 10 1 Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 1g of the CPU clock frequency 10 2 Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator
85. be enabled An external circuit is required to hold the device in reset at powerup until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 14 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 2 3 Clock output The P89LPC924 925 supports a user selectable clock output function on the XTAL2 CLKOUT pin when the crystal oscillator is not being used This condition occurs if a different clock source has been selected on chip RC oscillator Watchdog oscillator external clock input on X1 and if the Real time Clock is not using the crystal oscillator as its clock source This allows external devices to synchronize to the P8B9LPC924 925 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the content
86. bit inverse to carry 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LUMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1andclear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 101 of 105 Philips Semiconductors UM10108 Table 96 Instruction set summary P89LPC924 925 User manual Mnemonic Description Bytes Cycles Hex code JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJUNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne 3 2 B4 relative CJNE Rn d rel Compare register immediate jne 3 2 B8 to BF relative CJNE Ri d rel Compare indirect immediate jne 3 2 B6 to B7 relative DJNZ Rn rel Decrement register jnz relative 2 2 D8 to DF DJNZ dir rel Decrement direct byte jnz 3 2 D5 relative MISCELLANEOUS NOP No operation 1 1 00 Koninklijke Ph
87. bol Description 0 4 BOOTV 0 4 Boot vector If the Boot Vector is selected as the reset address the P89LPC924 925 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset 5 7 reserved 16 19 Boot status register Table 94 Boot Status BOOTSTAT bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BSBO Factory default 0 0 0 0 0 0 0 1 value Table 95 Boot Status BOOTSTAT bit description Bit Symbol Description 0 4 BOOTV 0 4 Boot Status Bit If programmed to logic 1 the P89LPC924 925 will always start execution at an address comprised of OOH in the lower eight bits and BOOTVEC as the upper bits after a reset See Section 7 1 Reset vector on page 36 5 7 reserved Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 98 of 105 Philips Semiconductors UM10108 17 Instruction set P89LPC924 925 User manual Table 96 Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A Rn Add register to A 1 1 28 to 2F ADD A dir Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 to 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 to 3F ADDC A dir Add direct byte to
88. bytes The Chip Erase operation will erase the entire program memory Five Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC924 925 Flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P89LPC924 925 uses Vpp as the supply voltage to perform the Program Erase algorithms 16 1 Features e Parallel programming with industry standard commercial programmers e In Circuit serial Programming ICP with industry standard commercial programmers e JAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application e Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite e Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 81 of 105 Philips Semiconductors UM1 01 08 16 2 16 3 P89LPC924 925 User manual e Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user e Programming and erase over the full operating
89. cation Boot ROM When the microcontroller contains a a 256 byte Boot ROM that is separate from the users Flash program memory This Boot ROM contains routines which handle all of the low level details needed to erase and program the user Flash memory A user program simply calls a common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation Boot ROM operations include operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FFOO to FFFF hex thereby not conflicting with the user program memory space This function is in addition to the IAP Lite feature Power on reset code execution The P89LPC924 925 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC924 925 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status Bit is set to a va one the contents of the Boot Vector is used as the HIGH byte of the execution address and the LOW byte is set to OOH The factory default settings for these devices are show in Table 82 below The factory pre programmed boot loader can be erased by the user Users who wish to use this loader should take cautions to avoid erasing the last 1 kB sector
90. configuration is shown in Figure 10 It is a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC924 925 data sheet Dynamic characteristics for glitch filter specifications input port data pin glitch rejection 002aaa916 Fig 10 Input only Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 11 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC924 925 data sheet Dynamic characteristics for glitch filter specifications VDD strong pin port latch N data input data f nae glitch rejection 002aaa917 Fig 11 Push pull output Port 0 analog functions The P89LPC924 925 incorporates two Analog Comparators In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 29 of 105 Philips Semiconductors
91. d User manual Rev 02 2 March 2005 74 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WDSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to Table 74 for details Figure 35 shows the Watchdog timer in Watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK or the Watchdog oscillator selected by the WDCLK bit in the WDCON register Note that switching of the clock sources will not take effect immediately see Section 14 3 The Watchdog asserts the Watchdog reset when the Watchdog count underflows and the Watchdog reset is enabled When the Watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect If a Watchdog reset occurs the internal reset is active for at least one Watchdog clock cycle PCLK or the Watchdog oscillator clock If CCLK is still running code execution will begin immediately after the reset cycle If the processor was in Power down mode the Watchdog reset will start the oscillator and code execution will resume after the oscillator
92. d data byte or 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or own SLA address general address Data has been read data byte 0 0 0 1 Switched to not addressed SLA received NACK or mode Own SLA will be recognized has been returned general call address will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 A START condition will be transmitted when the bus becomes free 90H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned General call Data fead data byte x 0 0 1 Data byte will be received and ACK has been will be returned received ACK has been returned 98H Previously Read data byte 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or General call Data General call address has been read data byte 0 0 0 1 Switched to not addressed SLA received NACK mode Own slave address will be has been returned recognized General call address will be recognized if IZADR O 1 read data byte 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmi
93. data Move immediate to indirect 2 1 76 to 77 memory MOV DPTR data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTRto 1 2 93 A MOVC A A PC Move code byte relative PC toA 1 2 94 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 100 of 105 Philips Semiconductors UM10108 Table 96 Instruction set summary P89LPC924 925 User manual Mnemonic Description Bytes Cycles Hex code MOVX A Ri Move external data A8 to A 1 2 E2 to E3 MOVX A DPTR Move external data A16 to A 1 2 EO MOVX Ri A Move A to external data A8 1 2 F2 to F3 MOVX DPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2 co POP dir Pop direct byte from stack 2 2 DO XCH A Rn Exchange A and register 1 1 C8 to CF XCH A dir Exchange A and direct byte 2 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 to C7 XCHD A Ri Exchange A andindirectmemory 1 1 D6 to D7 nibble BOOLEAN Mnemonic Description Bytes Cycles Hex code CLRC Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETB C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPLC Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct
94. e it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 256 clocks after start up for the internal RC or external clock input configurations Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include Brownout Detect Watchdog timer if WDCLK WDCON 0O is logic 1 e Comparators Note Comparators can be powered down separately with PCONA 5 set to logic 1 and comparators disabled Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is logic 1 Total Power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparators are also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupts and Brownout interrupt cannot be used as a wake up source The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled The following are the wake up options supported e Watchdog timer if WOCLK WDCON 0 is logic 1 Could generate Interrupt or Reset either one can wake up the device External interrupts INTO INT1 when programmed to
95. e Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page e Write the data for the next byte to be programmed to FMDATA e Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register e Write the page address in user code memory to FMADRH and FMADRL 7 6 if not previously included when writing the page register address to FMADRL 5 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 83 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual e Write the erase program command 68H to FMCON starting the erase program cycle e Read FMCON to check status If aborted repeat starting with the LOAD command Table 80 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol R 3 HVA HVE SV Ol Symbol W FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O Reset 0 0 0 0 0 0 0 0 Table 81 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 Ol R Operation interrupted Set when cycle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or
96. e the interrupt is enabled in order to prevent an immediate interrupt service Table 66 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CEn CPn CNn OEn COn CMFn Reset X x 0 0 0 0 0 0 Table 67 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled Cleared by software 1 COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous to the CPU clock 3 CNn Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the negative comparator input When logic 1 the internal comparator reference Vref is selected as the negative comparator input 4 CPn Comparator positive input select When logic 0 CINnA is selected as the positive comparator input When logic 1 CINnB is selected as the positive comparator input 5 CEn Comparator enable When set the corresponding comparator function is enabled Comparator output is stable 10 microseconds after CEn is set 6 reserved reserved Koninklijke Philips Electron
97. ed if enabled If the conversion result is within the limits the boundary limits will again be compared after all eight bits have been converted An interrupt will be generated if enabled if the result is outside the boundary limits The boundary limit may be disabled by clearing the boundary limit interrupt enable DAC output to a port pin with high impedance The ADODATS register is used to hold the value fed to the DAC After a value has been written to ADODAT3 the DAC output will appear on the DACO pin The DAC output is enabled by the ENDACO bit in the ADMODB register See Table 15 Clock divider The A D converter requires that its internal clock source be in the range of 500 kHz to 3 3 MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose See Table 15 I O pins used with A D converter functions The analog input pins used with for the A D converter have a digital input and output function In order to give the best analog performance pins that are being used with the ADC or DAC should have their digital outputs and inputs disabled and have the 5 V tolerance disconnected Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Table 21 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 21 of 105 Philips Semiconductors UM1 01 08
98. eeds to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow To feed the Watchdog two write instructions must be sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register An incorrect feed sequence will cause an immediate Watchdog reset The program sequence to feed the Watchdog timer is as follows CLR EA disable interrupt MOV WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC924 925 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a Watchdog reset If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In Watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WOCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a Watchdog reset will occur For example setting WDRUN 1 OV ACC WDCON get WDCON SETB ACC 2 set WD_RUN 1 OV
99. enable the 12C function AA bit must be set 1 to acknowledge its own slave address or the general call address STA STO and SI are cleared to 0 After I2ADR and I2CON are initialized the interface waits until it is addressed by its own address or general address followed by the data direction bit which is 0 W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 65 for the status codes and actions logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW LD from Master to Slave A not acknowledge SDA HIGH C1 trom Slave to Master S START condition P STOP condition RS repeated START condition 002aaa932 Fig 28 Format of Slave Receiver mode 11 6 4 Slave Transmitter mode The first byte is received and handled as in the Slave Receiver Mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 3 SDA while the serial clock is input through P1 2 SCL START and Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 61 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual STOP conditions are recognized as the beginning and end of a serial transfer In a given application the 1
100. epeated START will be been received transmitted no I2DAT action or 0 1 0 x STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset 28h Data byte in I2DAT Load data byte or 0 0 0 x Data byte will be transmitted has been ACK bit will be received transmitted ACK R START will has been received I2DAT action or 1 0 0 x epeated will be transmitted no l2DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 xX STOP condition followed by a START condition will be transmitted STO flag will be reset Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 64 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual Table 62 Master Transmitter mode Status code Status of the I2C Application software response Next action taken by I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 30h Data byte in I2DAT Load data byte or 0 0 0 x Data byte will be transmitted has been ACK bit will be received transmitted NOT ACK has been no I2DAT action or 1 0 0 X Repeated START will be received transmitted no I2DAT action or 0 1 0 x STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 x STO
101. er Mode register TMOD address 89h bit description Bit Symbol Description 0 TOMO Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the 1 TOM1 Timer 0 mode see Table 34 2 TOC T Timer or Counter selector for Timer 0 Cleared for Timer operation input from CCLK Set for Counter operation input from TO input pin 3 TOGATE Gating control for Timer 0 When set Timer Counter is enabled only while the INTO pin is HIGH and the TRO control pin is set When cleared Timer 0 is enabled when the TRO control bit is set T1MO Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the 5 TIM1 Timer 1 mode see Table 34 6 T1C T Timer or Counter Selector for Timer 1 Cleared for Timer operation input from CCLK Set for Counter operation input from T1 input pin 7 T1GATE Gating control for Timer 1 When set Timer Counter is enabled only while the INT1 pin is HIGH and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 37 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 33 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TiM2 TOM2 Reset x X xX 0 xX X xX 0 Table 34 Timer
102. er supply voltage drops below a certain level The default operation for a Brownout Detection is to cause a processor reset However it may alternatively be configured to generate an interrupt by setting the BOI PCON 4 bit and the EBO IENO 5 bit Enabling and disabling of Brownout Detection is done via the BOPD PCON 5 bit bit field PMOD1 0 PCON 1 0 and user configuration bit BOE UCFG1 5 If BOE is in an unprogrammed state brownout is disabled regardless of PMOD1 0 and BOPD If BOE is in a programmed state PMOD1 0 and BOPD will be used to determine whether Brownout Detect will be disabled or enabled PMOD1 0 is used to select the power reduction mode If PMOD1 0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to logic 0 indicating brownout detection is enabled on power on if BOE is programmed If Brownout Detection is enabled the brownout condition occurs when Vpop falls below the Brownout trip voltage Vgo see P89LPC924 925 Static Characteristics and is negated when Vpp rises above Vgo If the P89LPC924 925 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating If Brownout Detect is enabled BOE programmed PMOD1 0 11 BOPD 0 BOF RSTSRC 5 will be set when a brownout is detected regardless
103. es the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limited to 64 decimal ISP commands are summarized in Table 83 As a record is received by the P89LPC924 925 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the P89LPC924 925 will send an X out the serial port indicating a checksum error If the checksum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 88 of 105 Philips Semiconductors UM10108 Table 83 P89LPC924 925 User manual In system Programming ISP hex record formats Record type Command data function 00 Program User Code Memory Page nnaaaa0Odd ddcc Where nn number of bytes to program aaaa page address dd dd data bytes cc checksum Example 100000000102030405006070809cc 01 Read Version Id 00xxxx01cc Where XXXX required field but value is a don t care cc checksum Example
104. escription Normal mode default no power reduction 0 1 Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC924 925 exits Power down mode via any reset or certain interrupts external pins INTO INT1 brownout Interrupt keyboard Real time Clock System Timer Watchdog and comparator trips Waking up by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set External interrupts should be programmed to level triggered mode to be used to exit Power down mode In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage VRAM This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to VRAM therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mod
105. et when one of the 25 possible I2C bus states is entered When EA bit and El2C IEN1 0 bit are both set an interrupt is requested when SI is set Must be cleared by software by writing O to this bit 4 STO STOP Flag STO 1 In master mode a STOP condition is transmitted to the 12C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware automatically Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 57 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 56 12C Control register IZCON address D8h bit description Bit Symbol Description 5 STA Start Flag STA 1 The I2C bus enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits fora STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator When the 12C interface is already in master mode and some data is transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when the IC interface is
106. etect is enabled Note BOPD must be logic 0 before any programming or erasing commands can be issued Otherwise these commands will be aborted 6 SMODO Framing Error Location When logic 0 bit 7 of SCON is accessed as SMO for the UART When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 10 Table 27 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD VCPD l2PD SPD Reset 0 0 0 0 0 0 0 0 Table 28 Power Control register A PCONA address B5h bit description Bit Symbol Description 0 reserved 1 SPD Serial Port UART power down When logic 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled regardless of this bit reserved I2PD 12C power down When logic 1 the internal clock to the I2C bus is disabled Note that in either Power down mode or Total Power down mode the 12C clock will be disabled regardless of this bit 4 s reserved Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 34 of 10
107. g and therefore the Watchdog is effectively disabled 14 6 Periodic wake up from power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wake up is determined by the power consumption of the internal oscillator source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300 uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50 uA Whenever the WDT underflows the device will wake up 15 Additional features The AUXR1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 79 Table 78 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENTO SRST 0 DPS Reset 0 0 0 0 0 0 xX 0 Table 79 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowable to set to a logic 1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register 3 SRST Software Reset When set by software resets the P89LPC924 925 as if a hardware reset occurred 4 ENTO When set the P1 2 pin is toggled whenever Timer 0 overf
108. ggle dii oT O T1 pin P0 7 ENT1 AUXR1 5 002aaa922 Fig 16 Timer counter 0 Mode 3 two 8 bit counters overflow POLS o on TFn interrupt control and 256 THn on rising transition toggle TRn Gate THn INTn pin 8 bits ENTn 002aaa923 Fig 17 Timer counter 0 or 1 in mode 6 PWM auto reload 8 6 Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by control bits ENTO and ENT1 in the AUXR1 register and apply to Timer 0 and Timer 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer 9 Real time clock system timer The P89LPC924 925 has a simple Real time Clock System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see Figure 18 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 41 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual
109. gister SSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SCON 7 If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are programmed when SMODO is logic 0 10 9 Break detect A break detect is reported in the status register SSTAT A break is detected when any 11 consecutive bits are sensed LOW Since a break condition also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 46 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 44 Serial Port Control register SCON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO0 FE SM1 SM2 REN TB8 amp RB8 TI RI Reset xX X Xx xX xX X 0 0 Table 45 Serial Port Control register SCON address 98h bit description Bit Symbol Description 0 RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8
110. guration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes P0 0 POM1 0 POM2 0 KBIO CMP2 PO 1 POM1 1 POM2 1 KBI1 CIN2B AD10 Refer to Section 5 6 Port 0 P0 2 POM1 2 POM2 2 KBI2 CIN2A AD11 Sea functions for usage as analog inputs P0 3 POM1 3 POM2 3 KBI3 CIN1B AD12 P0 4 POM1 4 POM2 4 KBI4 CIN1A AD13 DAC1 P0 5 POM1 5 POM2 5 KBI5 CMPREF P0 6 POM1 6 POM2 6 KBI6 CMP1 PO 7 POM1 7 POM2 7 KBI7 T1 P1 0 P1M1 0 P1M2 0 TXD P1 1 P1M1 1 P1M2 1 RXD P1 2 P1M1 2 P1M2 2 TO SCL Input only or open drain P1 3 P1M1 3 P1M2 3 INTO SDA input only or open drain P1 4 P1M1 4 P1M2 4 INTI P1 5 P1M1 5 P1M2 5 RST P1 6 P1M1 6 P1M2 6 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 30 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 22 Port output configuration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes P1 7 P1M1 7 P1M2 7 P3 0 P3M1 0 P3M2 0 CLKOUT XTAL2 P3 1 P3M1 1 P3M2 1 XTAL1 6 Power monitoring functions 6 1 The P89LPC924 925 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout Detect Brownout detection The Brownout Detect function determines if the pow
111. he frequency of PCLK The values for I2SCLL and I2SCLH do not have to be the same the user can give different duty cycle s for SCL by setting these two registers However the value of the register must ensure that the data rate is in the 1 C data rate range of 0 to 400 kHz Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than 3 PCLKs are recommended Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 58 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 59 12C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 6 0 307 154 7 0 263 132 8 0 230 115 375 9 0 205 102 333 10 0 369 184 92 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 100 0 37 18 9 60 30 150 0 25 12 6 40 20 200 0 18 9 5 30 15 1 3 6 to 922 Kbps 1 8 to 461 Kbps 0 9 to 230 Kbps 5 86 to 1500 Kbps 2 93 to 750 Kbps Timer 1 in mode 2 Timer1inmode2 Timer 1in mode2 Timer1inmode2_ Timer 1 in mode 2 11 6 I C operation modes 11 6 1 Master Transmitter mode In this mode data is transmitted from master to slave Before the Master Transmitter Mode can be entered I2CON must be initialized as follows Table 60 12C Contr
112. he same priority level are pending at the start of an instruction cycle an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used for pending requests of the same priority level Table 19 summarizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mode Interrupt priority structure Table 18 Interrupt priority level Priority bits IPXH IPx Interrupt priority level 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 There are four SFRs associated with the four interrupt levels IPO IPOH IP1 IP1H Every interrupt has two bits in IPx and IPxH x 0 1 and can therefore be assigned to one of four levels as shown in Table 18 The P89LPC924 925 has two external interrupt inputs in addition to the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by clearing or setting bit IT1 or ITO in Register TCON If ITn 0 external interrupt n is triggered by a LOW level detected at the INTn pin If ITn 1 external interrupt n is edge triggered In this mode if consecutive samples of the INTn pin show a HIGH level in one cycle and a LOW level in the
113. hrough the use of an Flash byte UCFG1 shown in Table 87 Table 86 Flash User Configuration Byte UCFG1 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol WDTE RPE BOE WDSE FOSC2 FOSC1 FOSCO Unprogrammed 0 1 1 0 0 0 1 1 value Table 87 Flash User Configuration Byte UCFG1 bit description Bit Symbol Description 0 FOSCO CPU oscillator type select See Section 2 Clocks on page 14 for additional information Combinations other FOSC1 than those shown in Table 88 are reserved for future use should not be used 1 2 FOSC2 3 reserved Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 96 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 87 Flash User Configuration Byte UCFG1 bit description Bit Symbol Description WDSE Watchdog Safety Enable bit Refer to Table 88 for details BOE Brownout Detect Enable see Section 6 1 Brownout detection on page 31 RPE Reset pin enable When set 1 enables the reset function of pin P1 5 When cleared P1 5 may be used as an input pin NOTE During a power up sequence the RPE selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit 7 WDTE Watchdog
114. ics N V 2004 All rights reserved User manual Rev 02 2 March 2005 70 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Comparator 1 P0 4 CIN1A OE1 P0 3 CIN1B _ co1 oo CMP1 P0 6 P0 5 CMPREF VREF Change Detect a Change Detect P0 2 CIN2A P0 1 CIN2B Fig 31 Comparator input and output connections CP2 i Comparator 2 gt lt a or CMP2 P0 0 co2 i OE2 002aaa422 CN2 12 2 12 3 12 4 Internal reference voltage An internal reference voltage Vref may supply a default reference when a single comparator input pin is used Please refer to the P89LPC924 925 data sheet for specifications Comparator interrupt Each comparator has an interrupt flag CMFn contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register If both comparators enable interrupts after entering the interrupt service routine the user will need to read the flags to determine which comparator caused the interrupt When a compar
115. if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 0 not equal then any key connected to PortO which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs Table 68 Keypad Pattern register KBPATN address 93h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBPATN 7 KBPATN 6 KBPATN 5 KBPATN 4 KBPATN 3 KBPATN 2 KBPATN 1 KBPATN O Reset 1 1 1 1 1 1 1 1 Table 69 Keypad Pattern register KBPATN address 93h bit description Bit Symbol Access Description 0 7 KBPATN 7 0 R W Pattern bit 0 bit 7 Table 70 Keypad Control register KBCON address 94h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PATN_SEL KBIF Reset xX X xX X xX X 0 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 0
116. ilips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 102 of 105 Philips Semiconductors UM10108 18 Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or P89LPC924 925 User manual performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Application information Applications that are described herein for any of these products are for illust
117. in an addressed slave mode STA 0 No START condition or repeated START condition will be generated 6 I2EN 12C Interface Enable When set enables the 12C interface When clear the 12C function is disabled reserved 11 4 I C status register This is a read only register It contains the status code of the I2C interface The lower three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined 12C states When any of these states entered the SI bit will be set Refer to Table 62 to Table 65 for details Table 57 12C status register I2STAT address DQh bit allocation Bit 7 6 5 4 3 2 1 Symbol STA 4 STA 3 STA 2 STA 1 STA O 0 0 Reset 0 0 0 0 0 0 0 Table 58 12C Status register I2STAT address D9h bit description Bit Symbol Description 0 2 Reserved are always set to 0 3 7 STA 0 4 12C Status code 11 5 1 C SCL duty cycle registers I2SCLH and I2SCLL When the internal SCL generator is selected for the I2C interface by setting CRSEL 0 in the I2CON register the user must set values for registers I2SCLL and I2SCLH to select the data rate I2SCLH defines the number of PCLK cycles for SCL HIGH I2SCLL defines the number of PCLK cycles for SCL LOW The frequency is determined by the following formula Bit Frequency feciK 2 IZSCLH I2SCLL Where fpcix is t
118. interrupt INTLO SSTAT 6 0 is shown with ending Tx interrupt DBISEL SSTAT 4 1 002aaa928 10 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after SBUF is written provided TB8 is updated before that TB8 is shifted out TB8 must not be changed again until after TB8 shifting has been completed as indicated by the TX interrupt Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 52 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual If double buffering is enabled TB8 MUST be updated before SBUF is written as TB8 will be double buffered together with SBUF data The operation described in Section 10 17 becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SBUF The SBUF TB8 data is loaded to the shift register and a TX interrupt is generated immediately RON 5 If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL is logic 0 no more interrupt will occur If DBISEL is logic 1 and INTLO is logic 0 a TX interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a TX interrupt will occur at the end of the STOP bit of the data
119. inue until terminated by the user This mode is selected by setting the SCC1 bit in the ADMODA register Auto scan single conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel See Table 6 An interrupt if enabled will be generated after all selected channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode This mode is selected by setting the SCAN1 bit in the ADMODA register Table 7 Result registers and conversion results for fixed channel continuous conversion mode Result register Contains AD1DATO Selected channel first conversion result AD1DAT1 Selected channel second conversion result AD1DAT2 Selected channel third conversion result AD1DAT3 Selected channel forth conversion result Auto scan continuous conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A conversion of each selected input will be performed and the result placed in the result register which corresponds
120. is 2 7 V to 3 6 V generates an interrupt enable Upon a brownout interrupt BOF interrupt RSTSRC 5 will be set BOF can be cleared by writing logic 0 to the bit 0 Both brownout reset and xX 0 interrupt disabled Vpp operating range is 2 4 V to 3 6 V However BOF RSTSRC 5 will be set when Vpp falls to the Brownout Detection trip point BOF can be cleared by writing logic 0 to the bit 1 Cannot be used with operation above 12 MHz as this requires Vpp of 3 0 V or above 6 2 Power on detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing logic O to the bit Note that if BOE UCFG1 5 is programmed BOF RSTSRC 5 will be set when POF is set If BOE is unprogrammed BOF is meaningless 6 3 Power reduction modes The P89LPC924 925 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 24 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 32 of 105 Philips Semiconductors UM1 01 08 Table 24 P89LPC924 925 User manual Power reduction modes PMOD1 PCON 1 0 PMODO PCON 0 0 D
121. l Description 0 3 reserved 4 AIN10 when set enables the AD10 pin for sampling and conversion 5 AIN11 when set enables the AD11 pin for sampling and conversion 6 AIN12 when set enables the AD12 pin for sampling and conversion 7 AIN13 when set enables the AD13 pin for sampling and conversion Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 23 of 105 Philips Semiconductors UM1 01 08 4 Interrupts P89LPC924 925 User manual 4 1 The P89LPC924 925 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the P89LPC924 925 s 12 interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global enable bit EA which enables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of t
122. ler count The inaccuracy could be as much as two old clock source counts plus two new clock cycles Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the Watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to logic 1 the program should wait at least two PCLK cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the Watchdog could become disabled when CCLK turns off The Watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 78 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual MOV WFEED1 0A5H n MOV WFEED2 05AH y Watchdog oscillator A PRESCALER 8 BIT DOWN PCLK PRESCALER re COUNTER RESET 7 x i see note 1 l i SHADOW CONTROL REGISTER Hh REGISTER ry FOR WDCON AAA Vv WDCON A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK Fig 34 Watchdog timer in Watchdog Mode WDTE 1 002aaa423 MOV WFEED1 0A5H MOV WFEED2 05AH Watchdog oscillator o PCLK 32 PRESCALER Lo y 8 BIT DOWN COUNTER A A A Inte
123. leted or terminated by an interrupt When the program idle state is exited FMCON will contain status information for the cycle If an interrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the OI flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the Ol flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4 ms 2 ms for erase 2 ms for programming to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps e Write the LOAD command 00H to FMCON The LOAD command will clear all locations in the page register and their corresponding update flags e Write the address within the page register to FMADRL Since the loading the page register uses FMADRLJ 5 0 and since the erase program command uses FMADRH and FMADRL 7 6 the user can write the byte location within the page register FMADRL 5 0 and the code memory page address FMADRH and FMADRL 7 6 at this time e Write the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page register
124. llowed by a START condition will be transmitted STO flag will be reset Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 65 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual Table 63 Master Receiver mode Status code Status of the C Application software response Next action taken by the I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI STA 50h Data byte has Read data byte 0 0 0 0 Data byte will be received NOT ACK been received bit will be returned ACK has been read data byte 0 0 0 1 Data byte will be received ACK bit returned will be returned 58h Data byte has Read data byte or 1 0 x Repeated START will be transmitted been received read data byte or 0 x STOP condition will be transmitted NACK hasbeen STO flag will be reset returned read data byte 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset Table 64 Slave Receiver mode Status code Status of the I C Application software response Next action taken by the I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 60H Own SLA W has no I 2DAT action or x 0 0 0 Data byte will be received and NOT been received ACK will be returned ACK has been no I2DAT action x 0 0 1 Data byte will be recei
125. lows The output frequency is therefore one half of the Timer 0 overflow rate Refer to the Timer Counters section for details 5 ENT1 When set the PO 7 pin is toggled whenever Timer 1 overflows The output frequency is therefore one half of the Timer 1 overflow rate Refer to the Timer Counters section for details 6 EBRR UART Break Detect Reset Enable If logic 1 UART Break Detect will cause a chip reset and force the device into ISP mode 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation 15 1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or Watchdog reset had occurred If a value is written to AUXR1 that contains a logic 1 at bit position 3 all SFRs will be initialized and execution will resume at program address 0000 Care should be taken when writing to AUXR1 to avoid accidental software resets Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 80 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 15 2 Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that
126. mode Result register Contains AD1DATO First channel first conversion result AD1DAT1 Second channel first conversion result AD1DAT2 First channel second conversion result AD1DAT3 Second channel second conversion result Single step This special mode allows single stepping in an auto scan conversion mode Any combination of the four input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition The result of each channel is placed in the result register which corresponds to the selected input channel See Table 6 May be used with any of the start modes This mode is selected by clearing the BURST1 SCC1 and SCAN1 bits in the ADMODA register Conversion mode selection bits The A D uses three bits in ADMODA to select the conversion mode These mode bits are summarized in Table 9 below Combinations of the three bits other than the combinations shown are undefined Table 9 Conversion mode bits BURST1 SCC1 Scani ADC1 conversion BURSTO SCCO Scan0 ADCO conversion mode mode 0 single step 0 0 0 single step 1 fixed 0 0 1 fixed channel single channel single auto scan single auto scan single 0 1 0 fixed channel 0 1 0 fixed channel continuous continuous dual channel dual channel continuous continuous 1 0 0 auto scan 1 0 0 auto scan continuous continuous Koninklijke Philips Electronics N
127. n secured sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non volatile data storage IAP Lite provides an erase program function that makes it easy for one or more bytes within a page to be erased and programmed in a single operation without the need to erase or program any other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 64 byte page register to facilitate erasing and programing within unsecured sectors These SFRs are e FMCON Flash Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to logic Os when the command is written e FMDATA Flash Data Register Accepts data to be loaded into the page register e FMADRL FMADRH Flash memory address LOW Flash memory address HIGH Used to specify the byte address within the page register or specify the page within user code memory The page register consists of 64 bytes and an update flag for each byte When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is written the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL In addition the Koninklijke Philips Electronics N V 2004 All rights reserved User manual
128. n the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 52 12C Data register I2DAT address DAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2DAT 7 I2DAT 6 I2DAT 5 I2DAT 4 I2DAT 3 I2DAT 2 I2DAT 1 I2DAT O Reset 0 0 0 0 0 0 0 0 11 2 I C Slave Address register I2ADR register is readable and writable and is only used when the 12C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized Table 53 12C Slave Address register IZADR address DBh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC Reset 0 0 0 0 0 0 0 0 Table 54 12C Slave Address register IZADR address DBh bit description Bit Symbol Description 0 Gc 1 7 General call bit When set the general call address 00H is recognized otherwise it is ignored I2ADR1 7 7 bit own slave address When in master mode the contents of this register has no effect 11 3 12C Control register The CPU can read and write this register There are two bits are affected by hardware the SI bit and the STO bit The SI bit is set by hardware and the STO bit is
129. n will be transmitted when the bus becomes free Table 65 Slave Transmitter mode Status code Status of the IC Application software response Next action taken by the I2C I2STAT hardware to from I2DAT_ to I2CON hardware STA STO Si AA A8h Own SLA R has Load data byte or x 0 0 0 Last data byte will be transmitted been received and ACK bit will be received ACK has been load data byte x 0 0 1 Data byte will be transmitted ACK returned will be received Boh Arbitration lost in Load data byte or x 0 0 0 Last data byte will be transmitted SLA R W as and ACK bit will be received master Own load data byte x 0 0 1 Data byte will be transmitted ACK SLA R has been bit will be received received ACK has been returned B8H Data byte in Load data byte or x 0 0 0 Last data byte will be transmitted I2DAT has been and ACK bit will be received transmitted ACK load data byte x 0 0 1 Data byte will be transmitted ACK has been received will be received Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 68 of 105 Philips Semiconductors UM10108 Table 65 Slave Transmitter mode P89LPC924 925 User manual Status code I2STAT Status of the 12C hardware Application software response to from I2DAT to I2CON STA STO SI AA Next action taken by the I2C hardware COH Data byte in I2DAT has been transmitted NACK has been received No I2DAT action or 0 0
130. ncy above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage 1 0 P1 6 Port 1 bit 6 1 0 P1 7 Port 1 bit 7 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 5 of 105 Philips Semiconductors UM10108 Table 1 Pin description P89LPC924 925 User manual Symbol Pin Type Description P3 0 to P3 1 V0 Port 3 Port 3 is an 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details All pins have Schmitt triggered inputs Port 3 also provides various special functions as described below 7 1 0 P3 0 Port 3 bit 0 O XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the FLASH configuration O CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator Watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the real time clock system timer 6 1 0 P3 1 Port 3 bit
131. nfigurable port pins are programmed independently Refer to Section 5 1 Port configurations for details P1 2 and P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below 12 1 0 P1 0 Port 1 bit 0 O TXD Transmitter output for the serial port 11 1 0 P1 1 Port 1 bit 1 l RXD Receiver input for the serial port 10 VO P1 2 Port 1 bit 2 open drain when used as output 1 0 TO Timer counter 0 external count input or overflow output open drain when used as output 1 0 SCL C serial clock input output 9 VO P1 3 Port 1 bit 3 open drain when used as output l INTO External interrupt 0 input V0 SDA C serial data input output 8 V0 P1 4 Port 1 bit 4 l INT1 External interrupt 1 input 4 l P1 5 Port 1 bit 5 input only l RST External Reset input if selected via FLASH configuration A LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at powerup until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator freque
132. nklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 87 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 16 10 Using the In system programming ISP The ISP feature allows for a wide range of baud rates to be used in your application independent of the oscillator frequency It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit in a received character This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency The ISP feature requires that an initial character an uppercase U be sent to the P89LPC924 925 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initialization has been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC lt crif gt In the Intel Hex record the NN represents the number of data bytes in the record The P89LPC924 925 will accept up to 64 40H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 01 indicat
133. ode on any reset Table 46 Serial Port modes SM0 SM1 UART mode UART baud rate 00 Mode 0 shift register CCLK 16 default mode on any reset 01 Mode 1 8 bit UART Variable see Table 41 10 Mode 2 9 bit UART CCLK 32 or CCLK 16 11 Mode 3 9 bit UART Variable see Table 41 Table 47 Serial Port Status register SSTAT address BAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBMOD INTLO CIDIS DBISEL FE BR OE STINT Reset xX X xX xX X xX 0 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 47 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 48 Serial Port Status register SSTAT address BAh bit description Bit Symbol Description O STINT Status Interrupt Enable When set 1 FE BR or OE can cause an interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the combined TI RI CIDIS 0 When cleared 0 FE BR OE cannot cause an interrupt Note FE BR or OE is often accompanied by a RI which will generate an interrupt regardless of the state of STINT Note that BR can cause a break detect reset if EBRR AUXR1 6 is set to logic 1 1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI in SCON is s
134. of whether a reset or an interrupt is enabled BOF will stay set until it is cleared in software by writing logic 0 to the bit Note that if BOE is unprogrammed BOF is meaningless If BOE is programmed and a initial power on occurs BOF will be set in addition to the power on flag POF RSTSRC 4 For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the data sheet for specifications Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 31 of 105 Philips Semiconductors UM10108 P89LPC924 925 User manual Table 23 Brownout options BOE PMOD1 0 BOPD BOI EBO EA IEN0 7 Description UCFG1 5 PCON 1 0 PCON 5 PCON 4 IENO 5 O erased XX X X X X Brownout disabled Vpp 1 program 11 total x xX xX xX operating range is 2 4 V to 3 6 V med power down 11 any mode 1 brownout X X X Brownout disabled Vpp other than total detect operating range is 2 4 V to 3 6 V power down powered However BOPD is default to down logic 0 upon power up O brownout O brownout X X Brownout reset enabled Vpp detect active detect operating range is 2 7 V to 3 6 V generates Upon a brownout reset BOF reset RSTSRC 5 will be set to indicate the reset source BOF can be cleared by writing logic 0 to the bit 1 brownout 1 enable 1 global Brownout interrupt enabled Vpp detect brownout interrupt operating range
135. ogic 0 write L data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW C from Master to Slave A not acknowledge SDA HIGH O from Slave to Master S START condition 002aaa930 Fig 26 Format of Master Receiver mode After a repeated START condition the 1 C bus may switch to the Master Transmitter Mode Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 60 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual O from Master to Slave LSE Pe Ta aL e logic 0 write data transferred l logic 1 read n Bytes acknowledge A acknowledge SDA LOW A not acknowledge SDA HIGH O from Slave to Master S START condition P STOP condition SLA slave address RS repeat START condition 002aaa931 Fig 27 A Master Receiver switches to Master Transmitter after sending Repeated Start 11 6 3 Slave Receiver mode In the Slave Receiver Mode data bytes are received from a master transmitter To initialize the Slave Receiver Mode the user should write the slave address to the Slave Address Register IZADR and the I2C Control Register I2CON should be configured as follows Table 61 12C Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO Sl AA CRSEL value 1 0 0 0 1 CRSEL is not used for slave mode I2EN must be set 1 to
136. ol bit Set cleared by software to turn Timer Counter 1 on off 7 TH Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in hardware C T 0 overflow PCLK Tpi Pa Tin Trn TFn interrupt n pin O CT 1 control 5 bits 8 bits TRn on O Tn pin Gate INTn pin ENTn 002aaa919 Fig 13 Timer counter 0 or 1 in Mode 0 13 bit counter PCLK C T 0 a overflow Tapi on n n TFn gt interrupt n pin Qy CT 1 j control 8 bits 8 bits toggle TRn Gate INTn pin ENTn 002aaa920 Fig 14 Timer counter 0 or 1 in mode 1 16 bit counter PCLK CaO overflow TD om TFn interrupt npin 0 C T 1 control toggle TRn a L Tn pin Gate THn INTn pin 8 bits ENTn 002aaa921 Fig 15 Timer counter 0 or 1 in Mode 2 8 bit auto reload Koninklijke Philips Electronics N V 2004 All rights reserved 40 of 105 User manual Rev 02 2 March 2005 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual PCLK sia overflow To pi on reo TFO interrupt pin OF C T 1 i control 8 bits toggle TRO a C To pin Gate P1 2 open drain INTO pin ENTO AUXR1 4 overflow Osc 2 a ne TF1 interrupt on control to
137. ol register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO Sl AA CRSEL value 1 0 0 0 x bit rate CRSEL defines the bit rate I2EN must be set to 1 to enable the 12C function If the AA bit is logic O it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to logic 0 The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 indicating a write Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The C bus will enter Master Transmitter Mode by setting the STA bit The I C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be O8h This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 59 of 105 Philips Semiconductors UM1 01 08 P89LPC924 9
138. on the device Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 86 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Instead the page erase function can be used to erase the eight 64 byte pages located in this sector A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired Table 82 Boot loader address and default Boot vector Product Flash size End Signature bytes Sector Page Pre programmed Default Boot address Mfg id Id 1 Id 2 size size serial loader vector P89LPC924 4Kx8 OFFFh 15h DDh 1Bh 1K x8 64x8 OEOOh OFFFh OFh P89LPC925 8Kx8 1FFFh 15h DDh 1Ch 1Kx8 64x8 1E00h 1FFFh 1Fh 16 8 16 9 Hardware activation of Boot Loader The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see Figure 36 This is accomplished by powering up the device with the reset pin initially held LOW and holding the pin LOW for a fixed time after Vpp rises to its normal operating value This is followed by three and only three properly timed LOW going pulses Fewer or more than three pulses will result in the device not entering ISP mode Timing specifications may be found in the data sheet for this device This has the same effect as having a non zero status bit This allows an application to be built that will normally execute the user code but can be manually forced into ISP
139. ors UM1 01 08 5 1 5 2 P89LPC924 925 User manual Port configurations All but three I O port pins on the P89LPC924 925 may be configured by software to one of four types on a pin by pin basis as shown in Table 21 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin P1 5 RST can only be an input and cannot be configured P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Table 21 Port output configuration settings PxM1 y PxM2 y Port output mode 0 0 Quasi bidirectional 0 1 Push pull 1 0 Input only high impedance 1 1 Open drain Quasi bidirectional output configuration Quasi bidirectional outputs can be used both as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic HIGH it is weakly driven allowing an external device to pull the pin LOW When the pin is driven LOW it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin HIGH if it is left floating A second pull
140. owledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the 12C bus will not be released The P89LPC924 925 device provides a byte oriented I C interface It has four operation modes Master Transmitter Mode Master Receiver Mode Slave Transmitter Mode and Slave Receiver Mode The P89LPC924 925 CPU interfaces with the I2 C bus through six Special Function Registers SFRs I2CON l2C Control Register I2DAT 12C Data Register I2STAT I2C Status Register IZADR I C Slave Address Register I2SCLH SCL Duty Cycle Register HIGH Byte and I2SCLL SCL Duty Cycle Register LOW Byte Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 55 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual SDA I C BUS SCL P1 3 SDA P1 2 SCL OTHER DEVICE OTHER DEVICE WITH I2C BUS WITH I2C BUS P89LPC924 925 INTERFACE INTERFACE 002aaa952 Fig 24 I2C bus configuration 11 1 _1 C Data register I2DAT register contains the data to be transmitted or the data received The CPU can read and write to this 8 bit register while it is not in the process of shifting a byte Thus this register should only be accessed whe
141. r or the Watchdog oscillator the delay is 224 OSCCLK cycles plus 60 us to 100 ps 2 8 CPU Clock CCLK modification DIVM register The OSCCLK frequency can be divided down by an integer up to 510 times by configuring a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK N is the value of DIVM Since N ranges from 0 to 255 the CCLK frequency can be in the range Of fosc tO fosc 510 for N O CCLK fosc This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution 2 9 Low power select The P89LPC924 925 is designed to run at 12 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MH
142. rative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 103 of 105 Philips Semiconductors UM10108 19 Contents P89LPC924 925 User manual 1 1 1 1 2 1 3 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 1 3 2 3 3 3 4 3 5 3 6 3 7 4 1 4 2 5 1 5 2 5 3 5 4 5 5 5 6 5 7 6 1 6 2 6 3 7 1 8 1 8 2 8 3 8 4 8 5 Introduction 0 0 0c eee ee eee eee 3 Pin Configuration 0 00 0 ee 3 Special function registers 8 Memory organization 13 CIOCKS 2 25 5 o ends rnnr i Skee RIER RE E 14 Enhanced CPU 0000000s 14 Clock definitions 000 14 Clock output 2 2 0 0 eee eee ee 15 On chip RC oscillator option 15 Watchdog oscillator option 16 External clock input option 16 Oscillator Clock OSCCLK wake up delay 17 CPU Clock CCLK modification DIVM register nes cheek eae eee 17 Low power select 220 055 17 A D comverter 002 cece eee eee eee 17 FOAtUIES jnc fc sea kale Ge Oe ede ee 18 A D operating modes 4 19 Trigger modes 00 e eee eee 21 DAC output to a port pin with high impedance 2
143. re selected by setting up the microcontroller s registers before making a call to PGM_MTP at FFO3H The IAP calls are shown in Table 85 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 91 of 105 Philips Semiconductors UM1 01 08 16 12 16 13 16 14 P89LPC924 925 User manual IAP authorization key IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call This authorization key is set by writing 96H to RAM location FFH For example MOV RO 0FFH MOV RO0 96H CALL PGM_MTP After the function call is processed by the IAP routine the authorization key will be cleared Thus it is necessary for the authorization key to be set prior to EACH call to PGM_MTP that requires a key If an IAP routine that requires an authorization key is called without a valid authorization key present the MCU will perform a reset Flash write enable This device has hardware write enable protection This protection applies to both ISP and IAP modes and applies to both the user code memory space and the user configuration bytes UCFG1 BOOTVEC and BOOTSTAT This protection does not apply to ICP or parallel programmer modes If the Activate Write Enable AWE bit in BOOTSTAT 7 is a logic 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled
144. result status if Fm_stat amp Ox0F 0 prog_fail 1 else prog_fail 0 return prog_fail In circuit programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC924 925 through a two wire serial interface Philips has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Vpp Vss P0 5 P0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature ISP and IAP capabilities of the P89LPC924 925 An In Application Programming IAP interface is provided to allow the end user s application to erase and reprogram the user code memory In addition erasing and reprogramming of user programmable bytes including UCFG1 the Boot Status Bit and the Boot Vector is supported As shipped from the factory the upper 512 bytes of user code space contains a serial In System Programming ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot loader will in turn call low level routines through the same common entry point that can be used by the end user appli
145. rrupt 1 SHADOW CONTROL REGISTER REGISTER a a ry FOR WDCON AAA pees erer eao J J worn woror woco 002aaa939 WDCON A7H Fig 35 Watchdog timer in Timer Mode WDTE 0 14 4 Watchdog timer in Timer mode Figure 35 shows the Watchdog timer in Timer Mode In this mode any changes to WDCON are written to the shadow register after one Watchdog clock cycle A Watchdog underflow will set the WDTOF bit If IENO 6 is set the Watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the Watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode Koninklijke Philips Electronics N V 2004 All rights reserved 79 of 105 User manual Rev 02 2 March 2005 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual 14 5 Power down operation The WDT oscillator will continue to run in power down consuming approximately 50 uA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device see Section 14 3 Power down mode will also prevent PCLK from runnin
146. s on page 32 for details External Interrupt pin glitch suppression Most of the P89LPC924 925 pins have glitch suppression circuits to reject short glitches please refer to the P89LPC924 925 data sheet Dynamic characteristics for glitch filter specifications However pins SDA INTO P1 3 and SCL TO P1 2 do not have the glitch suppression circuits Therefore INT1 has glitch suppression while INTO does not Table 19 Summary of interrupts Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up External interrupt O IEO 0003h EXO IENO 0 IPOH 0 IP0 0 1 highest Yes Timer O interrupt TFO OOOBh ETO IENO 1 IPOH 1 IPO 1 4 No External interrupt 1 IE1 0013h EX1 IENO 2 IPOH 2 IP0 2 7 Yes Timer 1 interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IP0 3 10 No Serial port TX and RX Tl and RI 0023h ES ESR IENO 4 IPOH 4 IP0 4 13 No Serial port RX RI Brownout detect BOF 002Bh EBO IENO 5 IPOH 5 IPO 5 2 Yes Watchdog timer Real time clock WDOVF RTCF 0053h EWDRT IENO 6 IPOH 6 IP0 6 3 Yes 12C interrupt Sl 0033h El2C IEN1 0 IPOH O IPO 0 5 No KBI interrupt KBIF 003Bh EKBI IEN1 1 IPOH O IPO 0 8 Yes Comparators 1 and 2 interrupts CMF1 CMF2 0043h EC IEN1 2 IPOH 0 IPO 0 11 Yes Serial port TX TI 006Bh EST IEN1 6 IPOH 0 IP0 0 12 No ADC ADCI1 BNDI1 0073h EAD IEN1 7 IP1H 7 IP1 7 15 lowest No Koninklijke Philips Electronics N V
147. s of bits 5 0 of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register quartz crystal or ceramic resonator P89LPC924 925 _ XTAL1 I I Pe 1 el i __ XTAL2 002aaa951 Note The oscillator must be configured in one of the following modes Low frequency crystal medium frequency crystal or high frequency crystal 1 A series resistor may be required to limit crystal drive levels This is especially important for low frequency crystals see text Fig 4 Using the crystal oscillator 2 4 On chip RC oscillator option The P89LPC924 925 has a TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 Note the initial value is better than 1 please refer to the data sheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator frequency Table 4 On chip RC oscillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK E
148. ssed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC924 925 has 4 kB 8 kB of on chip Code memory Table 3 Data RAM arrangement Type Data RAM Size bytes DATA Directly and indirectly addressable memory 128 IDATA Indirectly addressable memory 256 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 13 of 105 Philips Semiconductors UM1 01 08 2 Clocks P89LPC924 925 User manual 2 1 2 2 2 2 1 2 2 2 2 2 3 2 2 4 Enhanced CPU The P89LPC924 925 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clock definitions The P89LPC924 925 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency see Figure 5 and Section 2 8 CPU Clock CCLK modification DIVM register
149. t bit if REN 1 SFR space The UART SFRs are at the following locations shown in Table 40 Table 40 UART SFR addresses Register Description SFR location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial Port UART Address A9H SADEN Serial Port UART Address Enable B9H SSTAT Serial Port UART Status BAH BRGR1 Baud Rate Generator Rate HIGH Byte BFH BRGRO Baud Rate Generator Rate LOW Byte BEH BRGCON Baud Rate Generator Control BDH Baud Rate generator and selection The P89LPC924 925 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1 and BRGRO SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 19 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is set The independent Baud Rate Generator uses CCLK Updating the BRGR1 and BRGRO SFRs The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is logic 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO or BRGR1 is written when BRGEN 1 the result is unpredictable Table 41 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON 1 Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 0 0 X
150. the Timer function the timer is incremented every PCLK In the Counter function the register is incremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 The external input is sampled once during every machine cycle When the pin is HIGH during one cycle and LOW in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes 2 machine cycles 4 CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 which are selected by bit pairs TnM1 TnMO in TMOD and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different The operating modes are described later in this section Table 31 Timer Counter Mode register TMOD address 89h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1IGATE T1C T TiM1 T1iMO TOGATE TOC T TOM1 TOMO Reset 0 0 0 0 0 0 0 0 Table 32 Timer Count
151. the P89LPC924 925 1 eee ee 86 16 6 Boot ROM 2 0 0 e eee eee ee 86 16 7 Power on reset code execution 86 16 8 Hardware activation of Boot Loader 87 16 9 In system programming ISP 87 16 10 Using the In system programming ISP 88 16 11 In application programming IAP 91 16 12 IAP authorization key 92 16 13 Flash write enable 92 16 14 Configuration byte protection 92 16 15 IAP error statuS 00000 eee 93 16 16 User configuration bytes 96 16 17 User security bytes 97 16 18 Boot Vector register 04 98 16 19 Boot status register 98 17 Instruction Set 00 cece eee 99 18 Disclaimers 2 00 c eee eee eee eee 103 PHILIPS P89LPC924 925 User manual Koninklijke Philips Electronics N V 2004 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Date of release 2 March 2005 Published in
152. this channel 3 ADCI1 A D Conversion complete Interrupt 1 Set when any conversion or set of multiple conversions has completed Cleared by software 4 EDGE1 When 0 an Edge conversion start is triggered by a falling edge on P1 4 When 1 an Edge conversion start is triggered by a rising edge on P1 4 5 TMM1 Timer Trigger Mode 1 Selects either stop mode TMM1 0 or timer trigger mode TMM1 1 when the ADCS11 and ADCS10 bits 00 6 ENADCI1 Enable A D Conversion complete Interrupt 1 When set will cause an interrupt if the ADCI1 flag is set and the A D interrupt is enabled 7 ENBI1 Enable A D boundary interrupt 1 When set will cause an interrupt if the boundary interrupt 1 flag BNDI1 is set and the A D interrupt is enabled Table 12 A D Mode Register A ADMODA address COh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BNBI1 BURST1 SCC1 SCAN1 Reset 0 0 0 0 0 0 0 0 Table 13 A D Mode Register A ADMODA address COh bit description Bit Symbol Description 0 3 reserved 4 SCAN1 when 1 selects single conversion mode auto scan or fixed channel for ADC1 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 22 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 13 A D Mode Register A ADMODA address COh bit description Bit Symbol Description SCC1 when 1 selects fixed channel
153. till set Cleared by software 2 BR Break Detect flag A break is detected when any 11 consecutive bits are sensed LOW Cleared by software FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be logic 0 when double buffering is disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO When the first character is written the transmit interrupt is generated immediately after SBUF is written 5 CIDIS Combined Interrupt Disable When set 1 RX and TX interrupts are separate When cleared 0 the UART uses a combined TX RX interrupt like a conventional 80C51 UART This bit is reset to logic 0 to select combined interrupts 6 INTLO Transmit interrupt position
154. timer reset enable When set 1 enables the Watchdog timer reset When cleared 0 disables the Watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 88 for details Table 88 Oscillator type selection FOSC 2 Oscillator configuration 0 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 20 30 tolerance 011 Internal RC oscillator 7 373 MHz 2 5 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 12 MHz 16 17 User security bytes This device has three security bits associated with each of its eight sectors as shown in Table 89 Table 89 Sector Security Bytes SECx bit allocation Bit 7 6 5 4 3 2 1 0 Symbol EDISx SPEDISx MOVCDISx Unprogrammed 0 0 0 0 0 0 0 0 value Table 90 Sector Security Bytes SECx bit description Bit Symbol Description 0 MOVCDISx MOVC Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte ina MOVC protected sector will return invalid data This bit can only be erased when sector x is erased 1 SPEDISx Sector Program Erase Disable x Disables program or erase of all or part of sector x This bit and sector x are erased by either a sector erase command ISP IAP commercial programmer or a global erase command commercial programmer 2 EDISx
155. tted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 67 of 105 Philips Semiconductors UM10108 Table 64 Slave Receiver mode P89LPC924 925 User manual Status code Status of the I2C Application software response Next action taken by the 12C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA AOH A STOP condition No I2DAT action 0 0 0 0 Switched to not addressed SLA or repeated mode no recognition of own SLA or START condition General call address hasbeen received ho I2DAT action 0 0 0 1 Switched to not addressed SLA while still mode Own slave address will be addressed as recognized General call address SUE er will be recognized if I2ADR 0 1 SLA TRX no I2DAT action 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START conditio
156. up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled LOW by an external device the weak pull up turns off and only the very weak pull up remains on In order to pull the pin LOW under these conditions the external device has to sink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage The third pull up is referred to as the strong pull up This pull up is used to speed up LOW to HIGH transitions on a quasi bidirectional port pin when the port latch changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin HIGH The quasi bidirectional port configuration is shown in Figure 8 Although the P89LPC924 925 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 27 of
157. up condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit Note Ona Power on reset both BOF and this bit will be set while the other flag bits are cleared 5 BOF Brownout Detect Flag When Brownout Detect is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both POF and this bit will be set while the other flag bits are cleared 6 7 reserved 7 1 Reset vector Following reset the P89LPC924 925 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the HIGH byte of the address and the LOW byte of the address 00h The Boot address will be used if a Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 36 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device has been forced into ISP mode Otherwise instructions will be fetched from address OOOOH 8 Timers 0 and 1 The P89LPC924 925 has two general purpose counter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters see Table 32 An option to automatically toggle the TX pin upon timer overflow has been added In
158. ut A l KBI2 Keyboard input 2 l AD11 ADC1 channel 1analog input 18 1 0 P0 3 Port 0 bit 3 l CIN1B Comparator 1 positive input B l KBI3 Keyboard input 3 l AD12 ADC1 channel 2 analog input 17 1 0 P0 4 Port 0 bit 4 l CIN1A Comparator 1 positive input A l KBI4 Keyboard input 4 l AD13 ADC1 channel 3 analog input l DAC1 Digital to analog converter output 1 16 VO P0 5 Port 0 bit 5 l CMPREF Comparator reference negative input l KBI5 Keyboard input 5 14 1 0 P0 6 Port 0 bit 6 O CMP1 Comparator 1 output l KBI6 Keyboard input 6 13 1 0 P0 7 Port 0 bit 7 1 0 T1 Timer counter 1 external count input or overflow output l KBI7 Keyboard input 7 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 4 of 105 Philips Semiconductors UM10108 Table 1 Pin description P89LPC924 925 User manual Symbol Pin Type Description P1 0 to P1 7 I O IE Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the co
159. ved and ACK received will be returned 68H Arbitration lostin No l2DAT action x 0 0 0 Data byte will be received and NOT SLA R W as or ACK will be returned master Own no I2DAT action x 0 0 1 Data byte will be received and ACK SLA W has been will be returned received ACK returned 70H General call No I2DAT action x 0 0 0 Data byte will be received and NOT address 00H or ACK will be returned has been no I2DAT action x 0 0 1 Data byte will be received and ACK received ACK will be returned has been returned 78H Arbitration lost in no I2DAT action or x 0 0 0 Data byte will be received and NOT SLA R W as ACK will be returned master General 9 I2DAT action x 0 0 1 Data byte will be received and ACK call address has will be returned been received ACK bit has been returned 80H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned own SLA address read data byte xX 0 0 1 Data byte will be received ACK bit Data has been will be returned received ACK has been returned Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 66 of 105 Philips Semiconductors UM10108 Table 64 Slave Receiver mode P89LPC924 925 User manual Status code Status of the I2C Application software response Next action taken by the I2C I2STAT hardware to from I2DAT to I2CON hardware STA STO SI AA 88H Previously Rea
160. x04ssaaaacc Where XXXX required field but value is a don t care aaaa sector page address ss 01 erase sector 00 erase page cc checksum Example 03000004010000F8 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 90 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual Table 83 In system Programming ISP hex record formats Record type Command data function 05 Read Sector CRC 01xxxx05aacc Where XXXX required field but value is a don t care aa sector address HIGH byte cc checksum Example 0100000504F6cc 06 Read Global CRC 00xxxx06cc Where XXXX required field but value is a don t care cc checksum Example 00000006FA 07 Direct Load of Baud Rate 02xxxx07HHLLcc Where XXXX required field but value is a don t care HH HIGH byte of timer LL LOW byte of timer cc checksum Example 02000007FFFFcc 08 Reset MCU 00xxxx08cc Where XXXX required field but value is a don t care cc checksum Example 00000008F8 16 11 In application programming IAP Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors pages security bits configuration bytes and device id All calls are made through a common interface PGM_MTP The programming functions a
161. z or slower 3 A D converter The P89LPC924 925 has an 8 bit 4 channel multiplexed successive approximation analog to digital converter module ADC1 and one DAC module DAC1 A block diagram of the A D converter is shown in Figure 6 The A D consists of a 4 input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs The control logic in combination with the successive approximation register SAR drives a digital to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 02 2 March 2005 17 of 105 Philips Semiconductors UM1 01 08 P89LPC924 925 User manual CONTROL LOGIC 002aaa791 Fig 6 A D converter block diagram 3 1 Features e An 8 bit 4 channel multiplexed input successive approximation A D converter e Four A D result registers e Six operating modes Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode Dual channel continuous conversion mode Single step mode e Three conversion start modes Timer triggered start Start immediately Edge triggered e 8 bit conversion time of gt 3 9 us at an ADC clock of 3 3 MHz e Interrupt or polled operation e Boundary limits interrupt

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