XSA Board V1.1, V1.2 User Manual
Contents
1. A O BOONWNBKWODOOWUIN 3 256 KByte Flash An Atmel AT49F002 Flash RAM with 256 KBytes of storage 256K x 8 is connected to both the FPGA and CPLD as shown below The CPLD and FPGA both have access to the Flash RAM Typically the CPLD will program the Flash with data passed through the parallel port If the data is an FPGA configuration bitstream then the CPLD can be configured to program the FPGA with the bitstream from Flash whenever the XSA Board is powered up See the application note XSA BOARD V1 1 V1 2 USER MANUAL 23 KSA Flash Programming and Spartanll Configuratior for more details on how the CPLD loads the Flash with a configuration bitstream and then transfers it to the FPGA After power up the FPGA can read and or write the Flash Of course the CPLD and FPGA have to be programmed such that they do not conflict if both are trying to access the Flash The Flash can be disabled by raising the CE pin to a logic 1 in which case the I O lines connected to the Flash can be used for general purpose communication between the FPGA and the CPLD 256 KByte Flash RAM I lt A 0 O A n LL x N 5 5 O2. 758 60 FLASH A5 77 5 76 59 FLASH A6 6 CODEC SDOUT_DIPSW4 7 9 78 PARPORTS6 867 jPushbuton SPARE _ 79 17 2 7 j DIPSWi XcheckerTRIG FPGA CPLD XSAFuncion Proto Pin XSTendFunctinns 85 8 DIPSW2 JXcheckerRST 8 18 WGAKRED 84 149 VWGAZHSYNC 85 20 8 amp 6 j 1 3 8 124 0 _ 88 13 MASTER JXcheckerCLK j lt 9 7 PS2 DATA PUSHBUTTON 25 VGABLUEO 94 26 VGABLUE 95 j SDRAMQO 96 7 4 9 SDRAMQ 22 _ 100 SDRAM Q14 0 0 101 1000 4 10 E06 jsPARHMAMM2 9 36 SPARTPAMMO 4 7 JSPARTAMM 1 1 12 4 13 7 4 50 4 14 115 J SDRAMQS 4 16 SDRAM Q10 0 0 0 j 1 7 J SDRAMQ 6 18 1200 4 121 JSDRAMQB 122 0 123 SDRAM WE 7 4 124 SDBRMQMH 4 120 SDRAM CAS 129
3. gt 42 2 4 5 6 7 8 e 9 10 5V Y so NM S2 14 53 56 58 54 Sd P WW p 54 o CNCOST 1 3333 amp ED EC EL OOOO XSA BOARD V1 1 V1 2 USER MANUAL 24 Seven Segment LED The XSA Board has a 7 segment LED digit for use by the FPGA or the CPLD The segments of this LED are active high meaning that a segment will glow when a logic high is applied to it The LED shares the same pins as the eight bits of the Flash RAM data bus Four Position DIP Switch The XSV Board has a bank of four DIP switches accessible from the CPLD and FPGA When closed or ON each switch pulls the connected pin of the FPGA and CPLD to ground Otherwise the pin is pulled high through a resistor when the switch is open or OFF When not being used the DIP switches should be left in the open or OFF configuration so the pins of the FPGA and CPLD are not tied to ground and can freely move between logic low and high levels The DIP switches also share the same pins as the uppermost four bits of the Flash RAM address bus If the Flash RAM is programmed with several FPGA bitstreams then the DIP switches can be used to select a particular bitstreams which will be loaded into the FPGA by the CPLD on power up PS 2 Port The XSA Board provides a PS 2 style interface mini DIN connector J4 to either a keyboard or a mouse The FPGA receives two signals from the PS 2 interface a clock signal and a
4. This is a simplified file format that does not use checksums XESS 24 XESS hexadecimal format with 24 bit addresses XSA BOARD V1 1 V1 2 USER MANUAL 17 XESS 32 XESS hexadecimal format with 32 bit addresses After the data is uploaded from the Flash the CPLD on the XSA Board is left with the Flash interface programmed into it You will need to reprogram the CPLD with either the parallel port or Flash configuration circuit before the board will function again The CPLD configuration bitstreams are stored in the following files XSTOOLS XSA dwnidpar svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure the FPGA through the parallel port XSTOOLS XSA fenfg svf Drag amp drop this file into the FPGA CPLD area and click on the Load button to put the XSA in a mode where it will configure the FPGA with the contents of the Flash device upon power up Downloading and Uploading Data to the SDRAM in Your XSA Board The XSA Board contains a 16 MByte synchronous DRAM 8M x 16 SDRAM whose contents can be downloaded and uploaded by GXSLOAD This is useful for initializing the SDRAM with data for use by the FPGA and then reading the SDRAM contents after the FPGA has operated upon it The SDRAM is loaded with data by dragging amp dropping one or more EXO MCS HEX and or XES files into the RAM area of the GXSLOAD window and then clicking on the Load button T
5. xsal_2 sch 8 Mon Feb 11 08 37 20 2002 U9C U9D 5 89 o8 gt PP CO 741514 741514 U9B HEINE 3 gt gt PP C1 J8 14 gt 74LS14 J8 2 D gt PP DO J8 15 gt PP S3 U9A U9E J8 3 gt 1 gt T p gt aoe J8 16 D 74LS14 74LS14 48 4 D gt PP C2 J8 17 gt PP D2 J8 5 D gt PP C3 J8 18 D gt mi gt PP D3 48 6 gt PP D4 MES J8 7 D gt PP D5 22 J8 8 D PP D6 pn 48 9 gt PP D7 J8 10 5 Hx XCBUSO78 J8 23 D 3 USF NO 12 13 J8 11 gt Pt O O PP S7 J8 24 D gt 9 EN 74LS14 54 48 15 gt 18 27 gt Er 1 R13 2 J8 26 gt C30 JE COMPANY XESS Corporation XSA Board Parallel Port Interface RELEASED DATED SHEET xsal_2 sch 9 Mon Feb 11 08 37 20 2002 XCBUS002 XCBUS063 XCBUS012 L s16 XCBUS064 201 84 XCBUS013 L J 1 27 XCBUS065 L 3 XCBUSO15 L 41 28 XCBUS066 O 0 4 XCBUS018 L J 1 31 XCBUS067 I 15 XCBUSO19 O s XCBUS068 5020 H J1 29 XCBUS069 ma XCBUS021 L J n3 XCBUS072 41 55 XCBUS022 ann XCBUSO74 H 53 XCBUS023 L J 01 54 XCBUS075 L 4 79 5026 XCBUS076 L J 9 77 XCBUS027 L J 1 37 XCBUS077 L 41 6 XCBUS028 L J 1 50 XCBUS078 O s 9 XCBUS029 H 1 51 XCBUS079 L J 1 67 XCBUS030 L 1 56 XCBUS080 L 7 XCBUSO31 L 21 69 XCBUSOB3 EL XCBUS032 L J 1 68 XCBUS084 L XCBUS034 L J XCBUS085 01 19 XCBUS037 L J i739 XCBUS086 XCBUS038 L J eds XCBUS087 L J 1 23 XCBUS039 L J ass XCB
6. The shunt should be installed on pins 2 3 if the XSA Board is to be downloaded using the XESS GXSLOAD software utility This is a header that provides access to the 5V and GND references on the board No shunt should be placed on this header XSA BOARD V1 1 V1 2 USER MANUAL 10 Testing Your XSA Board Once your XSA Board is installed and the jumpers are in their default configuration you can test the board using the GUI based GXSTEST utility as follows You start GXSTEST by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the window shown below X gxstest Board Type 00 ES Port Exit Next you select the parallel port that your XSA Board is connected to from the Port pulldown list GXSTEST starts with parallel port LPT1 as the default but you can also select LPT2 or LPT3 depending upon the configuration of your PC After selecting the parallel port you select either the XSA 50 or XSA 100 item in the Board Type pulldown list Then click on the TEST button to start the testing procedure GXSTEST will configure the FPGA to perform a test procedure on your XSA Board After several seconds you will see a O displayed on the LED digit if the test completes successfully Otherwise an E will be displayed if the test fails A status window will also appear on your PC screen informing you of the success or failure of the test If your XSA Board fails the
7. enters a dedicated clock input of the CPLD Then the CPLD can output a clock signal to a dedicated clock input of the FPGA To get a precise frequency value or to sync the XSA circuitry with an external system you can insert an external clock signal through pin 64 of the prototyping header This external clock replaces the internal 100 MHz clock source in the DS1075 oscillator You must use the GXSSETCLK software utility to enable the external clock input of the DS1075 Clock signals can also be directly applied to two of the dedicated clock inputs of the FPGA through the pins of the prototyping header 5V 1 lt PP CO J6 o2 DS1075 lt Pin 64 Pin 1 18 88 42 17 3 Spartan ll XC9572XL XSA BOARD V1 1 V1 2 USER MANUAL FPGA CPLD z 100 MHz Prog Osc 16 MByte Synchronous DRAM A Hynix HY57V281620AT H SDRAM with 16 MBytes of storage 8M x 16 is connected to the FPGA as shown below Note that the clock signal to the SDRAM is also re routed back to a dedicated clock input of the FPGA This makes it easy to synchronize the internal operations of the FPGA with the SDRAM operations 001 _ 4 8 16 SDRAM lt O A LL c c o
8. to access the Flash RAM They can be used for general purpose under the following conditions When the FPGA is configured bitstream data will be driven onto the Flash data bus 39 44 46 49 57 60 62 and 67 so any external logic should be disabled using the DONE pin Also after the configuration the Flash chip enable 41 should be driven high to disable the Flash RAM so it doesn t drive the data bus pins In addition the standard parallel port interface loaded into the CPLD dwnldpar svf will drive eight of the Flash RAM pins 42 43 47 48 50 51 58 65 with the logic values found on the eight data lines of the parallel port The CPLD will have to be reprogrammed so it does not drive these pins if you wish to use them for accessing external signals VGA Pins 12 13 19 20 21 22 23 26 When not used to drive a VGA monitor these pins can be used for general purpose I O through the prototyping header When used as I O the REDO RED1 12 13 GREENO GREEN 1 19 20 BLUEO BLUE1 21 22 pairs have an impedance of approximately 1 KO between them due to the presence of the resistor ladder DAC circuitry PS 2 Pins 93 94 When not used to access the PS 2 keyboard mouse port these pins can be used as general purpose I O through the prototyping header Global Clock Pins 15 18 These pins can be used as global clock inputs or general purpose inputs They cannot be used as outputs Free Pins 77 78 7
9. 4n 2 B XCRUSIII 141 XCBuS141 4 RSH 4 7 B 06 XCB 06 106 M2 500 2 XCBUS142 142 TMS XCBUSO 92 TDI nco HOS TDO c u or o o Do NC1 5822225222292929 WRITE 9 C5 C5 C5 CO C5 CO C5 Co C5 Co C5 Co C5 Co C5 BUSY DOUT 3 3V 2 5V COMPANY XESS Corporation TITLE XSA Board Spartan FPGA RELEASED XCBUSL001 144 0 01uF xsal_2 sch 2 Mon Feb 11 08 37 19 2002 N D5 XCBUSO60 8 5 OE K xcRus043 0 o TCK Kk xcRuson2 06 XCB 08 D7 XCBUSO6 CE XCBUSO4 CS TDI BUSO BSY BUSO CCL BUSO WRITE TDO XCB 19 U2 As raison s XC9572XL vQ64 M A7 XCBUSORS A6 Kk xcRus076 A4 Kk xcRus074 A3 Kk xcRus027 A2 Kk xcRusn2R A1 xcausn20 1 AO Kk xcRusn4n DO Kk xcRusnig D1 Kk xcRus044 D2 C xceusoss D3 K xcRusn4o D4 xcRus057 C17 C18 C19 0 01uF 0 01uF 0 01uF COMPANY XESS Corporation XSA Board CPLD Interface RELEASED DATED SHEET OF PROGRAM DONE XCBUS 001 144 C20 0 01uF xsal_2 sch 3 Mon Feb 11 08 37 19 2002 U3 AT49F002 01 4O 01 4 C42 XCBUS054 XCB 4 XCBUS063 N O XCBUS056 Kk xcausns amp 6 XCBUS 001 144 XESS Corporation XSA Board Flash RAM RELEASED DAT
10. 9 80 83 84 85 86 87 These pins are not connected to any other devices on the XSA Board so they can be used without restrictions as general purpose I O through the prototyping header JTAG Pins 2 32 34 142 These pins are used to access the JTAG features of the FPGA They cannot be used as general purpose pins XSA BOARD V1 1 V1 2 USER MANUAL 30 XSA Pin Connections The following tables list the pin numbers of the Spartan Il FPGA and the XC9572XL CPLD along with the pins of the other chips that they connect to on the XSA Board The columns of the table are arranged as follows Column 1 lists the Spartan II FPGA pin It is left blank if there is no connection to the FPGA for this function Pins marked with are useable as general purpose I O through the prototyping header pins marked with can be used as general purpose I O only if the CPLD interface is reprogrammed as described previously pins with no marking cannot be used as general purpose at all Column 2 lists the XC9572XL CPLD pin It is left blank if there is no connection to the CPLD for this function Column 3 lists the pins of other devices on the XSA Board that are connected to the associated FPGA and or CPLD pin Column 4 lists the pin of the XSA prototyping header that is connected to the associated FPGA and or CPLD pin Columns 5 7 list the pins of devices on the Xstend Board that will connect to the FPGA and or CPLD when the XSA Bo
11. AMD BARLD2 46 5 21 0 54 39 RAMD2 47 43 FLASH A11 PARPORT D3 59 8 RRLED SO 48 44 FLASH A9 PARPORT D1_ 460 96 4 6 FLASH D3 LED S6 38 50 45 FLASH A8 PARPORT DO_ 78 LLED S3 517 46 FLASH A13 PARPORT D5 79 4 LLED S4 54 47 FLASH A14 DIPSW1A 82 5 LLED S5 56 48 FLASH AI7DIPSWID 83 6 6 1 57 7 FLASH DALED S5 7 35 RAMD4 BARLDS 2 58 49 FLASH WE PARPORT D6 62 5 50 j FLASH RESET 7 66 CODECLRCK 60 8 FLASH DSLEDSS 490 RAM D6 BARLD7 627 9 FLASH D amp LED 2 181 05 67 51 FLASH A16 DIPSWIC 84 64 52 3 LED S0 657 56 FLASH A12 PARPORT D4 24 LED S 66 58 1 5 LED S2 67 10 FLASH DZLEDSO 10 2 _ 68 38 41 jRAMDO BARLED 1 _ 69 39 55 Pushbutton PROGRAM Xchecker PROG 72 40 53 Xchecker DONE_ 74 61 FLASFAA 70 5
12. ED SHEET xsal_2 sch 4 Mon Feb 11 08 37 19 2002 U4 SDRAM 256MB XCBUSL001 144 COMPANY XESS Corporation XSA Board Sync DRAM DRAWN DATED REV RELEASED DATED SHEET xsal_2 sch 5 Mon Feb 11 08 37 19 2002 R2C RED1 XCBUS013 3 AAN 6 330 REDO 05012 6 NU 3 680 R2B GREEN 05020 2 ANN 7 330 R1B GREENO 05019 7 MV 680 R2A BLUEI 05022 1 2 8 530 RIA BLUEO 05021 8 AAA 680 HSYNC XCBUS023 VSYNC XCBUS026 R3E 4 7K R3D NG 4 7K 12 R2D 330 XCBUS094 PS2 CLK RID Ann 4 XCBUSO93 PS2 DATA 680 D2 S4 XCBUS046 6 SW PUSH NO Sw2 w J3 13 D3 S6 XCBUS049 5 AAA D4 S5 XCBUS057 4 ANNE EPA 05 53 XCBUS060 3 14 06 52 XCBUS062 2 ANNE D7 S0 XCBUS067 1 ANNE 10 00 51 05039 8 AAN 9 D1 DP XCBUS044 7 10 XCBUSL001 144 COMPANY XESS Corporation mE XSA Board PS 2 Port VGA Port LED DRAWN DATED REV V1 2 RELEASED DATED SHEET OF xsal_2 sch 6 Mon Feb 11 08 37 19 2002 PP CO 41 64 PROG OSC 0 01uF 0 01uF ls Ll XSA Board Programmable Oscillator xsal_2 sch 7 Mon Feb 11 08 37 20 2002 PWRPLUG 95 3 SWITCH 1N4148 1N4148 COMPANY XESS Corporation XSA Board Regulated Power Supplies
13. SA Board can be plugged into a solderless protoboard with holes spaced at 0 1 intervals One of the A C E protoboards from 3M is a good XSA BOARD V1 1 V1 2 USER MANUAL 6 choice Once plugged in many of the pins of the FPGA are accessible to other circuits on the protoboard The numbers printed next to the rows of pins on your XSA Board correspond to the pin numbers of the FPGA Power can still be supplied to your XSA Board though jack J9 or power can be applied directly through several pins on the underside of the board Just connect 5V 3 3V 2 5V and ground to the pins of your XSA Board listed in e Table 1 Power supply pins for the XSA Board Voltage Pin Note 5V 2 3 3V 22 Remove the shunt from jumper J7 if you wish to use your own 3 3V supply Leave the shunt on jumper J7 to generate the 3 3V supply from the 5V supply 2 5V 54 Remove the shunt from jumper J2 if you wish to use your own 2 5V supply Leave the shunt on jumper J2 to generate the 2 5V supply from the 3 3V supply GND 52 Parallel Port e Figure 1 External connections to the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL PC Parallel Port Extemal Clock Input 100 MHz Osc 9VDC Power Supply 3 3V GND Pushbutton CPLD Flash RAM 5V Spartan II FPGA SDRAM Pushbutton 2 5V PS 2 Mouse VGA Monitor or Keyboard
14. SDRAMCLK 4 00 0 130 SDRAM RAS 131 4 132 ISDRAMYCS 7 13 5 2 T 134 SDRAMBA0 7 7 136 0 17 X SDRAMBA 138 SDRAMA9 139 SDRAMAO 4 140 J SDRAMAB 4 141 SDRAMA0 12 18 SPARTAN TMS 17 XcheckerTMS 30 29 4 5 J 1 28 JPARPORFCACPLDTD 4 33 JPARPORFTD 2 PARPORT D1 1 31 2 27 5 JPARPORFDA 1 4 PARPORT DS 3 22 07 1 4 4 0 JPARPORESA 4 ___ 35 55 53 PARPORT S7 CPLD TDO 1 1 7 l j _ A XSA Schematics The following pages show the detailed schematics for the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 32 xsal_2 sch 1 Mon Feb 11 08 37 19 2002 3 3V 2 5V cN rO lt t u 00 O O cN Fu 5 83338333888 888558855 E gt 50900 n BUSANA UA TTSSSSSUb 155 B 83 XCBUS051 ANT 2 VREFO 1 VREF3_2 RUSOD7 VREF0_2 65 X CBUS065 4 R 010 10
15. US088 L J 01 24 XCBUS040 en XCBUS093 L J 41 38 XCBUS041 31 57 XCBUS094 L J J1 25 XCBUS042 1 65 XCBUS106 L J 01 26 XCBUS043 ES 1 58 XCBUS109 O 1 12 XCBUS044 1 61 XCBUS111 XCBUS046 Ji 40 XCBUS142 L J J 21 XEBUS047 91 39 91 17 XCBUS048 L J 4599 41 60 i XCBUS050 O vi 38 OO Ji 42 41 78 4 91 43 XCBUSGER 91 79 i 31 44 NEBUSUSE O 31 82 i 31 46 XCHISUET O vi 83 A 5 47 XEHUSHER O 31 35 il 31 48 91 62 A Ji 49 1 66 A Ji 63 XCBUSD62 OO 4 72 Ji 81 i Ji 74 i Ji 75 i Ji 76 XCBUS 001 144 COMPANY XESS Corporation XSA Board Prototyping Header RELEASED
16. VREF3_3 X B 066 RUSO 74 XCBUS024 7 BUSO IS VREFO_3 76 xCBus0z6 X b BUS020 20 VREF4_1 78 xcRUSD7R A B 79 079 4 RUSO 22 VREF4_2 96 xcausnan 4 RUSO 23 B3 xcBUSOR3 4 BUS028 26 84 CBLSn84 TET VREF4_3 86 4 BUSO28 59 87 BUS040 40 3 xcausnai 7 RUSD4 42 5 195 5 1 43 96 yeausnan 4 BuS04 47 VREF2_2 59 BUS050 So VREFZ 3 T VREF5_2 yreuisiot 4 RUSO 51 102 xcBus102 4 Ben 54 XC2S TQFP144 VREF5_3 103 XCBuSin3 4 BUS056 56 72 xcBusu2 4 R7 5 113 xcBusns 4 CBUS088 88 CCLKO L4 2 BUSOG 18 VREF6_1 T6 XCBUSH6 4 Lion BLSA 15 GCLK2 vrere_2 XCBUSHZ Z XCR 39 120 xCBUS120 4 BUS044 44 DN 00 121 xCBus121 A XCRUSD4 46 0 122 XCRUSI22 4 XCBUS04 49 02 VREF63 423 XCBUISI23 4 3 3V XCR 57 09 124 gerus124 4 XC 6004 126 xCBUSI28 4 RBF 4 XC 82 129 xcBusi28 4 BAA AA KCB 67 06 130 XCBUS130 4 15038 38 151 xcBusiat 4 XCR ah 132 XCBUS132 4 g RBH 4 7K T 30 WRITE VREF7 1 H35 XCBUSI32 BUS068 A xcBUSO6R 68 Kir 134 xcBusi34 R8G 47 B XCBUSO 72 DONE 136 XCRUS136 4 eee 37 PROGRAM VREF7 2 138 XcRust38 1 SG ES CCLK VREF7 139 4 7 xcausi09 109 o 3 140 xcausi
17. Y 2501 B Ten Ten Road Apex NC 27502 Toll free 800 549 9377 A International 919 303 2883 Corporation FAX 919 303 2884 XSA Board V1 1 V1 2 User Manual How to install test and use your new XSA Board RELEASE DATE 5 6 2002 Copyright 2001 2002 by X Engineering Software Systems Corporation All XS prefix product designations are trademarks of XESS Corp All XC prefix product designations are trademarks of Xilinx All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America XSA BOARD V1 1 V1 2 USER MANUAL 1 Table of Contents XSA BOARD V1 1 V1 2 USER MANUAL 2 XSA BOARD V1 1 V1 2 USER MANUAL Preliminaries Here are some places to get help if you encounter problems If you can t get the XSA Board hardware to work send an e mail message describing our problem to help xess com or submit a problem report at http www xess com help html Our web site also has m answers to frequently asked questions m example designs application notes and tutorials for the XS Boards m a place to sign up for our email forum where you can post questions to other XS Board users If you can t get your Xilinx WebPACK software tools installed properly send an e mail message descr
18. a from the FPGA over the status lines The connections between the FPGA and the parallel port are shown below 256 KByte Flash RAM RESET CE OE WE AO Al A2 A3 4 5 6 A7 A8 L L LL E sssi h s s l QD_I MR F ts k Rol S XC9572XL CPLD Spartan II FPGA 5V A so am 52 4 53 56 PE 54 51 VV VV 50 9pp CNCOST aaaa The FPGA sends data back to the PC by driving logic levels onto pins 40 29 and 28 which pass through the CPLD and onto the parallel port status lines S3 S4 and S5 respectively Conversely the PC sends data to the FPGA on parallel port data lines DO D7 and the data passes through the CPLD and ends up on FPGA pins 50 48 42 47 65 51 58 and 43 respectively The FPGA should never drive these pins unless it is accessing the Flash RAM otherwise the CPLD and or the FPGA could be damaged However the CPLD can sense when the FPGA lowers the chip enable to access the Flash RAM and it will release the data lines so the FPGA can drive the address output enab
19. ard is inserted into an Xstend Board XSA BOARD V1 1 V1 2 USER MANUAL 31 FPGA CPLD XSA Function Proto Pin XSTendFuncions 221 A 54 2 18 12 o O oo nr SS JSDRAMAG 6 SDBRAMA2 U 10 SDRAMAS 4 VGA REDO Me 1 jJVGAGREN 83 Xchecker RT VGA BLUEO 33 34 96 37 Pushbuton RESET 62 FLASH AS 50 2 0 _ 63 2 55 51 5 _ 64 54 56 RLED SS 0 19 SPARTAN WRITE 7 46 PPSZDATA DIPSW8 15 SPARTANCS 68 15 SPARTAN TDE 15 46 1 30 JXcheckerRD 16 SPARTAN CCLK 73 Xcnecker CCLK 18 SPARTANDOUTBSY 45 39 2 FLASH DODIND0LED SI 1 1 0 JXcheckerDIN 40 1 FLASH AO PARPORT S3 57 9 RLED S 4r 11 6 JRAMCE 427 57 j FLASH ATO PARPORT D2 58 5 43 12 FLASH OE PARPORTD7 61 17 45 4 FLASH DILEDDP 4 R
20. atile storage for data and configuration bitstreams SDRAM A 16 MByte SDRAM provides volatile storage for data accessible by the FPGA LED A seven segment LED allows visible feedback as the XSA Board operates DIP switch A four position DIP switch passes settings to the XSA Board or controls the upper address bits of the Flash device Pushbutton A single pushbutton sends momentary contact information to the FPGA Parallel Port This is the main interface for passing configuration bitstreams and data to and from the XSA Board PS 2 Port A keyboard or mouse can interface to the XSA Board through this port VGA Port The XSA Board can send signals to display graphics on a VGA monitor through this port Prototyping Header Many of the FPGA I O pins are connected to the 84 pins on the bottom of the XSA Board that are meant to mate with solderless breadboards XSA BOARD V1 1 V1 2 USER MANUAL 20 Parallel Port PPD0 _ PPD1 _ XC9572XL 25100 D15 D0 PPD2 07 00 BAO A12 0 PPD3 DQML PPD5 PPD6 9 PPD7 17 PPC3 16 PPC2 14 11 PPS7 12 PPS5 13 PPS4 15 PPS3 BSY DOUT DONE TCK RED1 REDO us REEN1 GREEN m ewcw oneme TDO BLUE1 BLUEO AVSYNC d VGA Connector 10 PPS6 4 e Figure 3 XSA Board programmer s model Programmable log
21. der pin on the board This makes it easier to find a given FPGA pin when you want to connect it to an external system While most of the FPGA pins are already used to support functions of the XSA Board they can also be used to interface to external systems through the prototyping header The FPGA pins can be grouped into the various categories shown below Pins denoted with are useable as general purpose pins denoted with can be used as general purpose I O only if the CPLD interface is reprogrammed as described below pins with no marking cannot be used as general purpose at all XSA BOARD V1 1 V1 2 USER MANUAL 29 Configuration Pins 30 31 37 38 39 44 46 49 57 60 62 67 68 69 72 106 109 111 These pins are used to load the Spartanll FPGA with a configuration bitstream Some of these pins are dedicated to the configuration process and cannot be used as general purpose 37 69 72 106 109 111 The rest can be used as general purpose I O after the FPGA is configured If external logic is connected to these pins you may have to disable it during the configuration process The DONE pin 72 can be used for this purpose since it goes to a logic high only after the configuration process is completed Flash RAM Pins 27 28 29 39 40 41 42 43 44 46 47 48 49 50 5177 54 56 57 58 59 60 62 63 64 65 66 67 74 75 76 These pins are used by the FPGA
22. design into your XSA Board using the GXSLOAD utility as follows You start GXSLOAD by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the window shown below Then select the type of XS Board you are using and the parallel port to which it is connected as follows X gxsload 5 100 Load Port LPT FPGA CPLD Flash EEPROM High Address Low Address Upload Format HEX After setting the board type and parallel port you can download BIT or SVF files to the Spartan Il FPGA or XC9572XL CPLD on your XSA Board simply by dragging them to the FPGA CPLD area of the GXSLOAD window as shown below XSA BOARD V1 1 V1 2 USER MANUAL 13 X gxsload Once you release the left mouse button and drop the file the highlighted file name appears in the FPGA CPLD area and the Load button in the GXSLOAD window is enabled Clicking on the Load button will begin sending the highlighted file to the XSA Board through the parallel port connection BIT files contain configuration bitstreams that are loaded into the FPGA while SVF files will go to the CPLD GXSLOAD will reject any non downloadable files ones with a suffix other than BIT or SVF During the downloading process GXSLOAD will display the name of the file and the progress of the current download X gxsload You can drag amp drop multi
23. e Figure 2 Arrangement of components on the XSA Board Connecting a PC to Your XSA Board The 6 DB25 male to male cable included with your XSA Board connects it to a PC One end of the cable attaches to the parallel port on the PC and the other connects to the female DB 25 connector J8 at the top of the XSA Board as shown in Connecting a VGA Monitor to Your XSA Board You can display images on a VGA monitor by connecting it to the 15 pin J3 connector at the bottom of your XSA Board see Figure 1 You will have to download a VGA driver circuit to your XSA Board to actually display an image You can find an example VGA driver at http www xess com ho03000 html XSA BOARD V1 1 V1 2 USER MANUAL 8 Connecting a Mouse or Keyboard to Your XSA Board You can accept inputs from a keyboard or mouse by connecting it to the J4 PS 2 connector at the bottom of your XSA Board see Figure 1 You can find an example keyboard driver at http www xess com ho03000 html Inserting the XSA Board into an XStend Board If you purchased the optional Xstend Board then the XSA Board is inserted as shown below The XSA Board is inserted into the right most columns of the socket strips the same ones used by the XS40 Board Do not orient the LED display on the XSA Board as shown on the Xstend Board Refer to the Xstend Board Manual for more details on the Xstend Board Setting the Jumpers on Your XSA Board The default jumper settings sho
24. from an address range in the Flash type the upper and lower bounds of the range into the High Address and Low Address fields below the Flash EEPROM area and select the format in which you would like to store the data using the Upload Format pulldown list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The CPLD on the XSA Board is reprogrammed to create an interface between the Flash device and the PC parallel port 2 The Flash data between the high and low addresses inclusive is uploaded through the parallel port 3 The uploaded data is stored in a file named FLSHUPLD with an extension that reflects the file format X gxsload OE x Board Type 54 100 Load Port FPGA CPLD Flash EEPROM l E 00 High Address 0x3 FFF Low Address o Upload Format EXO 24 The uploaded data can stored in the following formats MCS Intel hexadecimal file format This is the same format generated by the promgen utility with the p mcs option HEX Identical to MCS format EXO 16 Motorola S record format with 16 bit addresses suitable for 64 KByte uploads only EXO 24 Motorola S record format with 24 bit addresses This is the same format generated by the promgen utility with the p exo option EXO 32 Motorola S record format with 32 bit addresses XESS 16 XESS hexadecimal format with 16 bit addresses
25. he Flash device by dragging it into the Flash EEPROM area and clicking on the Load button This activates the following sequence of steps 1 The entire Flash device is erased 2 The CPLD on the XSA Board is reprogrammed to create an interface between the Flash device and the PC parallel port This interface is stored in the fintf100 svf bitstream file located within the XSTOOLS XSA folder 3 The contents of the EXO or MCS file are downloaded into the Flash through the parallel port 4 The CPLD is reprogrammed to create a circuit that configures the FPGA with the contents of the Flash when power is applied to the XSA Board This configuration loader is stored in the fcnfg svf bitstream file located within the XSTOOLS XSA folder Multiple files can be stored in the Flash device just by dragging them into the Flash EEPROM area highlighting the files to be downloaded and clicking the Load button Note that anything previously stored in the Flash will be erased by each new download This is useful if you need to store information in the Flash in addition to the FPGA bitstream Files are selected and de selected for downloading just by clicking on their names in the Flash EEPROM area The address ranges of the data in each file should not overlap or this will corrupt the data stored in the Flash device XSA BOARD V1 1 V1 2 USER MANUAL 16 You can also examine the contents of the Flash device by uploading it to the PC To upload data
26. his activates the following sequence of steps 1 The Spartan II FPGA on XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit bitstream file located within the XSTOOLS XSA folder The CPLD must have previously been loaded with the dwnldpar svf file found in the same folder 2 The contents of the EXO MCS HEX or XES files are downloaded into the SDRAM through the parallel port The data in the files will overwrite each other if their address ranges overlap 3 If any file is highlighted in the FPGA CPLD area then this bitstream is loaded into the FPGA or CPLD on the XSA Board Otherwise the FPGA remains configured as an interface to the SDRAM You can also examine the contents of the SDRAM device by uploading it to the PC To upload data from an address range in the SDRAM type the upper and lower bounds of the range into the High Address and Low Address fields below the RAM area and select the format in which you would like to store the data using the Upload Format pulldown list Then click on the file icon and drag amp drop it into any folder This activates the following sequence of steps 1 The FPGA on the XSA Board is reprogrammed to create an interface between the RAM device and the PC parallel port This interface is stored in the ram100 bit bitstream file located within the XSTOOLS XSA folder 2 The SDRAM data be
27. ibing your problem to hotline xilinx com or check their web site at http www xilinx com support support htm If you need help using the WebPACK software to create designs for your XSA Board then check out this kutorial Take notice The XSA Board requires an external power supply to operate It does not draw power through the downloading cable from the PC parallel port If you are connecting a 9VDC power supply to your XSA Board please make sure the center terminal of the plug is positive and the outer sleeve is negative Do not power your XSA Board with a battery This will not provide enough current to insure reliable operation of the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 4 Packing List Here is what you should have received in your package m anXSA Board m a6 cable with a 25 pin male connector on each end m anXSTOOLS CDROM with software utilities and documentation for using the XSA Board XSA BOARD V1 1 V1 2 USER MANUAL 5 Installation Installing the XSTOOLS Utilities and Documentation Xilinx currently provides the WebPACK tools for programming their CPLDs and Spartan ll FPGAs Any recent version of WebPACK software should generate bitstream configuration files that are compatible with your XSA Board You can download the most current version of the WebPACK tools from http Avww xilinx com xInx xil_ prodcat landingpage jsp title ISE WebPacK Follow the directions Xilinx provides for installing thei
28. ic Spartan II FPGA and XC9572XL CPLD The XSA Board contains two programmable logic chips m A50 Kgate XC2S50 or 100 Kgate Xilinx 25100 FPGA in a 144 pin package The FPGA is the main repository of programmable logic on the XSA Board m A Xilinx KC9572XL CPLD that is used to manage the configuration of the FPGA via the parallel port The CPLD also controls the programming of the Flash RAM on the XSA Board 100 MHz Programmable Oscillator A Dallas 051075 programmable oscillator provides a clock signal to both the FPGA and the CPLD The DS1075 has a maximum frequency of 100 MHz that is divided to provide frequencies of 100 MHz 50 MHz 33 3 MHz 25 MHz 48 7 KHz The clock signal is connected to a dedicated clock input of the CPLD The CPLD passes the clock signal on to the FPGA This allows the CPLD to control the clock source for the FPGA To set the divisor value the DS1075 must be placed in its programming mode This is done by pulling the clock output to 5V on power up with a shunt across pins 1 and 2 of jumper J6 Then programming commands to set the divisor can be sent to the DS1075 XSA BOARD V1 1 V1 2 USER MANUAL 21 control pin C0 of the parallel port The divisor is stored in EEPROM in the DS1075 so it will be restored whenever power is applied to the XSA Board The shunt on jumper J6 must be across pins 2 and 3 to make the oscillator output a clock signal upon power up The clock signal
29. le and write enable pins of the Flash RAM without contention The CPLD also drives the decimal point of the LED display to indicate when the FPGA is configured with a valid bitstream Unless it is accessing the Flash RAM the FPGA should never drive pin 44 to a low logic level or it may damage itself or the CPLD But when the XSA BOARD V1 1 V1 2 USER MANUAL 28 FPGA lowers the Flash RAM chip enable the CPLD will stop driving the LED decimal point to allow the FPGA access to data pin D1 of the Flash RAM terface application note Prototyping Header The pins of the FPGA are accessible through the 84 pin prototyping header on the underside of the XSA Board Pin 1 of the header denoted by a square pad is located in the middle of the left hand edge of the board and the remaining 83 pins are arranged counter clockwise around the periphery The physical dimensions of the prototyping header and the pin arrangement are shown below For more details on how the CPLD manages the interface between the parallel port and the Spartanll FPGA both before and after device configuration see the XSA Parallel Port Interface 1 75 e o 64 4 0 1 Qo ERS N _ 22 A subset of the 144 FPGA pins connects to the prototyping header The number of the FPGA pin connected to a given header pin is printed next to the hea
30. ple files into the FPGA CPLD area Clicking your mouse on a filename will highlight the name and select it for downloading Only one file at a time can be selected for downloading XSA BOARD V1 1 V1 2 USER MANUAL 14 X gxsload KS Los imn s ram 00 bit dwnidpar sv Double clicking the highlighted file will deselect it so no file will be downloaded Doing this disables the Load button XSA BOARD V1 1 V1 2 USER MANUAL X gxsload 5 100 21 HEX 41 15 Storing Non Volatile Designs in Your XSA Board The Spartan ll FPGA on the XSA Board stores its configuration in an on chip SRAM which is erased whenever power is removed Once your design is finished you may want to store the bitstream in the 256 KByte Flash device on the XSA Board which configures the FPGA for operation as soon as power is applied Before downloading to the Flash the FPGA BIT file must be converted into a EXO or MCS format using one of the following commands promgen u 0 file bit p exo s 256 promgen u 0 file bit p mcs s 256 In the commands shown above the bitstream in the file bit file is transformed into an EXO or MCS file format starting at address zero and proceeding upward until an upper limit of 256 KBytes is reached Before attempting to program the Flash you must place all four DIP switches into the OFF position After the EXO or MCS file is generated it is loaded into t
31. r software XESS Corp provides the additional XSTOOLS utilities for interfacing a PC to your XSA Board Run the SETUP EXE program on the XSTOOLS CDROM to install these utilities Applying Power to Your XSA Board You can use your XSA Board in three ways distinguished by the method you use to apply power to the board Using a 9VDC wall mount power supply You can use your XSA Board all by itself to experiment with logic designs Just place the XSA Board on a non conducting surface as shown in Figure 1 Then apply power to jack J5 of the XSA Board from a 9V DC wall mount power supply with a 2 1 mm female center positive plug See Figure 2 the location of jack J5 on your XSA Board The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Be careful The voltage regulators on the XSA Board will become hot Attach a heat sink to them if necessary Powering Through the PS 2 Connector You can use your XSA Board with a laptop PC by connecting a PS 2 male to male cable from the PS 2 port of the laptop to the J4 connector You must also have a shunt across pins 1 and 2 of jumper J7 The on board voltage regulation circuitry will create the voltages required by the rest of the XSA Board circuitry Many PS 2 ports cannot supply more than 0 5A so large fast FPGA designs may not work when using this power source Solderless Protoboard Installation The two rows of pins from your X
32. serial data stream that is synchronized with the falling edges on the clock signal 5V A Spartan ll k PS 2 FPGA data Connector J4 o Pushbutton 12 SW2 XSA BOARD V1 1 V1 2 USER MANUAL 25 The XSA Board has a single pushbutton that shares the FPGA pin connected to the data line of the PS 2 port The pushbutton applies a low level to the FPGA pin when pressed and a resistor pulls the pin to a high level when the pushbutton is not pressed VGA Monitor Interface The FPGA can generate a video signal for display on a VGA monitor When the FPGA is generating VGA signals the FPGA outputs two bits of red green and blue color information to a simple resistor ladder DAC The outputs of the DAC are sent to the RGB inputs of a VGA monitor along with the horizontal and vertical sync pulses HSYNC NSYNC from the FPGA gt vsync REDO AAA RED1 d VGA Spartan Il NN gt re FPGA GREENO MN Connector GREEN 4 J3 BLUEO AAA BLUE1 AN gt blue Parallel Port Interface The parallel port is the main interface for communicating with the XSA Board Control line CO goes directly to the DS1075 oscillator and is used for setting the divisor as described previously and status line S6 connects directly to the FPGA for use as a communication line from the FPGA back to the PC The CPLD handles the fifteen remaining active lines of the interface to the parallel port Eleven of
33. test you will be shown a checklist of common causes for failure If none of these causes applies to your situation then test the XSA Board using another PC In our experience 99 9 of all problems are due to the parallel port If you cannot get your board to pass the test even after taking these steps then contact XESS Corp for further assistance As a result of testing the XSA Board the CPLD is programmed with the standard parallel port interface found in the dwnldpar svf bitstream file located within the XSTOOLS XSA folder This is the standard interface that should be loaded into the CPLD when you want to use it with the GXSLOAD utility Setting the XSA Board Clock Oscillator Frequency The XSA Board has a 100 MHz programmable oscillator a Dallas Semiconductor DS1075Z 100 The 100 MHz master frequency can be divided by factors of 1 2 up to 2052 to get clock frequencies of 100 MHz 50 MHz down to 48 7 KHz respectively The divided frequency is sent to the rest of the XSA Board circuitry as a clock signal XSA BOARD V1 1 V1 2 USER MANUAL 11 The divisor is stored in non volatile memory in the oscillator chip so it will resume operation at its programmed frequency whenever power is applied to the XSA Board You can store a particular divisor into the oscillator chip by using the GUI based GXSSETCLK as follows You start GXSSETCLK by clicking on the icon placed on the desktop during the XSTOOLS installation This brings up the
34. the active lines of the parallel port connect to general purpose pins on the CPLD Three of the parallel port control lines C1 C3 connect to the JTAG pins through which the CPLD is programmed The C1 control line clocks configuration data presented on the C3 line into the CPLD while the C2 signal steers the actions of the CPLD programming state machine Meanwhile information from the CPLD returns to the PC through status line S7 The eight data lines 00 07 and the remaining three status lines S3 S5 connect to general purpose pins of the CPLD The CPLD can be programmed to act as an interface between the FPGA and the parallel port the dwnldpar svf file is an example of such an interface Schmitt trigger inverters are inserted into the D1 line so it can carry a clean clock edge for use by any state machine programmed into the CPLD The CPLD connects to the configuration pins of the Spartan Il FPGA so it can pass configuration bitstreams from the parallel port to the FPGA The actual configuration data is presented on the to the FPGA on the same 8 bit bus that connects the CPLD Flash seven segment XSA BOARD V1 1 V1 2 USER MANUAL 26 LED and FPGA The CPLD also drives the configuration pins CCLK PROGRAM CS and WR of the FPGA that control the loading of a bitstream The CPLD uses the MO input of the FPGA to select either the slave serial or master select configuration mode M1 and M2 are already hard wired to VCC and GND respec
35. tively The CPLD can monitor the status of the bitstream download through the INIT DONE and BSY DOUT pins of the FPGA The CPLD also has access to the FPGA JTAG pins TCK TMS TDI TDO The TMS TDI and pins share the connections with the BSY DOUT CS and pins With these connections the CPLD can be programmed with an interface that allows configuration of the Spartan Il FPGA through the Xilinx JTAG Programmer software utility Jumper J9 allows the connection of status pin S7 to the general purpose CPLD pin that also drives status pin S5 This is needed to implement the parallel port interface required by the JTAG Programmer software FLASH RAM EO XC9572XL Spartan ll FPGA Parallel Port D7 DO 2 PPDO 3 PPD1 _ So gt 4 PPD2 CCLK 5 PPD3 IPROGRAM 6 PPD4 NNIT 7 PPD5 MO 8 PPD6 A AN M1 9 PPD7 M2 17 PPC3 TDI ae ANN os 16 PPC2 TMS SUR 14 gt gt TOK 1 BSY DOUT 11 57 4 lt 1 TDO DONE 12 PPS5 4 9 TCK 13 54 4 TMS 15 PPS3 4 TDI OSC IDO oi 10 PPS6 4 After the Spartanll FPGA is configured with a bitstream and the DONE pin goes high the CPLD switches into a mode that connects the parallel port data and status pins to the XSA BOARD V1 1 V1 2 USER MANUAL 27 FPGA This lets you pass data to the FPGA over the parallel port data lines while receiving dat
36. tween the high and low addresses inclusive is uploaded through the parallel port XSA BOARD V1 1 V1 2 USER MANUAL 18 3 The uploaded data is stored in a file named RAMUPLD with an extension that reflects the file format X gxsload 5 100 LPT1 gt The 16 bit data words in the SDRAM are mapped into the eight bit data format of the HEX MCS EXO and XES files using a Big Endian style That is the 16 bit word at address N in the SDRAM is stored in the eight bit file with the upper eight bits at location 2N and the lower eight bits at location 2N 1 This byte ordering applies for both RAM uploads and downloads XSA BOARD V1 1 V1 2 USER MANUAL 19 Programmer s Models This section describes the various sections of the XSA Board and shows how the I O of the FPGA and CPLD are connected to the rest of the circuitry The schematics which follow are less detailed so as to simplify the descriptions Please refer to the complete schematics at the end of this document if you need more details XSA Board Organization The XSA Board contains the following components 2550 or XC2S100 Spartan Ill FPGA This is the main repository of programmable logic on the XSA Board XC9572XL CPLD This CPLD manages the interfaces between the PC parallel port and the rest of the XSA Board Osc A programmable oscillator generates the master clock for the XSA Board Flash A 256 KByte Flash device provides non vol
37. window shown below Board Type XS4 100 gt Port Exit Divisor External Clock Your next step is to select the parallel port that your XSA Board is connected to from the Port pulldown list Then select either XSA 50 or XSA 100 in the Board Type pulldown list Next you enter a divisor between 1 and 2052 into the Divisor text box and then click on the SET button Then follow the sequence of instructions given by XSSETCLK for moving shunts and removing and restoring power during the oscillator programming process At the completion of the process the new frequency will be programmed into the DS1075 An external clock signal can be substituted for the internal 100 MHz oscillator of the DS1075 Checking the External Clock checkbox will enable this feature in the programmable oscillator chip If this option is selected you are then responsible for providing the external clock to the XSA Board through pin 64 XSA BOARD V1 1 V1 2 USER MANUAL 12 Programming This section will show you how to download a logic designs into the FPGA and CPLD of your XSA Board and how to download and upload data to and from the SDRAM and Flash devices on the board Downloading Designs into the FPGA and CPLD of Your XSA Board During the development and testing phases you will usually connect the XSA Board to the parallel port of a PC and download your circuit each time you make changes to it You can download a FPGA
38. wn in Table 2 configure your XSA Board for use a logic design environment You will need to change the jumper settings only if you are m downloading FPGA bitstreams to your XSA Board using the Xilinx JTAG Programmer software reprogramming the clock frequency on your XSA Board see page 1 XSA BOARD V1 1 V1 2 USER MANUAL Jumper J2 J6 J7 J9 J10 m changing the power sources for the XSA supply voltages Setting On default Off 1 2 set 2 3 osc default 1 2 default 2 3 1 2 xi 2 3 xs default N A e Table 2 Jumper settings for XSA Boards Purpose A shunt should be installed if the 2 5V supply voltage is derived from the 3 3V supply The shunt should be removed if the 2 5V supply voltage is applied from an external source through pin 22 of the XSA Board The shunt should be installed on pins 1 and 2 set when setting the frequency of the programmable oscillator The shunt should be installed on pins 2 and 3 osc during normal operations when the programmable oscillator is generating a clock signal The shunt should be installed on pins 1 and 2 if the 3 3V supply voltage is derived from the 5V supply The shunt should be installed on pins 2 and 3 if the 3 3V supply voltage is derived from the 9VDC supply applied through jack J5 The shunt should be installed on pins 1 2 if the XSA Board is to be downloaded using the Xilinx JTAG Programmer software utility
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