MIP7965 64-bit Superscaler Microprocessor
Contents
1. Industrial Temp 40 C to 85 C Base Processor Type R Extended Temp 55 C to 110 C T Military Temp 55 C to 125 C Note 2 Maximum Pipeline Frequency 750 750MHz 668 668MHz M Military Temp 45 C to 115 C Screened Note 2 Package Type amp Size B1 26mm Sq 256 TBGA F17 1 120 Sq 208 Lead CQFP Note 2 8 4 F24 1 120 Sq Inverted 208 Lead COFP Note 2 2 Screened to the individual test methods of MIL STD 883 PLAINVIEW NEW YORK INTERNATIONAL NORTHEAST Toll Free 800 THE 1553 Tel 805 778 9229 Tel 603 888 3975 Fax 516 694 6715 Fax 805 778 1980 Fax 603 888 4585 SE AND MID ATLANTIC WEST COAST CENTRAL Tel 321 951 4164 Tel 949 362 2260 Tel 719 594 8017 NEROFLEX Fax 321 951 4254 Fax 949 362 2266 Fax 719 594 8468 A passion for performance www aeroflex com info ams aeroflex com Aeroflex Microelectronic Solutions reserves the right to change at N v any time without notice the specifications design function or form Gd O of its products described herein All parameters must be validated for each customer s application by engineering No liability is assumed Our passion for performance is defined by three as a result of use of this product No patent licenses are implied All attributes represented by these three icons trademarks are acknowledged Parent company Aeroflex Inc 2003 solution minded performance driven and customer focused SCD7965 Rev H 10 01 102. for the internal phase locked loop Must be connected to Vss through a filter circuit Note Not applicable for the F17 F24 QFPs which incorporates the filter components except for the 10uF capacitor See PLL Analog Power Filtering section herein Interrupt Interface PIN NAME TYPE DESCRIPTION INT 9 0 Input Interrupt Ten general processor interrupts bit wise ORed with bits 9 0 of the interrupt register NMI Input Non maskable interrupt Non maskable interrupt ORed with bit 15 of the interrupt register JTAG Interface PIN NAME TYPE DESCRIPTION JTDI DBDI Input JTAG EJTAG data in JTAG EJTAG serial data in JTCK DBCK Input JTAG EJTAG clock input JTAG EJTAG serial clock input JTDO DBDO Output JTAG EJTAG data out JTAG EJTAG serial data out JTMS DBMS Input JTAG EJTAG command JTAG EJTAG command signal signals that the incoming serial data is command data JTRST DBRST JTAG EJTAG reset JTAGSEL Input JTAG EJTAG select Selects JTAG when JTAGSEL 1 selects EJTAG when JTAGSEL 0 SCD7965 Rev H 10 01 10 5 Aeroflex Plainview Initialization Interface PIN NAME TYPE DESCRIPTION BigEndian Input Big Endian Little Endian Control Allows the system to change the processor addressing VccOK Input Vcc is OK When asserted this signal indicates to the MIP7965 that the VccInt power supply has been above the recommended value for more than 100 milliseconds and will remain stable The assertion of VccOK initiates the reading of the bo
3. vs mo ssas in vs gt 17 ssaa 69 veo 121 syapso 173 sya as sapi so Syscmas 132 Veio Osi sysapca Vss ist vs ass ssa SysAD15 ModeClock S Do Not Conneci vs io Do Nor Connect 156 vs 208 vs SCD7965 Rev H 10 01 10 17 Aeroflex Plainview 56 EH 96 56 SS 9 Vss Vss SAMPLE ORDERING INFORMATION PIPELINE FREO PART NUMBER SCREENING id Nes PACKAGE MIP7965 750B 11 Industrial Temperature Range 256 TBGA 40 C to 85 C Testing MIP7965 750F171 208 Lead COFP F17 MIP7965 668F241 208 Lead COFP F24 668 MIP7965 668B IR Extended Temperature Range ep 55 C to 110 C Testing 256 TBGA MIP7965 750B1R Note 2 MIP7965 750F17T Military Temperature Range 208 Lead CQFP F17 55 C to 125 C Testing MIP7965 668F24T Note 1 208 Lead COFP F24 MIP7965 750F17M Military Screened 208 Lead COFP F17 45 C to 115 C Testing MIP7965 668F24M Note 1 Note 2 208 Lead COFP F24 MIP7965 INT Note 4 Engineering Evaluation Board 208 Lead COFP F17 Notes 1 Contact Factory for availability 2 Contact factory for military temperature range products CQFP hermetic MCM package will be screened at 45 C to 115 C 3 Contact factory for higher speed product options 4 Interposer evaluation board with MIPS7965 668B 1 processor configured as 208 lead F17 Foot Print PART NUMBER BREAKDOWN MIP 7965 750 BI I MIPS Series cl Te Screening AP Custom Series
4. METER CONDITIONS COMM COMM MIL MIL Power mWatts Maximum with no FPU operation 5000 4500 5000 4500 Notes 1 Worst case supply voltage maximum VccInt with worst case temperature maximum TCASE 2 Dhrystone 2 1 instruction mix 3 I O supply power is application dependant but typically lt 20 of VccInt 4 IccInt active test limit set to 2 3 Amps during a stable program loop for measurement consistency 5 IccInt standby test limit set to 1 2 Amps at 1 30 V and TCASE 115 C SCD7965 Rev H 10 01 10 8 Aeroflex Plainview AC CHARACTERISTICS CAPACITIVE LOAD DERATION SYMBOL PARAMETER MINIMUM MAXIMUM UNITS CLOCK PARAMETERS BUS SPEED PARAMETER SYMBOL TEST CONDITIONS vm UNITS EE IONES ene res Il sim me mem 5 ar apa ra O apa a EERER REESEN ET IEEE ene O E o Je REES E E ee 1077 O EC a Notes 1 Operation of the MIP7965 is only guaranteed with the Phase Loop enabled SYSTEM INTERFACE PARAMETERS BUS SPEED PARAMETER TEST CONDITIONS LVTTL IVTTLYO UNITS linad ke LVTTL VcclO 3 3V mode 15 14 01 slowest gt e EES E ronne O AE Notes 1 In LVTTL mode timings are measured from 0 425 x VecIO of clock to 0 425 x VcclO of signal for 3 3V I O and from 0 48 x VcclO of clock to 0 48 x VcclO of signal for 2 5V I O 2 Capacitive load for all LVTTL maximum output timings is 50 pF Minimum output timings are for theoretical no load conditions 3 Data Output timing ap
5. Standard Products MIP 7965 64 Bit Superscaler Microprocessor October 01 2010 www aeroflex com Avionics AEROF LEX A passion for performance FEATURES a Upscreened PMC Sierra RM7965 a Military and Industrial Grades Available a CPU core with MIPS647M compatible Instruction Set Architecture that features 668 750 MHz Dual issue superscalar 7 stage pipeline 16 KB 4 way set associative L1 Instruction cache 16 KB 4 way set associative L1 Data cache 256 KB 4 way set associative L2 cache with industry best 5 cycle access latency Error Checking and Correcting ECC on L2 cache Fast Packet Cache to assist processing of packet data 8K entry branch prediction table Fully associative 64 entry TLB with dual pages High performance Floating Point unit IEEE 754 Fixed point DSP instructions such as Multiply Add Multiply Subtract and 3 Operand Multiply Q High performance system interface O oO O 0 Multiple outstanding reads with out of order return 1600 MB s peak throughput Multiplexed address data bus SysAD supports 3 3V I logic Processor clock multipliers 2 3 3 5 4 4 5 5 5 5 6 6 5 7 7 5 8 8 5 9 10 11 12 13 14 15 16 17 Integrated on chip EJTAG controller 64 entry dynamic Trace Buffer for use in real time trace and debug Two 32 bit virtually addressed Watch registers Integrated performance counters Contains 2 independent 32 bit counters Counts over 30 processor events including mispredic
6. e output should be shorted at one time Duration of the short should not exceed more than 30 seconds RECOMMENDED OPERATING CONDITIONS CPU TEMP Commercial E 40 C to 85 C OV 1 3 V 50 mV 3 3 V 150 mV 1 3 V 50mV 3 3 V 150 mV 1 E 668 1 3 V 50 mV 3 3 V 150 mV 1 3 V 50mV 3 3 V 150 mV MHz Commercial 750 55 C to 1 3 V 50 mV 3 3 V 150 mV 1 3 V 50mV 3 3 V 150 mV R MHz 110 C 668 1 3 V 50 mV 3 3 V 150 mV 1 3 V 50mV 3 3 V 150 mV MHz Extended 668 55 C to OV 1 3 V 50 mV 3 3 V 150 mV 1 3 V 50mV 3 3 V 150 mV Screened MHz 110 C Class H Notes 1 VecIO should not exceed VccInt by greater than 2 5 V during the power up sequence 2 Applying a logic high state to any I O pin before VccInt becomes stable is not recommended 3 As specified in IEEE 1149 1 JTAG the JTMS pin must be held high during reset to avoid entering JTAG test mode Refer to the RM79xx User Manual 4 VccP must be connected to VecInt through a passive filter circuit See RM79xx User Manual for recommended circuit Not applicable for the F17 F24 QFP and Interposer evaluation board devices which incorporates the filter components except for the 10uF capacitor SCD7965 Rev H 10 01 10 7 Aeroflex Plainview DC ELECTRICAL CHARACTERISTICS VeclO 3 15V to 3 45V PARAMETER MINIMUM MAXIMUM CONDITIONS VcclO 0 3V 15uA a 0 15uA VIN VcclO IIOUTI 2mA POWER CONSUMPTION CPU SPEED 750MHz 668MHz 750MHz 668MHz PARA
7. eady Signals that an external agent can now accept a processor write request ValidIn Input Valid Input Signals that an external agent is now driving a valid address or data on the bus and a valid command or data identifier on the SysCmd bus ValidOut Output Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus Output Processor Request When asserted this signal requests that control of the system interface be returned to the processor Input Processor Acknowledge When asserted in response to PRgst this signal indicates to the processor that it has been granted control of the system interface a minimum of two cycles prior to the data itself being presented Note that this signal works as a toggle i e for each cycle that it is held asserted the order of return is reversed By default anytime the processor issues a second read it is assumed that the reads will be returned in RspSwap Input Response Swap RspSwap is used by the external agent to signal the processor when it is about to return a memory reference out of order 1 e of two outstanding memory references the data for the second reference is being returned ahead of the data for the first reference In order that the processor will have time to switch the address to the tertiary cache this signal must be asserted order 1 e no action is reguired if the reads are indeed return
8. ed in order RdType Output Read Type During the address cycle of a read request RdType indicates whether the read request is an instruction read or a data read SysAD 63 0 Input Output System address data bus A 64 bit address and data bus for communication between the processor and an external agent SysADC 7 0 Input Output System address data check bus An 8 bit bus containing parity check bits for the SysAD bus during data cycles SysCmd 8 0 Input Output System command data identifier bus A 9 bit bus for command and data identifier transmission between the processor and an external agent SysCmdP Input Output System Command Data Identifier Bus Parity For the RM79xx unused on input and zero on output SCD7965 Rev H 10 01 10 4 Aeroflex Plainview Clock Control Interface PIN NAME TYPE DESCRIPTION SysClock Input System clock Master clock input used as the system interface reference clock All output timings are relative to this input clock Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization Power Supply PIN NAME TYPE DESCRIPTION VccP Input Vcc for PLL Quiet VccInt for the internal phase locked loop Must be connected to VccInt through a filter circuit Note Not applicable for the F17 F24 QFPs which incorporates the filter components except for the 10uF capacitor See PLL Analog Power Filtering section herein VssP Input Vss for PLL Quiet Vss
9. erface to a variety of system controllers providing connectivity to a wide range of networking peripherals All products also contain vectored and prioritized interrupt controllers for versatile interrupt configurations On chip EJTAG debug modules ensure smooth and easy debugging for both hardware and software by allowing single step and state examination The inclusion of a pipeline rate branch instruction trace buffer facilitates debugging under operating conditions The MIP7965 is available in a 256 TBGA and 208 lead CQFP package The 256 TBGA package is pin compatible with previous RM7065x devices The RM7965 products offer a cost advantage by eliminating the L3 cache controller functionality available with the RM7900 For additional Detail Information regarding the operation of the PMC Sierra see the latest PMC Sierra datasheet for the RM79xx Family Microprocessors Data Sheet doc PMC 2030581 Issue No 11 September 2006 SCD7965 Rev H 10 01 10 3 Aeroflex Plainview PIN DESCRIPTIONS The following is a list of control data clock interrupt and miscellaneous pins of MIP7965 System Interface PIN NAME TYPE DESCRIPTION ExtRgst Input External request Signals that the external agent is submitting an external request Release Output Release interface Signals that the processor is releasing the system interface to slave state RdRdy Input Read Ready Signals that an external agent can now accept a processor read WrRdy Input Write R
10. ined by the spherical crowns of the solder balls 6 Al dimensions are in millimeters 7 Dimensioning and tolerancing per ASME Y14 5M 1994 8 After surface mount assembly solder ball will have 0 15 mm TYP collapse in A dimension 127TYP 9 Substrate base material is copper 10 Package top surface color shall be black 11 Cavity depth maximum is 0 50 mm SCD7965 Rev H 10 01 10 13 Aeroflex Plainview MIP7965 256 TBGA ALPHANUMERICAL PINOUT banana c2 vs Pe Oi 1s syans E fofo aos mo oz BEER e paca sa aiser o Deneme seg E EET Caa swana ole Elsa ET srana VecInt alo vos or DoNotConnect F19 Aw veto cis Velo o pep re E CR else elen Tass E als os vem m sans Lol on saves oo veo ns sana ni sab SCD7965 Rev H 10 01 10 14 Aeroflex Plainview SysAD51 SysAD19 SysAD38 SysAD6 EM EEN EEH KESTA vs ICE F18 aa Veetnt a EH 19 120 SIN MIP7965 256 TBGA ALPHANUMERICAL PINOUT CON T FUNCTION FUNCTION FUNCTION SysAD15 INT3 SysCmd5 TMS SysCmd7 SysCmd1 SCD7965 Rev H 10 01 10 15 Aeroflex Plainview MIP7965 F17 COFP 208 LEADS PACKAGE OUTLINE y 1 131 28 727 SQ 1 109 28 169 SG j 53 104 52 105 o gt Lid GT 010R REF oa 015 381 y 10 010R REF NE 229 KK 130 3 302 1 009 25 63 K MAX 9998 25 37 0 5 51 Space
11. material SCD7965 Rev H 10 01 10 11 Aeroflex Plainview PLL ANALOG POWER FILTERING The MIP7965 includes extra PLL Analog Power Filtering circuitry designed to provide low noise temperature stable filtering for the VccP and VssP signals The included circuitry consists of several passive components located at the closest possible point to the MIP7965 die and is configured as shown below RM7965 Die MIP7965 INCLUDING PLL FILTER CIRCUIT Additional board level PPL filtering is also reguired The recommended configuration is shown in below Veclnt VecP 10 HF Vssint 65 VssP RECOMMENDED BOARD LEVEL PLL FILTER CIRCUIT FOR THE MIP7965 SCD7965 Rev H 10 01 10 12 Aeroflex Plainview MIP7965 256 TBGA PACKAGE OUTLINE D 20 Ja 36 14 42 10 8 6 4 2 19 17 15 13 119 5 3 00000000000000000000 0000000000000 0000000000000 o o scIzrcomo gt lt lt JUZEZXITNTO0 00000000 00000000 00000000000000000000 pap EI a bo 00 00 Y 0000 4 00000 ch WE TOP VIEW o la 24 13 gt a x SIDE VIEW 9120 3009 cl A el b DETAIL X SEATING PLANE ZA DETAIL Y Notes 1 Package Dimensions conform to JEDEC Registration MO 149 BG 2X 2 e represents the basic solder ball grid pitch 3 M represents the maximum solder ball matrix size 4 Dimension b is measured at the maximum solder ball diameter parallel to the primary datum c 5 The Primary datum c and the seating plane are def
12. ot time mode control serial stream ColdReset Input Cold Reset This signal must be asserted for a power on reset or a cold reset ColdReset must be de asserted synchronously with SysClock Reset Input Reset This signal must be asserted for any reset seguence It may be asserted synchronously or asynchronously for a cold reset or synchronously to initiate a warm reset Reset must be de asserted synchronously with SysClock ModeClock Output Boot Mode Clock Serial boot mode data clock output at the system clock freguency divided by two hundred and fifty six Modein Input Boot Mode Data In Serial boot mode data input SCD7965 Rev H 10 01 10 6 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS SYMBOL RATING RANGE UNITS Terminal Voltage with respect to Vss 0 52 to 3 9 Ea Operating Temperature I Commercial 40 to 85 R Commercial 55 to 110 Class H Extended Screened 55 to 110 Notes 1 Stresses above those listed under AbsoluteMaximums Rating may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2 VIN minimum 2 0V for pulse width less than 15nS VIN maximum should not exceed 3 95 Volts 3 When VIN lt OV or VIN gt VcclO 4 No more than on
13. plies to all signal pins whether tristate I O or output only 4 Setup and Hold parameters apply to all signal pins whether tristate I O or input only 5 Only mode 15 14 10 is tested and guaranteed SCD7965 Rev H 10 01 10 9 Aeroflex Plainview TIMING DIAGRAMS CLOCK TIMING SysClock A JAJAA AH Luet tow trise tra l itterin SYSTEM INTERFACE TIMING SysAD SysCmd ValidIn ValidOut etc INPUT TIMING SysClock Data OUTPUT TIMING SysClock Data SCD7965 Rev H 10 01 10 10 Aeroflex Plainview THERMAL INFORMATION This product is designed to operate over a wide temperature range when used with a heat sink 23 Ambient Device Compact Model 256 TBGA Osa Bic C W 0 43 Heat Sink j i ll ia BJA C W 15 85 Case Be em Device Compact Model Junction OB Board Device Compact Model 208 Lead COFP F17 and F24 S SES Der Device Compact Case Operating power is dissipated in any package watts offered at worst case power supply Power at 750 MHz VecInt 1 3 V Vcel0 3 3 V Power at 668 MHz VccInt 1 3 V VcclO 3 3 V Notes 1 Short term is understood as the definition stated in Telcordia Generic Reguirements GR 63 Core 2 BIC the junction to case thermal resistance 0JB the junction to board thermal resistance are obtained from Package vendor 3 OSA is the thermal resistance of the heat sink to ambient OCS is the thermal resistance of the heat sink attached
14. s at 0197 t 51 Spaces at 50 N 090 2 286 REF 010 253 007 178 050 1 27 030 769 Detail A TAN 0 156 157 Pin 1 Chamfer 208 055 1 397 115 2 921 Units Inches Millimeters EF ja 960 24 384 Sa R MAX REF Detail A a 1 331 33 807 a 055 1 397 1 269 32 233 045 1 143 oo o o Note Pin rotation is opposite of PMC Sierra PQUAD due to cavity up construction MIP7965 F24 Inverted OFP 208 LEADS PACKAGE OUTLINE 1 131 28 727 SQ F 1 109 28 169 SG i 10 5 156 157 104 2 la Y Se 055 1 397 q 012R REF REF oo 1 009 25 63 012R REF mmm 9998 25 37 y A 51 Spaces at 0197 055 1 397 MAX 51 Spaces at 50 vo 045 1 143 0 5 Gem Fo Ni gt Aller 253 090 2 286 REF 007 178 055 1 397 208 EES 035 889 A Pin 1 Chamfer 52 Detail A 139 3 531 Detail BE MAX EES Units Inches Millimeters y TTT IR ET ES 960 24 384 REF N 1 331 33 807 015 381 1 291 Ges 009 229 Note Pin rotation is Identical to PMC Sierra POUAD due to cavity down construction Aeroflex Plainview 005 127 008 SCD7965 Rev H 10 01 10 16 MIP7965 208 LEAD COFP PINOUTS F17 8 F24 6 Sadi 58 Modein 110 veok 162 vs Ce ssas 60 Way 12 Veio Lal SysAb60 o ssas er vaia uns vs ies saba oi veo 66 SysClock is sywabi7 170 sysape oe ssa e
15. ted branches Enables full characterization and analysis of application software a MIP7965 is available in a 256 TBGA package 27x27 mm MIP7965 256 TBGA is pin compatible with RM7065C and RM7065A TBGA products MIP7965 208 lead CQFP cavity up package F17 is pin compatible with the ACT7000ASC MIP7965 208 lead COFP inverted footprint F24 is pin compatible and with the same pin rotation as the commercial PMC Sierra RM5261A NOTE MIPS64 and Fast Packet Cache are Trademarks of PMC Sierra SCD7965 Rev H On Chip Debug 64 bit Integer Unit 64 bit Floating Point Unit Dual Issue Superscalar Branch Trace Buffer Double Single IEEE 754 Integer Multiplier Instruction Dispatch 8K Entry Branch History Table Instruction Cache Memory Manager Data Cache 16 KB 4 way k 16 KB 4 way Line Lockable 64 Entry Dual Page Line Lockable Secondary Cache Interface Unit System Control 256 KB 4 way Line Lockable SysAD Interrupt EJTAG JTAG PLL 8 Clock System Interface Controller EEG BLOCK DIAGRAM SCD7965 Rev H 10 01 10 2 Aeroflex Plainview INTRODUCTION The MIP7965 comprise a new family of high performance 64 bit microprocessors This product is optimized for performance with features including a seven stage dual issue pipeline tightly coupled L1 and L2 caches and sophisticated branch prediction for maintaining pipeline efficiency A 200 MHz 64 bit multiplexed system address and data bus SysAD enables a high bandwidth I O int
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