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1. 0x01 Toggle P1 0 Texas Instruments Inc CCRO 50000 Add Offset to CCRO September 2003 interrupt TIMERAO VECTOR void TimerA void Built with IAR Embedded Workbench Version 1 26B December 2003 Updated for IAR Embedded Workbench Version 2 21B J RRR RK KKK KKK IK KKK KH HK KI KKK KKK KKK KKK IK KK KKK KKK IK KKK KK KKK KKK KK KKK KKK CPE EE 421 521 Microcomputers Serial Communication 10 Alex Milenkovich Serial I O Interface Functional Units ne l a r A Hardware and software of Transmission path eus 3 Twisted pair RE Coaxial cable ig Fiber optics Infrared beam Serial stars L Ultrasonic beam Sty Ta Plug and sdcket Translates data between the internal computer form and the form in which it is transmitted over the data link CPE EE 421 521 Microcomputers Asynchronous Serial gt Asynchronous Computer Fai i En System software L a a s oo ee Device driver Software a n eo EE Seria interface dl IL Line drivers Le Em Translates the TTL level signals processed by the ACIA into a form suitable for the transmission path Interface Transmitted and received data are not synchronized over any extended period No synchronization between receiver and transmitter clocks gt Serial Usually character oriented Z Data stream divided into individual bits at the
2. Q O GND vcc O O CCIO CAOUT 6 _ CCI1B O Q Timer AS TACLK ACLK SMCLK Timer_A3 Divider 15 0 CLK 1 2 4 8 16 bit Timer EE ala Clear RC S Set_TAIFG POR CLR COV Capture Mode Capture Mode MSP430x1xx Block Diagram Timer Clock Timer Block TASSELX Dx 16 bit Timer Divider TAR 15 x L 112 418 w Ea Clear Count Mode Equo Set TAIFG CMx Capture Mode Output EQUO Unit2 OUT2 Signal Page 11 3 a Manual OUTMODx CPE EE 421 521 Microcomputers Capture and Compare Registers gt What is a capture A record of the timer count when a specific event occurs The capture modules of the timers are tied to external pins of the MSP When the control registers of timer A and the specific capture compare module have been properly configured then the capture will record the count in the timer when the pin in question makes a specific transition either from low to high or any transition This capturing event can be used to trigger an interrupt so that the data can be processed before the next event In combination with the rollover interrupt on Capture module 0 you can measure intervals longer than 1 cycle gt Compare The inverse of a capture While capture mode is used to measure the time of an incoming pulse width modulation signal a signal whose information is encoded by the time variation between signal edges compare
3. 232 Interface Standard gt DB 25 connector is described in the book let s take a look at DB 9 Data Carrier Detect Received Date Transmitted Data Data Terminal Read Ring Indicator Signal Ground CPE EE 421 521 Microcomputers RS 232 Interface Standard Example 9 to 25 pin cable layout for asynchronous data CPE EE 421 521 Microcomputers 15 Alex Milenkovich The Minimal RS 232 Function DTE to DCE in simplex mode CPE EE 421 521 Microcomputers The Minimal RS 232 Function CPE EE 421 521 Microcomputers 16 Alex Milenkovich The Minimal RS 232 Function DTE to DCE with remote control DTE to DTE with remote control CPE EE 421 521 Microcomputers Handshaking Between RTS and CTS CPE EE 421 521 Microcomputers 17 Null Modem gt Null modem simulates a DTE DCE DCE DTE circuit Ring indicator Data terminal ready Carrier detect Signal ground Data set ready Clear to send Request to send Received data Transmitted data Protective ground Ring indicator Data terminal ready Carrier detect Signal ground Data set ready Clear to send Request to send Received data Transmitted data Protective ground CPE EE 421 521 Microcomputers USART Peripheral Interface gt Universal Synchronous Asynchronous Receive Transmit USART peripheral interface Supports two modes Asynchronous UART mode User manual Ch 13 Synchronous Peripheral Interface SPI mode User manual C
4. 421 521 Microcomputers Timer A PWM Up Down Mode Example OFFFFh lt thlfpe CCRO CCR2 CCRI1 CCR3 Oh TA1 Output 0 Degrees P 0 5xVmotor Px x TA2 Output 120 Degrees 0 93xVmotor HS ES 120 Degrees TAO Output 0 07xVmotor S PX Z TIMOV EQUO TIMOV EQUO TIMOV Interrupts can be generated Example shows Symmetric PWM Generation Digital Motor Control CPE EE 421 521 Microcomputers Alex Milenkovich C Examples J RRR K e e e He e KK KKK KK KKK KKK KKK KK IKK KKK KKK IK KKK IK KKK KK KKK KKK KKK s include lt msp430x14x h gt MSP FET430P140 Demo Timer_A Toggle P1 0 CCRO Contmode ISR DCO SMCLK Description Toggle P1 0 using software and TA_0 ISR Toggle rate is Void main void set at 50000 DCO SMCLK cycles Default DCO frequency used for TACLK Durring the TA 0 ISR P0 1 is toggled and 50000 clock cycles are added to WDTCTL WDTPW WDTHOLD Stop WDT CCRO TA 0 ISR is triggered exactly 50000 cycles CPU is normally P1DIR 0x01 P1 0 output off and 11 ve aa dun in CCTLO CCIE CCRO interrupt enabled ACLK n a MCLK SMCLK TACLK DCO 800k CCRO 50000 TACTL TASSEL 2 MC_2 SMCLK contmode MSP430F149 _BIS_SR LPMO_bits GIE Enter LPMO w interrupt 77 Timer AO interrupt service routine P1 0 gt LED M Buccini P10UT
5. Alex Milenkovich CPE EE 421 Microcomputers Instructor Dr Aleksandar Milenkovic Lecture Note S17 CPE EE 421 521 Microcomputers Course Administration gt Instructor gt URL gt TA gt Labs gt Test I gt Text gt Review gt Today Aleksandar Milenkovic milenka ece uah edu www ece uah edu milenka EB 217 L Mon 5 30 PM 6 30 PM Wen 12 30 13 30 PM http www ece uah edu milenka cpe421 05F Joel Wilder Lab 4 is on Hw 2 is posted Graded Solutions are in scr Microprocessor Systems Design 68000 Hardware Software and Interfacing M68K Chapter 1 Chapter 2 Chapter 3 MSP430 Introduction Arch Basic Clock System WDT Low Power Modes Digital 1 0 MSP43 eDigitat i Opmbiaaxers USART 2 Alex Milenkovich Review Digital I O all MSP430 Porti Ports Port2 Port6 ion Select Registe yes yes Direction Register PxDIR Output Register P egister P eee 3 Chapter 9 User s Manual pages 9 1 to 9 7 CPE EE 421 521 Microcomputers Digital I O Introduction gt MSP430 family up to 6 digital I O ports implemented P1 P6 gt MSP430F 14x all 6 ports implemented Ports P1 and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal The digital I O fea
6. ard Bi polar 3 to 12V ON O state or SPACE condition 3 to 12V OFF 1 state or MARK condition Modern computers accept OV as MARK Dead area between 3V and 3V is designed to absorb line noise Originally developed as a standard for communication between computer equipment and modems From the point of view of this standard MODEM data communications equipment DCE Computer equipment data terminal equipment DTE Therefore RS 232C was intended for DTE DCE links not for DTE DTE links as it is frequently used now CPE EE 421 521 Microcomputers Alex Milenkovich RS 232 Interface Standard gt Each manufacturer may choose to implement only a subset of functions defined by this standard gt Two widely used connectors DB 9 and DB 25 gt Three types of link Simplex Half duplex Full duplex gt Basic control signals RTS Request to send DTE indicates to the DCE that it wants to send data CTS Clear to send DCE indicates that it is ready to receive data DSR Data set ready indication from the DCE i e the modem that it is on DTR Data terminal ready indication from the DTE that it is on CPE EE 421 521 Microcomputers RS 232 Interface Standard another example Incgeterminate Region Seven Data Bits PU T DTR Data terminal ready indication from the DTE that it is on CPE EE 421 521 Microcomputers Alex Milenkovich Alex Milenkovich RS
7. h 14 gt UART mode Transmit receive characters at a bit rate asynchronous to another device Connects to an external system via two external pins URXD and UTXD P3 4 P3 5 Timing is based on selected baud rate both transmit and receive use the same baud rate Alex Milenkovich CPE EE 421 521 Microcomputers 18 Alex Milenkovich UART Features 7 or 8 bit data width odd even or non parity Independent transmit and receive shift reg Separate transmit and receive buffer registers LSB first data transmit and receive Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection Independent interrupt capability for transmit and receive CPE EE 421 521 Microcomputers 37 USART Block Diagram UART mode SWRST URMEx URXEIE URXWIE FE PE OE BRE L L Receive Status Recewer Buter UxRXBUF RXERR HXWAKE WD L TAKE LT AUF tax SYNG CKFH L SWRST UTAEs TERT SIG LHL Clack Phase and Polarity 19 Alex Milenkovich Initialization Sequence amp Character Format gt Initialization Sequence Set SWRST bit Initialize all USART registers with SWRST 1 Enable USART module via the MEx SFRs URXEx and or UTXEx Clear SWRST via software releases the USART for operation Optiona
8. l enable interrupts vie IEx SFRs gt Character format Mark sr C2 oe T 2nd Stop Bit SP 1 Parity Bit PENA 1 Address Bit MM 1 Optional Bit Condition 8th Data Bit CHAR 1 20
9. mode is used to generate a pulse width modulation PWM signal When the timer reaches the value ina compare register the module will give an interrupt and change the state of an output according to the other mode bits By updating the compare register numbers you change the timing of the signal level transitions CPE EE 421 521 Microcomputers 11 Timer_A Counting Modes UP DOWN Mode Timer counts between 0 and CCRO and 0 UP DOWN Mode Stop Halt Mode Timer is halted with the next CLK UP Mode Continuous Mode Timer counts between 0 and CCRO Timer continuously counts up OFFFFh Continuous Mode CPE EE 421 521 Microcomputers Alex Milenkovich Timer_A 16 bit Counter Timer Block TASSELx Dx Timer Clock TACLK Divider et Count Nie K 1 2 4 8 Mode ACLK Clear SMCLK INCLK Set TAIFG 0 0 0 0 sO Page 11 12 User s Manual CPE EE 421 521 Microcomputers Timer A Capture Compare Blocks Capture Path Capture Capture Compare Register Synchronize Capture Compare Path W W wW rw rw rw rw rw rw rw rw mw v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a rw rw rw rw rw mw w w w w w w r rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 CPE EE 421 521 Microcomputers Alex Milenkovich Timer_A Output Units OMx2 OMx1 OMx0 Function Operational Conditions Output Mode Outx signal is set according to Outx bit Set EQUx sets Out
10. pt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts Interrupt Edge Select Registers P1IES P2IES only for P1 and P2 Each PnlES bit selects the interrupt edge for the corresponding I O pin Bit 0 The PnIFGx flag is set with a low to high transition Bit 1 The PnIFGx flag is set with a high to low transition CPE EE 421 521 Microcomputers Timer_A MSP430x1xx gt Purpose The Timer A and B systems on the MSP are a versatile means to measure time intervals The timers can measure the timing on incoming signals or control the timing on outgoing signals This function is necessary to meet arbitrary timing requirements from outside components and the ability is useful in phase locking scenarios gt Features 16 bit counter with 4 operating modes Selectable and configurable clock sources internal ACLK SMCLK external INCLK TBCLK Three or five independently configurable capture compare registers with configurable inputs Three or five individually configurable output modules with 8 output modes Multiple simultaneous timings multiple capture compares multiple output waveforms such as PWM signals and any combination of these Interrupt capabilities e each capture compare block individually configurable CPE EE 421 521 Microcomputers Alex Milenkovich TACLK _ ACLK O Q SMCLK INCLK a CCIOA O__ CCIOB
11. transmitter side Individual bits are grouped into characters at the receiving side gt Information is usually transmitted as characters 7 or 8 bits of information plus control CPE EE 421 521 Microcomputers ASCII encoded bits 11 Alex Milenkovich Asynchronous Serial Interface cont d gt MARK level or OFF or 1 state or 1 level This is also the idle state before the transfer begins gt SPACE level or ON or O state or 0 level gt One character Start bit space level Data bits Optional parity bit Optional stop bit Data bits Parity Stop bit on s One character CPE EE 421 521 Microcomputers Asynchronous Serial Interface cont d gt 12 possible basic formats 7 or 8 bits of data Odd even or no parity 1 or 2 stop bits Others exist also no stop bits 4 5 6 data bits 1 5 stop bits etc Least significant bit Example Letter M ASCII 4D 1001101 even parity Mark 1 Space 0 CLP LL o AE 982 ETE I Parity CPE EE 421 521 Microcomputers 12 Receiver Clock Timing k an d Start bit T seconds Mark Space Beginning ot End of of start stop bit bit gt For N 9 bits 7 data parity stop maximum tolerable error is 5 assume that the receiver clock is slow T dt instead of T T 2 gt 2N 1 t 2 t 2 lt 1 2N 1 t T lt 100 2N 1 as a percentage CPE EE 421 521 Microcomputers RS 232 Interface Stand
12. tures include gt Independently programmable individual I Os gt Any combination of input or output gt Individually configurable P1 and P2 interrupts gt Independent input and output data registers The digital I O is configured with user software CPE EE 421 521 Microcomputers Alex Milenkovich Digital I O Registers Operation Input Register PniN Each bit in each PnIN register reflects the value of the input signal at the corresponding I O pin when the pin is configured as I O function Bit 0 The input is low Bit 1 The input is high Output Registers PnOUT Do not write to PxIN It will result in increased current consumption Each bit in each PnOUT register is the value to be output on the corresponding I O pin when the pin is configured as I O function and output direction Bit 0 The output is low Bit 1 The output is high CPE EE 421 521 Microcomputers Digital I O Operation Direction Registers PnDIR Bit 0 The port pin is switched to input direction Bit 1 The port pin is switched to output direction Function Select Registers PnSEL Port pins are often multiplexed with other peripheral module functions Bit 0 I O Function is selected for the pin Bit 1 Peripheral module function is selected for the pin CPE EE 421 521 Microcomputers Alex Milenkovich Digital I O Operation Interrupt Flag Registers P1IFG P2IFG only for P1 and P2 Bit 0 No interru
13. x signal clock synchronous with timer clock PWM Toggle Reset EQUx toggles Outx signal reset with EQUO clock sync with timer clock PWM Set Reset EQUx sets Outx signal reset with EQUO clock synchronous with timer clock Toggle EQUx toggles Outx signal clock synchronous with timer clock Reset EQUx resets Outx signal clock synchronous with timer clock PWM Toggle Reset EQUx toggles Outx signal set with EQUO clock synchronous with timer clock PWM Set Reset EQUx resets Outx signal set with EQUO clock synchronous with timer clock CPE EE 421 521 Microcomputers Timer_A Continuous Mode Example Oh CCRO TAO Input iti p Capture Mode Positive Edge CCR Pxy TA1 Input Capture Mode Both Edges CCR2 TA2 Input Capture Mode Negative Edge CCRO CCR1 CCR1 CCR1 CCR1 CCR1 CCR1 Interrupts can be generated CCR2 Example shows three independent HW event captures CCRx stamps time of event Continuous Mode is ideal CPE EE 421 521 Microcomputers Alex Milenkovich Alex Milenkovich Timer_A PWM Up Mode Example OFFFFh CCRO CCR1 CCR2 Oh CCR1 PWM Set Reset TA1 Output CCR2 PWM Reset Set TA2 Output Px y BO PWM Toggle TAO Output Px z Auto ns U2 EQU2 EQU2 Re loac 0 EQUI EQUO EQUI EQUO Interrupts can be generated Output Mode 4 PWM Toggle Example shows three different asymmetric PWM Timings generated with the Up Mode CPE EE

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