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16-Bit RISC Microcontroller User`s Manual

1. R D RISC DSP Controller R8820 Function Format Clocks Notes Unconditional Transfers CALL Call procedure direct within segment 11101000 disp low disp high 11 reg memory indirect within segment 11111111 mod 010 r m 12 17 indirect intersegment 11111111 mod 011 r m mod 41 25 direct intersegment 10011010 segment offset 18 selector RET Retum from procedure within segment 11000011 16 within segment adding immed to SP 11000010 data low data high 16 intersegment 11001011 23 instersegment adding immed to SP 1001010 data low data high 23 JMP Unconditional jump short long 11101011 disp low 9 9 direct within segment 11101001 disp low disp high 9 reg memory indirect within segment 11111111 mod 100 r m 11 16 indirect intersegment 11111111 mod 101 r m mod 11 18 direct intersegment 11101010 segment offset 11 selector Iteration Control LOOP z Loop CX times 11100010 disp 7 16 LOOPZ LOOPE Loop while zero equal 11100001 disp 7 16 LOOPNZ LOOPNE Loop while not zero equal 11100000 disp 7 16 JCXZ Jump if CX zero 11100011 disp 7 15 Interrupt INT Interrupt Type specified 11001101 type 41 Type 3 11001100 41 INTO Interrupt on overflow 11001110 43 4 BOUND Detect value out of range 01100010 mod reg r m 21 60 IRET Interrupt return 11001111 31 PROCESSOR CONTROL INSTRUCTIONS CLC clear carry 11111000
2. Function Format Clocks Notes BIT MANIPULATION INSTRUCTUIONS NOT Invert register memory 1111011w mod 010 r m 1 7 AND And reg memory and register to either 001000dw mod reg r m 1 7 immediate to register memory 1000000w mod 100 r m data data if w 1 1 8 immediate to accumulator 0010010w data data if w 1 1 OR Or reg memory and register to either 000010dw mod reg r m 1 7 immediate to register memory 1000000w mod 001 r m data data if w 1 1 8 immediate to accumulator 0000110w data data if w 1 1 XOR Exclusive or reg memory and register to either 001100dw mod reg r m 1 7 immediate to register memory 1000000w mod 110 r m data data if w 1 1 8 immediate to accumulator 0011010w data data if w 1 1 TEST And function to flags no result register memory and register 1000010w mod reg r m 1 7 immediate data and register memory 1111011w mod 000 r m data data if w 1 1 8 immediate data and accumulator 1010100w data data if w 1 1 Sifts Rotates register memory by 1 1101000w mod TTT r m 2 8 register memory by CL 1101001w mod TTT r m 1 n 7 n register memory by Count 1100000w mod TTT r m count 1 n 7 n STRING MANIPULATION INSTRUCTIONS MOVS Move byte word 1010010w 13 INS Input byte word from DX port 0110110w 13 OUTS Output byte word to DX port 0110111w 13 CMPS Compare byte word 101001 1w 18 SCAS Scan byte word 101011w 13 LODS Load byte word to AL AX 1010110w 13 STOS
3. 85 21 AC Characteristics 86 22 Package Information 95 23 Revision History 97 RDC Semiconductor Co Rev 1 3 Subject to change without notice R D RISC DSP Controller 16 Bit Microcontroller with 16 bit external data bus 1 Features Five stages pipeline RISC architecture e Static Design amp Synthesizable design e Bus interface Multiplexed address and Data bus which is compatible with 80C186 microprocessor Supports nonmultiplexed address bus A19 A0 1M byte memory address space 64K byte I O space Software is compatible with the 80C186 microproces sor Support two Asynchronous serial channel with hardware handshaking signals Supports 32 PIO pins R8820 PSRAM Pseudo static RAM interface with auto refresh control e Three independent 16 bit timers and one independent watchdog timer The Interrupt controller with seven maskable external interrupts and one nonmaskable external interrupt Two independent DMA channels Programmable chip select logic for Memory or I O bus cycle decoder Programmable wait state generator Support serial port DMA transfers 2
4. R D il RISC DSP Controller R8820 20 INSTUCTION SET OPCODES AND CLOCK CYCLES Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS MOV Move register to register memory 1000100w mod reg r m 1 1 register memory to register 1000101w mod reg r m 1 6 immediate to register memory 1100011w mod 000 r m data data if w 1 1 1 immediate to register 1011w reg data data if w 1 1 memory to accumulator 1010000w __ addr low addr high 6 accumulator to memory 1010001w addr low addr high 1 register memory to segment register 10001110 mod 0 reg r m 3 8 segment register to register memory 10001100 mod 0 reg r m 2 2 PUSH Push memory 11111111 mod 110 r m 8 register 01010 reg 3 segment register 000reg110 2 immediate 011010s0 data data if s 0 1 POP Pop memory 10001111 mod 000 r m 8 register 01011 reg 6 segment register 000 reg 111 reg Al 8 PUSHA Push all 01100000 36 POPA Pop all 01100001 44 XCHG Exchange register memory 1000011w mod reg r m 3 8 register with accumulator 10010 reg 3 XTAL Translate byte to AL 11010111 10 IN Input from fixed port 1110010w __ port 12 variable port 1110110w 12 OUT Output from fixed port 1110010w __ port 12 variable port 1110110w 12 LEA Load EA to register 10001101 mod reg r m 1 LDS Load pointer to DS 11000101 mod reg r m mod AD 14 LES Load pointer to ES 11000100 mod reg r m mod Al 14 ENTER Build stack frame 11001000 data low data high L L 0 7 L 1 11 L gt 1 1
5. 13 XI Input Input to the oscillator amplifier 14 X2 Output Output from the inverting oscillator amplifier 16 CLKOUTA Output Clock output A The CLKOUTA operation is the same as crystal input frequency X1 CLKOUTA remains active during reset and bus hold conditions 17 CLKOUTB Output Clock output B The CLKOUTB operation is the same as crystal input frequency X1 CLKOUTB remains active during reset and bus hold conditions Asynchronous Serial Port Interface RXDO0 PIO23 Input Output Receive data for asynchronous serial port 0 This pin receives asynchronous serial data TXDO PIO22 Output Input Tranmit data for asynchronous serial port 0 This pin transmits asynchronous serial data from the UART of the microcontrolles RTSO RTRO PIO20 Output Input Ready to send Ready to Receive signal for asynchronous serial port 0 When the RTSO bit in the AUXCON register is set and FC bit in the serial port O register is set the RTSO signal is enabled Otherwise the RTSO bit is cleared and FC bit is set the RTRO signal is enabled 100 CTS0 ENRXO PIO21 Input Output send Enable asynchronous serial port 0 when ENRXO bit in the AUXCON register is cleared and the FC bit in the serial port 0 control register is set the ENRXO signal is enabled Other when ENRXObit is set and the FC bit is set the ENRXO signal is enabled Clear to Receiver Re
6. RDC Semiconductor Co Rev 1 3 Subject to change without notice 14 R D RISC DSP Controller A19 A0 AD15 ADO BHE ucs LCS PCSx MCSx DEN DT R s2 s0 UZI T1 T2 READ CYCLE DRES T3 T4 CLKOUTA TW R8820 RDC Semiconductor Co Subject to change without notice Rev 1 3 R D RISC DSP Controller A19 A0 S6 AD15 ADO WHB WLB BHE UCS LCS PCSx MCSx DEN DT R S2 S0 UZI T1 T2 WRITE CYCLE DRESS T3 DATA T4 CLKOUTA TW R8820 RDC Semiconductor Co Subject to change without notice Rev 1 3 RDC BBO 6 Oscillator Characteristics amp System Clock For fundamental mode crystal C 20pF 20 C 20pF 20 C2 20pF 20 C2 20pF 20 Rf 1 mega ohm C3 200pf C3 Don t care Rf 1 mega ohm L Don t care L 3 0uH 20 40MHz 4 7uH 20 33MHz 8 2uH 20 25MHz 12uH 20 20MHZ RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC X Reo 7 Execution Unit 7 1 General Register The R8820 has eight 16 bit general registers And the AX BX CX DX can be subdivided into two 8 bit register AH AL BH BL CH
7. NoDMA No DMA 0 0 1 DMAO DMA 1 0 1 0 DMA1 DMA 0 0 1 1 N A N A 1 0 0 DMAO No DMA 1 0 1 DMA1 No DMA 1 1 0 NoDMA DMA 0 1 1 1 NoDMA DMA 1 Bit 12 RSIE Receive Status Interrupt Enable An exception occurs during data reception or error detection occur will generate an interrupt Set 1 Enable the serial port 0 to generate an interrupt request Bit 11 BRK Send Break Set this bit to 1 the TXD pin always drives low RDC Semiconductor Co Rev 1 3 Subject to change without notice 72 R D RISC DSP Controller Long Break The TXD is driven low for grater than 2M 3 bit times Short break The TXD is driven low for grater than M bit times M start bit data bits number parity bit stop bit R8820 Bit 10 TBS Transmit Bit 8 This bit is transmitted as ninth data bit in mode 2 and mode 3 This bit is cleared after every transmission Bit 9 FC Flow Control Enable Set 1 Enable the hardware flow control for serial port 0 Set 0 Disable the hardware flow control for serial port 0 Bit 8 TXIE Transmitter Ready Interrupt Enable When the Transmit Holding Register is empty THRE bit in Status Register is set it will have an interrupt occurs Set 1 Enable the Interrupt Set 0 Disable the interrupt Bit 7 RXIE Receive Data Ready Interrupt Enable When the receiver buffer contains valid data RDR bit in Status Register is set it
8. Priority PR2 PRO High 0 000 1 001 2 010 3 011 4 100 5 101 6 110 Low 7 111 Slave Mode Determining the minimum priority level at which maskable interrupts can generate an interrupt Bit 15 3 Reserved Bit 2 0 PRM2 PRMO Priority Field Mask Determining the minimum priority that is required in order for a maskable interrupt source to generate an interrupt Priority PR2 PRO High 0 000 1 001 2 010 3 011 4 100 5 101 6 110 Low 7 111 Interrupt Mask Register Offset 28h Reset Value 07FDh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode Bit 15 11 Reserved Bit 10 SPO Serial Port 0 Interrupt Mask The state of the mask bit of the asynchronous serial port 0 interrupt Bit 9 SP1 Serial Port 1 Interrupt Mask The state of the mask bit of the asynchronous serial port 1 interrupt Bit 8 4 14 10 Interrupt Masks Indicates the state of the mask bit of the corresponding interrupt Bit 3 2 D1 I6 D0 I5 DMA Channel or INT Interrupt Masks Indicates the state of the mask bit of the corresponding DMA Channel or INT interrupt Bit 1 Reserved Bit 0 TMR Timer Interrupt Mask The state of the mask bit of the timer control unit RDC Semiconductor Co Rev 1 3 Subject to change without notice 50 RDO ooo 620 Interrupt Request Register Offset 28h Reset Value 003Dh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode Bit 15 6 Reserved
9. Block Diagram INT2 INTAO INT1 SELECT CLKOUTA INT3 INTA1 IRO TMROUTO TMROUT1 A A A DROO DRQ1 itl CLKOUTB INT6 INT4 INTO ji TMRINO TAS imi x X2 Clock and Interrupt Timer Control DMA vec Power Control Unit Unit Unit GND gt Management RST gt Chip Select Instruction Unit Queue 64bits PSRAM Instruction Control Decoder Unit Register File General Refresh Segment SOME Or Eflag Register Unit Bus HOLD Interface ELDA Unit S6 CLKDIV2 lt gt vu lt gt Control Signal Micro ROM Address Execution Unit PIO Unit Asynchro nous Serial Port0 P gt RTSO RTRO CTSO ENRXO Asynchro nous Serial Portl J gt TXDO I RXDO gt RTST RTRI 4 CTS1 ENRXI J gt TxD1 RXD1 M AD15 aDO Y v Wi W BHE ADEN RDC Semiconductor Co Subject to change without notice Rev 1 3 R D RISC DSP Controller R8820 3 Pin Configuration PQFP 97 J UZI PIO26 96 S6 CLKDIV2 PIO29 95 AD15 99 RXD1 PIO28 98 TXD1 PIO27 93 AD14 92 VCC 91 AD6 90 AD13 89 GND 88 AD5 87 AD12 86 AD4 85 AD11 84 C_J AD3 83 AD10 94 AD7 R
10. Encodings BHE ADO or AO Type of Bus Cycle 0 0 Word transfer 0 1 High byte transfer D15 D8 1 0 Low byte transfer D7 DO 1 1 Refresh The address portion of the AD bus can be enabled or disabled by DA bit in the LMCS and UMCS register during LCS or UCS bus cycle access if BHE ADEN is held high during power on reset The BHE ADEN with a internal weak pull up register so no external pull up register is required The AD bus always drives both address and data during LCS or UCS bus cycle access if the BHE ADEN pin with external pull low resister during reset Output Write strobe This pin indicates that the data on the bus is to be written into a memory or an I O device WR is active during T2 T3 and Tw of any write cycle floats during a bus hold or reset al Output Read Strobe Active low signal which indicates that the microcontroller is performing a memory or I O read cycle RD floats during bus hold or reset ALE Output Address latch enable Active high This pin indicates that an address output on the AD bus Address is guaranteed to be valid on the trailing edge of ALE This pin is tri stated during ONCE mode and is never floating during a bus hold or reset ARDY Input Asynchronous ready This pin performs the microcontroller that the address memory space or I O device will complete a data transfer The ARDY pin accepts a rising edge that is asynchronou
11. For example if the block size is 32K bytes and the base address is located at 20000h The individual active memory address range of MCS3 to MCSO is MCS0 20000h to 21FFE MCSI 22000 to 23FFFh MCS2 24000h to 25FFFh MCS3 26000h to 27FFFh MCSx total block size is defined by M6 MO M6 M0_ Totalblock size MCSx address active range 0000001b 8k 2k 0000010b 16k 4k 0000100b 32k 8k 0001000b 64k 16k 0010000b 128k 32k 0100000b 256k 64k 1000000b 512k 128k Bit 7 EX Pin Selector This bit configures the multiplex output which the PCS6 PCS5 pins as chip selects or A2 A1 Set 1 PCS6 PCS5 are configured as peripheral chip select pins Set 0 PCS6 is configured as address bit A2 PCS5 is configured as Al Bit 6 MS Memory or I O space Selector Set 1 The PCSx pins are active for memory bus cycle Set 0 The PCSx pins are active for I O bus cycle Bit 5 3 Reserved Bit 2 R2 Ready Mode This bit is configured to enable disable the wait states inserted for the PCS5 PCS6 chip selects The R1 RO bits of this register determine the number of wait state to insert set to 1 external ready is ignored set to 0 external ready is required Bit 1 0 R1 RO Wait State value The R1 RO determines the number of wait states inserted into a PCS5 PCS6 access R1 RO 1 1 3 wait states 1 0 2 wait states 0 1 1 wait states 0 0 O wait states 12 4 PCSx The peripheral or m
12. RDC ezo 22 PACKAGE INFORMATION PQFP D 23 20 0 25 D1 20 00 0 10 A E 17 20 0 25 o H o 4 o o lt H e El 0 65 BSC A SEATING PLANE JN I I I 0 25 MIN Al a 0 089 e 0 22 0 38 bl f lt gt BASE META 0 22 0 30 0 33 3 40 MAX ha YGY P 1 60 REF H H 4 H E a pud Y ES Pd N y ou 0 25 l E z in A 0 88 0 15 DETAIL A NES Ro i v X e NC Y po i Et JP QT RE RDC Semiconductor Co Rev 1 3 Subject to change without notice 95 RDC ooo 620 LQFP TCR 0 50 TYP 0 224 0 05 Ds Sealing Plane amp 0 076 MAX q SS es UNIT mm RDC Semiconductor Co Rev 1 3 Subject to change without notice O R D RISC DSP Controller R8820 23 Revision History Rev Date History 0 1 2000 3 8 Preliminary release 1 0 2000 7 31 Formal release 1 1 2000 9 1 Adding the pin configuration amp package information for LQFP package 1 2 2000 9 22 Modify the Serial Port 0 Baud Rate Divisor Register in page 73 1 3 2001 3 13 Add PQFP and LQFP Pin Out Table Rev 1 3 RDC Semiconductor Co Subject to change without notice 97
13. Set 1 8 bits data bus access when the memory access locate in the selection memory space Set 0 16 bits data bus access when the memory access locate in the selection memory space IOSIZ VO Space Data Bus Size selection This bit determines the width of the data bus for all I O space accesses Set 1 8 bits data bus access Set 0 16 bits data bus access RDC Semiconductor Co Subject to change without notice 30 Rev 1 3 RDC ooo 12 Chip Select Unit The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or peripheral device The chip selects are programmed through five peripheral control registers AOh A2h A4h A6h A8h And all of the chip selects can be insert wait states by programmed the peripheral control register 12 1 UCS The UCS default to active on reset for program code access The memory active range is upper 512k 80000h FFFFFh which is programmable And the default memory active range of UCS is 64k F0000h FFFFFh The UCS active to drive low four CLKOUTA oscillators if no wait state inserts There are three wait states insert to UCS active cycle on reset Upper Memory Chip Select Register Offset AOh Reset Value FO3Bh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 Reserved Bit 14 12 LB2 LB0 Memory block size selection for UCS chip select pin The UCS chip select pin active region can be configured by the LB2 LBO The default memory block
14. The UCS code fetched selection is 16 bits bus width which can not be changed by programmed the register Auxiliary configuration Register Offset F2h 15 Reset Value 0000h 14 13 12 11 10 9 8 7 NRX1 o NRXO gt 5 3 2 1 0 E E Bit 15 7 Reserved Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ENRX1 Enable the Receiver Request of Serial port 1 Set 1 The CTSI ENRXI pin is configured as ENRXI Set 0 The CTSI ENRXI pin is configured as CTSI RTS1 Enable Request to Send of Serial port 1 Set 1 The RTR1 RTSI pin is configured as RTSI Set 0 The RTR1 RTSI pin is configured as RTRI ENRXO Enable the Receiver Request of Serial port 0 Set 1 The CTSO ENRXO pin is configured as ENRXO Set 0 The CTSO ENRXO pin is configured as CTSO RTSO0 Enable Request to Send of Serial port 0 Set 1 The RTRO RTSO pin is configured as RTSO Set 0 The RTRO RTSO pin is configured as RTRO LSIZ LCS Data Bus Size selection This bit can not be changed while executing from LCS space or while the Peripheral Control Block is overlaid with PCS space Set 1 8 bits data bus access when the memory access located in the LCS memory space Set 0 16 bits data bus access when the memory access located in the LCS memory space MSIZ MCSx PCSx Memory Data Bus Size selection This bit can not be changed while executing from the associated or while the Peripheral Control Block is overlaid on this address space
15. This bit contains the ninth data bit received in mode 2 and mode 3 Bit 7 RDR Received Data Ready Read only The Received Data Register contains valid data this bit is set high This bit can only be reset by reading the Serial Port 0 Receive Register Bit 6 THRE Transmit Hold Register Empty Read only When the Transmit Hold Register is ready to accept data this bit will be set This bit will be reset when writing data to the Transmit Hold Register Bit 5 FER Framing Error detected This bit should be reset by software This bit is set when a framing error is detected Bit 4 OER Overrun Error Detected This bit should be reset by software This bit is set when an overrun error is detected Bit 3 PER Parity Error Detected This bit should be reset by software This bit is set when a parity error for mode 1 and mode 3 is detected Bit 2 TEMT Transmitter Empty This bit is read only When the Transmit Shift Register is empty this bit will be set Bit 1 HS0 Handshake Signal 0 This bit is read only This bit reflects the inverted value of the external CTSO pin Bit 0 Reserved Serial Port 0 Transmit Register Offset 84h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 8 Reserved RDC Semiconductor Co Rev 1 3 Subject to change without notice 74 RDC 620 Bit 7 0 TDATA Transmit Data Software writes this register with data to be transmitted on the serial port 0 Serial Port 0 Receive Register Of
16. gt Decode gt EA gt Access gt Idle gt TQ gt 11 gt T gt T3 E Bus Cycle p d 4 2 Memory push uOP need 1 cycle if it has no previous Memory push uOP and 5 cycles if it has previous Memory push or Memory Write uOP Pipeline stages for Memory push uOP after Memory push uOP another 5 cycles Fetch gt Decode gt EA Accesd gt Idle gt T0 TI T2 gt 13 WB 1 Memory push uOP on uOP Fetch gt Decode gt EA Acces gt Acces gt Acces gt Accesd gt Access dle T1 gt T2 gt T3 gt WB B N pipeline stall 2 adii 4 3 MUL uOP and DIV of ALU function OP for 8 bits operation need both 8 cycles for 16 bits operation need both 16 cycles 4 4 All jumps calls ret and loopXX instructions required to fetch the next instruction for the destination address Unconditional Fetch uOP will need 9 cycles Pipeline stages for unconditional fetch Fetch gt Decode gt EA gt acces Idle gt TO gt T1 gt T2 Fetch uOP ne uOP Fetch gt Decode gt EA Acces Acces gt Acces gt T2 gt T3 gt WB o NE will be flushe These 9 cycles caused bra
17. 0 Interrupt is triggered by low go high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of the INT4 Set 0 Enable the INT4 interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of 44h INT3 Control Register Offset 3Eh Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pss ew fe i Pre ens en Master Mode Bit 15 8 bit 6 5 Reserved Bit 7 ETM Edge trigger enable When this bit set to 1 and Bit 4 set to 0 interrupt is triggered by low go high edge The low go high edge will be latched one level till this interrupt is been serviced Bit 4 LTM Level Triggered Mode Set 1 Interrupt is triggered by high active level Set 0 Interrupt is triggered by low go high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of the INT3 Set 0 Enable the INT3 interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of 44h RDC Semiconductor Co Rev 1 3 Subject to change without notice 42 RDC A3203 Reo INT2 Control Register Offset 3Ch Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IA E eue Pre ens ene Master Mode Bit 15 8 bit 6 5 Reserved Bit 7 ETM Edge trigger enable When this bit set to 1 and Bit 4 set to O interrupt is triggered by low go high edge The low go high edge will be latched one level till this interrupt is been serviced Bit 4
18. 0 Enable the DMA controller interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Timer Interrupt Control Register Offset 32h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LojojofojofolofojofoJo Jue prs emo Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the timer controller Set 0 Enable the timer controller interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Slave Mode reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the timer 0 controller Set 0 Enable the timer 0 controller interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h R8820 RDC Semiconductor Co Subject to change without notice 46 Rev 1 3 RDC io 620 Interrupt Status Register Offset 30h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode Reset value undefine Bit 15 DHLT DMA Halt Set 1 halts any DMA activity When non maskable interrupts occur Set 0 When an IRET instruction is executed Bit 14 3 Reserved Bit 2 0 TMR2 TMRO Set 1 indicates the corresponding timer has an interrupt request pending Slave Mode Reset value is 0000h Bit 15 DHLT DMA Halt Set 1 halts any DMA activity
19. Bit 5 4 TMR2 TMRI Timer 2 Timerl Interrupt Mask The state of the mask bit of the Timer Interrupt Control register Set 1 Timer2 or Time has its interrupt requests masked Bit 3 2 D1 I6 D0 I5 DMA Channel or INT Interrupt Mask Indicating the state of the mask bits of the corresponding DMA or INT6 INTS control register Bit 1 Reserved Bit 0 TMRO Timer 0 Interrupt Mask The state of the mask bit of the Timer Interrupt Control Register Poll Status Register Offset 26h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode The Poll Status POLLST register mirrors the current state of the Poll register the POLLST register can be read without affecting the current interrupt request Bit 15 IREQ Interrupt Request Set 1 if an interrupt is pending The S4 SO field contains valid data Bit 14 5 Reserved Bit 4 0 S4 S0 Poll Status Indicates the interrupt type of the highest priority pending interrupt Poll Register Offset 24h Reset Value 15 14 13 12 311 10 9 8 7 6 5 4 3 2 1 0 Master Mode When the Poll register is read the current interrupt is acknowledged and the next interrupt takes its place in the Poll register Bit 15 IREQ Interrupt Request Set 1 if an interrupt is pending The S4 SO field contains valid data RDC Semiconductor Co Rev 1 3 Subject to change without notice 51 RDC ooo 620 Bit 14 5 Reserved Bit 4 0 S4 S0 Poll Status Indicates the interrupt type of the highes
20. CL DH DL The functions of these registers are described as follows AX Word Divide Word Multiply Word I O operation AH Byte Divide Byte Multiply Byte I O Decimal Arithmetic Translate operation AL Byte Divide Byte Multiply operation BX Translate operation CX Loops String operation CL Variable Shift and Rotate operation DX Word Divide Word Multiply Indirect I O operation SP Stack operations POP POPA POPF PUSH PUSHA PUSHF BP General purpose register which can be used to determine offset address of operands in Memory SI String operations DI String operations High Low AX Accumulator Data DS Base Register TOUR cx Count Loop Repeat Shift DX Data Stack Pointer Index Group Base Pointer and Pointer Source Index Destination Index GENERAL REGISTERS 7 2 Segment Register R8820 has four 16 bit segment registers CS DS SS ES The segment registers contain the base addresses starting location of these memory segments and they are immediately addressable for code CS data DS amp ES and stack SS memory CS Code Segment The CS register points to the current code segment which contains instruction to be fetched The default location memory space for all instruction is 64K The initial value of CS register is OFFFFh RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC 20 DS Data Segment The DS register points to the current data segment which
21. Channel or INT Interrupt In Service Set 1 the corresponding DMA channel or INT interrupt is currently being serviced Bit 1 Reserved Bit 0 TMR Timer Interrupt In Service Set 1 the timer interrupt is currently being serviced In Service Register Offset 2Ch Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode The bits in the In Service register are set by the interrupt controller when the interrupt is taken The in service bits are cleared by writing to the EOI register Bit 15 6 Reserved Bit 5 4 TMR2 TMRI Timer2 Timerl Interrupt In Service Set 1 the corresponding timer interrupt is currently being serviced Bit 3 2 D1 I6 D0 I5 DMA Channel or INT Interrupt In Service Set 1 the corresponding DMA Channel or INT Interrupt is currently being serviced Bit 1 Reserved Bit 0 TMRO Timer 0 Interrupt In Service Set 1 the Timer 0 interrupt is currently being serviced Priority Mask Register Offset 2Ah Reset Value 0007h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lojojofojofolfofojofofofo uj Master Mode Determining the minimum priority level at which maskable interrupts can generate an interrupt Bit 15 3 Reserved Bit 2 0 PRM2 PRMO Priority Field Mask Determining the minimum priority that is required in order for a maskable interrupt source to generate an interrupt RDC Semiconductor Co Rev 1 3 Subject to change without notice 49 RDC io 620
22. LCS valid 0 15 ns 19 UCS LCS inactive delay 0 15 ns 20 PCS MCS active delay 0 15 ns 2 PCS MCS inactive delay 0 15 ns 22 DEN active delay 0 15 ns 23 DEN inactive delay 0 15 ns 24 DTR active delay 0 15 ns 25 DTR inactive delay 0 15 ns 26 Status active delay 0 15 ns 27 Status inactive delay 0 15 ns 28 UZI active delay 0 15 ns 29 UZI inactive delay 0 15 ns RDC Semiconductor Co Rev 1 3 Subject to change without notice 89 R8820 RISC DSP Controller O RD CLKOUTA o U o o v A19 A0 Rev 1 3 RDC Semiconductor Co Subject to change without notice 90 R8820 RISC DSP Controller O RD g d 9 Rev 1 3 RDC Semiconductor Co Subject to change without notice 91 RD O RISC DSP Controller R8820 CLKOUTA A19 A0 AD15 ADO al mn TT Te inum je HOLD HLDA Timing RDC Semiconductor Co Subject to change without notice 92 Rev 1 3 RDC vo 020 CLKOUTA ARDY Timing RDC Semiconductor Co Rev 1 3 Subject to change without notice 93 R8820 RISC DSP Controller RD CLKOUTA O E gt e oc o Rev 1 3 RDC Semiconductor Co Subject to change without notice 94
23. LTM Level Triggered Mode Set 1 Interrupt is triggered by high active level Set 0 Interrupt is triggered by low go high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of the INT2 Set 0 Enable the INT2 interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h INT1 Control Register Offset 3Ah Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pers en emu o cru ms pre ems eno Master Mode Bit 15 8 Reserved Bit 7 ETM Edge trigger enable When this bit set to 1 and Bit 4 set to O interrupt is triggered by low go high edge The low go high edge will be latched one level till this interrupt is been serviced Bit 6 SENM Special Fully Nested Mode Set 1 Enable the special fully nested mode of INT1 Bit 5 C Cascade Mode Set this bit to 1 to enable the cascade mode for INT1 or INTO Bit 4 LTM Level Triggered Mode Set 1 Interrupt is triggered by high active level Set 0 Interrupt is triggered by low go high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of the INTI Set 0 Enable the INT interrupt RDC Semiconductor Co Rev 1 3 Subject to change without notice 43 RDC ooo 620 Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Slave Mode This register is for timer 2 interrupt control reset value is 0000h Bit 15 4 Reserved Bit 3 MSK M
24. Maxcount Compare A again Maxcount Compare B is not used in this mode Bit 0 CONT Continuous Mode Bit Set 1 The timer to run continuously Set 0 The timer will halt after each counting to the maximum count and the EN bit will be cleared RDC Semiconductor Co Rev 1 3 Subject to change without notice 64 RDC vo 620 Timer 1 Count Register Offset 58h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 1 Count Value This register contains the current count of timer 1 The count is incremented by one every four internal processor clocks or by prescaled the timer 2 or by one every four external clock which is configured the external clock select bit to refer the TMRINI signal Timer 1 Maxcount Compare A Register Offset 5Ah Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO 3Bit 15 0 TC15 TCO Timer 1 Compare A Value Timer 1 Maxcount Compare B Register Offset 5Ch Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 1 Compare B Value Timer 2 Mode Control Register Offset 66h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Len mur o o folofofojolfwjofolopo low Bit 15 EN Enable Bit Set 1 The timer 2 is enable Set 0 The timer 2 is inhibited from counting The INH bit must be set 1 during writing the EN bit and the INH bit and EN bit must be in the same write Bit 14 INH In
25. O27 21 98 DT R PI 04 71 48 RXDI PI 028 22 99 DEN PI O5 72 49 CTSO ENRXO PIO21 23 100 MCSO PI O14 73 50 RXDO PI 023 24 1 MCSI PI O15 74 51 TXDO0 PI O22 25 2 I NT4 PI O30 75 52 RTSO RTRO PIO20 26 I NT3 INTAI I RQ 76 53 BHE ADEN 27 4 INT2 INTAO PI O31 77 54 WR 28 5 INTI SELECT 78 55 RD 29 6 INTO 79 56 ALE 30 7 UCS ONCEI 80 57 ARDY 31 8 LCS ONCEO sl 58 S2 32 3 PCS6 A2 PI O2 82 59 S1 33 10 PCS5 A1 PI O3 83 60 SO 34 11 VCC 84 31 GND 35 12 PCS3 RTSI RTR1 PI O19 85 62 XI 36 13 PCS2 CTSI ENRXI PI O18 86 63 X2 37 14 GND 87 64 VCC 38 15 PCS1 PI 017 88 65 CLKOUTA 39 16 PCSO PI O16 89 66 CLKOUTB 40 17 VCC 90 67 GND 41 18 MCS2 PI O24 9 68 A19 PI O9 42 19 MCS3 RFSH PI O25 92 69 A18 PI O8 43 20 GND 93 70 VCC 44 21 RST 94 71 A17 PI O7 45 22 TMRI N1 PI 00 95 72 A16 46 23 TMROUTI PI O1 96 73 A15 47 24 TMROUTO PI O10 97 74 Al4 48 25 TMRI NO PI O11 98 75 Al3 49 26 DRQI INT6 PI O13 99 76 A12 50 27 DRQO INT5 PI O12 100 71 RDC Semiconductor Co Rev 1 3 Subject to change without notice R D RISC DSP Controller 4 Pin Description R8820 Pin No PQFP Symbol Type Description 15 21 38 61 67 92 VCC Input System power 5 volt power supply 12 18 41 64 70 89 GND Input System ground 71 RST Input Reset input When RST is asserted the CPU immediately terminate all operation clears the internal registers amp logic and the address transfers to the reset address FFFFOh
26. Store byte word from AL AX 1010101w 7 Repeated by count in CX MOVS z Move byte word 11110010 1010010w 4 9n INS Input byte word from DX port 11110010 0110110w 5 9n OUTS Output byte word to DX port 11110010 0110111w 5 9n CMPS Compare byte word 1111011z 1010011w 4 18n SCAS Scan byte word 1111001z 1010111w 4 13n LODS Load byte word to AL AX 11110010 0101001w 3 9n STOS Store byte word from AL AX 11110100 0101001w 4 3n PROGRAM TRANSFER INSTRUCTIONS Conditional Transfers Xunpif JE JZ equal zero 01110100 disp 1 9 JL JNGE less not greater or equal 01111100 disp 1 9 JLE JNG less or equal not greater 01111110 disp 1 9 JC JB JNAE carry below not above or equal 01110010 disp 1 9 JBE JNA below or equal not above 01110110 disp 1 9 JP JPE parity parity even 01111010 disp 1 9 JO overflow 01110000 disp 1 9 JS sign 01111000 disp 1 9 JNE JNZ not equal not zero 01110101 disp 1 9 JNL JGE not less greater or equal 01111101 disp 1 9 JNLE JG not less or equal greater 01111111 disp 1 9 JNC JNB JAE not carry not below 01110011 disp 1 9 above or equal JNBE JA not below or equal above 01110111 disp 1 9 JNP JPO not parity parity odd 01111011 disp 1 9 JNO not overflow 01110001 disp 1 9 JNS not sign 01111001 disp 1 9 RDC Semiconductor Co Rev 1 3 Subject to change without notice 83
27. The Interrupt Request register is a read only register For internal interrupts D1 I6 D0 I5 TMR2 TMRI and TMRO the corresponding bit is set to 1 when the device requests an interrupt The bit is reset during the internally generated interrupt acknowledge Bit 15 6 Reserved Bit 5 4 TMRZ TMRI Timer2 Timerl Interrupt Request Set 1 Indicates the state of any interrupt requests form the associated timer Bit 3 2 D1 16 D0 I5 DMA Channel or INT Interrupt Request Set 1 Indicates the corresponding DMA channel or INT has an interrupt pending Bit 1 Reserved Bit 0 TMRO Timer 0 Interrupt Request Set 1 Indicates the state of an interrupt request from Timer 0 In Service Register Offset 2Ch Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode The bits in the INSERV register are set by the interrupt controller when the interrupt is taken Each bit in the register is cleared by writing the corresponding interrupt type to the EOI register Bit 15 11 Reserved Bit 10 SPO Serial Port O Interrupt In Service Set 1 the serial port 0 interrupt is currently being serviced Bit 9 SP1 Serial Port 1 Interrupt In Service Set 1 the serial port 1 interrupt is currently being serviced RDC Semiconductor Co Rev 1 3 Subject to change without notice 48 RDC co 20 Bit 8 4 14 10 Interrupt In Service Set 1 the corresponding INT interrupt is currently being serviced Bit 3 2 D1 I6 D0 I5 DMA
28. When non maskable interrupts occur Set 0 When an IRET instruction is executed Bit 14 3 Reserved Bit 2 0 TMR2 TMRO Set 1 indicates the corresponding timer has an interrupt request pending Interrupt Request Register Offset 2Eh Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Master Mode The Interrupt Request register is a read only register For internal interrupts SPO SP1 D1 I6 DO IS and TMR the corresponding bit is set to 1 when the device requests an interrupt The bit is reset during the internally generated interrupt acknowledge For INT4 INTO external interrupts the corresponding bit 14 10 reflects the current value of the external signal Bit 15 11 Reserved Bit 10 SPO Serial Port 0 Interrupt Request Indicates the interrupt state of the serial port 0 Bit 9 SP1 Serial Port 1 Interrupt Request Indicates the interrupt state of the serial port 1 Bit 8 4 14 10 Interrupt Requests Set 1 The corresponding INT pin has an interrupt pending Bit 3 2 D1 16 D0 I5 DMA Channel or INT Interrupt Request RDC Semiconductor Co Rev 1 3 Subject to change without notice 47 RDC ooo ezo Set 1 The corresponding DMA channel or INT has an interrupt pending Bit 1 Reserved Bit 0 TMR Timer Interrupt Request Set 1 The timer control unit has an interrupt pending Interrupt Request Register Offset 2Eh Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave Mode
29. can be used as a prescale to timer O and timer 1 or as a DMA request source Timer 0 Mode Control Register Offset 56h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wjmu o eo o jo o eowc no e e ar cor These bits definition for timer 0 are same as the bits of register 5Eh for timer 1 Timer 0 Count Register Offset 50h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO RDC Semiconductor Co Subject to change without notice 62 Rev 1 3 RDC ico 620 Bit 15 0 TC15 TCO Timer 0 Count Value This register contains the current count of timer 0 The count is incremented by one every four internal processor clocks or by prescaled the timer 2 or by one every four external clock which is configured the external clock select bit to refer the TMRINI signal Timer 0 Maxcount Compare A Register Offset 52h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 0 Compare A Value Timer 0 Maxcount Compare B Register Offset 54h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 0 Compare B Value Timer 1 Mode Control Register Offset 5Eh Reset Value 0000h 14 11 10 15 13 12 9 8 7 6 5 4 3 2 1 0 Len mu rjf o oj o foo wn e ext ar feon Bit 15 EN Enable Bit Set 1 The timer 1 is enable Set 0 The timer 1 is inhibited from counting The INH bit must be set 1 during writing the
30. hold request a refresh request or another DMA request The registers CAh C8h C6h C4h C2h COh DAh D8h D6h D4h D2h DOh are used to configure and operate the two DMA channels RDC Semiconductor Co Rev 1 3 Subject to change without notice 54 RDC ooo 620 CLKOUTA ALE A19 AO0 Addres Address l l apis ano Chic 1X Deme y ad zc ED WR l l l l l l l l l Typical DMA Trarsfer DMA Control Registers Offset CAh DMAO Reset Value FFF9h 14 11 1 9 8 7 6 5 4 3 2 1 0 15 13 12 0 DM O DDEC DINC SM IO SDEC SINC SYN1 SYNO P rona The definition of Bits 15 0 for DMAO are same as the Bits 15 0 of register DAh for DMAI DMA Transfer Count Register Offset C8h DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO DMA 0 transfer Count The value of this register is decremented by 1 after each transfer DMA Destination Address High Register Offset C6h DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 4 Reserved RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC ooo 620 Bit 3 0 DDA19 DDA16 High DMA 0 Destination Address These bits are map to A19 A16 during a DMA transfer when the destination address is in memory space or I O space If the destination address is in I O space 64Kbytes the
31. send data to DCE b RTS signal is asserted by DTE when data is available c The signal is interpreted by the DCE device as a request to enable its receiver d The DCE asserts the RTR signal to response that DCE is ready to receive data 17 1 2 CTS RTR Protocol The serial port can be programmed as a CTS RTS protocol by clearing both ENRX bit and RTS bit This protocol is a symmetric interface which provides flow control when both ports are sending and receiving data CTS Clear to send RTR Ready to receive CTS RTR Protocol Connection 17 2 DMA Transfer to from a serial port function DMA transfers to the serial port function as destination synchronized DMA transfers A new transfer is requested when the Transmit Holding Register is empty When the port is configured for DMA transmits the corresponding transmit interrupt is disabled regardless of the TXIE bit setting DMA transfers from the serial port function as source synchronized DMA transfers A new transfer is requested when the Receive Buffer contains valid data When the port is configured for DMA receives the corresponding receive interrupt is disabled regardless of the RXIE bit setting The DMA request is generated internaly when a DMA channd is being used for serial port transfers And the DRQO or DRQI are not active when a serial port DMA transfers Hardware handshaking may be used in conjunction with serial port DMA transfers RDC Semiconductor Co Rev 1 3 Subje
32. size is from F0000h to FFFFFh LB2 LB1 LBO Memory Block size Start address End Address 1 1 1 64k F0000h FFFFFh 1 1 0 128k E0000h FFFFFh 1 0 0 256k C0000h FFFFFh 0 0 0 512k 80000h FFFFFh Bit 11 8 Reserved Bit 7 DA Disable Address If the BHE ADEN pin is held high on the rising edge of RST then the DA bit is valid to enable disable the address phase of the AD bus If the BHE ADEN pin is held high on the rising edge of RST the AD bus always drive the address and data Set 1 Disable the address phase of the AD15 ADO bus cycle when UCS is asserted Set 0 Enable the address phase of the AD15 ADO bus cycle when UCS is asserted Bit 6 3 Reserved Bit 2 R2 Ready Mode This bit is used to configure the ready mode for UCS chip select Set 1 external ready is ignored Set 0 external ready is required Bit 1 0 R1 RO Wait State value When R2 is set to 0 it can inserted wait state into an access to the UCS memory area RDC Semiconductor Co Rev 1 3 Subject to change without notice 31 RDC oo 20 R1 RO 0 0 O wait state R1 RO 0 1 1 wait state R1 RO 1 0 2 wait state RLRO 11 3 wait state 12 2 LCS The lower 512k bytes 00000h 7FFFFh memory region chip selects The memory active range is programmable which has no default size on reset So the A2h register must be programmed first before to access the target memory range Th
33. will generate an interrupt Set 1 Enable the Interrupt Set 0 Disable the interrupt Bit 6 TMODE Transmit Mode Set 1 Enable the TX machines Set 1 Disable the TX machines Bit 5 RMODE Received Mode Set 1 Enable the RX machines Set 1 Disable the RX machines Bit 4 EVN Even Parity This bit is valid only when the PE bit is set Set 1 the even parity checking is enforced even number of 1s in frame Set 0 odd parity checking is enforced odd number of 1s in frame Bit 3 PE Parity Enable Set 1 Enable the parity checking Set 0 Disable the parity checking Bit 2 0 MODE Mode of Operation bit 2 bit 1 bit 0 MODE Data Bits Parity Bits Stop Bits 0 0 1 Mode 1 7 or 8 lorO 1 0 1 0 Mode 2 9 N A 1 0 1 1 Mode 3 8or9 lorO 1 1 0 0 Mode 4 7 N A 1 RDC Semiconductor Co Subject to change without notice 73 Rev 1 3 RDC vo 620 Serial Port O Status Register Offset 82h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 The Serial Port O Status Register provides information about the current status of the serial port 0 Bit 15 11 Reserved Bit 10 BRK1 Long Break Detected This bit should be reset by software When a long break is detected this bit will be set high Bit 9 BRKO Short Break Detected This bit should be reset by software When a short break is detected this bit will be set high Bit 8 RB8 Received Bit 8 This bit should be reset by software
34. 0 Master mode set 1 Slaved mode Bit 13 Reserved Bit 12 M IO Memory IO space At reset this bit is set to 0 and the PCB map start at FFOOh in I O space set 1 The peripheral control block PCB is located in memory space set 0 The PCB is located in I O space Bit 11 0 R19 R8 Relocation Address Bits The upper address bits of the PCB base address The lower eight bits default to 00h When the PCB is mapped to I O space the R19 R16 must be programmed to 0000b Offset F4h Processor Release Level Register Reset Value F9h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read only register that specifies the processor release version and RDC identify number Bit 15 8 Processor version 01h version A 02h version B 03h version C 04h version D Bit 7 0 RDC identify number D9h RDC Semiconductor Co Rev 1 3 Subject to change without notice 22 RDC io 620 9 System Clock Block PSEN FOh 15 enable disable Microprocessor Internal Clock xi CLKIN CLOCK or Divisior x2 CLKIN 2 CLK 2 CLK 128 fe CLKOUTA m CAD F0h 8 CLKIN 2 Select Divisor Select CAF FOh 9 F2 F0 FOh 2 F0h 0 S6 CLKDIV2 e CLKOUTB CBD F0h 10 CBF F0h 11 System Clock Power Save Control Register Offset FOh Reset Value 0000h Bit 15 PSEN Enable Power save Mode This bit is cleared by hardware when an external interrupt occurs This bit does not be changed when software interrupts INT instruction an
35. 1 0 2 0 1 1 3 1 0 0 5 1 0 1 7 1 4 0 9 l k 1 15 Bit 2 R2 Ready Mode This bit is configured to enable disable the wait states inserted for the PCS3 PCSO chip selects The R3 R1 RO bits determine the number of wait state to insert set to 1 external ready is ignored RDC Semiconductor Co Rev 1 3 Subject to change without notice 35 RDC vo 620 set to 0 external ready is required RDC Semiconductor Co Rev 1 3 Subject to change without notice 36 RDC 20 13 Interrupt Controller Unit There are 16 interrupt requests source connect to the controller 7 maskable interrupt pins INTO INT6 2 non maskable interrupts NMI pin WDT 7 internal unit request source Timer 0 1 2 DMA 0 1 Asynchronous serial port 0 1 Master Slave Mode Select FEH 14 N Timer0 1 2 o Interrupt REQ Interrupt Type Timer0 REQ T Execation m NMI N Unit Watchdog Timer INTO 0 Interrupt REQ Timerl REQ 1 Ww N o Timer2 REQ i a DMAO Interrupt REQ Interrupt INTS a ES Control Logic DMA1 Interrupt REQ INT6 a 16 Bit a INT2 a Register INT4 a R In Service Asynchronous Serial Port 0 Acknowledge E Register Asynchronous Serial Port 1 34 16 Bit Acknowledge to DMA Timer Serial port Unit lt Internal Address Data Bus gt I
36. 1 10 L 1 LEAVE Tear down stack frame 11001001 7 LAHF Load AH with flags 10011111 2 SAHF Store AH into flags 10011110 2 PUSHF Push flags 10011100 2 POPF Pop flags 10011101 11 ARITHMETIC INSTRUCTIONS ADD Add reg memory with register to either 000000dw mod reg r m 1 7 immediate to register memory 100000sw mod 000 r m data data if sw 01 1 8 immediate to accumulator 0000010w data data if w 1 1 RDC Semiconductor Co Rev 1 3 Subject to change without notice 81 R D RISC DSP Controller R8820 Function Format Clocks Notes ADC Add with carry reg memory with register to either 000100dw mod reg r m 1 7 immediate to register memory 100000sw mod 010 r m data data if sw 01 1 8 immediate to accumulator 0001010w data data if w 1 1 INC Increment register memory 1111111w mod 000 r m 1 8 register 01000 reg 1 SUB Subtract reg memory with register to either 001010dw mod reg r m 1 7 immediate from register memory 100000sw mod 101 r m data data if sw 01 1 8 immediate from accumulator 0001110w data data if w 1 1 SBB Subtract with borrow reg memory with register to either 0001 10dw mod reg r m 1 7 immediate from register memory 100000sw mod 011 r m 1 8 immediate from accumulator 0001110w data data if w 1 1 DEC Decrement reg
37. 14 DMA Unit 53 14 1 DMA Operation 53 14 2 External Request 59 14 3 Serial Port DMA Transfer 61 15 Timer Control Unit 62 15 1 Timer Counter Unit Output Mode 66 16 Watchdog Timer 68 17 Asynchronous Serial Port 70 17 1 Serial Port Flow Control 70 17 1 1 DCE DTE Protocol 70 17 1 2 CTS RTR Protocol 71 17 2 DMA Transfer to form a serial port function 71 17 3 The Asynchronous Modes description 12 18 PIO Unit 77 18 1 PIO Multi Function Pin list Table E 19 PSRAM Control Unit 80 20 Instruction Set Opcodes and Clock Cycle 81 20 1 R8000 Execution Timings
38. 2 CMC Complement carry 11110101 2 STC Set carry 11111001 2 CLD Clear direction 11111100 2 STD Set direction 11111101 2 CLI Clear interrupt 11111010 5 STI Set interrupt 11111011 5 HLT Halt 11110100 1 WAIT Wait 10011011 1 LOCK Bus lock prefix 11110000 1 ESC Math coprocessor escape 11011MMM mod PPP r m 1 NOP No operation 10010000 1 SEGMENT OVERRIDE PREFIX CS 00101110 2 SS 00110110 2 DS 00111110 2 ES 00100110 2 RDC Semiconductor Co Rev 1 3 Subject to change without notice 84 RDC ooo 620 20 1 R8820 Execution Timings The above instruction timing represent the minimum execution time in clock cycles for each instruction The timings given are based on the following assumptions 1 The opcode along with and data or displacement required for execution has been prefetched and resides in the instruction queue at the time is needed 2 No wait states or bus HOLDs occur 3 All word data is located on even address boundaries 4 One RISC micro operation uOP maps one cycle according the pipeline stages described below except the following case Pipeline Stages for single micro operation one cycle Fetch gt Decode gt lop_1 gt ALU gt WB For ALU function uOP Fetch gt Decode gt EA gt Access gt WB For Memory function uOP 4 1 Memory read uOP need 6 cycles for bus Pipeline stages for Memory read uOP 6 cycles Fetch
39. 2 DTR active delay 0 15 ns 23 DTR inactive delay 0 15 ns 24 Status active delay 0 15 ns 25 Status inactive delay 0 15 ns 26 UZI active delay 0 15 ns 21 UZI inactive delay 0 15 ns 1 T means a clock period time 2 All timing parameters are measured at 1 5V with 50 PF loading on CLKOUTA All output test conditions are with CL 50 pF RDC Semiconductor Co Rev 1 3 Subject to change without notice 87 RD O RISC DSP Controller CLKOUTA TW A19 A0 AD15 ADO ALE WHB WLB BHE ucs LCS PCSx MCSx DEN DTR UZI T1 T2 WRITE CYCLE T3 TA R8820 RDC Semiconductor Co Subject to change without notice 88 Rev 1 3 RDC ooo 620 No Description MIN MAX Unit 1 CLKOUTA high to A Address Valid 0 12 Ns 2 A address valid to WR low 1 5T 9 Ns 3 S6 active delay 0 15 ns 4 S6 inactive delay 0 15 ns 5 AD address Valid Delay 0 12 ns 6 Address Hold ns 7 ALE active delay 0 12 ns 8 ALE width T 10 ns 9 ALE inactive delay 0 12 ns 10 Address valid after ALE inactive 1 2T 5 ns 11 WR active delay 0 12 ns 12 WR pulse width 2T 10 ns 13 WR inactive delay 0 12 ns 14 WHB WLB active delay 0 15 ns 15 WHB WLB inactive delay 0 15 ns 16 BHE active delay 0 15 ns 17 BHE inactive delay 0 15 ns 18 CLKOUTA high to UCS
40. 66 FO System configuration register 23 5E Timer 1 Mode Control Register 63 E6 Watchdog timer control register 68 5C Timer 1 Maxcount Compare B Register 65 E4 Enable RCU Register 80 SA Timer 1 Maxcount Compare A Register 65 E2 Clock Prescaler Register 80 58 Timer 1 Count Register 65 EO Memory Partition Register 80 56 Timer 0 Mode Control Register 62 DA DMA 1 Control Register 56 54 Timer 0 Maxcount Compare B Register 63 D8 DMA 1 Transfer Count Register 58 52 Timer 0 Maxcount Compare A Register 63 D6 DMA 1 Destination Address High Register 58 50 Timer 0 Count Register 62 D4 DMA 1 Destination Address Low Register 59 44 Serial Port 0 interrupt control register 40 D2 DMA 1 Source Address High Register 59 42 Serial port 1 interrupt control register 4l DO DMA 1 Source Address Low Register 59 40 INT4 Control Register 42 CA DMA 0 Control Register 55 3E INT3 Control Register 42 C8 DMA 0 Transfer Count Register 55 3C INT2 Control Register 43 C6 DMA 0 Destination Address High Register 55 3A IINTI Control Register 43 C4 DMA 0 Destination Address Low Register 56 38 INTO Control Register 44 C2 DMA 0 Source Address High Register 56 36 DMA 1 INT6 Interrupt Control Register 45 CO DMA O0 Source Address Low Register 56 34 DMA O INTS Interrupt Control Register 45 A8 PCSand MCS Auxiliary Register 34 32 Timer Interrupt Control Register 46 A6 Midrange Memory Chip Select Register 33 30 Interrupt Status Register 47 A4 Peripheral Chip Select R
41. CS is programmed by software For ONCEO feature see UCS ONCEI description This pin incorporates weakly pull up register 59 60 PCS6 A2 PIO2 PCS5 A1 PIO3 Output Input Peripheral chip selects latched address bit For PCS feature these pins act low when the microcontroller accesses the fifth or sixth region of the peripheral memory I O or memory space The base address of PCS is programmable These pins assert with the AD address bus and are not float during bus hold For latched address bit feature These pins output the latched address A2 A1 when cleared the EX bit in the MCS and PCS auxiliary register The A2 Al retains previous latched data during bus hold 62 63 PCS3 RTS1 RTR 1 PIO19 Output Input Peripheral chip selects These pins act low when the microcontroller accesses the defined memory area of the RDC Semiconductor Co Subject to change without notice Rev 1 3 11 RD CE coco AQOOC me 65 PCS2 STSI ENRXI PIO18 peripheral memory block I O or memory address For I O 66 OG accessed the base address can be programmed in the region BOSE 00000h to OFFFFh PCSO PIO16 For memory address access the base address can be located in the 1M byte memory address region These pins assert with the multiplexed AD address bus and are not float during bus hold Interrupt Control Unit Interface Nonmaskable Interrupt The NMI is the highest pr
42. EN bit and the INH bit and EN bit must be in the same write Bit 14 INH Inhibit Bit This bit is allows selective updating the EN bit The INH bit must be set 1 during writing the EN bit and both the INH bit and EN bit must be in the same write This bit is not stored and is always read as 0 Bit 13 INT Interrupt Bit Set 1 A interrupt request is generated when the count register equals a maximum count If the timer is configured in dual max count mode an interrupt is generated each time the count reaches max count A or max count B Set 0 Timer 1 will not issue interrupt request Bit 12 RIU Register in Use Bit Set 1 The Maxcount Compare B register of timer 1 is being used RDC Semiconductor Co Rev 1 3 Subject to change without notice 63 RDC ooo 620 Set 0 The Maxcount Compare A register of timer 1 is being used Bit 11 6 Reserved Bit 5 MC Maximum Count Bit When the timer reaches its maximum count the MC bit will set to 1 by H W In dual maxcount mode this bit is set each time either Maxcount Compare A or Maxcount Compare B register is reached This bit is set regardless of the EN bit 66h 15 Bit 4 RTG Re trigger Bit This bit define the control function by the input signal of TMRINI pin When EXT 1 5Eh 2 this bit is ignored Set 1 Timer Count Register 58h counts internal events Reset the counting on every TMRINI input signal from low go high rising edge trigger Set 0 Low input holds the timer 1 Cou
43. Each one bank connects to the lower half of the data bus and contains the even addressed bytes A020 The other RDC Semiconductor Co Rev 1 3 Subject to change without notice 26 RDC 620 bank connects to the upper half of the data bus and contains odd addressed bytes AO 1 AO and BHE determine whether one bank or both banks participate in the data transfer 11 3 Wait States Wait states extend the data phase of the bus cycle The ARDY or SRDY input with high level will insert wait states To avoid wait states ARDY and SRDY must be low within a specified setup time prior to phase 2 of T2 To insert wait states ARDY or SRDY must drive high within a specified setup time prior to phase 2 of T2 or phase of T3 If the ARDY is not used tie this pin low to yield control to SRDY If the SRDY is not used tie this pin low to yield control to ARDY The SRD Y PIO6 is multi function pin and SRDY internally pull down when this pin is programmed for PIO function Case 1 TW TW TW T4 Case 2 T3 TW TW T4 Case 3 T2 T3 TW T4 Case 4 Ti T2 T3 T4 CLKOUTA ARDY Normally Not Ready System ARDY Normally Ready System Asynchronous Ready Waveforms Case 1 TW TW TW T4 Case 2 T3 TW TW T4 Case 3 T2 T3 TW T4 Case 4 T1 T2 T3 T4 1 1 I 1 1 I I b ll ll CLKOUTA SRDY Normally Not Ready System SRDY Normally Ready System Synchronous Ready Waveforms RDC Semiconductor Co Rev 1 3 Subject to change without notice 27 RDC oo
44. RDC BBD R8820 16 Bit RISC Microcontroller User s Manual R DC RISC DSP Controller RDC Semiconductor Co Ltd http www rdc com tw Tel 886 3 583 2666 Fax 886 3 583 2688 RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC BBD Contents page 1 Features 4 2 Block Diagram 4 3 Pin Configuration 5 4 Pin Description 8 5 Basic Application System Block Y Read Write timing Diagram 14 6 Oscillator Characteristics 17 7 Execution Unit 18 7 1 General Register 18 7 2 Segment Register 18 7 3 Instruction Pointer and Status Flags Register 19 7 4 Address Generation 20 8 Peripheral Control Block Register 21 9 System Clock B
45. T pin To reset the processor this pin should be held low for at least seven oscillator periods The Reset Status Figure shows the status of the RST pin and others relation pins When RST from low go high the state of input pin with weakly pull up or pull down will be latched and each pin will perform the individual function The AD15 ADO will be latched into the register F h UCS ONCEI LCS ONCEO will enter ONCE mode All of the pins will floating except X1 X2 when with pull low resisters The input clock will divide by 2 when S6 CLKDIV2 with pull low resister The AD15 ADO bus will not drive the address phase during UCS LCS cycle if BHE ADEN with pull low resister RDC Semiconductor Co Rev 1 3 Subject to change without notice 24 RDC vo 620 CLKOUTA Reset Status Reset Configuration Register Offset F6h Reset Value AD15 ADO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 0 RC Reset Configuration AD15 ADO The AD15 to ADO must with weakly pull up or pull down resistors to correspond the contents when AD15 ADO be latched into this register during the RST pin from low go high And the value of the reset configuration register provides the system information when software read this register This register is read only and the contents remain valid until the next processor reset RDC Semiconductor Co Rev 1 3 Subject to change without notice 25 RDC 620 11 Bus Interface Unit The bu
46. Watchdog Timer Bit 14 WRST Watchdog Reset Set 1 WDT generates a system reset when WDT timeout count is reached Set 0 WDT generates a NMI interrupt when WDT timeout count is reached if the NMIFLAG bit is 0 If the NMIFLAG bit is 1 the WDT will generate a system reset when timeout Bit 13 RSTFLAG Reset Flag When watchdog timer reset event has occurred hardware will set this bit to 1 This bit will be cleared by any keyed sequence write to this register or external reset This bit is O after an external reset or 1 after watchdog timer reset Bit 12 NMIFLAG NMI Flag After WDT generates a NMI interrupt this bit will be set to 1 by H W This bit will be cleared by any keyed sequence write to this register Bit 11 8 Reserved Bit 7 0 COUNT Timeout Count The COUNT setting determines the duration of the watchdog timer timeout interval Exponent a The duration equation Duration 2 Frequency b The Exponent of the COUNT setting Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Exponent 0 0 0 0 0 0 0 0 N A X X X X X X X X 10 X X Xx X x x 1 0 20 x x x x x 1 0 0 21 RDC Semiconductor Co Rev 1 3 Subject to change without notice 68 R D RISC DSP Controller R8820 x x x x 1 0 0 0 22 x x x 1 0 0 0 0 23 x x 1 0 0 0 0 0 24 x 1 0 0 0 0 0 0 25 1 0 0 0 0 0 0 0 26 c Watchdog timer Duration reference table Fr
47. XD0 PIO23 TXD0 PIO22 RTSO RTRO P1020 BHE ADEN O 100 CTSO ENRX0 PIO21 R8820 Microcontroller CLKOUTA CLKOUTB GND A19 PIO9 A18 PIO8 VCC A17 PIO7 A16 A15 A14 A13 A12 A11 A10 A9 A8 31 A7 32 A6 33 A5 EJ 34 A4 35 A3 36 A2 C 37 vec 38 Al EJ 39 AO 40 GND EE 41 WHB EE 42 WLB E 43 NMI 47 HLDA E 44 HOLD EE 45 SRDY PIO6 CT 46 DT R P104 CT 48 81 AD9 82 AD2 DEN PIO5 ET 49 MCSO PIO14 ET 50 DRQO INT5 PIO12 DRQ1 INT6 PIO13 TMRINO PIO11 TMROUTO PIO10 TMROUT1 PIO1 TMRIN1 PIOO RST GND MCS3 RFSH PIO25 MCS2 P1024 vec PCSO PIO16 PCS1 PIO17 GND PCS2 CTS1 ENRX1 PIO18 PCS3 RTS1 RTR1 PIO19 vec PCS5 A1 PIO3 PCS6 A2 PIO2 LCS ONCEO UCS ONCE1 INTO INT1 SELECT INT2 INTAO PIO31 INT3 INTA1 IRQ INT4 PI030 MCS1 PI015 RDC Semiconductor Co Subject to change without notice Rev 1 3 R8820 RISC DSP Controller LQFP RD o n s ood a q wo o 001 o O H HHOR A am OR HR ps NS dD Mos N SRESER mad EORB SERB SHBESea8aaeaeneags vd r4 AISI R 5 RHR O x d 4 amp 4 amp dd N MN nd O oo N M N nd O oo N M N HH gt e pe TM o wo amp N 10 ooa in OWI IVINI INI L ziv I OId OVINI ZINI LI erv LomTSS TINI LL viv OLNI __ L1 ST Y THONO son C 9T OMONO Ss9T C Lora L1v coid z
48. aches 0 Unsynchronized DMA transfer is always terminated when the DMA transfer count register reaches 0 regardless the setting of this bit Bit 8 INT Interrupt Set 1 DMA unit generates an interrupt request when complete the transfer count The TC bit must set to 1 to generate an interrupt Bit 7 6 SYN1 SYNO Synchronization Type Selection SYN1 SYNO Synchronization Type 0 0 Unsynchronized O0 1 Source synchronized RDC Semiconductor Co Rev 1 3 Subject to change without notice 57 RDC ooo 620 L490 Destination synchronized 1 1 Reserved Bit 5 P Priority Set 1 It selects high priority for this channel when both DMA 0 and DMA 1 are transfer in same time Bit 4 TDRQ Timer Enable Disable Request Set 1 Enable the DMA requests from timer 2 Set 0 Disable the DMA requests from timer 2 Bit 3 Reserved Bit 2 CHG Changed Start Bit This bit must set to 1 when will modify the ST bit Bit 1 ST Start Stop DMA channel Set 1 Start the DMA channel Set 0 Stop the DMA channel Bit0 B W Byte Word Select Set 1 The address is incremented or decremented by 2 after each transfer Set O The address is incremented or decremented by 1 after each transfer DMA Transfer Count Register Offset D8h DMA1 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO DMA 1 transfer Count The value of this register is decremented by 1 after each transfer DMA Destination Address Hi
49. ask Set 1 Mask the interrupt source of the Timer 2 Set 0 Enable the Timer 2 interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h INTO Control Register Offset 38h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pres En emu c cru sk pre ems eno Master Mode Bit 15 8 Reserved Bit 7 ETM Edge trigger enable When this bit set to 1 and Bit 4 set to 0 interrupt is triggered by low go high edge The low go high edge will be latched one level till this interrupt is been serviced Bit 6 SFNM Special Fully Nested Mode Set 1 Enable the special fully nested mode of INTO Bit 5 C Cascade Mode Set this bit to 1 to enable the cascade mode for INT1 or INTO Bit 4 LTM Level Triggered Mode Set 1 Interrupt is triggered by high active level Set 0 Interrupt is triggered by low go high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of the INTO Set 0 Enable the INTO interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Slave Mode For Timer 1 interrupt control register reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the timer 1 RDC Semiconductor Co Rev 1 3 Subject to change without notice 44 RDC 620 Set 0 Enable the timer 1 interrupt Bit 2 0 PR Interrupt Priority These bits setting for pr
50. ct to change without notice 7 RDC ve 620 17 3 The Asynchronous Modes description There are 4 modes operation in the asynchronous serial port Model Mode 1 is the 8 bit asynchronous communications mode Each frame consists of a start bit eight data bits and a stop bit when parity is used the eighth data bit becomes the parity bit Mode 2 Mode 2 is used together with Mode 3 for multiprocessor communications over a common serial link In mode 2 the RX machine will not complete a reception unless the ninth data bit is a one Any character received with the ninth bit equal to zero is ignored No flags are set no interrupts occur and no data is transferred to Receive Data Register In mode 3 characters are received regardless of the state of the ninth data bit Mode 3 Mode 3 is the 9 bit asynchronous communications mode Mode 3 is the same as mode 1 except that a frame contains nine data bits The ninth data bit becomes the parity bit when the parity feature is enabled Mode 4 Mode 4 is the 7 bit asynchronous communications mode Each frame consists of a start bit seven data bits and a stop bit Parity bit is not available in mode 4 Serial Port 0 Contrl Register Offset 80h Reset Value 0000h 15 7 4 3 14 13 12 11 10 9 8 6 5 2 1 0 Ww a a a E a Bit 15 13 DMA DMA Control Field These bits configure the serial port for use with DMA transfers DMA control bits Bit 15 bit 14 bit 13 b Receive Transmit 0 0 0
51. d exceptions occurs Set 1 enable power save mode and divides the internal operating clock by the value in F2 F0 Bit14 MCSBIT MCSO control bit Set to 0 The MCSO operate normally Set to 1 MCSO is active over the entire MCSx range Bit13 12 Reserved Bit 11 CBF CLKOUTB Output Frequency selection Set 1 CLKOUTB output frequency is same as crystal input frequency Set 0 CLKOUTB output frequency is from the clock divisor which frequency is same as that of microprocessor internal clock Bit 10 CBD CLKOUTB Drive Disable Set 1 Disable the CLKOUTB This pin will be three state Set 0 Enable the CLKOUTB Bit 9 CAF CLKOUTA Output Frequency selection Set 1 CLKOUTA output frequency is same as crystal input frequency Set 0 CLKOUTB output frequency is from the clock divisor which frequency is same as that of microprocessor RDC Semiconductor Co Rev 1 3 Subject to change without notice 23 RDC io 620 internal clock Bit 8 CAD CLKOUTA Drive Disable Set 1 Disable the CLKOUTA This pin will be three state Set 0 Enable the CLKOUTA Bit 7 3 Reserved Bit 2 0 F2 F0 Clock Divisor Select F2 Fl F0 Divider Factor 0 0 0 Divide by 1 0 0 1 Divide by 2 0 1 0 Divide by 4 0 tI 1 Divide by 8 1 0 0 Divide by 16 1 0 1 Divide by 32 1 1 0 Divide by 64 L 1 1 Divide by 128 10 Reset Processor initialization is accomplished with activation of the RS
52. ddress process Refer the STD and CLD instructions for how to set and clear the DF flag Bit 9 IF Interrupt Enable Flag Refer the STI and CLI instructions for how to set and clear the IF flag Set to 1 The CPU enables the maskable interrupt request RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC 620 Set to O The CPU disables the maskable interrupt request Bit 8 TF Trace Flag Set to enable single step mode for debugging Clear to disable the single step mode If an application program sets the TF flag using POPF or IRET instruction a debug exception is generated after the instruction The CPU automatically generates an interrupt after each instruction that follows the POPF or IRET instruction Bit 7 SF Sign Flag If this flag is set the high order bit of the result of an operation is 1 indicating it is negative Bit 6 ZF Zero Flag The result of operation is zero this flag is set Bit 5 Reserved Bit 4 AF Auxiliary Flag If this flag is set there has been a carry from the low nibble to the high or a borrow from the high nibble to the low nibble of the AL general purpose register Used in BCD operation Bit 3 Reserved Bit 2 PF Parity Flag The result of low order 8 bits operation has even parity this flag is set Bit 1 Reserved Bit 0 CF Carry Flag If CFis set there has been a carry out or a borrow into the high order bit of the instruction result 7 4 Address generation The Execut
53. e LCS pin is not active on reset but any read or write access to the A2h register activates this pin Low Memory Chip Select Register Offset A2h Reset Value 11 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Bit 15 Reserved Bit 14 12 UB2 UBO Memory block size selection for LCS chip select pin The LCS chip select pin active region can be configured by the UB2 UBO The LCS pin is not active on reset but any read or write access to the A2h LMCS register activates this pin UB2 UB1 UBO Memory Block size Start address End Address 0 0 0 64k 00000h OFFFFh 0 0 1 128k 00000h LFFFFh 0 1 1 256k 00000h 3FFFFh 1 1 1 512k 00000h 7FFFFh Bit 11 8 Reserved Bit 7 DA Disable Address If the BHE ADEN pin is held high on the rising edge of RST then the DA bit is valid to enable disable the address phase of the AD bus If the BHE ADEN pin is held low on the rising edge of RST the AD bus always drive the address and data Set 1 Disable the address phase of the AD15 ADO bus cycle when LCS is asserted Set O Enable the address phase of the AD15 ADO bus cycle when LCS is asserted Bit 6 PSE PSRAM Mode Enable This bit is used to enable PSRAM support for the LCS chip select memory space The refresh control unit registers EOh E2h E4h must be configured for auto refresh before PSRAM support is enabled PSE set to 1 PSRAM support is enable PSE set to 0 PSRAM support i
54. e programmable These pins are floated during a bus hold or reset DMA U nit Interface DMA request These pins are asserted high by an external device when the device is ready for DMA channel or channel O to perform a transfer These pins are level triggered and internally synchronized The DRQ signals must remain act 76 DRQI INT6 PIO13 oO until finish serviced and are not latched T DRQO INTS PIO12 P Pu For INT6 INTS function When the DMA function is not being used INT6 INT5 can be used as an additional external interrupt request And they share the corresponding interrupt type and register control bits The INT6 5 are edge triggered only and must be hold until the interrupt is acknowledged Notes 1 When enable the PIO Data register there are 32 MUX definition pins can be as a PIO pin For example the DRD1 PIO13 pin76 can be as a PIO13 when enable the PIO Data reg ister 2 The PIO status during Power On reset PIO1 PIO10 PIO22 PIO23 are input with pull down PIO4 to PIO9 are normal operation and the others are input with pull up RDC Semiconductor Co Subject to change without notice Rev 1 3 RDC o_o 5 Basic Application System Block amp Read Write timing Diagram Flash ROM Data 16 Address l BASIC APPLICATION SYSTEM BLOCK A Flash ROM High Byte Low Byte Level Converter Converter Timer0 1 INTx DMA i BASIC APPLICATION SYSTEM BLOCK B
55. egister 35 2E Interrupt Request Register 47 A2 Low Memory Chip Select Register 32 2C interrupt In service Register 48 AO Upper Memory Chip Select Register 31 2A InterruptPriority Mask Register 49 88 Serial Port O Baud Rate Divisor Register 75 28 interrupt Mask Register 50 86 Serial Port O Receive Register 75 26 interrupt Poll Status Register 51 84 Serial Port 0 Transmit Register 74 24 interrupt Poll Register 51 82 Serial Port 0 Status Register 74 22 Interrupt End of Interrupt 52 80 Serial Port O Control Register 72 20 interrupt Vector Register 52 7A PIO Data 1 Register 78 18 Serial port 1 baud rate divisor 76 78 _ PIO Direction 1 Register 78 16 Serial port 1 receive register 76 76 PIO Mode 1 Register 78 14 Serial port 1 transmit register 76 74 PIO Data 0 Register 79 12 Serial port 1 status register 75 72 PIO Direction O Register 79 10 Serial port 1 control register 75 RDC Semiconductor Co Rev 1 3 Subject to change without notice 2 RDC ooo 620 Peripheral Control Block Relocation Register Offset FEh Reset Value 20FFh 14 1 11 10 9 8 7 6 5 4 3 2 1 0 15 3 12 The peripheral control block is mapped into either memory or I O space by programming this register When the other chip selects PCSx or MCSx are programmed to zero wait states and ignore the external ready the PCSx or MCSx can overlap the control block Bit 15 Reserved Bit 14 S M Slave Master Configures the interrupt controller set
56. emory chip selects which are programmed through A4h and ASh register to define these pins RDC Semiconductor Co Rev 1 3 Subject to change without notice 34 RDC vo 620 The base address memory block can be located anywhere within the 1M bytes memory space exclusive of the areas associated with the MCS4 LCS and MCS chip elects If the chip selects are mapped to I O space the access range is 64k bytes PCS6 PCSS can be configured from O wait state to 3 wait states PCS3 PCSO can be configured from 0 wait state to 15 wait states Peripheral Chip Select Register Offset A4h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 7 BA19 BA11 Base Address BA19 BA11 correspond to bit 19 11 of the 1M bytes 20 bits programmable base address of the PCS chip select block When the PCS chip selects are mapped to I O space BA19 BA16 must be wrote to 0000b because the I O address bus in only 64K bytes 16 bits wide PCSx address range PCSO Base Address Base Address 255 PCSI Base Address 256 Base Address 511 PCS2 Base Address 512 Base Address 767 PCS3 Base Address 768 Base Address 1023 PCS4 Base Address 1280 Base Address 1535 PCS5 Base Address 1536 Base Address 1791 Bit 6 4 Reserved Bit 3 R3 Bit 1 0 R1 RO Wait State Value The R3 R1 RO determines the number of wait states inserted into a PCS3 PCSO access R3 R1 RO Wait States 0 0 0 0 0 0 1 1 0
57. equency Exponent 10 20 21 22 23 24 25 26 20 MHz 51lus 52ms 104 ms 209 ms 419 ms 838ms 1 67s 3 35 s 25 MHz 40us 41ms 83ms 167ms 335 ms 671ms 1 34s 12 68 s 33 MHz 30us 31ms 62ms 125 ms 251 ms 503ms 1 00s 2 01 s 40 MHz 25us 26ms 52ms 104 ms 209 ms 419ms 838 ms 1 67 s 50 MHz 20 5 us 21 ms 41 9 ms 83 9ms 167 8 ms 335 5 ms 671 ms 1 34 s RDC Semiconductor Co Rev 1 3 Subject to change without notice 69 RDC 2 s Reo 17 Asynchronous Serial Port R8820 has two asynchronous serial ports which provide the TXD RXD pins for the full duplex bi directional data transfer and with handshaking signals CTS ENRX RTS RTR The serial ports support 9 bit 8 bit or 7 bit data transfer odd parity even parity or no parity 1 stop bits Error detection DMA transfers through the serial port Multi drop protocol 9 bit support Double buffers for transmit and receive The receive transmit clock is based on the microprocessor clock The serial port can be used in power saved mode but the transfer rate must be adjusted to correctly reflect the new internal operating frequency Software is programmed through the registers 80h 82h 84h 86h 88h for port 0 10h 12h 14h 16h 18h for port 1 to configure the asynchronous serial port Internal Address Data Bus Transmit TED Shift Regoster Receive Shift Register Interrupt Request RTS ENRX CTS e Control Re
58. esister during reset The AD _ bus is in high impedance state during bus hold or reset condition and this bus also be used to load system configuration information with pull up or pull Low resister into the RESCON register when the reset input from low go high 42 Output Write high byte This pin indicates the high byte data AD15 AD8 on the bus is to be written to a memory or I O device WHB is the logic OR of BHE WR and ADO inverting This pin is floating during reset or bus hold 43 Output Write low byte This pin indicates the low byte data AD7 ADO on the bus is to be written to a memory or I O device WLB is the logic OR of BHE WR and ADO This pin is floating during reset or bus hold 44 HLDA Output Bus hold acknowledge Active high The microcontroller will issue a HLDA in response to a HOLD request by external bus master at the end of T4 or Ti When the microcontroller is in hold status HLDA is high the AD15 ADO A19 AO WR RD DEN S0 S1 S6 BHE DT R WHB and WLB are floating and the UCS LCS PCS6 PCS5 MCS3 MCSO and PCS3 PCSO will be drive high After HOLD is detected as being low the microcontroller will lower HLDA 45 HOLD Input Bus Hold request Active high This pin indicates that another bus master is requesting the local bus 46 SRDY PIO6 Input Output Synchronous ready This pin performs the microcontroller that the address memor
59. et 1 The destination address is in memory space Set 0 The destination address is in I O space Bit 14 DDEC Destination Decrement Set 1 The destination address is automatically decrement after each transfer The B W bit 0 bit determines the decrement value which is by 1 or 2 When both DDEC and DINC bits are set to 1 the address remains constant Set 0 Disable the decrement function Bit 13 DINC Destination Increment Set 1 The destination address is automatically increment after each transfer The B W bit 0 bit determines the increment value which is by 1 or 2 Set 0 Disable the decrement function Bit 12 SM IO Source Address Space Select Set 1 The Source address is in memory space Set 0 The Source address is in I O space Bit 11 SDEC Source Decrement Set 1 The Source address is automatically decrement after each transfer The B W bit 0 bit determines the decrement value which is by 1 or 2 When both SDEC and SINC bits are set to 1 the address remains constant Set 0 Disable the decrement function Bit 10 SINC Source Increment Set 1 The Source address is automatically increment after each transfer The B W bit 0 bit determines the increment value which is by 1 or 2 Set 0 Disable the decrement function Bit 9 TC Terminal Count Set 1 The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0 Set 0 The synchronized DMA transfer is terminated when the DMA transfer count register re
60. fset 86h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 8 Reserved Bit 7 0 RDATA Received DATA The RDR bit should be read as 1 before read the RDATA register to avoid reading invalid data Serial Port 0 Baud Rate Divisor Register Offset 88h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAVDDIV Bit 15 0 BAUDDIV Baud Rate Divisor The general formula for baud rate divisor is Baud Rate Microprocessor Clock 16 x BAUDIV For example The Microprocessor clock is 22 1184MHz and the BBDIV 5 Decimal the baud rate of serial port is 115 2k Serial Port 1 Contrl Register Offset 10h Reset Value 0000h 7 6 4 3 15 14 13 12 11 10 9 8 5 2 1 0 Ww Q Q Q E a These bits definition are same as the bits definition of Register 80h Serial Port 1 Status Register Offset 12h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 These bits definition are same as the bits definition of Register 82h RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC coso Serial Port 1 Transmit Register Offset 14h Reset Value 7 6 5 4 3 2 1 0 Reserved TDATA These bits definition are same as the bits definition of Register 84h al x AR w ak N al a En o co Serial Port 1 Receive Register Offset 16h Reset Value 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 These bits definition are same as the bits definition of Register 86h Serial P
61. ge without notice RDC ooo 620 19 PSRAM Control Unit The PSRAM interface is provided by the R8820 and the refresh control unit automatically generates refresh bus cycles The refresh control unit uses the internal microprocessor clock as a operating source clock if the power saved mode is enabled the refresh control unit must be programmed to reflect the new clock rate Software programs the registers EO E2 E4 to control the refresh control unit operation Memory Partition Register Offset EOh Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lee Jo fojofolofolofojo Bit 15 9 M6 MO Refresh Base M6 MO map to A19 A13 of the 20 bit memory refresh address Bit 8 0 Reserved Clock Prescaler Register Offset E2h Reset Value 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 RC8 RCO 9 Bit 15 9 Reserved Bit 8 0 RC8 RCO Refresh Counter Reload Value Enable RCU Register Offset E4h Reset Value 0000h 15 14 183 12 11 10 8 7 6 5 4 3 2 1 0 E T8 TO 9 Bit 15 E Enable RCU Set 1 Enable the refresh counter unit Set 0 Disable the refresh counter unit Bit 14 9 Reserved Bit 8 0 T8 T0 Refresh Count Read only bits and these bits present value of the down counter which triggers refresh requests RDC Semiconductor Co Rev 1 3 Subject to change without notice 80
62. generally contains program variables The DS register initialize to OOOOH SS Stack Segment The SS register points to the current stack segment which is for all stack operations such as pushes and pops The stack segment is used for temporary space The SS register initialize to 0000H ES Extra Segment The ES register points to the current extra segment which is typically for data storage such as large string operations and large data structures The DS register initialize to 0000H 15 8 7 0 Code Segment Stack Segment Extra Segment SEGMENT REGISTERS 7 3 Instruction Pointer and Status Flags Register IP Instruction Pointer The IP is a 16 bit register and it contains the offset of the next instruction to be fetched Software can not to direct access the IP register and this register is updated by the Bus Interface Unit It can change be saved or be restored as a result of program execution The IP register initialize to 0000H and the CS IP starting execution address is at OFFFFOH Processor Status Flags Registers FLAGS Reset Value 0000h 1 10 9 8 7 6 15 14 13 12 5 4 3 2 1 0 These flags reflect the status after the Execution Unit is executed Bit 15 12 Reserved Bit 11 OF Overflow Flag An arithmetic overflow has occurred this flag will be set Bit 10 DF Direction Flag If this flag is set the string instructions are increment address process If DF is cleared the string instructions are decrement a
63. gh Register Offset D6h DMA1 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 4 Reserved Bit 3 0 DDA19 DDA16 High DMA 1 Destination Address These bits are map to A19 A16 during a DMA transfer when the destination address is in memory space or I O space If the destination address is in I O space 64Kbytes these bits must be programmed to 0000b RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC io 620 DMA Destination Address Low Register Offset D4h DMA1 Reset Value a a A E si N A A zx o co N D al A wo N ag o DDA15 DDAO Bit 15 0 DDA15 DDA0 Low DMA 1 Destination Address These bits are mapped to A15 AO during a DMA transfer The value of DDA19 DDAO b will increment or decrement by 2 after each DMA transfer DMA Source Address High Register Offset D2h DMA1 Reset Value 3 2 1 0 Reserved DSA19 DSA16 Bit 15 4 Reserved Bit 3 0 DSA19 DSA16 High DMA 1 Source Address These bits are mapped to A19 A16 during a DMA transfer when the zx a A ot wo zk N oy zu zs oO co N D al A source address is in memory space or I O space If the source address is in I O space 64 Kbytes these bits must be programmed to 0000b DMA Source Address Low Register Offset DOh DMA1 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSA15 DSAO Bit 15 0 DSA15 DSA0 Low DMA 1 Source Address These bits are ma
64. gister 80h 10h Control Status Register 82h 12h Logic Bi aud Rate Divisor Register 88h 18h Serial Port Block Diagram 17 1 Serial Port Flow Control The two serial ports provided with two data pins RXD and TXD and two flow control signals RTS RTR Hardware flow control is enabled when the FC bit in the Serial Port control Register is set And the flow control signals are configured by software to support several different protocols 17 1 1 DCE DTE Protocol The R8820 can be as a DCE Data Communication Equipment or as a DTE Data Terminal Equipment This protocol provides flow control where one serial port is receiving data and other serial port is sending data To implement the DCE device the ENRX bit should be set and the RTS bit should be cleared for the associated serial port To implement the DTE device the ENRX bit should be cleared and the RTS bit should be set for the associated serial port The ENRX bit and RTS bit are in the register F2h The DCE DTE protocol is asymmetric interface since the DTE device can not signal the DCE device that is ready to receive RDC Semiconductor Co Rev 1 3 Subject to change without notice 70 RDC h 2 Reo data and the DCE can not send the request to send signal RTS Request to send CTS Clear to send RTR Ready to receive ENRX Enable receiver request DCE DTE Protocol Connection The DCE DTE protocol communication step a DTE
65. hibit Bit This bit is allows selective updating the EN bit The INH bit must be set 1 during writing the EN bit and both the INH bit and EN bit must be in the same write This bit is not stored and is always read as 0 Bit 13 INT Interrupt Bit RDC Semiconductor Co Rev 1 3 Subject to change without notice RD 620 Set 1 A interrupt request is generated when the count register equals a maximum count Set 0 Timer 2 will not issue interrupt request Bit 12 6 Reserved Bit 5 MC Maximum Count Bit When the timer reaches its maximum count the MC bit will set to 1 by H W This bit is set regardless of the EN bit 66h 15 Bit 4 1 Reserved Bit 0 COUNT Continuous Mode Bit Set 1 Timer is continuously running when timer reaches the maximum count Set 0 The EN bit 66h 15 is cleared and the timer is hold after each timer count reaches the maximum count Timer 2 Count Register Offset 60h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TCO Timer 2 Count Value This register contains the current count of timer 2 The count is incremented by one every four internal processor clocks Timer 2 Maxcount Compare A Register Offset 62h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC15 TCO Bit 15 0 TC15 TC0 Timer 2 Compare A Value 15 1 Timer Counter Unit Output Mode Timers O and 1 can use one maximum count value or two maximum count value Timer 2 can use only one
66. ion Unit generates a 20 bit physical address to Bus Interface Unit by the Address Generation Memory is organized in sets of segments Each segment contains a 16 bits value Memory is addressed using a two component address that consists of a 16 bit segment and 16 bit offset The Physical Address Generation figure describes how the logical address transfers to the physical address Shift left 4 bits Segment Base Logical Address Offset Physical Address TO Memory Physical Address Generation RDC Semiconductor Co Rev 1 3 Subject to change without notice 20 RDC ooo 620 8 Peripheral Control Block Register The peripheral control block can be mapped into either memory or I O space which is to program the FEh register And it starts at FFOOh in I O space when reset the microprocessor The following table is the definition of all the peripheral Control Block Register and the detail description will arrange on the relation Block Unit pia Register Name Page m Register Name Page FE Peripheral Control Block Relocation Register 22 70 PIO Mode 0 Register 79 F6 Reset Configuration Register 25 66 Timer 2 Mode Control Register 65 F4 Processor Release Level Register 22 62 Timer 2 Maxcount Compare A Register 66 F2 Auxiliary configuration Register 30 60 Timer 2 Count Register
67. iority hardware interrupt and is nonmaskable When this pin is asserted NMI transition from low to high the microcontroller 47 NMI Input always transfers the address bus to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table The NMI pin must be asserted for at least one CLKOUTA period to guarantee that the interrupt is recognized Maskable interrupt request 4 Act high This pin indicates that an interrupt request has occurred The microcontroller will jump to the INT4 address vector to execute the service routine 52 INT4 PIO30 Input Output if the INT4 is enable The interrupt input can be configured to be either edge or level triggered The requesting device must holt the INT4 until the request is acknowledged to guarantee interrupt recognition Maskable interrupt request 3 interrupt acknowledge 1 slave interrupt request For INT3 feature except the difference interrupt line and interrupt address vector the function of INT3 is the same as INT4 53 INT3 INTA1 IRQ Input Output For INTAI feature in cascade mode or special fully nested mode this pin corresponds the INTI For IRQ feature when the microcontroller is as a slave device this pin issues an interrupt request to the master interrupt controller Maskable interrupt request 2 interrupt acknowledge 0 For INT2 feature except the difference interrupt line and interrupt 54 INT2 INTAO PIO31 Input Output address vector the functi
68. iority selection is same as bit 2 0 of the register 44h DMA 1 INT6 Interrupt Control Register Offset 36h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lojejeo eojo oje o eo ojo Jus rns en pre Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 1 controller Set 0 Enable the DMA controller interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Slave Mode reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 1 controller Set 0 Enable the DMA controller interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h DMA O INT5 Interrupt Control Register Offset 34h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LolololofofoJofojoJo o us ere ems ero Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 0 controller Set 0 Enable the DMA 0 controller interrupt RDC Semiconductor Co Rev 1 3 Subject to change without notice 45 R D RISC DSP Controller Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Slave Mode reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the DMA 0 controller Set
69. is sampled on the rising edge of RST 97 UZI PIO26 Output Input Upper zero indicate This pin is the logical OR of the inverted A19 A16 It asserts in the T1 and is held throughout the cycle Chip Select Unit Interface MCSO PIO14 MCSI PIO15 MCS2 PIO24 MCS3 RFSH PIO25 Output Input Midrange memory chip selects For MCS feature these pins are active low when enable the MMCS register to access a memory The address ranges are programmable MCS3 MCSO are held high during bus hold When programming LMCS register pin69 is as a RFSH pin to auto refresh the PSAM 57 UCS ONCEI Output Input Upper memory chip select ONCE mode request 1 For UCS feature this pin acts low when system accesses the defined portion memory block of the upper 512K bytes 80000h FFFFFh memory region UCS default acted address region is from F0000h to FFFFFh after power on reset The address range acting UCS is programmed by software For ONCEI feature If ONCEO and ONCEI are sampled low on the rising edge of RST The microcontroller enters ONCE mode In ONCE mode all pins are high impedance This pin incorporates weakly pull up resistor 58 LCS ONCEO Output Input Lower memory chip selectONCE mode request 0 For LCS feature this pin acts low when the microcontroller accesses the defined portion memory block of the lower 512K 00000h 7FFFFh memory region The address range acting L
70. ister memory 1111111w mod 001 r m 1 8 register 01001 reg 1 NEG Change sign register memory 1111011w mod reg r m 1 8 CMP Compare register memory with register 0011101w mod reg r m 1 7 register with register memory 0011100w mod reg r m 1 7 immediate with register memory 100000sw mod 111 r m data data if sw 01 1 7 immediate with accumulator 0011110w data data if w 1 1 MUL multiply unsigned 1111011w mod 100 r m register byte 13 register word 21 memory byte 18 memory word 26 IMUL Integer multiply signed 1111011w mod 101 r m register byte 16 register word 24 memory byte 21 memory word 29 register memory multiply immediate signed 011010s1 mod reg r m data data if s 0 23 28 DIV Divide unsigned 1111011W mod 110 r m register byte 18 register word 26 memory byte 23 memory word 31 IDIV Integer divide signed 1111011w mod 111 r m register byte 18 register word 26 memory byte 23 memory word 31 AAS ASCII adjust for subtraction 00111111 3 DAS Decimal adjust for subtraction 00101111 2 AAA ASCII adjust for addition 00110111 3 DAA Decimal adjust for addition 00100111 2 AAD ASCII adjust for divide 11010101 00001010 14 AAM ASCI adjust for multiply 11010100 00001010 15 CBW Corrvert byte to word 10011000 2 CWD Convert word to double word 10011001 2 RDC Semiconductor Co Rev 1 3 Subject to change without notice 82 RDC 20
71. l port DMA transfer When a DMA channel is in use by a serial port the corresponding external DMA request signal is deactivated For DMA to the serial port the DMA channel should be configured as destination synchronized For DMA from the serial port the DMA channel should be configured as source synchronized RDC Semiconductor Co Rev 1 3 Subject to change without notice 61 R D RISC DSP Controller 15 Timer Control Unit TMRIN1 TMRINO Microprocessor Clock 50h Timer 0 Count Register 52h 54h Timer0 Maxcount Compare Register PE 58h Timer 1 Compare Register paid pid Counter Element amp Control Timer2 5Ah 5Ch Timer 1 Maxcount Compare Register 60h Timer 2 count Register 62h Timer 2 Count Register 56h Timer 0 Control Register 5Eh Timer 1 Control Register 66h Timer 2 Control Register 16 bit Internal Address Data Bus Timer Counter Unit Block 3 TMROUT1 J TMROUT2 DMA Request Logic Timer0 1 2 R8820 Interrupt Request There are three 16 bit programmable timers in the R8820 The timer operation is independent of the CPU The three timers can be programmed as a timer element or as a counter element Timers O and 1 are each connect to two external pins TMRINO TMROUTO TMRIN1 TMROUT1 which can be used to count or time external events or they can be used to generate a variable duty cycle waveforms Timer 2 is not connected any external pins It
72. le of the size of the memory block size selected in these bits For example if the midrange block is 32Kbytes only the bits BA19 to BA15 can be programmed So the block address could be locate at 20000h or 38000h but not in 22000h The base address of the MCS chip select can be set to 00000h only if the LCS chip select is not active And the MCS chip select address range is not allowed to overlap the LCS chip select address range The MCS chip select address range also is not allowed to overlap the UCS chip select address range Bit 8 3 Reserved Bit 2 R2 Ready Mode This bit is configured to enable disable the wait states inserted for the MCS chip selects The R1 RO bits of this register determine the number of wait state to insert set to 1 external ready is ignored set to 0 external ready is required Bit 1 0 R1 RO Wait State value The R1 RO determines the number of wait states inserted into a MCS access R1 RO 1 1 3 wait states 1 0 2 wait states 0 1 1 wait states 0 0 O0 wait states RDC Semiconductor Co Rev 1 3 Subject to change without notice 33 RDC coo 620 PCS and MCS Auxiliary Register Offset A8h Reset Value 15 014 13 12 A 9 8 7 6 5 4 3 2 4 0 Me uo ESPSRERERERETERES Bit 15 Reserved Bit 14 8 M6 MO MCS Block Size These bits determines the total block size for the MCS3 MCSO chip selects Each individual chip select is active for one quarter of the total block size
73. ll up 10 74 TMROUTO Input with 10k pull down 11 75 TMRINO Input with 10k pull up 12 T DRQO INTS Input with 10k pull up 13 76 DRQI INT6 Input with 10k pull up 14 50 MCSO Input with 10k pull up 15 51 MCSI Input with 10k pull up 16 66 PCSO Input with 10k pull up 17 65 PCSI Input with 10k pull up RDC Semiconductor Co Subject to change without notice 77 Rev 1 3 RD CE isc BBO 18 63 PCS2 CTS1 ENRX1 Input with 10k pull up 19 62 PCS3 RTSI RTRI Input with 10k pull up 20 3 RTSO RTRO Input with 10k pull up 21 100 CTSO ENRXO Input with 10k pull up 22 2 TXDO Input with 10k pull down 23 1 RXDO Input with 10k pull down 24 68 MCS2 Input with 10k pull up 25 69 MCS3 RFSH Input with 10k pull up 26 97 UZI Input with 10k pull up 27 98 TXDI Input with 10k pull up 28 99 RXDI Input with 10k pull up 29 96 S6 CLKDIV Input with 10k pull up 30 52 INT4 Input with 10k pull up 31 54 INT2 Input with 10k pull up PIO Data 1 Register PDATA 31 16 Bit 15 0 PDATA31 PDATA16 PIO Data Bits These bits PDATA31 PDATA16 map to the PIO31 PIO16 which indicate the driven level when the PIO pin as an Offset 7Ah Reset Value 4 3 2 1 0 output or reflects the external level when the PIO pin as an input PIO Direction 1 Register PDIR 31 16 Bit 15 0 PDIR 31 PDIR16 PIO Direction Register Set 1 Configure the PIO pin as an input Offset 78h Reset Va
74. lock 23 10 Reset 24 11 Bus Interface Unit 26 11 1 Memory and I O Interface 26 11 2 Data Bus 26 11 3 Wait States 27 14 Bus Hold eer eoe se eee 28 11 5 Bus Width 30 12 Chip Select Unit 31 12 1 UCS ee C 31 15 2 Dl fete ERE eines cep ade des rane Aa 32 TIRAS e ADE ne CERE eee 33 124 POS dl dad ete 34 13 Interrupt Controller Unit 37 13 1 Master Mode and Slave Mode 37 13 2 Interrupt Vector Type and Priority 38 13 3 Interrupt Request 39 13 4 Interrupt Acknowledge 39 13 5 Programming Register 40 RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC BBD
75. low Exception 04h 10h 1 Array Bounds Exception 05h 14h 1 Undefined Opcode Exception 06h 18h 1 ESC Opcode Exception 07h 1Ch 1 Timer 0 08h 20h 08 2 1 E 4 Reserved 09h DMA O INTS OAh 28h 0A 3 il DMA 1 INT6 OBh 2Ch OB 4 ER INTO OCh 30h oC j5 INTI ODh 34h OD 6 INT2 OEh 38h 0E 7 INT3 OFh 3Ch OF 8 INT4 10h 40h 10 9 Asynchronous Serial port 1 11h 44h 11 9 Timer 1 12h 48h 08 2 2 d Timer 2 13h 4Ch 08 2 3 PS Asynchronous Serial port 0 14h 50h 14 9 Reserved 15h 1Fh Note When the interrupt occurs in the same time the priority is 1 1 gt 1 2 2 1 2 2 gt 2 3 Note The interrupt types of these sources are programmable in slave mode 13 3 Interrupt Request When an interrupt is request the internal interrupt controller verifies the interrupt is enable The IF flag is enable no MSK bit set and that there are no higher priority interrupt requests being serviced or pending If the interrupt is granted the interrupt controller uses the interrupt type to access a vector from the interrupt vector table If the external INT is active level trigger to request the interrupt controller service and the INT pins must hold till the microcontroller enter the interrupt service routine There is no interrupt acknowledge output when running in fully nested mode so it should use PIO pin to simulate the interrupt acknowledge pin if necessary 13 4 Interrupt Acknowledge The processor requires the interrup
76. lue FFFFh 4 3 2 1 0 Set 0 Configure the PIO pin as an output or as normal pin function PIO Mode 1 Register PMODE 31 16 Bit 15 0 PMODE31 PMODE16 PIO Mode Bit Offset 76h Reset Value 0000h 4 3 2 1 0 RDC Semiconductor Co Subject to change without notice 78 Rev 1 3 RDC ooo The definition of PIO pins are configured by the combination of PIO Mode and PIO Direction And the PIO pin is programmed individual The definition PIO Mode PIO Direction for PIO pin function 0 0 Normal operation 0 1 PIO input with pull up pull down 1 0 PIO output 1 1 PIO input without pull up pull down PIO Data 0 Register Offset 74h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDATA 15 0 Bit 15 0 PDATA15 PDATAO PIO Data Bus These bits PDATA15 PDATAO map to the PIO15 PIOO which indicate the driven level when the PIO pin as an output or reflects the external level when the PIO pin as an input PIO Direction 0 Register Offset 72h Reset Value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDIR 15 0 Bit 15 0 PDIR 15 PDIRO PIO Direction Register Set 1 Configure the PIO pin as an input Set 0 Configure the PIO pin as an output or as normal pin function PIO Mode 0 Register Offset 70h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMODE 15 0 Bit 15 0 PMODE15 PMODEO PIO Mode Bit RDC Semiconductor Co Rev 1 3 Subject to chan
77. maximum count value Timer O and timer can be configured to single or dual Maximum Compare count mode the TMROUTO or TMROUTI signals can be used to generated waveform of various duty cycle RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC ezo Maxcount A Maxcount B Maxcount A Maxcount B Dual Maximum Count Mode LP Maxcount A 1T Maxcount A 1T Maxcount A Single Maximum Count Mode 1T One Microprocessor clock Timer Counter Unit Output Modes RDC Semiconductor Co Rev 1 3 Subject to change without notice 67 RDC 620 16 Watchdog Timer R8820 has one independent watchdog timer which is programmable The watchdog timer is active after reset and the timeout count with a maximum count value The keyed sequence 3333h CCCCh must be written to the register E6h first then writing new configuration to the Watchdog Timer Control Register It is a single write so every one writing to Watchdog Timer Control Register must follow the rule To read the Watchdog Timer Control Register the keyed sequence 5555h AAAAh must be written to the register E6h first The current count should be reset before modifying the Watchdog Timer timeout period to ensure that an immediate timeout dose not occur Watchdog Timer Control Register Offset E6h Reset Value C080h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 15 ENA Enable Watchdog Timer Set 1 Enable Watchdog Timer Set 0 Disable
78. nch penalty IDecodd following stages New uOP Note op 1 operand read stage EA Calculate Effective Address stage Idle Bus Idle stage TO T3 Bus TO T3 stage Access Access data from cache memory stage RDC Semiconductor Co Rev 1 3 Subject to change without notice 85 R D RISC DSP Controller 21 AC Characteristics A19 A0 AD15 ADO UCS LCS PCSx MCSx DEN T1 T2 READ CYCLE T3 T4 CLKOUTA TW R8820 RDC Semiconductor Co Subject to change without notice 86 Rev 1 3 RDC 4X23S Reo No Description MIN MAX Unit 1 CLKOUTA high to A Address Valid 0 12 ns 2 A address valid to RD low 1 5T 9 ns 3 S6 active delay 0 15 ns 4 S6 inactive delay 0 15 ns 5 AD address Valid Delay 0 12 ns 6 Address Hold 0 12 ns T Data in setup 5 ns 8 Data in Hold 2 ns 9 ALE active delay 0 12 ns 10 ALE inactive delay 0 12 ns 11 Address Valid after ALE inactive T 2 5 ns 12 ALE width T 5 ns 13 RD active delay 0 12 ns 14 RD Pulse Width 2T 10 ns 15 RD inactive delay 0 12 ns 16 CLKOUTA HIGH to LCS UCS valid 0 15 ns 17 UCS LCS inactive delay 0 15 ns 18 PCS MCS active delay 0 15 ns 19 PCS MCS inactive delay 0 15 ns 20 DEN active delay 0 15 ns 21 DEN inactive delay 0 15 ns 2
79. nized transfer which differs from a source synchronized transfer in that two idle states are added to the end of the deposit cycle The two idle states extend the DMA cycle to allow the destination device to deassert its DRQ pin four clocks before the end of the cycle If the two idle states were not inserted the destination device would not have time to deassert its DRQ signal Fetch Cycle Fetch Cycle T1 T2 T3 T4 T1 T2 T3 T4 TI TI CLKOUTA DR Casel DRQ Case2 O AA NETES Case1 Current destination synchronized transfer will not be immediately followed by another DMA transfer Case Current destination synchronized transfer will be immediately followed by another DMA transfer Destination Synchronized Transfers RDC Semiconductor Co Rev 1 3 Subject to change without notice 60 RDC e20 14 3 Serial Port DMA Transfer The serial port data can be DMA transfer to or from memory or IO space And the B W bit of DMA control Register must be set 1 for byte transfer The map address of Transmit Data Register is written to the DMA Destination Address Register and the memory or I O address is written to the DMA Source Address Register when transmit data The map address of Receive Data Register is written to the DMA Source Address Register and the memory or I O address is written to the DMA Destination Address Register when receive data The software is programmed through the Serial Port Control Register to perform the seria
80. nt Register 58h value High input enables the counting which counts internal events The definition of setting the EXT RTG 0 0 Timerl counts the internal events if the TMRINI pin remains high 0 1 Timer counts the internal events count register reset on every rising transition on the TMRINI pin 1 x TMRINI pin input acts as clock source and timer count register increase one every four external clock Bit 3 P Prescaler Bit This bit and EXT 5Eh 2 define the timer 1 clock source The definition of setting the EXT P 0 0 Timerl Count Register increase one every four internal processor clock 0 1 Timerl count register increase one which prescal by timer 2 1 x TMRINI pin input acts as clock source and Timer1 Count Register increase one every four external clock Bit 2 EXT External Clock Bit Set 1 Timer 1 clock source from external Set 0 Timer 1 clock source from internal Bit 1 ALT Alternate Compare Bit This bit controls whether the timer runs in single or dual maximum count mode Set 1 Specify dual maximum count mode In this mode the timer counts to Maxcount Compare A then resets the count register to 0 Then the timer counts to Maxcount Compare B then resets the count register to O again and starts over with Maxcount Compare A Set 0 Specify single maximum count mode In this mode the timer will count to the valve contained in Maxcount Compare A and reset to 0 and then the timer counts to
81. nterrupt Control Unit Block Diagram 13 1 Master Mode and Slave Mode The interrupt controller can be programmed as a master or slave mode program FEh bit 14 The master mode has two connections Fully Nested Mode connection or Cascade Mode connection Interrupt Source Interrupt Source Interrupt Source Interrupt Source Interrupt Source Interrupt Source Interrupt Source Fully Nested Mode Connections RDC Semiconductor Co Subject to change without notice Rev 1 3 37 RDC coo 620 Interrupt Sources IR7 8259 8259 pal CAS3 CASO INTA f CAS3 CASO Interrupt Sources Interrupt Sources 8259 CAS3 CASO i NE INT INTA CAS3 CASO Interrup f Sources Cascade Mode Connection Address Dccode Slave Mode Connection 13 2 Interrupt Vector Type and Priority The following table shows the interrupt vector addresses type and the priority The maskable interrupt priority can be changed by programmed the priority register The Vector addresses for each interrupt are fixed Interrupt source Interrupt Vector EOI Priority Note Type Address Type Divide Error Exception 00h 00h Trace interrupt 01h 04h 1 1 NMI 02h 08h 1 2 Breakpoint Interrupt 03h OCh 1 RDC Semiconductor Co Rev 1 3 Subject to change without notice 38 RDC coo INTO Detected Over F
82. o 620 11 4 Bus Hold When the bus hold requested HOLD pin active high by the another bus master the microprocessor will issue a HLDA in response to a HOLD request at the end of T4 or Ti When the microprocessor is in hold status HLDA is high the AD15 ADO A19 A0 WR RD DEN S1 S0 S6 BHE DI R WHB and WLB are floating and the UCS LCS PCS6 PCS5 MCS3 MCSO and PCS3 PCSO will be drive high After HOLD is detected as being low the microprocessor will lower the HLDA Case 1 Ti Ti Ti Ti Case 2 T3 T4 Ti Ti CLKOUTA HOLD HLDA AD15 ADO Floating A19 A0 p co ae _Floating _ DEN F Floating _ Floating SC S2 S0 WLB BUS HOLD ENTER WAVEFORM RDC Semiconductor Co Rev 1 3 Subject to change without notice 28 RD O RISC DSP Controller Case 1 Case 2 Ti Ti Ti Ti T1 Ti Ti Ti T4 T1 CLKOUTA HOLD HLDA AD15 ADO A19 A0 DEN e A a ee el DT R S2 S0 Floating _ Floating Floating _ Floating _ Floating Iu Floating _ Floating 7 BUS HOLD LEAVE WAVEFORM R8820 RDC Semiconductor Co Subject to change without notice 29 Rev 1 3 RDC io 620 11 5 Bus Width The R8820 default is 16 bits bus access And the bus can be programmed as 8 bits or 16 bits access during memory or I O access is located in the LCS or MCSx or PCSx address space
83. on of INT2 is the same as INT4 For INTAO feature in cascade mode or special fully nested mode this pin corresponds the INTO Maskable interrupt request l slave select For INTI feature except the difference interrupt line and interrupt address vector the function of INTI is the same as INT4 For SELECT feature when the microcontroller is as a slave 55 INTI SELECT Input Output device this pin is drived from the master interrupt controller decoding This pin acts to indicate that an interrupt appears on the address and data bus The INTO must act before SELECT acts when the interrupt type appears on the bus Maskable interrupt request 0 Except the interrupt line and 56 INTO SO1 Input Output interrupt address vector the function of INTO is the same as INT4 imer Control Unit Interface Timer input These pins can be as clock or control signal input which depend upon the programmed timer mode After a TUN IC Input Output internally synchronizing low to high transitions on TMRIN the 75 TMRINO PIO11 timer controller increments These pins must be pull up if not being used 73 TMROUT1 PIO1 GuteuUfipdt Timer output Depending on timer mode select these pins 74 TMROUTO PIO10 P P provide single pulse or continuous waveform The duty cycle RDC Semiconductor Co Rev 1 3 Subject to change without notice R D RISC DSP Controller R8820 of the waveform can b
84. ort 1 Baud Rate Divisor Register Offset 18h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAVDDIV These bits definition are same as the bits definition of Register 88h RDC Semiconductor Co Rev 1 3 Subject to change without notice 76 R D RISC DSP Controller 18 PIO Unit R8820 provides 32 programmable I O signals which are multi function pins with others normal function signals Software is R8820 programmed through the registers 7Ah 78h 76h 74h 72h 70h to configure the multi function pins for PIO or normal function PIO Data In Out Read PDATA Normal Data I Normal Function For internal L i L L L PIO PIO Mode Direction H L i L L For internal pull down Microprocessor Clock O un normal function PIO pin Operation Diagram 18 1 PIO multi function Pin list table PIO No Pin No Multi Function Reset status PIO internal resister 0 72 TMRINI Input with 10k pull up 1 73 TMROUTI Input with 10k pull down 2 59 PCS6 A2 Input with 10k pull up 3 60 PCS5 A1 Input with 10k pull up 4 48 DT R Normal operation Input with 10k pull up 5 49 DEN Normal operation Input with 10k pull up 6 46 SRDY Normal operation Input with 10k pull down 7 22 Al7 Normal operation Input with 10k pull up 8 20 A18 Normal operation Input with 10k pull up 9 19 A19 Normal operation Input with 10k pu
85. p to A15 AO during a DMA transfer The value of DSA19 DSAO b will increment or decrement by 2 after each DMA transfer 14 2 External Requests External DMA requests are asserted on the DRQ pins The DRQ pins are sampled on the falling edge of CLKOUTA It takes a minimum of four clocks before the DMA cycle is initiated by the Bus Interface The DMA request is cleared four clocks before the end of the DMA cycle And no DMA acknowledge is provided since the chip selects MCSx PCSx can be programmed to be active for a given block of memory or I O space and the DMA source and destination address registers can be programmed to point to the same given block DMA transfer can be either source or destination synchronized and it can also be unsynchronized The Source Synchronized Transfer figure shows the typical source synchronized transfer which provides the source device at least three clock cycles from the time it is acknowledged to deassert its DRQ line RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC ico 620 Fetch Cycle Fetch Cycle T1 T2 T3 T4 T1 T2 T3 T4 CLKOUTA DR Casel DR Case2 NOTES Case1 Current source synchronized transfer will not be immediately followed by another DMA transfer Case2 Current source synchronized transfer will be immediately followed by antoher DMA transfer Source Synchronized Transfers The Destination Synchronized Transfer figure shows the typical destination synchro
86. quest signal for 98 TXD1 PIO27 Output Input Tranmit data for asynchronous serial port 1 This pin transmits asynchronous serial data from the UART of the microcontrolles 99 RXD1 PIO28 Input Output Receive data for asynchronous serial port 1 This pin receives asynchronous serial data 62 PCS3 RTS1 RTR 1 PIO18 Output Input Ready to send Ready to Receive signal for asynchronous serial port 1 When the RTSI bit in the AUXCON register is set and FC bit in the serial port 1 register is set the RTSI signal is enabled Otherwise the RTSI bit is cleared and FC bit is set the RTR I signal is enabled RDC Semiconductor Co Subject to change without notice Rev 1 3 RD RISC DSP Controller R8820 63 PCS2 CTS1 ENRX1 PIO19 Input Output Clear to send Enable Receiver Request signal for asynchronous serial port 1 when ENRXO bit in the AUXCON register is cleared and the FC bit in the serial port 1 control register is set the ENRXI signal is enabled Other when ENRXI bit is set and the FC bit is set the ENRXI signal is enabled Bus Interface BHE ADEN Output Input Bus high enable address enable During a memory access the BHE and ADO or AO encodings indicate what type of the bus cycle BHE is asserted during T1 and keeps the asserted to T3 and Tw This pin is floating during bus hold and reset BHE and ADO or AO
87. s disable Bit 5 3 Reserved Bit 2 R2 Ready Mode This bit is used to configure the ready mode for LCS chip select Set 1 external ready is ignored RDC Semiconductor Co Rev 1 3 Subject to change without notice 32 RDC vo 620 Set 0 external ready is required Bit 1 0 R1 RO Wait State value When R2 is set to 0 it can inserted wait state into an access to the LCS memory area R1 RO 0 0 O wait state R1 RO 0 1 1 wait state RLRO 2 1 0 2 wait state R1 RO 1 1 3 wait state 12 3 MCSx The memory block of MCS4 MCSO can be located anywhere within the 1M bytes memory space exclusive of the areas associated with the UCS and LCS chip selects The maximum MCSx active memory range is 512k bytes The MCSx chip selects are programmed through two registers A6h and A8h and these select pins are not active on reset Both A6h and ASh registers must be accessed with a read or write to activate MCS4 MCSO There aren t default value on A6h and ASh registers so the A6h and A8h must be programmed first before MCS4 MCSO active Midranage Memory Chip Select Register Offset A6h Reset Value LER NE NE ONCE 9 8 7 6 5 4 3 2 4 0 TT ERERERERERETERES Bit 15 7 BA19 BA13 Base Address The BA19 BA13 correspond to bits 19 13 of the 1M bytes 20 bits programmable base address of the MCS chip select block The bits 12 to 0 of the base address are always 0 The base address can be set to any integer multip
88. s interface unit drives address data status and control information to define a bus cycle The bus A19 AO are non multiplex memory or I O address The AD15 ADO are multiplexed address and data bus for memory or I O accessing The S2 SI are encoded to indicate the bus status which is described in the Pin Description table in page 5 The Basic Application System Block page 10 and Read Write Timing Diagram page 12 describe the basic bus operation 11 1 Memory and VO interface The memory space consists of 1M bytes 512k 16 bit port and the I O space consists of 64k bytes 32k 16 bit port Memory devices exchange information with the CPU during memory read memory write and instruction fetch bus cycles I O read and I O write bus cycles use a separate I O address space Only IN OUT instruction can access I O address space and information must be transferred between the peripheral device and the AX register The first 256 bytes of I O space can be accessed directly by the I O instructions The entire 64k bytes I O address space can be accessed indirectly through the DX register I O instructions always force address A19 A16 to low level FFFFFH Memory 1M Bytes Space OFFFFH I O 64K Bytes Space 0 0 Y Memory and I O Space 512K Bytes 512K Bytes EL A19 1 D15 8 BHE Physical Data Bus Models 11 2 Data Bus The memory address space data bus is physically implemented by dividing the address space into two banks of up to 512k bytes
89. s to CLKOUTA and is active high The falling edge of ARDY must be synchronized to CLKOUTA Tie ARDY high the microcontroller is always asserted in the ready condition If the ARDY is not used tie this pin low to yield control to SRDY 10 S2 SI SO Output Bus cycle status These pins are encoded to indicate the bus status S2 can be used as memory or I O indicator Sl can be used as DT R indicator These pins are floating during hold and reset Bus Cycle Encoding Description S2 SI SO Bus Cycle RDC Semiconductor Co Subject to change without notice Rev 1 3 RD RISC DSP Controller R8820 Interrupt acknowledge Read data from I O Write data to I O Halt Instruction fetch Read data from memory Write data to memory 1 1 Passive pee OOOO Re OOrrF CO re OroOoroOr oOo A19 PIO9 A18 PIO8 A17 PIO7 A16 A2 Al A0 Output Input Address bus Non multiplex memory or I O address The A bus is one half of a CLKOUTA period earlier than the AD bus These pins are high impedance during bus hold or reset 78 80 82 84 8 6 88 91 94 79 81 83 85 8 7 90 93 95 AD0 AD7 AD8 AD15 Input Output The multiplexed address and data bus for memory or I O accessing The address is present during the t1 clock phase and the data bus phase is in t2 t4 cycle The address phase of the AD bus can be disabled when the BHE ADEN pin with external pull Low r
90. se bits must be programmed to 0000b DMA Destination Address Low Register Offset C4h DMAO Reset Value Il a A A zi wo EN N EN Te A o co oo N D al A wo m a o DDA15 DDAO Bit 15 0 DDA15 DDA0 Low DMA 0 Destination Address These bits are mapped to A15 AO during a DMA transfer The value of DDA19 DDAO b will increment or decrement by 2 after each DMA transfer DMA Source Address High Register Offset C2h DMAO Reset Value 3 2 1 0 DSA19 DSA16 zi al Aa Az EN wo EN N are arr A o co co N o al A Bit 15 4 Reserved Bit 3 0 DSA19 DSA16 High DMA 0 Source Address These bits are mapped to A19 A16 during a DMA transfer when the source address is in memory space or I O space If the source address is in I O space 64 Kbytes these bits must be programmed to 0000b DMA Source Address Low Register Offset COh DMAO Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSA15 DSAO Bit 15 0 DSA15 DSA0 Low DMA 0 Source Address These bits are mapped to A15 AO during a DMA transfer The value of DSA19 DSAO b will increment or decrement by 2 after each DMA transfer DMA Control Registers Offset DAh DMA1 Reset Value FFF9h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DM IO DDEC DINC SM IO SDEC SINC SYN1 SYNO P rona RDC Semiconductor Co Rev 1 3 Subject to change without notice 56 RDC e20 Bit 15 DM IO Destination Address Space Select S
91. t priority pending interrupt End Of Interrupt Offset 22h Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O o z Master Mode Bit 15 NSPEC Non Specific EOI Set 1 indicates non specific EOI Set 0 indicates the specific EOI interrupt type in S4 SO Bit 14 5 Reserved Bit 4 0 S4 S0 Source EOI Type Specifies the EOI type of the interrupt that is currently being processed End Of Interrupt Offset 22h Reset Value 0000h 14 13 12 11 10 15 9 8 7 6 5 4 3 2 1 0 Eojojeo ofe ojero ejojoje oju uju Slave Mode Bit 15 3 Reserved Bit 2 0 L2 L0 Interrupt Type Encoded value indicating the priority of the IS interrupt service bit to reset Writes to these bits cause an EOI to be issued for the interrupt type in slave mode Interrupt Vector Register Offset 20h Reset Value 15 14 19 12 11 10 9 8 7 6 5 4 3 2 1 0 LoloPolefojofojo 14 10 EXE Slave Mode Bit 15 8 Reserved Bit 7 3 T4 TO Interrupt Type The following interrupt type of slave mode can be programmed Timer 2 interrupt controller T4 T3 T2 T1 TO 1 0 1 b Timer 1 interrupt controller T4 T3 T2 T1 TO 1 0 O b DMA 1 interrupt controller T4 T3 T2 T1 TO 0 1 Db RDC Semiconductor Co Rev 1 3 Subject to change without notice RDC io Rewo DMA 0 interrupt controller T4 T3 T2 T1 TO 0 1 0 b Timer 0 interrupt controller T4 T3 T2 T1 TO 0 0 0 b Bit 2 0 Reserved RDC Semiconductor Co Rev 1 3 S
92. t type as an index into the interrupt table The internal interrupt can provide the interrupt type or an external controller can provide the interrupt type The internal interrupt controller provides the interrupt type to processor without external bus cycles generation When an external interrupt controller is supplying the interrupt type the processor generates two acknowledge bus cycles and the interrupt type is written to the AD7 ADO lines by the external interrupt controller RDC Semiconductor Co Rev 1 3 Subject to change without notice 39 RDC voz 1 1 1 1 1 1 1 1 ro Tl 92 T3 4 TI T2 T3 TA 1 1 1 1 1 1 1 CLKOUTA ADDRESS 19 0 AD15 ADO ALE BHE INTAO INTA1 DEN DT R S2 S0 INTERRUPT ACKNOWLEDGE CYCLE CASECADE OR SLAVE MODE 13 5 Programming the Registers Software is programmed through the registers Master mode 44h 42h 40h 3Eh 3Ch 3Ah 38h 36h 34h 32h 30h 2Eh 2Ch 2Ah 28h 26h 24h 22h Slave Mode 3Ah 38h 36h 34h 32h 30h 2Eh 2Ch 2Ah 28h 22h 20h to define the interrupt controller operation Serial Port 0 Interrupt Control Register Offset 44h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A ESE Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the asynchronous serial port 0 Set 0 Enable the serial port O interrupt Bit 2 0 PR2 PRO Priority These bits determine the priorit
93. ubject to change without notice 53 RDC 620 14 DMA Unit The DMA controller provides the data transfer between the memory and peripherals without the intervention of the CPU There are two DMA channels in the DMA unit Each channel can accept DMA request from one of three sources external pin DRQO for channel 0 or DRQ1 for channel 1 or serial port port 0 or port 1 or Timer 2 overflow The data transfer from source to destination can be memory to memory or memory to I O or I O to I O or I O to memory Either bytes or words can be transferred to or from even or odd addresses and two bus cycles are necessary read from source and write to destination for each data transfer 20 bit Adder Subtractor DONT OUR u Logic C8h Transfer Counter Channel 0 p C2h COh Source Address Channel 0 Request BE nux Arbitration DRO1 C6h C4h Destination Address Channel 0 Logie e Control g Serial Port0 CAH 4 Channel 0 DAH 4 Channel 1 TDRQ Timer 2 Request DRQO D8h Transfer Counter Channel 1 D2h DOh Source Address Channel 1 D6h D4h Destination Address Channel 1 Logic Serial Portl Interrupt Request CAh 8 Channel 0 CAh 8 Channel 1 INT Channel Control Register0 CAh Channel Control Registerl DAh 16 bit Internal Address Data Bus DMA Unit Block 14 1 DMA Operation Every DMA transfer consists of two bus cycles figure of Typical DMA Transfer and the two bus cycles can not be separated by a bus
94. v 9soa L__ 7 22 tora 1v ssoa C LL sora srv 224 LL eora erv erord Iulu IsiW tsod 7 ano 8TOId TXaNa TSLO zZsod PT a amp rinoxio ano L VINONTO LTOId tsod L 924 91oria osoa C zx 99A E ET TX yzold zson C 7 ano SzOId HS4M ESON LT os ano TT IS asa I zs OOId ININML L Aquw TOId TLNOMNL av oroia O0inowWNL HO aqu IIOId ONIWWL A uM TOId 9LNI TOud wsav sH amp zrorda siNI O0 ud 7 ozora ouiu 0slu E 858833238 3525528358 amp 8 3 q com cm e em i m M prece EE NU QUNM AR E 4 9 924992 A OE E QA q A A a A SNS c C0 C NNN N JH dH d jO o o SERBERE E a E z E oO E Po n wo E n oO Rev 1 3 Subject to change without notice RDC Semiconductor Co O R D RISC DSP Controller R8820 R8820 Pin OUT Pin name LQFP Pin No PQFP Pin No Pin name LQFP Pin No PQFP Pin No ADO 1 78 All 51 28 AD8 2 79 A10 52 29 ADI 3 80 A9 53 30 AD9 4 81 A8 54 31 AD2 5 82 A7 55 32 AD10 6 83 A6 56 33 AD3 7 84 A5 57 34 ADII 8 85 A4 58 35 AD4 9 86 A3 59 36 AD12 10 87 A2 60 37 AD5 11 88 VCC 61 38 GND 12 89 Al 62 39 AD13 13 90 AO 63 40 AD6 14 91 GND 64 41 VCC 15 92 WHB 65 42 ADI4 16 93 WLB 66 43 AD7 17 94 HLDA 67 44 AD15 18 95 HOLD 68 45 UZI PI 026 20 97 NMI 70 47 TXD1 PI
95. y of the serial port relative to the other interrupt signals RDC Semiconductor Co Rev 1 3 Subject to change without notice 40 RD RISC DSP Controller The priority selection PR2 PR1 PRO Priority R8820 0 0 0 O High 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 L 3 05 1 5 Lx X20 6 1 1 7 Low Serial Port 1 Interrupt Control Register Offset 42h 15 14 Master Mode 13 12 4 3 2 1 0 A ESE em Bit 15 4 Reserved Bit 3 MSK Mask 10 Reset Value 000Fh 9 8 7 6 5 Set 1 Mask the interrupt source of the asynchronous serial port 1 Set 0 Enable the serial port 1 interrupt Bit 2 0 PR2 PRO Priority These bits determine the priority of the serial port relative to the other interrupt signals The priority selection PR2 PRI PRO Priority 0 0 0 0 5i gt 0 gt 0 1 0 0 High RDC Semiconductor Co Subject to change without notice Rev 1 3 41 RDC vei 620 INT4 Control Register Offset 40h Reset Value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pres fem fe fusk Pre ens ene Master Mode Bit 15 8 bit 6 5 Reserved Bit 7 ETM Edge trigger enable When this bit set to 1 and Bit 4 set to 0 interrupt is triggered by low go high edge The low go high edge will be latched one level till this interrupt is been serviced Bit 4 LTM Level Triggered Mode Set 1 Interrupt is triggered by high active level Set
96. y space or I O device will complete a data transfer The SRDY pin accepts a falling edge that is asynchronous to CLKOUTA and is active high SRDY is accomplished by elimination of the one half clock period required to internally synchronize ARDY Tie SRDY high the microcontroller is always assert in the ready condition If the SRDY is not used tie this pin low to yield control to ARDY 48 DT R PIO4 Output Input Data transmit or receive This pin indicates the direction of data flow through an external data bus transceiver DT R low the microcontroller receives data When DT R is asserted high the microcontroller writes data to the data bus RDC Semiconductor Co Subject to change without notice Rev 1 3 R D RISC DSP Controller R8820 49 DEN PIO5 Output Input Data enable This pin is provided as a data bus transceiver output enable DEN is asserted during memory and I O access DEN is drived high when DT R changes state It is floating during bus hold or reset condition 96 S6 CLKDIV PIO29 Output Input Bus cycle status bit6 clock divided by 2 For S6 feature this pin is low to indicate a microcontroller initiated bus cycle or high to indicate a DMA initiated bus cycle during T2 T3 Tw and T4 For CLKDIV2 feature The internal clock of microcontroller is the external clock be divided by 2 CLKOUTA CLKOUTB X1 2 if this pin held low during power on reset The pin

16-Bit RISC Microcontroller User`s Manual

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