MrX Sound Board for the ZX81 from Sinclair “Manual for users and
Contents
1. EO E Oo D HL DFILE C HL D HL O C HL D HL F C HL LD HL F EE SE aE H LD BC 100 ALL 0F35 Q D A 14 LATCH A QE oc e O E G E DTAX A Set all bits of port A to 1 high DFILE HE a n Ti H D HL O H H ICE a Li E Iw L N H Cx m Li LD HL LD BC 100 CALL 0F35 jp looop Version v005 16 Date 22 05 2012 Reading from port A DTAX equ SOF DTAX equ 1F LATCH equ SCF LATCH equ SDF XXX LD A 7 out LATCH A LD A 00 set port A amp B to Input out DTAX A looop LD A 14 out LATCH A in a LATCH Port A register No 14 is read and a 3F LD HL DFILE INC HL LD HL A Print the port content to the screen jp looop Version v005 17 Date 22 05 2012 9 The Yamaha YM2149 This is a copy from http www atari forum com wik1 Software Controlled Sound Generator SSG Overview The SSG Software Controlled Sound Generator is an NMOS LSI device designed to be capable of music generation It only requires the microprocessor or microcomputer CPU to initialize its register array thus reducing the load on the CPU Music generation is carried out by the three sequence square wave generator noise generator and envelope generator according to the set parameters This allows for the generation of music special effects warnings and various other types of sounds Feat2. Input is selected when 0 is written to the register bits I O port and mixer setting register R7 B7 B6 B5 B4 B3 B2 B1 BO IN N Input is selected for I O port when 0 and noise or tone can be output when 0 Version v005 22 Date 22 05 2012 4 Level control controlled by R8 RA The audio level output from the D A convertors for the three channels A B and C is adjusted by registers R8 R9 and RA Level setting registers Channel R8 A R9 B RA C B7 B6 B5 B4 B3 B2 B1 BO Wr N N Not used N N N M L3 L2 L1 LO Mode 4 bit level selection Mode M selects whether the level is fixed when M 0 or variable M 1 When M 0 level is determined from one of 16 by level selection signals L3 L2 L1 and LO which compromise the lower four bits When M 1 the level is determined by the 5 bit output of E4 E3 E2 E1 and EO of the envelope generator of the SSG This level is variable as E4 EO change over time 5 Setting of envelope frequency controlled by R8 and RC Thus the envelope repetition frequency fE is obtained as follows from the envelope setting period value EP decimal FE fMaster fMaster if the frequency of the master clock Envelope rough adjustment register RC Envelope fine adjustment register RB B7 B6 B5 B4 B3 B2 B1 BO B7 B6 B5 B4 B3 B2 B1 BO N N i b N EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EPA EP3 EP2 EP1 EPO 16 bit envelope period setting value EP The
3. following manner from the value of the register TP decimal fMaster is the frequency of the master clock this is the input click frequency when SEL is high and 1 2 of this frequency when low Rough tone adjustment Fine tone adjustment register Channel register R1 A RO R3 B R2 R5 C R4 B7 B6 B5 B4 B3 B2 B1 BO B7 B6 B5 B4 B3 B2 B1 BO WNee e e N Not used N TP11 TP10 TP9 TP8 TP7 TPO TP5 TP4 TP3 TP2 TEL TPO 12 bit oscillation frequency setting value TP 2 Setting of noise generator controlled by register R6 The noise frequency fN is obtained from the register value NP decimal in the following manner fN fMaster fMaster if the frequency of the master clock Noise frequency register R6 B7 B6 B5 B4 B3 B2 B1 BO Aem N Not used N NP4 NP3 NP2 NP1 NPO 5 bit noise frequency setting value NP 3 Settings of mixer and I O ports controlled by register R7 The mixer is used to combine music and noise components The combination is determined by bits B5 BO of register R7 Sound is output when a 0 is written to the register Thus when both the noise and tone are 0 the output is combined by the mixer When the noise is 0 and the tone is 1 only the noise signal is output When the noise is 1 and the tone is 0 music square wave is output Nothing is output when both the noise and tone are 1 Selection of input output for the I O ports is determined by bits B7 and B6 of register R7
4. DIR BC1l and Controls the following fou is redundant BDIR BC2 BC1 0 0 0 l nspPb booo PRPOORPPRSO FPOrRPOrROPR Inactive mode Address mode Write mode Read mode 7 ANALOG CHANN Each of the t the calculate 8 IOA7 IOAO These are two between an ex have pullup r 9 TESTL Output pin fo 10 Vee 5V power pin ll Ves Ground pin Version v005 BC2 external bus DA7 DAO and internal bus of the SSG The r modes can be set by the bus control decoder The bus control control is possible even when BC5 is connected to 5V Mode Inactive Address Inactive Read Address Inactive Write Address DA7 DAO has high impedance DA7 DAO set to input mode and address is fetched from register array DA7 DAO set to input mode and data is written to register currently being addressed DA7 DAO set to output mode and contents of register currently being addressed are output EL A B C hree channels is equipped with a D A convertor which converts d digital values to analog signals for output IOB7 IOBO 8 bit I O ports These ports allow the SSG to be placed ternal system and the CPU for the transfer of data These pins esistance r testing the device Do not connect to anything 20 Date 22 05 2012 Description of funtions All functions of the SSG are controlled by the 16 internal registers The CPU need only write data to the internal registers of the SSG The SSG itself gen
5. MrX Sound Board for the ZX81 from Sinclair Manual for users and programmers www eightbits de Version v005 1 Date 22 05 2012 CONTENT l System Requirements O eae 4 2 MrX Sound Card eee 5 3 MrX Expansion Bus K3 aaa 6 4 Optional 3 5mm jacks and ZX96 bus diodes 7 5 Connection ees 8 6 Software eee 11 7 Six Channel Sound Turbo Sound Turbo AY 12 8 Programming eee 15 9 The Yamaha YM2149 0 eee 18 Version v005 2 Date 22 05 2012 Disclaimer This book is presented solely for educational and entertainment purposes The author and publisher are not offering it as legal accounting or other professional services advice While best efforts have been used in preparing this book the author and publisher make no representations or warranties of any kind and assume no liabilities of any kind with respect to the accuracy or completeness of the contents and specifically disclaim any implied warranties of merchantability or fitness of use for a particular purpose Neither the author nor the publisher shall be held liable or responsible to any person or entity with respect to any loss or incidental or consequential damages caused or alleged to have been caused directly or indirectly by the information or programs contained herein No warranty may be created or extended by sales representatives or written sales materials Every company is different and the advice and strategies contained herein may not be su
6. el o o o A B e Description of pins Tu DA7 DAO This is an 8 bit bidirectional data bus which is used for moving data and addresses between the SSG and CPU In the read and write modes DA7 DAO corresponds to B7 BO of the register array In the address mode DA3 DAO is used for the register address and DA7 DA4 is used together with A9 and A8 for the upper address A8 and A9 These are the upper address input pins A8 has pullup resistance while A9 has pulldown resistance When the voltage level at A8 while the level at A9 and DA7 DA4 is low the address mode is selected allowing for the fetching of a register address Connect A8 and A9 to 5V and ground respectively when not in use RESET Reset is effective when the voltage level is low and the contents of all registers in the array are reset to 0 This pin has pullup resistance CLOCK Supplies the master clock to the sound generator and envelope generator This is equipped with a 1 2 frequency divider which allows for the use of a frequency which is 1 2 of the input clock as the master clock SEL When SEL is driven to the high level the input clock is taken as the master clock When the voltage level of SEL is low the input clock is divided by 2 to obtain the master clock This pin has pullup resistance allowing for full pin compatibility with the AY 3 8910 manufactured by AI when this pin is not connected to anything Version v005 19 Date 22 05 2012 6 B
7. erates the sound Sound is generated by the following blocks Music generator Square waves having a different frequency are generated for each channel A B and C Noise generator Pseudo random waveforms are generated variable frequency Mixer Music and noise output are mixed for the three channels A B and C Level control Constant level or variable level is given for each of the three channels A B and C Constant levels are controlled by the CPU and variable levels by the envelope generator Envelope generator Generates various types of attenuation single burst attenuated and repeated attenuation D A convertor Sound is output on each of the three channels A B and C at the level determined by the level control The CPU can read the contents of the internal registers with no effect on sound Register Array A9 A8 DA7 DA6 DAS DA4 DA3 DA2 DA1 DAO 0 1 0 0 0 0 0 0 0 0 0 af 0 0 0 0 1 1 1 1 Upper addresses Lower addresses chip select register select Of the ten bit address the lower addresses DA3 DAO are used to select the 16 internal registers register array The upper addresses are used for chip selection A9 and A8 is programmed to 01 while DA7 through DA4 are set to 0000 When the upper addresses match this program in the address mode a register address lower four bits DA3 through DAO is fetched from the register address latch When the value set is in the upper addresses is different from the prog
8. is step Version v005 13 Date 22 05 2012 Now the MrX card is ready for the 6 channel stereo sound Connect the MrX according to chapter 5 Connection The following combinations are tested and working Modified MrX ZXpand Zxpand AY ZX81 SE fervor ZXpand MESLLILILILILLIII TT pee Modified MrX Original MrX ZX81 Connect two PC speakers with the two sound cards or use an appropriate mixer Version v005 14 Date 22 05 2012 8 Programming The MrX is compatible with the original ZON X sound card Addresses The MrX Interface responds to data placed in the following addresses Latch Data Comment OxDF OxOF modified ZON X OxCF Ox1F original ZON X OxCF OxOF from ZON X user manual OxDF OxlF additional combination See chapter 9 The Yamaha YM2149 for further explanation about Latch register address latch and Data write mode Examples in assembler Simple Sound H LATCH equ DF LATCH equ CF DTAX equ SOF DTAX equ S1F XXX LD A out LATCH A LD A CO out DTAX A LD A 08 out LATCH A LD A45 out DTAX A looop LD A 0 out LATCH A LD A 70 out DTAX A ret Version v005 15 Date 22 05 2012 Output on port A DTAX equ SOF DTAX equ 1F LATCH equ CF LATCH equ SDF XXX LD A 7 out LATCH A LD A CO set port A and B as output out DTAX A looop D A 14 ut LATCH A D A 00 ut DTAX A set port A to 0
9. itable for your situation You should seek the services of a competent professional before beginning any actions described in this manual Version v005 3 Date 22 05 2012 1 System Requirements Computer Manufacturer Amplifier Recommended Version v005 ZX81 Sinclair UK active amplifier PC amplifier with 3 5mm jack 16k Ram Date 22 05 2012 2 MrX Sound Card A 3 5mm jack Connect the amplifier here B Port connector C 30 pin expansion bus K3 see next chapter reve v Yvon sny B 1 1 1 1 1 1 1 T T T T T 1 1 OCooooo0o0000dc0000 D Through port connector Version v005 5 Date 22 05 2012 3 MrX Expansion Bus K3 The MrX Interface is supplied with a built in expansion bus K3 which allows direct access to the signals provided by the YM2149 sound chip should you wish to develop an add on daughterboard Pinout K3 1 IOB7 Port B from YM2149 2 IOB6 Port B from YM2149 3 IOB5 Port B from YM2149 4 IOB4 Port B from YM2149 5 IOB3 Port B from YM2149 6 IOB2 Port B from YM2149 7 IOBI Port B from YM2149 8 IOBO Port B from YM2149 9 IOA7 Port A from YM2149 10 IOA6 Port A from YM2149 11 IOA5 Port A from YM2149 12 IOA4 Port A from YM2149 13 IOA3 Port A from YM2149 14 IOA2 Port A from YM2149 15 IOAI Port A from YM2149 16 CHL Left channel of 3 5mm jack behind capacitor 17 CHR Right channel of 3 5mm jack behind capacitor 18 GND Ground 19 CLK ZX81 clock signa
10. l 3 25 MHz 20 GND Ground 21 ANALOG CH C Analog Channel C directly connected to YM2149 22 ANALOG CH B Analog Channel B directly connected to YM2149 H 23 ANALOG C A Analog Channel A directly connected to YM2149 24 VCC Supply current 5V 25 GALI Pin 15 of GAL 16V8 26 GAL2 Pin 14 of GAL 16V8 27 GAL3 Pin 13 of GAL 16V8 28 GALA Pin 12 of GAL 16V8 29 clock 2 1 625 MHz 30 IOAO Port A from YM2149 Version v005 6 Date 22 05 2012 4 Optional 3 5mm jacks and ZX96 bus diodes If needed additional 3 5mm jacks can be soldered on the MrX sound card on J1 and J2 For the ZX96 bus http www fischerkai de zxteam treib_e htm a diode DX1 for the BUSCS signal has to be soldered and the port connector has to be exchanged by a VG64 connector The VG64 connector uses all pins of K2 Note The ZX96 bus is only used by some freaks if your ZX81 is equipped with the same the original MrX won t fit mechanically Version v005 7 Date 22 05 2012 5 Connection Switch off the computer before connecting or removing any interfaces Disconnect the power lead to be certain Otherwise severe damage may occur to the computer and the sound card The ZX81 computer is connected to the sound card via the ZX expansion port on the back of the computer L II237 TT 8 S LE N p B E EDI Make sure that the pins of the ZX81 PCB are exactly aligned with the connector of the MrX sound card Don t use brute force to connect the MrX
11. period of the actual frequency fEA used for the envelope generated is 1 32 of the envelope repetition period 1 fE 6 Envelope shape control controlled by RD The envelope generator counts the envelope clock fEA 32 times for each envelope pattern cycle The envelope level is determined by the 5 bit output E4 EO of the counter The shape of the envelope is created by increasing decreasing stopping or repeating this counter The shape is controlled by bits B3 BO of the register RD Envelope shape control register RD B7 B6 B5 B4 B3 B2 B1 BO N 7i Not used Hold Ob Sess Alt on ao SaaS S Cont Envelope shape control signals Version v005 23 Date 22 05 2012 The envelope can take the shapes shown below according to combinations of the CONT ATT ALT and HOLD signals BS B2 Bl BO CONT ATT ALT HOLD 0 0 pid X 1 0 0 O N IN IN IN IN IN IN LIN VENTE NE NE NE NE NEN 1 1 0 0 ll Zl 7l Zl SI 71 7 J If M M IA AA AS AS NOTE The writing to register RD will reset the envelope frequency clock Version v005 24 Date 22 05 2012
12. ram value the bidirectional bus formed from DA7 through DAO is driven to high impedance A register address which has been fetched is retained until the next address is fetched and is not affected by the read write or inactive mode Register Array B7 BO RO Frequency of Channel A 00000000 8 bit fine tone adjustment R1 0000 4 bit rough tone adjustment R2 Frequency of Channel B 00000000 8 bit fine tone adjustment R3 0000 4 bit rough tone adjustment R4 Frequency of Channel C 00000000 8 bit fine tone adjustment R5 0000 4 bit rough tone adjustment R6 Frequency of Noise 00000 5 bit noise frequency R7 I O port and mixer iinnnttt i I O n Noise t Tone settings bacbacba R8 Level of channel A mllll m Mode l Level R9 Level of channel B mllll m Mode l Level RA Level of channel C mllll m Mode l Level RB Frequency of envelope 00000000 8 bit fine adjustment RC 00000000 8 bit rough adjustment RD Shape of envelope cath c Cont a Att t Alt h Hold RE Data of I O port A 00000000 8 bit data RF Data of I O port B 00000000 8 bit data Version v005 21 Date 22 05 2012 1 Setting of music frequency controlled by registers RO R5 The frequencies of the square wave generated by the music generators for the three channels A B and C are controlled by registers RO through R5 RO and R1 control channel A R2 and R3 are used for channel B and R4 and R5 control channel C The oscillation frequency fT is obtained in the
13. urbo AY sound on the ZX81 REMARKS The modified GAL changes the port address of the MrX to the following values Latch Data OxAF OxE7 OxBF OxF7 OxAF OxF7 OxBF OxE7 This implies that the MrX with the modified GAL is not ZON X compatible any more ATTENTION The following instructions describe how to exchange the orignal GAL chip with the Turbo Sound GAL Follow the instructions carefully and exactly If you are not sure engage a radio engineer or similar to perform the exchange In case of failures severe damage may occur to the computer and the sound card Instructions e Put the MrX sound card in front of you On the top right hand corner you can see the GAL chip marked here with a red rectangle Use a screwdriver or similar to lift the GAL chip out of its socket Don t use brute force There is a gap between the chip and the socket Version v005 12 Date 22 05 2012 e Pull out the GAL Chip You can see the empty socket LEM NE VPRRRORYURBEYYD om e Take the MrX Turbo Sound chip stick it into the socket carefully Pay attention that every pin of the GAL chip is aligned exactly with the socket Watch the pit of the GAL it must be exactly placed like shown on the picture e Press down the chip slowly until it snaps into the socket While pressing make sure that none of the pins is twisted or misaligned If a pin is twisted stop pressing Pull out the chip allign the pin carefully and repeat th
14. ures 5V single power supply Easy connection to 8 bit or 16 bit CPU Simple connection to external system through 2 sequence 8 bit I O port Wide voicing range of 8 octaves Smooth attenuation by 5 bit envelope generator Built in 5 bit D A convertor Input of double frequency clock can be handled by built in clock frequency divider TTL compatible level Low power consumption typical 125mW 40 pin plastic DIL package Pin compatible with AY 3 8910 manufactured by GI Pin Layout Vss GND 1 40 Vcc 5V N C 2 39 Testl Analog Channel B 3 38 Analog Channel C Analog Channel A 4 37 DAO N C 5 36 DA1 IOB7 6 35 DA2 IOB6 7 34 DA3 IOB5 8 33 DA4 IOB4 9 32 DAS IOB3 10 31 DA6 IOB2 11 30 DA7 IOB1 12 29 BCL IOBO 13 28 BC2 IOA7 14 27 BDIR IOA6 15 26 SEL IOA5 16 25 A8 IOA4 17 24 A9 IOA3 18 23 RESET IOA2 19 22 CLOCK IOA1 20 21 IOAO Version v005 18 Date 22 05 2012 Block diagram A9 A8 BDIR BC2 BEI DA7 DAO o 0 o o o ME Bus Control o Bidirectional o I O Port A lt gt IOA7 IOA0 Decoder o buffer o fal o o Register Addr o Address o Register o Latch Decoder Array o I O Port B lt gt IOB7 IOBO o o o o o Noise Music Envelope Level Frequency Generator Generator Generator o Control o divider o CLOCK master o clock cecec o Mixer o o SEL o D A Convertor o Analog Chann
15. with the ZX81 Version v005 8 Date 22 05 2012 The PC speaker with integrated amplifier has to be connected with the 3 5mm stereo jack GRAPHICS M RUBOUT POKE PRINT PEEK TAB LET FUNCTION NEW K LINE USR BREAK Version v005 9 Date 22 05 2012 Ifneeded connect further equipment NOTE Make sure that the pins of the MrX PCB are exactly aligned with the connector of the equipment Otherwise severe damage may occur to the computer the equipment and the sound card Version v005 10 Date 22 05 2012 6 Software This manual and the software for the MrX sound card is provided at http www eightbits de in the download section manual pdf This manual AY Demo Sound Demo Basic Demo Original Basic Demos from the ZON X Manual Demon Demo Dancing Demon Demo Games 2 Games from Brasilian TK85 PT3 Player Player plays PT3 files Pink Panther Music demo ZON X Manual HTML document original zonx manual Concerning the PT3 Player PT3 files have to be converted to wav files according the instructions in the ZX81 forum http www rwapservices co uk ZX80 ZX81 forums aye aye t528s170 html p4919 Version v005 11 Date 22 05 2012 7 Six Channel Sound Turbo Sound Turbo AY With a modified GAL for the MrX Sound interface you can combine it with the ZXpand plus ZXpand AY module or a second MrX sound module using the original GAL to provide 6 channel stereo output sound T
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