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Xilinx XAPP1000: Reference System : PLBv46 PCI Express in a

1. X1000_73_041408 Figure 73 EP to RC Write Results 8 DW XAPP1000 v1 0 1 May 6 2008 www xilinx com 57 Testing with a PC Testing with a PC XILINX Using a Personal Computer PC as Root Complex RC is an inexpensive method of verifying PLBv46 Endpoint Bridge functionality PCltree and the Memory Endpoint Test MET run on PCs Figure 74 shows the ML555 in a Dell 390 PC The PC PCle integrated circuit s act as root complex The Dell 390 has a x1 connector for PCle slot 1 and a x8 connector for PCle slot 4 In the Dell 390 only 4 of the 8 lanes of the x8 connector are active The Dell 390 runs Windows XP which has ISE EDK and PCltree installed The USB Platform Cable is connected to the ML555 JTAG port for Impact XMD and ChipScope operations A Type A to Type B USB cable is used for communicating to a communication terminal In the tests described in this section the ML555 PCI PCI Express Development Platform is inserted into a Dell 390 x8 slot for the ml555_mb_plbv46_pcie project X1000_74_041408 Figure 74 PC Test Environment The ML555 receives power from the PCle slot and the power up sequence of the PC affects the PCle scan In order for BIOS to recognize the drivers and PCle BARs at power up the FPGA bit file should be loaded prior to PC power up Xilinx recommends writing the XCF32P PROM so that configuration occurs at power up Xilinx recommends the use of Master SelectMap mode fo
2. Dev Num H Func Num H Reg Num Data 4 Bytes H Comp ID H Status 5 af EJE Start Time Type Len H Req ID H Tag H Last DVV BE H First DW BE H Bus Num H Dev Num H Func Num H Reg Num Data 4 Bytes H Comp ID H Status E2 Type Len H Req ID H Tag H Last DW BE H First DW BE H Bus Num H Dev Num H Func Num H Reg Num Data 4 Bytes H Comp ID H Status s EF pa eels Start Time Type Len H Req ID H Tag H Last DWV BE H First DW BE H Bus Num H Dev Num H Func Num H Reg Num Data 4 Bytes H Comp ID H Status E2 Type Len H Req ID H Tag H Last DW BE H First DW BE H Bus Num H Dev Num H Func Num H Reg Num Data 4 Bytes H Comp ID H Status Le ND eo 7 bit 8 i Class Code bit 0 l Programming Interface l 00 p Identifies a sp bit 8 Sub Class Code 80 identifies m bit 16 Base Class Code 05 Memory controller _ Broadly classi _ Ready E N Sal X1000_34_041408 Figure 34 Results from Catalyst Configuration XAPP1000 v1 0 1 May 6 2008 www xilinx com 27 Catalyst Testing lt XILINX Figure 35 shows an excerpt of the Exerciser cfg_x4 sdc file The file contains the stimuli TLPs While it is generally easier to read and edit the TLPs using the Catalyst Display Viewer the text file is readable and editable and more details are provided than can be efficiently presented in the Display Viewer The figure shows t
3. Analyzer 1 000E85000159 USB Exerciser Stop Analyzer Run X1000_51_041408 Figure 51 EP to RC Performance Length 200 Use the LeCroy ML555 test setup shown in Figure 52 to verify the PLBv46 Endpoint Bridge using the LeCroy tester as root complex including configuration and data transactions The ML555 is inserted into the host emulator The m1555_mb_plbv46_pcie lecroy directory contains the stimuli files which use peg as the filename extension This section discusses the procedures used in setting up the LeCroy including defining the Recording and Generation Options Root Complex to Endpoint transactions are discussed followed by a section on Endpoint to Root Complex transactions SPx4 Slot PC Catalyst Software PCle Slot EDK ISE PXP 100a PCI Express DVT Platform X1000_52_041408 Figure 52 LeCroy Test Setup XAPP1000 v1 0 1 May 6 2008 www xilinx com 42 LeCroy Testing XILINX Figure 53 is a photograph of the LeCroy test setup The ML555 is inserted into the LeCroy Host Emulator The Platform Cable USB Programming cable is connected to the ML555 JTAG connector iii es pa X1000_53_041408 Figure 53 LeCroy Test Equipment XAPP1000 v1 0 1 May 6 2008 www xilinx com 43 LeCroy Testing XAPP1000 v1 0 1 May 6 2008 lt XILINX Figure 54 shows the menu for setting Generation Options after selecting Setup gt Generation Options The LeCroy ML test equipment is s
4. header registers are read At power up the Device ID is 0x0505 and the Vendor ID is 0x10EE BARO is 0x0000000C MSR clr set Instruction Support on Compare Instruction Support Connected to MicroBlaze mdm target id G Starting GDB server for mdm target Cid gt at TCP port no 1234 mbconnect command is Deprecated Use connect mb command System reset successfully SMD mur 6x85cO61e8 Bx883fF 61807 AMDz mrd x85cO61e8 1 85C661 EG 663F6167 AMD mrd x85c82808 8 EE100505 46661606 66068685 66060606 6CE08608 66608608 98060608 S5C82G1C M6 5 5 515 515 4 ZMD X1000_80_041408 Figure 80 XMD Read of PLBv46 Endpoint Bridge Registers XAPP1000 v1 0 1 May 6 2008 www xilinx com 64 PCltree Testing XILINX After invoking PCltree and running a scan Figure 81 shows the ML555 PLBv46 Endpoint Bridge detected as Other Memory Controller with Bus Number 3 Device Number 0 Function Number 0 or BDF 3 0 0 The Xilinx Vendor ID and Device ID are displayed In its Configuration Space Header BARO has a value of 0x0000000C direct select show INT routing bus dev 5 3 4 0 0 Den show Mem Map 370 0 i Other Memory Controller Host PCI Bridge Ij YID x 10EE Xilinx Corp O gt 1 l PCI PCI Br DID x0505 no device name found no VGA PC Compatil sunyip x0000 o Multimedia s80f SubID xo000 O gt Z 2 PCI PCI Br rev x00 O gt 3 3 PCI PCI Br edit ConfReg
5. D Sus i amp gt a ELP t nA ACPO SOR Exerciser Program Capture Trigger On Link Settings Settings Global Loop No Loop C Count C Continuous Name MEM WRITE 64 Last DW BE H 00 F MEM READ 64 H Last DW BE H Seq H Fmt H 009 4DW header with data Mem Write First DW BE H Addr H 00A 4DW header no data Mem Read First DWV BE H Addr H Len H 020 Data H F 0000000060000000 RandomData E Len H 001 0000000060000000 Analyzer 1 000E85000159 USB Triggered Exerciser Stop Analyz X1000_37_041408 Figure 37 wr_rd_x4 TLP Stimuli www xilinx com 29 Catalyst Testing XILINX Figure 38 shows the results after running a version of wr_rd_x4 sdc in which a pattern of 0xAA55AA55AA55AA55 is transmitted followed by a pattern of 0x1234567812345678 Catalyst Enterprises Inc SPX Analyzer Exerciser Software wr_rd_x4 l Fie Edit View Configuration Tools Filtering Report Window Help 0 s866 mlajeseis gt m ERE EE Ta PP OlHla SOOe B B 8 ee at 4 ex 3 5 a S E Start Time 0 Req ID H Tag H Last DW BE H 0000 oo F 0000 X1000_38_041808 Figure 38 Catalyst wr_rd_x4 Results XAPP1000 v1 0 1 May 6 2008 www xilinx com 30 Using Catalyst to test PCle Performance XILINX Figure 39 shows the use
6. Look in catalyst lll pcie_dmaz Check All Uncheck All B examples mwr 4 ey pcie_dma Note Link Aggregate E direction does not File name Files of type Apply Settings Start Analyzer 1 000E85000159 USB Exerciser Stop Analyzer X1000_48_041408 Figure 48 Importing Performance Test Setup XAPP1000 v1 0 1 May 6 2008 www xilinx com 39 Endpoint to Root Complex Transactions gt XILINX To generate stimuli either C code or an XMD script is used to write the DMAC registers Figure 49 shows an XMD script to generate stimuli Using XMD scripts and commands allows the relatively quick verification that the operation is functioning correctly After running a DMA operation a mrd command can be used to verify that the data in the source and destination regions are equivalent XMD commands may be too slow to give maximum performance results The DMA Status Register is monitored to determine if the DMAC is Busy When it is not busy a DMA transaction is initiated by a write to the DMAC Length register set outfile open dma txt w connect mb mdm rst puts outfile mwr 0x85C001E0 0x003F0107 puts outfile mwr 0x80200000 0x0000000A puts outfile mwr 0x80200030 0x00000003 puts outfile mwr 0x80200004 0xCc0000004 puts outfile mwr 0x80200008 0x20000000 puts outfile mwr 0x8020000C 0x20002000 puts outfile mwr 0x20000000 0x12345678 100 puts outfile mwr 0x20002
7. XILINX XAPP1000 v1 0 1 May 6 2008 Abstract Included System Introduction Application Note Embedded Processing Reference System PLBv46 Endpoint Bridge for PCI Express in a ML555 PCI PCI Express Development Platform Author Lester Sanders This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI Express used in the Xilinx ML555 PCI PCI Express Development Platform The PLBv46 Endpoint Bridge is used in x1 and x4 PCle lane configurations The PLBv46 Endpoint Bridge uses the Xilinx Endpoint core for PCI Express in the Virtex 5 XC5VLX50T FPGA The PLBv46 Bus is an IBM CoreConnect bus used for connecting the IBM PPC405 or PPC440 microprocessors which are implemented as hard blocks on Xilinx Virtex FPGAs and the Xilinx Microblaze microprocessor to Xilinx IP A variety of tests generate and analyze PCle traffic for hardware validation of the PLBv46 Endpoint Bridge PCle transactions are generated and analyzed by Catalyst and LeCroy test equipment For endpoint to root complex transactions the pcie_dma software application generates DMA transactions which move data over the PCle link s For root complex to endpoint transactions Catalyst and LeCroy scripts generate PCle traffic A Catalyst script which configures the PLBv46 Endpoint Bridge and performs memory write read transactions is discussed The steps to use Catalyst to measure PCle performance are given and performance results are
8. Listing Bus Plot DELA Ramen ed ALON av Signals DEV 0 UNIT 0 9 Data Port jM_wrDBus Sl_rdDBus CH 0 Sl_addrAck CH 1 SI_rdDAck CH 2 SI_wait o gt M weDBus CH 3 SI_rdBTerm a CH 4 PLB_RNW gt Sl1_rdDBus CH 5 SI_rdDBus lt 0 gt 1 addrAck CH 6 SI_rdDBus lt 1 gt CH 7 SI_rdDBus lt 2 gt 51_rdDAck CH 8 SI_rdDBus lt 3 gt CH 9 SI_rdDBus lt 4 gt CH 10 SI_rdDBus lt 5 gt S1_rdBTerm CH 11 SI_rdDBus lt 6 gt CH 12 SI_rdDBus lt 7 gt CH 13 SI_rdDBus lt 8 gt PLB MiirDAck CH 14 SI_rdDBus lt 9 gt a CH 15 SI_rdDBus lt 10 gt PLB_rdBurst CH 16 SI_rdDBus lt 11 gt CH 17 SI_rdDBus lt 12 gt CH 18 SI_tdDBus lt 13 gt TP2INTC_Irpt CH 19 SI_rdDBus lt 14 gt x CH 20 SI_rdDBus lt 1 gt epupepavelt CH 21 SI_rdDBus lt 16 gt 31_wrComp CH 22 SI_rdDBuss17 gt CH 23 SI_rdDBus lt 18 gt CH 24 SI_rdDBus 19 gt Be li 7 ESET Match Unit Function 9 Ci Mo TriggerPortd yaen Bula Add Active Trigger Condition Name TriggerConditiond Type Window v Windows 1 Depth Storage Qualification All Data ainjdeoe E Waveform DEV 0 MyDevice0 XC5VLX50T UNIT 0 MyILAO ILA Bus Signal x o 5l_wait PLB_RNU M_request M_wrBurst INFO Cable Platform Cable USB Port USB21 Speed 3 MHz INFO Found 1 Core Unit in the JTAG device Chain COMMA
9. Pcilree BAR space 00000000 FFFFFFFF oooo0002 FFFFFFFD 00000004 FFFFFFFB oooo00006 FFFFFFF9 ooooo000s FFFFFFF oooo0004 FFFFFFFS ooooo00c FFFFFFF3 00000000E FFFFFFF1 00000010 FFFFFFEF oooo00012 FFFFFFED oooo0014 FFFFFFEB 00000016 FFFFFFE9 00000018 FFFFFFE oooo001la FFFFFFES oooooo1c FFFFFFE3 00000001E FFFFFFE1 ooo0o000z0 men test load tile save lt x00000000 gt x00000004 gt x00000008 gt lt x0000000C gt x00000010 gt x00000014 gt x00000018 gt x0000001C gt x00000020 gt lt x00000024 gt x00000028 gt x0000002C gt lt x00000030 gt x00000034 gt x00000038 gt lt x0000003C gt x00000040 gt x00000044 gt lt x00000048 gt x0000004C gt x000000S0 gt x000000S4 gt x000000S8 gt x000000SC gt lt x00000060 gt x00000064 gt x00000068 gt x0000006C gt x00000070 gt x00000074 gt lt x00000078 gt x0000007C gt lt x00000080 gt V auto read memory Memory Space typeZ prefetchable base 0000000 range ffff0000 64 KByte 64bit BARs not supported yet medit memory pesa E toggle refr I count eE m verify K destination m select view range mem copy KB range 0 63 0 Ki MB range 0 0 Display range v file C 128 Bytes 1024 Bytes X1000_85_041408 Figure 85 PCltree Memory Test Results The ML555 memory written read is the BRAM and or DDR2 defined in the system
10. lt x00000018 gt lt x0000001C gt x00000020 gt lt x00000024 gt x00000028 gt lt x0000002C gt lt x00000030 gt x00000034 gt lt x00000038 gt lt x0000003C gt x00000040 gt x00000044 gt x00000048 gt lt x0000004C gt x000000S0 gt x000000S4 gt lt x000000S88 gt lt x000000SC gt lt x00000060 gt x00000064 gt x00000068 gt x0000006C gt x00000070 gt lt x00000074 gt x00000078 gt x0000007C gt lt x00000080 gt save file he Iv auto read memory Memory Space typeZ prefetchable base 0000000 range ffff0000 64 KByte 64bit BARs not supported yet medit memory Data c toggle Write Memory m count verif loop on off J verity refresh view after write refr view men copy mem copy source destination select view range KB range 0 63 Kil MB range 0 0 K f Display range 128 Bytes 1024 Bytes X1000_84_041408 Figure 84 Running PCltree Memory Test XAPP1000 v1 0 1 May 6 2008 www xilinx com 68 PCltree Testing XILINX Figure 85 shows the results of running the memory test The leftmost column shows the count pattern used for data The count increments for even addresses and decrements on odd addresses With the PCltree read of BARO the data is the count value specified in the PCltree memory test The results No Errors are provided
11. parity 1 stop bit and None for flow control Click Apply and OK to open up the terminal console on the PC This terminal console is the user control point for the DMA initiator reference design Port Settings Bits per second 9600 v Data bits 8 v Parity None v Stop bits 1 v Flow control EENS v X1000_20_042108 Figure 20 HyperTerminal Port Settings for ML555 Communications XAPP1000 v1 0 1 May 6 2008 www xilinx com 15 Interfacing to a Communication Terminal XILINX The port number COMS is displayed as shown in Figure 21 Device Manager File Action view Help e gt amp R zaag 4 XAQLESTERSS Catalyst Test Tools 3 Computer S Disk drives 32 Display adapters lt 2 DVD CD ROM drives E Human Interface Devices IDE ATA ATAPI controllers gt Keyboards T5 Mice and other pointing devices Monitors E9 Network adapters OY Ports COM amp LPT I Communications Port COM1 HE H A E MR Processors E Programming cables Sound video and game controllers Storage volumes 3 System devices X1000_21_041408 Figure 21 Device Manager Communication Port If there are problems with the communication terminal review pages 35 44 of XAPP859 for a step by step description of setting up the ML555 to use a communication terminal Figure 22 shows the setup of Tera Term Using Tera Term or a similar serial communications u
12. 1 0 Length 1 ByteCount 0 LowerAddr 0x00 Payload 0x12345678 X1000_65_041408 Figure 65 ep2rce_mrd32 Figure 66 defines the functionality of the LeCroy Root Complex when receiving a MRd32 transaction from the PLBv46 Endpoint Bridge endpoint on the ML555 Wa LeCroy PETracer TM PCI Express Protocol Analyzer H lecroy ep2re_mrd32_1dw peg p E sie Setup Record Generate Report Search View Tools Window Help SHE PRM et 2 F RRT RA MK Oh Oe Infinite _ 3DW header no data MRd MWVr 0000 000 000 000 s I TLP CompleterlD o 10 01010 000 00 0 0 000 01 0 SC BCM Byte Cnt Lwr Addr LCRC 0 0 O00 12345678 OxDF6ACEB1 0000 000 000 000 s PETrainer ML SN 1102 see Link State InitFC State 25 646 23 0 Complete Ready Search X1000_66_041408 Figure 66 EP to RC MRd32 Test Stimuli 1 DW XAPP1000 v1 0 1 May 6 2008 www xilinx com 53 LeCroy Testing XILINX Figure 67 shows results from running the EP to RC memory read The peg is loaded Start recording by clicking on the Sun icon in the menu bar Click the Traffic Light icon Generate a 1 doubleword read using XMD mrd 0x20000000 1 Click the Black Square icon to stop recording and view the results Sec 8 x Pa Lec roy PETracer TM PCI Express Protocol Analyzer C Program Files CATC PETracer data1 157 pex File Setup Record Generate Report Search Yiew Tools Window Help E p WH e nt Ft QQB x 6 P ives MRd
13. 32 ia 0000000 1111 0000 Lwr Adar BEE o o 00 Link State InitFC State Complete XP PPR aa PETrainer ML SN 1102 En SS Bo Ready X1000_67_041408 Figure 67 EP to RC MRd32 Test Results 1 DW Figure 68 shows the ep2rc_mrd32_4dw peg for a four doubleword Endpoint to Root Complex MRd32 gt LeCroy PETracer TM PCI Express Protocol Analyzer H lecroy ep2re_mrd32_4dw peg E eile Setup Record Generate Report Search View Tools Window Help SHR PRM ent RATON RR Me OS A 3DW header no data MRd MWWr Packet TLP CompleterID o0 10 01010 000 00 0 0 000 01 0 Lwr Adar f Data sc o 0o 00 12345678 0000AAAA 87654321 FFFFOOOO InitFC State Complete PETrainer ML SN 1102 nee Link State B46 646 33 Ready X1000_68_041408 Figure 68 EP to RC MRd32 Test Stimuli 4 DW XAPP1000 v1 0 1 May 6 2008 www xilinx com 54 LeCroy Testing XILINX Figure 69 shows results from running the XMD command below mrd 0x20000000 4 5 LeCroy PETracer TM PCI Express Protocol Analyzer C Program Files CATC PETracer data1 157 pex EF File Setup Record Generate Report Search View Tools Window Help oh ey p HEE nt St RA ss OPP MK OLGS whe s J MRd 32 x on 00 00000 000 00 0 0 00000000 1111 0000 G1 CompleteriD x4 16 10 01010 000 00 0 0 000 01 0 SC Lwr Addr f Data o o 00 PETrainer ML SN 1102 Link State InitFC State
14. Bint Ta ed 5 B LO Complete Ready Search Fwd X1000_69_041408 Figure 69 EP to RC MRd32 Test Results 4 DW Endpoint to Root Complex Write Transactions Figure 70 shows the peg for the EP to RC MWr82 As with EP to RC memory reads start recording by clicking on the Sun icon and then click on the traffic light wait TLP TLPType MWr32 X1000_70_041408 Figure 70 ep2rc_wait_mwr32 peg Figure 71 shows LeCroy Root Complex setup for analyzing an Endpoint to Root Complex MWr32 operation gt LeCroy PETracer TM PCI Express Protocol Analyzer H lecroy ep2rc_wait_mwr32 peg File Setup Record Generate Report Search View Tools Window Help sH PRM o nt Ap RAB e ORR Ow OLB abe Time Stamp 0000 000 000 000s PETrainer ML SN 1102 InitFC State Fa f 2 Complete Ready Search Fwd X1000_71_041408 Figure 71 EP to RC Write Operation XAPP1000 v1 0 1 May 6 2008 www xilinx com 55 LeCroy Testing XILINX The xmd command below generates the stimuli for the PLBv46 Endpoint Bridge to transmit the TLP mwr 0x20000000 0x12345678 Figure 72 shows the Analyzer output for an EP to Root Complex Memory Write of 0x1234567 W LeCroy PETracer TM PCI Express Protocol Analyzer C Program Files CATC PETrace a OX E File Setup Record Generate Report Search View Tools Window Help la x AF Te AT R RRR op MVVir 32 a 10 0000 000 00 0_ 0 BE ist BE Last BE BIBETe 00000
15. C Slow Speed System Clock 1 25 2 5 Gbps iz c Full Speed System Clock supports Spread Spectrum Clocking Link Settings Transmitter Receiver Intemal Source gt 5 ce Scramble Bypass Polarity Reversal De Scramble Bypass Polarity Reversal a eose no support Spread Spectrum Physical Data Link Layers Status Physical Layer Status LTSSM CONFIGURATION Link Number O7 iwi 4 1S5 1413 12 IL10 9 8 F 6 S1720 LanePolaity tee e eet Data Link Layer Status DLCMSM INACTIVE Check All Clear Al if Advanced Options Link Status I Define different patterns for pre trigger and post trigger data captures Easy switch to Advanced mode Apply Settings Bun Analyzer 1 000E85000159 USB Not Triggered Exerciser Sto _ X1000_32_041408 Figure 32 Catalyst Link Settings XAPP1000 v1 0 1 May 6 2008 www xilinx com 25 Catalyst Testing XILINX Figure 33 is a graphical view of the stimuli for configuring the PLBv46 Endpoint Bridge including BAR 0 The m1555_mb_ plbv46_pcie catalyst directory contains the cfg_x4 sdc stimuli file The cfg_x4 sdc project is loaded using the File gt Open pull down menu The sdc files are readable text files which contains the transactions used as stimuli In cfg_x4 sdc the Device ID Vendor ID is read The Command Status register is written and read The Revision ID and Class Code
16. Complete XAPP1000 v1 0 1 May 6 2008 www xilinx com 10 Interfacing to a Communication Terminal XILINX CP210x USB to UART Second Driver Installation A second driver must be installed on the PC The Found New Hardware Wizard is again displayed on the PC Figure 13 1 Select No not this time and click Next to continue with driver installation Found New Hardware Wizard Welcome to the Found New Hardware Wizard Windows will search for current and updated software by looking on your computer on the hardware installation CD or on the Windows Update Web site with your permission Read our privacy policy Can Windows connect to Windows Update to search for software Yes this time only Ove w and every time connect a device Click Next to continue X1000_13_041408 Figure 13 Found New Hardware Wizard Second CP210x Driver Install 2 The driver for the CP210x USB to UART bridge controller must also be installed on the PC Select Install from a list or specific location Advanced as shown in Figure 14 Click Next to continue Found New Hardware Wizard This wizard helps you install software for CP2102 USB to UART Bridge Controller C If your hardware came with an installation CD lt gt or floppy disk insert it now What do you want the wizard to do Install the software automatically Recommended OF Click Next to continue X1000_14_041408 Figure 14 USB to UAR
17. Configuration Space FirstDwBe OxF First DW Byte Enables Length 1 1 DWORD Enumerate all 6 Base Address registers repeat Begin Count 6 Counter i Write OxFFFFFFFF into Base Address register packet MyCfgWrite Register 0x10 i 4 Wait for completion received wait TLP TLPType Cpl Read Base Address register packet MyCfgRead Register 0x10 i 4 Wait for completion received wait TLP TLPType CpID repeat End X1000_64_041408 Figure 64 PEG Example www xilinx com 52 LeCroy Testing gt XILINX Endpoint to Root Complex Transactions In Endpoint to Root Complex transactions the read and write operations originate from the ML555 and target the LeCroy The LeCroy model used in this application note ML does not have target memory For read operations the peg files are written to respond with read data Invoke PETracer and run File Open lecroy ep2rc_mrd32_1dw Endpoint to Root Complex transactions are generated with XMD commands or C code Since the MWr and MRd TLPs originate from the ML555 the LeCroy peg files cause the LeCroy to wait for the TLP s from the ML555 Figure 65 shows the peg for the EP to RC MRd32 The LeCroy waits for the MRd32 packet from the ML555 When the MRd32 packet is received the LeCroy returns a Completion with Data CpID packet with a 0x12345678 payload wait TLP TLPType MRd32 Packet TLP TLPType CpID CompleterID 0
18. New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for CP2101 USB Composite Device Click Finish to close the wizard Finish X1000_16_041408 Figure 16 Completion of Second CP210x Driver Installation XAPP1000 v1 0 1 May 6 2008 www xilinx com 12 Interfacing to a Communication Terminal gt XILINX Verification of USB to UART Driver Installation Verification of PC to ML555 communication requires the ML555 powered up in the system unit the reference design loaded into the Virtex 5 FPGA on the ML555 and a USB cable connected between the ML555 and the USB port of the PC hosting the remote DMA initiator terminal console If the ML555 is connected to the USB port of the PC but the reference design is not loaded into the Virtex 5 FPGA the CP210x USB to UART bridge controller port is not recognized by the device manager application software running on the PC To determine which COM port has been assigned to the USB to UART bridge controller attached to the ML555 board the COM port assignments must be known 1 Go into the Windows device manager by right clicking on My Computer gt Properties gt Hardware gt Device Manager gt Ports COM amp LPT to view the COM port assignments Knowledge of the COM port assignment for the CP210x USB to UART bridge controller is required when the HyperTerminal or TeraTerm application is started on the PC Figure 17 shows a
19. XILINX Figure 97 is the waveform output of a ChipScope inserted into the reference system when running the endpoint to root complex performance tests The chipscope ml555_mb_plbv46_pcie_scs vcd file can be used to view all of the signals more clearly S ChipScope Pro Analyzer 1_ep2rc_mpmc_2000 Eile View JTAG Chain Device TriggerSetup Waveform Window Help gt matl oo Project 1_ep2rc_mpmc_2000 JTAG Chain DEV 0 MyDeviced XC5VLX50T System Monitor Console UNIT 0 MyILAO ILA Trigger Setup Waveform Listing Bus Plot Signals DEV 0 UNIT 0 CH 02 xps CENTA Ota UM WIO CH 63 kkps_central_dma_O M_wrD CH 64 kps_central_dma_O M_wrD CH 65 xps_central_dma_O M_wrD CH 70 kps_central_dma_O M_wrD CH 71 xps_central_dma_O M_wrD CH 72 xps_central_dma_O M_wrDB _ CH 73 xps_central_dma_O M_wrDB CH 74 ixps_central_dma_O M_wrDI CH 75 kps_central_dma_O M_wrD CH 76 PCle_Bridge S _wrDAck CH 77 PCle_Bridge PLB_MVVrBTer CH 78 PCle_Bridge SI_wrBTerm CH 79 PCle_Bridge PLB_rdBurst CH 80 PCle_Bridge PLB_PAValid CH 81 PCle_Bridge SI_wrComp CH 82 PCle_Bridge PLB_RNW CH 83 PCle_Bridge PLB_MAddrAck CH 84 PCle_Bridge PLB_wrBurst CH 85 PCle_Bridge SIl_addrAck CH 86 PCle_Bridge S _wait CH 87 PCle_Bridge PLB_ABus lt 0 gt CH 88 PCle Bridge PLB_ABus lt 1 gt T MAND upload UU q 2 A waveform DEV 0 MyDevice0 XC5VLX50T UNIT 0 MyiLA0 ILA Bus Signa
20. cores into system ngc The flow for using the two debugging methods differs Below an outline of the steps for debugging at the system level is provided This is followed by a detailed list of steps for debugging at the core level Inserting ChipScope at the System Level The following steps insert the ChipScope cores into the system 1 In XPS select Hardware gt Generate Netlist 2 From the EDK shell in the implementation directory run ngcbuild i system ngc system2 ngc 3 Copy chipscope m1555 mb plbv46_ pcie cdc file to the project area usually either one directory above chipscope or the implementation directory 4 Invoke ChipScope Inserter To specify the input in the Input Design Netlist window browse to the system2 ngc file created in step 2 Define the Clock Trigger and Data signals in Inserter and generate the ICON and ILA cores 5 From ml555_mb_plbv46_pcie implementation copy the file displayed in the Inserter Output Design Netlist window usually implementation system2 ngo to implementation system ngc 6 In XPS run Hardware Generate Bitstream Inserting ChipScope in the PLBv46 Endpoint Bridge The m1555 mb plbv46 pcie chipscope plbv46_ pcie cdc file is used to insert a ChipScope ILA core into the pcie_bridge_wrapper core Do the following steps to insert a core and analyze PLBv46 Endpoint Bridge signals with ChipScope 1 Invoke XPS Run Hardware Generate Netlist 2 Copy chipscope plbv46 pcie cdc file
21. device manager screenshot depicting the ML555 COM port assigned to COM3 Device Manager Action View Help TS e arza GODZILLA018 1 Computer amp Disk drives 32 Display adapters 4 DVD CD ROM drives 4 Floppy disk controllers QB Floppy disk drives Qj Human Interface Devices jy IDE ATA ATAPI controllers IEEE 1394 Bus host controllers Keyboards Mice and other pointing devices Monitors B Network adapters Ports COM amp LPT Communications Port COM1 F CP2101 USB to UART Bridge Controller COM3 ov ECP Printer Port LPT1 R Processors amp SCSI and RAID controllers Sound video and game controllers X1000_17_041408 Figure 17 Windows Device Manager COM Port Assignment 2 To uninstall the Silicon Laboratories VCP drivers from the PC go to Start gt Control Panel gt Add or Remove Programs Microsoft Windows searches for all software applications installed on the PC and presents a list of installed applications for user selection Scroll down and select the CP210x USB to UART bridge controller driver to be removed If installing a newer version of the VCP driver remove the older driver version driver before installing a newer driver version on the PC The reference design was hardware verified using version 3 1 of the Silicon Laboratories VCP driver with the production silicon version of the ML555 XAPP1000 v1 0 1 May 6 2008 www xilinx com 13 Interfacing to a Communi
22. gt Nx of ConfRegs Other Memory hex 16 64 O gt 4 4 PCI PCI Br Ethernet Netwe use BIOS int aration ae nal Write ConfReg refresh O niversal Host Cor dump Universal Host Cor refr after wr Universal Host Cor Config Space Dump type 1 xs DID VID o serial bus Dev gt i O gt S 5 Subtractive Stat Cmd PCI ISA Bridge De BaseClass SubClass I o Mass Storage Ci BIST Header LatTimer o Mass Storage Cc BAR O mem pref 64bi SMBus Serial Bus BAR 1 BAR Z 3 4 5 Dz 0 gs 0 0 Qo z 0 Qo BAR BAR BAR Cardbus _CIS_ Ptr SubID SubVendorID Exp_ROM_BAR reserved reserved maxLat minGnt IntPir rescan write to reset j X1000_81_041408 Figure 81 PCltree Scan To edit the registers in the Configuration Space Header CSH highlight the register in the CSH to edit and provide a value in the Edit ConfReg dialog box As an example select the Command Status Register write OxFFFFFFFF in the Edit ConfReg dialog box click Write ConfReg and click Refresh Dump to see the new value of the Command Status Register CSR displayed The new value of the CSR is not OxFFFFFFFF as some of the CSR bits are reserved XAPP1000 v1 0 1 May 6 2008 www xilinx com 65 PCltree Testing lt XILINX Click BARO and use the edit ConfReg dialog box to change the BARO value to xE000000C Click Write ConfReg and then Refresh Dump The new value of BARO is disp
23. mhs and addressed with the PLBv46 Endpoint Bridge C_PCIBAR2IPIFBAR_ generics In this reference system two PLBv46 Endpoint Bridge BARs are active The C_PCIBAR2IPIFBAR_0O generic points to the ML555 BRAM located at 0x8AE10000 After writing the ML555 BRAM using PCI tree Edit Memory XMD can be used to verify BRAM or DDR2 if the BAR is enabled from the PLBv46 side XAPP1000 v1 0 1 May 6 2008 www xilinx com 69 PCltree Testing XILINX shows verification that the XPS BRAM contains the data written by PCltree using XMD commands BEE 85C82614 6680808 85C02018 86668608 85C02A1C 15 5 515 5 15 5 AMD mrd x8AE16808 8 6660608 1151515 5 515 5 66680008 6080808 86680808 86660608 96680808 115 515 5 1515 5 RMDZ mrd x8AE16606 8 SAE1 6606 66680008 SAE16004 FFFFFFFF SAE1 688 62660608 SAE1GQGC FDFFFFFF SAE16616 64660608 FBFFFFFF 46660608 F9FFFFFF X1000_86_041408 Figure 86 XMD Verification of PCltree Write Operation In the next two figures XMD is used to write XPS BRAM which is then re read by PCltree shows the writing and reading of 0x12345678 to the first four locations in XPS BRAM BEE SAE16018 gallalaus SAE1 1C M15 1515 515 5 AMD mrd x8AE16086 8 SAE1 6606 66080808 SAE1 6004 FFFFFFFF SAE1 6008 626808068 SAE1 GC FDFFFFFF SAE16616 64660606 SAE16614 FBFFFFFF SAE16 18 666806008 SAE1 1C F9FFFFFF RMD mur x8AE1 606 x12345678
24. no data Config Read TO Boom TTT Last DW BE H First DW BE H Bus Num H Dev Num H Func Num H Regi Num shad ee I Define different pattems for pre trigger and post trigger data captures Easy switch to Advanced mode Apply Settings Run Analyzer 1 000E85000159 USB Not Triggered Exerciser Stop Analyzer Stop 7 X1000_33_041408 Figure 33 Catalyst Configuration Stimuli XAPP1000 v1 0 1 May 6 2008 www xilinx com 26 Catalyst Testing XILINX Figure 34 shows the Analyzer output after running cfg_x4 The results are contained in the cfg_x4 ssf file Registers in the Configuration Space Header are displayed in packet 0 using Vendor ID and Device ID symbolic names with Xilinx 0x10EE and 0x0505 values The Command Status Register is read The SC in the status field indicates successful completion of the transaction In the figure the Revision ID and Class Code Register field is expanded to provide a readable table of the values in the Data field ata erprise PX Analyze e er So e g x4 5 G File Edit view Configuration Tools Filtering Report Window Help a x 0 2908 touas seis m B G PL gt mbBE PP Olpla gt ee BlB e a e 8 Pala u 33k Ho owe FEL rts RE X T 000 000 000 360 we D Type Len H Req ID H Tag H Last DW BE H First DW BE H Bus Num H
25. of XMD to read ML555 DDR2 memory to provide a second verification that the wr_rd_x4 sdc script functioned as intended The data read in XMD should be the same as the data in the Analyzer waveform display mmand Prompt xmd AMD mrd 6x 6660008 20000000 12345678 RMD mrd 6x 6660688 8 7 6668086 12345678 12345678 AASSAASS AASSAASS AASSAASS AASSAASS AASSAASS AASSAASS X1000_23_041408 Figure 39 Verifying Root Complex to Endpoint Transactions with XMD Using Catalyst Catalyst is used for performance testing This section provides performance tests for Root to test PCle Complex to Endpoint transactions first for read transactions and then for write transactions The test setup is defined and then performance results are given for various lengths for 32 and Performance 64 bit transactions Figure 40 shows the physical link setup for the performance test For the ml555_mb_plbv46_pcie project change the Physical Layer Settings Link Width to x4 Catalyst Enterprises Inc SPX Analyzer Exerciser Software cfg_x4 Fie Edit View Configuration Tools Project Setup Window Help Di SaaS l a a B8 O p in KBE Exerciser Program Capture Trigger On Link Settings Settings gt OF E h Physical Layer Settings Link Width C x2 G XA Link Settings Transmitter Scramble Bypass Polarity Reversal Receiver De Scramble Bypass C XIE SPX Reference Clock Slow Speed System Clock 1 1 25 Gbps C S
26. provided The principal intent of the performance testing is to illustrate how performance measurements can be done Two stand alone tools PCltree and Memory Endpoint Test are used to write and read PLBv46 Endpoint Bridge configuration space and memory in a PC environment This is the least expensive and easiest to use hardware test environment The use of the ChipScope tool in debugging PLBv46 Endpoint Bridge issues is described The reference system for the PLBv46 Endpoint Bridge in the ML555 PCI PCI Express Development Platform is available at http www xilinx com support documentation application_notes xapp1000 zip The zip file contains the reference system which is described on page 2 of this application note The ml555_mb_plbv46_pcie project uses the PLBv46 Endpoint Bridge configured with four PCle lanes To change this to a reference x1 lane system change the PLBv46 Endpoint Bridge C_NO_OF_LANES generic to 1 The PLBv46 Endpoint Bridge is an endpoint instantiated in a Xilinx FPGA which communicates with a root complex The reference systems are tested using commercial test equipment from LeCroy and Catalyst LeCroy and Catalysts are two Analyzers Exercisers used to verify PCle systems The Catalyst and LeCroy testers allow generation analysis capture and triggering of Translation Layer Data Link Layer and Physical Layer packets The reference systems are also tested in two test environments which are inexpensive and PC base
27. regions DMA transactions are generated by writing to the Control Source Address Destination Address and Length registers of the DMA controller Table 4 provides the register locations for the XPS Central DMA In the reference design C_BASEADDR is set to 0x80200000 Table 4 XPS Central DMA Registers DMA Register Address Control Register C_BASEADDR 0x04 Source Address Register C_BASEADDR 0x08 Destination Address Register C_BASEADDR 0x0c Length Register C_BASEADDR 0x10 XAPP1000 v1 0 1 May 6 2008 www xilinx com 20 Endpoint to Root Complex Transactions XILINX The pcie_dma c code consists of the four functions in the functional diagram in Figure 26 The Barberpole Region function provides a rotating data pattern in the memory located at the source address The Zero Region function sets the memory located at the destination address to all zeroes The DMA Region function generates a DMA transaction of data located at the source address to the memory at the destination address Following the DMA transfer the Verify function verifies that data at the source and destination address are equal Barberpole X1000_26_041408 Figure 26 Functional diagram of pcie_dma c Figure 27 show the communication terminal output when running the pcie_dma executable elf t HyperTerminal DMASrc 20000000 Dest 20002000 DMAlength words O000008b lt DHASrc 2000002c Dest 2000202c DMAlength wor
28. the reference design PCI BARO is written as 0x0000000060000000 C_PCIBAR2IPIFBAR_0 addresses XPS BRAM at 0x8AE10000 and C_PCIBAR2IPIFBAR_1 addresses DDR2 at location 0x90000000 ML555 XPS BRAM PLBv46 PCle OPPE TOON LeCroy PCle x4 C_PCIBAR2IPIFBARO 0x8AE10000 C_PCIBAR2IPIFBAR1 0x90000000 MPMC DDR2 Root Complex 0x90000000 End Point X1000_59_041408 Figure 59 LeCroy Complex The display area shows the TLPs defined in the peg file Figure 60 shows an excerpt from the lc_rc2ep_wr_rd peg file The Ic_rc2ep_wr_rd peg shown is writes FFFFFFFFs to the six BAR registers in the Configuration Space header This is done using the Repeat construct The first register written is BARO located at offset 0x10 a LeCroy PETracer TM PCI Express Protocol Analyzer H lecroy lc_rc2ep_wr_rd peg File Setup Record Generate Report Search Yiew Tools Window Help Sne p BH ont yp AQEB x Time Stamp 0000 000 000 000 s Idle Fo Time TA Infinite 3DW 3DW header no data no data Cpl CpID 0000 000 000 024 s 000 000 024 s JE C1 Cf CfgRd0 ist BE 0 s 00 00100 000 00 0 000 00 0 0x010 tot Time Stamp Ox4ED12154 0 000 ns 0000 000000 024 s Crete Infinite 3DVV header with data Cpl CpID 0000 000 000 044 s Repeat End 0 0000 000 000 264 s Packet ci LP ie Cfg Wi e jister 1st BE MRS 26 o ie 10 00100 oo0 00 0 o oo0 00 0 oxo10 1111 LCRC Idle Time Stamp OxFAN62642 0 000
29. to the project area usually either one directory above chipscope or the implementation directory 3 Run Start gt Programs ChipScope Pro gt ChipScope Inserter XAPP1000 v1 0 1 May 6 2008 www xilinx com 74 Using ChipScope with the PLBv46 Endpoint Bridge XILINX 4 From ChipScope Inserter run File Open plbv46_pcie cdc Figure 91 shows the ChipScope Inserter setup GUI after File Open plbv46_pcie cdc ChipScope Pro Core Inserter plbv46_pcie cde Ox File Edit Insert Help EW o DEVICE Select Device Options Design Files Input Design Netlist b_plbv46_pcie_cs implementation pcie_bridge_wrappe Browse Output Design Netlist b_plbv46_pcie_cs implementation pcie_bridge_wrapper Browse Core Utilization i tch i l b_plbv46_pci impl t Core resource stimadon is Output Directory scratch designs mi555_mb_plbv46_pcie_cs implemeni Browse currently not available for this architecture Device Settings Device Family VirtexS y Use SRL16s V Use RPMs Previous copy scratch designs mi555_mb_plbv46_pcie_cs implementation pcie_bridge_wrapper ngc gt scratch designs mI555_mb_plov46_pcie_cs implementation pcie_bridge_wrapper_signalbrowser ngo SetDesign pcie_bridge_wrapper show SignalBrowserDialog X1000_91_041408 Figure 91 Opening plbv46_pcie cd
30. www xilinx com 35 Using Catalyst to test PCle Performance XILINX Figure 45 shows the performance of MRd32 transactions of length 3 The data and payload throughput are 114 6MB s and 15 4 MB s Catalyst Enterprises Inc SPX Analyzer Exerciser Software PerformanceAnalyzer3 Carats DER Fie Edit View Configuration Tools Project Setup Window Help 0 5208 mj erm m B2 2 en KAET Kellee Ia E Link Chart Average Payload 0 X _ Link Chart Throughput uje fe iafe fi p 2282 Throughputci14 6 MB Sec J 2021298 Payload 00 Bytes et Bl 22vload Throughput15 4 MB Sec PerformanceAnalyzer3 BEE Exerciser Program Performance Items Link Settings Setting ra mle jee x seat Fmd type Te ow FO ae First DW BE H Addr H Digest H LCRC H K Sym H Analyzer 1 000E85000159 USB Exerciser Stop Analyzer Stop X1000_45_041408 Global Loop lr NoLoop C Count Ee Continuous Figure 45 MRd32 Performance Results Length 3 XAPP1000 v1 0 1 May 6 2008 www xilinx com 36 Using Catalyst to test PCle Performance XILINX Root Complex to Endpoint Write Transactions Figure 46 shows a write transaction The length field is set to 020H or 128 bytes The data written is an Upcount pattern The Continuous radio button is selected Catalyst Enterprises Inc SPX Analyzer Exerciser Software rc2ep_wr64 File Ed
31. 00 000 00 0 000 00 0 0x010 f 4111 51 CfgRd0 1st BE 00 00100 000 00 0 000 00 0 oxo14 f 1111 a Dare 000 00 0 60000000 1111 0000 2 000 00 0 60000000 1141 0000 12345678 a ae 000 00 0 60000000 _ 1111 0000 wi InitFC State Complete Search Fwd X1000_61_041408 Figure 61 Configuring and Testing BARO XAPP1000 v1 0 1 May 6 2008 www xilinx com 50 LeCroy Testing gt XILINX Figure 62 shows the results after running rc2ep_cfg_wr_rd_bar0 peg Packet 9 is a MWr32 of 0x12345678 to address 0x0000000060000000 This address is translated using the generic C_PCIBAR2IPIFBARO to the XPS BRAM at 0x8AE10000 In packet 12 the data value 0x12345678 is returned in the CpID packet The status fields indicate Successful Completion SC 5 LeCroy PETracer TM PCI Express Protocol Analyzer C Program Files CATC PETracer data1 157 pex File Setup Record Generate Report Search View Tools Window Help cH PRB en AH Ft RRE HeC ETE RA eR inven MaKe ist BE Last BE ee 00 00000 000 00 0 60000000 1111 0000 mer MWr 32 ist BE Last BE a 10 00000 000 00 0 60000000 1111 0000 CompleteriD a 10 01010 000 00 0 0 000 00 0 oC 0 12345678 1st BE 00 00000 000 00 0 0 60000000 1111 0000 CompleterID BCM 10 01010 000 00 0 0 000 00 0 Sc 0 Data 0x00 Link State InitFC State Complete Search Fwd X10
32. 000 0x0 100 set DMASR mrd 0x80200014 1 set DMASR_BUSY 0x40000000 puts outfile DMA Status Register DMASR while 1 for set i 1 i lt 1000 incr i if SDMASR DMASR_BUSY puts outfile mwr 0x80200010 64 puts outfile mrd 0x20000000 100 puts outfile mrd 0x20002000 100 close outtfile exit X1000_49_041408 Figure 49 dma tcl XAPP1000 v1 0 1 May 6 2008 www xilinx com 40 Endpoint to Root Complex Transactions XILINX Figure 50 shows the Catalyst SPX4 Analyzer Exerciser output after running the ep2rc_ performance analyzer project The payload throughput depends on various factors such as the size of the transfer if print statements are included in the source code and if the verification is Spf included in the source code For this run all print statements are removed there is no verification and length is set to 20 This is a hex value of doublewords so the TLP lenght is 128 bytes The transfer is from XPS BRAM to Catalyst memory across the PCle link The data throughput is 19 0 MB s and the payload throughput is 8 3 MB s Catalyst Enterprises Inc SPX Analyzer Exerciser Software per_ep2rc_x1 Seiwa Toos Project Setup Window Help D 58408 u a gt m m B2 2 tn A AEDS E J 2v2129 Pavioad a0 05 Bytes per_ep2rc_x1 Exerciser Program Performance Items Link Settings Setting Items Group Report Direction DLink u i H o Link Utization
33. 000 1111 0000 Link State InitFC State LO Complete X1000_72_041408 Figure 72 EP to RC Write Results The write operation is easily varied using XMD The XMD command below writes eight locations mwr 0x20000000 0x12345678 8 XAPP1000 v1 0 1 May 6 2008 www xilinx com 56 LeCroy Testing XILINX Figure 73 shows the results from running the eight doubleword Endpoint to Root Complex write transaction 5 LeCroy PETracer TM PCI Express Protocol Analyzer C Program Files CATC PETracer data1 157 pex BF File Setup Record Generate Report Search View Tools Window Help SUE PHE em A B A QB eR a EL ab eX el Pet Unk Spi liven 2 ist BE Last BE is 10 0000 000 00 0 00000000 1111 0000 12345678 Packet ANC me 2 1st BE Last BE x4 d5 000 00 0 00000004 1111 0000 12345678 Packet ist BE BE Last BE 2 000 00 0 00000008 1111 0000 12345678 Packet Mam 1st BE BE Last BE 3 im 000 00 0 0000000C 111 0000 12345678 Packet 2 1st BE Last BE 000 00 0 00000010 111 0000 12345678 Morn ist BE BE Last BE ai 000 00 0 00000014 111 0000 12345678 Packet MVVr 32 ist BE E Last BE 6 0 00000 000 00 0 00000018 111 0000 12345678 Packet Mem viWir 32 1st BE Last BE 7 28 2 0 00000 000 00 0 0000001C 111 0000 12345678 la PE Trainer ML SN 1102 Link State _ InitFC State EFA 5 25 0 Complete Ready Search Fwd
34. 00_62_041808 Figure 62 BARO Test Results Figure 63 shows the verification of the Endpoint to Root Complex PCle transactions using XMD In the system mhs the PLBv46 Endpoint Bridge generic C_PCIBAR2IPIFBARO is 0x8AE10000 the location of XPS BRAM This shows that the 0x12346578 written by the LeCroy Root Complex MWr64 TLP is resident in XPS BRAM c lt Command Prompt xmd AMD mrd x aei 8 SAE1 6606 12345678 SAE1 6604 66606608 SAE1 0688 66606608 SAE1G0GC 66660000 SAE16616 96680088 66660806 98060608 9a880088 X1000_63_041408 Figure 63 XMD Verification of BARO Tests XAPP1000 v1 0 1 May 6 2008 www xilinx com 51 LeCroy Testing XAPP1000 v1 0 1 May 6 2008 2 XILINX Figure 64 shows an excerpt of a peg file The peg file used as stimuli in LeCroy transactions is readable and editable In the figure templates are defined for Configuration Write and Configuration Read TLPs The Configuration Write template is called in the repeat loop to write FFFFFFFFs to the six Configuration Space Header BARs The peg files inm1555 mb plbv46 pcie lecroy can be used to test the PLBv46 Endpoint Bridge on the ML555 template TLP Name MyCfgWrite Template name TlpType CfgWr0 Write device Configuration Space FirstDwBe OxF First DW Byte Enables Length 1 1 DWORD Payload OxFFFFFFFF template TLP Name MyCfgRead Template name TlpType CfgRdO Read device
35. 11 gt 17 Sl_rdDBus lt 12 gt 18 SI_rdDBus lt 13 gt Trigger Condition Name Trigger Condition Equation 219 SI_rdDBus lt 14 gt TriggerConditionO Mo 20 SI_rdDBus lt 15 gt Type Window Vv Windows 1 Depth Position 0 21 SI_rdDBus lt 16 gt Storage Qualification All Data PL gt lt 2 lt gt lt gt lt gt lt gt lt gt x 22 S _rdDBus lt 17 gt 23 SI_rdDBus lt 18 gt 24 SI_rdDBus lt 19 gt aindega a gt COMMAND upload 0 0 INFO Device 0 Unit 0 Waiting for core to be armed Upload X1000_94 041408 Figure 94 ChipScope Analyzer Trigger Setup XAPP1000 v1 0 1 May 6 2008 www xilinx com 78 Using ChipScope with the PLBv46 Endpoint Bridge XILINX 12 Arm the trigger by selecting Trigger Setup Arm or clicking on the Arm icon as shown in Figure 95 Si ChipScope Pro Analyzer ml1555_mb_plbv46_pcie Eile View JTAG Chain Device TriggerSetup Waveform Window Help adormi Project mI555_mb_plbv46_pcie tigger Setup DEV 0 MyDevice0 XC5VLX507 UNIT 0 MyILAO ILA JTAG Chain z DEV 0 MyDeviced XC5VLX50T fi ial Function Counter System Monitor Console EI Mo TriggerPorta disabled UNIT O MyILAO ILA Ci Sl_addrAck Trigger Setup C PLe_Pavalic ce Ey ssiraDack BuSPlot 3 Cy PLB_MAddrA QA
36. 2 Click Next to continue InstallShield Wizard Welcome to the InstallShield Wizard for Silicon Laboratories CP210x Evaluation Kit Tools The InstallShield Wizard will install Silicon Laboratories CP210x Evaluation Kit Tools Release 3 1 on your computer To continue click Next X1000_05_041408 Figure 5 Silicon Laboratories CP210x InstallShield Wizard 3 Review the Silicon Laboratories software license agreement Click Yes to accept all the terms and conditions of the license agreement as shown in Figure 6 InstallShield Wizard License Agreement Please read the following license agreement carefully Press the PAGE DOWN key to see the rest of the agreement SILICON LABORATORIES INC SOFTWARE LICENSE AGREEMENT Licensee and Silicon Laboratories Inc Silicon Labs located at 4635 Boston Lane Austin Texas 78735 collectively the Parties or individually a Party hereby enter into this Software License Agreement in accordance the Terms and Conditions the TERMS AND CONDITIONS Do you accept all the terms of the preceding License Agreement If you choose No the setup will close To install Silicon Laboratories CP210x Evaluation Kit Tools Release 3 1 you must accept this agreement lt Back x No X1000_06_041408 Figure 6 Silicon Laboratories License Agreement XAPP1000 v1 0 1 May 6 2008 www xilinx com 7 Interfacing to a Communication Terminal XILINX 4 Click Next to accep
37. 4 RMDZ mrd x8AE16608 8 SAE1 6006 12345678 SAE16004 12345678 SAE1 6608 12345678 SAE1G GC 12345678 SAE1 6616 64660606 FBFFFFFF 66660606 F9FFFFFF X1000_87_041408 Figure 87 Writing XPS BRAM using XMD XAPP1000 v1 0 1 May 6 2008 70 Memory Endpoint Test XILINX Figure 88 shows a PCltree read of XPS BRAM The first four locations are read as 0x12345678 BAR space 78563412 78563412 78563412 78563412 oooo00004 FFFFFFFB oooo0006 FFFFFFF9 00000008 FFFFFFF ooooo00a FFFFFFFS oooooo00c FFFFFFF3 oooo000E FFFFFFF1 00000010 FFFFFFEF ooo00012 FFFFFFED 00000014 FFFFFFEB 00000016 FFFFFFE9 00000018 FFFFFFE oooo001a lt x00000000 gt x00000004 gt lt x00000008 gt lt x0000000C gt x00000010 gt lt x00000014 gt x00000018 gt x0000001C gt lt x000000Z0 gt x00000024 gt lt x000000Z8 gt lt x000000Z2C gt x00000030 gt lt x00000034 gt lt x00000038 gt x0000003C gt lt x00000040 gt x00000044 gt x00000048 gt lt x0000004C gt x000000S0 gt x000000S4 gt lt x000000S8 gt lt x000000SC gt x00000060 gt lt x00000064 gt x00000068 gt V auto read memory Memory Space typeZ prefetchable base 0000000 range ffff0000 64 KByte 64bit BARs not supported yet edit memory Data toggle eee Write Memory l count wel verif loop on off refresh view after write mem copy source destination mem copy sel
38. 52 Bits used File mISSS_mb_plbv46_pcie in Location H designs ml555_mb_plbv46_pcie X1000_79_041408 Figure 79 Selecting Generate File The recommended configuration mode is Master SelectMap which is specified when the configuration Mode Switch SW5 should be set to MO 0 ON M1 0 M2 1 Use Impact to download the mcs file into the ML555 XCF32 PROM Select the XCF32P left click to invoke a menu and select Program Under the Programming Properties menu check Parallel Mode under the PROM Specific Properties Insert the ML555 into the PCle slot and power on the PC Verify that the DONE LED lights It is possible to configure the FPGA after PC power up using the JTAG mode but a warm reset is usually required for the ML555 PLBv46 Endpoint Bridge to be recognized in a PCI scan A warm reset is a PC Shutdown with Restart PCltree Testing PCltree is shareware available from http www pcitree de It runs on Windows XP PCltree can be used for either PCI or PCle tests In the tests described in this section the ML555 PCI PCI Express Development Platform is inserted into a Dell 390 x8 slot for the ml555_mb_plbv46_pcie project Invoke XMD and enable the master and the BARs by writing to the PLBv46 Endpoint Bridge Bridge Control Register mwr 0x85C001E0 0x003F0107 XAPP1000 v1 0 1 May 6 2008 www xilinx com 63 PCltree Testing XILINX Figure 80 shows the XMD output when the PLBv46 Endpoint Bridge configuration space
39. BTerm CH 14 SI_rdDBus lt 9 CH 15 SI_rdDBus 10 gt CH 16 SI_rdDBus 11 gt J M RNW CH 17 Sl_rdDBus lt 12 gt CH 18 SI_rdDBus 13 CH 19 SI_rdDBus 14 gt CH 20 SI_rdDBus lt 15 gt CH 21 SI_rdDBus 16 gt CH 22 SI_rdDBus 17 gt CH 23 SI_rdDBus lt 18 gt CH 24 SI_rdDBus lt 19 gt x T gt a x 0 0 M_request PLB_PAValid PLB_wrBurst 1_rdComp a gt COMMAND upload 0 0 INFO Device 0 Unit 0 Waiting for core to be armed Upload X1000_96_041408 Figure 96 ChipScope Pro Analyzer Triggered To share the results with remote colleagues save the results in the waveform window as a Value Change Dump vcd file The vcd files can be translated and viewed in most simulators The ved2wlf translator in ModelSim reads a vcd file and generates a waveform log file wif file for viewing in the ModelSim waveform viewer The vcd file is opened in the Cadence Design System Inc Simvision design tool by selecting File Open Database After running ChipScope it is sometimes necessary to revise the Trigger or Data nets or both used in a debug operation Saving Inserter and Analyzer projects simplifies this procedure The saved project can be re opened in Inserter and edits can be made XAPP1000 v1 0 1 May 6 2008 www xilinx com 80 Using ChipScope with the PLBv46 Endpoint Bridge
40. Base Address Registers BARs amp Command Prompt xmd INo of PC Breakpoints INo of Read Addr Data ch No of Write Addr Data Watchpoin 0 Instruction Cache Support on Instruction Cache Base Addre 6x 6606006 Instruction Cache High Addre XIFFFFFFF PU eee eee ee On ES 4x 6666606 TATE OxXIFFFFFFF E off TOTOO off Saana off on Mul32 gt ff Data Cache High Addr Exceptions Support PU SU WG cals evaceiace aiavare ace Hard Divider Support Hard Multiplier Support MDM UART Target mb target id 6 server for mb target Cid gt at TCP port no 1234 System reset successfully MDZ mur x85CGG1e8 Ox8O3f 6187 XMDZ Figure 30 Writing the Bridge Control Register X1000_30_041408 XAPP1000 v1 0 1 May 6 2008 www xilinx com 23 Catalyst Testing XILINX Five tabs are used to setup the Catalyst PCle Bus Protocol Analyzer Exerciser Figure 31 shows Catalyst Capture settings The option selected is to Capture Everything except Idles In the Trigger On tab select Pattern and Trigger on TLP Any Type Select Any Direction In the Settings tab specify the name of the output ssf file Catalyst Enterprises Inc SPX Analyzer Exerciser Software cfg_x4 MS Edit View Configuration Tools Project Setup Window Help D SREST OHAJ FF els gt OB B LHR BRE CR OP e Sou Exerciser Program Capture Trigger On Link Settings Settings Pr
41. IM Link Aggregate D1 Transmission Efficiency I Upstream Transmit l J Throughput I Downstream Receive Average Payload C Number of Packets C Latency Analyzer 1 000E85000159 USB J Data Throughputt19 0 MB Sec By Payload Throughput 3 MB Sec CoR Exerciser Stop Analyzer Run X1000_50_041408 Figure 50 EP to RC Performance Length 20 XAPP1000 v1 0 1 May 6 2008 www xilinx com 41 LeCroy Testing LeCroy Testing XILINX Figure 51 shows the performance of an Endpoint to Root Complex transaction using C code pcie_dma_0 c to generate stimuli with the length 200 The data throughput is 61 8 MB s and the payload throughput is 36 8 MB s In this test the Source Address is XPS BRAM which is 0x8AE10000 and the Destination Address is written to 0x20000000 which translates to Catalyst memory across the PCle link Catalyst Enterprises Inc SPX Analyzer Exerciser Software per_ep2rc_x1 O sBHS ula gt m m B E e n RAED OFE Link Chart Average Payload J Data ThoughputG16 MB Sec Payload Throughput 36 8 MB Sec J Aereo Payload61 54 Bytes per_ep2rc_x1 Exerciser Program Performance Items Link Settings Setting Items Group Report Direction C Link Usage Pia C Link Utiization Link Aggregate O Transmission Efficiency IF Upstream Transmit EY Throughput F Downstream Receive Average Payload C Number of Packets C Latency
42. JM_wrBurst Signals DEV 0 UNIT 0 Csi wrComp Data Port C Sl_racomp fo Misr Bus QO S _wrBTerm IS _rdDBus CH 0 SI_addtack M _rdBurst CH 1 SI_rdDAck 0 Sl _wrDAck CH 2 Sl_wait CH 3 SI_rdBTerm CH 4 PLB_RNW CH 6 SI_rdDBus lt 0 CH 6 SI_rdDBus lt 1 gt CH SI_rdDBus lt 2 gt CH 8 SI_rdDBus lt 3 gt CH 9 SI_rdDBus 4 gt CH 10 SI_rdDBus lt 5 gt CH 11 SI_rdDBus lt 6 gt CH 12 SI_rdDBus lt 7 gt CH 13 SI_rdDBus lt 8 gt CH 14 SI_rdDBus lt 9 gt CH 15 SI _rdDBus lt 10 gt CH 16 SI_rdDBus lt 11 gt CH 17 S _rdDBus lt 12 gt CH 18 SI_rdDBus lt 13 gt Add Active Trigger Condition Name Trigger Condition Equation CH 19 SI_rdDBus lt 1 4 gt HT Del TriggerConditiond MO CH 20 Sl_rdDBus lt 15 gt Type Window Windows 1 Depth 1024 w Position i CH 22 SI_rdDBus lt 17 gt ay window x p CH 23 SI_rdDBus lt 18 gt CH 24 SI_rdDBus 19 gt x PRL gt lt gt lt X lt gt X lt X lt gt lt gt x lt Storage Qualification All Data ar COMMAND set_storage_condition 0 0 FFFF COMMAND run 0 0 Device 0 Unit O Waiting for trigger Sample Buffer has 0 samples 0 X1000_95_041408 Figure 95 ChipScope Analyzer with Trigger Armed 13 Run XMD or GDB to trigger patterns which cause ChipScope to display waveform outp
43. ND save_project C Xilinx ChipScope_Pro_9_2itbin ntim1555_mb_plbv46_pcie cpj Writing project file C dlindChipScope_Pro_9_2itbinintiml555_mb_plbv46_pcie cpj X1000_93_041408 Figure 93 ChipScope Pro Analyzer Waveform XAPP1000 v1 0 1 May 6 2008 www xilinx com 77 Using ChipScope with the PLBv46 Endpoint Bridge XILINX 11 Set the trigger in the Trigger Setup window as shown in Figure 94 The trigger used depends on the problem being debugged Simple triggers are PA_Valid SI_AddrAck Sl_wrComp i ChipScope Pro Analyzer m1555_mb_plbv46_pcie File View JTAG Chain Device TriggerSetup Waveform Window Help o Ty Project mi555_mb_plbv46_pcie JTAG Chain DEV 0 MyDeviced XC5VLX50T Match Unit Function Counter System Monitor Console 9 CI MoTriggerPortd _ 0001 3 disabled UNIT O MyILAO ILA O sSi_adarack Trigger Setup CI sPLB_Pavalid Waveform C SLraDack Listing Bus Plot C PLe_madara Q M_wrBurst Signals DEV 0 UNIT 0 C sS1_wrComp 9 Data Port C sSl_racomp iM_wrDBus C Si wrBTerm ISl_rdDBus CH 0 Sl_addrAck E mM _rdBurst 1 ISI_rdDAck O ssiwrDack 2 5l _wait 3 S _rdBTerm 4 PLB_RNVW 5 8l _rdDBus lt 0 gt 6 SI_rdDBus lt 1 gt 7 ISIrdDBus lt 2 gt gt 8 SI_rdDBus lt 3 gt 9 SI_rdDBus lt 4 gt 10 SI_rdDBus lt 5 gt 11 fSI_rdDBus lt 6 gt 128l _rdDBus 7 gt 213 SIrdDBus lt 8 gt 14 SIrdDBus lt 9 gt 15 SI_rdDBus lt 10 gt 16 SI_rdDBus lt
44. PC recognizes new hardware attached to the computer and displays the Found New Hardware Wizard as shown in Figure 9 Select No not this time and click Next to continue with driver installation Found New Hardware Wizard Welcome to the Found New Hardware Wizard Windows will search for current and updated software by looking on your computer on the hardware installation CD or on the Windows Update Web site with your permission Read our privacy policy Can Windows connect to Windows Update to search for software Yes this time only O Yes now and every time connect a device Click Next to continue X1000_09_041408 Figure 9 Found New Hardware Wizard 2 Select Install from a list or specific location Advanced as shown in Figure 10 Click Next to continue Found New Hardware Wizard This wizard helps you install software for CP2102 USB to UART Bridge Controller If your hardware came with an installation CD lt gt or floppy disk insert it now What do you want the wizard to do O Install the software automatically Recommended OFT Click Next to continue X1000_10_041408 Figure 10 New Hardware Wizard Install from a Specific Location XAPP1000 v1 0 1 May 6 2008 www xilinx com 9 Interfacing to a Communication Terminal gt XILINX 3 Select Search for the best driver in these locations and select Include this location in the search Figure 11 Browse to the
45. T Bridge Controller Driver Installation Wizard XAPP1000 v1 0 1 May 6 2008 www xilinx com 11 Interfacing to a Communication Terminal gt XILINX 3 Select Search for the best driver in these locations and select Include this location in the search Figure 15 Browse to the directory that contains the CP210x drivers or enter C SiLabs MCU CP210x WIN Click Next to continue Found New Hardware Wizard Please choose your search and installation options tax Y Search for the best driver in these locations Use the check boxes below to limit or expand the default search which includes local paths and removable media The best driver found will be installed C Search removable media floppy CD ROM Include this location in the search C SiLabs MCUSCP21 Ox WIN Don t search will choose the driver to install Choose this option to select the device driver from a list Windows does not guarantee that the driver you choose will be the best match for your hardware lt Back l Next gt Cancel X1000_15_041408 Figure 15 VCP Driver Directory Location Driver installation takes one or two minutes to complete The Completing the Found New Hardware Wizard status box is displayed for the second time as shown in Figure 16 This is the second of two drivers that must be installed for the PC and ML555 USB port to communicate correctly 4 Click Finish to complete driver installation Found
46. _IPIFBAR2PCIBAR_0 is set to 0x00000000 This is different from the Base System Builder BSB value for C_IPIFBAR2PCIBAR_O XAPP1000 v1 0 1 May 6 2008 www xilinx com 18 Endpoint to Root Complex Transactions XILINX Figure 24 shows the selection of the pcie_dma software project Xilinx Platform Studio H designs m 555_mb_plbv46_pcie system xmp Block Diagram File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help DP HBOtO MP 4ve XR MHIDABGHOH ek SiMecANM INR IM RRR E SEBO Software Projects Add Software Application Project microblaze_0_bootloop E Default Default microblaze 0 xmdstub E Processor microblaze_0 Executable H designs ml595_mb_plbv46_pcie pc E Compiler Options E Sources Headers a Project pcie_mch_dma Processor microblaze_0 Executable H designs mI555_mb_plbv46_pcie pe Compiler Options E Sources Headers lt il gf Output Waring Error hamanna Figure 24 Selecting the pcie_dma Software Project Dow X Platform Studio System Assembly View Block D i X1000_24 041408 XAPP1000 v1 0 1 May 6 2008 www xilinx com 19 Endpoint to Root Complex Transactions XILINX pcie_dma The pcie_dma project runs Direct Memory Access DMA operations The user sets the source address destination address and DMA length The pcie_dma code is used for DMA operations between u
47. __YSLrdDBus lt 1 gt S_LrdDBus lt 2 gt g 4 SLrdDBus lt 3 gt I gt i Sl_rdDBus lt 4 gt SLrdDBus lt 5 gt Net Name Pattern Filter 4 SLrdDBus lt 6 gt SLrdDBus lt 7 gt Net Name pees se eee 3 Sl_rdDBus lt 8 gt P2INTC_Irpt ee P M SlrdDBus lt 9 gt MSl_request p p P 3 SLrdDBus lt 10 gt SPLB_Rst p F SlLrdDBus lt 11 gt PaPe Sl_rdDBus lt 12 gt SLrdDBus lt 13 gt SLrdDBus lt 14 gt SLrdDBus lt 15 gt SlLrdDBus lt 16 gt SLrdDBus lt 17 gt SL_rdDBus lt 18 gt SLrdDBus lt 19 gt PLB_wrBurst Sl_addrAck Sl_rdBTerm MPLB_Rst Make Connections Move Ne ieee p p E Remove Connections Move Ne X1000_92_041408 Figure 92 Inserter Data Signals 6 Click Insert to insert the core into pcie_bridge_wrapper ngo In the m1555_ mb plbv46_pcie implementation directory copy pcie bridge wrapper ngo to pcie bridge wrapper ngc 8 In XPS run Hardware Generate Bitstream and Device Configuration Download Bitstream Do not rerun Hardware Generate Netlist as this overwrites the implementation pcie bridge wrapper ngc produced by the step above Verify that the file size of the pcie_bridge_wrapper ngc with the inser
48. al simulation performed No Timing simulation performed No Testbench used for functional simulations provided No Testbench format N A Simulator software used version i e ISE software Mentor N A Cadence other SPICE IBIS simulations No Implementation Synthesis software XST EDK Software EDK10 1 Implementation software tools used versions ISE10 1 Static timing analysis performed Yes Hardware Verification Hardware verified Yes Hardware platform used for verification ML555 XAPP1000 v1 0 1 May 6 2008 www xilinx com 84 References References Revision History Notice of Disclaimer XILINX 1 UG197 Virtex 5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide 2 UG201 Virtex 5 FPGA ML555 Development Kit for PCI and PCI Express Designs User Guide v1 4 March 10 2008 3 XAPP1022 Using the Memory Endpoint Driver MET with the Programmed Input Output Example Design for PCI Express Endpoint Cores 4 LeCroy PCI Express Multi Lane Exerciser User Manual Version 5 0 SpekChek User Manual Version 6 5 Catalyst PCI Express Bus Protocol Analyzer Exerciser User s Guide The following table shows the revision history for this document Date Version Revision 04 25 08 1 0 Initial release 5 6 08 1 0 1 Made minor non technical edits Xilinx is disclosing this Application Note to you AS IS with no warranty of any kind This Application Note is one possible implementation o
49. ata 0000 60000000 Upcount H X1000_47_041408 Figure 47 MWr32 Performance Results Length 20 XAPP1000 v1 0 1 May 6 2008 www xilinx com 38 Endpoint to Root Complex Transactions XILINX Endpoint to This section measures the performance of Endpoint to Root Complex transactions The stimuli Root Complex for these transactions are generated using the Xilinx XPS Central DMA Controller in the Transactions reference system The functionality of the DMA controller is discussed earlier in this application note The DMA transaction is from the address specified in the DMAC Source Address register to the address specified in the DMAC Destination Address register The length of the DMA transaction is specified by the value in the DMAC Length register Prior to generating the stimuli the performance test is set up Figure 48 shows the importing of the performance test setup file catalyst pcie dma spf The throughput measurements in this application note are aggregate throughput Catalyst Enterprises Inc SPX Analyzer Exerciser Software pcie_dma2 lil O c2 8S u a m B PL gt eA BE OK OF E POe D Exerciser Program Performance Items Link Settings Setting Items Group Report Direction C Link Usage F Li DLink Utilization Link Aggregate O Transmission Efficiency I Upstream Transmit X Throughput I Downstream Receive Average Payload 1 Number of Packets C Latency
50. c XAPP1000 v1 0 1 May 6 2008 www xilinx com 75 Using ChipScope with the PLBv46 Endpoint Bridge XILINX 5 The plbv46_pcie cdc provides a good starting point for analyzing designs In most analyses additional nets are needed Figure 92 shows the GUI for making net connections Click Next four times to move to the Modify Connections window Select Modify Connections The Filter Pattern is used to find net s As an example of using the Filter Pattern enter ack in the dialog box to locate acknowledge signals such as SI_AddrAck In the Net Selections area select either Clock Trigger or Data Signals Select the net and click Make Connections Correct Clock Trigger and or Data signals displayed in red o x Select Net Structure Nets Net Selections pcie_bridge_wrapper Trigger Signals Data Signals PCle_Bridge comp_master_bridge RxSFIFO_64 RxSFIFO fifo_7O0x5 12 Clock Signals PCle_Bridge comp_master_bridge TxSFIFO CompFiIFO_64 dpram dpram_ PCle_Bridge comp_plbv46_master USE_SYNC_RD_LLINK _LLINK_RD_BKEND P SladdrAck PCle_Bridge comp_plbw46_master USE_SYNC_WR_LLINK _WR_LL_BACKEND SLrdDAck PCle_Bridge comp_slave_bridge comp_rx_fifo GEN_64 COMP_RX_RAM dpr ST am PCle_Bridge comp_slave_bridge GEN_TX_64_FIFO comp_tx_tifo fifo_ 72x51 z PLB_RNW PCle_Bridge comp_tlif RxFIFO_64 rx_afifo fifo_ 70x32 d SLrdDBus lt 0 gt gt PCle_Bridge comp_tlif TxFIFO_64 tx_afifo fifo_ 70x16 i6
51. cation Terminal gt XILINX Opening a HyperTerminal Console 1 On the start menu of the PC run the HyperTerminal application by selecting Start gt All Programs gt Accessories gt Communications gt HyperTerminal This opens a connection description window as show in Figure 18 Enter ML555 as the name of the terminal connection and click OK to continue Connection Description a5 New Connection Enter a name and choose an icon for the connection Name ML555 Icon X1000_18_041408 Figure 18 Start HyperTerminal Application on the PC A Connect To window is displayed as shown in Figure 19 2 Select Connect Using COM3 or COM4 according to the COM port assignment to the ML555 USB interface Click OK Verify COM port assignment for the CP210x port review information depicted in Figure 17 specific to end user system configuration Connect To B ML555 Enter details for the phone number that you want to dial Country region Area code Phone number Connect using imu X1000_19_ 041408 Figure 19 Connect Using COM4 or COM3 XAPP1000 v1 0 1 May 6 2008 www xilinx com 14 Interfacing to a Communication Terminal XILINX UART Lite COM parameters are fixed at the time of reference design compilation A COM Properties window is displayed Figure 20 3 Enter the port settings properties by selecting 9600 bits per second 8 data bits None for
52. comp_slave_bridge sig_IP2Bus_WrAck_bar comp_registers IP2Bus_WrAck sig_IP2Bus_Cond_Wr sig_IP2Bus_Cond_Wr_Go sig_IP2Bus_Cond_Rd_Go comp_slave_bridge sig_ip2bus_wrgo_bar comp_slave_bridge_ip2bus_rdgo_bar comp_slave_bridge sig_rxtlif_completed comp_slave_bridge sig_rxtlif_ request XAPP1000 v1 0 1 May 6 2008 www xilinx com 82 Using ChipScope with the PLBv46 Endpoint Bridge lt XILINX Table 5 ChipScope Signals in Debugging Reference System Cont d Component DDR2_SDRAM_32Mx32 Signal SPLBO_PLB_ABus 31 0 SPLBO_SI_rdDAck xps_central_dma_0O SLAVE_ATTACHMENT_ dma_status_reg 0 SLAVE_ATTACHMENT_ dma_status_reg 1 M_ABus 0 31 S _rdDAck SPLB_RNW MPLB_MWrBTerm MPLB_MWrDAck M_wrBurst Sl_addrAck MPLB_MAddrAck XAPP1000 v1 0 1 May 6 2008 www xilinx com 83 Reference Design Matrix XILINX Reference The reference design matrix is shown in Table 6 Design Matrix Table 6 Reference Design Matrix General Developer Name Xilinx Target devices stepping level ES production speed grades Virtex 5 XC5VLX50T Production Silicon Source code provided No Source code format Verilog VHDL Design uses code IP from an existing reference design application No note 3rd party or CORE Generator software Simulation Function
53. d The PLBv46 Endpoint Bridge is tested using the LeCroy and Catalyst testers as root complex The ML555 Evaluation Board is inserted into the LeCroy or Catalyst PCle slots for testing Sample Catalyst scripts are provided in the m1555_ mb plbv46 pcie catalyst directory Sample Lecroy scripts are provided in the m1555_ mb plbv46 pcie lecroy directory 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners XAPP1000 v1 0 1 May 6 2008 www xilinx com 1 Hardware and Software Requirements XILINX Hardware and Software Requirements Reference System Specifics The tests for the PLBv46 Endpoint Bridge which do not require LeCroy or Catalyst test equipment are the PCIE Configuration Verification PCIE CV PCltree and the Memory EndPoint Test MET tests These are run using the ml555_mb_plbv46_pcie project configured as x1 and x4 These tests are quick to setup and costs nothing other than a PC with PCle slots For these tests the ML555 PCI PCI Express Development Platform is inserted into the x8 PCle slot of a PC Dell 390 The PC based PCltree and or MET software are installed The PCltree Bus Viewer www pcitree de and the Xilinx MET tests allow the user to write and read ML555 memory with any pattern with different lengths PCltree and the MET do not provide the capability to analyz
54. directory containing the CP210x drivers or enter C SiLabs MCU CP210x WIN if the default directory is selected Click Next to continue Found New Hardware Wizard Please choose your search and installation options Pua Ba Y Search for the best driver in these locations Use the check boxes below to limit or expand the default search which includes local paths and removable media The best driver found will be installed C Search removable media floppy CD ROM Include this location in the search CASiLabs MCUNCP210x WIN Browse Don t search will choose the driver to install Choose this option to select the device driver from a list Windows does not guarantee that the driver you choose will be the best match for your hardware lt Back Next gt Cancel X1000_11_041408 Figure 11 Search for the Best Driver in these Locations Driver installation takes one or two minutes to complete The Completing the Found New Hardware Wizard status box is displayed Figure 12 This is the first of two drivers that must be installed for the PC and ML555 USB port to communicate correctly 4 Click Finish to continue with VCP driver installation Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for ad CP2101 USB Composite Device Click Finish to close the wizard X1000_12_041408 Figure 12 Found New Hardware Wizard Driver Installation
55. ds 0000000c DMASrc 2000005c Dest 2000205c DMAlength words 9080000d DHASHE 20000090 Dest 20002090 DHAlength words 000000He DHASrc 200000c8 Dest 200020c8 DMAlength words 0000000f DHA Finished DHASrc 20000104 Dest 20002104 DMAlength words 00000010 DHA Finished DHASrc 20000144 Dest 20002144 DMAlength words 680000000 DHA Finished DHASrc 20000144 Dest 20002144 DMAlength words 80000001 DMA Finished unsere 20000148 Dest 20002148 DMAlength words 68000002 inished DMASrc 20000158 Dest 20002150 DMAlength words 00000003 DMASrc 2000015c Dest 2000215c DMAlength words 60000004 DMASrc 2000016c Dest 2000216c DMAlength words 00000005 DHA Finished Kam lt i gt Figure 27 pcie_dma c output XAPP1000 v1 0 1 May 6 2008 www xilinx com 21 Catalyst Testing XILINX Catalyst Testing This section discusses testing using Catalyst Enterprises SPX Series PCI Express Analyzer Exerciser system The SPX is a serial bus Analyzer Exerciser used to analyze and or exercise PCI Express data transactions The SPX4 Analyzer consists of the SPX4 card and Analyzer software The Analyzer allows capture and trigger on Transaction and Data LInk Layer Packets Physical Layer Ordered Sets and all bus conditions The Exerciser generates bus traffic while operating as either a root complex or endpoint device Figure 28 shows a functional diagram of the Catalyst test setu
56. e PCle traffic The hardware and software requirements for this reference system are e Xilinx ML555 board Production Silicon e Xilinx Platform USB or Parallel IV programming cable e USB Type A to Type B Interface cable and serial communication utility TeraTerm e Xilinx Platform Studio 10 1i e Xilinx Integrated Software Environment ISE 10 1i e Xilinx ChipScope PRO 10 1i e Catalyst SPX Series PCI Express Bus Protocol Analyzer Exerciser e LeCroy PETracer Analyzer PETrainer Exerciser This reference system includes the MicroBlaze Processor MPMC XPS BRAM XPS INTC XPS GPIO XPS UART Lite XPS Central DMA and the PLBv46 Endpoint Bridge Both the processor and the bus run at a frequency of 125 MHz The MicroBlaze processor uses 2 KB for the instruction cache I cache and 4 KB the data cache D cache MPMC runs at a frequency of 125 MHz and is set up for three ports Figure 1 is the block diagram of the reference system MicroBlaze Processor PLBv46 XPS PCle UART Lite Figure 1 Block Diagram of Reference System X1000_01_041408 Table 1 provides the address map of the system Table 1 Reference System Address Map Peripheral Instance Base Address High Address MDM debug_module 0x84400000 Ox8440FFFF XPS INTC xps_intc_O 0x81800000 Ox8180FFFF XPS GPIO xps_gpio_0O 0x81400000 0x8140FFFF XPS BRAM CNTLR xps_bram_if_cntlr_1 0x8AE10000 Ox8AE1FFFF XAPP1000 v1 0 1 May 6 2008 www xilin
57. ect view range KB range 0 63 0 FFFFFFES lt x0000006C gt oooo001c lt x00000070 gt FFFFFFES lt x00000074 gt oooooo1E lt x00000078 gt FFFFFFElL lt x0000007C gt ooo000z0 x00000080 gt Display range men test load tite save fie C128 Bytes 1024 Bytes X1000_88_041408 MB range 0 0 O0 Figure 88 PCltree Read of XPS BRAM Memory Endpoint Test The Memory Endpoint Test MET is run on a PC with the ML555 inserted into a PCle slot MET provides a simple method of writing and reading memory Like PCltree the ML555 memory written read is the BRAM and or DDR2 defined in the system mhs and addressed with the PLBv46 Endpoint Bridge C_PCIBAR2IPIFBAR_ generics The MET requires the installation of the Xilinx Virtex 5 PCle Endpoint Driver The Xilinx application note XAPP1022 Using the Memory Endpoint Test MET Driver with the Programmed Input Output PIO Example Design for PCI Express Endpoint Cores provides instructions on setting up and running the MET XAPP1022 uses the PCle Endpoint Block Plus core driven by the PIO interface This section uses MET to write and read ML555 memory using the PLBv46 Endpoint Bridge Pages 6 11 of XAPP1022 provide instructions for installing the Xilinx Virtex 5 PCle Endpoint Driver XAPP1000 v1 0 1 May 6 2008 www xilinx com 71 Memory Endpoint Test XAPP1000 v1 0 1 May 6 2008 XILINX Figure 89 shows the invocation of the Memory Endpoint Test The values fo
58. elected Link Width is specified as x4 Select Host as the Interposer Generation Options General Link Integrity Flow Control Transactions Target PETrainer ML C PETrainer EML l Disable Scrambling Reverse Lanes Invert Polarity Uo th bi si Beem os i fs Ut ah ae aes ae Gig 0 ja gie WE A pe de Skew a E aagal PPPPPPER Automatically detect Link Configuration Base Spec Rev 1 0 Compatibility Mode Use External Reference Clock Save Save As Defaut Load Link Width x1 e Ax F Disable Descrambling Reverse Lanes Invert Polarity 0 Ay eho E E 8 2 a ja es jab nterposer Host C Device Analyzer control Start recording when generation starts r Cancel X1000_54_041408 Figure 54 Setting Generation Options www xilinx com 44 LeCroy Testing XAPP1000 v1 0 1 May 6 2008 XILINX Figure 55 shows the menu for setting Recording Options after selecting Setup gt Recording Options The Simple Mode is used An Event Trigger is selected The Buffer Size is specified as 32 MB and the Trigger Position is set at 90 post triggering The x4 Lane Width is selected Recording Options Simple Mode Recording Type Snapshot C Manual Trigger Event Trigger r Buffer Size 32 000 MB Trigger On I Eror F Link Up Down M 181 1s2 Bins M Any TLP F Config wr M lORd M lO wr Filt
59. er Qut IV SKIP Ordered Sets Trace Filename amp Path C Program Files CATC PET racer data pex Options Name l ConfigRd MemAd T Mem Wr I Message Completion Target Analyzer PETracer Edge PETracer ML PETracer ML 2 units PETracer EML PETracer Summit Trigger Position 90 post triggering P InitFC1 I InitFC2 T ACK D NAK T PM F UpdateFC DLLP Browse Default Switch to Advanced Mode Save Save As Default Load Link 1 x2 x4 x8 Ki oe s Port 1 of PETracer ML SN 1157 Inhibit Channel Reverse Lanes Invert Polarity G 1 2 sis sce A R he TA JE pe IE E Port 2 of PETracer ML SN 1157 Inhibit Channel P Reverse Lanes Invert Polarity ye e Ee SG ty aie lS Sele a iat ia I Use External Reference Clock l Disable Descrambling IV Auto Configure Lane Polarity X1000_55_041408 Figure 55 Setting Recording Options www xilinx com 45 LeCroy Testing XILINX Figure 56 shows using File Open to open a LeCroy stimuli peg file The LeCroy PETracer software provides the interface to the PETracer Analyzer and PETrainer Exerciser To run an analysis click on the Record icon the Sun in the menu bar Click the Traffic Light icon at the bottom left of the GUI After the status bar indicates Traffic Finished click the Stop icon black filled square next to the Sun This causes results to be shown in the Display area Results files have a pex extension L
60. er is generally optional 5999 92799992299993 9922NTIITTIITIAVAINIAIAD S RIDIAVVIPTL ij Figure 4 x1 and x4 PCle Adapters Communication terminals are commonly used to display information related to the functionality of the ML555 The information displayed is usually output from C code running on the MicroBlaze processor Many newer PCs do not have a COM port The ML555 addresses this by providing an interface to the communication terminal through a USB port This differs from earlier Xilinx boards This eliminates the serial communication cable null modem gender changers used by other Xilinx boards to communicate with a communication terminal Installing CP210x USB to UART Bridge VCP Drivers Silicon Laboratories CP210x USB to UART Bridge Virtual COM Port VCP device drivers permit a CP210x device to appear to any PC application software as an additional COM port in addition to any existing hardware COM ports in the PC Application software running on the PC accesses the CP210x device as it would access a standard hardware COM port However actual data transfer between the PC and the CP210x device is performed over the USB interface COM port applications such as HyperTerminal or TeraTerm transfer data between the USB to the CP210x device without the need to modify the terminal application software on either end of the communications interface The latest CP210x USB to UART Bridge VCP drivers can be downloaded from the Silicon Laboratories
61. f this feature application or standard and is subject to change without further notice from Xilinx You are responsible for obtaining any rights you may require in connection with your use or implementation of this Application Note XILINX MAKES NO REPRESENTATIONS OR WARRANTIES WHETHER EXPRESS OR IMPLIED STATUTORY OR OTHERWISE INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OF DATA LOST PROFITS OR FOR ANY SPECIAL INCIDENTAL CONSEQUENTIAL OR INDIRECT DAMAGES ARISING FROM YOUR USE OF THIS APPLICATION NOTE XAPP1000 v1 0 1 May 6 2008 www xilinx com 85
62. h training states S LeCroy PETracer TM PCI Express Protocol Analyzer H lecroy cfe_x4 peg ak Eile pe Record Generate Report Search View Tools Window Help e nep E em AM F QQ eR A ae OL ab Be CfgRdO pea o oomoo j ooo oe Time UE 0000ns O00 ns 0000 000 000 000 s 000 000 000 s Idle nip 0 000 ns on 3 O00 000 020 s The following scripts perform configuration reads and writes to configure space Script commands Packet template TLP Idle Link Name MyCfgWrite Template name Config TlpType CfgWr0 Write device Configuration Space Wait FirstDwBe OxF First DU Byte Enables Template Length 1 1 DWORD Include Loop Payload OxFFFFFFFF Repeat Branch Proc AddressSpace template TLP PETrainer ML SN 1102 Link State InitFC State 3h s 5 amp Lo Complete Ready Search Fwd X1000_58_041408 Figure 58 LeCroy After Link Trained XAPP1000 v1 0 1 May 6 2008 www xilinx com 48 LeCroy Testing lt XILINX Root Complex to Endpoint Transactions As Root Complex the LeCroy Trainer generates memory writes and memory reads to the ML555 memory The ML555 reference design contains XPS BRAM and an MPMC interface to DDR2 Figure 59 shows the memory addressing for Root Complex Catalyst to Endpoint ML555 transactions The memory addressed is controlled by the BAR value written and by the C_PCIBAR2IPIFBAR_ generics In
63. he content of a single Configuration Read TLP XAPP1000 v1 0 1 May 6 2008 Packet_Type Config Read TO Framing_Symbol1 FB Reserved_1 0 Sequence_Number 000 Reserved_2 0 Format 0 Type 04 Reserved_3 0 TC 0 Reserved_4 0 TD 0 EP 0 Attribute 0 Reserved_5 0 Length 001 Requester_ID 0000 Tag 00 Last_DW_BE 0 First_DW_BE P Bus_Number 00 Device_Number 00 Function_Number 0 Reserved_6 0 Register_Address 000 Reserved_7 0 TLP_Digest LCRC 2AC 19647 Framing_Symbol2 FD Loop_Type No_Loop Loop_Count Iterate_After_Trigger No Delay_Count 0 Trigger_Source Immediate_Execution Disparity_Error No ZData 10000000000000000001 Symbol_View Collapse Trigger_Output No Trigger_Output_Type Pulse Global_Loop Figure 35 sdc_example www xilinx com 28 Catalyst Testing XAPP1000 v1 0 1 May 6 2008 XILINX As Root Complex the Catalyst Exerciser performs memory writes and memory reads to the ML555 memory The ML555 reference design contains XPS BRAM and a Multiported Memory Controller MPMC interface to DDR2 Figure 36 shows the memory addressing for Root Complex Catalyst to Endpoint ML555 transactions The
64. ie_bridge_wrapper 555_pcie_x1 bit pcie_diff_clk_wrapper download bit Desktop pcie_ref_clk_buf_wrapper download_cclktemp bit plb_v46_0_wrapper system bit plb_v46_1_wrapper plbv46_pci_1_wrapper proc_sys_reset_O_wrapper Syrs232_uart_1_wrapper Syrs232_wrapper xps_bram_if_cntlr_1_bram_wrapper xps_bram_if_cntlr_1_wrapper My Documents lt m EJ My Network File name download gt Places Files of type FPGA Bit Files bit X Cancel X1000_78_041408 Figure 78 Specifying the Bit File XAPP1000 v1 0 1 May 6 2008 www xilinx com 62 PCltree Testing gt XILINX Select Generate File The generated MCS file is shown in Figure 79 amp iMPACT PROM File Formatter G File Edit View Operations Window Help AH SBOXK PRIN G Bao wy ZsiBoundary Scan PlSlaveSerial FaSelectMAP FaDesktop Configuration FEDirect SPI Configuration xef32p E SystemACE 41 88 Full xo5vix50t E PROM File Formatter R download bit iMPACT Processes Available Operations are PROM File Generation Succeeded e2 Boundary Scan B PROM File Formatter Operations Writing file H designs ml555_mb_plbv46_pcie m1l1555_mb_plbv46_pcie mcs Writing file H designs ml555_mb_plbv46_pcie ml1555_mb_plbv46_pcie prm Writing file H designs ml555_mb_plbv46_pcie ml555_mb_plbv46_pcie sig A lt f Output Error Waming PROM File Generation Target Xilinx PROM 14 052 3
65. ike peg files pex files can be opened using File gt Open 55 LeCroy PETracer TM PCI Express Protocol Analyzer Eile Setup Record Generate View Tools Help 2 a ODETA Look in S lecroy aae My Recent Documents e eskto D My Documents BElconfig_3 i 1 Configuration_Only Bldrp_rc_to_ep Eldrp_wait_cpld Bldrp_wait_mwr32 My Computer My Network Places PETrainer ML SN 1102 Eni S S BSE Detect auiet 1_DW_Mrd e4 1DW_completion Blow mrd Elow mrd 4k_out_of_order_cpld 16_DW_Mrd64 Bels2bit_dma_read_write_burst BlcFa_re2ep_rd_wr Blcompleter abort config lt im ep_to_rc ep_to_rc_2 ep_to_rc_4 ep_to_rc_6 fBelm32_dma_BARn_to_BRAM_burst m32_dma_BARn_to_BRAM_burst_RCB fB lm32_dma_BARn_to_BRAM_single Belme4_rdwr_singles_bursts Belmrd32_sligned_tests Belmrd32_unaligned_tests pcie_29 PETrainer rc_to_ep Sel sol_mrde simple_loop Configuration Ony x All PETracer Files pex pem peraw peg Link State InitFC State Not initialized Ready Figure 56 Opening a LeCroy PEG File Search Fwd A X1000_56_041408 XAPP1000 v1 0 1 May 6 2008 www xilinx com 46 LeCroy Testing gt XILINX Figure 57 shows the use of XMD to enable the PLBv46 Endpoint Bridge Bridge Control Register The BCR enables the Bus Master and Base Address Registers BARs cx Command Prompt xmd of PC B
66. it view Configuration Tools Project Setup Window Help D suas a a B etln ABE OK Ol E Voe Link Chart Average Payload 0X _ Link Chart Throughput auj o Ef amfi ao Ef J 22t2 Throughput520 6 MB Sec Average Payload 128 00 Bytes a By Payload Throughput3o1 3 MB Sec rc2ep_wr64 Exerciser Program Performance Items Link Settings Setting Global Loop S E C NoLoop C Count 20 Continuous 4DW header with data MemWrite 020 Addr H Data H 0000000060000000 Upcount EIl Analyzer 1 000E85000159 USB Exerciser Run Analyzer X1000_46_041408 Figure 46 MWr64 Performance Results Length 20 XAPP1000 v1 0 1 May 6 2008 www xilinx com 37 Using Catalyst to test PCle Performance XILINX Figure 47 shows the performance results from running a continuous MWr82 transaction The data and payload throughput are 508 4 MB s and 391 3 MB s Catalyst Enterprises Inc SPX Analyzev bmrciar Software Link Chart Throughput Carat ys File iguration tSetup M oe saus u a gt m m BELLS nA AETR RE vee Se Link Chart Throughput J Data Throughputs08 4 MB Sec J 2021292 Payload 128 00 Bytes i ae ca J Payload Throughput3a1 3 MB Seo PerformanceAnalyzer_x4 Exerciser Program Performance Items Link Settings Setting Global Loop 1 JE 2 jka C NoLoop Count 2 Continuous 000 3DW header with d
67. k to location 0x00000000 I 0 and the contents of the memory is re displayed using d 40 The 0x12345678 value just written at location 0x00000000 is displayed c Command Prompt met log 555_pcie log Device 6x565 Bus 6x6 Dev x MemAddress 6xe 4000000 MemS ize 6x1 6668 IoAddress 6x IloSize 6x IsPciExpress TRUE Interactive mode MEM 32 Hex G6666000 gt d 40 HEGHHH0H AHAHAHHA FFFfffff BBHHHHH2 fFFfFFfFFffffd HEG00016 BHHHH0H4 FFFFFFFfFb BHHHHHHE FFFFFFF HE660826 AAAHAHAS FFFFFFFfF7 BHHHHHBa FFFFFFF5 66660636 B66600Hc FFFFFFFfF3 OOHAHHHe FfFFFFFFFi MEM 32 Hex AHAHA4A gt 1 AxA MEM 32 Hex 6600000 gt s 12345678 MEM 32 Hex 66666606 gt 1 AxA MEM 32 Hex G 66668606 gt d 46 PONAHOHA 12345678 FFFLLELL BHHHHHH2 FFFFFffda HOGH0816 AAANHANA4 FFfffffh AAAAHAHG FFF HG600826 BHHHHHH8 FFFFFFFfF7 BHHHHOHa FFFFFFF5 HE6H0036 BH6000Hc FFFffff3 BHHHHHHBe FFFFLLF1 MEM 32 Hex 66606646 gt X1000_90_041408 Figure 90 Running the Memory Endpoint Test XAPP1000 v1 0 1 May 6 2008 www xilinx com 73 Using ChipScope with the PLBv46 Endpoint Bridge XILINX Using ChipScope with the PLBv46 Endpoint Bridge ChipScope is used to debug hardware problems Debugging is done at either the system or PLBv46 Endpoint Bridge level To analyze PLBv46 Endpoint Bridge internal signals insert the ChipScope cores into pcie_bridge_wrapper ngc To analyze signals involving multiple cores insert the ChipScope
68. l o DDR2_SDRAM_32Mx32 SPLBO_PLB ABUS DDR2_SDRAM_32Mx32 SPLBO_ 1_rdDAck sPCle Bridge PLB_ABus jxps central dma 0 M_wrDBus jxps central dma 0 M_ABus xps_central_dma_0 M_request xps_central_dma_0 MPLB_MRdDAck xps_central_dwa_0 1_rdDAck xps_central_dwa_0 SPLB_RNU xps_central_dwa_0 MPLB_MWrBTerm xps_central_dwa_0 MPLB_MirDAck xps_central_dma_0 SPLB_PAValid xps_central_dwa_0 M_wrBurst xps_central_dma_0 1_addrAck xps_central_dma_0 MPLB_MAddrAck xps_central_dma_0 xps_central_dma xps_central_dwa_O0 xps_central_dma PCIe_Bridge S1_wrDAck PCIle_Bridge PLB_MWUrBTerm PCIe_Bridge S1_wrBTerm PCle_Bridge PLB_rdBurst PCIe_Bridge PLB_PAValid MMAND upload INFO Device 0 Unit 0 Waiting for core to be armed 400 360 320 280 240 200 160 120 80 40 0 40 80 120 160 200 240 FFFFFFFF 00000000 a WUN Nl LL Upload X1000_97_041408 Figure 97 System Debugging Using ChipScope Analyzer As show in Figure 97 memory XPS Central DMA and PLBv46 Endpoint Bridge transactions are monitored simultaneously The trigger is PCle_bridge comp_slave_bridge sig_request_complete The m1555_ mb plbv46_ pcie_scs cdc is included in the chipscope directory Table 5 ChipScope Signals i
69. layed Figure 82 shows the value of BARO re defined to 0xE000000C direct select Pcilree bus dev j3 o Host PCI Bridge I O gt 1l 1 PCI PCI Br VGA PC Compati o Multimedia 80 O gt Z 2 PCI PCI Br O gt 3 3 PCI PCI Br Other Memory C O gt 4 4 PCI PCI Br Ethernet Netwe Universal Host Cor Universal Host Cor Universal Host Cor Universal Host Cor o serial bus Dev O gt S 5 Subtractive PCI ISAa Bridge De o Mass Storage Ci o Mass Storage Ci s z z z 0 z 0 0 Oo 0 SMBus Serial Bus rescan write to reset show INT routing p e show Mem Map 3 0 0 Other Memory Controller VID xlOEE Xilinx Corp DID xO0505 no device name found no SubVID xo0000 SubID xo0000 rev x00 redit ConfReg Ixzhoooooc hex Write ComftReg Nr of ConfRegs 16 64 use BIOS int refresh dump type l xs E refr after wr Config Space Dump DID VID Stat Cmd BaseClass SubClass I BIST Header LatTimer 0000 000C lt 10 BAR O mem pref 64b z BAR 1 BAR Z BAR 3 BAR 4 BAR Cardbus CIS Ptr SubID SubVendorID Exp_ROM_BAR reserved reserved maxLat minGnt IntPir X1000_82_041408 Figure 82 Defining BARO in PCltree XAPP1000 v1 0 1 May 6 2008 www xilinx com 66 PCltree Testing gt XILINX Figure 83 is XMD output which shows that BARO has been written as 0xE000000c The XMD mrd also
70. low Speed System Clock 1 25 2 5 Gbps g Full Speed System Clock supports Spread Spectrum Clocking _ intemal Source does not support Spread Spectrum Polarity Reversal Clocking O Lane O g Lane O O Lane 1 O Lane O Lane 2 O Lane 2 O Lane 3 O Lane 3 Check All Check All Clear All_ Clear All O Lane O O Lane 1 O Lane 2 o Lane 3 Check All as Trigger Out ane ane 2 C Negative Edge a Positive Edge Capabilities Level Enable Back to Back Transmission Enable Data Link Layer V Enable LISSM LTSSM Behavior Platform Mode Transmitter Device Clear All C End Point Mode Receiver Device Analyzer Simulation Mode Not Triggered X1000_40_041408 Figure 40 Performance Test Physical Settings XAPP1000 v1 0 1 May 6 2008 www xilinx com 31 Using Catalyst to test PCle Performance XILINX Root Complex to Endpoint Performance Tests To setup the performance test the ML555 is inserted into the Catalyst The bitstream is downloaded into the FPGA Use XMD to write 0x003F0107 to the PLBv46 Endpoint Bridge Bridge Control Register to enable the bus master and the Base Address Register s Root Complex to Endpoint Read Operations Figure 41 shows the opening of the rc2ep_rd64 performance project Performance projects use the spf extension Catalyst Enterprises Inc SPX Analyzer Exerciser Software File View Configuration Tools Project Setup Hel
71. memory addressed is controlled by the BAR value written and by the C_PCIBAR2IPIFBAR_ generic s In the reference design BARO is written as 0x0000000060000000 C_PCIBAR2IPIFBAR_0 addresses XPS BRAM at 0x8AE10000 and C_PCIBAR2IPIFBAR_1 addresses DDR2 at location 0x90000000 ML555 XPS BRAM 0x8AE10000 PLBv46 PCle Catalyst PCle x4 C_PCIBAR2IPIFBARO 0X8AE10000 C_PCIBAR2IPIFBAR1 0x90000000 MPMC DDR2 Root Complex 0x90000000 End Point X1000_36_041408 Figure 36 Catalyst Root Complex Figure 37 shows the write then read TLPs in the wr_rd_x4 sdc file In the figure Packet 0 is a MWr64 to address 0x0000000060000000 of 128 bytes The Data Field allows the user to specify data as Upcount Walking Bit or Random pattern or a user defined pattern such as 0x12345678 can be entered As exercises in learning to use the PLBv46 Endpoint Bridge the data can be varied and the memory written read can be changed from XPS BRAM to DDR2 The Length field is O20H which is 32 doublewords DWs or 128 bytes Packet 1 is a MRd64 of address Ox0000000060000000 used to verify the written data The MRd64 TLP address endianess differs from the CfgWr address endiness used when the BAR was written with a CfgWr in Figure 33 Bit Order and Endianess can be defined by right clicking a field to invoke a pop up menu Catalyst Enterprises Inc SPX Analyzer Exerciser Software wr_rd_x4 File Edit View Configuration Tools Project Setup Window Help
72. n Debugging Reference System Component Trigger Signal PCle_Bridge Sl_wrDAck Sl_addrAck comp_slave_bridge sig_request_complete xps_central_dma_0O SLAVE_ATTACHMENT_ dma_status_reg 0 Sl_addrAck MPLB_MWrBTerm M_rdBurst M_wrBurst Data XAPP1000 v1 0 1 May 6 2008 www xilinx com 81 Using ChipScope with the PLBv46 Endpoint Bridge XILINX Table 5 ChipScope Signals in Debugging Reference System Cont d Component Signal PLB_ABus 0 31 sig_sb_txsof_n comp_tlif TxESM TxEOFn sig_sb_txeof_n comp_slave_bridge sig_ip2bus_wrgo_bar sigIP2Bus_Cond_Wr_Go sig_IP2Bus_Cond_Rd_Go comp_slave_bridge sig_cmd_rnw comp_slave_bridge sig_memory_request comp_hard_pcie mim_dll_bwen comp_hard_pcie mim_tx_bwen comp_slave_bridge sig_cmd_burst comp_slave_bridge sig_cmd_bar_num 0 comp_slave_bridge sig_cmd_complete comp_hard_pcie gt_tx_data_reg 0 comp_hard_pcie gt_rx_data_reg 0 comp_hard_pcie dst_req_n comp_tlif RxESM PendingWrite comp_tlif RxISM Load comp_tlif TxESM LoadPipe PCle_Bridge comp_tlif TxESM TxRdEn comp_tlif TxSOFn comp_tlif TxEOFn comp_tlif TxESM TxSOPn comp_tlif TxESM TxEOPn comp_tlif TxESM TxSrcRdyN comp_slave_bridge sig_completion_request comp_plbv46_slave I_SLAVE_ATTACHMENT bus2ip_rnw_i comp_registers sig_bus2ip_rnw
73. ns 0000 000 000 264 s PETrainer ML SN 1102 Link State InitFC State Bune SSBS Complete Ready ji Search Fwd X1000_60_041408 Figure 60 RC to EP Write Read Test XAPP1000 v1 0 1 May 6 2008 www xilinx com 49 LeCroy Testing XILINX The next figures show BARO configuration packets followed by write then read operations on BARO Figure 61 shows the configuration of BARO and the read write and read transactions The address of BARO is 0x0000000060000000 Packet 0 is a CfgWr of the lower order address and packet 2 is a CfgWr of the higher order address Packets 4 and 5 use CfgRd TLPs to verify the configuration writes Packets 6 7 and 8 are MRd32 MWr32 and MRd32 TLPs used to read and write BARO memory Double click on the Data field in packet 7 to display the 1234678 value The endianess of the address in the CfgWr0 TLP differs from the endianess of the address in the MWr32 and MRd32 TLPs gt LeCroy PETracer TM PCI Express Protocol Analyzer H Xlecroy rc2ep_cfg wr_rd_bar0 peg FF tie Setup Record Generate Report Search View Tools Window Help SUE P WH em A FERRE e OR MB E h O e wh E lt Ge Pet Ue spe Faia C1 1st BE 0 10 00100 000 00 0 000 00 0 0x010 1111 00000060 a E Infinite _ 3DVV header no data Cpl CpID i 31 1st BE 10 00100 000 00 0 0 000 00 0 0x014 1111 00000000 ca 3DW header no data Cpl CpID 1 CfgRd0 a Tew ease 1st BE 00 001
74. obal Loop TH x C NoLoop C Count Continuous Z Addr H MemRead64 O00 4DW header no data iz 003 0000 0000000060000000 Analyzer 1 000 85000159 USB Exerciser Stop Analyzer Stop X1000_42_041408 Figure 42 Defining MRd64 Performance Stimuli The next two figures show the performance results of MRd64 transactions varying the length of the TLP The single continuously transmitted TLP stimuli just defined is shown in the pane at the bottom of the figure The left pane is a Link Chart which provides the average payload size The right pane is a Link Chart which provides the data throughput and the payload throughput In the Performance Items tab Link Usage Number of Packets and Latency are unchecked Under Report Directions Aggregate is checked In the following tests Data Throughput is the overall bus traffic of all non idle packets divided by the update interval Payload Throughput is the payload data of TLPs divided by the update interval The update interval defined in the Settings tab for performance measurements in this document is 1 s The MRd performance is the round trip time including the MRd command and the Completion with Data packet XAPP1000 v1 0 1 May 6 2008 www xilinx com 33 Using Catalyst to test PCle Performance XILINX Figure 43 shows the performance results of a MRd64 TLP of length 10 The data and payload throughput are 314 2 MB s and 163 9 MB s Catalyst Enter
75. oject Tree Capture Everything Everythingl Exclude Idles C Pattern a A Trigger On No Capture P TLP Any Type Fmt Any Format Type Any Type I Exclude DLLPs Requester ID Xxxx H Exclude Ordered Sets Traffic Class Any TC Payload oxxxxX H Parameters g i Start at XX H IV Exclude Idles Address 00000000000000 H 4 Enhanced oOOSO0OOO OOO OOOO Direction Any Direction E S A Settings Trig Position in Memory 9 Capture Memory Space 100 KB Output Sample File H catalyst ctg_x4 ssf Analyzer Simulation Mode Analyzer Simulation Mode Not Triggered 74 X1000_31_041408 Figure 31 Capture Settings XAPP1000 v1 0 1 May 6 2008 www xilinx com 24 Catalyst Testing XILINX Figure 32 shows the setup of the Catalyst Link Settings The ML555 can be used with either x1 or x4 lane width This application note uses x4 lane width Select the Platform mode hidden behind the Link Status pane Click on the Link Status button to invoke the Link Status pane displayed The figure shows a Link Width 4 so the link is up and trained as x4 Catalyst Enterprises Inc SPX Analyzer Exerciser Software cfg O cAOS nleal ereis gt m B 2 2 en BBE OK OR amp Exerciser Program Capture Trigger On Link Settings Settings Physical Layer Settings SPX Reference Clock Link width C Slow Speed System Clock 1 1 25 Gbps C x2 x4 C C
76. p 0 548082 Hg Look in je catalyst z Mae E perf_ep2rc PerformanceAnalyzer1 Ik rc2ep_rd64_10 ey PerformanceAnalyzer2 rc2ep_wr PerformanceAnalyzer_x1_ep2rc lkl rezep_wre4 PerformanceAnalyzer_x4 Ih reZep_wr64_10 ey re2ep_rd32 g z a File name rc2ep_rd64 Files of type PettormanceAnalyzer Files spf z Cancel A X1000_41_041408 Figure 41 Opening a Catalyst Performance Test The four tabs used in performance projects are the Exercise Program Performance Items Link Settings and Settings In Performance Items the type of performance tests run are defined The PCle traffic used in the performance measurement is defined in the Exercise Program XAPP1000 v1 0 1 May 6 2008 www xilinx com 32 Using Catalyst to test PCle Performance XILINX Figure 42 shows a single TLP used in the performance measurements of Rd64 transactions of length 003 Click the TLP button below Performance Items to add the TLP to the Exercise Program Using the pop up menu select Memory Read Request 64 bits Fill out the address and Len fields Select the Continuous radio button so that the TLP is continuously transmitted Catalyst Enterprises Inc SPX Analyzer Exerciser Software cat_perf_x4_rd64 DER iel File Edit View Configuration Tools Project Setup Window Help si We D Suaa eOk a gt S R A wy ARE OK Ol Pe SOU Exerciser Program Performance Items Link Settings Setting Gl
77. p SPx4 Slot PC Catalyst Software PCle Slot EDK ISE PXP 100a PCI Express DVT Platform X1000_28_ 041408 Figure 28 Catalyst Test Setup Figure 29 is a photograph of the Catalyst setup A x1 or x4 adaptor is attached to the ML555 PCle edge and the ML555 is inserted into the PCle slot The Platform Cable USB cable is connected to the ML555 to use Impact XMD and GDB A USB cable connects the PC based Catalyst software to the SPX4 Analyzer el Express DVT Platform www getcatalyst com DK ORG OHN WHOS 00 AG 100 969710 19PON ASN qeg woed EXNIIX 33 Figure 29 Photo of Catalyst PCI Express Test Equipment XAPP1000 v1 0 1 May 6 2008 www xilinx com 22 Catalyst Testing XILINX In addition to using the Catalyst Bus Protocol Analyzer Exerciser software discussed extensively in this application note the Catalyst SoekChekTM PCI Express Compliance Suite has been run with this reference design to verify that the PLBv46 Endpoint Bridge meets PCI SIG compliance tests The SpekCheck tests are defined in the SpekChek User Manual Version 6 5 Several tools including Impact XMD and Catalyst are used in the setup and testing of this reference system and their order of use can affect functionality After downloading the bit file into the ML555 FPGA using Impact the Bridge Control Register BCR of the PLBv46 Endpoint Bridge is written as shown in Figure 30 The BCR enables the PCle Bus Master and
78. prises Inc SPX Analyzer Exerciser Software Link Chart Average Payload File View Configuration Tools Project Setup Window Help O0 s586 Ha amp S P Oe H amp B OL OS e SOae B B 8 Link Chart Average Fhkyload DER Link Chart Throughput J Data Throughput314 2 MB Sec J 2021292 Payload a2 67 Bytes BB Payload Throughput 163 9 MB Sec C NoLoop C Count pe Continuous ce Global Loop X1000_43_041408 Figure 43 MRd64 Performance Results Length 10 XAPP1000 v1 0 1 May 6 2008 www xilinx com 34 Using Catalyst to test PCle Performance XILINX Figure 44 shows the performance results of a MRd64 TLP of length 100 The data and payload throughput are 298 5MB s and 215 1MB s Catalyst Enterprises Inc SPX Analyzer Exerciser Software rc2ep_rd64 File Edit view Configuration Tools Project Setup Window Help sH Ou a gt a B P Le eRRE OX OP E SOe Gls Link Chart Average Payload 3a x muje fE 100 90 80 70 60 60 40 Average Payload 102 40 Bytes 30 Global Loop Noloop Count 2 Continuous Analyzer 1 000E8S000159 56 Exerciser Run Analyzer Run 7 X1000_48_041408 Figure 44 MRd64 Performance Results Length 100 The maximum length TLP which can be measured by the Catalyst software at the time of this measurement is 400 bytes XAPP1000 v1 0 1 May 6 2008
79. r configuration Configuring the ML555 XC5VLX50T when used in a PC PCle Slot Them1555_ mb plbv46 pcie ready for _download m1555 mb plbv46_pcie mcsis the configuration file for this reference design Because Xilinx recommends configuring from the PROM the next figures outline the steps for creating a mcs for the ML555 Users generating the PROM file for the first time should reference the detailed instructions provided on pages 101 108 of UG201 v1 4 Virtex 5 FPGA ML555 Development Kit for PCI and PCI Express Designs XAPP1000 v1 0 1 May 6 2008 www xilinx com 58 Testing with a PC Figure 75 shows the ML555 Boundary Scan chain The first XCF32P is used to configure the FPGA Right clicking on the XCF32P invokes the Prepare PROM GUI iMPACT Boundary Scan S File Edit View DH BSiBoundary Scan GilSlaveSerial TalSelectMAP Fa Desktop Configuration Operations Output Debug Window Help B X te alala XILINX oR Right click device to select operations FaDirect SPI Configuration E SystemACE E PROM File Formatter IMPACT Processes xc5vix50t file xc2c32a file xcf32p file Available Operations are Operations xct32p file B Boundary Scan PROGRESS_END End Operation Elapsed time BATCH CMD 2 sec identifyMPM gt Configuration Parallel Iv SMHz LPT1 Figure 75 ML555 Bo
80. r the Device Number Vendor Number and the address indicate that the PLBv46 Endpoint Bridge on the ML555 is detected amp Command Prompt met log 555 log Co x Microsoft Windows XP Version 5 1 2666 lt C Copyright 1985 2661 Microsoft Corp H gt cd met H met gt met log 555 log 4 request report MemAddress Gxe 6666006 MemS ize 6x1 6666 IoAddress 6x Ilo ize 6x IsPciExpress TRUE Interactive mode MEM 32 Hex 666008000 gt X1000_89_041408 Figure 89 Invoking the Memory Endpoint Test Pages 11 15 of XAPP1022 provide detailed instructions on using the MET to test transfers to PLBv46 Endpoint Bridge memory www xilinx com 72 Memory Endpoint Test XILINX Figure 90 shows basic read and write operations using the MET In the figure the Display d Location I and Set s instructions illustrate basic memory read and write transactions The command d 40 causes the values of 40 current memory locations to be displayed The values displayed 00000000 FFFFFFFF 00000002 FFFFFFFD arethe same as the values displayed by PCltree in Figure 23 because this test was run shortly after the PCltree tests The location command 10 moves the address to location 0x00000000 All addresses are offset addresses from the BAR start address The set command s 12345678 is a memory write to the current address In the figure after the write of 0x12345678 the address pointer is move bac
81. reakpoints of Read Addr Data Watchpoint of Write Addr Data Watchpoin on 8x 6066068 Instruction Cache High Addre OxPfFFELEE Data Cache Support on Data Cache Base Addr OxI 35 5 5 51515 Data Cache High Addr Oxf FFL LFF Exceptions Support off FPU Support off Hard Divider Suppor off Hard Multiplier Supp on CMul32 gt Barrel Shifter Support off MSR clr set Instruction Support Compare Instruction Support MDM UART Target mb target id server for mb target Cid at TCP port no 1234 System reset successfully SMD mur x85CHALe Ox883f8187 MDZ X1000_57_041408 Figure 57 Using XMD Commands to Write the Bridge Control Register After generation and recording options are specified and the BCR is written the link must be trained The Link State is displayed at the bottom of the PETracer GUI Prior to training the Link State is displayed as Detect Quiet as shown at the bottom of Figure 56 After training the Link State is displayed as LO To initiate training click on the Connect icon To disable a trained link click on the Disconnect icon XAPP1000 v1 0 1 May 6 2008 www xilinx com 47 LeCroy Testing XILINX Figure 58 shows that the LeCroy ML555 PLBv46 Endpoint Bridge link is trained with the LTFSM in LO If the clocking and resets are correct link training occurs in less than one second If link training is unsuccessful the LTFSM cycles throug
82. register is read In the figure the Name column provides the type of transaction and the Reg Num column specifies the register in the Configuration Space Header BARPO is written and read BARO is a 64 bit BAR with the lower 32 bits defined at Configuration Space Header CSH Register Number 4 and the higher 32 bits defined at CSH Register Number 5 Packets 10 and 11 are Configuration Writes and packets 12 and 13 are Configuration Reads In the Data field in packet 10 the endianess of the data written is swapped Catalyst Enterprises Inc SPX Analyzer Exerciser Software cfg_x4 o File Edit View Configuration Tools Project Setup Window Help n saas ute Fes m B PLe WABE OK OP e POe S Exerciser Program Capture Trigger On Link Settings Settings Global Loop e NoLoop Count f Continuous aj j x ne Fmt H Type H Len H ReqiD H CONFIG WRITE TO 3DW header with data Config Write TO Egon ITT Last DW BE H First DW BE H Bus Num H Dev Num H Func Num H Reg Num H Data H Fmt H Type Len H Req D H CONFIG WRITE TO 3DW header with data E TO Last DW BE H First DW BE H Bus Num H Dev Num H Type H Len H ReaD H CONFIG READ TO 3DW header no data Config Read TO Boo ITT Last DW BE H First DW BE H Bus Num H Dev Num H Func Num H Reg Num H OEO D Fmt H Type H Len H Roall ID A AEAT 3DW header
83. s not provided with the Virtex 5 FPGA ML555 Development Kit for PCI Express and PCI designs Power up the PC and ML555 system before continuing with the VCP driver installation Successful CP210x driver installation consists of five steps a Create an installation directory on the PC and copy the installation files from the ML555 CD ROM or downloaded driver from a temporary directory into the CP210x directory b With the reference design loaded in the Virtex 5 FPGA and a USB A to B cable connected between the PC and ML555 USB port install the first of two CP210x USB to UART device drivers on the host PC c Install the second CP210x USB to UART device driver on the host PC d Verify driver installation using Windows device manager e Start a HyperTerminal application to verify communications Place the ML555 CD ROM in the CD ROM drive on the PC The driver file is named CP210x_ Drivers exe and is located in the directory ML555 Support Files SiLabs CP2102 VCOM Driver If the ML555 CD ROM is not available download the latest CP210x driver from the Silicon Laboratories website before continuing XAPP1000 v1 0 1 May 6 2008 www xilinx com 6 Interfacing to a Communication Terminal XILINX CP210X Installation Directory Creation 1 Double click the self extracting ZIP file A folder containing various drivers is created in the c SiLabs MCU CP210x directory The InstallShield Wizard is displayed as shown in Figure 5
84. ser defined source and destination addresses Figure 25 shows the parameters in pcie_dma c which are edited to test PCle transactions between different memory regions The elf for pcie_dma c runs on the MicroBlaze processor in the XC5VLX50T FPGA on the ML555 pcie_mch_dma The pcie_mch_dma project runs multi channel Direct Memory Access DMA operations The user sets the source address destination address and DMA length for each channel The pcie_mch_dma code is used for DMA operations between user defined source and destination addresses As with the pcie_dma code The parameters in pcie_mch_dma c which can be edited to test PCI transactions between different memory regions are DMAChannel BAR The elf for pcie_mch_dma c runs on the MicroBlaze processor in the XC5VLX50T FPGA on the ML555 DMA Transactions As examples of source and destination addresses in the DMA transactions the source address is an address in the ML555 XPS BRAM and the destination address is Catalyst memory across the PCle link Another DMA transaction transfer is data from the source address in one location in the Catalyst memory to a second location in Catalyst memory define MEM_O_BASEADDR 0x8AE10000 define MEM_1_BASEADDR 0x20000000 DMALength 1024 X1000_25_ 041408 Figure 25 Defining Source and Destination Addresses Length in pcie_dma c The XMD scripts and C code generate DMA operations to transfer data between different ML555 and Catalyst memory
85. shows that the data in the initial 8 addresses in XPS BRAM is 0x00000000 ex Command Prompt xmd a x 66680068 15151515 515 5 415 15 5 5 5 5 Gx85cH2608 8 EE100505 66661668 66668 605 66680808 OCOAOHEA M15 515 5 15 5 M15 5 5 15 15 5 M15 5 5 15 515 5 Ox8AE1 6000 8 66680808 M15 5 151515 5 66668608 66868608 66660608 66680808 66680808 115 5 515 515 5 X1000_83_041408 Figure 83 XMD showing the Configuration Space Header XPS BRAM XAPP1000 v1 0 1 May 6 2008 www xilinx com 67 PCltree Testing lt XILINX Figure 84 shows the memory test for PCI tree To run the memory test click on Mem Test at the lower left of the BAR Space GUI Check Auto Read Memory at the top of the BAR Space GUI to display memory values in the left side of the display To edit a memory location highlight the location to be edited and enter the value in the Edit memory dialog box Click Write Memory To view the results click on the Refr View icon Pcilree BAR space oooo0000 ooooo0000 00000000 oooo0000 ooooo000 ooooo0000 oooo00000 ooooo000 oooo00000 ooooo000 ooooo0000 oooo0000 ooooo0000 oooo00000 ooooo000 ooooo0000 oooo0000 ooooo000 oooo0000 ooooo000 00000000 oooo0000 ooooo000 oooo00000 ooooo000 oooo0000 ooooo0000 00000000 oooo0000 ooooo000 oooo0000 oooo0000 ooooo000 x00000000 gt x00000004 gt x00000008 gt lt x0000000C gt lt x00000010 gt x00000014 gt
86. sters 12003 28800 41 Slice LUTs 12437 28800 43 DCM_ADV 2 12 16 Block RAM 56 60 93 XAPP1000 v1 0 1 May 6 2008 www xilinx com ML555 Setup XILINX ML555 Setup Figure 3 shows the ML555 PCI PCI Express Development Platform The ML555 has a PCI connector on one edge of the printed circuit board and a x8 PCle connector on the other edge In the figure no PCle adapter is connected to the ML555 x8 PCI edge connector For PCle operation move switch SW8 to the PCle position and install a shunt on P18 Swe cro D im 8638 94V 8 s fog 3s WO 141795 Slide Switch SW8 AE P13 8 Lane Connector for PCI Express LOSXTASOX G XALYIA h XNOKI Ek B az l P45 Configure for PCle Lane Width Presence Detect P18 Install Shunts for PCI Express X1000_03_041408 Figure 3 ML555 PCI PCle Evaluation Platform XAPP1000 v1 0 1 May 6 2008 www xilinx com Interfacing to a Communication Terminal XILINX Interfacing to a Communication Terminal Put the shunt on P45 to indicate the number of PCle lanes used in the project as shown in Table 3 Table 3 Selecting the Number of PCle Lanes on the ML555 No of PCle Lanes P45 Shunt Location 1 5 6 3 4 1 2 Figure 4 shows the x1 and x4 PCle adapters which connect to the x8 PCle connector on the ML555 The adapters are used when inserting the ML555 into PC Catalyst or LeCroy test equipment The usage of the adapt
87. t the default destination folder as shown in Figure 7 InstallShield Wizard Choose Destination Location Select folder where Setup will install files Setup will install Silicon Laboratories CP210x Evaluation Kit Tools Release 3 1 in the following folder To install to this folder click Next To install to a different folder click Browse and select another folder C SiLabs MCUSCP21 Ox Browse InstallShield Destination Folder Cancel X1000_07_041408 Figure 7 Default CP210x Driver Destination Directory After the destination folder is created on the PC and the VCP drivers are copied to this folder the Wizard Complete status screen is displayed as shown in Figure 8 5 Click Finish to continue with VCP driver installation At this point the VCP drivers are only copied onto the host disk drive InstallShield Wizard InstallShield Wizard Complete 4 Setup has finished installing Silicon Laboratories CP210x Evaluation Kit Tools Release 3 1 on your computer X1000_08_041408 Figure 8 CP210x Directory Creation and File Installation Complete XAPP1000 v1 0 1 May 6 2008 www xilinx com 8 Interfacing to a Communication Terminal XILINX CP210x USB to UART First Driver Installation The following steps require the reference design to be successfully loaded into the FPGA on the ML555 and the USB interface cable to be connected between the PC and ML555 J1 connector 1 The
88. ted core is significantly larger than the original version 9 Invoke ChipScope Pro Analyzer by selecting Start Programs gt ChipScope Pro gt ChipScope Pro Analyzer Click on the Chain icon located at the top left of Analyzer s GUI Verify that the message in the transcript window indicates that an ICON is found XAPP1000 v1 0 1 May 6 2008 www xilinx com 76 Using ChipScope with the PLBv46 Endpoint Bridge XILINX 10 The ChipScope Analyzer waveform viewer displays signals named DATA To replace the DATA signal names with the familiar signal names specified in ChipScope Inserter select File Import and browse to plbv46_pcie cdc in the dialog box The Analyzer waveform viewer is more readable when buses rather than discrete signals are displayed Select the SI_rdDBus lt gt signals click the right mouse button and select Add to Bus New Bus With SI_rdDBus in the waveform viewer select and delete the discrete SI_rdDBus lt gt signals The signals are displayed as buses in Figure 93 Note The Reverse Bus Order operation is useful for analyzing buses in Analyzer S ChipScope Pro Analyzer ml555_mb_plbv46_pcie File View JTAG Chain Device TriggerSetup Waveform Window Help Dbe el e Ee Project miS55_mb_plbv46_pcie Trigger Setup DEV 0 MyDeviceO MC5VLXSOT UNITOMYILAD LA JTAG Chain a DEV 0 MyDeviced XC5VLX50T System Monitor Console UNIT 0 MyILAO ILA Trigger Setup Waveform
89. tility set the TeraTerm Port Baud Rate to 9600 Data Bits to 8 Parity to None and Flow Control to None B Tera Term Web 3 1 COM3 VT Tera Term Serial port setup Port Baud rate Data il Cancel Parity Stop Help Flow control r Transmit delay i 0 msec char 0 msecjline X1000_22 041408 Figure 22 TeraTerm Settings XAPP1000 v1 0 1 May 6 2008 www xilinx com 16 Executing the Reference System gt XILINX Executing the The sequence of steps to test the PLBv46 Endpoint Bridge reference system differs depending Reference on whether endpoint to root complex transactions or root complex to endpoint transactions are System run For endpoint to root complex transactions the steps must be run in the order below For root complex to endpoint transactions the steps are the same but there is no elf to download Change directories to the ready_for_download directory 4 10 XAPP1000 v1 0 1 May 6 2008 Use iMPACT to download the bitstream impact batch xapp1000 cmd Invoke XMD and connect to the MicroBlaze processor xmd connect mb mdm rst Download the executable dow executable elf Write to the PLBv46 Endpoint Bridge Control Register to enable Bus Master and the BARs mwr 0x85C001E0 0x003F0107 Use the Catalyst to write the PLBv46 Endpoint Bridge Configuration Space Header File gt Open catalyst cfg x4 sdc In the Catalyst GUI click on Run From the XMD prompt run con
90. undary Scan Chain X1000_75_041408 XAPP1000 v1 0 1 May 6 2008 www xilinx com 59 Testing with a PC XILINX Provide the PROM file name as shown in Figure 76 iMPACT Prepare PROM Files want to target a Xilinx PROM Generic Parallel PROM 31d Party SPI PROM PROM Supporting Multiple Design Versions Spartan3E MultiBoot PROM File Format MCS OTEK UFP C format EX0 BIN Isc HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name ml555_mb_plbv46_pcie Location H designs ml555_mb_plbv46_pcie X1000_76_041408 Figure 76 Defining the PROM File XAPP1000 v1 0 1 May 6 2008 www xilinx com 60 Testing with a PC XILINX Specify the XCF32P PROM as shown in Figure 77 iMPACT Specify Xilinx PROM Device C Auto Select PROM C Enable Revisioning Number of Revisions C Enable Compression Select a PROM bits xcf v Pee Delete All C Add Data Files X1000_77_041408 Figure 77 Specifying the XCF32P PROM XAPP1000 v1 0 1 May 6 2008 www xilinx com 61 Testing with a PC XILINX Select the bit file download bit as shown in Figure 78 Add Device Look in le implementation gt ae EA Imb_bram_wrapper xps_cdma_O_wrapper mb_plb_wrapper xps_central_dma_O_wrapper My Recent microblaze_O_wrapper xps_gpio_O_wrapper Documents mpmc_0_wrapper xps_intc_O_wrapper pc
91. ut For example set the trigger to Sl_wrComp arm the trigger and run xmd tcl xmd_commands dma tcl at the command prompt This produces signal activity in the Analyzer waveform viewer XAPP1000 v1 0 1 May 6 2008 www xilinx com 79 Using ChipScope with the PLBv46 Endpoint Bridge XILINX 14 ChipScope results are analyzed in the waveform window as shown in Figure 96 This figure shows the bus signals generated in Step 10 ChipScope Pro Analyzer m1555_mb_plbv46_pcie File View JTAG Chain Device TriggerSetup Waveform Window Help l gt aries cl eee Project mIS55_mb_plbv46_pcie m Waveform DEV 0 MyDevice0 XC5VLX507 UNIT 0 MyILAO ILA JTAG Chain H 3 DEV 0 MyDeviced KC5VLX50T Bus Signal ce fy eat eA cee Gi System Monitor Console UNIT 0 MyILAQ ILA AX_wrDBus 0000000000000000 poe E 1 S1_x0Bus 0000000000000000 Waveform ee Listing S1_addrAck Bus Plot S1_xdDAck Signals DEV 0 UNIT 0 Sl_wait Data Port Ss 31_rdBTerm IM_wrDBus SI_rdDBus see CH 0 SI_addrAck z PLB_MUrDAck CH 1 SI_rdDAck CH 2 SI_wait PLB_rdBurst CH 3 SI_rdBTerm CH 4 PLB_RNW CH 5 SI_rdDBus lt 0 gt IP2INTC_Irpt CH 6 SI_rdDBus 1 gt CH 7 SI_rdDBus lt 2 gt CH 8 SI_rdDBus lt 3 gt 1_wrComp CH 9 SI_rdDBus 4 gt CH 10 SI_rdDBus lt 5 PLNEBULSY CH 11 SI_rdDBus lt 6 gt PLB MAddrAck CH 12 S _rdDBus lt 7 gt CH 13 SI_rdDBus lt 8 gt PLB_MRG
92. website at XAPP1000 v1 0 1 May 6 2008 www xilinx com 5 Interfacing to a Communication Terminal XILINX http www silabs com tgwWebApp public web_content products Microcontrollers en MCU_Do wnloads htm For technical information and support of the CP210x USB to UART bridge controller integrated circuit and the associated VCP device driver visit the Silicon Laboratories website at www silabs com The ML555 contains a CP210x USB to UART bridge controller integrated circuit To communicate with the MicroBlaze processor in the Virtex 5 FPGA the Silicon Laboratories CP210x USB to UART Bridge VCP drivers must first be installed on the PC used to remotely control the DMA operations For the installation procedure it is assumed that The remote terminal console operates on the same machine that the ML555 board is plugged into No previous versions of this driver are installed on the PC running Microsoft Windows XP The ML555 has been properly configured for PCI Express compliant system power the reference design has been programmed into the platform flash configuration device on the ML555 board and the ML555 is configured to load the reference design into the FPGA from platform flash at power up With the PC powered off install the ML555 in an 8 lane or 16 lane PCI Express compliant add in card socket in the PC Connect the USB B to A cable between the ML555 USB port connector J1 and the USB connector on the PC The USB cable i
93. www xilinx com 17 Testing the PLBv46 Endpoint Bridge gt XILINX Testing the The system including the interface to the LeCroy Catalyst test equipment is shown in PLBv46 Figure 23 The root complex is the Catalyst or LeCroy test equipment and the endpoint is the Endpoint PLBv46 Endpoint Bridge in the ML555 reference system Bridge S Analyzer Catalyst or LeCroy Exerciser Root Complex Catalyst or LeCroy X1000_23_041408 Figure 23 PLBv46 Endpoint Bridge System Identifying Root Complex Endpoint Endpoint to Endpoint to root complex transactions are tested using XMD commands and C code Two Root Com plex software projects pcie_dma and pcie_mch_dma generate Direct Memory Access DMA Transactions transactions which create PCle traffic This code provides an interface to the user which allows the selection of the number of loops to run and the seed The code generates and verifies pseudo random traffic patterns on the PCle link The pcie dma c code uses one DMA channel The pcie_mch_dma c code allows the specification of 1 3 DMA channels The PLBv46 Endpoint Bridge Configuration Space Header CSH must be written for the code to run correctly The Catalyst and LeCroy scripts cfg_x4 sdc and cfg_x4 peg set up the configuration space header of the PLBv46 Endpoint Bridge The Catalyst PCI Express Bus Protocol Exerciser Analyzer has memory located at address 0x00000000 In the reference systems the PLBv46 Endpoint Bridge generic C
94. x com 2 Implementation Results Table 1 Reference System Address Map Cont d 2 XILINX Peripheral Instance Base Address High Address XPS Central DMA xps_cdma_0O 0x80200000 Ox8020FFFF PLBv46 Endpoint plov46_pcie_O 0x85C00000 Ox85COFFFF Bridge XPS Uartlite RS232 0x84000000 0x8400FFFF LMB Cntlr ilmb_cntlr 0x00000000 0x00001FFF LMB Cntlr dimb_cnitlr 0x00000000 Ox00001FFF MPMC DDR2_SDRAM_32Mx32 0x90000000 OxOFFFFFFF In XPS double click on PCle_Bridge in the System Assembly View to invoke the PLBv46 _PCle generics editor The generics shown in Figure 2 are used to configure the PLBv46 Endpoint Bridge The Xilinx Device ID 0x0505 and Vendor ID 0x10EE are displayed in many of the PCle tests done in this application note Implementation Results PCle_ Bridge plbv46_pcie_v1_00_a All Buses HOL bs Toagle Names Datasheet estore C_IPIFBAR_NUM C_INCLUDE_BAROFFSET_REG C_PCIBAR_NUM C_NO_OF_LANES C_DEVICE_ID C_VENDOR_ID C_CLASS_CODE C_REV_ID C_SUBSYSTEM_ID C_SUBSYSTEM_VENDOR_ID C_COMP_TIMEOUT C_MPLB_AWIDTH C_MPLB_DWIDTH C_MPLB_SMALLEST_SLAVE exeooo toro X1000_02_041408 Figure 2 PLBv46 Endpoint Bridge Parameters Table 2 Design Resource Utilization The resource utilization in the reference design is shown in Table 2 Resources Used Available Utilization Slice Regi

Xilinx XAPP1000: Reference System : PLBv46 PCI Express in a

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