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Xilinx PlanAhead User Guide

1. Description Names in the physical constraints file are fully hierarchical Constraints files rojects Plan4head_Tutorial labs design_files 802RC V_cos13 uc Figure 2 37 Import Constraints Dialog Box www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Floorplans 2 Set the following editable options in the Import Constraints dialog box Import physical constraints for Selects the level to assign constraints to Netlist lt netlist name gt imports top level constraints Instance Selected instance imports constraints for a selected instance The dialog box is seeded with a pre selected instance prior to running the command This button is used when importing module level constraints such as core level NCF files Constraints files Displays the constrains files to import 3 Click the Add button to locate and select the constraint files to import 4 Click OK to import the constraints Any information regarding warnings and errors during the import are displayed in the Console view and written to the planAhead 1og file Multiple constraints files can be imported to allow for separation of different types of constraints such as I O Port assignments and timing constraints Note Timing constraints will be duplicated if imported more than once To remove duplicated timing constraints delete the duplicate in the Constraints view Importing Modul
2. TimeAhead Results Excel file The results from TimeAhead timing analysis can be exported into a text file To export the data select the Export to Text File icon in the Timing Results view Netlist Module Pblock and Clock Region Statistics Reports The resource statistics displayed in the Instance Properties Clock Region and Pblock Properties View can be exported to an Microsoft Excel format file This information includes resource utilization RPM and carry chain sizes clocks and clocked instances and other relevant resource data To export the data select the Save statistics to file icon from the Statistics tab of the Instance Clock Region or Pblock Properties View The dialog box allows you to define the information to include in the report as well as how many levels of hierarchy to report A browser will allow you to specify a file name and location SSN Analysis Report The results from the PlanAhead Simultaneous Switching Noise SSN analysis can be exported to a CSV report file by specifying a file name and location in the Run SSN Analysis dialog box PlanAhead User Guide www xilinx com 25 UG632 v 11 4 26 Chapter 1 Understanding the PlanAhead Design Flow g XILINX WASSO Analysis Reports The results from the PlanAhead Weighted Average Simultaneous Switching Output WASSO analysis can be exported to a text report file by specifying a file name and location in the Run WASSO Analysis dialog box
3. f Package Device x 1 gt E Figure 8 1 Device View The amount of logic object detail displayed depends on the zoom level selected The more the zoom level is increased the more logic object detail is displayed There are many self explanatory zoom level related commands contained in the popup and toolbar menus in the Device view The Device view also has scroll bars and dynamic pan capabilities to pan the viewable area of the Device Each object displayed in the Device view can be identified by dragging the cursor over it and reading the tool tip displayed They also have object properties that can be viewed in the Properties view when selected Each selected object has popup menu commands specific to the type of object selected Sometimes the desired commands for selected objects are only available if the cursor is moved to another more appropriate view for the command such as the Netlist view Use Edit gt Find to search for specific logic object sites A dynamic cursor is utilized within the Device view The appearance of the cursor will change depending on the activity being performed The dynamic cursor also changes to indicate when an illegal logic resource assignment is being attempted For more information see Understanding the Context Sensitive Cursor There are several icons in the upper left corner toolbar of the Device view These view specific toolbar commands are covered in Manipulating Views using the Vi
4. B LO Port Interface D I O Port Set From To Description Cl w Fy E Pblock J Instance E Pblock A Rectangle E Site P Package Pin A Package Pin E Site M ERM Instance M D Pin Instance 1 0 Bank D 1 0 Port amp Bus Net Net M Path Instance M Lo Port Instance M Instance I0 Port M Yo Port J Package Pin P Package Pin I O Port TO Port Bus D 1 0 Port Tl Tl Tl Tl Tl Tl Clock Region a I O Bank Debug Core ij Instance D Debug Port Debug Channel Net i Instance Debug Core lt iil Select all instances contained by selected Pblock Select all rectangles comprising the selected Pblock Select the package pin with which the selected I O site is associated Select the IJO site with which the selected package pin is associated Select all instances belonging to the selected RPM Select the instance to which the selected pin belongs Select all top level ports assigned to the selected I O bank Select all scalar nets belonging to the selected bus net Select all instances belonging to the selected path Select all pad instances connected to selected top level port Select top level port connected to selected pad instance Select top level port assigned to selected package pin Select package pin to which selected top level port is assigned Select scalar ports belonging to the selected port bus and vice versa Select all scalar ports and port buses that are assi
5. Importing ISE Placement and Timing Results Importing ISE Placement and Timing Results With New Project Wizard You can create a new project and populate the project with a netlist and timing and placement report files from an ISE software implementation For more information about creating a new project that imports ISE implementation results see Creating a Project with ISE Placement and Timing Results Importing ISE Placement and Timing Results from PlanAhead Runs ISE placement and timing results can be imported and used to analyze the design The PlanAhead environment makes it easy to import the results from any PlanAhead run For more information about implementing the design see Importing Run Results Importing ISE Placement and Timing Results from Outside PlanAhead Implementation results from outside of PlanAhead can be imported using the File gt Import Placement and File gt Import TRCE Results commands For more information about importing ISE implementation results see Importing ISE Implementation Results Importing ISE Placement and Timing Results from Project Navigator PlanAhead User Guide UG632 v 11 4 When using PlanAhead with Project Navigator ISE placement and timing results are automatically imported when you run the Analyze Timing Floorplan Design process in Project Navigator Additional ISE placement or trace timing results from previous runs can be imported by using the PlanAhead Fi
6. Run Name Enter a name for the implementation run or accept the default name Description Enter any description for the implementation run Synthesized Netlist Select the name of the synthesis run to implement Floorplan Select the name of the Floorplan to implement www xilinx com 191 Chapter 7 Implementing a Design XILINX Part Select a target part or accept the default Constraints Browse to select a single top level UCF constraint file to use for the run This field is disabled if a floorplan is selected as the constraints from the floorplan will be used Strategy Select the implementation strategy to use for the Run For more information see Creating Strategies G Choose Strategy Tool Version ISE 11 v A MapGlobalOptParHigh A MapLogicOptParHighExtra 3a MapTimingIgnoreKeephierarchy 2g MapCoverBalanced 28 MapCoverdrea A ParHighEffort Je ParStandard A MapGlobalOptLogicOptRetimingDupP Description Select ISE Defaults including packing registers in IOs off Eye MAP Timing Driven High Effort Normal Extra Effort PAR High Ef MAP Timing Driven Global Optimization High Effort Normal Extra MAP Timing Driven Logic Optimization Register Duplication High MAP Timing Driven Global Optimization Logic Optimization Retimi MAP Timing Driven Ignore Keep Hierarchy High Effort Normal E MAP Balanced Cover Mode PAR High Effort MAP Area Cover Mode PAR High
7. XILINX Chapter 8 Analyzing the Design This chapter describes the many design analysis features of the Floorplan environment available in the PlanAhead software There are additional analysis features described in Chapter 5 I O Pin Planning Chapter 6 Creating and Analyzing the RTL Design and Chapter 9 Analyzing Implementation Results Most of these features can be used prior to implementing the design They are intended to identify any potential design issues prior to running the implementation tools There are also a wide range of features useful for analyzing an implemented design PlanAhead enables you to import the placement and timing results from ISE implementation runs for further analysis and floorplanning This chapter contains the following sections e Using the Floorplanning Environment e Analyzing the I O Pinout and Clock Logic e Analyzing the RTL Design e Analyzing the Synthesized Design Using the Floorplanning Environment Using the Device View The Device view displays all of the FPGA device resources including the logic fabric clock regions I O pads BUFGs DCMs Pblocks instance locations and net connectivity The locations on the device where specific logic can be assigned are referred to as Sites PlanAhead User Guide www xilinx com 221 UG632 v 11 4 222 Chapter 8 Analyzing the Design g XILINX gt LBP R O4 R aK k
8. Figure 2 11 Creating a Project with RTL Sources 2 Click Next Selecting a Product Family and Default Part The next page in the New Project wizard prompts you to select a product family and default part 44 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Create New Project Wizard to Create a New Project New Project Choose a Part and a Floorplan Name Enter a name for your floorplan and choose a Xilinx device Product Family virtexS Choose Part xcSvh30fF324 1 Floorplan name floorplan_1 Figure 2 12 New Project Wizard Product Family and Default Part Page 3 Select the desired target product family architecture and default part 4 Click Next Note Once a Product Family is selected for a Project it cannot be changed A new Project will need to be created to target a different architecture The Default Part however can be changed during Synthesis and Implementation Run creation and during Floorplan creation Adding Source Files or Directories The next page in the New Project wizard enables you to select HDL source files or directories that contain HDL source files Add Files To add individual files to the Project select the Add Files button and browse to and select the file s Add Directories To add the contents of an entire directory and its subdirectories to the Project select the Add Directories button and browse to and select the directory All
9. P Path Setup 0 050 usbEngine1 usb_dma_wb_in BU2 U0 gen_fifo18_36 fafifo18_36 Fblkfinst_few k1 1 inst_fed one_p usbEngine1 u4 inta_msk 5 P Paths Setup 0 050 usbEngine1 usb_dma_wb_in BUZ2 UO gen_fifo18_36 fgfifo18_36 fblk inst_few ki 1 inst_fedjone_p usbEngine1 u4 inta_msk 7 SLICE_x45v2 IRo Sede Flow i Figure 2 26 PlanAhead Floorplanning Environment Note If any warning messages appear in the PlanAhead Console view examine the messages or the PlanAhead log file to identify the design errors or specific issues that may cause problems during implementation Managing Projects The project maintenance commands described below assume a synthesized netlist was imported to create the Project Some of the commands are not available or applicable for PinAhead Projects or Projects created with HDL sources Opening an Existing Project Existing Projects are opened in the PlanAhead software by using the Open Project command or in Windows by double clicking any PlanAhead project PPR file which invoked PlanAhead and open the project As Projects are opened the project state from the time the Project was last closed is restored The state of all previous Implementation runs is restored Previously opened Floorplans are re opened and available for modification PlanAhead User Guide www xilinx com 59 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX The applicable view layout is displ
10. Play back a recorded script of debug commands later Tcl Commands Selecting Nets for Debug The first step in the PlanAhead ChipScope debug flow is to identify the set of nets to debug PlanAhead makes the debug net selection process as simple as picking a set of nets or busses in the Netlist view and selecting the Add to ChipScope Unassigned Nets popup command Net selection is also available by selecting nets or busses in the Schematic view Unassigned Nets List PlanAhead User Guide UG632 v 11 4 PlanAhead maintains an Unassigned Nets list Figure 11 3 in the ChipScope view Window gt ChipScope The Unassigned Nets list is a convenient place to bookmark nets of interest while browsing the design Nets may be stored for later debug by dragging and dropping from the netlist or schematic view into the Unassigned Nets list Nets may also www xilinx com 331 Chapter 11 Debugging the Design with ChipScope g XILINX be added to the Unassigned Nets list by selecting the nets and selecting the Add to ChipScope Unassigned Nets popup menu command ChipScope Q sa 9 chipscope_icon_v1 u_icon es gt z Ses a Bear Oar zs chipscope_ila_v1 csdebugcore_0_0 A gt CLK 1 E Om D A22 Fa 9 i gt Unassigned nets 56 counter1 24 FD 2 counter2 32 af A Console D 1 0 Ports amp ChipScope Figure 11 3 Unassigned Nets List in ChipScope Window ChipScope Wizard based Debug Core Inser
11. SSN is available for the Virtex 6 FPGA device in the PlanAhead software See Running Simultaneous Switching Noise SSN Analysis page 157 for more information Weighted Average Simultaneous Switching Output WASSO is supported in Virtex 5 and Spartan 3 device families through rules published in the device specific select I O User Guides See Running Weighted Average Simultaneous Switching Output WASSO Analysis page 161 for more information 10 Perform signal integrity analysis using IBIS or HSPICE models for production boards 126 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PinAhead Overview PinAhead Overview The PinAhead environment provides an interface to analyze the design and device I O requirements and to define an I O pinout configuration or pinout that satisfies the requirements of both the PCB and the FPGA designers The PlanAhead software enables the creation of I O port signals and the import of an I O port list in CSV UCF or HDL format This allows for early and intelligent pinout definition to eliminate pinout related changes that typically happen later in the design It can also substantially improve the performance Often designers are hindered by a non optimal pinout that causes further delays when trying to meet timing and signal integrity requirements By considering the data flow from PCB to FPGA die optimal pinout configurations can be achieved quickly thus
12. receiveADCValic TIMESPEC TS_GCLK_F PERIOD GCLK_F 16 A QQ Netlist 2 Constre Modifying Timing Constraints Values Figure 8 29 Timing Constraints Grouped by List Most constraint values can be modified by selecting a constraint and viewing the Constraints Properties The appropriate changeable values for the constraint are shown in the dialog box PlanAhead User Guide UG632 v 11 4 www xilinx com 245 Chapter 8 Analyzing the Design g XILINX Constraints Od g x z sia W amp Constraints 809 Clk period PERIOD 2 TIMESPEC TS_GCLK_F PERIOD GCLK_F 16 Basic period 0 Timespec period 1 Source C Data PlanA4head_Projects project_2 project fem TIMESPEC TS_GCLK_F PERIOD GCLK_F Derived period 1 Pad clk offset OFFSET 20 Hne To Go F Path delay FROM TO 0 Period Specification Time groups 780 Basic group TNM 780 ihh Multi group TIMEGRP 0 wath bs s False path TIG 7 Duty Cycle HIGH 50 B Off chip delay 0 Group ea e C C Priority e lt gt Selection Netlist amp Constraints Figure 8 30 Modifying Timing Constraints Properties The various dialog boxes for each constraint type are too numerous to describe here Use the correct syntax when defining constraints values Refer to the Xilinx Constraints Guide for more information on constraints and constraints sy
13. www xilinx com Host execution is performed with SSH a service provided by Linux operating system and not PlanAhead In order for this to work you must configure SSH so that you are not prompted for a password each time you log in to a remote machine If you have not configured key agent forwarding for passwordless SSH or if you have configured SSH and you are prompted for a password see Appendix C Configuring SSH Without Password Prompting 211 Chapter 7 Implementing a Design g XILINX 212 Linux to Linux hosting is the only supported platform because of security and lack of remote shell capabilities of windows systems ISE tool installation is assumed to be available from any login shell which means that XILINX and PATH are configured correctly in your cshrc bashrc setup scripts If you can log into a remote machine and enter map help without sourcing any other scripts this flow will work If you do not have ISE set up upon login cshre or bashrc you can use the Run pre launch script option to pass an environment setup script to be run prior to all jobs PlanAhead installation must be visible from the mounted file systems on remote machines If the PlanAhead installation is stored on a local disk on your own machine it will not be visible from remote machines PlanAhead project files ppr and directories data and runs must also be visible from the mounted file systems on remote machines
14. 3 Click Next to continue The Import Netlist dialog box appears 4 Set the following two editable options in the Import Netlist dialog box Netlist file Enter a name to identify the top level netlist in this project Use the File Browser to select the top level netlist file for the design Netlist directories Use the Add button to select directories to be searched for lower level modules and cores during netlist import By default the PlanAhead invocation directory and the directory that the top level netlist was selected from are included in the search path You can arrange the order in which to search these PlanAhead User Guide www xilinx com 61 UG632 v 11 4 62 Chapter 2 Creating and Managing Projects g XILINX directories by selecting them and using the Up or Down buttons Directories can be removed from the search path by using the Remove button Update Netlist Import Netlist Specify the Edif netlist that contains the top module and optionally a list of directories to be used as a search path during netlist reading Netlist file C Data Plan4head_Projects Plan4head_Tutorial labs design_fi Netlist directories C Data planshead_Projects Plan4head_Tutorial labs design_files Figure 2 30 Update Netlist Wizard Import Netlist Dialog Box 5 To continue click Next 6 Inthe Update Netlist Summary dialog box click Finish to continue The netlist will now be imported in
15. 3 Select the target interface to which you will add the I O ports To remove I O Ports and Interfaces 1 Select a port or Interface 2 Select Unassign from Interface from the popup menu To delete Interfaces select an Interface and select Delete from the popup menu or press the Delete key Placing I O Ports PinAhead provides a variety of ways to assign I O Ports to package pins Individual I O Ports groups of I O Ports or Interfaces can be selected in the I O Ports view and graphically assigned to package pins in the Package view or I O pads in the Device view Online DRCs can be toggled on or off during interactive placement The three placement mode options available for assigning I O Ports are the following Each is described below e Place I O Ports in an I O Bank e Place I O Ports in an Area e Place I O Ports Sequentially For information on automatic I O Port assignment see Automatically Assigning I O Ports page 146 142 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Placing I O Ports Enabling Interactive Design Rule Checking While the PlanAhead software is not a sign off pin assignment tool it does try to ensure a legal pin out The interactive I O placement routines check many common error cases This capability is toggled on and off using the I O Placement section of the General dialog box accessible using Tools gt Options gt General Using the feature will not allow placement
16. Creating an Empty Project for I O Pin Planning Creating a Project by Importing RTL Sources Creating a Project with Synthesized EDIF or NGC Format Netlists Creating a Project with ISE Placement and Timing Results Note If you select Do not import sources at this time above and you do not import a netlist the PinAhead pin planning layout will launch when you finish defining the new project 40 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Create New Project Wizard to Create a New Project Creating an Empty Project for I O Pin Planning An empty project can be created for I O pin planning purposes prior to having completed HDL or synthesized EDIF For more information about I O pin planning see Chapter 5 T O Pin Planning 1 Select the Do not import sources at this time option in the Design Source dialog box New Project Design Source Specify the type of sources for your design You can start with RTL or a synthesized EDIF Import RTL Sources You will be able to run RTL analysis synthesis and implementation Import synthesized EDIF or NGC netlist You will be able to run post synthesis design analysis planning and implementation Import ISE Place amp Route results You will be able to do post implementation analysis of your design Do not import sources at this time You will be able to do pin planning now and import a netlist later Figure 2 8 Cr
17. Figure 5 37 SSN Results View The SSN Results view displays the following information Name Displays the I O Banks available in the device Each I O bank has pin icons indicating how full the bank is and a check mark or red circle indicating whether it passed or failed Group Displays the various groups of pins with like I O standards assigned within the bank and displays their status Groups are determined automatically based on the I O standards drive strength slew rate and phase assigned Noise V Contributed Contains the SSN aggregate of each group generated by the I O standard drive strength and slew type of that group Bank Total Defines aggregate SSN predicted for a bank or group If multiple phases are specified for the groups of a given bank the SSN contributions of groups with different phases will be accumulated separately and the maximum of these will be reported Because the SSN of an output are isolated to the output of that Bank one SSN Bank total does not affect another Bank total This column identifies which I O groups are creating the most SSN and how much margin they use up Margin V Available Defines the allowable noise margin for that particular I O standard on the high side of the signal as it switches to a 1 It is strictly based on the DC logic levels implicit in the I O standard no quantity information is taken into account and represents the margin that the weakest drive o
18. g XILINX SL 74 82 FO 2 S SPECIAL_SVGA_TI gt SL 74 60 FO 2 Cl 5 O SL 73 60 FO 2 SL N P CR MUXCY lt fil Package Device E Schematic Figure 8 16 Annotated Pins in the Schematic View v lv Annotating Cell References and Instance Equations onto Instances The PlanAhead Options dialog box Schematic settings enable you to tag instances with Cell References and Instance Equation values The PlanAhead Options dialog box is available by selecting Tools gt Options and clicking Schematic in the Options dialog box 1 To annotate these values you must first set the Attribute type field to Instance 2 Select the desired values to annotate on the left side of the dialog box below and use the arrow indicators to move them to the right side labeled Displayed DB Attributes 3 Click OK 234 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Floorplanning Environment G PlanAhead Options Attribute Types v Available DB Attributes Displayed DB Attributes Cell Ref Inst Equation Shortcuts iia Strategies eT Text Editor v Figure 8 17 PlanAhead Options Schematic Instance Annotation An example of the resulting instance annotation is shown below RIX GIR X SPECIAL_SVGA_TIMING_GENERATION pixel_count_inst_cy_16 CR MUXCY F Package Device 3 Schematic x 1 b gt Figure 8 18 Annotated Ins
19. 260 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Analyzing the Synthesized Design 4 Click OK to invoke the selected DRC checks Viewing DRC Violations Once completed the DRC Results view will appear Violation Properties ogg x Netlist og x gt BN 5 W DPOP 1 6 6 Nets 899 DSP p0 _2_5 47 0 output is not pipelined Pipelining DSP48 ouput will improve H 5 Primitives 200 R cpuEngine or1200_top fi gt D E 1 fftEngine MtTop performance Both multiplier adder output can t Nets 73 be pipelined H 5 Primitives 2 lt itt gt 2 finst bft GS Nets 2314 M4 General Details 3 Properties R Selection lt ili gt A Name Severity Details e 6 5 All Violations 104 B DSP48 73 amp DSP output pipelining DPOP DPOP 1 Warning nO_2_5 47 0 output is not pipelined Pipelining DSP48 ouput will improve perfo Q DPOP 2 Warning DSP p0_2_6 47 0 output is not pipelined Pipelining DSP48 ouput will improve perfo amp DSP multiplier output pipelining OMOP DMOP 1 Warning The multiplier output of DSP pO_2_5 47 0 is not pipelined Pipelining the ouput will i DMOP 2 Warning The multiplier output of DSP pO_2_0 35 0 is not pipelined Pipelining the ouput will i DMOP 3 Warning The multiplier output of DSP p0_2_7 47 0 is not pipelined Pipelin
20. E orig_Fp_16ns A 802RCV_cos13 ucf General Part Info Constraint Files Attributes fe Selection Figure 2 45 Floorplan Properties Constraint Files Tab 6 Click the Attributes tab In this tab you can assign attributes to the Floorplan using the Define new attributes toolbar button Figure 2 46 Define New Attributes Toolbar Button in Properties View Closing a Floorplan To close the Floorplan select File gt Close Floorplan or click the X icon to the right of the Floorplan tab Figure 2 47 Floorplan Tab A dialog box is displayed to confirm the closing of the Floorplan Click OK to proceed If unsaved changes exist in the Floorplan being closed you are prompted to save the changes Click OK to save the changes Closed Floorplans are available within the Project and can be re opened at any time All Floorplans that exist in the Project are listed in the Floorplans view PlanAhead User Guide www xilinx com 75 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX 76 Id Name Device i State 1 floorplan_1 4 lx25 Open 2 original_fp 4y lx25 Open D Properties amp Selection Figure 2 48 Floorplans View Floorplans can be opened closed copied and deleted from the Floorplan view Deleting a Floorplan To remove a floorplan from a Project and to remove the data from disk select File gt Delete Floorplan The command produces a confirming dialog box
21. Import Synthesis Results Import Constraints Import physical and timing constraints from a UCF file You can also import a UCF File later with the Import Constraints command Constraints Files BS C Data Planahead_Designs Planahead_TutoriallProjects project_cpu_netlist project_cpu_r Figure 7 31 New Floorplan Wizard Import Constraints Click the Add button to locate and select top level UCF and NCF constraint files for import You can arrange the order in which to import these files by selecting them and using the Up or Down buttons Files can be removed from the list by using the Remove button If module level constraints are being used do not include them here For more information on importing module level constraints see Importing Module Level Constraints Click Next to continue The UCF files are imported into PlanAhead This may take a few moments The Import Synthesis Results Summary dialog box is now displayed Click Finish to proceed The PlanAhead environment displays with Synthesis run results imported and a new floorplan open if one was created Importing Implementation Run Results Implementation run results can be imported into PlanAhead for further analysis or floorplanning The placement is imported and displayed in the form of unfixed LOC constraints You can visualize where the ISE implementation tools placed various logic objects The Trace timing results are also impo
22. Specifies a new target SLICE utilization target for Pblocks 3 Click OK to place Pblocks in the design A Place Pblocks progress meter is displayed while the Place Pblocks command is running The Pblocks will be automatically sized and placed based on SLICE utilization only 314 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Placement LOC Constraints FANON DE R E ERR P ai lt DERE l 7 Figure 10 35 Auto Placed Pblocks Larger Pblocks can be partitioned again and Place Pblocks command can be performed within them Refer to the PlanAhead Tutorials for ways to create top level Floorplans using the Partition and Place Pblocks commands Working with Placement LOC Constraints Primitive logic elements can be assigned to specific logic sites using either the Create Site Constraint Mode or Create BEL Constraint Mode PlanAhead includes BEL level constraint assignments to lock logic to specific gates within the site Understanding Fixed and Unfixed Placement Constraints PlanAhead differentiates placement constraints that are user assigned to those that are assigned by the ISE implementation tools User assigned constraints are either defined within imported UCF files or manually assigned in PlanAhead Constraints that are user assigned are considered fixed and are displayed in a different color All placement constraints
23. Statistics Pins Children Attributes Connectivity Selection Figure 9 7 Tracing Nets from Connectivity Tab The Net Properties will then display under the Connectivity tab All of the instances and pin names the net connects to are listed You can continue this process to traverse any logic in the design PlanAhead User Guide www xilinx com 279 UG632 v 11 4 Chapter 9 Analyzing Implementation Results g XILINX To step back or advance through the selected items click the Previous Object and Next Object arrow toolbar buttons The highlighted items displayed will also be recalled as the previous steps are navigated Highlighting Selected Objects Highlighting Objects PlanAhead has a very flexible highlight mechanism allowing selective highlighting of objects Highlighting enables you to display multiple placement groups at once using one or more colors Highlighted objects remain highlighted even when you click elsewhere in PlanAhead You can highlight any number of selected objects PlanAhead has a lot of different ways to select the desired logic objects Once selected objects can be highlighted with the Select gt Highlight command or by selecting Highlight from the popup menu in most views This command operates on the selected logic When highlighting Pblock logic you may use the Highlight Primitives command in order to highlight the lower level logic For more information see Using the Select P
24. The table is updated dynamically as the Run commands are progressing Runs that are launched outside of PlanAhead using the PlanAhead generated scripts will cause the table to update upon invoking PlanAhead Using the Design Runs View Popup Menu Commands The Design Runs view popup menu contains the following commands Synthesis or Implementation Run Properties Displays the Run Properties View For more information see Viewing and Modifying Run Properties Delete Deletes the selected Runs You are prompted to confirm prior to removing any runs Apply Strategy Invokes the Strategy chooser to select a new run Strategy This command is only available prior to launching the run Save as Strategy Enables you to save any modifications made to the applied strategy to a new strategy file for future use Edit Strategies Invokes the Tools gt Options gt Strategies dialog box to edit or create Strategies Launch Runs Invokes the Launch Runs dialog box to launch the selected runs Reset Runs Invokes the Reset Runs dialog box to remove previous run results and to set the Run status back to Not Started for the selected runs Import Run Loads the resulting netlist from the synthesis run or implementation results from ISE in to the PlanAhead analysis environment The active loaded run appears in bold text in the Design Runs view Run Multiple Strategies Invokes the Run Multiple Strategies dialog box to create and launc
25. Using the Viewing Environment For more information about the I O pin planning environment see Chapter 5 I O Pin Planning 84 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead Viewing Environments Design Analysis and Floorplanning View Layout new C DataPlandl wad Designs dem 0 9iproject_new p oject new ppr Pla View Tools Window arjoa projet pew I archy H Physical Hierarchy A So Ftio Properties BD F ROOT 8 Prpacal Resource Lstmates Ste Type Avaliable tut 2640 Gid 32640 wa soo an 3120 SCAN BFOs meoc x wt daj oog oxron The PlanAhead design and analysis environment is invoked automatically from Project Navigator when you select Floorplan Area lO Logic or Analyze Timing Floorpan Design from the Processes pane or the Tools gt PlanAhead menu as described above It can also be loaded from within PlanAhead by selecting Layout gt Load Layout gt PlanAhead Default When a Floorplan is opened and made active the default Floorplan environment layout configuration is displayed Layag Netist ogox z Ato E O Mets E Darm e E pengu dait S R pengikut _o D N engipipu_ db _ a Ta ENT E TT S B aigen job tj N oingneipu nd dst o E pudingli at Wy ENGADE SRAM T tengra juib dma r n P tingreihnd n B ustingne tfusb_ot 1 ad Gormes Satistics Ineterces Rectargies Attr utes 5 Properties Selection YO Poets
26. Verilog or VHDL A Verilog or VHDL format file header that contains ports can be imported to populate the I O Ports view within PinAhead You can then assign these I O Ports to physical package pins to define the device pin configuration Refer to Chapter 5 I O Pin Planning for more information about the HDL file content and format Top Level Netlists EDIF Currently PlanAhead supports the importing of EDIF netlists The netlist should be synthesized for a Virtex 4 Virtex 5 Virtex 6 Spartan 3 or Spartan 6 device PlanAhead can construct the design using multiple EDIF netlists supporting a hierarchical design methodology When you select the top level logic lower level modules are imported automatically Incremental netlist import capabilities allow netlist updates at any level of design hierarchy In process floorplanning constraints are maintained through iterations Module Level Netlists EDIF PlanAhead can construct the design using multiple EDIF netlists supporting a hierarchical design methodology When you select the top level logic lower level modules are imported automatically You can define a search path to locate the design modules The advantage to this process is more flexibility when updating the design PlanAhead has a robust incremental netlist import capability allowing netlist updates at any level of the design hierarchy Top Level Netlists NGC If top level NGC files are used PlanAhead automatical
27. Virtex 4 www xilinx com 263 Chapter 8 Analyzing the Design 264 g XILINX RAMB16 Rule Table 8 9 RAMB16 Rule Rule Name Rule Abbrev Rule Intent Severity RAMB16 output RBOR RAMB16 has a register on the output Information registers side to use this register the register should be synchronously controlled Virtex 4 Netlist Rules Table 8 10 Net Rules Rule Name Rule Abbrev Rule Intent Severity Driverless Nets NDRV Checks that each net has a proper Warning driver pin Table 8 11 Instance Rules Rule Name Rule Abbrev Rule Intent Severity Black Box INBB Checks that there is no blackbox Warning Instances undefined logics in the netlist Running Timing Analysis About TimeAhead TimeAhead is used in various modes during different stages of design completion It can provide early estimations of path delays to assist during floorplanning as well as for detailed path tracing debugging and constraint assignment It has two different modes for Estimated and No Interconnect style analysis The more physical constraints such as Pblocks and placement constraints are assigned in the Floorplan the more accurate the analysis results will be Running TimeAhead 1 Runa timing analysis using one of the following methods Select Tools gt Run TimeAhead Click the Run TimeAhead toolbar button e Figure 8 51 Run TimeAhead Toolbar Button www xilinx com Plan
28. www xilinx com 337 Chapter 11 Debugging the Design with ChipScope g XILINX Debug Core Properties Og x e gt a csdebugcore_0_0 enable_storage_qualification max_sequence_levels T sample_data_depth 1024 sample_on rising edge use_rpms enable_storage_qualification qualify storage General Options Port amp Properties Selection ChipScope sa 9 chipscope_icon_vl u_icon Ow CLK 1 OB TRIGO 32 chipscope_ila_vl csdebugcore_0_1 Ow CLK 1 B TRIGO 32 chipscope_ila_vl csclebugcore_O_2 Ow CLK 1 S TRIGO 24 5 Unassigned nets 0 T e i m E A Console D 1 0 Pons ChipScope Figure 11 12 Debug Core Parameters 338 www xilinx com PlanAhead User Guide UG632 v 11 4 Using the Core Insertion Flow XILINX Debug Port Properties e eR B TRIGO counter_width Disabled exclude_from_data_storage O match_type basic match_units 1 Select an option above to see description of it General Options Channel Properties Selection ChipScope chipscope_icon_v1 u_icon chipscope_ila_v1 csdebugcore_0_0 Om CLK 1 ed chipscope_ila_vl csdebugcore_O_1 Ow CLK 1 gt B TRIGO 32 chipscope_ila_v1 csdebugcore_0_2 CLK 1 gt TRIGO 24 5 Unassigned nets 0 console 1 O Ports amp ChipScope Figure 11 13 Debug Port Parameters Implementing Debug Cores ChipScope Pro ICON and ILA
29. 2 Select File gt Import Constraints The selected instance will be seeded in the Import Constraints dialog box www xilinx com 327 Chapter 10 Floorplanning the Design Import Constraints Import physical constraints for XILINX Netlist FPGA_RCY_802_11 Instance receiver RChainTopInst C Description The physical constraints are based on the logical hierarchy Q Names in the physical constraints file are relative to instance receiver RChainTopInst CONVDECOD Constraints files w4head_Tutorial labs projects Project_2 export yviterbi witerbi ucf Figure 10 52 Import Module Level Constraints 3 Set Import physical constraints for to Instance with the proper instance selected in the field 4 Use the file browser to select the exported UCF file for the IP instance 5 Click OK to import the constraints The physical constraints and AREA_GROUP constraint will be reproduced in the same location as they were created Note The site locations must exist in the new target device Duplicating Placement for Identical Modules Placement constraints can be duplicated for identical modules by selecting the instances individually and using the File gt Import Constraints command as described in Reusing the IP Module Once the constraints are imported for one instance the Pblock can be moved to allow the second instance to be imported in t
30. 276 Expanding Logic in the Schematic View 6 0 cece cece eee eee eee 277 Tracing Logic Paths using the Properties Dialog Box Connectivity Tabs 278 Highlighting Selected Objects 0 0 0 cece e ene 280 Highlighting Objects ers eninin ccc a ee 280 Unhighlighting Objects esiet oeiee seie pere nee eens see Sle pE wens eee 280 Highlighting Placed Modules 000 0 cece cece eee eee 280 Using the Select Primitives and Highlight Primitives Commands 280 Marking Selected Objects occ ccsssccasccsedeidesbevage card esavantrsenvens 281 Marking Objects 22 esegua i ask aege gae oiea eea a aE a A eee anes 281 Removing Marks sssocrcsisrsr istr oiu vende EnD EEEE E EEEE EE E E E 282 Displaying Design Metrics uaannunsranu ccc eee nes 282 Using the Metrics VieW scis cics ssc teap tina dees dks saad aoe eases eee ee 282 Displaying the Metric Maps in the Device View 00 0000000 eee 283 Hiding Metric Map Display irinin ieo Ena ec e ii 284 Using the Metrics Results View osre cessieteus tieses edee ied eeasieitpi senus 284 Configuring the Metric Ranges 0 000 e eee eee eee ee eens 285 Chapter 10 Floorplanning the Design UG632 v 11 4 Floorplanning Overview ipod 56a dog od Be wah phn hu ed hem cle ep ete rnrn 287 Floorplanning Methodology Tips 0 0 cece eee eee eee 287 Partitioning the Design by Creating Pblocks
31. 39 Using the Getting Started jump page 38 Types 38 Empty 38 40 Implementation results based 39 40 RTL based 38 40 Synthesis netlist based 38 40 Project Navigator integration 79 Analyze Timing Floorplan Design Post Implementation 82 86 Floorplan Area IO Logic Post Syn thesis 82 I O Pin Planning Post Synthesis 81 I O Pin Planning Pre Synthesis 81 Properties view 238 R Recommended Pin Planning Method 125 Remote Hosts Linux Configuring 211 355 Resource utilization Estimates for modules 176 Statistics 253 Using utilization statistics to size Pblocks 307 resource utilization statistics Exporting 254 257 RTL Editor 171 View specific popup menu com mands 172 RTL Hierarchy view 176 RTL Netlist view 175 resource estimates 176 View specific popup menu com mands 176 RTL Schematic view 177 Run Elaboration 173 Run Implementation 191 195 Run Multiple Strategies 188 193 Run Synthesis 185 Run Tel Script 37 Running DRC 178 Running PlanAhead 35 PlanAhead User Guide UG632 v 11 4 www xilinx com 359 XILINX S Save Floorplan 76 Schematic view 227 Annotating fanout and slack on sche matic pins 233 Expanding and collapsing logic for selected modules 230 Expanding logic from selected pins 229 Printing 232 Regenerating schematic 231 Selecting objects 232 Traversing hierarchy 231 Viewing logic hierarchy 228 Viewing timing path logic 236 View specific popup me
32. 4 E Wortrol_ped_t_o OpMode_pad_0_o HG Datett padio EY mms Package Pee a Name D wa D Corse _ P Package Pins toaton f Bork NORJ DrveSrengh Sewe PA Type 17 ooa 12 20W detak 15 WOMORIS 12 20W detak 17 WweMonS 12 20W detak 15 1MOS 12 ROW detak 17 WMO 12 ROW detak 15 LvCMOSZS 12 20W detak Brk Type Off Por Cod votage Min Trace Cty MaxTraxceDiy 106 Alas Ste Type Dataln_ pod 0 2 17 User 10 wn 76 59 99 5 C6073 10_L0N_17 Dataln pad 0 2 17 Ler 10 tip 73 40 5 10 106 07 OLP Omaln pad 17 User 30 uw aD 75 12 108076 HO_LIN_17 2 17 User 10 us rr 93 08 ONIS OLI Ractive p 2 17 User 10 es 97 99 OIN OINI PAJDA LOMO 3 2 17 User 10 sy M0 I0 ITI OpMode pa 17 User 10 76 10 88 79 108 2072 DReady p 9 17 User 10 73 95 92 11 108 OTE Figure 4 2 Default PinAhead View Layout The areas of the viewing environment are the following Object Properties Netlist Sources Physical Hierarchy Clock Regions Selected Objects Constraints I O Ports list Package Pins Console View Results Views Timing Find Design Rules Check SSN P o pP r 96 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX The Viewing Environment 5 Split Workspace Device View Package View Schematic View Instance Hierarchy View Reports WASSO Results The PinAhead environment displays information about the specific device package and the design specific I O information To open the PinAhead
33. After you select the Show command the metric results are displayed in the bottom view 284 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Displaying Design Metrics The information in the Metric Results view can be sorted by clicking any of the column headers You can sort by a second column by pressing the Ctrl key and clicking a second column header Add as many sort criteria as necessary to refine the list order The Results are automatically updated as the floorplan is modified The different types of metrics such as for Pblocks CLBs and primitives are displayed in different charts Each type has its own tab along the bottom of the Metrics Results view Id Name 1R14c9 2 R22C27 3 R12C26 4 R15C27 5 R24C1 Type Row Cal Sites Instances LUT Util CENTER 12 CENTER 35 CENTER 34 CENTER 35 CENTER 2 gy E CLBs 1280 x 2 Console E Pblocks 6 Figure 9 16 Metric Type Tabs in Metrics Results View Configuring the Metric Ranges PlanAhead User Guide UG632 v 11 4 The bin ranges for each map can be configured within the Properties view Colors and the range display are fully adjustable New bins can be added or deleted to define desired ranges To do so select the Apply changes button in the Metrics Properties view or select Apply Changes from the popup menu To insert a new range bin select the desired bin to split and select Insert Bin from the right click popup menu The dialo
34. Constraints b Figure 8 21 Display Percentage of Logic Selected in Module PlanAhead User Guide www xilinx com 237 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX 238 A sub hierarchy for any submodule can be displayed by double clicking on the module in the Hierarchy view To select logic parent modules for Pblock assignment in this view use the Select Primitive Parents command Using the Properties View All PlanAhead objects have associated properties As objects are selected their properties will automatically appear in the Properties view The Properties view has object specific tabs that display various types of information The Properties dialog box is dynamic by default As new items are selected the view updates automatically Many of the object types have multiple types of properties displayed View tabs are added to the bottom of the Properties view to accommodate various types of information Select the different tabs to display or modify information about the selected object gt fit a pblock_1 Physical Resource Estimates Site Type Available Required o Util 256 175 256 152 40 34 24 21 0 RAMBFIFO36 1 0 Carry Statistics General Statistics Instances Rectangles Attributes Selection Figure 8 22 Property View With Tabs Using the Properties View Toolbar The Properties view toolbar contains the following commands Table 8 2 P
35. Deleting Selected Runs Toolbar Button Select the Delete popup menu command in the Design Runs view Select the Edit gt Delete command Press the Delete key 204 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Importing Run Results Importing Run Results Importing Synthesis Run Results PlanAhead enables you to import the results of a synthesis run for further analysis I O pin planning floorplanning and implementation Once the synthesis run has completed a dialog box is displayed prompting you to import the run For more information see Running Synthesis During the import you can elect to import the netlist for logical netlist exploration only or create a Floorplan which enables a wide range of design analysis floorplanning and implementation options Once a synthesis run is complete you can import the resulting netlist as follows 1 Select an synthesis run in the Design Runs view 2 Select one of the following commands Select Import Run from the popup menu in the Design Runs view Select the Import Run toolbar button in the Design Runs view a Figure 7 28 Import Run Toolbar Button Note Double clicking on any completed run in the Design Runs view will invoke the import Run dialog on that run The Import Synthesis Results wizard is invoked Import Synthesis Results Import Synthesis Results Import the netlist generated by the synthesis run synth_1 There are curren
36. Figure 7 18 Setting Synthesis Strategy Options All of the command line options and their preset values are displayed in the view A description of the command option intent can be displayed by selecting any of the options Selecting an option enables a pulldown menu on the right side to view the available values for the option Map map x pr smartquide ir cm ignore_keep_hierarchy c z pr Pack internal flops latches into input i output 0 or both b types of IOBs per Nnbinne ae Danmark Figure 7 19 Setting Implementation Strategy Options PlanAhead User Guide www xilinx com 199 UG632 v 11 4 Chapter 7 Implementing a Design g XILINX Overriding ISE Command Options Set in a Strategy The Options tab enables you modify Strategy options Ty gt impl_2 Map map lt nane gt smartquide Input registers i ir Output registers 0 t Input and output registers b cm lt none gt ignore_keep_hierarchy pr Pack internal Flops latches into input i output o or both b types of IOBs General Options Monitor Reports la Apply g Cancel Figure 7 20 Run Properties View Options Tab Using the popup commands you can override edit the Strategy for the selected run and save or save as the options to anew User Defined Strategy Additional command options that are not displayed can be entered in the More Options field under the desired command Click the
37. Import Constraints 1 Click the Add button to locate and select top level UCF or NCF constraint files for import You can arrange the order in which to import these files by selecting them and using the Up or Down buttons Files can be removed from the list by using the Remove button If module level constraints are being used do not include them here For more information on importing module level constraints see Importing Module Level Constraints 2 Click Next to continue The UCF files are imported into PlanAhead This may take a few moments The New Floorplan Summary dialog box is now displayed 3 To initiate the floorplan click Finish The new Floorplan is initiated and active in the PlanAhead environment Additional Floorplans can be created using the New Floorplan or Copy Floorplan commands RTL Projects PlanAhead User Guide UG632 v 11 4 RTL Projects do not require a Floorplan to be created in order to create and launch synthesis and implementation runs As implementation runs are launched a target device and single top level UCF can be defined You can experiment with any number of devices constraints and implementation options The one limitation is that only a single UCF file can be assigned to each run and constraints are not modified by PlanAhead If you intend to modify constraints or analyze implementation results a Floorplan is created When you use the Select gt Import Run command to import and
38. It provides an integrated and intuitive environment for the entire FPGA implementation process With PlanAhead you can realize circuit performance improvements by analyzing the design RTL sources synthesized netlists and implementation results You can experiment with different implementation options refine timing constraints and apply physical constraints and floorplanning techniques to help improve design results Early estimates of resource utilization interconnect delay and routing connectivity can assist with appropriate logic design device selection and floorplanning A hierarchical database also enables a block based incremental design methodology that can reduce the run times and compute resources required to place and route the design PlanAhead Features PlanAhead User Guide UG632 v 11 4 e I O pin planning environment Interactive and automatic I O placement Group related I Os into interfaces Robust Design Rule Checks DRCs Simultaneous Switching Noise SSN Analysis Weighted Average Simultaneous Switching Output WASSO Analysis Alternate device compatibility e RTL development and analysis environment RTL source Verilog and VHDL importing RTL elaboration with construct checking www xilinx com 5 Preface About this Guide XILINX RTL Editor with crossprobing Resource estimation RTL Netlist and Hierarchy views RTL Schematic RTL Design Rule Checks DRCs e Synthesis and implementation envir
39. Multiplexers Storage etc Memory and primitive www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Elaborating and Analyzing the RTL Design tables are available and they list all memories and their depth bit width number of ports etc and macros primitives broken down by bit width in the chosen level of the hierarchy The Resource Estimator provides information about hardware resources for an RTL design without running Synthesis and therefore with a much quicker run time The current accuracy is an average of 15 RTL Od 4 x wrapper W Nets 238 RTL Macro Resources GH Gj Primitives 1 ia bignpegd dec mpeg decoder Macro type Slice LUT Flop 18k BRAM DSP48 5 Nets 1405 Bitwise Logic 30 117 GH Primitives 11 Arithmetic 654 2613 G R Buffer_U dp_ram 0 32 11 1520 blo Comparators 112 447 G ig Buffer_ dp_ram 0 32 11 1520 bloq Multiplexers 539 2156 ig Buffer_ dp_ram 0 32 13 6080 blog Storage 759 962 ig cc2me_Fifo FIFO_ TOTAL 2058 6295 R copy_controller copy_controller 13 6 ia idct2tu_fifo ObjFifo 9 64 6 distribut RTL Hierarchy Resources it interFace 0 Fifo_in synch_fifofO 8 1 R me2tu_fifo ObjFifo 8 64 6 distribute Child Slice LUT
40. Netlist Module Pblock and Clock Region Statistics Reports e SSN Analysis Report e WASSO Analysis Reports I O Pin Assignment CSV This comma separated value CSV format file contains all of the I O port assignment and relative package pin information This file is intended to be used for RTL port header definition and PCB schematic symbol generation Refer to Chapter 5 I O Pin Planning for more information I O Pin Assignment RTL Verilog or VHDL This Verilog or VHDL format file contains all of the I O port assignments defined as ports in the file header in a legal language format This file is intended to be used for RTL port header definition Refer to Chapter 5 I O Pin Planning for more information Log File planAhead log The log file planAhead log captures the contents of the messages created from running PlanAhead commands The file is created in the PlanAhead invocation directory for www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Input and Output Files Linux andin C Documents and Settings lt user gt Application Data HDI for Windows It can be displayed in PlanAhead by selecting Window gt View Log File Journal File planAhead jou The journal file p lanAhead jou captures all of the TCL commands from PlanAhead session that was invoked The file is created in the PlanAhead invocation directory for Linux andin C Documents and Settings lt
41. UCF modifications performed in PlanAhead are being performed on the active Floorplan only Note Importing a new UCF file will not automatically update previous UCF settings To avoid duplicate entries the constraints being updated should first be removed from the Project before importing the new files The Constraints view will display any duplicates allowing for removal later Removing Timing Constraints To remove the timing constraints first configure the Constraints view to list all timing constraints defined Select the desired constraints to remove and use the Delete command to remove them 70 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 Working with Floorplans 1 Select the Group by type toolbar icon in the Constraints view to expand the list of Constraints Select some or all constraints using Ctrl click or Ctrl A Select the Delete popup menu command Click OK to confirm removal OFFSET IN 8 5 ns BEFORE TIMEGRP nRESET O IN 16 OFFSET IN 8 5 ns BEFORE GCLK_F TIMEGRP ASIC_ST_RD_I0 OFFSET IN 9 5 ns BEFORE GCLK_F TIMEGRP receiveADCValid OFFSET IN 11 5 ns BEFORE GCLK_F TIMEGRP MAX_RX OFFSET IN 6 5 ns BEFORE GCLK_F TIMEGRP nRESET_0 OFFSET IN 16 ns BEFORE GCLK_F NET GCLK_F TNM_NET GCLK_F NET CK_MIC_O TNM_NET CK_MIC_O NET ASIC_ST_DAT_REQ_T_I TNM ASIC_ST_DAT_REQ_T_
42. and any other I O attributes b Run DRCs in PlanAhead to check I O standards against I O Banking restrictions Some I O standards can be combined within a single Bank some cannot Refer to the device specific packaging and pinout specifications for rules 7 Define clock pins and clock topology a Use the external clock pins on the FPGA for best clock performance b Understand the I O versus the fabric clocking resources and any device specific restrictions on regional clocks Generally pinout restrictions are few for simpler clock structures and lower clock counts fewer than the number of global and I O clocks on the device For more complex clock structures for example high clock counts that require either automatic or manual floorplanning to use regional clocks you must enter the clock tree and enough loads to be able to run the early design through ISE for validation For more information regarding clock pins and clock topology refer to the device specific Clocking user guides 8 Run the design through ISE to validate final pinouts The more of the design I O IP and clocking structures that are available the more accurate DRCs are for the design You do not need to have all the logic in place just the primary structures as described in the previous steps that affect pinout 9 Analyze pinouts for Simultaneous Switching Noise SSN or Weighted Average Simultaneous Switching Output WASSO based on device family
43. similar element in the selected family However modifying the source code to infer or instantiate native elements will take advantage of any added or expanded functionalities in the element This may in turn improve area utilization performance etc Severity Warning Missing pipeline register RPPR Found multiplier with unregistered outputs You can improve the multiplier clock to out performance by adding a level of registers In addition for best results avoid using asynchronous control signals on these registers Found RAM ROM with unregistered outputs You can improve the RAM ROM clock to out performance by adding a level of registers In addition for best results avoid using asynchronous control signals on these registers Warning In efficient pipeline register RPIP Found lt register_name gt lt file_name gt lt line_number gt register with asynchronous control signals on input or output of multiply function Dedicated DSP hardware resources do not have asynchronous control signals such as preset or clear The registers will not be mapped into the dedicated hardware resources resulting in suboptimal use of the device Warning Found Black Box instance not belonging to UNISIM library RPBX Component Module lt component module_name gt description unavailable during synthesis lt file_name line gt Paths to and from this back box cannot be optimized Synthesis tool
44. 4 XILINX Working with Placement LOC Constraints Clear Placement Constraints Instance Types to Unplace Below is a list of types of the 14719 instances you have specified to unplace Only instances of the selected types below will be unplaced Primitive Types to Unplace Block Multiplier 16 C Global Clock 4 Function Generator 10844 Flip Flop and Latch 3436 ar 10 243 Figure 10 45 Clear Placement Constraints Wizard Filter Logic Types to Remove The Instance Types to Unplace page provides a mechanism to filter the types of placement constraints to filter The I O related boxes are unchecked because we elected to clear instance constraints in the first page of the wizard only 6 Inthe Instance Types to Unplace page select the Primitive Types checkbox 7 Click Next Clear Placement Constraints Fixed Placement Some of the instances you are about to unplace are marked as Fixed Do you want to unplace these fixed instances Fixed Instances Keep 161 fixed instances Unplace all 14472 placed instances Figure 10 46 Clear Placement Constraints Wizard Filter Fixed Constraints PlanAhead User Guide www xilinx com 321 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX 8 Inthe Fixed Placement page specify whether or not to unplace the fixed instance s Fixed instances are those you placed or fixed in your design or those you im
45. 95 PinAhead Environment View Layout 0 000 e eee eee 96 Project Environment View Layout 6 cece teens 97 Floorplan Environment View Layout 0 000 e eee eee eee ee 98 Navigating Views 22 214 d4iistedeeecian desea ceed bedacs eee ds teed Heeed dante 99 UG632 v 11 4 www xilinx com PlanAhead User Guide Toggling Views Displayed 2 2 0 6202 cceae sind snipes side niti erste e Enan ceed 99 Opening VACWS 4 duis hath nii oaa Racine a atten Sage Aa ead ecu a hacia a ake 99 Manipulating Views using the View Banner Commands 000 100 Using the View Auto Hide Capability 0 100 Floating VidWS sid cigdsseeccisee cbse sieeecieencisatsieedsreakared eia 101 Defining Viewing Area Sizes 0 eee eee eee 101 Using the View Specific Toolbar Commands 0 000 101 Using the Workspace VIEWS 24 44 0455 io daiepnsiveyoiwadne perekenerennwkns 102 What are the Workspace Views 0000 obec cece cece ete eens 102 Opening Workspace Views escores etienne eni een eens 103 Viewing the Workspace Full Screen 0 6 103 Floating the Workspace View 6006 6 e cece eee eens 103 Printing the Workspace View 6 60 6 c cece eee eee ees 103 Closing Workspace Views 6c ccc eee eee es 103 Splitting the Workspace 10 6 ee 104 Using Common Environment Views 0 000 e ccc 105 Using the Console View and Tcl Command Line 00
46. Apply toolbar button to apply all changes MUA Any values modified receive an next to the option indicating that the default Strategy value has been changed The Strategy field for the Run in the Design Runs view also receives an indicating that the default Strategy has been changed Once a Strategy is launched as described in the next section the Strategy options can no longer be modified To edit an option you will need to reset the run and then edit the option See Resetting Runs Monitoring Run Status Select the Run and then select the Monitor tab of the Run Properties view to view the status of the run while it is running The view displays the same standard out command status logs that displays when at the command line 200 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Monitoring and Configuring Runs gt GN v synth_2 ttt Ruming xst with args ifn synth_2 xst ofn synth 2 srp eading desim synth_2 prj ARNING Xst 29 Optimization Effort not specified Compiling verilog file iic v in library work Compiling verilog file mydiv v in library work Figure 7 21 Monitoring Run Status The Monitor view will continue to update as the commands are being run The scroll bar can be used to browse through the command log reports Select the Automatically update the contents of this view button to stop the active reporting This may enable you
47. Command log file 24 Design logical netlist and Pblock statistics report files 25 DRC results files 25 Error report file 25 TimeAhead results and con straints files 25 WASSO analysis reports 26 CVS files 24 Environment defaults 26 Initialization file 26 ISE implementation strategy files 27 Shortcuts definitions 27 View layout defaults 26 ISE implementation data 28 ChipScope core netlists 30 Constraint files 31 EDIF netlists 29 ISE run scripts 31 Run directories 29 Project data 27 Floorplan data directories 28 Project data directory 28 Project directory 27 Project file 28 Project netlist 28 RTL files 24 PlanAhead product description 5 Printing 103 Device view 226 Package view 132 Schematic view 232 Prohibit Pins See PinAhead Project 38 Adding sources 168 Closing a Project 61 Copying sources into directory 169 Creating new source 170 Floorplan 65 Closing a floorplan 75 Copying a floorplan 77 Creating a floorplan 65 Deleting a floorplan 76 Renaming a floorplan 77 Saving a floorplan 76 Viewing and editing floorplan properties 73 Importing constraints 68 Importing module level con straints 69 Importing top level constraints 68 Netlist update 61 Updating a module level netlist Updating the top level netlist 61 Opening a Project 59 Opening an existing project 59 Opening multiple projects 60 Using the Getting Started jump page 38 Starting a Project 35 Using the Create Project Wizard
48. Ctrl Shift c M Paste trl Shift v New Pblock 2 Schematic F4 WW Connectvit Sula Figure 2 51 Selecting Floorplan Properties The Floorplan Properties dialog box will display floorplan_2 xcSvix30fF324 1 General Part Compatibility Constraint Files Attributes Selection Figure 2 52 Floorplan Properties 3 Enter the new Floorplan name in the Floorplan Properties dialog box under the General tab 4 Click Apply to rename the Floorplan 78 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 3 Using PlanAhead With Project Navigator This chapter contains the following sections e Integration Overview e TSE and PlanAhead Integration Process e PlanAhead Viewing Environments e Transitioning from PACE Floorplan Editor to PlanAhead e Transitioning from Floorplanner to PlanAhead Integration Overview PlanAhead User Guide UG632 v 11 4 The PlanAhead software is integrated with the ISE software in order to perform specific design tasks When the PlanAhead software is invoked from the ISE Project Navigator environment PlanAhead is in ISE Integration mode In this mode the available PlanAhead features apply only to specific design tasks including I O pin planning floorplanning and timing analysis A PlanAhead project is automatically created and managed by the Project Navigator e
49. DSP48 Rules e RAMB16 Rule e Netlist Rules XILINX Note For Global Clock Rules IOB Rules and Bank IO Standard Rules see I O Port and Clock Logic DRC Rule Descriptions Floorplan Pblock Rules Table 8 3 Floorplan Pblock Rules Rule Name Rule Abbrev Rule Intent Severity Longest Carry LCCH Checks that the Pblock height will Amber Chain Height accommodate longest Carry Chain Warning assigned to Pblock Pblock overlap FLBO Checks for overlapping Pblock Information rectangles Pblock Partition FLBP Checks that the LUT to MUXCY and Error MUXEx connection is not broken by a Pblock partition Resource UTLZ Checks that the Pblocks have enough Warning for Utilization resources for logic assigned to them SLICE logic Error for non SLICE logic Area Group Tile FLBA Checks that the site ranges in Warning Argument AREA_GROUP constraints are aligned with the CLB grid Bank Rules Table 8 4 DCI Cascade Rules Rule Name Rule Abbrev Rule Intent Severity DCI Cascade DCIC Checks that DCI cascade constraint is Error Checks legal Table 8 5 Delay Control Rules Rule Name Rule Abbrev Rule Intent Severity IDelayCtrl IDLYCTRL Checks that IDelay placement is Error Checks consistent with IDlyController locs For Bank IO Standard Rules see Bank I O Standard Rules www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Gu
50. Effort PAR High Effort Normal Extra Effort PAR Standard Effort Figure 7 10 Choose an Implementation Strategy Launch Options Select additional launch options Specify Launch Options Launch Directory wrk hdstaff brianj DESIGNS Therm project_1 pr LJe Options O Do not launch now O Launch Runs on Local Host Number of Jobs 1 E Launch Runs on Remote Hosts Configure Hosts O Generate scripts only ok cancer Figure 7 11 Implementation Run Launch Options The Specify Launch Options dialog provides the following launch options Launch Directory Specify a location to create and store the implementation run data 192 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 Running Implementation Note Defining any non default location outside of the project directory structure makes the project non portable as absolute paths are written into the project files Launch Runs on Local Host Select this option to launch the Run on the local machine processor Number of Jobs Define the number of local processors to use for Runs This option is only used when launching multiple runs simultaneously Individual runs will be launched on each processor No multi threaded processors are used with this option Launch Runs on Remote Hosts Linux only Select this option to use remote hosts to launch job or job
51. Fie Edit View Tools Window Select Layout Help teeta agimax gp 60 gt Kiougxexcaneagr kt so rersp Sources Name H bft vhdl E B Verilog 4 FFtTop v QaseB sE f Group by Type v EH VHOL 2 E bft_package vhdl work C DatalPlandhead_Designs NewDe blk_mem_512 32 work C Data Plan4head_Designs NewDer fifo_32x128 v work C DatalPlandhead_Designs NewDe Frame_gen v C Data Plandhead_Designs NewDer Gol xX Geer Gees 7 7 work C Data Plandhead_Designs NewDer work C Data Plan4head_Designs NewDer Properties eo mhk p 3 Properties Selection Command gt hdi Command gt hdi iproject close name project_2 project new name project_l dir C Data PlanAhead Projects project_1 rtl yes Command gt hdi Command gt hdi project setPart name project_l part xcSvlx30ff 324 1 desim addSources project project_l sources C Data Plandhead Designs NewDemo src bft vhdl C Data Plandhead Desiqns NewDemo src bft_package vhdl Figure 2 14 PlanAhead RTL Environment Note If any warning messages appear in the PlanAhead Console view it is highly recommended that you examine either these messages or the PlanAhead log file to identify the design errors or specific issues that may cause problems during implementation Creating a Project with Synthesized EDIF or NGC Format Netlists Synthesized netlists along with corresponding constraints can be import
52. Flop 18k BRAM DSP48 R motion_comp motion_comp 720 576 Buffer_U 0 H Nets 301 Buffer _v a H Primitives 13 Buffer _Y 16 0 6B R mc_core MotionCompensationDe cc2mc_fifo 0 0 Nets 216 copy_controller 0 0 E Primitives 7 idct2tu_Fifo 0 0 m MC_Compensate_pe Comper interface 0 fifo_in 1 0 R MC_Control Control 6 11 11 mce2tu_fifo 0 0 i MC_Interpolation_engine Int motion_comp 0 3 w E MC_TranslateAddress transla parser _vld 3 0 R parser_vid parser_vid 1 1 0 720 texture_idct 6 0 R texture_idct texture_idct 13 texture_update 0 T texture_update texture_update vid2cc_fifo 0 amp R vid2cc_fifo FIFO_1W 12 vid2idct_Fifo 1 R vid2idct_Fifo synch_object_fifof0 20 vid2mc_Fifo 0 E vid2me_Fifo synch_fifo O 16 A vid2tu_fifo 0 R vid2tu_fifo synch_fifo 0 18 5 32 1 1 Primitives 0 General Statistics Pins Children Attributes Connectivity Selection lt ji gt Figure 6 16 Viewing RTL Resource Estimates Click the Save icon to save the Statistics report to XML format for parsing or XLS format Analyzing the RTL Schematic The RTL view works similarly as the Netlist view Any level of logic hierarchy can be selected and viewed in the RTL Schematic view To invoke the RTL Schematic view for any selected logic select one of the following commands e Click the Schematic toolbar button e Select Tools gt Schematic PlanAhead User Guide www x
53. IC FSM a s addr icfsm_biu_read saved_addr between input data generated by LSU 262 263 assign to_icram icbiu_dat_i 264 il Getting Started W blk_mem_512X32 v FFtTop v usbf_to Figure 6 14 RTL View The RTL netlist can be expanded and collapsed using the tree widget controls and view specific toolbar icons PlanAhead User Guide www xilinx com 175 UG632 v 11 4 Chapter 6 Creating and Analyzing the RTL Design Using the RTL View Specific Popup Menu Commands XILINX Common commands are described in the Using Common Popup Menu Commands page 251 The RTL view commands and a brief description of each are as follows e Schematic Invokes the RTL Schematic view e Show Hierarchy Invokes the RTL Hierarchy view e Show in Source Invokes the HDL Editor and highlights the selected logic Using the RTL Hierarchy View The RTL netlist hierarchy can be examined using the RTL Hierarchy view Select the Show Hierarchy popup menu command to invoke the RTL Hierarchy view The design logic hierarchy is displayed in the RTL Hierarchy view with relative sized modules The selected module s are cross highlighted in the RTL Hierarchy view z E 176 E top t amp B B Nets 117 Primitives 1 Bt cpuEngine for1200_top W Nets 179 4 Primitives 2 EJ cpu_dbg_dat_i FifoBuffer EJ cpu_dbg_dat_o FifoBuffer EJ cpu_dwb_dat_i FifoBuffer EJ
54. ISE implementation All of the Pblock Statistics should be taken into account when sizing Pblocks Occasionally Pblocks will need to be enlarged in order for ISE to place them successfully Placing Pblocks Based on Connectivity PlanAhead User Guide UG632 v 11 4 PlanAhead provides dynamic connectivity feedback to help guide placement of Pblocks www xilinx com 309 Chapter 10 Floorplanning the Design g XILINX KKRKIBL ALLO Figure 10 30 Displaying Connectivity Helps To Determine Floorplan The combined connectivity between Pblocks is displayed as bundled nets Each bundle is sized and colored based on the number of connections between Pblocks The intent is to make the heavily connected Pblocks easy to identify A reasonable strategy might be to define the Pblocks with the largest net bundles close together Typically the Pblocks should be placed in such a way as to achieve the shortest net lengths and to avoid routing conflicts or congestion Displaying Bundle Net Properties Connectivity information can be viewed by displaying properties for net bundles or for individual nets To view connectivity information 1 Select the desired net or bundle net 2 View the Net Properties or Bundle Net Properties view The Nets tab in the Bundle Net Properties dialog box displays the nets contained in the bundle 310 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Automatic Pbloc
55. Input Input Input Input Input Input Output Output Figure 5 2 Neg Diff Pair Location Bank CORE_CLK_N I O Std HSTL_I HSTL_I HSTL_I HSTL_I HSTL_I HSTL_I LYCMOS25 LYTTL LYTTL LYCMOS25 LYDS_25 LYTTL LYDS_25 LYTTL LYDS_25 LYTTL LYDS_25 LYTTL PCI33_3 PCI33_3 PCI33_3 PCI33_3 PCI33_3 PCI33_3 LYDS_25 LYCMOS25 LYTTL HSTL_I LYCMOS25 Drive Strength Slew Type 12 SLOW 12 SLOW 12 SLOW 12 SLOW 12 SLOW 12 SLOW 12 SLOW 12 SLOW 12 SLOW 12 SLOW 12 SLOW I O Ports View Displaying I O Port Interfaces Pull Type Phase default default default default default default default default default default default default default default default default default default default default default default default default default default default default default The view displays the ports according to category by Interface or displays the ports alphabetically by clicking the Group by Interface or Bus toolbar button in the I O Ports view Figure 5 3 Group by Interface or Bus Toolbar Button Port signal names direction package pin bank I O Standard Drive strength Diff pair partner Slew type and other signal information are listed for each I O port Table values PlanAhead User Guide UG632 v 11 4 www xilinx com 129 Chapter 5 VO Pin Plan Using the ning g XILINX appear bla
56. Instances tab of the Pblock Properties view displays information about the instances contained in the Pblock Pblock Properties Og gg x Gw a pblock_1 Id Name Cell Pins lt a r 2jusbEngine0 usbEngineSRAM bik _mem_5 3JusbEngineO usb_dma_wb_in Ea 4 usbEngine1 usbEngineSR 4M 2 _mem_512x32 Ea 5fepuEngine cpu_ jwb _dat_o CY chistengneijusb n Pfobuffer 71 i 7 fsbEngnel feb dma _whb_in Fifobuffer 71 EY alistencineojame_out fobuffer 71 GEE Enone ljama o E EH 11fusbEngine0 usb_out General Statistics Instances Rectangles Attributes 3 Properties Selection Figure 10 22 Pblock Properties View Instances Tab www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Pblocks The instance fields are selectable and may be used to seed many popup menu commands The Rectangles tab The Rectangles tab of the Pblock Properties view displays information about the various rectangles created for the Pblock The Rectangle tab is used for selecting rectangles of a Pblock For more information about this tab refer to the Modifying Non Rectangular Pblocks The Attributes tab The Attributes tab of the Pblock Properties view is described in the next section Setting Pblock Logic Types Ranges You can set Pblock AREA_GROUP Range types in the Pblock Properties view by modifying the Grid Range options in the General tab Adjusting these toggles will c
57. O pads and clock objects are displayed around the periphery and or down the the row of I O pads Available I O bank sites are indicated with colored filled I O bank aon HOG DAR HA CO DD OO CC DO N Hag AARAA DAR HOO San HAG HAG CD CODD CO CDC CO OC CF Cr BHO Aaa HO AAG Bag Hag aA CECT al eel eel to CS elt lel Cl Cl Cet Cel ef PORRI SRE SR a aa o a S F ERR Eno0R7 oRR0 Re AA ae wml mh ae ae agli ae me i ER AA 99 OF 99 tG 99 0G OF Of 99 G9 99 0G FF og DAA ooo oan noo ooo aaa A rl A fr rl rt rll Chr rl Gr Ch rl A Figure 8 2 Device View Up Close Primitive logic instances can be assigned to the appropriate sites displayed ISE placement CLBs SLICEs and BELs are only visible when the zoom level is close enough to display results can be imported to display the logic assignments them 223 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 8 Analyzing the Design co oo a Go O BO E LI l mooojmoodoooojoOoo0m0o0g TE i f fin AaninsAnl insan ni anie 2 selevere UG632 v 11 4 placed instances appear as re
58. Pblock 4 Scroll down to view the required RAM sites for the Pblock The dialog box is dynamic and will update each time the Pblock is modified If the Pblock does not contain a site for a specific logic device element the following values are shown e Available O e Required the number required e Utilization Disabled meaning no sites of the required type are defined in the rectangle A value of Disabled is an error condition indicating that there are no sites of the required type in the rectangle defined 308 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Placing Pblocks Based on Connectivity Physical Resource Estimates Site Type Available Required Util LUT 80 36 FF 80 SLICEL 15 SLICEM RAMBFIFO36 ps General Statistics Instances Rectangles Attributes Selection Figure 10 29 No RAMFIFO36 Resources Available in Pblock Disabled Note The Pblock SLICE utilization calculation assumes maximum site utilization In reality the maximum site utilization is rarely achieved in placement and routing tools Thus a designer should optimize for a target utilization of approximately 80 or higher This number is a function of the device used and the characteristics of the design and its constraints Note Pblock utilization is affected by carry chains RPM macros and the geometry of the Pblock rectangle These statistics are merely estimates to help guide you to a successful
59. Pblock amp pblock_1 C Match Case Figure 8 60 Searching for Objects with Additional Search Criteria 4 Multiple objects can be searched for simultaneously by using the OR criteria as shown below Find Instances Netlist Synthesized w Criteria Type i v Block RAM OR oy Type i Block FIFO OR v Type li v Gigabit 10 C Match Case Figure 8 61 Searching for Multiple Object Types Simultaneously PlanAhead User Guide www xilinx com 271 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX 5 Click the Fewer button to remove search criteria rows 6 Click OK to perform the search The combined search results are displayed in the Find Results view Using the Find Results View The objects matching the Find dialog box criteria are displayed in the Find Results view once you initiate the search by clicking OK A Id Name Cell Pins Del usbEngine1 usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop 0 ram r vS ramjSP WI i 2 usbEngineO usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop 0 ram r v5 ram SP WI RAMB18 112 3 mgtEngine tileO_frame_gen1 dual_port_block_ram_i RAMB16 194 F 4 mgtEnginejtile2_frame_gen0 dual_port_block_ram_i RAMB16 194 AF 5 cpuEngine or1200_dmmu_top or1200_dmmu_tlb dtlb_mr_ram ramb16_s18 RAMB16 194 6 cpuEngine or1200_dc_top or1200_dce_ram dc_ramjramb16_s9_0 RAMB16 194 7 cpuEngine or1
60. Pblocks wizard seeded with selected set of instances to allow creation of multiple Pblocks Auto create Pblocks Invokes the Auto create Pblock dialog box to automatically place the instances into Pblocks and name them accordingly Place Pblocks Invokes the Place Pblocks dialog box to automatically size and place Pblocks Auto place I O Ports Places the entire device or any selected portion of it while obeying I O bank rules differential pair rules and global clock pin rules A PinAhead feature PlanAhead User Guide UG632 v 11 4 www xilinx com 343 Appendix A Menu and Toolbar Commands Table A 4 Tools menu commands Clear Placement Constraints Invokes the Clear Placement Constraints Wizard to selectively remove port or placement location constraints Schematic Opens a new Schematic view in the Workspace and displays a schematic of the currently selected elements Show Connectivity Selects the elements connected to the selected instances nets or Pblocks This command can be used sequentially to continue to fanout and select a cone of logic Show Hierarchy Invokes a Hierarchy view in the Workspace and graphically displays the entire logic hierarchy Selected logic is highlighted in the tree Run TimeAhead Invokes the Run TimeAhead dialog box and enables you to configure and launch the TimeAhead static timing analyzer Run Elaboration Invokes the RTL parsing a
61. Pin Planning command When PlanAhead is invoked Project Navigator passes the synthesized NGC or EDIF format netlist and the UCF file s to PlanAhead PlanAhead is invoked with the default I O pin planning PinAhead view layout displaying The I O ports are displayed in the PlanAhead I O Ports view When the PlanAhead project is saved or closed the original Project Navigator source UCF file s are updated This will also reset the Project Navigator design process state if appropriate Refer to Passing Logic and Constraints for more information about the integration mechanics and process www xilinx com 81 82 Chapter 3 Using PlanAhead With Project Navigator g XILINX Refer to Chapter 5 I O Pin Planning for more information about using the PlanAhead I O pin planning environment PinAhead Floorplan Area IO Logic Post Synthesis PlanAhead has a robust design analysis and floorplanning environment that can be used prior to or after implementation To analyze the design or to perform floorplanning from Project Navigator after running logic synthesis and prior to implementation in the Processes pane expand User Constraints and select Floorplan Area lO Logic PlanAhead Post Synthesis or select the Tools gt PlanAhead gt Post Synthesis Floorplan Area lO Logic command When PlanAhead is invoked Project Navigator passes the synthesized NGC or EDIF format netlist and the UCF file s to PlanAhead PlanAhead i
62. RTL Design g XILINX e Select the links in the Violations Properties view to highlight the design objects in question e Select the Show Source popup menu command to highlight the line of RTL source Click the Hide Warning and Information Messages toolbar button to hide all warnings and info messages and view only errors Click the toolbar button again to view all errors and warnings once again Figure 6 20 Hide Warning and Information Messages Button Definitions of RTL DRC Rules The following tables describe the various DRC rules rule intent and severity 180 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 Elaborating and Analyzing the RTL Design RTL Rules Table 6 1 Power Rules Rule Name Rule Abbrev Rule Intent Severity Constantly RPRC A described RAM either inferred or Warning enabled instantiated which are constantly enabled synchronous was found in one or both ports If it can be RAM determined that this RAM is not constantly accessed Significant power reduction may be seen by describing the logic to disable the RAM unless it is being accessed Inefficient RPRM A RAM in which there is an unconnected Warning dangling output port has been detected and the BRAM port WRITE_MODE is set to a value other than NO_CHANGE Modifying the description of the RAM in order to set unconnected output port WRITE_MODE set to NO_CHANGE may sa
63. Resource Statistics The Export Netlist Statistics dialog box contains the following editable options File Name Enter the name and location of the spreadsheet file to be created Format Select either an XML or Microsoft Excel format output file format Levels Indicate the number of levels of hierarchy to traverse and include in the report as separated modules Reports to Generate Define the types of information from the Pblock Property Statistics view to include in the output report file Select the desired options for the exported file Click OK Exploring the Logical Hierarchy Refer to the Using the Netlist View and Using the Instance Hierarchy View for more information Analyzing the Hierarchical Connectivity PlanAhead provides a wide variety of capabilities to examine the logic hierarchy including the ability to visualize connectivity between the various logic modules Sometimes it is helpful to initially create a Floorplan consisting of the top level netlist instances to help visualize the connectivity flow as shown below 258 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Analyzing the Synthesized Design lt ll Package Device x 7 Figure 8 46 Viewing Top level Design Connectivity The Net bundles clearly indicate the heaviest connectivity requirements between the modules The color and line thickness of the Net bundles can be configured depending on the
64. Run Each Run is associated with a specific strategy You can launch multiple runs either simultaneously with multiple processors or serially Runs will be queued sequentially with the status displayed in PlanAhead Strategy A Strategy is a predefined set of tool command line options You can apply factory delivered Strategies or create your own Strategies can be applied to individual runs www xilinx com 33 34 Chapter 1 Understanding the PlanAhead Design Flow g XILINX Site PlanAhead displays a tile grid representation of the specific FPGA device resources that can be used to implement the design netlist Primitive logic sites are displayed and are available for placement of netlist instances These sites vary in shape and color to differentiate the object types e g RAMs MULTs CLBs DSPs PPCs MGTs etc Leaf level logic can be assigned to specific SLICEs with placement constraints LOCs or to gates within the SLICE with LOC and BEL constraints Site Placement Constraint LOC Location constraints or LOCs can be assigned to the leaf level instances that have fixed placement sites assigned to a specific SLICE coordinate These are different than BEL constraints as they do not lock the logic into specific logic gates within the SLICE Assigning a LOC constraint will result in a LOC constraint being fixed and applied in the exported UCF files for the instance Depending on zoom level these LOCs appear in the De
65. Select Layout Help eee I EE O gt gt XA s E Id Name Device E project_1 home mdarnall dev pa designs multclock mls05 pa project_1 project_l pprj PlanAhead 111 LR0 Floorplans Od g X Netlist Oot x OB aN EJOS WW top Nets 4 Bus Net Properties O a X eo ER amp counter1 Dee aea E General Scalar Nets O gt counter amp counter3 gt led amp CONTROL_csdebugcore_0_ bugcore_O_ clk m S Properties Selection t Schematic Figure 11 11 ChipScope Od x Q Name Drive Q chipscope_icon_vl Drag Drop E chipscope_ila_v1 csdebugce 2 Ow CLK 1 o ei Nets amp Busses Ell SB TRIGO 24 9 DATA _ cho E Console D 1 0 Pons Design Runs ChipScope R Post Synthesis Flow 443 1 Insert Text 29M of 42M i Dragging and Dropping Nets onto Debug Core Ports Customizing Debug Core and Port Parameters ChipScope Debug cores have parameters that can be customized To access these core parameters select one of the ChipScope debug cores in the ChipScope view In the Properties tab select Options to configure the core parameters Figure 11 12 Port parameters are modified by first clicking the Trigger or Data port of a debug core and selecting Options in the Properties tab Figure 11 12 ole PlanAhead User Guide UG632 v 11 4
66. Select this option to import results from a previously implemented Pblocks 3 Click OK to import the placement results The results of importing placement are shown below Net connection and traced paths will now display to the placement constraint location instead of the Pblock center Importing ISE TRCE Timing Results into an Existing Project TimeAhead also has the ability to import the twx and twr format timing reports generated by the Xilinx tree command Once imported all the signal tracing and viewing capabilities described in this chapter are available with the TimeAhead environment PlanAhead User Guide www xilinx com 217 UG632 v 11 4 Chapter 7 Implementing a Design g XILINX To import timing results 1 Select File gt Import TRCE Results The Import TRCE Results dialog box appears G Import TRCE Results Floorplan Fp2_usb_timing 3 75 File name Results Name results_1 Import timing results for Netlist top Instance Pblock Description Names in the timing results file are fully hierarchical Figure 7 42 Import TRCE Results Dialog Box 2 View and edit the definable fields in the Import TRCE Results dialog box File Name Define a trce format twxor twr file name for PlanAhead to import results Results Name Define a name to appear on the results tab in the Timing Results view Impo
67. Selecting Pblocks The Run Implementation command can be seeded with pre selected Pblocks prior to running the command To run the ISE commands on selected Pblocks 1 Select a Pblock in PlanAhead 2 Select one of the following commands Select Tools gt Run Implementation Click the Run Implementation toolbar button oa Figure 7 13 Run Implementation Toolbar Button In the Run Implementation dialog box the Pblock field should display the selected Pblock G Run Implementation Run Name impl_1 Description ISE Defaults including packing registers in IOs off Floorplan 4 original_Fp xc4vlx25FF668 10 Part Constraints Pblock a DDR 1 _pblock Strategy ISE Defaults ISE 11 Launch Options Launch on local host xcobrianj30 _ Figure 7 14 Run Implementation for Pblocks 3 Alternately you can select the desired Pblock to implement after selecting the Run Implementation command If a Pblock is not pre selected click the Pblock field and select one Pblock from the list www xilinx com 195 4 5 Chapter 7 Implementing a Design g XILINX Select the Run options as described in Running Implementation Click OK The Pblock Run will appear in the Design Runs view and can be monitored and managed as other implementation runs are Monitoring and Configuring Runs Using the Design Runs View As Runs are created launched or imported the st
68. Slew Rate The slew rate of the I O standard for a specific user I O Not all I O standards accept a slew rate If this field is blank the tools will use the default Values are FAST and SLOW e Phase Used to specify the phase of an I O relative to the phase of other I O in the bank in cases of a synchronous phase offset You can also attach other information The software will add any other fields with user defined values to the set of user defined columns Also you can add extra columns to the Package Pins table Using User Defined I O Port Properties in the CSV PlanAhead has a specific expected format for importing I O pin related data Often design groups have additional information in their CSV files If additional columns of data exists in the imported CSV file PlanAhead will create new columns in the Package Pins view to display and or modify the field values Select the Set User Column Values popup menu command to modify or define values in the customer CSV fields If you select File gt Export I Os gt CSV the columns and new values are preserved and exported in the output CSV file HDL Format Files PlanAhead User Guide UG632 v 11 4 PlanAhead lets you import an HDL format header as a way to populate the I O Ports view To import I O port definitions from HDL files select File gt Import I O Ports gt From HDL In the wizard you can specify VHDL and or Verilog files for import Enter the top level module name and
69. To Defined Area 144 Placing I O related clock logic 148 Prohibiting I O Pins 140 Running SSN analysis 157 Running WASSO analysis 161 UCF file Importing I O ports 138 Viewing Clock Region resources 134 358 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Viewing I O bank resources 133 Place and route See Implementation Placement constraints Adjusting the visibility of LOC con straints 317 Assigning BEL constraints 316 Assigning LOC or Site constraints 316 Deleting selected LOC BEL con straints 319 Duplicating placement for identical modules 328 Importing ISE placement results 216 Locking placement during ISE im plementation 324 Moving 318 Pblocks with placement con straints assigned 324 Selectively clearing LOC constraints 319 Setting Prohibits 324 Understanding fixed and unfixed constraints 315 Understanding LOC and BEL con straints 315 Viewing primitive logic connectivity 318 PlanAhead configuration Adjusting Bundle net defaults 311 Checking for software updates 351 Configuring tool shortcut keys 118 Setting display options 112 PlanAhead default layout 85 PlanAhead inputs 21 Constraint files 22 23 CSV files 22 HDL files 23 ISE placement results 23 ISE TRCE timing results 24 Module level netlists and cores 23 RTL files 22 Top level netlists 23 Xilinx cores 22 PlanAhead Options 112 PlanAhead outputs 24 Command logs and reports 24 Command journal file 25
70. To clear netlist instances from the list click the Clear button Click Next G Create Pblocks Specify a naming scheme for the 5 new a Prefix pblock_ Suffix Instance name Numeric Sample pblock_cpuEngine_cpu_dwb_dat_i pblock_cpuEngine_cpu_dwb_dat_o Figure 10 5 Create Pblock Wizard Specify Name 7 Inthe Create Pblocks wizard view and edit the naming scheme fields Prefix Defines a name prefix to be used for the Pblock names Enter a new prefix or allow the default instance name or number to be used Suffix Select Instance name to append the instance name onto the prefix or select Numeric to append a number starting with 1 to the prefix Click Next Verify the contents in the Summary page 10 Click Finish to create the Pblocks with these settings PlanAhead User Guide www xilinx com 291 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX The Pblocks should now be shown in the Physical Hierarchy view 5 floorplan_1 eB ROOT E pblock_cpuEngine_cpu_dbg_dat_i pblock_cpuEngine_cpu_dbg_dat_o E pblock_cpuEngine_cpu_dwb_dat_i pblock_cpuEngine_cpu_dwb_dat_o pblock_cpuEngine_cpu_iwb_adr_o amp Sources ai Metrics Figure 10 6 Pblocks in Physical Hierarchy To create rectangles for the newly created Pblocks 1 Select each of the new Pblocks one at a time in the Physical Hierarchy view 2 Click the Set Pblock Size De
71. Windows or Linux On Windows you can double click on the PlanAhead desktop icon To start using PlanAhead 1 Select Create a New Project from the launch screen 2 Follow the New Project wizard 3 Proceed to floorplanning tasks For a full description on how to invoke PlanAhead in a standalone mode see Chapter 2 Creating and Managing Projects For the most common floorplanning tasks the typical set of input files are the synthesized NGC or EDIF netlist and UCF file for saving constraints If design timing analysis tasks are the goal then a placed NCD file and timing report TWX or TWR file are also required For information on importing ISE results see Creating a Project with ISE Placement and Timing Results General Floorplanning Tasks PlanAhead User Guide UG632 v 11 4 e Drag drop objects to the Device view From the design hierarchy view any individual primitive logic object LUT FF BRAM etc can be placed by dragging it to the graphical Device view Select the Create Site Constraint Mode toolbar icon in the Device view prior to dragging primitive logic onto Device sites This results in a LOC constraint in the UCF which directs the placer to place that object at the specified site Any object type can be floorplanned in this manner Note PlanAhead refers to user constrained LOCs as fixed e Pin placement and area based floorplanning functionality is integral to PlanAhead so full DRC checking is e
72. a E Console P Package Pins i a Figure 3 1 O a9 x SPU Ce x f SARRERA gt H f 0 5 project_new proje t new ppr PlanAhead 11 1 1 RO SS RSORD RS oh bork NO ad Drive Strength Sow Typo Pl Type 17 WWwOMOSIS 2 Row 15 eveMoses 2 zow 17 WWOMOSSS 2 20W 15 LweMosa5 2 Row 17 WCMOS2S 2 20w 15 WwoMos2s 2 20w Bsh Type 17 User 10 17 User 10 17 User 10 17 User 10 17 User 10 17 User 10 17 User 10 17 User 10 Max Trace Dy 106 Alas 99 6 108 OTS 6 10 108_xOY7 75 12 106 TS 93 08 106 ITS 97 99 108 pars 99 40 OO INTI 68 79 100 X72 92 11 108 X071 PinAhead View Layout in ISE Integration Mode The areas of the viewing environment are the following OF Be Gen o Object Properties Selected Objects Netlist Constraints Clock Regions I O Ports list Ste Type 1010417 OL 37 HOLT HII HINI LP 17 DINI 1014717 Package Pins Console View Results Views Timing Find Design Rules Check Split Workspace Device View Package View Schematic View Instance Hierarchy View Reports The PinAhead environment presents information about the specific device package and the design specific I O information Opening the PinAhead environment consists of nothing more than loading an alternate view layout Use the Layout gt Load Layout gt PlanAhead Default command to return back to the default PlanAhead environment For more information about using the PlanAhead Viewing Environment see Chapter 4
73. and Managing Projects g XILINX Entering a Project Name and Storage Location for the Project Enter a project name and storage location as follows 3 In the Project Name page specify a Project name and disk storage location Project name Enter a name to identify the project directory e g project_2 Project data files location Enter a location to create the project directory 4 After the above selections are defined click Next Selecting the Design Source Data Type Designate the Design Source input format by selecting either to import RTL sources or a synthesized EDIF or NGC netlist for PlanAhead or to start with an empty Project for I O pin planning New Project Design Source Specify the type of sources for your design You can start with RTL or a synthesized EDIF Import RTL Sources You will be able to run RTL analysis synthesis and implementation Import synthesized EDIF or NGC netlist You will be able to run post synthesis design analysis planning and implementation Import ISE Place amp Route results You will be able to do post implementation analysis of your design Do not import sources at this time You will be able to do pin planning now and import a netlist later Figure 2 7 New Project Wizard Design Source Chooser 5 After the above selection is defined click Next 6 Depending on the desired design input continue with the instructions in one of the following sections
74. automatically imported from the PlanAhead installation directory and then from the HDI directory if it exists You can save custom Theme files for use in future PlanAhead sessions by clicking the Save As button in the Themes dialog box accessed using Tools gt Options gt Themes A pull down selection menu allows you to select the desired Theme file to use during the active PlanAhead session For more information see Creating and Using a Customized Theme When you select the PlanAhead Light Dark Theme buttons of the View Options dialog box the C Documents and Settings Owner Application Data HDI lt version_number gt planAhead ini file on Windows and the HDI planAhead ini file on Linux is overridden with these preset defaults To avoid loss of any custom settings keep a backup of the custom settings file Window Layout Files lt ayoutname gt layout Window layout files are created using the Save Layout As or Save as Default Layout commands and will save the current PlanAhead Desktop view configuration to be recalled at a later time The configurations for both the Floorplan and Project viewing environments are stored in the following subdirectories On Windows this is often in C Documents and Settings lt Username gt Application www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Input and Output Files Data HDI lt version_number gt layouts floorplan_
75. been taken to integrate the two processes as much as possible and to ensure data is passed effectively between the two tools Changes to design data in one tool are not automatically recognized in the other in real time Users should not attempt to edit logic or constraints simultaneously in both tools Invoke PlanAhead for the intended purpose and close it before updating the Project Navigator design data The Project Navigator process steps are synchronized to recognize edits to the UCF file made in PlanAhead once the data is saved The following sections describe the steps involved and the data transactions that enable the integration Passing Logic and Constraints PlanAhead in ISE Integration mode enables only physical constraint modification for I O pins logic LOC and AREA_GROUP constraints In all cases below logic connectivity in the form of RTL sources or synthesized netlists are passed to PlanAhead for analysis purposes only They are not passed back to Project Navigator All of the PlanAhead features that enable logic or timing constraint modification have been disabled in ISE Integration mode All logic modification must be performed in Project Navigator or in an external RTL or synthesis tools The only files being passed back to Project Navigator are the UCF constraint files PlanAhead attempts to maintain the original content and format of the UCF files This includes comments incomplete constraints etc The legality of constraints in
76. button and shortcut key if available are displayed for each command Table A 9 Toolbar commands Toolbar Command Name Tike Description New Project Opens the New Project wizard Gi 3 Open Project Opens the Open Project dialog box New Floorplan Opens the New Floorplan wizard E 4 Save Project Ctrl S Saves the Project with the current Project name Run Tcl Script Invokes the Run Script dialog box to select and execute a Tel script Undo Ctrl Z Undoes previous run command from active PlanAhead session is Redo Shift Redoes previously undone command from active PlanAhead a Ctrl Z session x Delete Delete Deletes the current selection PlanAhead User Guide www xilinx com 347 UG632 v 11 4 Appendix A Menu and Toolbar Commands Table A 9 Toolbar commands XILINX a Find Ctrl F Invokes the Find dialog box to search for specific design elements Run TimeAhead Invokes the TimeAhead dialog box to run static timing analysis Run DRC Invokes the DRC dialog box to run the design rule checker Run Synthesis F11 Invokes the Run Synthesis dialog box to create and launch a gt Synthesis Run Run Implementation Invokes the Run Implementation dialog box to run a implementation strategy using one or more hosts Linux only Options Invokes the PlanAhead Options dialog box X Schematic F4 Invokes a new Schematic view i
77. can be read in using the Import I O Ports function of the File menu e Create I O Ports To start pin planning without any pre existing input files you can also interactively create new pin definitions using the Create I O ports popup menu command in the IO Port view e Export Top level HDL Once pin assignments have been completed like PACE and Floorplan Editor you can also export a top level Verilog or VHDL file with the pin names populated within the HDL port list This is a convenience feature to help you start the HDL coding process e Export CSV PlanAhead also provides the ability to export a CSV format file of the pin list and information as this can be used by external applications e g board layout tools e Export UCF PlanAhead also provides the ability to export a UCF format constraint file of the pin definitions General Notes on Empty Design and Pre Synthesis pin planning e DRC Checking The DRC can be invoked by selecting Tool gt Run DRC In the Empty Design or Pre Synthesis pin planning modes there are only limited design rule checks that can be performed on the legality of the pin assignments These typically include things like IO standard banking rules but don t include the more sophisticated DRC such as checking of clocking rules The more robust DRC set is only enabled when a post synthesis netlist is available to PlanAhead e Saving Constraints to UCF Once pin assignments are complete you can save th
78. command in the popup menu For example the Fit Selection command can be accessed by pressing F9 Default values for shortcuts can be modified by using the Shortcuts option of the PlanAhead Options dialog box G PlanAhead Options Plandhead Default Filter Z Name Shortcut Pe Description PE pe gje All Actions Selection Rules a Main Menu Code Editor Device View 4 Package View Main Menu Shortcuts Code Editor Shortcuts Device view Shortcuts Package View Shortcuts i Explore Ahead Schematic Sources a3 Netlist Strategie S Properties E 170 Ports W Schematic Metrics General aes eae Find View A amp Chipscope l Configurations Text Editor Other d lt a Other Shortcuts Shortcuts for selected command i Cancel Figure 4 27 Shortcuts Options The Shortcuts dialog box provides a helpful interface to create new Shortcut schemas which contain custom shortcut settings At the top the Available shortcut schemas enables you to manage Shortcut schemas Click the Copy button to copy the PlanAhead Default schema to create a new schema You can activate any schema in the list by selecting it from the pull down menu of available PlanAhead User Guide UG632 v 11 4 118 www xilinx com g XILINX Configuring the Viewing Environment schemas The PlanAhead Default schema must first be copied in order to make any modifications Modifi
79. cpu_dwb_dat_o FifoBuffer EJ cpu_iwb_adr_o FifoBuffer EJ cpu_iwb_dat_i FifoBuffer EJ cpu_iwb_dat_o FifoBuffer dwb_biu or1200_wb_biu iwb_biu or1200_iwb_biu lor1200_cpu or1200_cpu or1200_de_top or1200_dc_top or1200_dmmu_top or1200_dmmu_top or1200_du or1200_du or1200_ic_top or1200_ic_top Nets 50 E Primitives 25 E or 1200_ic_fsm or1200_ic_Fsm E or 1200_ic_ram or1200_ic_ram E or1200_ic_tag or1200_ic_tag or1200_immu_top or1200_immu_top or1200_pic or1200_pic or1200_pm or1200_pm F F a F E Liz T Ea E5 Ez F F aj BERR RIG 4 WU L L L LCL od oT CI C1 OM SOD SCOT YT IO CCT j ams Getting Started i RTL Hierarchy lt _ Figure 6 15 RTL Hierarchy View f aa a II The RTL Hierarchy view works similarly to the Instance Hierarchy view For more information on exploring the RTL Hierarchy refer to Using the Instance Hierarchy View page 236 Viewing the Resource Estimates for Modules The RTL Netlist view works similarly to the Netlist view Any level of logic hierarchy can be selected and its hardware resources analyzed The Statistics tab in the Instance Properties view can be selected to view the estimated device resource requirements for the selected module or for the top level module in the RTL view Logic resources are categorized as Arithmetic Comparators
80. da end eed ine ian eae ae 65 Creating a Floorplan sissies sings otis Seat orbs iei ean Rad eo e ee aks 65 Importing Constraints ss e e eeit ete nett e nee 68 Importing Module Level Constraints 0 0 6 6 cece eee 69 Updating Design Constraints for Floorplans 0 0000 e eee eee eee 70 Creating Multiple Floorplans 2 0 6 6 c cece nee ee 72 Managing Multiple Floorplans 00 0 0 e eee 72 Viewing or Editing Floorplan Properties 6 6 6 73 Closing a Floorplan incies iets eae boy eee eda ae gees 75 Deleting a Floorplan pee cccd dee dis he rini Megat oth e e iein e Riad ole he erred asi bs 76 Saving a Floorplan 42 9 0 oe cerei neei ea ae bee eed ela 76 Copying a PlOOrp lan spera eae e eee a eho EE eE EEE ea RoE u keta A E eea e REE 77 Renaming a Floorplati 4 oi d iawbe whade cres piar epia She PR a 77 Chapter 3 Using PlanAhead With Project Navigator Integration Overview ci ivcwsesewsdiewi i sare ke weed Vien eee ena Been wen ees 79 ISE and PlanAhead Integration Process 0 000 c eee eee eee 80 Passing Logic and Constraints s s sessar rnrn e eee eee eee 80 I O Pin Planning Pre Synthesis 0 66 6 81 I O Pin Planning Post Synthesis 0 0 81 Floorplan Area IO Logic Post Synthesis 0 000 e eee eee eee eee 82 Analyze Timing Floorplan Design Post Implementation 0 82 PlanAhead Viewing Environments 0 0 00050
81. desired Drive Strength value Slew Type Select the desired Slew Type value Pull Type Select the desired Pull Type value Phase Enter a phase group or select an existing phase group A phase group is a logical grouping of ports that is used in SSN calculations to indicate that the set of ports share the same frequency and phase For more information on using this option see Defining the I O Port Switching Phase Groups Refer to Xilinx device documentation for information regarding voltage capabilities of the device PlanAhead User Guide UG632 v 11 4 www xilinx com 139 Chapter 5 VO Pin Planning g XILINX Setting I O Port Direction Select the I O ports busses or interfaces to be configured and select the Set Direction popup menu command in the I O Ports view Defining Differential Pairs To define a differential pin pair select any two I O ports and select the Make Diff Pair popup menu command in the I O Ports view GB Make 1 0 Diff Pair Create a Differential I O Pair From the Following two ports Positive End D gt QDRO_DIN O Negative End O ODRO_DIN 1 aA Swap i Cancel Figure 5 17 Make I O Diff Pair The two I O Ports display in the dialog box with initial Positive End and Negative End definitions Click the Swap button to alternate the Positive End and Negative End definitions Select the Split Diff Pair popup menu command to remove the differential pair definition o
82. e There is also a Project creation method which allows results to be imported from a previous command line implementation attempt Depending on the Project type created the Project can contain one or more versions of the netlist Each with any number of Floorplans along with the implementation attempts or Runs Refer to Managing Projects for more information The Project information is stored in directory structure containing a combination of a project file such as project_1 ppr a Project data directory such as project_1 data a Project sources directory such as project_1 srcs and a Project runs directory such as project_1 runs The sources directory contains all RTL related source files imported into the Project The data directory contains the netlist directories containing the Project netlists and directories for each Floorplan in the Project The runs directory contains all ISE implementation attempts created by PlanAhead The Project data is maintained automatically by PlanAhead The tool expects to find project data in the state it left it Therefore you should not attempt to modify these files manually PlanAhead will automatically restore the state of the Project upon opening it The Project status including all opened or closed Floorplans and each associated Run are updated and available to you when a Project is re opened Source Projects can be created with a variety of input file formats Projects can be created by
83. eee eee eens 211 Executing Runs on Multiple Linux Hosts 00 000020008 211 Limita hons serat oe nee rN oP a Re a ne a E 211 Configuring Remote Hosts Linux Only 00 000 e eee eee eee eee 212 Interfacing with ISE Outside of PlanAhead 00088 214 Exporting Constraints 6 cee ncpeeee Wein siepe i dha lends Eea sande owed 214 Exporting Netlist j ci i0 b0 jae adie iae ee ern E 214 Exporting Pblocks for ISE Implementation 0 0000 c cece eee eee eee 215 Importing ISE Implementation Results 0 0 0 e eee eee eee 216 Chapter 8 Analyzing the Design Using the Floorplanning Environment 00 0 eee e ee eee 221 Using the Device View a siicsete le iiet eee tale se decade tose dag lecd hat e ated ang aisle oben od 221 Using the Schematic View 0000s 227 Using the Instance Hierarchy View 00 0000 e eee eee eee ee 236 Using the Properties View 0 0 000 c cece eee eee eee eee 238 Using the Netlist VIEW asec dciteciend uate dig tguerdlgdislend o ie pin yen apy ni nnd os ee 239 Using the Constraints View 0 0 0000 e eee eee 243 Using the Physical Hierarchy View 00 00 e eee eee eee eee 247 Using Common Popup Menu Commands n s sassa sasssa e eee eee eee 251 Analyzing the I O Pinout and Clock Logic 0 e eee eee 252 Analyzing the RTL Design 1is igiitsntag iene el Pha ei eudarbRieg
84. enables you to configure launch and monitor multiple synthesis runs using the Xilinx XST synthesis tool You can define reusable strategies for synthesis runs As an example you might create strategies for power performance or area optimization You d then assign these strategies to individual runs and launch them simultaneously or serially The synthesis run results are displayed interactively and report files are accessible Running multiple synthesis strategies results in multiple netlists being created and stored within the PlanAhead project PlanAhead then enables you to interactively load the various versions of the netlist into the environment for analysis During the netlist import Floorplans can be created for I O pin planning device analysis floorplanning and implementation Implementation runs can be created from any completed PlanAhead synthesis run floorplan or imported third party synthesized netlist Creating floorplans allows you to experiment with various logical constraints physical constraints or alternate devices You can define reusable strategies for implementation runs As an example you might create strategies for the various map logic optimization options or par effort levels You d then assign these strategies to individual runs and launch them simultaneously or serially The implementation run results are displayed interactively and the command report files are accessible Design Analysis and Floorplann
85. environment simply load this alternate view layout Then select Layout gt Load Layout gt PlanAhead Default to return back to the default PlanAhead environment Project Environment View Layout A Project environment is available for RTL development and analysis launching synthesis runs launching implementation runs and managing the overall Project For more information see Chapter 2 Creating and Managing Projects When an RTL based Project is opened or when the Project environment tab is selected in below the toolbar buttons in the PlanAhead window the Project environment layout is displayed The views that display reflect the state of the design E Prentoves J omowe S F MATPUER s Fk include defines v 18 module thern 19 Source File Properties px 20 iic acik gt 15 if iic_sdat A Sources S Fioorpisrs temy F 24 Location C Datallanthead_Desiy fhe 35 ieee SAS Library work 26 slow_clkx 2 Se a7 Modified 27 07 11 27 58 AM 29 30 3 C Data Planahead_Designs Thermmymukta v Q WARNING 64 Expression sine truncated to Fk in target soe 3 A WARUMI LIEN Boat tata Aua nek conemctad te thie let neem S Coracle D 0 Ports Ulaboration Figure 4 3 PlanAhead Project Environment For the Project environment the areas of the viewing environment are defined as follows 1 Floorplans View RTL Sources View 2 Object Properties View Selection View PlanAhead User Guide www xili
86. file for the design Netlist directories Use the Add button to select directories in which to search for lower level modules and cores during netlist import By default the PlanAhead invocation directory and the directory that the top level netlist was selected from are included in the search path You can arrange the order in which to search these directories by selecting them and using the up or down arrows buttons Directories can be removed from the search path by using the Remove button in the dialog box 48 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Create New Project Wizard to Create a New Project Import Netlist Specify the Edif netlist that contains the top module and optionally a list of directories to be used as a search path during netlist reading Netlist file ajects Pland4head_Tutorial labs design_files 802RCV_cos13 edf New Project x fe LJ Netlist directories C Data pPlanshead_Projects PlanA4head_Tutorial labs design_files Figure 2 16 New Project Wizard Import Netlist Page 2 To continue with the wizard click Next The netlist will now be imported into PlanAhead which may take a few moments A status bar is displayed for each netlist imported Any information regarding warnings and errors will be displayed in the Console view and written to the planAhead log file A successful file parser message should be displayed Note PlanAhea
87. files with source recognized file extensions that are located in the directory tree will be imported Import Sources into Project To copy the source files into the PlanAhead Project directory structure rather than reference the original locations PlanAhead User Guide www xilinx com 45 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX New Project Add Sources Specify HDL files or directories containing HDL files to add to your project You can also add create sources later Project Sources Name Library Location bFt vhdl work C Data Plan4head_Designs NewDemo src bft_package vhdl work C Data PlanShead_Designs NewDemo src blk_mem_512X32 work C Data PlanShead_Designs NewDemo src FFtTop v work C Data Plan4head_Designs NewDemo src fifo_32 128 work C Data PlanShead_Designs NewDemo src Figure 2 13 New Project Wizard Add Sources 5 After adding the intended source files or directories click Next The HDL Source files are imported into PlanAhead The New Project Summary page is displayed next 6 To initiate the Project click Finish in the Summary page PlanAhead then displays the Project environment with the RTL related views available 46 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Create New Project Wizard to Create a New Project project_1 C Data PlanAhead_Projects project_1 project_1 ppr PlanAhead 11 1 LRO BAR i
88. for the Floorplan Choose Part Use the device browser to select a desired device or accept the default to use the entry defined in the top level EDIF netlist file Enter a floorplan name and select the target device Click Next Importing Constraints The Import Constraints page of the New Project wizard is now invoked 56 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Create New Project Wizard to Create a New Project New Project Import Constraints Import physical and timing constraints from a UCF file You can also import a UCF file later with the Import Constraints command Constraints files C Data Pland amp head_Projects project_1 project_1 data floorplan_1 fp ucf Figure 2 24 New Project Wizard Import Constraints Page 8 Use the Add button to select top level UCF or NCF constraint files for import You can arrange the order in which to import these files by selecting them and using the Up or Down buttons Files can be removed from the list by using the Remove button in the dialog box If module level NCF or UCF constraints are being used do not include them here Refer to the Importing Constraints on page 68 for more information on importing module level constraints 9 To continue the wizard click Next The UCF files are imported into PlanAhead This may take a few moments Importing Placement and Timing Results The Import ISE Implementation R
89. importing RTL source files in Verilog and VHDL These files are considered source files Only Projects created by importing RTL files contain Sources Projects created by importing synthesized netlists or empty Projects do not contain source files Floorplan Floorplans are merely a set of constraints associated with a selected netlist and device Creation of Floorplans is not required to use PlanAhead Implementation runs can be launched using any external User Constraints File UCF In order to modify or apply any constraints within PlanAhead a Floorplan must first be created Each Floorplan associates an active netlist with the specific placement and timing constraints defined in it Each Project netlist can support multiple Floorplans using different constraints or devices Floorplans may be saved closed restored copied renamed and deleted Closed www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 PlanAhead Terminology Floorplans remain in the Project but do not open by default upon reopening the Project which saves system memory Netlist A netlist represents a logical description of the design A netlist should be hierarchical consisting of a top level netlist with child netlists for underlying levels of hierarchy modules PlanAhead RTL based Projects can contain multiple netlists since multiple synthesis runs are enabled Constraint A constraint can either be a
90. information see Analyzing Timing Results Using the Instance Hierarchy View The Instance Hierarchy view displays a graphical view of the logic hierarchy Viewing the design from top to bottom you can easily identify module sizes and location within the design Select the Show Hierarchy command in the popup menu to invoke the Instance Hierarchy view 236 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Floorplanning Environment BEARLIO I lt Package Device 2 Schematic E Hierarchy lt Figure 8 20 Hierarchy View Only hierarchical instances are displayed in the Hierarchy view Primitive logic is grouped into folders that are represented as submodules Refer to the Using the Netlist View for more information about Primitive logic folders The widths of the blocks in the Hierarchy View are based on the relative FPGA resources including LUTs flops block RAMs and DSP48s Selected logic is highlighted so you can quickly see where critical logic resides in the design When logic contained in a module is selected the module highlights proportionally to the amount of logic selected det_unit_1 dctu_1is_8s G it det_unit_2 detu_11s_i y a det_unit_3 detu_11s_8s_1_3 B E Nets 349 Primitives 319 aa pdct_cos_table Package Device Schematic Sj Hierarchy X 4 E e ail amp
91. labs design_files hath ae ET Figure 2 32 Update Netlist Wizard Import Netlist Dialog Box PlanAhead User Guide www xilinx com 63 UG632 v 11 4 64 4 9 Chapter 2 Creating and Managing Projects g XILINX The Import Netlist dialog box contains the following editable options Netlist file Enter a name to identify the netlist containing the module to update the project Use the file browser to select the module netlist file for the design Netlist directories Use the Add button to select directories to be searched for lower level modules and cores during netlist import By default the PlanAhead invocation directory and the directory that the top level netlist was selected from are included in the search path You can arrange the order in which to search these directories by selecting them and using the Up or Down buttons Directories can be removed from the search path by using the Remove button Click Next to continue The Specify Replacement Module dialog box will appear Update Netlist Specify Replacement Module Select a module from the list below to use For the netlist update It will replace one of the modules in the current netlist Id Name File Library Pins 24 acs_3 viterbi edn viterbi_lib 36 25 acs_30 yviterbiedn viterbi_lib 36 26 acs_31 viterbi edn viterbi_lib 36 27 acs_4 viterbi edn viterbi_lib 36 28 acs_5 viterbi edn viterbi_lib 36 29 acs_6 viterbi
92. location All other existing rectangles are removed e Add Pblock Rectangle Enables you to draw an additional rectangle for the Pblock This is helpful when trying to create non rectangular shapes for Pblocks e Select Children Selects all child Pblocks for all selected Pblocks e Select Primitives Selects all primitive logic objects in the current Schematic view If modules are selected only the primitive logic objects inside of those modules will be selected This command is available in other views as well e Select Primitives Parents Selects all parent modules of the selected primitive logic objects If modules are selected they remain selected The command does not ascend the hierarchy and selects a module s parent This command is available in other views as well e Highlight Primitives The primitive logic that belongs to the selected modules is highlighted using the color selected in the secondary popup menu This command is available in many views If a group of modules is selected you can highlight each module primitive using a unique color by selecting the Cycle Colors option in the secondary popup menu This command is very helpful when displaying placement locations for groups of logic www xilinx com 251 Chapter 8 Analyzing the Design g XILINX hierarchy The module icons in the Netlist view are also highlighted with the same unique colors to easily identify associated objects from view to view e Unhig
93. logic Hierarchical netlist modules Hierarchical netlist modules or instances are displayed with a yellow I icons as shown below T LED decode7SeqDispCK_49_123 E receiver RCV_802_11 m Hierarchical netlist modules assigned to Pblocks Hierarchical netlist modules or instances are assigned to Pblocks are displayed with blue checkmark icons shown below busMuxWrapInst busMuxWrap Modules derived from NGC Modules that were derived from NGC or NGO format core netlist input files are displayed with a red square in the lower right corner as shown below The NGC file name is displayed in parenthesis ig BUZ dpram_depth16_width1 _dist_mem_gen_v1_1_xst_1 242 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Floorplanning Environment Black box Modules Modules that do not have netlists associated with them are displayed with a yellow I icon and a dark background This could be a result of a search path not being specified during Project creation or missing portions of the design E CONVDECOD viterbi Primitive logic instances usn 1 Primitive logic instances without placement constraints assigned display as an i inside a yellow rectangle Primitive logic instances with placement constraints assigned display a yellow rectangle with a blue stripe Primitive logic instances assigned to a Pblock display a blue checkmark inside a yellow rectangle Primitive l
94. netlist Floorplanner had a Group by Hierarchy function to recreate a name based hierarchy While not 100 accurate it was useful for design analysis and area based floorplanning PlanAhead does not provide this functionality and we recommend setting the appropriate control in the synthesis tool to either keep or rebuild the design hierarchy during synthesis This is a much more reliable and robust method to visualize the true hierarchy of the design Use the XST option which creates hierarchical netlists netlist_hierarchy rebuilt to accomplish this e Floorplanner color coded the hierarchy by default which is a manual process in PlanAhead You can add color to the hierarchy by selecting a hierarchy block in the Netlist view selecting Highlight Primitives from the context menu and then selecting Cycle Colors from the context menu The colors are not stored with the design Timing Analysis Path Visualization Floorplanner could be used in conjunction with Timing Analyzer to view the placement of individual timing paths To do this you would select a path in the timing report and direct Timing Analyzer to cross probe the path to Floorplanner Floorplanner would then highlight the objects in that timing path on the device view and show the connections of the path Often a timing problem could be traced to some sort of placement issue PlanAhead supports reading in and displaying information from the placed NCD file and the post route t
95. new HDL source file Location Designate a location to create the file Type Select either Verilog or VHDL format Library Select which library to reference for the file File to Create Displays the file location and name G New Source File Name imynewfile Location head_Designs demo project_new project_new srcs newsrcs Ga Type VHDL v Library bftLib E File to Create ins demo project_new project_new srcs newsrcs mynewfile vhdl Figure 6 6 Create New Source File Dialog 2 Once the information is entered click OK The RTL Editor opens with the newly created file Standard HDL templates are available in the RTL Editor to assist with defining certain logic constructs For more information see Using the RTL Editor Updating RTL Source Files Externally Referenced Source Files If RTL source files are not copied to the project the original versions are referenced by PlanAhead Therefore any changes made to the RTL source files are immediately recognized when the design is elaborated or when the RTL files are accessed Sources Copied to the Project RTL Source files that have been copied into the project during project creation or by using the Import to Project command must be either maintained within PlanAhead or updated if the original versions are modified 170 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the RTL Editor Updating source files can be accomp
96. of I O Ports on pins that will cause a design issue In Place I O Ports Sequentially mode when attempts are made to place an I O Port on a problematic pin a tool tip displays describing why the I O Port is not able to be placed The online DRC checks are enabled by default Many of these checks can only run when a netlist representing the final design is loaded The interactive I O placement rules include e Prohibiting placement on noise sensitive pins associated with Gigabit Transceivers GTs Currently all I O potentially noise sensitive package pins are prohibited e Prohibiting I O standard violations e Ensures that I O standards are not used in banks that do not support them e Ensuring that banks do not have incompatible VCC ports assigned e Ensuring that banks that need a VREF ports have free VREF pins e Proper assignment of global clocks and regional clocks only with EDIF NGC netlist and UCF imported e Ensuring Input and High Drive outputs only go to capable pins for Spartan 3 devices e Differential I O ports to the proper sense pin e Ensures that no output pins are placed on input only pins Placing I O Ports into I O Banks PlanAhead User Guide UG632 v 11 4 To place I O ports into I O banks 1 Inthe I O Ports view select an individual I O port a group of I O ports or Interfaces 2 Use one of the following commands Select Place I O Ports in an I O Bank from popup menu in the I O Ports view Clic
97. of design constraints targeted at a specified netlist and device They are created in PlanAhead to modify or experiment with devices or constraints You can select any number of top level UCF files to be used during creation of the floorplan Module level UCF files can also be imported using the Import Constraints command Once imported PlanAhead manages all of the constraints within the floorplan The original imported UCF files are no longer referenced by PlanAhead or by the implementation tools All of the imported and newly assigned constraints are merged together into a single UCF file passed to the implementation tools Multiple floorplans can be created for any given netlist based project or for any Synthesis run in an RTL based project Creating a Floorplan Synthesized Netlist and Empty Projects If working with synthesized netlist based or empty pin planning Projects an initial floorplan is created during the project creation process You are prompted to define a floorplan name and target device as well as any number of top level UCF files in the New Project wizard Module level UCF files can also be imported using the Import Constraints command To create a new Floorplan in an existing Project use of the following methods 1 Launch the New Floorplan Wizard using one of the following methods Select File gt New Floorplan Click the New Floorplan toolbar button ef Figure 2 34 New Floorplan Toolbar Button The New Flo
98. or selected object Fit Selection Fits the display to include all selected objects Fit Highlight Fits the display to include all highlighted objects Fit Markers Fits the display to include all marked objects Options Invokes the PlanAhead Options dialog box which is also accessed using Tools gt Options For more information see Customizing PlanAhead Display Options Refresh Redraws and refreshes the display e Metric Opens a submenu which lists all available metrics to display For more information on Metrics see Analyzing the I O Pinout and Clock Logic Analyzing the I O Pinout and Clock Logic Refer to Chapter 5 I O Pin Planning for more information Analyzing the RTL Design Refer to Chapter 6 Creating and Analyzing the RTL Design for more information 252 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Analyzing the Synthesized Design Analyzing the Synthesized Design Reporting Design Resource and Device Utilization Statistics Reporting Device Resource Utilization Statistics PlanAhead provides estimates of the number of device resources utilized by the design These device utilization statistics can be displayed or output as follows 1 Select either the ROOT design or any Pblock in the Physical Hierarchy view e 4 orig a G pblock_1 E pblock_ASIC_BIF_ADDR_O_hNib_ibuf 0 pblock_ASIC_BIF_ADDR_O_hNib_ibuf 1 E pblock_ASIC_B
99. populated in the Pblock e Clock Report Displays all clock signals contained in the Pblock as well as the number of clocked instances on each clock Local Global and Resource clocks are all displayed e Carry Statistics Displays the number of vertical carry chain logic objects assigned to the Pblock It also displays the tallest carry chain assigned to the Pblock and the percentage of its height in relation to the Pblock height Carry height utilization values over 100 may cause PlanAhead DRC errors and ISE map errors e RPM Statistics Displays the number of Relatively Placed Macros RPM objects assigned to the Pblock It also displays the tallest and widest RPM assigned to the Pblock and the percentage of its size in relation to the Pblock size RPM utilization values over 100 will cause PlanAhead DRC errors and ISE map errors PlanAhead does not indicate whether multiple RPMs will fit inside the Pblock rectangle e Clock Region Statistics Displays the utilization percentage of each clock region that the Pblock overlaps e Net Statistics Displays the number of internal and external nets in the Pblock e Cellview Statistics Displays the number of each type of logical resource assigned to the Pblock e Boundary crossing Nets Statistics Displays the number of nets that interface to the selected Pblock Any net that is connected to logic inside of the Pblock is referred to as a boundary crossing net Instances Tab The
100. resource statistical properties are displayed Once implementation results have been imported the clock placement statistics can be viewed PlanAhead User Guide UG632 v 11 4 www xilinx com 225 Chapter 8 Analyzing the Design g XILINX Clock Regions Od x Id Name Row Column ap m 1 xovO 0 0 5 Z 2 x0Y1 1 0 EF E E a amp E 4 x0Y3 3 0 5 x1 0 0 1 f 2 6 X1Y1 1 1 E 7 X1Y2 2 1 Z 8 X1Y3 3 1 X ne E Physical Hie amp Sources Clock Reg i Clock Region Properties Od 4 x a Mik Ie xov2 Physical Resource Estimates Z iZ Type of Site Count a DCI 2 a GLOBALSIG 18 2 IODELAY 60 PMVBRAM 1 TIEOFF 360 DSP48E 8 RAMBFIFO36 4 SLICEL 400 SLICEM 160 General Statistics Resources I O Banks Figure 8 5 Clock Region Resource Statistics Selecting the Clock Region will result in the associated I O banks and clock related logic sites also being selected The display color for Clock Regions in the Device view can be changed using the Tools gt Options gt Themes gt Device dialog box Printing the Device View You can print the Device view using the File gt Print command The current viewable area is printed To print the entire Device view zoom to fit and then print Opening Multiple Device Views Multiple Device views can be opened for the same floorplan This allows you to work on different areas of the device Open a seco
101. see the Xilinx website at http www xilinx com support mysupport htm Xilinx Customer Education Training e Designing with PlanAhead Attend this Xilinx Customer Education Training Course to learn about the PlanAhead functionality using a sample design Documentation e Xilinx ISE Design Suite Installation Licensing and Release Notes This document provides specific installation instructions and requirements Available from the software and from the Xilinx website e PlanAhead Release Notes The Release Notes provide specific information about new features in this release Available from the software and from the Xilinx website e PlanAhead Methodology Guide This Guide provides information about various strategies aimed at improving performance repeatability of results or reducing design times Available from the software and from the Xilinx website e PlanAhead Tutorials The following tutorials are available with the PlanAhead software and on the Xilinx website Quick Front to Back Flow Overview I O Pin Planning RTL Development and Analysis Design Analysis and Floorplanning Debugging with PlanAhead and ChipScope Using PlanAhead with Project Navigator Video Demonstrations e PlanAhead Technical Video Demonstrations Watch the video demonstrations to learn more about specific areas of the PlanAhead software Available from the Xilinx website only at http www xilinx com products design
102. tab at the perimeter Toggle auto hide of the PlanAhead Desktop The other docking areas will occupy the space To restore the view click the icon displayed on the tab Closes the window leaving other tabs or docking w Close areas to occupy the space To re opened a window or tab use the Window menu commands Each of these commands is also available using the right click popup menu in the banner of the view Using the View Auto Hide Capability The viewing areas can be placed in Auto hide mode to help control the view display To initiate auto hide mode click the view banner Toggle auto hide button or select the Auto hide command from the popup menu Floorplans Og g x Netlist C aE Ws Id Name Device State Netlist Z E R E EESE 1 cosp_sinn_lut_th13 w Nets 26 9 Primitives 235 Figure 4 6 Click the Toggle Auto hide Button in the Netlist View The entire Docking area will appear as a tab on the perimeter of the PlanAhead Desktop The other docking areas will grow to occupy the space 100 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Navigating Views Floorplans Od Gx Id Name Device State Netlist Ef BEE Se ee lnetlist 1f 09 Netlist Figure 4 7 Netlist View in Auto hide Mode Each auto hide tab has an icon that can be used to restore the view to its original location Hover the cursor over the appropriate auto hidden tab to display the view t
103. the Searching for Objects Using the Find Command page 270 Running RTL DRCs Selecting the DRC Rules to Run PlanAhead offers several Design Rule Checks DRCs that can be run after RTL design elaboration The available rules focus on power reduction and performance improvement opportunities 1 Select one of the following commands to run the DRC checks after elaborating the design Tools gt Run DRC Select the Run Design Rule Checker toolbar button 178 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Elaborating and Analyzing the RTL Design Figure 6 18 Run Design Rule Checker Toolbar Button 2 In the Run DRC dialog box select the desired rules For rule descriptions see Definitions of RTL DRC Rules 3 Click OK Analyzing DRC Violations If violations are found the DRC Results view will appear Group by Type v Name Library Location B top S amp Core 2 al e A FifoBuffer nac Cixin BG B blk_mem_512x32 ngc C xilinx 1 H a S VHDL 7 al bft vhdl work C xilinx y P E bft_package vhdl bFtLib C xilinx 4 core_transform vhdl bftLib C xilinx 1 round_1 vhdl bftLib Cixilinx 1 round_2 vhdl bftLib C Kilinx H round_3 vhdl bftLib C2 xilinx 1 cd round_4 vhdl bftLib C xilinx ye Ej i m l gt Ei Physical Hierarchy amp Sources Q RPWL 1 An instance dual port block ram i of type RAMB16_536_536 fro
104. the Find toolbar button kij Figure 8 58 Find Toolbar Button The Find dialog box will appear w Primitive C Match Case Figure 8 59 Find Dialog Box 2 View or edit the definable fields in the Find dialog box Find Select the object type Instances Nets Pblocks etc you wish to search for Netlist Select whether to search the RTL or Synthesized netlist Criteria For each object type a different set of search parameters are available in the dialog box In the first field select the way in which you would like to search for the objects Name Status Type Parent Pblock Module or Primitive count 270 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Analyzing the Synthesized Design The second field can be used to set boolean options for the search such as matches doesn t match contains or doesn t contain The third field enables you to input search criteria strings An asterisk can be used to define the search strings 3 Optionally click the More button to define additional search filters or to simultaneously search for additional types of objects A new row of search criteria fields will display in the Find dialog An AND OR field appears to define the additional search criteria Setting it to AND will define an additional search filter as displayed below Find Instances Netlist Synthesized w Criteria Type i v Block RAM AND w Parent
105. the design is not checked upon opening or closing PlanAhead It is checked during the Translate process step in Project Navigator When PlanAhead is invoked the UCF source files in the Project Navigator project are passed to PlanAhead where physical constraints can be added or modified When the Save Project command is used in PlanAhead the modified UCF files are written back to the original Project Navigator source location If constraint changes are made in PlanAhead and the Exit command is selected you are prompted to save changes back to the Project Navigator project before the tool closes If PlanAhead is invoked and no UCF file exists in the Project Navigator project you are prompted to create one This empty UCF file is then passed to PlanAhead Project Navigator projects with more than one UCF source file are supported Before PlanAhead is invoked a dialog box prompts you to select one of the UCF files All new constraints defined in PlanAhead will be written to the selected UCF file Any physical constraints that exist in a non chosen UCF file will remain in that file even if the value of that constraint is modified in PlanAhead Core level NCF files used in the Project Navigator design flow are not passed to PlanAhead To use or view any physical constraints in these files in PlanAhead you must manually merge them into a top level UCF file prior to invoking PlanAhead A temporary PlanAhead project is created in the ISE project dir
106. the floorplan to implement Part Select a target part or accept the default Constraints Browse to select a single top level UCF constraint file to use for the run This field is disabled if a floorplan is selected as the constraints from the floorplan will be used 3 Click Next to bring up the Choose Implementation Strategies dialog box Run Multiple Strategies Choose Implementation Strategies Create and configure one or more implementation runs using various flows and strategies Create Implementation Runs Name Strategy impl_2 ISE Defaults ISE 11 impl_3 MapTiming ISE 11 impl_4 MapGlobalOptParHigh ISE 11 j Runs to create 3 Figure 7 13 Run Multiple Strategies dialog box Enter a name and select a strategy for the first implementation run Click the More button to add more runs Enter names and choose a implementation strategies for the additional runs MOY Sr A Click Next to invoke the Launch Options dialog box For more information on specifying Launch Options see Creating and Launching a Single Implementation Run 8 Click OK to create the defined Runs and execute the specified launch options Implementing Pblocks PlanAhead has the unique ability to implement Pblocks individually The ISE software u option is used to isolate the module for ISE implementation This presents many benefits when trying to achieve maximum design performance a
107. the popup menu All available command option settings are displayed in the popup menu Options Translate nadbuild ur a False aul False alr False u False f More Options Map map utput registers b i Output registers 0 Input and output registers b lt none gt cm ignore_keep_hi False timing False pr B v Pack internal flops latches into input output 0 or both b types of IOBs 6 Click Apply and OK to save the new strategy Figure 7 36 Command Options and Description The new strategy appears as a User Defined Strategy and can be used for Design runs as described in Using the Design Runs View For more information about saved Strategies see Outputs for Environment Defaults Creating Common Group Strategies Design groups that want to create and use group wide custom strategies can copy any User Defined Strategy to the following directory lt InstallDir gt strategies Executing Runs on Multiple Linux Hosts PlanAhead currently is shipping functionality to allow parallel execution of Runs on multiple Linux hosts This is accomplished with simplified versions of more robust load sharing software such as Sun s Grid Engine and LSF Job submission algorithms are implemented using a greedy round robin style with Tcl pipes with Secure Shell SSH Limitations PlanAhead User Guide UG632 v 11 4 The limitations are as follows
108. this pin or instance name To Pins Instances is used to select paths that end at this pin or instance name Sort Paths By is used to sort the Timing report by constraint group or by slack www xilinx com 265 266 Chapter 8 Analyzing the Design g XILINX Transition is used to select either rise or fall Setup Hold Mode is used to select Hold analysis versus Setup analysis Number of Paths per Clock Group is used to determine how many paths to list per constraint Number of Paths per Endpoint is used to control the number of paths reported per path endpoint 3 After selections are made click OK to launch TimeAhead Excluding Paths from TimeAhead Analysis TimeAhead can exclude objects from timing analysis by using special control characters in the Filter options fields Exclusions Append an exclamation mark to any name full name or wildcard name to signify an exclusion For example if you enter the following From Pins Instances pblock_1 To Pins Instances pblock_1 The TimeAhead analysis uses the paths starting from instances in pblock_1 but not ending at instances in pblock_1 Inclusions and Exclusions You can specify a mix of includes and excludes For example if you enter the following From Pins Instances pblock_1 To Pins Instances pblock_2 pblock_3 If pblock_2 and pblock_3 have instances in common this can happen if pblock_3 is within pblock_2 then paths endin
109. tools The Create New Project wizard has an option to create a Project from ISE results The wizard walks you through project creation prompting for the netlist constraints placement and timing data For information on loading results from ISE Creating a Project with ISE Placement and Timing Results Summary PlanAhead User Guide UG632 v 11 4 PlanAhead provides all of the main functionality for common tasks previously done in Floorplanner and the transition to using it should be quite straightforward When launched from Project Navigator PlanAhead presents only those features that are specific to the requested process and hides the full featured PlanAhead environment In contrast when launched in standalone mode the full capability of PlanAhead is exposed While PlanAhead is a very easy tool to learn for basic floorplanning tasks it has considerably more analysis design optimization and design closure capabilities Refer to the PlanAhead documentation including the introductory video for further information http www xilinx com planahead www xilinx com 93 Chapter 3 Using PlanAhead With Project Navigator 94 www xilinx com XILINX PlanAhead User Guide UG632 v 11 4 XILINX Chapter 4 Using the Viewing Environment This chapter contains the following sections e The Viewing Environment e Navigating Views e Using the Workspace Views e Using Common Environment View
110. user gt Application Data HDI for Windows The journal file can be replayed to reproduce the session s previous commands TCL scripts can be created by copying commands from the journal file for replay later in PlanAhead It may be necessary to edit this file to remove any erroneous commands or commands from multiple PlanAhead sessions prior to replay Note Not every action in PlanAhead will log a TCL command into the journal file Error Log Files planAhead_pidxxxx debug amp hs_err_pidxxxx log The error files can provide valuable information for debugging PlanAhead crashes If PlanAhead issues a dialog box that warns of an internal exception error the error files are stored in the PlanAhead invocation directory on Linux and in C Documents and Settings lt user gt Application Data HDI on Windows When you open a case with Xilinx Technical Support include any generated error log files the PlanAhead journal file planAhead jou and the log file planAhead log These files contain no design data DRC Results results_x_drc txt The results from the Design Rule Check DRC are reported in the results_x_dre txt files created in the PlanAhead invocation directory on Linux and in C Documents and Settings lt user gt Application Data HDI on Windows Each time DRC is run a new file is produced in the PlanAhead Project directory with a corresponding number to results listed in the PlanAhead DRC dialog box
111. utilization estimates and mapping decisions may be negatively affected Warning www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Elaborating and Analyzing the RTL Design Table 6 2 Performance Rules Rule Name Rule Abbrev Rule Intent Severity Found latchin RPLD Found latch description for signal Warning design lt signal_name gt lt file_name gt lt line_num gt Latches creates difficult to analyze timing paths which require post implementation simulations to ensure implemented design match expected behavior Found RPCL Found combinatorial loop for signal Warning combinatorial lt signal_name gt loop in design lt file_name gt lt line_number gt Combinatorial loops are generated when a cone of combinatorial logic uses its outputs to feed back as partial input to the same cone of logic The total combinatorial delay from source to destination should be increased by the feedback path delay This type of structure may be required from the design expected behavior or may be unintentional PlanAhead User Guide www xilinx com 183 UG632 v 11 4 Chapter 6 Creating and Analyzing the RTL Design g XILINX 184 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 7 Implementing a Design The PlanAhead software includes a synthesis and implementation environment that allows multiple synthesis and implementation attempts using different
112. view and edit the editable options Floorplan name Enter the desired name for the Floorplan Choose Part Use the device browser to select a desired device or accept the default 6 Click Next The New Project Summary page is displayed next 7 To initiate the Project click Finish in the Summary page PlanAhead then displays the Project environment with the I O pin planning related views Creating a Project by Importing RTL Sources RTL source files can be imported to create a Project This can be used for RTL code development and analysis purposes as well as synthesis and implementation For more information on RTL development and analysis see Chapter 6 Creating and Analyzing the RTL Design 1 Select the Import RTL sources option in the Design Source dialog box PlanAhead User Guide www xilinx com 43 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX New Project Design Source Specify the type of sources for your design You can start with RTL or a synthesized EDIF Import RTL Sources You will be able to run RTL analysis synthesis and implementation Import synthesized EDIF or NGC netlist You will be able to run post synthesis design analysis planning and implementation Import ISE Place amp Route results You will be able to do post implementation analysis of your design Do not import sources at this time You will be able to do pin planning now and import a netlist later
113. views This provides a visual indication of the relationship between the physical package and the internal die Many types of device and design information is displayed in the various view There are extensive exploration possibilities such as e Select one of the I O banks is the Package Pins view e Click the General Tab in the I O Bank Properties view I O Bank Properties Og qx amp l gt BGR p I O Bank 5 Name I O Bank 5 i Available Pins 40 a Used Pins ip Total Pins 43 Ra I O standards Used T Vref Used cco Used ae z lt gt General Package Pins I O Ports Clock Regions g 7 1 p a filPackage x 1 Package Pins Om g gt Name Prohibit Port IO Std Dir Veco Bank Type Diff Pair Clock Voltage Min Trace Dly Max Trace Dly IOB Alias an I O Bank 4 22 hf G a I O Bank 6 43 Ham I O Bank 11 43 Ham I O Bank 12 43 Ham IO Bank 13 43 lt console J Package Pins Figure 5 10 Displaying I O Bank Location and Resources PlanAhead User Guide www xilinx com 133 UG632 v 11 4 Chapter 5 VO Pin Planning XILINX Viewing Clock Region Resources The clock regions are displayed graphically in the Device view They are currently shown an dark blue rectangles but the color selection can be modified in the Device dialog box accessible using Tools gt Options gt Themes gt Device The Clock Regions view al
114. 0 000 eee ee 105 Using the World View te lt coicee sieuv nce sguar gras op i ea eed terete le geet ee wee a4 106 Using the Status Bari i tataviowa sped tal ode edad wand eiee eect 107 Understanding Object Selection Options 0 00 e eee eee 108 Selecting Objects oo i435 i 5 i eir i ea EEA E EEE pile esas ede desde basa bee 108 Fitting the Display to Show Selected Objects 2 0 0 6 ccc cece eens 109 Using the Selection Vi W sso i24 55 004 sbi cde ie edie eater ede ede vaaciw es 109 Highlighting Selected Objects 0 e eee eee ee 110 Marking Selected Objects 000 e eee eee 110 Setting Selection RULES o ii0022ise4 siege sigan resider san eseed tiisa aesae Aven 110 Setting Selection Ability for Objects in the Workspace Views 111 Understanding the Context Sensitive Cursor 0 0 00000 rnrn nr 111 Configuring the Viewing Environment 00 000 eee 112 Customizing PlanAhead Display Options 00 00 e cece e eens 112 Setting PlanAhead Behavior Options 00000 c eee eee eee eee ee 118 Moving Views within Viewing Areas 0 0 6 cen eens 121 Creating Custom View Layouts 0 6 666 c cece tan iaia ees 122 Restoring a View Layout 0 0 6 6 eect ete nes 123 Chapter 5 I O Pin Planning Recommended Method for Pin Planning With Xilinx FPGAs 125 PinAhead IVER VICW oss c side 0 Ciel i ie Ge ee OR We Dae ig
115. 0 gen_fifo18_36 fofifo18_3 usbEnginet ud 4 050 1 415 65 062 Setup 0 225 usbEngine1fusb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_3 usbEngine1 ud 4 025 1 407 65 043 Setup 0 179 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_3 usbEngineD us 3 979 1 630 59 035 Setup 0 166 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_3 usbEngineD us 3 966 1 348 66 011 lusbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_3 JusbEngineO us 3 96 Setup 0 155 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_3 usbEngine0 u4 3 955 1 416 Setup 0 126 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_3 usbEngine0 u4 3 926 1 407 Setup 0 086 usbEngine1 usb_dma_wb_in BUZ2 UO gen_fifo18_36 fgfifo18_3 usbEngine1 ud 3 886 1 415 E a C e E aan S x dail TRCE impl_2 240 paths a TimeAhead results_1 10 paths x D gt Yo Ports Design Runs Figure 8 54 Timing Results Sorted by Slack and Total Delay PlanAhead User Guide UG632 v 11 4 www xilinx com 267 Chapter 8 Analyzing the Design g XILINX Click Ctrl and click the column header again to remove a sort from a column Flattening the List of Paths By default the paths are categorized by constraint You can flatten the list and view all paths by selecting the Group by Constraint in the Timing Results view icon in the Timing Results view toolbar Figure 8 55 Group Paths by Constraint Toolbar B
116. 000 288 Using the Draw Pblock Command 0 00 e eee eee eee eee 288 Using the New Pblock Command 0 0 0 e eee eee eee ee 290 Creating Multiple Pblocks with the Create Pblocks Command 290 Creating Non Rectangular Pblocks 0 e eee eee eee eee 292 Creating Nested Child Pblocks 00 00 293 Creating Clock Region Pblocks 0 0000 e eee eee eee ee 294 Working with Pblocks 3 666 466 eeid abiobs bed deere ea teehee eens 296 Understanding Pblock Graphics 0 0 0 c cece eee eee cece 296 Assigning Logic to Pblocks 1 6 0 aiei 298 Unassigning Logic from Pblocks 00 0 c cece eee eee ee 299 Movitig PDIO K siti dduiea edt abs Sele a eed ea ae ea 299 stretching a PDLOCK 6 3 6 pesi peiie iot patia KEG AE EE EEE EE E EEE E gah wee 300 Using the Set Pblock Size Command n nnnnnnun nnar nr eee eee 300 Modifying Non Rectangular Pblocks ssasssns rnnr r rnrernnrrnn nnn 301 Removing a Pblock Rectangle nunnu nunnnn nrnna rrr eee 301 Renaming a Plok er penceresi rencr kece ies er kan p begs Dene e p eai 302 Deletinga Phlotkss i e sisa eadtae reged cited Soe de oe dea ee etir 302 www xilinx com PlanAhead User Guide Viewing or Changing Pblock Properties 0 00 c cece eee eee eee 302 Setting Pblock Logic Types Ranges 0 000 ee 305 Setting Attributes f r Pblocks oii 2c pic ee beste e eee be eer gee cusi dreia d Esi 30
117. 02_11 Nets 111 B Primitives 426 channel channelinterfaceRx LED decode SegDispCk_49_123 receiver RCV _802_11 amp Constraints _ Figure 8 24 Collapsed Netlist Tree 240 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Floorplanning Environment Using the Primitives Folder When a module contains primitive logic the primitive logic is placed in a Primitives folder This helps condense the display the modules in the Netlist view x QW FPGA_RCY_802_11 H 5 Nets 111 Primitives 426 0 ASIC_BIF_ADDR_O_hNib_ibuffc 0 ASIC_BIF_ADDR_O_hNib_ibuff1 0 ASIC_BIF_ADDR_O_hNib_ibuffz 0 ASIC_BIF_ADDR_O_hNib_ibuffz 0 ASIC_BIF_ADDR_O_INib_ibuf O 0 ASIC_BIF_ADDR_O_INib_ibuf 1 0 ASIC_BIF_ADDR_O_INib_ibuf 2 0 ASIC_BIF_ADDR_O_INib_ibuf 3 0 ASIC_BIF_DA amp T_IOO__ibuf 0 dll ij ASIC_BIF_DAT_IO0__ibuf 1 ll 0 ASIC_BIF_DAT_IO0__ibuf 2 dl E ASIC_BIF_DAT_IO0__ibuf 3 ll 0 ASIC_BIF_DAT_I00__ibuf 4 ll 0 ASIC_BIF_DAT_IOO__ibuf 5 ll ASIC_BIF_DAT_IO0__ibuf 6 ll 0 ASIC_BIF_DA amp T_IO0__ibuf 7 dll G ASIC_ITO_I_obuf OBUF 0 ASIC_IT1_I_obuf OBUF 0 ASIC_ST_ATTR_IO__obuf 0 C 0 ASIC_ST_ATTR_IO__obuf 10 1 0 ASIC_ST_ATTR_IO__obuf 11 1 0 ASIC_ST_ATTR_IO__obuf 12 1 A ASIC ST ATTR I0 obuffi311 ji gt amp Constraints Figure 8 25 Primitives Folder in the Netlist View You can assign the Primitives folder directly to a Pblock resulting in
118. 1 tH Min Slack per placed BEL E CLB Metrics 2 LUT Utilization per CLB i FF Utilization per CLB S Pblock Metrics 6 LUT Utilization per Pblock l FF Utilization per Pblock Estimated Slice Utilization per Pblock t Min Slack per Pblock B Physical Hierarchy a Metric J J a fon age a a LUT Utilization per CLB Summary ia carne of LUT resources consumed by LOC Constraints Pol jf mE aas cSeG Details Helps to visualize LUT densities of your placed design BEE H Stix Bins Id From To Show Color o 7m e 255 255 255 1 2 7 8 1255 255 153 3 85 100 EE 255 153 0 4 EE 255 0 0 Vp Properties by Selection fi Package x 4 Figure 9 14 Metric Map in the Device View In order to display any of the slack related metrics a TimeAhead timing estimated mode analysis must first be run In order to display any of the CLB or BEL constraints type metrics the placement results from ISE implementation must be imported For more information see Importing Placement Results into Existing Project Multiple metric maps can be displayed simultaneously Hiding Metric Map Display To hide a metric map in the Device view select the metric and select the Hide or Hide Metrics from the popup menu or click the Hide Metrics toolbar button Ss Figure 9 15 Hide Metrics Toolbar Button Using the Metrics Results View
119. 2 20w 15 LWOMOSIS 12 20w 17 WOOS 12 20w 35 WwOMOSSS 2 zow woss Figure 4 4 PlanAhead Floorplan Environment defa deiak delak lak detak Gefen detak The areas of the viewing environment are the following 1 2 Object Properties View Selection View Floorplans View Physical Hierarchy View Metrics View RTL Sources View 3 Console View I O Ports View Package Pins View Design Runs View Results Views Timing Find Design Rule Check Metrics 98 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Navigating Views 4 Netlist View Constraints View Workspace Device View Package View Schematic View Instance Hierarchy View Reports WASSO Results 6 World View Navigating Views Toggling Views Displayed Tabs are created in the viewing areas for each view Views are activated by clicking on the tabs Multiple tabs are allowed for certain view types This may take a moment to get used to so we suggest you take a moment to experiment with the view manipulation as described below Selecting objects in one view will result in the same objects being selected in all other appropriate views This cross selection capability makes logic exploration and floorplanning much easier The default layout attempts to maximize the information displayed when various objects are selected The overall size of these viewing areas can be stretched by sliding the view borders The cursor wil
120. 200_dce_top or1200_de_ram de_ram ramb16_s9_1 RAMB16 194 8 cpuEngine or1200_dce_top or1200_dc_ram dc_ramframb16_s9_2 RAMB16 194 9 cpuEnginejor1200_dc_top or1200_de_ram dc_ram ramb16_s9_3 RAMB16 194 I Instances Type is Block RAM 36 x A Console Timing Results D I O Ports Design Runs FE SSN Results Figure 8 62 Find Results View A new Find Results tab is created each time the Find command is run The tab is named according to the Search criteria and number of objects found Objects can be selected directly from the Find Results dialog box Selecting objects from the list of found objects will select them in other PlanAhead views Multiple elements can be selected by using the Shift or Ctrl keys Additional commands are available using the popup menu The Find Results can be sorted by clicking any of the column headers You can sort by a second column by pressing the Ctrl key and clicking a second column header Click the X in a Find Results tab to close Find Results views 272 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 9 Analyzing Implementation Results This chapter contains the following sections e Importing ISE Placement and Timing Results e Analyzing Placement and Timing Results e Exploring Logic Connectivity e Highlighting Selected Objects e Highlighting Placed Modules e Marking Selected Objects e Displaying Design Metrics
121. 3 El SLICE_x18Y9 pblock_usbEngine0 gt usbEngine u2 sram_we I4 LUT6 0 094 2 907 SLICE_x18Y9 pblock_usbEngine0 lt usbEngineO u2 sram_we O net fo 4 0 430 3 337 E RAMB36_X1Y1 pblock_usbEngineO usbEngineO usbEngineSRAM BL 3 961 RAMB36_X1 1 pblock_usbEngineO FE usbEngineO usbEngineSRAM Bl Total 3 961 3 961 Destination Clock Path ante ot w General Report Instances Options 5 Properties Selection Timing Results TimeAhead results_1 10 paths Ogaqx Al Type Slack From To Total Delay Logic Delay Net St a SeLup U 1 9 USUE EU USU Ud WO YOUL OU Yet _1U10_90 1 yi U10_S0 1 IRISL I ew KALA JSt EUNE p USUCI IYI eu USC Yi ESR AY OU OUIRE EEr dur Van USUr FSNUUPLU rit VO T I OP Le EEIE 1 090 35u99 e Setup 0 166 usbEngine0 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_36 fblk inst_few k1 1 inst_fed one_p usbEngineO usbEngineSRAM BLI2 UO bIk_mem_generator valid cstr ramloop O ram r v5 ram SP WL 3 966 1 348 66 011 kal setup fusbEngine0 usb_dma_wb_in BU2 UO gen_fifo18_36 fafifo18_36 fblk inst_few k1 1 inst_Fedone_p usbEngine0 usbEnginesRAM BU2 UO blk_mem_generator valid cstr ramloop 0 ram r vS rar SP WI 1630 58 849 ERI Setup 0 155 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 Fafifo18_36 Fblkjinst_Few ki 1 inst_fed one_p usbEngine0 u4 dout 6 3 955 1 416 64 197 x Setup 0 126 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_36 fblkjinst_Few ki 1 inst_fed one_p usbEngi
122. 5 255 Mm 0 0 0 Mm 0 0 255 E 153 0 0 MB 204 102 0 255 255 255 Mmm 0 0 0 Description Color to use for selected objects Color for Tel commands Color For error messages Color for warning messages General Device I Os Bundle Nets Figure 4 21 i Cancel General Display Options Select a color to reveal a pulldown and click the down arrow to open a popup menu to select another color Setting Device View Display Options The Device tab allows you to adjust the default color visibility and selection options for each object type in the Device view PlanAhead User Guide UG632 v 11 4 www xilinx com 113 Chapter 4 Using the Viewing Environment g XILINX G PlanAhead Options Planahead Dark Theme v Delete Frame Color Fill Color EE 204 102 255 E 153 51 255 E 170 151 189 EE 102 0 204 EI 225 196 255 EE 143 131 1 EE 0 153 0 EE 0 255 255 E 0 255 255 EE 255 102 0 EE 255 102 0 EE 0 215 217 EE 0 215 217 EE 255 102 0 EE 255 102 0 EE 0 1 204 WE 51 51 51 E 102 102 102 EE 255 0 0 E 255 0 255 EE 51 255 51 EE 0 0 102 255 200 0 E 0 255 255 EE 255 0 255 E 255 175 175 E 255 200 0 E 255 255 0 E 153 153 255 EE 255 0 0 Object Type Display Pblock 1st Level Pblock 2nd Level Pblock 3rd Levels Assigned Instance 10 Net Shortcuts Bundle Net Placed Port a Fixed Port Schema
123. 6 Using Resource Utilization Statistics to Size Pblocks 307 Placing Pblocks Based on Connectivity 0 000 c eee eee 309 Displaying Bundle Net Properties uss 0 e eee eee eee eee ee 310 Adjusting Bundle Net Defaults 0 0 one eee 311 Using the Automatic Pblock Commands 0000 00 eee e eee 311 Automatically Creating Pblocks 0000 eee eee eee 311 Running the Automatic Pblock Placer 0000 eee 313 Working with Placement LOC Constraints 00 0 e eee eee 315 Understanding Fixed and Unfixed Placement Constraints 00 315 Understanding Site and BEL Level Constraints 000000008 315 Assigning Site Location Placement Constraints LOCs 00 000005 316 Assigning BEL Placement Constraints BELs 0 00 0000 e eee eee 316 Adjusting the Visibility of Placement Constraints 00 0000008 317 Viewing Logic Connectivity using Show Connectivity Mode 318 Moving Placement Constraints 0000 318 Deleting Selected Placement Constraints 0 00000 e eee eee eee eee 319 Selectively Clearing Placement Constraints 0 00 c eee eee eee eee 319 Moving Pblocks with Placement Constraints Assigned 000000 00s 324 Locking Placement During ISE Implementation 00000000000 324 Setting Prohibits cs 3scssa
124. 7 Configuring Remote Hosts Click the Add button to enter the names of remote servers Toggle the Jobs option to specify how many processors on the remote machine to use Individual runs are launched on each processor No multi threading of processors is used Toggle the Enable option to specify whether to use the server You can use this field when launching runs to specify which servers to use for the selected runs to be launched Optionally modify the Launch jobs with field to change the remote access command The default is ssh Note Use extreme caution when modifying this field For example removing BatchMode yes may cause the process to hang because the shell incorrectly prompts for an interactive password Optionally click the Run pre launch script button and define a script to run prior to launching the runs Use this option to pass an environment setup script if you do not have ISE set up upon login cshrc or bashrc Optionally click the Run post completion script button and define a custom script to run after the run completes Optionally click the Send email to button and enter an email address to send notification when the run completes Select one or more hosts and select the Test button to verify that the server is available and the configuration is set up properly Note It is highly recommended that you test each host to ensure proper set up Select the Remove button to delete selected remote hosts C
125. 84 N Netlist update 61 Updating a module level netlist 62 Updating the top level netlist 61 Netlist view 239 Collapsing the netlist tree 240 Selecting logic in the Netlist view 243 Understanding the Netlist view icons 242 Using the Nets folder 241 Using the Primitives folder 241 View specific popup menu com mands 243 Nets Display See Connectivity New Device View 226 New Project 39 O Open PinAhead 83 96 127 Open Project 60 Options 112 233 Output files 24 P PACE transition to PlanAhead 86 Package Pin Properties 132 Package Pins view 130 Prohibiting I O Pins Package view 131 Placing I O Ports 143 Printing 132 Prohibiting I O Pins Show Differential I O Pairs 132 Viewing Package Pin properties 132 Pblock See Floorplanning Physical Hierarchy view 247 Understanding the Physical Hierar chy icons 248 Using the ROOT Pblock 248 Working with Relatively Placed Macros RPMs 249 PinAhead 125 Autoplacing I O Ports 128 146 Configuring I O Ports 139 Creating I O Port Interfaces 128 130 141 Creating I O Ports 138 CSV file Contents 136 Exporting 164 Importing 136 User Columns 137 Default Layout 96 Device resources 132 Device view 132 DRC See DRC HDL file Importing I O ports 137 I O Ports view 129 Importing I O Ports 136 Layout 84 Opening 96 127 Package Pins view 130 Package view 131 Placing GT I O Ports 148 Placing I O Ports 142 Enabling DRC 143 Into I O Banks 143 Sequentially 145
126. A Console D 1 0 Pons amp ChipScope Figure 11 8 ChipScope View The main ChipScope view shows the list of debug cores connected to the ICON controller core The ChipScope view also maintains the list of unassigned nets at the bottom of the window Debug cores and ports may be manipulated from the popup menu or the toolbar buttons on the left side of the view Creating and Removing Debug Cores PlanAhead User Guide UG632 v 11 4 ChipScope debug cores can be created in the ChipScope view by clicking the Create ChipScope Debug Core popup menu command or toolbar button Using this interface you can change the parent instance debug core name and set parameters for the core Figure 11 9 To remove an existing debug core select the core in the ChipScope view and select the Delete popup command Create Debug Core Parent Instance top la Name debugcore_1 Type chipscope_ila v1 7 Options enable_storage_qualification max_sequence_levels 1 sample_data_depth 1024 sample_on rising edge use_rpms enable_storage_qualification qualify storage Figure 11 9 Creating a Debug Core www xilinx com 335 Chapter 11 Debugging the Design with ChipScope g XILINX Adding Removing and Customizing Debug Core Ports In addition to adding and removing debug cores ports of each debug core may be added removed and customized to suit your debugging needs To add a new port 1 2 4 Select the core C
127. Ahead User Guide UG632 v 11 4 XILINX Analyzing the Synthesized Design The Timing dialog box displays G Run TimeAhead Results Name results_1 Delay Options Interconnect Estimated v Speed Grade 1 default w Report Options From Pins Instances Through Pins Instances To Pins Instances Sort Paths By Slack Transition Rise Fall Setup Hold Mode Total Number of Paths Number of Paths per Endpoint Figure 8 52 Run TimeAhead Dialog Box 2 View or set the definable fields in the Run TimeAhead dialog box PlanAhead User Guide UG632 v 11 4 Results Name View or enter a name for the internal results displayed in the Timing Results view tabs Interconnect Set the timer mode used The field toggles between the following options Estimated Estimates logic and typical route delays based on pseudo placement None Estimates all logic primitive delays without any estimated route delays This report should correlate with the Trace report after the ISE map command is run Speed Grade Adjust the device speed grade to experiment with alternate speed grades Filter Options are used to trim the list of paths the Timer will run on A wildcard can be used to delineate multiple signals From Pins Instances is used to select paths that source from this pin or instance name Through Pins Instances is used to select paths that travel through
128. Ahead User Guide UG632 v 11 4 This section details the steps involved in running I O Port and clock related DRCs See Running Netlist and Floorplan DRCs in Chapter 8 for information on running netlist and floorplan related DRCs Individual rules can be selected and run as follows 1 Select Tools gt Run DRC The Run DRC dialog box opens as shown in Figure 5 33 www xilinx com 151 Chapter 5 VO Pin Planning XILINX CB Run DRC Results Name results_1 Rules to Check 41 of 41 Ge All Rules 41 MI Floorplan 5 Clock 5 a w Global 5 F Clock region primary secondary CRPS HM IBUFG to DCM connectivity DCI Mi DCM to BUFG connectivity OCMB E Number of BUFGs allowed for DCM DCMN M DCM and BUFG connectivity DCME MM Bank 13 Md DCI 1 MI IDLY 1 Gi 10 Standard 11 M Bank IO standard Vcc BIVC M Bank IO standard Support BIVB M Bank IO standard Termination BIT HM Bank IO standard Vref BIVR M Bank IO standard Vref Occupied BIVRU M Bank IO standard limits BISLIM M Bank IO standard VRN YRP Occupied DCIP M Inconsistent Diff pair IOStandards DIFFISTD M Inconsistent Diff pair 1OStandards DIFFISTDDry wM Yccaux voltage requirement VvCCAUX Gt DCI 1 MI ClkBuf 1 Mi IOB 10 I IOB clock sharing OCS M IOB set reset sharing lOSR M Differential IO pads IODI IOStandard Type OSTDTYPE M Number of 10s lOCNT M 10s placed on disallowed sites IOPL M M
129. CoverArea General J ParHighEffort 2 XST 10 f da XST Defaults Text Editor GHISE 10 Select an option above to see descripti J ISE Defaults J MapTiming 3 fa ManflinhalNntParHir gt Figure 7 34 PlanAhead Options Strategies 2 Copy the supplied PlanAhead Strategies to the User Defined Strategies area for modification by using one of the following commands Select the Create a copy of this strategy Strategies toolbar button 2 Figure 7 35 Create a Copy of this Strategy Toolbar Button Select the Copy Strategy popup command A copy of the strategy will be made in the User Defined Strategies area allowing modification of command option values on the right side of the dialog box For more information about the strategy file see Strategy Files lt strategyname gt psg 3 Edit the definable option in the Strategies dialog box are as follows Name Enter a Strategy name to assign to a Run Description Enter the Strategy description which will be displayed in the Design Run results table Flow Enter the tool and version the strategy is intended for 4 Click a command option to view the option description at the bottom of the dialog box 210 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Executing Runs on Multiple Linux Hosts 5 Modify command options by clicking in the command option area to the right and selecting an option from
130. D2_F52_2 19 P13 2UserIO LOP A 30 01 IOB_X1 41 IO_L9P_D1_F51_2 20 P12 2UserIO LON 28 83 IOB_X1Y40 IO_L9N_DO_FSO_2 21 R8 2 CCO CCO_2 22 V9 2 CCO CCO_2 D D A D A D p D D D D pe D D D D D D D D General Package Pins I O Ports Clock Regions Figure 5 38 WO Bank Properties Package Pins Defining the I O Port Switching Phase Groups In some cases different groups of I O within a bank have a synchronous phase offset from one another meaning it is not possible for them to switch simultaneously This is true of data and strobe signals in many memory interfaces In this case proper SSN accounting must be informed by phase information A phase group is a logical grouping of ports that are all in phase with each other from a timing perspective i e their clocks have the same frequency and phase By creating a grouping phase not only is a group created but I Os with a different phase are being separated The noise produced by the groups within a bank is summed to get the total noise for that bank and if all outputs are either in phase with each other or do not have a synchronous relationship the output can be expected to switch change values at the same time If in the SSN analysis a bank is failing phase groups can be used to group ports that are at separate synchronous phases thus lowering the total noise for that bank when the SSN predictor is run again To set the switching phase for a
131. E Defaults ISE 11 Description ISE Defaults including packing registers in IOs off Status PAR Complete Parent v synth_1 Run Directory C Data Plandhead_Designs Therm project_new project_ne lt jii gt General Options Monitor Reports Selection Figure 7 17 Setting Implementation General Properties View or edit the information found in the Implementation General Run Properties dialog box Name Defines the Run name Strategy Invokes the Strategy browser to select a Run Strategy Description Defines the Run description Status Displays the status of the Run Parent Displays the synthesis Netlist or Pblock being implemented Run Directory Displays the location that the run data exists or will be created in www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Monitoring and Configuring Runs Viewing the Run Strategy Options The command line options that are defined in the Strategy can be viewed and modified in the Run Properties Options dialog box Select the Run and then select the Options tab in the Run Properties view opt_mode speed opt_level 1 register_balancing no Fsm_encoding auto ic off auto_bram_packing no use_dsp48 auto resource_sharing yes iob auto netlist_hierarchy rebuilt 0O power no More Options netlist_hierarchy Netlist Hierarchy General Options Monitor Reports J erti k Selection
132. E pblock_ASIC_BIF_ADDR_O_hNib_ 8 pblock_ASIC_BIF_ADDR_O_hNib_ E pblock_ASIC_BIF_ADDR_O_hNib_ pblock_FPGA_RCV_802_11 Figure 10 17 Select Pblock Dialog Box Unassigning Logic from Pblocks Instances may be removed from Pblocks as follows 1 Select the instances by any means 2 Select the Unassign popup command A confirmation dialog box appears asking to confirm the removal of instances from the Pblock Moving a Pblock PlanAhead User Guide UG632 v 11 4 Moving a Pblock is done by selecting and dragging the Pblock within the Floorplan and dropping it in the new location The dynamic cursor shaped like a hand indicates that the Pblock is selected for moving Ensure that the outer Pblock rectangle is selected and not one of the instances assigned to it If the Pblock is moved to a location which includes new device logic types such as BRAM DSP etc a dialog box is displayed prompting you to add the new range types to the Pblock definition Pblocks behave different when location placement constraints are assigned inside of them The desired target location should contain adequate resources to assign the placement constraints As the Pblock is being dragged around the cursor will indicate which are legal placement sites for a move If not a dialog box is displayed prompting you to either remove or leave the location constraints intact Fixed and unfixed location constraints are listed separately in th
133. EngineD usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop 0 ran Total 3 101 3 101 lt gt General Report Instances Options E Selection Figure 8 56 Path Properties Report tab Notice how the report has a similar format to the Trce report By default selecting a path will also select all instances contained in it Selecting any of the blue hyperlinked objects in the report will also select them in other views such as the Netlist and Device views Multiple paths may be selected using the Shift and Ctrl keys All instances contained in all selected paths will be selected but the Path Properties will only display information about the first path selected PlanAhead User Guide www xilinx com 269 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX Displaying Timing Path Reports in the Workspace An individual Timing Path Report can also be displayed in the Workspace for easier viewing To view the report 1 Select the desired timing path 2 Click the View Path Report popup menu command or click the View path timing report in the workspace toolbar button in the Timing Results view toolbar 2 Figure 8 57 View Path Timing Report in the Workspace Button Searching for Objects Using the Find Command PlanAhead enables you to selectively search for instances or nets using the Find command To invoke the Find command 1 Select Edit gt Find or click
134. Find to search for various Site types available in the Device They can then be selected in the Find Results view to highlight their location PlanAhead has many means to select the design clock related logic such as the Find command or the Schematic and Netlist views To place clock logic manually 1 Zoom in the Device view to locate the appropriate device site to place the logic 2 Select the Create Site Constraint Mode toolbar icon 3 Select the desired logic to place in the Find Results Schematic or Netlist views and drag it onto the available corresponding Device view site UOf clkO snkelk_bufrO Full Name frmi_pl _wrapperO frm1_spi_64_pl4 _snk_top UO clkO snkclk_b Parent Frmi_pl _wrapperO frm1_spi_64_pl _snk_top Type Regional Clock Site 5 BUFR _X0Y4 V Fixed General Statistics Pins Children Attributes Connectivity 148 BRR OF fe 4 rt RK S Figure 5 29 Manually Placing Clock Logic www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Removing I O Placement Constraints Removing I O Placement Constraints Placement constraints can be removed by first selecting them and then selecting the Unplace popup menu command Refer to Working with Placement LOC Constraints for information on selectively removing I O related placement constraints Configuring DCI_CASCADE Constraints The DCI_CASCADE constraint can be configured within the PlanAhead enviro
135. G Run Elaboration Top Module Name top Synthesis Options Figure 6 10 Elaborate Design Dialog Box Enter the top level module to elaborate in the Run Elaboration dialog box 3 Optional Click the file browser to enter synthesis options In the Synthesis Options dialog box specify the Verilog or VHDL language options and a Loop count G Synthesis Options Verilog Options VHDL Options Loop Count 1 000 i Cancel Figure 6 11 Elaboration Synthesis Options 5 Click OK Viewing Elaboration Results The Elaboration view displays the results of the compilation flagging irregularities in the RTL Source files Information Analysis completed successfully with 0 errors and 9 warnings 1 13 09 4 06 26 PM i Information 9 warnings 5 C Data PlanAhead_Designs Therm mydiv8 0 errors 2 warnings WARNING 65 bin_scaled was previously declared with a different range i WARNING 237 Expression size 16 truncated to fit in target size 9 E C Data Plan head_Designs Therm mymult8 0 errors 1 warning WARNING 68 Expression size 4 truncated to fit in target size 3 5 C Data PlanAhead_Designs Therm therm y 0 errors 6 warnings WARNING 149 Actual bit length 6 differs from formal bit length 5 for port state_iic WARNING 149 Assignment to state_iic ignored since the identifier is never used WARNING 153 Port state_div is not connected to thi
136. G632 v 11 4 The Pblock rectangle can be removed by selecting the Pblock and clicking the Clear Pblock Rectangle popup command Individual Pblock rectangles can be cleared one at a time Multiple rectangles and Pblocks can be cleared simultaneously Clearing Pblock rectangles does not delete the Pblock from the Physical Hierarchy www xilinx com 301 Chapter 10 Floorplanning the Design g XILINX Note Certain floorplanning advantages can be gained by removing the Pblock rectangle and not the partition from the Physical Hierarchy view The logic contained in the partition will receive an AREA_GROUP property for ISE During placement ISE will attempt to group the logic with AREA_GROUP properties and prevent it from being placed in other AREA_GROUP locations Renaming a Pblock Pblocks can be renamed using the General tab of the Pblock Properties view Enter the new Pblock name in the Name field and click Apply Deleting a Pblock You can delete a selected Pblocks as follows 1 Select one or more Pblocks in the Physical Hierarchy view 2 Press the Delete key or select the Delete popup menu command 3 In the Confirm Delete dialog box you can select the Remove Pblock children option to remove any nested Pblocks along with their partitions Otherwise when left unselected you will delete the selected Pblock only and move any nested Pblocks up one layer of hierarchy 4 Click OK to remove the Pblock partition from the Physical Hi
137. GT not allowed for part compatibility OPCMGT M BUFR placement problem IOBUFR M BUFIO placement problem IOBUFIO MI DSP48 5 RAMB16 1 M Inconsistent Diff pair IOStandards DIFFISTDSlew M Part compatibility implied prohibits not respected IOPCPR Select All Clear All Figure 5 33 Run DRC Dialog Box I O Pin and Clock DRC Rules 2 View or edit the Results Name field Enter a name for the results for a particular run for easier identification during debug in the DRC Violations browser The output file name will match the name entered 3 Inthe Rules to Check group box use the check boxes to select the design rules to check for each design object For information about each rule see I O Port and Clock Logic DRC Rule Descriptions Expand the hierarchy using the Expand All toolbar buttons or click the next to each category or design object Click the check box next to design object if you want all DRCs to be run click individual DRCs or click All Rules to run a complete DRC all rules for all design objects 152 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Running I O Port and Clock Logic Related DRCs 4 Click OK to invoke the selected DRC checks Viewing DRC Violations Once completed the DRC Results view opens Violation Properties Od x Netlist Oo gt Bal 5B f DPOP 1 H 6 Nets 889 gt Primit
138. I Ja ee larre ee omar nsira oe eile Harre ee mar mea vii Figure 2 39 Deleting Timing Constraints Removing Placement Constraints Placement Constraints assignment can be updated by simply importing new constraints Previous LOC constraint assignments are replaced with the new assignment LOC constraints are not removed if they are absent from the constraint file being imported Placement constraints can be selectively removed prior to import For more information see Selectively Clearing Placement Constraints Importing New UCF Constraint Files New top level or module level UCF or NCF format constraint files can be imported 1 Select the File gt Import Constraints command The Import physical constraints for options include Netlist netlist name Imports constraints relative to the top level of the design Instance Provides a browser to select a logic module instance to import the constraints relative to A pre selected logic instance is automatically seeded into the dialog box The Constraints files lists all files that have been selected to be imported into the Floorplan The Add buttons enables you to select UCF files for import Constraint files are imported in the order they appear in the list Use the Up or Down buttons to reorder the constraints files for import Files can be removed from the list by using the Remove button www xilinx com 71 Chapter 2 Creating and Managing Projects g XILIN
139. IF_ADDR_O_hNib_ibuf 2 So ok Metrics Figure 8 38 Physical Hierarchy View with ROOT Selected The Pblock Properties should appear in the Properties view 2 If the Pblock Properties are not displayed right click on the ROOT or Pblock and select Pblock Properties from the popup menu The Pblock Properties dialog box contains five tabs four of which are discussed in this section 3 Click the Statistics tab The Statistics tab displays valuable design information including overall device utilization for the various device resources carry chain count and max length RPM count and maximum sizes clock names and clocked instance count I O utilization and signal and primitive instance counts PlanAhead User Guide www xilinx com 253 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX Physical Resources Estimates Type of Site Available Required Utilization 10 240 5 913 10 240 3 507 5 120 3 607 0 16 MULT18X18 PCILOGIC PMY RAMB16 STAPTIIP rs IJnmoornocc0c0c ON N lt General Statistics Instances Rectangles Attributes Selection Figure 8 39 Pblock Properties Statistics Tab Exporting Estimated Hierarchical Device Utilization Statistics You can save the displayed data to an spreadsheet file PlanAhead enables a hierarchical style report to be generated You can define how many levels of hierarchy to report with estimates listed for e
140. INX Using the Floorplanning Environment TIMESPEC TS_CK_MIC_O PERIOD CK_MIC_ OFFSET OUT 14 5 ns AFTER GCLK_F OFFSET OUT 11 5 ns AFTER CK_MIC_O OFFSET IN 8 5 ns BEFORE CK_MIC_O amp TIMEGRP nRESET OFFSET IN 16 5 ns BEFC amp OFFSET IN 8 5 ns BEFORE GCLK_F amp TIMEGRP ASIC_ST_RD_IO OFFSET IN 9 51 amp TIMEGRP receiveADCValid OFFSET IN 11 5 amp TIMEGRP MAX_RX OFFSET IN 6 5 ns BEFO amp TIMEGRP nRESET_O OFFSET IN 16 5 ns BE NET GCLK_F TNM_NET GCLK_F NET CK_MIC_O TNM_NET CK_MIC_O amp NET ASIC_ST_DAT_REQ_T_I TNM ASIC_ i NET ASIC_ST_DAT_VALID_I_I TNM ASIC_ amp NET receiveADCBusy TNM ASIC_ST_DAT_ amp NET nRESET TNM nRESET NET ASIC_ST_RD_IO TNM ASIC_ST_RD_II NET receiveADCYValid TNM receiveADCVali NET receiveADC O TNM receive DCY alid NET receiveADC 1 TNM receive DCY alid NET receiveADC 2 TNM receive DCY alid NET receiveADC 3 TNM receive DCY alid NET receiveADC 4 TNM receiveADCValid NET receiveADC 5 TNM receiveADCValid NET receiveADC 6 TNM receive DCY alid NET receiveADC 7 TNM receiveADCValid NET receiveADC 8 TNM receiveADC alid amp NET receiveADC 9 TNM receiveADCYalid gi m gt TIMEGRP ASIC_ST_DAT_REQ_T_I OFFSET amp NET receiveADC 10 TNM
141. If the design data is saved to a local disk it will not be visible from remote machines Configuring Remote Hosts Linux Only After you have configured SSH as described in APPENDIX C PlanAhead enables runs to be launched using remote servers In order to do so they must first be configured To configure a remote host select one of the following commands Select Tools gt Options gt Remote Hosts Select the Configure Hosts button within the Run Synthesis gt Launch Runs options dialog box Select the Configure Hosts button within the Run Implementation gt Launch Runs options dialog box Select the Configure Hosts button within the Launch Selected Runs options dialog box The Remote Hosts dialog box displays www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 10 11 Executing Runs on Multiple Linux Hosts Ey PlanAhead Options x Remote Hosts Lb Hosts bai Name Jobs Enabled Re E xsihd colin 19 7 S B xsjho linux2 3 Selection Rules E Sess ed eae ay Shortcuts Schematic Strategies PUn ERSE Add Remove Test W Launch jobs with ssh 0 BatchMode yes general Run pre launch script ir Run post completion script Text Editor Send email to After all jobs C OK J Cancel Apply Figure 7 3
142. Inthe Synthesis Completed Successfully dialog box select the option that matches how you want to proceed Import the Netlist Now Will import the netlist into the PlanAhead design analysis and floorplanning environment enabling you to perform I O pin planning design analysis and floorplanning Run Implementation on the Netlist Will launch the Run Implementation dialog enabling you to create and launch an implementation run Do Nothing Now Will enable you to continue creating and launching synthesis or implementation runs using the PlanAhead environment commands Creating Multiple Synthesis Runs PlanAhead enables you to create and launch multiple synthesis runs simultaneously Various synthesis options and tools can be explored to find the best results 1 Select Tools gt Run Multiple Strategies to create multiple synthesis Runs 2 If prompted select Synthesis from the first Run Multiple Strategies dialog box 188 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Running Synthesis Run Multiple Strategies Set Up Synthesis Runs Define the Part and Constraints for the synthesis runs to be created Top Module Name therm 5 Part xc5wx3 Off324 1 l Synthesis Options Cr n cancel Figure 7 6 Set Up Multiple Synthesis Runs The Set Up Synthesis Runs dialog box has several options fields Top Module Name Enter or accept the top level RTL module name
143. LINX Importing I O Ports PlanAhead supports importing UCF CSV or HDL header format files into an empty PlanAhead Project to begin I O pin planning Creating an RTL based or synthesized netlist based Project will automatically populate the I O Ports view with the I O ports defined in the design CSV Format File A B To import an I O ports list from a CSV 1 Make sure you have a Floorplan in focus 2 Select File gt Import I O Ports gt From CSV 3 In the file browser browse to and select a CSV file to import The CSV file format is shown in Figure 5 14 page 136 At a minimum the Signal Name field must be present in the file C D E F G H lefele g 3 136 avy amar Top top Floorplan floorplan_1 Part xchvsx35tfi665 1 Generated by brianj on Fri Feb 06 17 26 39 2009 Build PlanAhead v11 1 LRO by ECloudinternalUser4 on Thu Feb 5 20 04 57 PST 2009 10 Bank Pin Number IOB Alias Site Type Min Trace Max Trace Prohibit Interface Sig P2 OPAD_ O0 5 MGTTXPO_114 34878 40691 TXP Wi2 OPAD_XO MGTTXP1_114 41406 48307 TXP B2 OPAD_X0 13 MGTTXPO_116 63540 74130 TXP G2 OPAD_ 0 15 MGTTXP1_116 55620 64890 TXP IAN wo im LAr at ANCOM A NANANA Mai Figure 5 14 VO Port List CSV Format CSV Columns CSV is a standard file format used by FPGA and board designers to exchange information about device pins and pinout e I O Bank The I O Bank in which the pin is located The software fills in this field fo
144. NT_BCD of CNT_BCD is 21 be lt ibed_cnt vhd x E Figure 6 7 RTL Editor lv An asterisk is appended to the file name in the view tab if the file has been modified without saving The file can be saved by using the Save Project command PlanAhead User Guide www xilinx com 171 UG632 v 11 4 172 Chapter 6 Creating and Analyzing the RTL Design g XILINX Using the RTL Editor Specific Popup Menu Commands The RTL Editor commands and a brief description of each is as follows Cut Copy Paste Cuts or copies the selected source code into the clipboard Pastes the contents of the clipboard Duplicate Selection Copies the current selected text and inserts it at the current cursor location Insert Template Invokes the Template browser to select a logic construct to insert in the RTL file Find Replace Invokes the Find Text dialog box to enter the text string in order to filter criteria for the search Selected text can be used to seed the search string The Find dialog box enables you to search forward or in reverse for each occurrence and a replace all option is available Find Next Find Previous Performs a search based on criteria in the Find dialog box Find in Files Invokes the Find in Files dialog box to enter text strings to search in the selected files The Find in Files Results view is displayed with the results of the search Indent Selection Unindent Selection C
145. Outputs for Environment Defaults This section briefly describes the files created during normal PlanAhead design operations These files can contain valuable information and are described here The last two reports are not automatically generated and require user interaction to create The output files are as follows e View Display Options File planAhead ini amp lt theme_names gt patheme e Window Layout Files lt layoutname gt layout e Shortcut Schema default xml e Strategy Files lt strategyname gt psg View Display Options File planAhead ini amp lt theme_names gt patheme The initialization file planAhead ini captures all of the current Tool gt Options settings which include display color and other viewing options for the entire PlanAhead Environment Upon exiting PlanAhead custom user settings are saved to this file for future PlanAhead sessions The file is automatically created in your home directory On Windows this is often in C Documents and Settings lt Username gt Application Data HDI lt version_number gt planAhead ini When PlanAhead is invoked the file is automatically imported from the PlanAhead installation directory first and then from the C Documents and Settings Owner Application Data HDI lt version_number gt directory if it exists On Linux this is often in HDI planAhead ini When PlanAhead is invoked the file is
146. Parameters 26 Input File Name synth_2 prj 27 28 Target Parameters 29 Target Device xeSvlx30 324 1 lt MT XST Report synth_2 x Figure 7 23 Viewing Report Files The scroll bar can be used to browse the report file Select the Find or Find in Files Toolbar buttons to search for specific text Use the Go to the beginning or Go to the End toolbar buttons to scroll to the beginning or end of the file Managing Runs Launching Existing Runs The Launch Runs command is used to launch existing Runs in the Design Runs view Launching Runs can be performed on Runs in any state including completed Runs The Launch Selected Runs dialog box is first displayed to set launch options 1 Inthe Design Runs view select one or more runs Use Shift click or Ctrl click for multiple selections 2 Select one of the following commands Select the Launch Runs popup command Select the Launch selected runs Design Runs toolbar button gt Figure 7 24 Launch Selected Runs Toolbar Button 202 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Managing Runs The Launch Selected Runs dialog box appears G Launch Selected Runs Launch Directory alPlandhead_Designs Therm project_new project_new runs Placement Export Export fixed placement only vi Options Launch Runs on Local Host Number of Jobs 2 w b Generate scripts only Runs to Launch 3 py sy
147. Pblock is created CLOCKREGION Select this button to define the Pblock range to be an entire clock region The Pblock rectangle is drawn to match the clock region boundary The Statistics Tab The Statistics tab of the Pblock Properties view displays content information about the Pblock Note that you can also save the contents to a text file using the Export Statistics icon gt BN pblock_cpuEngine_cpu_dbg_dat_i Physical Resource Estimates Site Type Available Required o Util LUT 6400 FF 6400 SLICEL 880 SLICEM 720 DSP48E 80 RAMBFIFO36 32 Clock Report Domain Module Resource Instar cpuClk_BUFGP top Globalt BUFGCTRL_X0Y15 wbClk_BUFGP top Global BUFGCTRL_X0Y19 p lt ii General Statistics Instances Rectangles Attributes Selection Figure 10 21 Pblock Properties View Statistics Tab The Statistics tab display the following Pblock information e Physical Resources Estimates Displays a chart of each resource type in the device Site Type Displays the Site Types defined within the Pblock rectangle Available Displays the number of sites contained in the Pblock PlanAhead User Guide www xilinx com 303 UG632 v 11 4 304 The Chapter 10 Floorplanning the Design g XILINX Required Displays the number of sites required for the logic assigned to the Pblock Utilization Displays the estimated percentage of the sites
148. Pin Global Clock Pin Clock Capable Pin WCC Pin GND Pin Special Pin Config Pin JTAG Pin Temp Sensor Pin ISYSMON Pin GT Pin II O Bank 0 II O Bank 1 IIO Bank 2 I O Bank 3 Yo Bank 4 IO Bank 5 Yo Bank 6 IIO Bank 7 I O Bank 8 Wo Bank 9 iPower Management Pin Q ES KS KS EA KS ES KA KS CYS S KA KS CS KS S KAY SIRS KS CSCS in T SYS ES KS ES KS ES SYS ES KS ES SYS SYS ES KS CS ESS ES KS Frame Color E 204 0 204 E O 204 51 EE O 204 204 E 255 153 153 E 255 204 0 EE 255 102 102 E 102 102 255 153 255 153 EE 51 204 0 E 255 255 0 Fill Color Mm 51 51 51 Mm 51 51 51 EE 153 153 153 E 153 204 255 EE 255 0 0 E 0 255 0 EE 102 102 102 EE 255 102 0 E 255 102 0 E 255 102 0 E 255 102 0 EE 255 102 0 Mm 102 0 0 E 204 0 204 E 0 204 51 E O 204 204 E 255 153 153 E 255 204 0 E 255 102 102 E 102 102 255 153 255 153 EE 51 204 0 E 255 255 0 General Device I Os Bundle Nets dpe i Cancel Figure 4 23 Theme Options Device Settings The check boxes can be toggled to the desired display effect In the Display column toggle the check boxes off to display the object types in the Device view In the Select column toggle the check boxes off to make the object types unselectable in the Device view They will still be visible if the Display toggle is on Note The Frame and Fill color options are not availab
149. PlanAhead User Guide UG632 v 11 4 December 1 2009 XILINX amp XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR LOS
150. Run the following command at a Linux terminal or shell to generate a public key on your primary machine Though not required you should enter and remember a private key phrase when prompted for maximum security ssh keygen t rsa 2 Append the contents of your publish key to an authorized_keys file on the remote machine The remote_server below should be changed to a valid host name cat ssh id_rsa pub ssh remote_server cat gt gt ssh authorized_ keys 3 Run the following command to prompt for your private key pass phrase and enable key forwarding ssh add You should now be able to ssh to any machine without typing a password The first time you attempt to access a new machine it will prompt you for a password then subsequent accesses will not If you are always prompted for a password contact your System Administrator to have your Linux account set up for passwordless SSH After a passwordless SSH is set up you can continue with Configuring Remote Hosts Linux Only PlanAhead User Guide www xilinx com 355 UG632 v 11 4 Appendix C Configuring SSH Without Password Prompting g XILINX 356 www xilinx com PlanAhead User Guide UG632 v 11 4 Index A About PlanAhead 5 PlanAhead ChipScope integration 329 PlanAhead Project Navigator inte gration 6 79 this Guide 5 Add Sources 168 Appendix A Menu and Toolbar Commands 341 B Installing Releases with XilinxUp date 351 C Config
151. ST defaults with _ 38 TimingWithIOBP Timing Performance with IOB Packing A TimingWithoutl Timing Performance without IOB Packing amp AreaReduction Area Reduction Ja PowerOptimizat Power Optimization da XST Defaults XST Defaults no hierarchy Figure 7 3 Choose a Synthesis Strategy e Part Select a target part or accept the default e Launch Options Select additional launch options Specify Launch Options Launch Directory wrk hdstaff brianj DESIGNS Therm project_1 pr Je Options Launch Runs on Local Host Number of Jobs 1 Launch Runs on Remote Hosts Configure Hosts Generate scripts only Do not launch now Figure 7 4 Synthesis Run Launch Options The Specify Launch Options dialog box provides the following launch options Launch Directory Specify a location to create and store the synthesis run data Note Defining any non default location outside of the project directory structure makes the Project non portable as absolute paths are written into the project files Launch Runs on Local Host Select this option to launch the Run on the local machine processor Number of Jobs Define the number of local processors to use for Runs This option is only used when launching multiple runs simultaneously Individual runs will be launched on each processor No multi threaded processors are used with this option Launch Runs on Remo
152. T PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2009 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners PlanAhead User Guide www xilinx com UG632 v 11 4 Included in the PlanAhead software source code is source code for the following programs Centerpoint XML The initial developer of the Original Code is CenterPoint Connective Software Engineering GmbH Portions created by CenterPoint Connective Software Engineering GmbH Copyright Copyright IBM Corp 1998 1998 2000 CenterPoint Connective Software Engineering GmbH All Rights Reserved Source Code for CenterPoint is available at http www cpointc com XML NLView Schematic Engine Copyright Copyright IBM Corp 1998 Concept Engineering Static Timing Engine by Parallax Software Inc Copyright Copyright IBM Corp 1998 Parallax Software Inc Java Standard Edition Copyright Copyright IBM Corp 1998 1995 2006 Sun Microsystems Includes portions of software from RSA Security Inc and some portions licensed from IBM are available at http oss software ibm com icu4j Powered By JIDE http www jidesoft com The BSD License for the JGoodies Looks Copyright Copyright IBM Corp 1998 2001 2008 JGoodies Karsten Lentzsch All rights reserved Redistribution and use in sou
153. TL source files the top level module name and the UCF file s to PlanAhead PlanAhead is invoked with the default I O pin planning PinAhead view layout displaying A quick RTL elaboration is performed to extract the top level I O ports and displays them in the PlanAhead I O Ports view When the PlanAhead project is saved or closed the original Project Navigator source UCF file s are updated This will also reset the Project Navigator design process state if appropriate Refer to Passing Logic and Constraints for more information about the integration mechanics and process Refer to Chapter 5 I O Pin Planning for more information about using the PlanAhead I O pin planning environment PinAhead I O Pin Planning Post Synthesis PlanAhead User Guide UG632 v 11 4 Note Whenever possible I O pin planning should be performed after logic synthesis The presence of a netlist ensures that the clocks clock logic differential pairs GTs etc are recognized and automatically considered during pin assignment in PlanAhead There are also many more Design Rule Checks DRCs that are performed based on logic connectivity and clocks to ensure a legal placement prior to implementation To perform I O pin planning in Project Navigator after running logic synthesis in the Processes pane expand User Constraints and double click IO Pin Planning PlanAhead Post Synthesis or select the Tools gt PlanAhead gt Post Synthesis IO
154. U0 gen_fifo18_36 fofifo18_ usbEngine0 u4 dout 23 0 050 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 inta_msk 4 0 050 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 inta_msk 5 0 050 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 inta_msk 7 0 050 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 inta_msk 6 0 039 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 dout 7 0 023 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 dout 25 ORR RATBHB GND TRCE results_1 240 paths x D gt 1 0 Ports Figure 7 43 TRCE Timing Results All of the path selection highlighting and tracing capabilities can now be explored using the TimeAhead interface Slack values appear red for paths with negative slack values The Timing Results can be sorted by clicking any of the column headers You can sort by a second column by pressing the Ctrl key and clicking a second column header Add as many sort criteria as necessary to refine the list order Multiple Timing Results can be displayed for a Floorplan Each result from Trce or TimeAhead will receive a tab at the bottom of the report as shown above PlanAhead User Guide UG632 v 11 4 www xilinx com 219 Chapter 7 Implementing a Design g XILINX 220 www xilinx com PlanAhead User Guide UG632 v 11 4
155. U2 U0 gen_fifo18_36 fgfifo18_36 fblkfins Setup Setup Setup 0 254 usbEngine1 usb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_36 fblkfins 0 252 usbEngine1 usb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_36 fblkfins 0 250 usbEnginel fusb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_36 fblkfins 0 225 usbEngine1 usb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_36 Fblkfins 0 179 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fgfifo18_36 Fblkfins 0 166 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_36 Fblkji lusbEngineO usb_dm BU2 UO gen_Fif off blk usbEnginel u4 dout 6 usbEngine1 u4 dout 22 usbEngine1 u4 dout 20 usbEngine1 u4 dout 23 Total Delay 2 Logic Delay Net Stages all usbEngineO usbEngineSRAM BU2 U0 blk_mem usbEngine0 usbEngineSRAM BU2 U0 blk_mem lusbEngineO usbEngineSRAM BU2 U0 blk_mem usbEngineO u4 dout 6 usbEngineO u4 dout 23 usbEngine1 fu4 dout 21 4 054 4 052 4 050 4 025 3 979 3 966 3 955 3 926 3 886 1 416 1 418 1 415 1 407 1 630 1 348 1 416 1 407 1 415 65 072 65 005 65 062 65 043 59 035 66 011 TRCE impl_2 240 paths G TimeAhead results_1 10 paths x D IO Ports Design Runs Figure 8 53 TimeAhead Timing Results The interface enables you to examine sort and select specific paths and instances In the Timing Results view the following information is displayed for each path e Constraint Name Displays the cons
156. User Guide UG632 v 11 4 XILINX Working with Pblocks Modifying Non Rectangular Pblocks Selecting a Pblock with multiple rectangles defined will select all of its rectangles They may be moved individually or together as a group To reshape one of the rectangles of a multiple rectangle Pblock select a rectangle and use the Set Pblock Size command or manually stretch to resize it To select a rectangle individually use one of the following methods e Select the Select popup command to select a single Pblock rectangle e Use the Pblock Properties Rectangles tab to select them individually Pblock Properties Od x ry e otk gt pblock_busMux WrapInst Q Id XLo Lo Hi Hi P O E E E E b fm 2 2 2 42 5 R D Eas A it Cinst i x K 7 baht Bi dost i ae 0 General Statistics Instances Rectangles Attributes i lt DI Netlist Constraints G Properties F Package Device x 4 Figure 10 19 Selecting the Pblock Rectangles Individually Pblocks defined that span PowerPC and MGT sites may automatically receive multiple rectangle regions This is done to enable the correct rectangle ranges to be defined for implementation Note The Xilinx ISE implementation tools are not optimized to handle too many ranges per the AREA_GROUP constraint It is best to use simple shape configurations such as L or T shapes Removing a Pblock Rectangle PlanAhead User Guide U
157. Workspace o Float Window H Package Device Figure 4 10 Splitting the Workspace Vertically Each panel now acts as an independent Device view allowing multiple views to be docked for viewing 104 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using Common Environment Views a 21 31 4 5 6 7 8 9 10 11 12 13 o gt oa in m o 0 PE KKKIOe cja jojz z T Ase I i lt E Package x 1E S 1 gt E Figure 4 11 Two Workspace Views Displayed Vertically Multiple views of the same type can be opened such as two Device views for viewing different areas of the device or different zoom levels Using Common Environment Views Using the Console View and Tcl Command Line The Console view displays messages from previously executed Tcl commands All messages are also written to the planAhead 1og file Indications of command errors warnings and successful completion are echoed to this window To invoke the Console View select Window gt Console INFO HD ArchReader 8 Loading clock buffers from C Xilinx 11 1 Plandhead parts xilinx virtex51lx 5vl1x50 ClockBuffers xml INFO HD ArchReader 3 Loading package from C Xilinx 11 1 Plandhead parts xilinx virtex51x 5v1x504f 324 Package xml INFO HD ArchReader 4 Loading io standards from C Xilinx 11 1 Plandhead parts xilinx virtex51lx I05tandards xml INFO HD ArchReader 5 Loading pkg sso
158. X G Import Constraints Import physical constraints For Netlist FPGA_RCY _802_11 Instance receiverjuartinst Description The physical constraints are based on the logical hierarchy 3 Names in the physical constraints file are relative to instance receiver fuartInst Constraints files C Documents and Settings brianj Desktop new_uart ucf Figure 2 40 Importing New UCF Constraint Files 2 Select either the Netlist or Instance option to import top level or module level constraints 3 Use the Add browser to select the files to import When done click OK 5 View either the planAhead log file or scroll through the Console view to look for any issues encountered during the import process Module level constraints are interpolated into the Project and are included as top level constraints for implementation After successful import the new placement constraint locations will be displayed in the Device and Package views Timing constraints can be viewed or modified in the Constraints view The PlanAhead interface enables further manipulation of the physical or timing constraints Creating Multiple Floorplans Additional floorplans can be created in an existing project Follow the steps for Creating a Floorplan Managing Multiple Floorplans The Floorplans view provides maintenance commands for the Floorplans in the Project You can copy delete and close Floorp
159. X Using the Core Insertion Flow Specifying Debug Nets and Clock Domains The ChipScope wizard will attempt to automatically detect the correct clock for each selected net or bus Figure 11 5 If multiple clocks are detected for a given net a dropdown list allows the selection of different clocks for the net or bus The debug net selection may be further modified by clicking the Add Remove Nets button Each net or bus may be configured for use as a trigger data storage or both When the net and clock configuration is correct click Next to proceed to the summary screen y Set up ChipScope Specify Nets to Debug Specify Nets for debugging using ChipScope cIk1_IBUF YV v DA cIk3 Yv vy X Set TRIG and DATA Export to Spreadsheet Set DATA only Add Remove Nets Nets to debug 96 lt Back Next gt Cancel 4 Figure 11 5 Specifying Debug Nets and Clock Domains Inserting ILA Cores The ChipScope Wizard inserts one ILA core per clock domain The nets that were selected for debug are automatically assigned to the trigger and data ports of the instantiated ILA cores The last wizard screen shows the core creation summary displaying the number of clocks found and ILA cores that will be created and removed Figure 11 6 If satisfied with the results click Finish to instantiate and connect the ILA cores in the design PlanAhead User Guide www xilinx com 333 UG632 v 11 4 Chapter 11 Debugging the Design wit
160. _cpuEngine_cpu_dbg_dat_o ao cpuEngine cpu_dbg_dat_i FifoBuffer 5 pblock_cpuEngine_cpu_dwb_dat_i H 8 cpuEngine cpu_dbg_dat_o FifoBuffer 5 pblock_cpuEngine_cpu_dwb_dat_o H cpuEngine cpu_dwb_dat_i FifoBuffer LJ E pblock_cpuEngine_cpu_iwb_adr_o i cpuEngine cpu_dwb_dat_o FifoBuffer pblock_cpuEngine_cpu_iwb_dat_i R cpuEngine cpu_iwb_adr_o FifoBurfer E pblock_cpuEngine_cpu_iwb_dat_o 4 cpuEngine cpu_iwb_dat_i FifoBuffer pblock_usbEngineO_usb_out E cpuEngine cpu_iwb_dat_o FifoBuffer pblock_usbEngine1_usb_dma_wb_in usbEngineO dma_out FifoBurfer 4 E pblock_usbEngine1_usb_out lt j B ta Metrics PI Netlist Constraints Figure 10 33 New Auto Created Pblock Running the Automatic Pblock Placer PlanAhead User Guide UG632 v 11 4 The PlanAhead Pblock placer will automatically size and place pblocks in the device Pblocks are sized based on SLICE content only All other device types are ignored when Pblocks are created The Pblocks are created with all RANGES defined The Pblock Placer command is intended to provide a quick placement of the selected pblocks This is often very helpful to view the data flow through the design You are required to manually adjust Pblock shapes before ISE implementation to include non SLICE resources Note The resulting Pblocks from the Place Pblocks command may not be suitable for ISE implementation They are sized based on SLICE logic only You are required to manually si
161. _ibuf ibufg O net fo 1 0 818 s BUFGCTRL_X0Y9 D usbClk_ibuf bufg I BUFG 1 068 S BUFGCTRL_XOY9 A usbClk_ibuf bufg O net fo 407 3 101 E RAMB36_x2Y1 pblock_usbEngine0 D usbEngine0 usb_dma_wb_in BUZ2 UO gen_fifo18_36 fgfifo18_36 fblk inst_few k1 Total 3 101 Data Path Delay Type Cumulative Location PBlock Logical Resource FIFO36_EXP 0 818 0 818 E RAMB36_x2Y1 pblock_usbEngine0 lt usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 Fafifo18_36 Fblkjinst_few ki 1 net fo 40 1 520 2 338 E SLICE_X19 8 pblock_usbEngine0 D usbEngine0 u2 wselj10 LUT 0 094 2 432 E SLICE_X19Y8 pblock_usbEngine0 lt usbEngine0 u2 wsel O net fo 42 0 381 2 813 E SLICE_X18Y9 pblock_usbEngine0 D usbEngine0 u2 sram_we I4 LUT6 0 094 2 907 E SLICE_X18Y9 pblock_usbEngine0 lt usbEngineO u2 sram_we O net fo 4 0 430 3 337 E RAMB36_X1 1 pblock_usbEngine0 D usbEngine0 usbEngineSRAM BUZ UO blk_mem_generator valid cstr ramloop 0 ram RAMB18 0 624 3 961 E RAMB36_x1Y1 pblock_usbEngine0 usbEngineO usbEngineSRAM BU2 U0 blk_mem_generator valid cstr ramloop 0 ram Total 3 961 3 961 Destination Clock Path Delay Type Delay Cumulative Location Logical Resource 0 000 0 000 s AB19 D usbclk net Fo 0 0 000 0 000 s AB19 D usbClk_ibuFfibuFg T IBUFG 0 818 0 818 E AB19 GusbClk_ibuffibufa o net Fo 1 0 000 0 818 E BUFGCTRL_X0Y9 D usbClk_ibuf bufg I BUFG 0 250 1 068 S BUFGCTRL_X0Y9 A usbClk_ibuf bufg O net fo 407 2 033 3 101 E RAMB36_X1 1 pblock_usbEngineO D usb
162. _resources design_tool resources index h tm 8 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Conventions PlanAhead User Guide UG632 v 11 4 Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Courier font Meaning or Use Messages prompts and program files that the system displays Example speed grade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild lt design_name gt Helvetica bold Commands that you select from amenu File gt Open Keyboard shortcuts Ctrl C Italic font Variables in a syntax statement for which you must supply values ngdbuild lt design_name gt References to other manuals See the PlanAhead Methodology Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name lt design_name gt Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has b
163. ach module at each level 1 Select the Export Statistics button to export the data to a spreadsheet file Figure 8 40 Export Statistics Toolbar Button The Export Pblock Statistics dialog box appears 254 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Analyzing the Synthesized Design C Export Phlock Statistics Pblock el ROOT File Name ans v4_color_design projects project_adder ROOT_stats xls IC Format Spreadsheet XML Levels v Reports to Generate Primitive Statistics Clock Report 10 Statistics C Carry Statistics C Net Boundary Statistics RPM Statistics i Cancel Figure 8 41 Export Design Utilization Statistics The Export Pblock Statistics dialog box contains the following editable options File Name Enter the name and location of the spreadsheet file to be created Format Select either an XML or Microsoft Excel output file format Levels Indicate the number of levels of hierarchy to traverse and include in the report as separated modules Reports to Generate Define the types of information from the Pblock Property Statistics view to include in the output report file Select the desired options for the exported file Click OK Reporting Design Resource Statistics PlanAhead provides estimates of the number of device resources contained in the design This same type of estimated statistical information can be display
164. ad environment Launch and Invocation of PlanAhead from Project Navigator The Processes pane of Project Navigator provides four main processes to accomplish pin planning and floorplanning tasks I O Pin Planning Pre Synthesis I O Pin Planning Post Synthesis Floorplan Area IO Logic Post Synthesis and Analyze Timing Floorplan Design Post Implementation Invoking any of these four processes will launch PlanAhead in a mode to most directly accomplish the selected task There is full integration between Project Navigator and PlanAhead This means that Project Navigator will automatically supply all required input files to PlanAhead Any saved output files from PlanAhead e g UCF based constraints will be saved to the proper location within the Project Navigator project www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Transitioning from PACE Floorplan Editor to PlanAhead It is important to note that when launched from Project Navigator PlanAhead is opened in a streamlined ISE Integration mode where not all functionality of standalone PlanAhead is available Launch and Invocation of Standalone PlanAhead PlanAhead can be launched by typing planahead at the standard command line shell prompt Windows or Linux or on Windows you can double click on the PlanAhead desktop icon To start using PlanAhead 1 Select Create a New Project from the launch screen 2 Follow the New Project wizard 3 Proceed to pin p
165. ailable for modifying existing interface content also as described in Creating I O Port Interfaces You can assign the individual pins busses or interfaces to I O pins by dragging them into either the Device or the Package view The entire group of pins is assigned to I O pins using various assignment pattern modes The modes available include Place I O Ports in an I O Bank Place I O Ports in Area and Place I O Ports Sequentially Each mode offers a different assignment pattern for the I O Ports to be assigned to pins Information about the number of ports being placed is provided on the cursor tool tip The mode remains active until all of the selected I O ports are placed or until you press the Esc key For more information see Placing I O Ports The software attempts to maintain correct assignment rules Differential pair ports are assigned into proper pin pairs Online DRCs are also available to help ensure legal I O placement The batch PlanAhead I O related DRCs flag such I O issues The Tools gt Autoplace I O Ports command places the entire device or any selected portion of the device automatically The command obeys I O bank rules differential pair rules and global clock pins and places as many of the I O Ports as possible 128 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the PinAhead Environment The command also attempts to group the interfaces as much as possible You can place Prohibits o
166. ains the following sections e PlanAhead Release Strategy e Running XilinxUpdate e Automatically Checking for Updates PlanAhead Release Strategy The PlanAhead software release strategy is the same as other Xilinx software tools PlanAhead is a tool that is targeted to introduce new technology and respond to customer New releases are periodically introduced The version number reflects the release e g 11 1 11 2 etc The Help gt About PlanAhead command will display the currently installed PlanAhead version To check for new PlanAhead releases run the Help gt Check for Updates command as described below Refer to the Xilinx ISE Design Suite Installation Licensing and Release Notes for more information about Xilinx tool installation Running XilinxUpdate PlanAhead now invokes the XilinxUpdate utility to download and install new releases The utility automatically searches all tools that are installed compares them with the newest updates on the Xilinx website and notifies the user of any available updates Users can selectively install updates for any Xilinx tool To check for and install PlanAhead updates select the Help gt Check for Updates command PlanAhead User Guide www xilinx com 351 UG632 v 11 4 Appendix B Installing Releases with XilinxUpdate XILINX 5 R Fa XilinxUpdate r Welcome Welcome to XilinxUpdate To get started Click Advanced to set or verify your p
167. al blocks to specific regions of the device using the graphical device view www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Transitioning from PACE Floorplan Editor to PlanAhead e Similar to PACE and Floorplan Editor you can use PlanAhead to lock down global logic such as place global clock buffers block RAMs DSP blocks PLL DLLs etc e Differing from PACE and Floorplan Editor you can also perform detailed low level floorplanning of specific LUTs FFs SRLs etc using PlanAhead In this way PlanAhead is a complete pin planning and floorplanning tool General I O Pin Planning and Floorplanning Tasks Transitioning from PACE or Floorplan Editor to PlanAhead is a relatively straightforward process as virtually all of the main operations have direct counterparts in PlanAhead Below is a list of those general features Note Some of the feature below are not available for Empty Design or Pre Synthesis modes I O Pin Assignment PlanAhead User Guide UG632 v 11 4 e Graphical drag drop assignment from IO Ports view to the graphical device or package views In the Package view both the top and bottom view perspectives are supported e Busses can be treated as set of pins and assigned as a whole during the drag drop operation e Similar to pre defined busses you can create user defined groups for group based pin assignment e Inthe IO Ports view you can assign IO properties e g IO standard drive st
168. all primitives to be assigned Note Netlist updates may require reassignment of the Primitives folder to the Pblock as logic names may have changed during re synthesis Using the Nets Folder The Nets folder contains all of the nets and busses defined at any level of hierarchy Busses can be expanded to show each individual bit PlanAhead User Guide www xilinx com 241 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX DI FPGA_RCV_802_11 Nets 111 4 ASIC_BIF_ADDR_O_hNib z3 P T n O 2 im T o o 5 O gt M ASIC_BIF_ADDR_O_INib amp ASIC_BIF_ADDR_O_INib_c amp ASIC_BIF_DAT_IOO_ amp ASIC_BIF_DAT_IOO__c amp ASIC_ST_ATTR_IO_ amp ASIC_ST_ATTR_IO__c amp ASIC_ST_ATTR_TO_ amp ASIC_ST_ATTR_TO_c amp ASIC_ST_DAT_IO_ amp ASIC_ST_DAT_IO__c amp ASIC_ST_DAT_TO_ amp ASIC_ST_DAT_TO__c amp bus_select amp CONN2_ amp CONN2__c amp EXTERNALCONN_ amp EXTERNALCONN__1 amp EXTERNALCONN__18 amp EXTERNALCONN__18 2 amp EXTERNALCONN__18 2 am amp EXTERNALCONN__18 2 bm lP D H SR amp H A 2 j D A Constraints Figure 8 26 Nets Folder in Netlist View As nets are selected they are highlighted in the Device view Selecting a bus will highlight all nets contained in it Nets can be viewed in the Schematic view Understanding the Netlist View Icons Various icons are used to represent the state of the netlist
169. allation Licensing and Release Notes for proper installation of this product The PlanAhead software can be invoked from any directory However invoking it from a project directory may prove advantageous as project specific log files can be more easily located Linux To invoke PlanAhead type the following command at the Linux command prompt planAhead Windows Double click on the Xilinx PlanAhead 11 shortcut icon Figure 2 1 Xilinx PlanAhead 11 Icon The PlanAhead Start in folder can be specified by modifying the desktop icon properties to define where the PlanAhead log files will be written PlanAhead User Guide www xilinx com 35 UG632 v 11 4 Chapter 2 Creating and Managing Projects The PlanAhead Environment will display CB PlanAhead 11 1 LRO i File Edit View Tools Window Select Layout Help XILINX toe Fimaxapc6errxtoapxexaneap rt so xrersh E ng PlanAhead Getting Started PlanAhead PlanAhead is a Hierarchical Design and Analysis Tool that will enable you to 1 Improve Design Performance through Analysis and Floorplanning 2 Optimize Results by Experimenting with Implementation Strategies 3 Improve FPGA on PCB Integration with the I O Pin Planning Environment Please select one of the following options to get started Create a New Project The new project wizard will guide you through importing an edif netlist or an ngc file and creating a floorplan Open a Previously Created Projec
170. an on Mon Feb 26 22 27 48 PST 2007 Start of session at 2 28 07 11 44 49 AM Process ID 4728 hdi project open file C Data PlanAhead_Designs PlanAhead_Tutorial labs projects Project_2 Project_2 ppr hdi project startUpdate name Project_2 file C Data PlanAhead_Designs PlanAhead_ Tutorial labs design_files revl_top_upda hdi project commitUpdate name Project_2 all yes hdi timing run name results_1 project Project_2 floorplan orig fp min_max max transition rise fall sort_by group int hdi dre run name results_1 project Project_2 floorplan orig fp hdi run add name run_1 project Project_2 floorplan orig_fp flow ISE 9 strategy EA 1 hdi run add name run_2 project Project_2 floorplan orig_fp flow ISE 9 strategy EA 2 hdi run schedule names run_l run_2 project Project_2 floorplan orig fp hdi run launch project Project_2 jobs 1 scriptsOnly no allPlacement no dir C Data PlanAhead_Designs PlanAhead_Tutori End of session at 2 28 07 11 47 57 AM Process ID 4728 Figure 2 4 Example PlanAhead Tcl Script PlanAhead User Guide www xilinx com 37 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX Using the Getting Started Jump Page When PlanAhead is invoked the Getting Started jump page is displayed in the PlanAhead window You can select the blue underlined command links to invoke specific commands or view documentation as shown above By default the last 10 p
171. analyze implementation results you are prompted to define a Floorplan name The Floorplan is then created for you and results are displayed The UCF file used to launch the run is loaded into the Floorplan www xilinx com 67 Chapter 2 Creating and Managing Projects g XILINX 68 A Floorplan can also be created prior to implementation to analyze the design or to modify constraints Click Select gt Import Run to import the desired synthesis run for floorplanning Once loaded use the New Floorplan command to create a Floorplan Refer to the Creating Multiple Floorplans for more information Additional Floorplans can be created using the New Floorplan or Copy Floorplan commands Importing Constraints UCF and NCF format constraints files are created by synthesis software tools designers Xilinx ISE software tools or by previous sessions of PlanAhead These files can be imported into a Floorplan Constraints consist of Timing constraints I O locations and standards and physical location constraints for various instances For more information regarding UCF format files refer to the Xilinx Constraints Guide The Floorplan must be initialized before importing physical constraints To import physical constraints do as follows 1 Select File gt Import Constraints This displays the Import Constraints dialog box gt Import Constraints Import physical constraints for Netlist FPGA_RCV_802_11 Instance
172. ances found in the RPM www xilinx com 249 Chapter 8 Analyzing the Design g XILINX RPM Properties fe oi x aff b E sdram_ctrl ROM o 4 x Id Name Cell Pins General Instances S Properties Selection Figure 8 35 Viewing All Instances in the RPM When you assign RPM logic to a Pblock the RPM size information will be displayed in the Pblock Statistics Properties Pblock Properties Og 4x B xa W 2 ROOT t RPM Statistics Total Number of Sets 1 Type Dim Avail Reqd Util Set Name E SLICE Max Width 56 1 1 sdram_ctrl ROM SLICE Max Height 64 5 7 sdram_ctr ROM lt Clark Reninn Statistirs lt Jili gt General Statistics Instances Rectangles Attributes Properties Selection Figure 8 36 Pblock Properties RPM Statistics The number of RPMs assigned to the Pblock along with the tallest and the widest RPMs are displayed This RPM size information is helpful when shaping the Pblock as the overall height and width utilization percentage is displayed 250 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Floorplanning Environment To save this data click the Save icon of the Pblock Properties dialog box and specify a file name for data Figure 8 37 Save Pblock Statistics to File Itis recommended that you increase the size of your Pblocks if they contain a large number of RPMs This e
173. and you are prompted to remove all floorplans and associated runs from disk Note You are prompted to save floorplans if any modifications were made during the PlanAhead session Saving a Floorplan Using Save Floorplan When a Floorplan is saved the files in the Project data directory for the saved Floorplan are updated For more information about which files are saved see Outputs for Project Data To save a Floorplan select File gt Save Floorplan or click the Save Floorplan toolbar button Figure 2 49 Save Floorplan Toolbar Button Using Save As Floorplan You may elect to modify an existing Floorplan and save it as a new name This results in the original Floorplan and the newly saved Floorplan both exiting in the Project To rename the Floorplan see Renaming a Floorplan To save a Floorplan to a new name 1 Select File gt Save Floorplan As The Save Floorplan As dialog box is displayed www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Floorplans 2 Inthe Save Floorplan As dialog box enter a new name in the New Name field 3 Click OK to save the Floorplan to the new name Any Runs defined in the Floorplan are also copied into the Saved Floorplan The Runs will have no results data in the Run directories and will display a Not started state Copying a Floorplan The primary reason for copying Floorplans is to select a different device or device architectu
174. ard VREF compatibility check for IOs in that bank Occupied Bank I O DCIP There are dedicated VRP and VRN I O Error Standard sites in I O bank which can also be used VRN VRP as regular IOs If a DCI I O standard is Occupied used in that bank these IOs should be left unoccupied Bank I O BISLIM Checks the I O placed within an I O Error Simultaneous bank against Simultaneous Switching Switching Output Output Noise Limits Inconsistent Diff DIFFISTD Checks that the terminals of a Error pair 1 O differential pair have the same I O Standards standard Inconsistent Diff DIFFISTDDrv_ Checks that the terminals of a Error pair 1 O differential pair have the same drive Standards Inconsistent Diff DIFFISTDSlew Checks that the terminals of a Error pair I O differential pair have the same slew Standards Vccaux Voltage VCCAUX Warns of any requirements on Vccaux Warning requirement based on used I O standards www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Running Simultaneous Switching Noise SSN Analysis Running Simultaneous Switching Noise SSN Analysis Running SSN Analysis Virtex 6 PlanAhead User Guide UG632 v 11 4 PlanAhead now incorporates the new Xilinx Simultaneous Switching Noise SSN predictor to improve the prediction of simultaneous switching output noise in Virtex 6 devices This tool is designed to provide estimates of the disruption that switching outputs will cau
175. area The Workspace may be split any number of times either horizontally or vertically Views may be closed by selecting the Close button in the view The Workspace view can be maximized or floated by selecting the view tab Opening Views Select the Window menu from the Main Menu to provide commands to open most window types Select a window that is already open to make it the active window For a list PlanAhead User Guide www xilinx com 99 UG632 v 11 4 Chapter 4 Using the Viewing Environment g XILINX of Window menu commands and a brief description see Toolbar Commands in Appendix A The Schematic view requires at least one object to be selected and is opened using the popup menu Schematic command or the Schematic toolbar button The Properties view requires at least one object to be selected and is opened using the popup menu lt Object type gt Properties command Select New Device View or New Package View to open an additional view in the Workspace Manipulating Views using the View Banner Commands Each viewing area can be manipulated using common window environment commands Table 4 1 View Banner Commands Toolbar Button Command Description a Maximizes and restores non Workspace views is Maximize restore Toaaletioatin Floats and docks non Workspace views Views may a gg 9 be floated outside of the PlanAhead Desktop Hides and restores the view When hidden the H entire Docking area appears as a
176. atic views in the Workspace The Getting Started page can be displayed by selecting Help gt Getting Started Viewing the Workspace Full Screen Double clicking the Workspace tab will result in the view being displayed full screen Workspace views can be restored by double clicking the view tab again You can also right click on the tab to view the Workspace tab popup menu Select either Maximize Workspace or Restore Workspace from the popup menu depending on the state of the Workspace Floating the Workspace View To Float the Workspace view select the Workspace view tab and use the Float Window popup menu command Printing the Workspace View You can print the View in focus in the Workspace Device View Package View Schematic View Instance Hierarchy View Select File gt Print to print the current viewable area Closing Workspace Views The views within the Workspace can be closed by clicking on the X icon in a view tab Device x Figure 4 9 Device View Tab with X Icon PlanAhead User Guide www xilinx com 103 UG632 v 11 4 Chapter 4 Using the Viewing Environment g XILINX Splitting the Workspace The Workspace viewing area can be split horizontally or vertically to enable multiple views to be displayed simultaneously To do so use the popup menu in the Device view to select the desired split ews eave Close Others Close All Previous Rk BIR IM TY New Horizontal Group A New Vertical Group O Maximize
177. atus is displayed in the Design Runs view Select Tools gt Design Runs to invoke the Design Runs view QL Name mle Pak gt v synth_1 I gt 196 av impl_1 gt Dd synth_2 Part 5vlx30 5vlx30 5vlx30 Constraints Strategy Status Progress Start Elapsed Util FMax MHz Timing Score Unrouted Description XST Defaults XST 11 XST Complete a 100 12 31 08 9 30 AM 00 00 21 0 000 186 776 XST Defaults ISE Defaults ISE 11 PAR Complete HEHEHEHEHE 100 1 4 09 10 12AM 00 01 37 0 ISE Defaults incl XST Defaults XST 11 Running XST 2 0 1 4 09 10 24AM 00 00 03 XST Defaults Figure 7 15 Design Runs View The view displays the status and results of the Runs defined as well as provides commands to modify import launch and manage the Runs This same view is also used to manage and report synthesis and implementation runs The view indicates the runs currently running with a green arrow icon as seen above on the left Completed Runs receive a blue check mark icon Run information is displayed as the commands are being run PlanAhead can be closed without affecting runs in progress When the Project is re opened the Run status is updated to reflect the latest status which is displayed in the Design runs chart Columns that are used for tracking information are as follows Run Name Displays run name Target Part lIndicates the target part selected for the run Constraint file Displays either the constraint fi
178. ayed for the type of Project being opened or created PinAhead HDL Sources or PlanAhead with a synthesized netlist To open a Project in PlanAhead use one of the following methods e Select File gt Open Project e Click the Open Project toolbar button B Figure 2 27 Open Project Toolbar Button e Click the Open a Previously Created Project link in the Getting Started jump page The Open Project browser is displayed Select a PPR project file to open G Open Project Lookin project_1 A iY project_1 ppr My Recent Documents Desktop My Documents 3 My Computer L J D File name project_1 ppr E My Network Places Files of type Planahead Project File ppr i Figure 2 28 Open Project Dialog Box Opening Multiple Projects Multiple Projects can be opened simultaneously in a single PlanAhead session by using any of the methods described above in the Opening Existing Projects section of this chapter A separate PlanAhead main window will appear for each opened project Some window focus issues may present themselves with multiple projects opened simultaneously System memory requirements may hinder performance when opening multiple projects You can monitor the Java memory consumption status bar at the button right corner of the PlanAhead environment window PlanAhead has a preset Java memory limit 512MB on Windows and 1GB on 64 bit Linux If you get close to that number you
179. bal Clock Rules Rule Name Rule Abbrev Rule Intent Severity Clock Region CRPS Only one of the primary secondary pair Error Primary clocks have access to any one quadrant via Secondary global clock routing resources If these two clocks drive clock inputs in the same quadrant the nets will not be routable using the global clock routing resources Spartan 3 devices Note f the Pblock spans more than one clock region the error reported may not be an issue for the ISE software to place the logic in the appropriate clock regions with the Pblock IBUFG to DCM IDCM IBUFGs have dedicated routing only to all Warning connectivity DCMs on the same edge top bottom left right of the device DCM to BUFG DCMB DCM can connect to a maximum of four Error connectivity BUFGs There are pairs of buffers with shared dedicated routing resources such that if both are driven by the same DCM one of the two will necessarily be driven using non dedicated routing resources this causes the design to fail If the buffers are numbered 1 through 8 from left to right there are four pairs of exclusives 1 5 2 6 3 7 4 8 If a buffer is placed in Site 1 another driven by the same DCM should not be placed in Site 5 Numter of DCMN DCM can connect only up to 4 BUFGs Thisis Error BUFGs allowed related to DCMB for DCM DCM and DCME BUFGs have dedicated routing only to all Warning BUFG DCMs on the same edge top bott
180. box will display www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Interfacing with ISE Outside of PlanAhead Import Placement File name ig_fp_16nsrun_1FPGA_RCY_802_11_routed xdl Floorplan floorplan_1 Import placement results for Netlist FPGA_RCY_802_11 Instance J Pblock Description Q Names in the placement results file are fully hierarchical Figure 7 41 Import Placement Dialog Box 2 View and edit the definable fields are available in the Import Placement dialog box File Name Click the browse button to locate and select either the XDL format file or the lt design_name_routed gt ncd file If the NCD format file is selected PlanAhead will automatically convert it to XDL format and import the XDL result file Import placement results for Selects the level of the design to import placement for This command is seeded with pre selected objects so carefully select the proper level of the design Netlist lt netlist name gt Select this option when importing a top level XDL This is typically the case when running ISE on the top level design Instance Select this option to import placement results for a selected logic instance The dialog box can be seeded with a pre selected instance prior to running the command This option is useful when importing block level placement constraints Pblock
181. by Name ID number or Type by clicking on the banner of the desired sort column Selected items can be removed from the Selection list by using the Unselect Unselect All or Unselect All Except command from the popup menu Groups of objects may be selected by using the Ctrl and Shift keys The total number of objects selected is displayed in the view banner Id Name R Unselect All Unselect All Except um Properties Ye Figure 4 19 Selection View Popup Menu Commands Highlighting Selected Objects You can highlight objects with color for display purposes Highlighting remains until you clear all highlights for the floorplan For more information on highlighting see e Highlighting Selected Objects e Using the Select Primitives and Highlight Primitives Commands Marking Selected Objects You can place a Mark symbol for all selected objects For more information see Marking Selected Objects Setting Selection Rules When selecting an object other objects may also become selected e g selecting a Pblock also selects the assigned netlist instances Selection behavior is controlled with selection rules set by selecting Tools gt Options gt Selection Rules 110 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX The Selection Rules dialog box displays Understanding Object Selection Options G PlanAhead Options Text Editor Zi Selection Rules
182. c cece eee eens 83 I O Pin Planning View Layout 0 0000s 83 Design Analysis and Floorplanning View Layout 00 0 00000 85 Transitioning from PACE Floorplan Editor to PlanAhead 86 Overview cccteasgedsneanw Riese nage cat gechi eye Re E reo aseaeedod nes aa 86 Launch and Invocation of PlanAhead from Project Navigator 86 Launch and Invocation of Standalone PlanAhead 0 e eee eee eee 87 Empty Design amp Pre Synthesis I O Pin Planning 00sec eee eee 87 Post Synthesis Pin Planning and Area based Floorplanning 88 General I O Pin Planning and Floorplanning Tasks 060 cece eee 89 Viewing ISE Implementation Results 0 0 000 c eee eee eee eee 90 MATIN ANY 5 stag so ota dest E E ek races ace des dune bine ge ee 90 Transitioning from Floorplanner to PlanAhead 04 90 Launch and Invocation of PlanAhead from Project Navigator 91 Launch and Invocation of Standalone PlanAhead 0 0 00 e ee eee eee 91 General Floorplanning Tasks 0 2 6c eee ees 91 Timing Analysis Path Visualization 0 00 c cece eee cece cece eee 92 Viewing ISE Implementation Results 0 000 c cee 93 SUMMATY eriei tetas e belted Red oe ripy ieo DiE E AE E EE 93 Chapter 4 Using the Viewing Environment The Viewing Environment 0 5 0 c cece eect eee ees
183. cable to wire bond packaging While PlanAhead does not provide a graphical view of package flight time display trace length values are available in the properties for each IO pin Select a pin and view the Package Pin view table www xilinx com 89 Chapter 3 Using PlanAhead With Project Navigator g XILINX Area Based Floorplanning e Much like PACE and Floorplan Editor you can create an area based floorplan using PlanAhead In the PlanAhead terminology this is called creating physical blocks or PBlocks Simply select a group of hierarchy from the Netlist view and use the Draw PBlock right click menu command or use the Draw PBlock toolbar button You can now draw a rectangular region in the device view which will assign the selected block of logic to the drawn site range on the Device view e PlanAhead will ensure the drawn regions are capable of fitting the logic in that block It accounts for logic utilization carry chain height and RPM footprints if applicable More information on creating and manipulating area based PBlocks can be found in Chapter 10 Floorplanning the Design Saving the New Constraints in a UCF File Just as with PACE and Floorplan Editor the main output of the pin planning and floorplanning task is a UCF file Once the project is saved the UCF file can be used in exactly the same manner as if it had been generated with the previous tools Viewing ISE Implementation Results PlanAhead can import
184. cations to shortcuts in the copied schema can be made using the bottom portion of the dialog box You can search through the list of views and select commands to enter new shortcuts Select the Add Shortcut button and type in the new desired shortcut in the Add Shortcut dialog box Click OK to accept the new shortcut Commands listed for shortcut assignment can be filtered using the Filter field containing field Enter any text string to filter the list of available commands Different shortcuts can be used for the same command in different views All user specific shortcut schemas are saved to e C Documents and Settings lt Username gt Application Data HDI shortcuts Windows e HDI shortcuts Linux To delete shortcuts click the Remove button Setting General PlanAhead Options Selecting the Tools gt Options gt General tab will invoke the PlanAhead Options dialog box Note The Office 2003 Look and Feel options are not available to Linux users PlanAhead User Guide www xilinx com 119 UG632 v 11 4 Chapter 4 Using the Viewing Environment g XILINX G PlanAhead Options Look and Feel nonna il Style Office 2003 w Theme Default v Warning Dialogs Selection Rules ATP D 7 g Show warning dialog before closing a Floorplan Shortcuts Show warning dialog before closing a project Show warning dialog before upgrading an old project 2 Show dialog before adding net Fo
185. ceive an AREA_GROUP property for ISE with no RANGE defined ISE uses the AREA_GROUP property to attempt to group the logic and to prevent it from being placed in other AREA_GROUP ranges Creating Multiple Pblocks with the Create Pblocks Command Multiple Pblocks can be created in a semi automated way by using the Create Pblocks wizard The wizard will create a separate Pblock for each selected netlist instance To use the wizard pre select a set of instances for inclusion into individual Pblocks To create multiple Pblocks for specific netlist instances 1 Select the instances to include in a Pblock 2 Select Tools gt Create Pblocks The Create Pblocks wizard will appear A list of the selected instances is displayed 290 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Partitioning the Design by Creating Pblocks G Create Pblocks Create Pblock s from the following instances Instances 5 Id Name Cell Primitives a 1 cpuEngine cpu_dwb_dat_i FifoBuffer a 2 cpuEngine cpu_dwb_dat_o FifoBuffer E7 3 cpuEngine cpu_dbg_dat_i FifoBuffer B 4 cpuEngine cpu_dbg_dat_o FifoBuffer E 5 cpuEngine cpu_iwb_adr_o FifoBuffer Cer Figure 10 4 Create Pblocks Wizard Create Pblocks from Instances 3 To add additional netlist instances to this list click the Add button to invoke a browser in which you can select other instances To remove any netlist instances from the list click the Remove button
186. ck if they are default values black with an asterisk for non default values and red when they are illegal or undefined values Ports can be selected and grouped together into Interfaces by selecting the Create I O Port Interface popup menu command These Interfaces can be selected and placed as one object within the PinAhead environment Busses are displayed as folders in the view Each folder is a group of bus signals Ports and Interfaces can be selected from the I O Ports view and assigned using the PinAhead environment Package Pins View The Package Pins view displays device package pin information Information about the device pins is displayed in table form To invoke the Package Pins view select Window gt Package Pins Name S E All Pins 324 Ham I O Bank 0 4 Sam I O Bank 2 22 P T8 D7 SP R15 SD T16 D RI D T9 B Console 130 H a I O Bank 1 22 Prohibit Port I OStd Dir cco Bank Type Diff Pair Clock Voltage Low Cap Min T 2 User IO LOP ae False 2 User IO LON GG False 2 User IO L1P fae False 2 User IO LIN ce False 2 User IO L2P false 2 User IO L2N false Figure 5 4 Package Pins View The view can be toggled to display pins according to category by I O bank or displays the pins alphabetically by clicking the Group by I O Bank toolbar button in the Package Pins view Al Figure 5 5 Group by I O Bank Toolbar Button Device pin information such as I O Bank number Type Differential pai
187. ckage bE Figure 10 40 Zoomed Out Device View Z Show Hide LOC Constraints Toolbar Button To display or hide the location constraints click the Show Hide LOC Constraints toolbar button Figure 10 41 317 www xilinx com PlanAhead User Guide UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX To adjust other display characteristics for the LOC and BEL constraints 1 Select Tools gt Options gt Themes gt Device The Device dialog box displays 2 Adjust values under the Constraint object To adjust the display of the device resource grid sites select Tools gt Options gt Themes gt Device and in the Device dialog box toggle values under the Site object Fixed and unfixed placement constraints have individual color and selection controls Viewing Logic Connectivity using Show Connectivity Mode When placement constraints are visible net connectivity is displayed to the individual placement constraint locations When placement constraints are not visible net connectivity is displayed to the center of the logic instance within the Pblock To display connectivity for a selected logic instance or group of instances select one of the following commands e The Show Connectivity popup command e The Show connections for selected instances Mode toolbar button Figure 10 42 Show connections for selected instances Mode Toolbar Button The Show connections for selected instances mode wi
188. com 357 XILINX Using resource utilization statistics to size Pblocks 307 Using the automatic Pblock com mands 311 Running the Partitioner 311 Running the Pblock Placer 313 G Getting Started 36 Glossary of terms 32 H HDL Editor 171 HDL format header See PinAhead Hierarchy view 236 Highlighting objects Highlighting Primitives 280 Unhighlighting objects 280 I O nets See Connectivity I O pin planning See PinAhead I O Ports view 129 Implementation 185 ChipScope flow 340 Interfacing with ISE 214 Importing ISE placementresults 216 Importing ISE TRCE results 217 Pblocks 194 Runs 191 195 Importing ISE results for Run 207 On Multiple Linux Hosts 211 355 Running Bitgen on Run 208 Strategies 185 209 Creating common group strate gies 211 Creating Strategies 209 Modifying ISE command op tions 211 Importing Constraints 328 I O Ports 136 Input files 21 Instance Hierarchy view 236 IP Reuse 325 ISE Implementation 214 Placement and Timing Results 273 ISE integration See Project Navigator in tegration L Launching PlanAhead 35 Layout Default layout 123 Load layout 123 PinAhead Cockpit 83 PlanAhead Default 85 Saving custom layouts 122 M Make Part Compatible 134 Marking objects 110 281 Removing marks 282 Metrics view 282 Configuring Metric ranges 285 Displaying Metrics in the Device view 283 Hiding Metrics map display 284 Using the Metrics Results table 2
189. cons in the upper left corner of the Device view These view specific Toolbar commands are covered in Using Common Popup Menu Commands page 251 Printing the Package View You can print the Package view using the File gt Print command The current viewable area is printed To print the entire Package view zoom to fit and then print Using the Device View The I O Pad Banks and Clock related resources are displayed in the Device view Users can cross select I O resources in the any of the PinAhead views to view the relationship between the physical package pins and the internal die resources For more information see Using the Device View in Chapter 8 Viewing Device Resources Viewing Package Pin Properties Pins or I O banks can be selected in the Package view and corresponding details are displayed in the Properties view Select an object in the Package view and view the details in the Properties view as shown in Figure 5 9 page 133 132 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Viewing Device Resources Package Pin Properties Oo g x gt x JIE D15 Name D15 Type User IO Bank IO Bank 5 Site type IO LOP 5 Trace length 12685 IOB alias IOB_X1 319 Figure 5 9 Package Pin Properties Viewing I O Bank Resources I O resources can be selected in any of the PinAhead views and their corresponding data is highlighted in all other
190. constraint or group of constraints in the Constraints view and select Delete from the popup menu You will be prompted to remove the selected constraint s prior to the removal of the constraint Note Due to the interdependence between timing constraints removing one constraint may result in the removal of several other related constraints Note Adding editing and deleting timing constraints cannot be undone Using the Physical Hierarchy View PlanAhead User Guide UG632 v 11 4 The Physical Hierarchy view displays the hierarchical partitioning structure of the design Physical design navigation is performed by expanding and collapsing the tree widget elements Tree elements can be selected and commands applied to them using the menu toolbar or context sensitive menu mouse popup menu Press Ctrl or Shift keys to select multiple elements for use with some commands The physical hierarchy tree is dynamic and will automatically expand and change when physical hierarchy is manipulated As objects are selected in other views the appropriate elements are highlighted in the Physical Hierarchy view The objects displayed in the Physical Hierarchy view are Relatively Placed Macros RPMs and Physical Block Pblocks These objects may be selected in the Physical Hierarchy view for manipulation in other views www xilinx com 247 Chapter 8 Analyzing the Design g XILINX Using the ROOT Design Pblock The physical hierarchy begins w
191. cores are initially created in the PlanAhead tool as black boxes These cores must be implemented prior to running through map place and route ChipScope debug core implementation is automatic when running the implementation flow using Tools gt Run Implementation However you can manually force debug core implementation for floorplanning or timing analysis by clicking the Implement toolbar button on the left side of the ChipScope view The Xilinx CORE Generator tool will be invoked in batch mode for each black box debug core This operation may take some time A progress dialog will indicate the operation is running Figure 11 14 When debug core implementation is complete the debug core black boxes are resolved and you may push inside the generated instances Implement Debug Core Progress W Invoking COREGen for u_icon cance Figure 11 14 Debug Core Implementation Progress Indicator PlanAhead User Guide www xilinx com 339 UG632 v 11 4 Chapter 11 Debugging the Design with ChipScope g XILINX Exporting Net Connections CDC File for ChipScope Analyzer Tool A ChipScope Analyzer CDC file is automatically generated when design implementation is complete You may also manually export a CDC file from the Export Debug Net Names popup command in the ChipScope view This CDC file may be imported into the ChipScope Analyzer to automatically set up the net names on the ILA core data and trigger ports Implementing the De
192. cpu_iwb_adr_o usbEngineO usb_out cpuEngine cpu_dwb_dat_i cpuEngine cpu_dwb_dat_o Figure 10 32 Auto create Pblocks Dialog Box 2 View and edit the definable options in the Auto create Pblocks dialog box Pblock to partition Select the partition level It can either be the top level Pblock ROOT or any other pre selected Pblocks Note PlanAhead partitions are not related to ISE partitions The PlanAhead partition command does not create ISE partitions Maximum number of Pblocks to generate This instructs the Auto create Pblocks command to create no more Pblocks than the number set If the number of modules exceeds the number set the largest lt number set gt of Pblocks will be created Process instances with instance count of at least This instructs the command to not create Pblocks with a number of instances less than the number set Preview Displays the Pblocks that will be created 3 Click OK to automatically crate the Pblocks in the design Pblocks are automatically created and named accordingly for each of the top level Netlist modules as shown in the following figure No rectangles are created yet 312 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Automatic Pblock Commands Netlist ogg x TS z id 3 Floorplan_1 top a 3 ROOT a Nets 473 F amm block_cpuEngine_cpu_dbg_dat_i E Primitives 304 E pblock
193. creation To export the I O Ports list information select the File gt Export I O Ports command Gi Export 1 0 Ports Specify Types to Generate csv C Data Plan4head_Designs Plan4head_Tutorial labs projects project_ 7 floorplan_1 csv UCF C Data Plandhead_Designs Planahead_Tutorialilabs projects project_7ifloorplan_1 suc Verilog C Data PlanShead_Designs Plan4head_Tutorial labs projects project_7 netlist_1_EMPTY vf e C Data Plan4head_Designs Plan4head_Tutorial labs projects project_7 netlist_1_EMPTY vhdl Figure 5 42 Exporting I O Port Lists 164 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 6 Creating and Analyzing the RTL Design The PlanAhead software Project environment enables you to create and manage RTL design files Included in PlanAhead is basic source file management an RTL Editor an RTL schematic viewer a set of RTL DRCs and a resource estimator Logic synthesis and implementation can then be run using PlanAhead For more information about running synthesis and implementation refer to Chapter 7 Implementing a Design This chapter contains the following sections e Using the Project Environment e Adding Sources to the Project e Using the RTL Editor e Elaborating and Analyzing the RTL Design Using the Project Environment The Project environment is used to import develop and elaborate the RTL source fil
194. ct Data Directory lt projectname gt data The Project Data Directory stores all of the Floorplan and netlist related data contained in the Project These folders are maintained by PlanAhead and do not require your attention Caution Modifying any of these files could result in Project data corruption Project Data Netlist Subdirectory netlist A subdirectory called netlist contains a copy of the netlist files for the entire design For RTL based Projects a subdirectory for each synthesis run is created containing the netlist produced It is refreshed each time the synthesis run is reset For netlist based Projects as single netlist directory is created containing the imported netlist including copies of all NGC core files used in the design The File gt Update Netlist command can be used to update the contents of this subdirectory Project Data Floorplan Subdirectories and Files lt floorplan_name gt As Floorplans are created matching subdirectories are created under the lt projectname gt data directory The files found in the Floorplan directory are listed below e ucf Allimported UCF file names may differ from input files e fp ucf Contains current PlanAhead constraints for the Floorplan e iseloc xml Used to differentiate the PlanAhead fixed placement constraints from the unfixed placement constraints imported from ISE e pfi xml Contains target device for Floorplan e pfp xml Contains current PlanAhead e
195. ctangles within a SLICE logic symbols are displayed PlanAhead User Guide ni Figure 8 3 Place Instance as Rectangles in the Device View www xilinx com At the zoom level shown above When the zoom level increases 224 XILINX Nii g eeso i ig g a Eele t zl e i a x a Ld T i T I a a HU FECRRRR Using the Floorplanning Environment oy ela boo oo pol Fo OG pY Ez y Ez 9v REP EE E eee OE E HA Ca ee a a a a A ES EEE Oe we e fi Package Device x Figure 8 4 Logic Symbols in the Device View gt e e Logic can be assigned to specific sites which will generate LOC placement constraints They can be assigned to a SLICE or to specific gates using BEL level constraints All logic imported from ISE is displayed as BEL level constraints For more information about LOC placement constraints see Working with Placement LOC Constraints page 315 Displaying Clock Regions The clock regions are displayed as large rectangles indicating the periphery of the various device clock regions These outlines can be used to help guide floorplanning for critical circuitry The Clock Regions view can be used to select the various clock regions Select the Window gt Clock Regions command to invoke the Clock Regions view Clock regions can be selected and their
196. d Click the Hide Warning and Information Messages toolbar button to hide all warnings and info messages and view only errors Click the toolbar button again to view all errors and warnings once again Figure 5 35 Hide Warning and Information Messages Button Select an error in the DRC Results view list and the specific violation information is displayed in the Properties view Select a blue link in the Properties view to highlight the violating design elements in the Device view Netlist view and Schematic view Violations will no longer be displayed in the DRC Results view after the error condition is rectified and DRC is rerun Each time the Run DRC command is run and errors are detected anew results tab is added to the DRC Results view A separate results output file is also created in the PlanAhead invocation directory www xilinx com 153 Chapter 5 VO Pin Planning 154 I O Port and Clock Logic DRC Rule Descriptions XILINX The following tables describe the various DRC rules rule intent and severity Note Other DRC rule descriptions are found in DRC Rule Descriptions in Chapter 8 e Global Clock Rules e IOB Rules e Bank I O Standard Rules Note The I O Port and Clock Logic DRCs available in PlanAhead is not an exhaustive list of I O related DRCs Consult the device documentation for more information on I O ports and clock region specifications Global Clock Rules Table 5 1 Glo
197. d as fixed and locked during subsequent ISE attempts Before assigning instances toggle the Create BEL Constraint Mode toolbar button on to initiate the Create BEL constraint mode g Figure 10 38 Create BEL Constraint Mode Toolbar Button The dynamic cursor will not allow instance placement to an illegal or already occupied gate sites A legal placement site is indicated when the dynamic cursor changes from a slashed circle to an arrow The dynamic cursor does not allow instances to be placed if the SLICE will be over packed with logic www xilinx com PlanAhead User Guide UG632 v 11 4 Working with Placement LOC Constraints XILINX After location constraint assignment is complete return to the default Assign instance to Pblock mode by clicking the Assign Instance Mode toolbar button Figure 10 39 Assign Instance Mode Toolbar Button To view location constraint properties select the placement constraint and view the Instance Property view Adjusting the Visibility of Placement Constraints Adjust the zoom level to change how assigned placement constraints are displayed From a zoomed out vie w the LOCs and BELs are displayed as a filled in rectangle inside the o m0m oojoo Oooo o o o jo o D assigned site When the zoom level increases the logic is displayed as being assigned to specific logic gates within the site n7900 g0 aie IHLE E oogoprogdmroporogjoooog m F Pa
198. d eS ho ad eRe DECRG Oye Bek se RE ee BAS 343 Window Menu 0 cc eee ce nee ence tn een ene nent n eens 344 Select Men is 00 46a0 scubsbdans debe dres ehee dees ert een a eases 345 Thayout Meninas cena bile atten teat E E E Pine ath a cess aves oa a 346 Help Menu vss dive aiics tee ete a ee ek Bite SR oe ae dee Wace ae wa 347 UG632 v 11 4 www xilinx com PlanAhead User Guide Toolbar Commands 0 cece cece cece eee ene nneeeee beens 347 Appendix B Installing Releases with XilinxUpdate PlanAhead Release Siratepy iss sicpsiibidinsici yinteein ti eiieie wietee xe 351 Running XilinxUpdate naana nanan nerra Geni ueeeeewegonenienwhs 351 Automatically Checking for Updates 0 0 02 raana 352 Appendix C Configuring SSH Without Password Prompting Setting Up SSH Key Agent Forward unssauussnnunrrnnrrr rnnr 355 UG632 v 11 4 www xilinx com PlanAhead User Guide XILINX Chapter 1 Understanding the PlanAhead Design Flow This chapter contains the following sections e PlanAhead Design Flows e Input and Output Files e PlanAhead Terminology PlanAhead Design Flows The PlanAhead software can be used in various ways at different points in the FPGA design flow It can be used as a complete flow management tool from RTL development through bitstream generation or for I O pin planning RTL netlist analysis implementation result design analysis floor
199. d relies heavily on logic hierarchy for floorplanning Imported netlists must contain logic hierarchy Flat netlists are very difficult to floorplan Ensure that designs are coded in RTL and synthesized hierarchically Note Importing either top level or module level NGC or NGO format files requires the use of the nge2edif command to create EDIF files for PlaanAhead The status of the nge2edif commands is displayed in the PlanAhead Terminal window as the commands are running Selecting a Product Family Default Part and Floorplan Name The next page in the New Project wizard prompts you to select a product family and default part PlanAhead User Guide www xilinx com 49 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX 50 New Project Choose a Part and a Floorplan Name Enter a name for your floorplan and choose a Xilinx device Product Family VirtexS Choose Part xcSvlxS0ff324 1 Floorplan name floorplan_1 Figure 2 17 New Project Wizard Product Family and Default Part Page 3 View and edit the definable options Product Family Displays the device to be used Only compatible devices can be selected here Choose Part Use the device browser to select a desired device or accept the default to use the entry defined in the top level EDIF netlist file Floorplan name Enter the desired name for the Floorplan 4 Click Next Note Once a Product Family is selected for a Project i
200. d stored in HDI strategies Outputs for Project Data This section briefly describes the files created for saved PlanAhead Projects and Floorplans These files are maintained by PlanAhead and should not be modified manually The project output files are as follows e Project Directory lt projectname gt e Project File lt projectname gt ppr e Project Data Directory lt projectname gt data e Project Data Netlist Subdirectory netlist e Project Data Floorplan Subdirectories and Files lt floorplan_name gt e Project RTL Directory lt projectname gt srcs Project Directory lt projectname gt When a new Project is created PlanAhead creates a Project directory to store the Project File the Project data directory and the ISE implementation results The Project directory has the same name as the Project name entered in the New Project Wizard PlanAhead User Guide www xilinx com 27 UG632 v 11 4 Chapter 1 Understanding the PlanAhead Design Flow g XILINX Project File lt projectname gt ppr The Project PPR file stores the state of the Project It contains information about the netlist and the various Floorplans contained in the Project The file is continuously maintained while PlanAhead is invoked It does not require saving This file should not be edited manually The PPR file is the item selected in the PlanAhead browser when opening an existing Project Proje
201. dditions to PlanAhead in the 11 release You can now import RTL sources synthesize the logic implement the synthesized netlist analyze the implementation results floorplan and experiment with implementation options and generate bitstreams It is going a long way toward providing a comprehensive front to back design environment and solution PlanAhead manages the design flow and data to accommodate experimentation with multiple synthesis and implementation runs simultaneously Previously PlanAhead projects consisted of a single imported netlist You could create multiple floorplans for experimentation which were basically constraint sets that all leveraged that single version of the netlist Creation of a floorplan was always required and the netlist was always loaded into memory during a PlanAhead session Basic Design Flow The basic flow enables users to easily import RTL sources synthesize and implement the design and view results It is often used to implement the design initially If further design analysis and floorplanning is desired the design analysis flow should be used Run Experimentation Flow You can experiment with multiple synthesis or implementation runs using different strategies A set of proven PlanAhead strategies is shipped with the tool or you can define your own 20 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Input and Output Files The PlanAhead synthesis and implementation environment
202. description of the timing of logic some behavioral requirement or a physical placement requirement I O Port assignments are also defined by constraints Physical Block Pblock Design partitions are referred to as physical blocks or Pblocks Traditionally a single or group of logic instances are assigned to a Pblock The Pblock can have an area such as a rectangle defined on the FPGA device to constrain the logic Pblocks can be defined without rectangles and ISE will attempt to group the logic during placement Netlist logic placed inside of Pblocks will receive AREA_GROUP constraints for ISE Pblocks may be specified with specific RANGE types to contain various types of logic only e g SLICE RAM MULF DSP etc Pblocks may also be defined with multiple rectangles to enable non rectangular shapes to be created such as L shaped and T shaped Instance Elements in the Netlist referred to as instances include leaf level logic primitives and hierarchical module components The module components are referred to as modules in this document Module Elements in the netlist that represent hierarchical module instantiations are referred to as modules or components Leaf level primitive logic is referred to as instances or primitives Primitive Elements in the netlist that represent leaf level logic objects are referred to as primitives e g LUTs Flip Flops etc Run Each synthesis or implementation attempt is called a
203. diiak esd peso dae d eee eee desea bee 324 Using IP Reuse Capabilities 0 0 0 c eee eee 325 IP Reuse Overview ssir r r trar ECAA EAE Stare EEI E EEA dele EENS 325 Creating and Reusing an IP Module 0 00 00 325 Duplicating Placement for Identical Modules 00000000000 ee 328 Chapter 11 Debugging the Design with ChipScope Overview of ChipScope Integration in PlanAhead 329 Requirements and Limitations When Using Core Insertion Flow 330 Using the Core Insertion FIOW 1 3505 o i0ede icy ieee vueeesdesaydiwiewes cess 330 Deciding Which Debug Core Insertion Mode to Use 0000 0s eee 331 Selecting Nets for Debug sss ccie4ccigecienecieed anaiai aa ne aed ede eee nies 331 ChipScope Wizard based Debug Core Insertion 00000 c ee eee eee 332 Using the ChipScope Window to Add and Customize Debug Cores 334 Implementing the Design 51 4 iciidescis sting chap eee a ese eeker gen BoA 340 Invoking the ChipScope Analyzer 0 00 0 c cece cee eee eee 340 Appendix A Menu and Toolbar Commands Main Menu Commands 000 0000 c cette eet aeaaee 341 Fil M nitlss s lt s003 04093 2505 iA 3 004 Lb hss eee he oa ES Rakes 341 Edit Ment 05ni2g0areuedsisints beta aaheenr a ot gdns aan eens a a 342 View Menthe ss cei sco eaten kauteee Gadde EEE os E EEN ee hee ead eRe eB 343 TOOlS Men tis s amp dss baie tee eS Ba Yaa
204. displayed in the Properties view To view and edit the properties for a Floorplan 1 Select the Floorplan e g fp1_16ns in the Physical Hierarchy view The Floorplan Properties view will appear PlanAhead User Guide www xilinx com 73 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX floorplan _2 xc4vlx40ff668 10 General Part Compatibility Constraint Files Attributes _ Selection E Floorplans Figure 2 43 Floorplan Properties General Tab 2 Inthe Floorplan Properties window enter a new name in the Name field to identify the Floorplan in this project e g floorplan_2 3 Click Apply to implement any changes entered Note The Cancel button will discard any changes 4 Click the Part Compatibility tab This tab displays the parts selected to be compatible for I O pin planning purposes Parts can be added and removed from the list using the dialog box icon commands Refer to the Defining Alternate Compatible Parts for more information bp xc5vix50ff324 x General Part Compatibility Constraint Files Attributes Selection Figure 2 44 Floorplan Properties Part Compatibility Tab 5 Click the Constraints Files tab This tab displays a list of imported UCF constraint files in the non editable dialog box 74 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Working with Floorplans gt B x aff
205. dual blocks or for the entire design www xilinx com 23 24 Chapter 1 Understanding the PlanAhead Design Flow g XILINX When using the Import Placement command PlanAhead will automatically run the XDL command when a lt placed_design_name gt ncd file is selected in the Import Placement dialog box To run the command by hand the file syntax is detailed below xdl ncd2xdl lt placed_design_name gt ncd Running this command will result in creation of a lt placed_design_name gt xd 1 file The XDL command status is displayed in the PlanAhead Terminal window Xilinx TRCE Timing Results TWX TWR PlanAhead can import the timing report generated by the Xilinx tree command This includes TWX and TWR files Once imported all signal tracing and selection is available through the TimeAhead interface Outputs for Reports This section briefly describes the files created during normal PlanAhead design operations These files can contain valuable information and are described here The last two reports are not automatically generated and require user interaction to create The output log and report files are as follows e T O Pin Assignment CSV e I O Pin Assignment RTL Verilog or VHDL e Log File planAhead log e Journal File planAhead jou e Error Log Files planAhead_pidxxxx debug amp hs_err_pidxxxx log e DRC Results results_x_dre txt e TimeAhead Results Excel file e
206. e and click Next If you select I O ports that have already been assigned to package pins the following dialog box opens Autoplace I O Ports Placed I O Ports 3 of the 92 ports you are about to place already are assigned to package pins How do you want to treat these ports Keep these 3 ports in their current locations Find new locations for these 3 ports Figure 5 28 Autoplace I O Ports Wizard 4 Select the I O ports to place and click Next 5 Click Finish in the Summary page to place the selected I O ports PlanAhead User Guide www xilinx com 147 UG632 v 11 4 Chapter 5 VO Pin Planning g XILINX Placing Gigabit Transceiver I O Ports To better manage Gigabit Transceivers GTs PinAhead groups the two related I O diff pairs and the GT logic object automatically during selection placement and moving The GT objects get selected as one object and move together which prohibits illegal assignment of the GT resources The noise sensitive I O pins surrounding the GTs are prohibited automatically during port placement if the online DRCs are enabled Refer to Enabling Interactive Design Rule Checking Placing I O Related Clock Logic Instance Properties gt x aff Global and regional clock related logic such as BUFGs DCMs BUFRs DelayCtrls etc can be manually placed in the Device view Appropriate logic sites are displayed for all device specific resources Select Edit gt
207. e constraints to a UCF file for further processing by the ISE implementation tools The above set of tasks are those that most directly correspond to the early pin planning tasks as would be done using PACE or Floorplan Editor For further details on any of the tasks described above or the broader set of pin planning capabilities within PlanAhead see Chapter 5 I O Pin Planning Post Synthesis Pin Planning and Area based Floorplanning In this mode you have synthesized netlist EDIF or NGC file and possibly a pre existing UCF file These are the minimum set of input files that PlanAhead requires to work in this mode When PlanAhead is invoked in the post synthesis mode a larger set of features within PlanAhead s environment is available for you to use For the purposes of this document the tasks that are most applicable for transitioning from PACE or Floorplan Editor include e Pin assignment with the full set of PlanAhead s robust DRCs This includes clocking rules IO placement checks etc Since this more complete set of functionality is available in the post synthesis mode we recommend working from this mode when possible DRC can be invoked with the File gt Run DRC For a full description of the IO DRCs within PlanAhead see Chapter 5 I O Pin Planning e PlanAhead also has fully featured set of tools to accomplished area based floorplanning of your design Just as with PACE or Floorplan Editor you can map hierarchic
208. e planAhead jou file in the PlanAhead invocation directory Using the World View The World view located at the bottom right corner displays a less detailed overview of the active Workspace view To invoke the World View if hidden select Window gt World World Od x Figure 4 13 World View The World View will reflect the zoom area and selected objects for the active view for the Schematic Device Package and Hierarchy Views A navigation rectangle displays the area that is visible in the active view The navigation rectangle can be dragged to reposition the display area in the active view The navigation rectangle can also be resized by dragging one of the resize handlers This adjusts the active view scale factor i e zoom in or zoom out to match the new display area defined by the navigation rectangle Selected Pblocks instances and I O Ports are highlighted in the World view for easier location www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using Common Environment Views Using the Status Bar The status bar at bottom of the PlanAhead Desktop displays useful information N vga_color_bars_inst CLOCKGEN MAIN_DCM DCM_ADV_XO 1 Post Synthesis Flow 87M of 162M mi Figure 4 14 Status Bar The parts of the status bar are defined and described below Status Mode Field The left side of the status bar shows an icon representing the current mode The default mode is the select mode i
209. e run on either a single module or multiple selected modules These commands are available from the right click popup menu or from the Schematic view toolbar buttons 230 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Floorplanning Environment Table 8 1 Schematic View Toolbar Toolbar Button Command Description am Expand all logic Expands all logic inside selected instance a inside selected instance Collapse all Collapses all logic inside selected instance logic inside selected instance rah pa Expand all logic Expands all logic outside selected instance p a outside selected instance Collapse all Collapses all logic outside selected logic outside instance selected instance The commands are intended to display all logic associated within a level of hierarchy as shown in the example below in which the Expand Inside command is used receiver RChainTop inst equacalAinst RAM bitREV EQUAL cxMULT_BRE muit12b_RE1_RE2 reTMP 0 axb 28 BUTS BUSI r o a gt ShreTMP_O_cry 23 0 yreTMPos24 feTMPl24 BUF DIJ Lo Da MULTISXIS al lt I mult 2b_HO25 ROBEY MUX Y_L FOR oxMULT_12_12_10_RChainTop bitRev_Equal_12 RAMB16_S30_S36 ARH ORAA IR D ee equa Cal AF FT RChainTop RCV S021 Figure 8 12 Displaying All Logic Within a Level of Hierarchy Traversing the Schematic Hierarchy Double clicking on a hiera
210. e E Primitive Statistics Primitive type Count LUT 4558 FD_LD 2481 MUXFX 184 CARRY 993 BMEM 28 MULT 4 OTHERS 67 Net Boundary Statistics Boundary crossing Nets 202 Clock Report Domain Module Resource Instances cpuClk_cf top Global 2430 wbclk_cf top Global 113 Carry Statistics Number of carry chains Longest chain 26 cpuEngine dwb_biu retry_cntr_cry 0 I ae ree Ee de Pe Reet General Statistics Pins Children Attributes Connectivity Selection Figure 8 43 Netlist Resource Statistics Exporting Hierarchical Design Resource Statistics You can save the displayed data to an spreadsheet file PlanAhead enables a hierarchical style report to be generated You can define how many levels of hierarchy to report with estimates listed for each module at each level 1 Select the Export Statistics button to export the data to a spreadsheet file Figure 8 44 Export Statistics Toolbar Button The Export Netlist Statistics dialog box appears PlanAhead User Guide www xilinx com 257 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX G Export Netlist Statistics Netlist BI top File Name 2signs v4_color_design projects project_adder top_stats xls oe Format Spreadsheet XML Levels 1 x Reports to Generate Primitive Statistics Clock Report C Carry Statistics C Net Boundary Statistics Figure 8 45 Export Netlist
211. e IP blocks The Export IP command is run ona selected netlist hierarchy in the design A RPM can also be produced as output for the IP module The exported files will include the EDIF netlist and UCF physical constraints written in the original logical netlist format This allows easier implementation in the next design by keeping the interface identical The exported EDIF file can be used to populate any number of black boxed RTL modules in the new design If using XST the exported EDIF file can be used to derive some timing data The exported UCF file can be used to recreate the Pblock placement constraints Identical placement can be duplicated for multiple modules by moving the modules after they are imported Xilinx Cores ngc ngo During the Export Floorplan and Save Floorplan commands described in Chapter 10 Floorplanning the Design the NGC and NGO core logic is filtered out of the netlist and black box modules are created The original source NGC and NGO core files are copied into the save or export directory This ensures that these original NGC and NGO core files are used during ISE implementation Note The output log for the ngc2edif command can be viewed in the PlanAhead terminal window where PlanAhead was invoked Occasionally the ngc2edif command produces EDIF that is unusable or that now has discrepancies with the accompanying NCF constraints Please report these issues to Xilinx along with the data to repr
212. e Level Constraints PlanAhead allows selective assignment of module level constraints To assign constraints to a module instance 1 Select the instance in the Netlist view 2 Select File gt Import Constraints The Import Constraints dialog box will be displayed PlanAhead User Guide www xilinx com 69 UG632 v 11 4 Chapter 2 Creating and Managing Projects ei Import Constraints Import physical constraints for XILINX Netlist FPGA_RCY_802_11 Instance receiver RChainTopInst Description The physical constraints are based on the logical hierarchy QG Names in the physical constraints file are relative to instance receiver RChainTopInst CONYDECOD Constraints files i Remove Whead_Tutorial labs projects project_2 exportiyviterbi witerbi ucf Figure 2 38 Import Constraints Dialog Box 3 Select Instance and make sure the Instance field is set to the netlist instance for which you are importing module level constraints 4 Inthe Constraints files area click the Add button to locate and select the constraint files to import 5 Click OK to import the constraints Any information regarding warnings and errors during the import are displayed in the Console view and written to the planAhead 1og file Updating Design Constraints for Floorplans PlanAhead stores each Floorplan with a unique set of UCF constraint file s Currently all
213. e Pblock range as the Clock Region GB New Pblock Name oblock_usbEngineO_usb_in Grids CLOCKREGION_xO0 1 Assign selected instance ij Cancel Figure 10 12 New Pblock Dialog to Confirm Pblock as Clock Region The Pblock rectangle needs to encompass the clock region boundary to enable the CLOCKREGION option Unselecting the CLOCKREGION_X button will enable the Pblock to be defined using traditional logic based ranges PlanAhead User Guide www xilinx com 295 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX gt fal E pblock_usbEngine0 _usb_in Name pblock_usbEngine0_usb_in Parent ROOT v Grid Range CLOCKREGION XO 1 x0 1 General Statistics Instances Rectangles Attributes Selection Figure 10 13 Clock Region Pblock General Properties 3 The two types of Pblocks can be toggled by selecting or unselecting the CLOCKREGION button in the New Pblock dialog or in the Pblock General Properties view The Pblock clock region coordinates are displayed in the Pblock General Properties view Working with Pblocks Understanding Pblock Graphics Using the default display options Pblocks and the instances assigned to them are displayed The outer rectangle is the Pblock border The rectangles contained inside the Pblock are the netlist instances assigned to it Multiple instances can be placed into a Pblock Instance rectangles dis
214. e Remove Selected Elements From Schematic toolbar command in the Schematic View x Figure 8 14 Remove Selected Elements From Schematic Toolbar Button Printing the Schematic View You can print the Schematic view using the File gt Print command The current viewable area is printed To print the entire Schematic view zoom to fit and then print Schematic View Specific Popup Menu Commands Instances and nets may be selected within the Schematic view for manipulation The common popup menu commands are covered in the Using Common Popup Menu Commands The Schematic view commands and a brief description of each is as follows e Expand Cone Appends the view to display the entire cone of input logic either to the first Primitives Flops or to the I Os e Toggle Autohide Pins Toggles the display of module pins for selected modules e Remove Selected Elements From Schematic Removes the selected objects from the schematic e Expand Inside Expands all logic contained inside of selected modules e Expand Outside Expands all logic contained outside of selected modules The expansion will only occur on the parent module logic e Collapse Inside Collapses all logic contained inside of selected modules e Collapse Outside Collapses all logic contained outside of selected modules The collapsing will only occur on the parent module logic e Select All Primitive in Schematic Selects all displayed primitive logic in the act
215. e also displayed in the PlanAhead Console view RTL Source Files Verilog VHDL or other design text files Verilog and or VHDL files can be imported and elaborated to analyze the logic or modify the source The original source files can be referenced and left in place or they can be copied into the project for portability The search directories are specified when importing RTL source files All recognized files and file types contained in the directories will be imported into the Project Xilinx Cores NGC NGO PlanAhead can support designs which use NGC format netlists such as Xilinx core files and XST output netlists The software behaves differently depending on whether the NGC file is a top level netlist or a module level netlist Upon netlist import PlanAhead will automatically convert NGC and NGO format core files to EDIF NGC format files get converted using the Xilinx nge2edif command NGO format files get converted to EDIF using the Xilinx ngecbuild and nge2edif commands For secure cores the LUT equations are stripped out of the converted EDIF These types of NGC or NGO core files have usually been meticulously hand placed for maximum performance Chances are that floorplanning will not improve their performance It is not recommended that you floorplan logic inside the core modules However you can floorplan the location for the entire core and all surrounding logic very effectively During the Export Floorplan and Sa
216. e button to select the top level netlist file for the design Netlist directories Use the Add button to select directories in which to search for lower level modules and cores during netlist import By default the PlanAhead invocation directory and the directory that the top level netlist was selected from are included in the search path You can arrange the order in which to search these directories by selecting them and using the Up or Down buttons Directories can be removed from the search path by using the Remove button in the dialog box www xilinx com 53 Chapter 2 Creating and Managing Projects g XILINX New Project Import Netlist Specify the Edif netlist that contains the top module and optionally a dE list of directories to be used as a search path during netlist reading i Netlist file 3 jects Pland4head_Tutorial labs design_files 802RC _cos13 edf Netlist directories C Data planshead_Projects PlanA4head_Tutorial labs design_files Figure 2 21 New Project Wizard Import Netlist Page 2 To continue with the wizard click Next The netlist will now be imported into PlanAhead which may take a few moments A status bar is displayed for each netlist imported Any information regarding warnings and errors will be displayed in the Console view and written to the planAhead 1log file A successful file parser message should be displayed Selecting a Product Family and Default Par
217. e dialog box allowing you to handle them differently To cancel an active move operation press the Esc key The active command will be terminated Note If having difficulty moving Pblocks click the Set Pblock Size toolbar button to redraw the rectangle elsewhere You may also wish to remove placement constraints prior to moving Pblocks www xilinx com 299 300 Chapter 10 Floorplanning the Design g XILINX Stretching a Pblock Stretching Pblock edges may be done by selecting the Pblock and moving the cursor near one of its edges or corners When the cursor changes to a drag symbol click and drag to reshape the Pblock If the Pblock is stretched to a location which includes new device logic types such as BRAM DSP etc a dialog box is displayed prompting you to add the new range types to the Pblock definition Pblocks behave differently when location placement constraints are assigned inside of them If location constraints are assigned to the Pblock a dialog box is displayed prompting you to either remove or leave the location constraints intact Fixed and unfixed location constraints are listed separately in the dialog box allowing you to handle them differently To cancel an active stretch operation press the Esc key The active command will be terminated Using the Set Pblock Size Command Existing Pblocks can be sized or resized with a new rectangle by using the Set Pblock Size command To create a new rectangle fo
218. e list of pins that is created in a spreadsheet program like Microsoft Excel and saved as a CSV comma separated value file PlanAhead can read this file to populate the IO Ports list view by selecting File gt Import I O Ports From there you can use the drag and drop individual pins or groups of pins to the graphical device or package view e UCF Import On many designs you may have a list of pins defined in an existing UCF file PlanAhead can import this pre existing UCF file to populate the IO Ports list view From there you can use the drag and drop individual pins or groups of pins to the graphical device or package view Similar to importing a CSV file select File gt Import I O Ports Port direction is not defined in the UCF file format You should use the Set Direction popup menu command in define Port direction prior to assigning pins e HDL Import You may have a top level HDL file that defines the main IO pins of the design but is not yet synthesized into an NGC or EDIF netlist It may often be the case that this top level HDL file contains nothing more than the port definitions so it www xilinx com 87 Chapter 3 Using PlanAhead With Project Navigator g XILINX 88 may not even be synthesizable at this time However just as with PACE or Floorplan Editor PlanAhead can read in this file and enable you to accomplish early pin planning and assignment tasks Just as with CSV or UCF import a pre synthesis HDL file
219. e reimplemented 5 Click Apply to accept the changes Using Resource Utilization Statistics to Size Pblocks Pblocks can be sized and placed using the utilization estimates in the Pblock Properties view The device resources available inside the rectangle are compared against the logic contained in the Pblock to compute utilization estimates To display the utilization estimates for a Pblock 1 Select the Pblock and view the Pblock Properties 2 Click the Statistics tab PlanAhead User Guide www xilinx com 307 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX gt GR pblock_cpuEnaine_cpu_dbg_dat_i Physical Resource Estimates Site Type Available Required Util LUT 6400 FF 6400 SLICEL 880 SLICEM 720 DSP48E 80 RAMBFIFO36 32 Clock Report Domain Module Resource Instar cpuClk_BUFGP top Global BUFGCTRL_X0 15 wbClk_BUFGP top Globali BUFGCTRL_X0Y19 m lt j General Statistics Instances Rectangles Attributes R Selection Figure 10 28 Pblock Properties View Statistics Tab 3 In the Statistics tab view the utilization estimates in the following three columns Available Displays the number of available sites in the Pblock Required Displays the number of sites that the assigned logic requires Utilization Displays the estimated utilization percentage for each logic type The appropriate utilization can be met by resizing the
220. ead environment The PlanAhead software replaces PACE and Floorplanner for all pin planning design viewing and floorplanning flows for FPGA designs www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Guide Contents When PlanAhead is invoked from Project Navigator the interface provides access to only the PlanAhead features specific to the selected task This mode of PlanAhead is called ISE Integration mode The mode is displayed in the status bar at the bottom of the PlanAhead viewing environment Guide Contents This document contains the following chapters Chapter 1 Understanding the PlanAhead Design Flow provides an overview of the benefits of using PlanAhead an overview of the design flow and features in PlanAhead and describes the required inputs and outputs to the product Chapter 2 Creating and Managing Projects describes the initial setup and management of a project within PlanAhead Chapter 3 Using PlanAhead With Project Navigator describes the PlanAhead flows that are integrated with Project Navigator Chapter 4 Using the Viewing Environment describes the PlanAhead user interface Chapter 5 I O Pin Planning describes the PinAhead environment which enables pin assignment Chapter 6 Creating and Analyzing the RTL Design describes the PlanAhead RTL environment Chapter 7 Implementing a Design describes the PlanAhead synthesis and implementation environ
221. eating an Empty Project 2 Click Next Selecting a Product Family and Default Part The next page in the New Project wizard prompts you to select a product family and default part PlanAhead User Guide www xilinx com 41 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX 42 New Project Choose a Part and a Floorplan Name Enter a name for your floorplan and choose a Xilinx device Product Family virtexS Choose Part xcSvh30fF324 1 Floorplan name floorplan_1 Figure 2 9 New Project Wizard Product Family and Default Part Page 3 Select the desired target product family architecture and default part 4 Click Next Note Once a Product Family is selected for a Project it cannot be changed A new Project will need to be created to target a different architecture The Default Part however can be changed during Synthesis and Implementation Run creation and during Floorplan creation Defining the Initial Floorplan Name and Selecting a Target Device The Floorplan Name page of the New Project wizard is now invoked www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Create New Project Wizard to Create a New Project New Project Floorplan Name Enter a name for your floorplan and choose a Xilinx device Floorplan name floorplan_1 Choose Part xcSvlx30FF324 1 Figure 2 10 New Project Wizard Floorplan Name Page 5 Inthe Floorplan Name page
222. ect Navigator source UCF file s are updated This will also reset the Project Navigator design process state if appropriate Refer to Design Analysis and Floorplanning View Layout for more information about the integration mechanics and process Refer to the Chapter 9 Analyzing Implementation Results and Chapter 10 Floorplanning the Design for more information about using the PlanAhead environment following implementation PlanAhead Viewing Environments I O Pin Planning View Layout PlanAhead User Guide UG632 v 11 4 The PinAhead environment is invoked automatically when selecting either of the I O pin planning processes in Project Navigator It can also be launched from within PlanAhead by selecting Tools gt Open PinAhead or Layout gt Load Layout gt PinAhead Cockpit www xilinx com 83 Chapter 3 Using PlanAhead With Project Navigator XILINX GB projecte ew C WataPlandbear Des Layo Help Fle Edt Toos Window ser pupivex a goonk1oeng E Pome pr Jen Netist o to aat nak WW cpu rgneicpu jb dat WW ceebrgrekpu_md_dat_o E tigre jdn ak T ubirgredfusbingnesRAM E uhFoeine lh nsh ima sh in J Properties Bp Netist A Source Cock Regions Id Name Row Coan 10 2 xmi 3am m 5 xs xws 7 xio a xivt a a E HD Vorrei pad Oo 4 DG Corro pad to Mode pad 0o HG OpMode pad_1o G Otat pad 0o wam 3 Daan pas adap Pins i ER i D
223. ection Diff Pair Define differential pair signals or busses Create Bus Enter bus range for bus creation 138 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Defining and Configuring I O Ports Configure I O Standard Select the desired I O Standard constraint Drive Strength Select the desired Drive Strength value Slew Type Select the desired Slew Type value Pull Type Select the desired Pull Type value Phase Enter a phase group or select an existing phase group A phase group is a logical grouping of ports that is used in SSN calculations to indicate that the set of ports share the same frequency and phase For more information on using this option see Defining the I O Port Switching Phase Groups page 160 Refer to Xilinx device documentation for information regarding voltage capabilities of the device Configuring I O Ports To configure a port or a group of ports 1 Select the ports in the I O Ports view 2 Select Configure I O Ports from the popup menu The Configure Ports dialog box opens Configure Ports I O Standard DIFF_HSTL_I_18 Drive Strength Slew Type Pull Type NONE default v Phase default v Cancel Figure 5 16 Configure Ports dialog box 3 View and edit the definable options in the Configure I O Ports dialog box I O Standard Select the desired I O Standard constraint Drive Strength Select the
224. ectory and is removed and replaced each time PlanAhead is invoked from Project Navigator 80 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX ISE and PlanAhead Integration Process I O Pin Planning Pre Synthesis You can elect to perform early I O pin planning prior to having a synthesized netlist This can be done either by using PlanAhead standalone or by selecting this process step in Project Navigator Note At this stage of the design process logic synthesis has not yet been run The tool has no concept of clock ports clock related logic differential pairs GTs etc You must be especially careful to ensure these types of ports are placed appropriately to avoid implementation errors Whenever possible I O pin planning should be performed after logic synthesis The presence of a netlist ensures that the clocks clock logic differential pairs GTs etc are recognized and automatically considered during pin assignment in PlanAhead There are also many more Design Rule Checks DRCs that are performed based on logic connectivity and clocks to ensure a legal placement prior to implementation To perform I O pin planning in Project Navigator prior to running synthesis in the Processes pane expand User Constraints and double click I0 Pin Planning PlanAhead Pre Synthesis or select the Tools gt PlanAhead gt Pre Synthesis IO Pin Planning command When PlanAhead is invoked Project Navigator passes all of the R
225. ed and exported from an elaborated RTL design project Refer to the Elaborating and Analyzing the RTL Design These design resource statistics are displayed as follows 1 Select either the top level module or any instance module in the Netlist view PlanAhead User Guide UG632 v 11 4 www xilinx com 255 Chapter 8 Analyzing the Design g XILINX H Nets 116 He Primitives 37 a g control_inst control Afi reconfig_module rmodule E uart_baudClock_inst uart_baudclock 2 uart_rx_inst uart_rx 2 uart_tx_inst uart_tx E vga_color_bars_inst vga_color_bars amp Constraints Figure 8 42 Netlist View with Top Module Selected The Netlist or Instance properties should appear in the Properties view If the Netlist or Instance Properties are not displayed right click on the module and select Netlist Properties or Instance Properties from the popup menu The Netlist Properties view contains one tab and should display the statistics by default The Instance Properties dialog box contains five tabs 3 If viewing the Instance Properties click the Statistics tab The Statistics tab displays valuable design information including primitive instance counts interface signal counts clock names and clocked instance count and carry chain count and max length 256 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Analyzing the Synthesized Design e gt GN El cpuEngin
226. ed instance location constraints can be deleted by selecting the placed instances and using one of the following methods e Select Tools gt Clear Placement Constraints For more information see Selectively Clearing Placement Constraints e Click the Unplace popup menu command Selectively Clearing Placement Constraints Instance location constraints can be selectively removed from the design You can filter the type of constraints you want to clear based on ISE assigned selected logic or Pblocks and specific logic types Preselected objects will dictate the behavior of the Clear Placement Constraints wizard If Pblocks are pre selected the wizard will display default settings to clear placement constraints inside of them If Instances are selected the wizard will display default settings to remove them To clear placement constraint assignments 1 Select Tools gt Clear Placement Constraints The Clear Placement Constraints wizard is invoked Clear Placement Constraints Clear Placement Constraints This wizard will guide you through the process of deleting placement constraints from the current floorplan You can clear instance placement I O port placement or both What type of placement do you want to clear Instance placement 1 0 port placement O Both To continue click Next 1 Cancel Figure 10 43 Clear Placement Constraints Wizard Clear Instance Placement I O Ports Placement or Bot
227. ed launch options If the selected Runs are in a state other than Not Started you are prompted to first reset the runs prior to launching them PlanAhead User Guide www xilinx com 203 UG632 v 11 4 Chapter 7 Implementing a Design g XILINX Resetting Runs The Reset Runs command is used to remove the results of the selected runs You are prompted to remove the run data from disk which is advisable The status of the Run is set back to Not Started 1 Select one or more runs in the Design Runs view Use Shift click or Ctrl click for multiple selections 2 Select the Reset Runs popup command The Reset Runs confirming dialog box will appear to prompt you to remove all implementation data from disk for the selected runs G Reset Runs A OK to reset run synth_2 Delete files on disk Figure 7 26 Resetting Runs 3 Inthe confirming dialog box click Reset If any ISE processes are currently running or queued you are prompted to stop them 4 Click Yes to proceed The status for the selected runs is reset Deleting Runs The Delete command is used to remove selected Runs from the Design Runs view and to remove their associated data from disk You are prompted to confirm the deletion of the selected runs 1 Select one or more runs in the Design Runs view Use Shift click or Ctrl click for multiple selections 2 Select one of the following commands Select the Delete main toolbar button x Figure 7 27
228. ed to create a PlanAhead Project This is used to analyze floorplan or implement the design using the extensive floorplanning and implementation environment 1 Select the Import synthesized EDIF or NGC netlist option in the Design Source dialog box PlanAhead User Guide UG632 v 11 4 www xilinx com 47 Chapter 2 Creating and Managing Projects g XILINX New Project Design Source Specify the type of sources for your design You can start with RTL AE or a synthesized EDIF Import RTL Sources You will be able to run RTL analysis synthesis and implementation Import synthesized EDIF or NGC netlist You will be able to run post synthesis design analysis planning and implementation Import ISE Place amp Route results You will be able to do post implementation analysis of your design Do not import sources at this time You will be able to do pin planning now and import a netlist later Figure 2 15 Creating a Project using a Synthesized EDIF or NGC Netlist Selecting a Top Level Netlist and Module Search Path If the Import synthesized EDIF or NGC netlist option was selected the next page in the New Project wizard enables you to input a top level netlist file and a search path to find module level netlists 1 Inthe Import Netlist page edit the definable option Netlist file Enter a name to identify the top level netlist in this project Use the File Browse button to select the top level netlist
229. edn viterbi_lib 36 30 acs_7 viterbi edn viterbi_lib 36 31 acs_8 viterbi edn viterbi_lib 36 32 acs_9 viterbi edn viterbi_lib 37 33 acstop viterbiiedn viterbi_lib 80 34 dpram_64b_256w_wa_rb viterbi edn test_lib 147 35 tbunit viterbi edn viterbi_lib 106 Cancel Figure 2 33 Update Netlist Wizard Specify Replacement Module Page Select the module to be used as the replacement during the update from the list By default PlanAhead will automatically select the top level module in the replacement netlist The list can be sorted by clicking on the column headers Click Next to continue The Specify Module to be Replaced dialog box will appear Select the module from the original netlist to be updated PlanAhead will attempt to select the module to be replaced based on the name of the replacement module You may need to scroll to find the module you want to select Click Next to continue The Summary dialog box will appear Review the Summary for the module replacement 10 Click Finish to update the design with the new module level netlist www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Floorplans Working with Floorplans What is a Floorplan PlanAhead provides the Floorplanning environment to analyze and experiment with various design parameters including alternate devices timing and or physical constraints and implementation options Think of a floorplan as a snapshot
230. ee 162 Exporting Package Pin Information 0 0 0 cece eee eee 163 Exporting a I O Port List eerca eie ohana ee edi hinde teeta keudG RA lois 164 Chapter 6 Creating and Analyzing the RTL Design Using the Project Environment 44 6 0054s05n4n0 nc eawee rina sannur rnnr rrn 165 Using the Sources View 600 e eee eee eens 165 Viewing Source File Properties 0 0 0 cece cece eee eee eee 168 Adding Sources to the Project 0 0 0 c cece cence eee 168 Adding Source Files or Directories 0 0000 0000s 168 Creating a New Source File 0 0 6 ccc eee 170 Updating RTL Source Piles oc srssri tia striae ri Ved Sa diese Haves de vee ca eae 170 Using the RIL Editor 5 ie1ytins inte sag tak eee ed ite nae Recah 171 Using the RTL Editor Specific Popup Menu Commands 55 172 Using the Find in Files Command to Search Source Files 000 172 Elaborating and Analyzing the RTL Design 0005 173 Using the RTL Netlist View 0 0 0 e eee ee 175 Using the RTL Hierarchy View 0 0 00 e eee eee eee ee 176 Viewing the Resource Estimates for Modules 00600 e eee eee eens 176 Analyzing the RTL Schematic 0 000 e eee eee 177 Searching for Objects Using the Find Command 00 000 eee ee 178 Running RT DRCS scence ictus de hatin Shei Aha bbb pwced whale gees 178 UG632 v 11 4 www xi
231. eei ea 252 Analyzing the Synthesized Design 0 00 c cece cece eee 253 Reporting Design Resource and Device Utilization Statistics 253 Exploring the Logical Hierarchy 0 258 Analyzing the Hierarchical Connectivity 0 00 0 c cece eee eee eee 258 Running Design Rule Checks DRC 0 00 cece cece neces 259 Running Timing Analysis 0 0 0 0 coo eens 264 Analyzing Timing Results 0 ccc e e ena 266 Searching for Objects Using the Find Command 00000 270 UG632 v 11 4 www xilinx com PlanAhead User Guide Chapter 9 Analyzing Implementation Results Importing ISE Placement and Timing Results 0 273 Importing ISE Placement and Timing Results With New Project Wizard 273 Importing ISE Placement and Timing Results from PlanAhead Runs 273 Importing ISE Placement and Timing Results from Outside PlanAhead 273 Importing ISE Placement and Timing Results from Project Navigator 273 Analyzing Placement and Timing Results 0 00008 274 Exploring Xilinx TRCE Results 0 00 000 274 Viewing Timing Paths in the Device View 0 0 66 c cece eens 274 Viewing Timing Paths in Schematic View 6606 e cece eee e ne 275 Exploring Logic Conmecthvity i ci0ccseevianw ena leenkenks winnaar deo eewicies 276 Using the Show Connectivity Command 6 666
232. een omitted IOB 1 IOB 2 QOUT CLKIN Name Name Horizontal ellipsis Repetitive material that has been omitted allow block block_name loc1 loc2 locn www xilinx com Preface About this Guide 10 Online Document The following conventions are used in this document XILINX Convention Meaning or Use Example See the section Additional Cross reference link toalocation Resources for details Blue text in the current document Refer to Title Formats in Chapter 1 for details Cross reference link toalocation See Figure 2 5 in the XST Red text in another document User Guide f Go to http www xilinx com Blue underlined text Hyperlink to a website URL for the latest speed files www xilinx com PlanAhead User Guide UG632 v 11 4 Preface About this Guide About PlanA head 20030545045 Hohe bib iard ekee rakda rpa ek adada 5 Plan Ahead Features ertreccreneetece o ierit inete e e ie Bad ane 5 Integration with the Project Navigator Environment 00000005 6 Guide Contents 000 0 0000 aaaeeeaa 7 Additional Resources 0 0 00 ccc ccc ccc ec cence beeen eben nes 8 Xilinx Customer Education Training 00 00 cee eee eee ee 8 DOCUMENTAHON 20s cose saslc eda cwkeue thet or eet creat eredne E aeseals ES 8 Video Demonstrations ecis orere nsir d EEEren eee REEERE EEEE eens 8 Conv
233. egies that have been used extensively on internal benchmarks with great success The option settings for these strategies are not editable You can copy and modify these Strategies to create your own Strategies are Tool and version specific Each major release of ISE have version specific command line options which PlanAhead can support Select or copy a strategy from a specific tool and version category as shown below To review copy and modify strategies 1 Select Tools gt Options gt Strategies The Strategies dialog box will appear It contains a list of pre defined strategies www xilinx com 209 Chapter 7 Implementing a Design g XILINX Ei PlanAhead Options Z Strategies CZ eo mw re O_O s axXxAT p Themes A 7 User Defined Strategies a steed ee Er Plandhead Strategies Description Timing Performance with IOB mae es amp xXST 11 Flow XST 11 Selection Rules da Plandhead Defaults i EAT imingWithIOBPacki ere A TimingWithoutlOBP lt opt_mode 3 AreaReduction opt_level Shortcuts da PowerOptimization register_balancin v A XST Defaults fsm_encoding SISE 11 Jz Schematic da ISE Defaults auto_bram_packi Name TimingwithIoBPacking Options 28 MapTiming use_dsp48 J MapGlobalOptParHic resource_sharing 3 MapLogicOptParHigt iob J MapGlobalOptLogicc netlist_hierarchy Ja MapTiminglgnoreke power W amp MapCoverBalanced More Options J Map
234. egin tracing logic 1 Select a net or an instance The Net Properties or Instance Properties view should appear in the Properties view 2 Ifthe Net Instance Properties are not displayed right click on the net or instance and select Net Properties or Instance Properties from the popup menu www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Exploring Logic Connectivity Full Name receiver ousMuxWrapInst ousMuxInst sub_blocks_to_ASIC_ Parent E receiver busMuxWrapInst busMuxInst sub_blocks_to_AS Pblock pblock_2 Cell RA4AMB16_S36_S36 Type Block RAM lt il General Statistics Pins Children Attributes Connectivity Selection Figure 9 6 Instance Properties Notice in the example above that the RAMB16 instance is selected In the Connectivity tab of the Instance Properties view all of the nets that connect to that instance are listed along with the pin names they connect to The number of pins on the net is also listed To view individual nets simply select a line in the list To further trace a particular net 1 Select the line in the list in the Connectivity tab 2 Select the Net Properties command from the popup menu 1 receiver fousMuxWrapInst busMuxInst sub_blocks_to_ASIC_ a s to_ASIC Schematic Highlight Ctrl H Highlight vith gt Mark Ctrl M Show Connectivity Ctrl T APPPPPPPPPPPP General
235. emporarily To re dock an auto hidden view click the Toggle auto hide button or select the Auto hide command from the popup menu once again To undo the auto hide mode select Layout gt Undo Toggle Autohidden Docking Mode Floating Views Views can be undocked or floated so that they may be moved and sized independently To float a window click on the view tab or banner and or click the Toggle floating button or select Floating from the popup menu The view will appear in a separate floating window In this case windows will obviously overlap Floating windows can be moved by dragging the view banner They may also be moved outside of the PlanAhead main window The default locations and sizes to display all floating view types are also stored in your saved layouts The Workspace view is floated by selecting the view tab and then selecting the Float Window popup menu command Defining Viewing Area Sizes The window borders between the main docking areas can be dragged to resize any of the PlanAhead docking areas views The cursor will change to a slider bar indicating that the view border is selected for dragging The viewing areas can also be removed or hidden to provide more viewing space for other views If a view is closed the other docking areas will fill in the void Using the View Specific Toolbar Commands Many views have toolbar commands that are displayed within the view The most common View specific toolbar c
236. entions oeereerbi eei et ea d en e ekee aree i ni a ait 9 Typographical ss ca ooiss dap secon win siestvelediarewigns t i e e a eE Baga A 9 Online Document ics Sc eed ce te Pode wd 6 hoe ew eee a ead van 10 Chapter 1 Understanding the PlanAhead Design Flow PlanAhead Design Flows 00 000 c cece cece cnn eee eee 19 Basic Design BOW dirrnecionesrinss beds abled benenta eder e e 20 Run Experimentation Flow 0 000 e eee eee ee 20 Design Analysis and Floorplanning Flow 0 0 066 c cece eee eens 21 Input and Output Files Luanna nuanean coer decid cea yeaa cones 21 Inputs to PlanA head iusa tecsslotsisicredats steele seksi AEE Ee Bia EER E elect 21 Outputs for Reports wi sici g iiris ieiti iad heed ea i a ee 24 Outputs for Environment Defaults 0 0 000 e eee 26 Outputs for Project Data 0 0 0 eee eee ee 27 Outputs for ISE Implementation 0 0 00 28 PlanAhead Terminology 000 c ccc e ccc cence eens 32 Chapter 2 Creating and Managing Projects Invoking PlanAhead ics sieve cain s cae ede ete ned ebb Vinee pee 35 Eni o osc eh ewe Bae de eek bee Cede Tied ov Sia Seed ee eik eed eee teas 35 WindOWS 30 o6sd5 cee cian de bee eed E EEE ERE EE Eee dE eee ee aes eae 35 PlanAhead Command Line Options 0 6c cece cece cece ences 36 Using a PlanAhead Startup Tcl Script 6 ene ee 37 Using the Getting Started Jump Page 000 00 38 Und
237. erarchy view Viewing or Changing Pblock Properties Various types of information can be displayed with the Pblock Properties view To display or edit Pblock properties select the Pblock and view the Pblock Properties view The tabs of this window are described below Note To accept any changes made click Apply To cancel any changes click Cancel Selecting another item or closing the Properties view will not initiate any changes unless you click Apply gt iti 3 pblock_cpuEngine_cpu_dbg_dat_i Name pblock_cpuEngine_cpu_dbg_dat_i Parent ROOT w Grid Range SLICE XBY7O 4 77109 DSP48 XOVZ8 X4 43 RAMB36 XOV14 x3 21 General Statistics Instances Rectangles Attributes Selection Figure 10 20 Pblock Properties View 302 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Pblocks The General Tab The General tab contains the following definable fields e Name Displays the Pblock name e Parent Displays the Parent Pblock This field is a non editable field for some Pblocks If a Pblock has multiple potential parent Pblocks the field becomes active allowing definition of the Parent Pblock e Grid Range Enables the Pblocks to be specified with specific AREA_GROUP RANGE properties Selecting specific ranges will only constrain the selected logic types within the Pblock area The grid range coordinates are displayed for each logic type once the
238. eriment with different constraint or device strategies Implemented Design Results Based Projects Projects can also be created to allow analysis of implementation results created outside of PlanAhead using the Xilinx command line tools The design netlist implementation and timing results can be imported to explore timing or placement related issues Using the Create New Project Wizard to Create a New Project The New Project wizard walks through the individual steps to define a Project name and storage location to import the netlist and to create an initial Floorplan including selecting a device and importing the constraints To create a new project 1 Select one of the following commands Click the New Project toolbar button Gj Figure 2 5 New Project Toolbar Icon Click the Create a New Project link on the Getting Started jump page Select File gt New Project The first dialog box of the New Project wizard gives an overview of the wizard intent 2 To continue click Next The Project Name page appears New Project Project Name Enter a name for your project and specify a directory where the project data files will be stored Projectname project_2 Project location fc Pata Plandhead_Projects Project will be created at C Data PlanA4head_Projects project_2 i Cancel Figure 2 6 New Project Wizard Project Name Page PlanAhead User Guide www xilinx com 39 UG632 v 11 4 Chapter 2 Creating
239. erstanding the Different Types of PlanAhead Projects 38 Empty Projects for I O Pin Planning 000 c eee eee eee eee 38 RIE Source Based Projects i jecoi ila cov eres ovations othe btu e e e a aah we 38 Synthesized Netlist Based Projects nunana nanana eens 38 Implemented Design Results Based Projects 0 000 e eee eee eee 39 Using the Create New Project Wizard to Create a New Project 39 Entering a Project Name and Storage Location for the Project 40 Selecting the Design Source Data Type 6 6 c cece ee 40 Creating an Empty Project for I O Pin Planning 06 e eee eee 41 Creating a Project by Importing RTL Sources 0 0 0 c cece eee eee 43 Creating a Project with Synthesized EDIF or NGC Format Netlists 47 Creating a Project with ISE Placement and Timing Results 52 Managing Projects 2c0 c2cresvebierneeieerterneetaeedasnetes1eeerdanensees 59 Opening an Existing Project 6 6 cece teen E 59 Opening Multiple Projects 0 cece cence eee eee 60 Closing a Project s2 s02ccsc dees obese chee eee r EEEE cee aE Bees Shas 61 UG632 v 11 4 www xilinx com PlanAhead User Guide Updating the Netlist for a Synthesized Netlist Based Project 61 Working with Floorplans 6 09 0242 s eee es Var inn do pebed een syn uicned sail Reaneds 65 What is a Floorplan riere ieee iii
240. es Reusing the IP Module PlanAhead User Guide UG632 v 11 4 Instance IP files that have been exported can be reused in other designs The format of the exported IP files maintains the original logic interface of the module which will make reuse much easier The logic designer should create a black box module with the exact same interface as the exported instance If using XST for logic synthesis the exported EDIF file can be used to derive timing information during synthesis Once the netlist has been created through synthesis create a new Project using the new netlist For more information about creating a new project see Using the Create New Project Wizard to Create a New Project Importing the Instance EDIF Netlist To reuse an IP module you must first import the instance EDIF netlist To import the netlist use one of the following methods e During new project creation Define the search path in the New Project dialog box to add the module to a new project using File gt New Project e Into existing project Import the module using the File gt Update Netlist command after the Floorplan has been created For more information on updating a module level netlist see Updating a Module Level Netlist Importing the Placement Constraints UCF Once the module netlist has been imported the next step is to import the placement constraints To import placement constraints 1 Select the instance in the Netlist view
241. es and analyze the RTL design Currently Verilog VHDL and core level NGC NGO files can be imported and managed within the PlanAhead RTL Project Using the Sources View The Sources view displays the RTL source directories and files imported into the Project These files are either Verilog or VHDL format RTL sources NGC NGO core netlists or XCF constraints files for XST synthesis PlanAhead User Guide www xilinx com 165 UG632 v 11 4 166 Chapter 6 Creating and Analyzing the RTL Design g XILINX Azresee8 Name Library Location G amp S VHDL 7 wh bFt vhdl bFELib C Data Plan4head_Designs NewDemo src wh bft_package vhdl bFELib C Data Plan4head_Designs NewDemo src G core_transform vhdl bFtLib C Data Plan4head_Designs NewDemolsrc G round_1 vhdl bFtLib C Data Plan4head_Designs NewDemol src wh round_2 vhdl bftLib C Data Plandhead_Designs NewDemo src wh round_3 vhdl bFELib C Data Plan4head_Designs NewDemo src G round_4 vhdl bFELib C Data Plan4head_Designs NewDemo src Verilog 96 Core 2 A FifoBuffer ngc C Data Plan4head_Designs NewDemol src A blk_mem_512X 32 ngc C Data Plandhead_Designs NewDemo src y Group by Type fal Floorplans Figure 6 1 Sources View The Sources view displays the source files It also displays the source file type VHDL library location and whether the files are imported locally in the Project or referenced remotely e Name List files alphabetically or grouped by
242. es what is selected and returns with only modules selected unless ROOT level logic was originally selected The command will not select parent modules if modules are selected The pre selected modules will remain selected Using the Select Main Menu Commands Several of the Selection Unselect Highlight and Mark commands are available from the Select menu For a description of all Select commands see Select Menu in Appendix A Fitting the Display to Show Selected Objects Views in the Workspace have a Zoom option to fit all selected objects To zoom fit the selected objects use one of the following methods e Select View gt Fit Selection e Press F9 e Click the Fit Selection toolbar button R Figure 4 17 Fit Selection Toolbar Button Using the Selection View The Selection view as shown below displays the list of objects currently selected Objects may be sorted unselected or marked from this view The Selection list is dynamically updated as Floorplan objects are manipulated To invoke the Selection View select Window gt Selection PlanAhead User Guide www xilinx com 109 UG632 v 11 4 Chapter 4 Using the Viewing Environment g XILINX Name ASIC_BIF_ADDR_O_hNib_ibuf 3 D 2 ASIC_BIF_ADDR_O_hNib 3 I O Port D 3 H2 Package Pin 4 H2 I O site amp Properties Figure 4 18 Selection View To sort elements click on the column header to use as alpha numeric sort criteria Objects can be sorted
243. esults page is invoked It enables you to import the place and route results generated in ISE which are used to create a floorplan for viewing and analysis in PlanAhead PlanAhead User Guide www xilinx com 57 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX New Project Import ISE Implementation Results Specify placement results C lt DL or routed NGC and or timing results TWR or TWh Import Placement M Import Timing Results Name results_1 Figure 2 25 New Project Wizard Import ISE Implementation Results 10 In the Import ISE Implementation Results page edit the definable options Import Placement Select this option and locate and select a placement results file from the ISE implementation such as an XDL GZ or NCD format file Import Timing Select this option and locate and select a timing results file from the ISE implementation such as a TWX format file Results Name Enter the name of the results floorplan The New Project Summary page is displayed next 11 To initiate the Floorplan click Finish in the Summary page The Floorplan is initialized and the PlanAhead floorplanning environment is invoked 58 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Managing Projects e project_2 C Data PlanAhead_Designs demo_bckup project_2 project_2 ppr PlanAhead 11 1 LRO i File Edit View Tools Window Select Layout Help geet ea agimax a Gorrxna
244. etailed LUT FF and so forth based floorplanning and timing path analysis Each main task will be covered in its own sub section below and provide you with a brief description of how to accomplish the same task using the PlanAhead environment For information about pin planning or area based floorplanning see Transitioning from PACE Floorplan Editor to PlanAhead www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Transitioning from Floorplanner to PlanAhead Launch and Invocation of PlanAhead from Project Navigator For general post implementation floorplanning PlanAhead can be invoked from Project Navigator using the Floorplan Design Analyze Timing Post Implementation process in the Processes pane Invoking the process launches PlanAhead in a mode to most directly accomplish the selected task There is full integration between Project Navigator and PlanAhead This means Project Navigator will automatically supply all required input files to PlanAhead Any saved output files from PlanAhead e g UCF based constraints will be saved to the proper location within the Project Navigator project It is important to note that when launched from Project Navigator PlanAhead is opened in a streamlined ISE Integration mode where not all functionality of standalone PlanAhead is exposed Launch and Invocation of Standalone PlanAhead PlanAhead can be launched by typing planahead at the standard command line shell prompt
245. ets 166 E Primitives 58 E E bitREV_EQUAL bitRev_Equal_12 fl CONVDECOD viterbi E E descinst descrambler E3 ml DMDIBQi deMapInterBPSK_QPSK_12 Gl E opmuxi DEPUNCT_MUX E equaCalAInst equaCalAFFT GB FOInst FrameOut 4 E RCCInst RChainContral ii SIGNALDecodInst SIGNALDecoder E tracker tracking z synchroTOPInst synchroTOP H 5 Nets 130 E Primitives 35 E autoCORRI autoCORR_12_10 Ga m CFOCorri CFOCorrection_12_16_18 E GB syNBUFFi synchroBUFFIn_12_5 E ij synCFOAwi synchroCFOAv_16_4 G synCTRLi synchroCTRL_12 E m synDETECTI synchroDETECT_16_48 E E uartInst uart_fpga lt j 5u QU netlist Constraints J Package Device x Figure 9 9 Matching Highlighting Color in the Netlist and Device Views Res Beat aSS Ee TO BONES EEE LA E Sa E kRKIDLAANL OF lite Ee bol Pe Rea St GETS d Faa FS i mert ea ik a e E a A m kii E E Er e E SrA ite eae tsn n E SS Ei as M He EH E STERGE rH HEEE Be AEPEHHE i ii a RYO S MARR B ss a A a a a U e E EE Marking Selected Objects Marking Objects PlanAhead enables you to place a Mark symbol in the Device view for all selected objects Marking a selected object is particularly helpful when displaying small objects that you wish to see in the Device view To mark selected objects select Select gt Mark or press Ctrl M This command is available in othe
246. etting these attributes can affect implementation results or cause failures BD a pblock_1 de Name Type Yalue gt lt COMPRESSION Integer 1 General Statistics Instances Rectangles Attributes Selection Figure 10 25 Pblock Properties View Attributes Tab 306 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using Resource Utilization Statistics to Size Pblocks To define new attributes for the Pblock in the Attributes tab of the Pblock Properties View 1 Select Define from the popup menu or click the Define new attribute toolbar button Figure 10 26 Define New Attribute Toolbar Button The Define Attribute dialog box displays Cancel Figure 10 27 Define Attribute Dialog Box 2 Select the desired attribute to assign 3 Click OK The specified attribute type is added in Attributes tab 4 You can then specify an attribute value The available Pblock Attributes are as follows COMPRESSION Controls the compression factor for the area group The percent values can be from 0 to 100 with 0 being no compression and 1 being maximum compression COMPRESSION will not work with Virtex 5 or Virtex 6 devices and any design using map timing GROUP Controls the packing of logic into physical components that is slices allowing logic outside the area group to be with logic inside the area group IMPLEMENT Controls whether the area group logic will b
247. ew Banner Commands The Device view is also used during the I O pin planning process For more information about using the Device view during pin assignment see Chapter 5 I O Pin Planning www xilinx com PlanAhead User Guide UG632 v 11 4 Using the Floorplanning Environment XILINX Viewing Device Resources detail at which the Device resources are displayed depends on the active zoom level within the Device view Graphical sites are displayed and available for all of the device specific FPGA resources rectangles Some devices have unbonded I O banks which are displayed with empty I O bank rectangles The I O clock pads are shown as filled in rectangles All clock resources sites Each site in the Device view can be identified by a tool tip when you hover the cursor consist of placement sites for the different types of logic primitives for the architecture over a logic site an I O bank will display all of the available device resources in the I O Bank Properties being used Virtex 4 Virtex 5 and Virtex 6 devices have many different types of logic such as BUFG BUFRs and BUFGPs are also shown distinctly in the Device view Selecting view center of the device I O banks are displayed as thin color shaded rectangles just outside The interior of the device is broken up into smaller rectangles called tiles These tiles PlanAhead displays the various resources contained in the selected device The level of The I
248. ew is displayed with the results of the search For more information see Using the Find in Files Command to Search Source Files e Open file Opens the selected file s in the RTL Editor view e Add Sources Imports all of the selected source files directories and sub directories into the project e Import into Project Copies all of the selected source files and directories into the project directory e Create Source Invokes the New Source File dialog box which enables you to enter the file name location library and type The new source file will be opened in the RTL Editor e Set Library Enables you to select a library for the selected RTL source file s www xilinx com 167 Chapter 6 Creating and Analyzing the RTL Design g XILINX e Run Elaboration Invokes the RTL parsing and elaboration capabilities which enable resource estimation and RTL schematic exploration e Run Synthesis Invokes the Run Synthesis dialog box to create and launch a Synthesis Run Viewing Source File Properties Selecting an RTL source file in the Sources view displays information in the Source File Properties view The location library size modified timestamp date and parent are displayed for the file SB P P cs G round_3 vhdl Location C Data Plandhead_Designs NewDemolsrc Library lbftLib v Size 2 8 Kb Modified 9 4 08 2 43 28 PM Parent S src Selection Figure 6 3 Viewing Sou
249. f PlanAhead users The highest level is a simple GUI wizard that automatically creates and configures ILA cores based on the selected set of nets to debug One level lower is the main ChipScope view allowing control over individual cores ports and their parameters The lowest level is the set of Tcl debug commands that may be manually entered or replayed as a script for ultimate control A combination of the modes can also be used to quickly insert and customize debug cores www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Core Insertion Flow lt Fast and simple ChipScope Wizard ChipScope Window in Main PlanAhead GUI lt 1 _ ___ Precise control ChipScope Tcl debug commands X11122 Figure 11 2 Debug Core Insertion Modes Deciding Which Debug Core Insertion Mode to Use Table 11 1 summarizes how to decide what insertion mode s to use based on the debugging goal Table 11 1 Debugging Goals and Core Insertion Modes Debugging Goal Core Insertion Mode Quickly create ILA debug core s with default settings for the ChipScope Wizard selected nets Change parameters on existing debug cores ChipScope Window Manually create or delete existing debug cores ChipScope Window Manually create delete or configure trigger or data ports onan ILA ChipScope Window core Manually assign nets to the trigger data clock channels ChipScope Window
250. f a high signal is above the JEDEC input thresholds These margin values assume the weakest drive conditions JEDEC Spec termination and standard receiver requirements for the standard This is one place where conservative assumptions are made in the analysis providing some guard band Remaining Displays the amount of noise margin that is left over after accounting for all SSN in the bank www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Running Simultaneous Switching Noise SSN Analysis Results are displayed in red when over 100 of the available margin is lost to SSN The SSN predictor arrives at this value by subtracting the bank total predicted SSN a per bank number from the noise margin of I O standard a per group number Result Displays a Pass or Fail condition with failures displayed in red Notes Displays information about the I O bank or groups The SSN results are relative to the state of the design when the SSN Analysis is run It is not a dynamic report Resolving SSN Issues PlanAhead User Guide UG632 v 11 4 When a violation occurs there are a number of ways to improve the results The offending group s can be spread across multiple synchronous phases If the Result is a Fail condition assigning phase groups to ports that are switching concurrently See Defining the I O Port Switching Phase Groups The offending group can be spread across multiple banks This reduces
251. floorplan run result is imported the results are displayed with the same Floorplan view layout tab Running Bitgen on an Implementation Run 208 Once a run has been completed the ISE Bitgen command can be run on the results to create the bitstream data To do so 1 Select the desired completed run in the Design Runs view 2 Select the Run BitGen command from the popup menu The run Bitgen dialog box will appear www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Creating Strategies G Run Bitgen Number of Jobs fi v Options i a d teh O O O O O O O O O oO BB seo faa ce tag a More Options Name Description Figure 7 33 Setting Bitgen Options The Bitgen command options can be set prior to running the command Selecting an option will display a description of the option intent in the dialog box A pulldown menu of the available options values is presented on the right side 3 Click OK to start the bitgen command The command status can be viewed in the Run Properties Monitor tab and the Bitgen report file can be viewed in the Run Properties Reports tab The resulting bit file is generated in the Run directory Creating Strategies Creating Synthesis and Implementation Strategies PlanAhead User Guide UG632 v 11 4 A strategy is a set of command options for each ISE implementation command PlanAhead is shipped with several commonly used Strat
252. for the design Synthesis Options Click the file browser button and enter an optional top level VHDL Library name Verilog or VHDL Options or a Loop Count in the Synthesis Options dialog box Part Select a target part or accept the default 3 Click Next to bring up the Choose Strategy dialog box PlanAhead User Guide UG632 v 11 4 www xilinx com 189 190 Chapter 7 Implementing a Design g XILINX Run Multiple Strategies Choose Synthesis Strategies Create and configure one or more synthesis runs using various flows and strategies Create Synthesis Runs Name Strategy synth_1 Plan amp head Defaults XST 11 synth_2 Timing WithIOBPacking XST 11 Runs to create 2 Figure 7 7 Choose Synthesis Strategy Select a Name and Strategy for the first synthesis Run Select the More button to add more runs Enter names and choose a synthesis strategies for the additional Runs MSY Or A Click Next to invoke the Launch Options dialog box For more information on specifying Launch Options see Creating and Launching a Single Synthesis Run 8 Click OK to create the defined Runs and execute the specified Launch options Synthesis Methodology Tips The following are suggestions on a logic synthesis methodology For more information on optimizing ISE synthesis results see the Xilinx Synthesis and Simulation Design Guide 1 To the extent possible partition the design at
253. from C Xilinx 11 1 Plandhead parts xilinx virtex51x 5v1x50 324 550Rules xml INFO HD GDRC 0 Loading list of dres for the architecture C Xilinx 11 1 Plandhead parts xilinx virtexSlx dre xml Command gt hdi floorplan close name floorplan_2 project project_adder Command gt SESIO EEEE E Figure 4 12 Console View Using the Tcl Command Line The Command Line shown above enables manual command entry using Tcl format PlanAhead commands Commands are entered by clicking on the command line and PlanAhead User Guide www xilinx com 105 UG632 v 11 4 106 Chapter 4 Using the Viewing Environment g XILINX typing them in the Command dialog box entry Every editing command that can be performed using the menu or direct manipulation e g drag amp drop has an equivalent Tel command When invoking a command in the interface i e menu or direct manipulation the equivalent Tcl command is invoked and displayed on the message area and written to the planAhead jou file Command history can be accessed using the Up arrow and Down arrow keys in the Command Line window Using Tcl Help Command line help is available for all commands by using the following syntax at the command line Command gt hdi or Command gt help More detailed information about the commands can be retrieved by extending the help query Command gt hdi pblock For explicit command syntax perform the command once and then view th
254. g Implementation PlanAhead refers to the process of running the ISE command sequence of ngdbuild map par trce and xdl as implementation The bitgen command can be run separately from the PlanAhead environment after satisfactory implementation results are achieved PlanAhead automatically runs these commands and enables you to review and analyze the results The run data is all stored in the project directory for future retrieval of bit files Creating and Launching Implementation Runs Implementation Runs can be created and launched simultaneously or created configured and launched independently Creating and Launching a Single Implementation Run PlanAhead User Guide UG632 v 11 4 1 Select one of the following commands Select the Run Implementation main toolbar button q gt Figure 7 8 Run Implementation Main Toolbar Button Select the Tools gt Run Implementation command The Run Implementation dialog box appears G Run Implementation Run Name impl_1 Description ISE Defaults including packing registers in IOs off Synthesized Netlist pv synth _2 xcSvlx30FF324 1 v Floorplan Part xc5vlx30ff324 1 CJ Constraints CJ CJ Strategy ISE Defaults ISE 11 Launch Options Launch with 2 jobs on local host xcobrianj30 i Cancel Figure 7 9 Run Implementation The Run Implementation dialog box contains several options and editable fields
255. g PlanAhead Description FPGA hierarchical floorplanning and analysis software tool Syntax planfhead help yes no mode lt gui batch tcl gt init yes no source lt list of names gt genJour nal yes no appJournal yes no journal lt string gt genLog yes no appLog yes no log lt st ring gt ise yes no Arguments I Name Type Optional Default 7 Description I help I boolean I yes Ino I Display comand Line syntax I Imode lenm lyes lgui I Invocation mode linit I boolean I yes Ino I Source the plan head tcl file I source list of nanes yes I I Source the specified TCL file I genJournal boolean I yes yes 1 Generate a jounal file I appJournal boolean lyes l Open Journal File in append mode Deea erra u j rine Journal iere ititisid Ieo e e a a laa lea le l Ime Fille in append me i Lia lamo lee plarhead log Log filename Ol lise boolean e e E Project Navigator integration mode Figure 2 3 The planAhead Command Arguments Using a PlanAhead Startup Tcl Script The PlanAhead Tools gt Run Tel Script command can be used to run a startup script PlanAhead Tcl commands copied from the planAhead jou file can be used to create startup scripts For more information regarding the PlanAhead journal file see Outputs for Reports Oe ee ae ee ea a a ee eee PlanAhead version JPA 91 0 Built by bdeeg
256. g TRCE timing results 274 Undo Dragging 122 Unfixed constraints 315 Unhighlighting objects 280 Update Netlist 61 62 V Viewing environment 95 Common popup menu and view specific toolbar commands 251 Configuring tool shortcut keys 118 Configuring views Auto hiding views 100 Defining view locations within viewing areas 121 Defining viewing area sizes 101 Manipulating views using view banner commands 100 Moving views to other viewing areas 121 Opening views 99 Resetting views back to the de fault layout 123 Restoring views to original loca tions 123 Saving view layouts 122 Undoing view manipulations 123 Default view layout 95 Selecting objects See Selecting ob jects Setting display options 112 General view defaults 119 Saving and restoring user cus tomized themes 117 Setting Bundle Nets display op tions 115 Setting Default Light or Dark Themes 117 Setting Device view defaults 113 Setting I O view defaults 114 Setting look and feel options 119 Setting Software update check 120 Status Bar 107 Clock 107 Coordinates field 107 Current mode field 107 Information message field 107 Java memory consumption gauge 107 W WASSO analysis 161 Running WASSO analysis 161 Viewing WASSO analysis results 162 Workspace 102 Closing Workspace views 103 Common commands 251 Opening Workspace views 103 Splitting the Workspace 104 Views 102 World view 106 X Xilinx Tech
257. g a Netlist is to supply the design EDIF file for ISE implementation outside of the PlanAhead environment When a Netlist is exported the original logical netlist hierarchy is maintained in the output netlist You can specify an output file name in the Export Netlist dialog box www xilinx com 29 30 Chapter 1 Understanding the PlanAhead Design Flow g XILINX Exported Pblocks The purpose of exporting a Pblock is to write out the EDIF and UCF files for the specified Pblocks to use for ISE implementation outside of the PlanAhead environment When a Pblock is exported PlanAhead will create the netlist based on the Pblock logic assignments The resulting EDIF and module port list are derived and use the PlanAhead physical hierarchy structure A single EDIF netlist is created and it includes all of the logic assigned to the Pblock This provides ultimate flexibility when using a block based implementation strategy The exported Pblock files consist of a single netlist file and constraint file for each of the selected Pblocks during export A block level directory structure is automatically created and maintained simplifying a block based ISE approach Exporting selected Pblocks will create lt pblockname gt _CV subdirectories containing lt pblockname gt _CV edn and lt pblockname gt _CV ucf files Exported IP The purpose of exporting IP is to write out the EDIF and UCF files for specified Netlist modules to be used for creating reusabl
258. g at common instances will not be reported Complex Scenarios Complex scenarios are guided by the following rule of thumb If includes are specified then excludes will take away objects from includes If only excludes are specified then includes are assumed to be all leaf level instances in the netlist Analyzing Timing Results The Timing Results view can be populated with timing results from either TimeAhead or from the ISE trce timing analysis tools Either TimeAhead or Trce must be run first in order to populate the Timing Results view with paths The Timing Results view contains the paths that meet the criteria defined in the Run TimeAhead dialog box as described in Running Timing Analysis When Trce results are imported or when TimeAhead is run with the default options paths are sorted and listed by constraint The Timing Results view is displayed once TimeAhead completes or Trce results are imported www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Analyzing the Synthesized Design Name P Pathi P Path2 P Path3 P Path4 P Paths P Pathe P Paths P Paho P Path 10 a a a E x art K2 E Type Slack 4 From B Constrained Paths 10 Setup Setup Setup Setup Setup Setup a e o 0 155 usbEngine0 usb_dma_wb_in BUZ UO gen_fifo18_36 fgfifo18_36 fblk ins 0 126 usbEngine0 usb_dma_wb_in BUZ2 UO gen_fifo18_36 fgfifo18_36 fblk ins 0 086 usbEngine1 usb_dma_wb_in B
259. g box below allows the definition of the range and color Insert Bin Enter bin range between 0 and From 0 To New bin color 255 255 0 v Cancel Figure 9 17 Insert Bin Dialog Box The ranges are adjusted to accommodate the newly defined range www xilinx com 285 Chapter 9 Analyzing Implementation Results g XILINX 286 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 10 Floorplanning the Design This chapter contains the following sections e Floorplanning Overview e Partitioning the Design by Creating Pblocks e Working with Pblocks e Using Resource Utilization Statistics to Size Pblocks e Placing Pblocks Based on Connectivity e Using the Automatic Pblock Commands e Working with Placement LOC Constraints e Using IP Reuse Capabilities Floorplanning Overview The PlanAhead software supports a floorplanning methodology that allows designers to constrain critical logic in order to ensure shorter interconnect lengths with less delay This methodology involves user interaction with the physical design and is not a push button flow Designers can use the analysis capabilities in PlanAhead coupled with their own knowledge of the design to define a Floorplan aimed at improved performance Floorplanning can be accomplished by creating physical block Pblock locations to constrain logic
260. gated by expanding and collapsing the logic tree Scroll bars are used to view the entire netlist tree The netlist tree dynamically expands and scrolls to display netlist objects whenever they are selected in other views This default is considered the most useful To disable this feature select the Automatically scroll to selected objects toolbar button in the Netlist view www xilinx com 239 Chapter 8 Analyzing the Design g XILINX RI FPGA_RCV_802_11 a Nets 111 B Primitives 426 channel channelInterfaceRx LED decode7SeqDispCK_49_123 receiver RCY_802_11 Nets 55 B Primitives 2 busMuxWrapInst busMuxrap RChainTopInst RChainTop HS Nets 166 B Primitives 58 bitREV_EQUAL bitRev_Equi Nets 58 Primitives 124 bitRevDPR dpram_24b_ BITREVLUT_RCVi BITRE cxMULT_BREi cxMULT_ B Nets 241 Primitives 296 mult12b_IM1_IM2 n mult12b_IM1_RE2 r Nets 27 H 0 BUS1 MULT18X1 0 BUS2 BUF 0 BUSS BUF OB os os _ Constraints Figure 8 23 Netlist View Collapsing the Netlist Tree The entire netlist tree can be collapsed by selecting the Collapse All toolbar button in the Netlist view For more information see Using the View Specific Toolbar Commands The Netlist tree collapses to display only the top level logic modules OQ FPGA_RCY_8
261. ght the string Found usages 1337 usages H A C DatalPlandhead_Designs New_demo src xfft v 607 usages H A C DatalPlandhead_Designs New_demo src wb_conmax_msel v 12 C Data Planahead_Designs New_demo src wb_conmax_rf v 2 C Data Plandhead_Designs New_demo src wb_conmax_top y 52 u C Data Plan4head_Designs New_demo src wb_conmax_slave_if v 15 usages k Occurrences of clk in all project files 1337 x H Console D 1 0 Ports Figure 6 9 Find in Files Results View Elaborating and Analyzing the RTL Design PlanAhead enables you to quickly compile and analyze the RTL sources Elaboration is available to analyze the compiled RTL design prior to running synthesis but is not a required step prior to synthesis All of the RTL source files imported into the project will be elaborated regardless of whether they are compiled as a part of the design during synthesis Elaboration results are not saved with the design Elaboration is run and rerun until the design is synthesized and a floorplan is created 1 Once the design source files have been imported into the Project select one of the following commands to elaborate the design Select Tools gt Run Elaboration Select the Run Elaboration popup menu command The Run Elaboration dialog box opens PlanAhead User Guide www xilinx com 173 UG632 v 11 4 Chapter 6 Creating and Analyzing the RTL Design g XILINX
262. ght to help guide the ISE tools The automatic placement features available in PlanAhead are not a shortcut to floorplanning the design You may still need to make partitioning decisions and shape Pblocks accordingly to ensure that non SLICE based logic is accounted for in the Pblock areas Automatically Creating Pblocks PlanAhead User Guide UG632 v 11 4 The Auto create Pblocks command is an automatic partitioning tool that can operate on either the top level of the netlist or at any logical instance level in the netlist By default the Auto create Pblocks command starts at the top level and works down the hierarchy one module at a time It can create a Pblock for each logic module in the underlying netlist or it can be filtered to only create a subset This command will automatically place the instances into Pblocks and name them accordingly www xilinx com 311 Chapter 10 Floorplanning the Design g XILINX To run the Auto create Pblocks command 1 Select Tools gt Auto create Pblocks The Auto create Pblocks dialog box appears Note Pblocks can be preselected to seed the Auto create Pblocks dialog box G Auto create Pblocks Pblock to partition Maximum number of Pblocks to generate Process instances with primitive count of at least Preview 10 Pblocks are going to be generated For the Following instances cpuEngine cpu_iwb_dat_i cpuEngine cpu_iwb_dat_o usbEngine1 usb_dma_wb_in cpuEngine
263. gned to the selected port Select all I O banks associated with the selected clock region Select instance corresponding to the ChipScope debug core Debug Channel Select debug channels that belongs to the ChipScope debug port Select net connected to ChipScope debug channel Select ChipScope debug core corresponding to Instance Figure 4 20 PlanAhead Options Selection Rules Automatic selection is enabled disabled by clicking on the Set column heading Enabling a selection rule will force PlanAhead to select the other affiliated To object types when the From object gets selected Disabling the selection rule will force PlanAhead to only select the From object when it gets selected The default Selection Rules will enable PlanAhead to operate in the most efficient manner We would advise against changing them unless you know what you are doing Setting Selection Ability for Objects in the Workspace Views Object selection is set in the Themes panel of the PlanAhead Options after selecting Tools gt Options For more information about setting object selections see Customizing PlanAhead Display Options Understanding the Context Sensitive Cursor PlanAhead User Guide UG632 v 11 4 The cursor will change the symbol displayed during the command modes described below e Pblock edges and Windows view borders may be stretched when the cursor changes into a horizontal vertical or diagonal stretch bar symbo
264. h 2 Inthe Clear Placement Constraints wizard specify the type of placement constraints you wish to remove Instance placement I O Port placement or both 3 Click Next PlanAhead User Guide www xilinx com 319 UG632 v 11 4 Chapter 10 Floorplanning the Design Instance placement XILINX The next dialog will differ depending on what types of objects were selected prior to invoking the command If nothing was selected it is not shown If a Pblock is selected it defaults to clear the contents of the Pblock If instances are selected it defaults to remove them Additional options are presented depending on the preselected set as shown below Clear Placement Constraints Unplace Instances Specify the primitive instances to be unplaced Instances to Unplace Unplace all primitives belonging to selected Pblock Unplace all instances Do not unplace any instances Clear Placement Constraints Unplace Instances Specify the primitive instances to be unplaced Instances to Unplace ZARN Unplace 302 selected instance Unplace all except for 302 selected instances Unplace all instances Do not unplace any instances Figure 10 44 Clear Placement Constraints Wizard Placement Removal Options Based on Pre Selected Objects 4 Inthe Unplace Instances page select the category of instances to be unplaced 5 Click Next 320 www xilinx com PlanAhead User Guide UG632 v 11
265. h ChipScope g XILINX Set up ChipScope Set up ChipScope Summary 0 debug cores will be removed 3 debug cores will be created Found 3 clocks PlanAhead To create ChipScope core click Finish lt Back Cancel Figure 11 6 Inserting ILA Cores into Design Using the ChipScope Window to Add and Customize Debug Cores Fine grained control over ILA core insertion that is not available in the ChipScope wizard is available in the main ChipScope view The controls available in this window allow core creation core deletion debug net connection and core parameter changes To bring up the ChipScope view select Window gt ChipScope Figure 11 7 Window Select Layout H BA Netlist R RTL Netlist amp Sources Floorplans E Physical Hierarchy Package Pins D I O Ports Constraints g Figure 11 7 Opening the ChipScope Window The ChipScope Window can also be brought into focus in the foreground by clicking on the ChipScope view tab at the bottom of the PlanAhead main window Figure 11 8 334 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Core Insertion Flow ChipScope Q ca 9 chipscope_icon_v1 u_icon sa chipscope_ila_v1 csdebugcore_0_0 A gt CLK 1 S TRIGO 32 chipscope_ila_v1 csdebugcore_O_1 Om CLK 1 i gt B TRIGO 22 at chipscope_ila_v1 csclebugcore_O_2 Ow CLK 1 F gt B TRIGO 24 a 5 Unassigned nets 0
266. h multiple runs For more information see Creating Multiple Synthesis Runs or Creating Multiple Implementation Runs Run Bitgen Invokes the Run Bitgen dialog box to a create bitstream This command is only available for completed implementation runs Export to Spreadsheet Creates a Microsoft Excel format spreadsheet file containing the entire Design Runs table view Viewing and Modifying Run Properties Each run has a variety of run properties that can be viewed or modified Modification of most Run Properties is only possible prior to launching the run Once the run has been launched select the Reset Run popup command to view and edit most Run Properties Viewing the Run General Properties Select the Run and the select the General tab in the Run Properties view PlanAhead User Guide UG632 v 11 4 www xilinx com 197 Chapter 7 Implementing a Design g XILINX 198 Name synth_2 Strategy XST Defaults XST 11 Description XST Defaults Status Not started General Options Monitor Reports Selection Figure 7 16 Setting Synthesis General Properties View or edit the information found in the Synthesis General Run Properties dialog box Name Defines the Run name Strategy Invokes the Strategy chooser to select a Run Strategy Description Defines the Run description Status Displays the status of the Run gt fais 5v impl_1 Name impl_1 Strategy IS
267. he same location Repeat the procedure for each module 328 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 11 Debugging the Design with ChipScope This chapter contains the following sections Overview of ChipScope Integration in PlanAhead Requirements and Limitations When Using Core Insertion Flow Using the Core Insertion Flow Implementing the Design Invoking the ChipScope Analyzer Overview of ChipScope Integration in PlanAhead The ChipScope Pro integration provides simplified post synthesis insertion and connection of the ChipScope Pro ILA debug cores in the PlanAhead tool A GUI wizard is provided for quick and easy design debug for most situations A non wizard GUI and Tcl command flow are also available for precision debug core and net connection control This flow provides a robust ILA core connection solution without leaving the PlanAhead tool User s Design Logic PlanAhead User Guide UG632 v 11 4 User s Design Logic PlanAhead Chipscope Core Insertion ChipScope ILA Debug Cores X11123 Figure 11 1 Block Diagram of PlanAhead ChipScope Integration www xilinx com 329 Chapter 11 Debugging the Design with ChipScope g XILINX Requirements and Limitations When Using Core Insertion Flow PlanAhead ChipScope integration requires that the Xilinx ISE 11 x tools be installed with PlanAhead for ChipScope Pro debug core inser
268. head sessions For more information see Saving Custom Display Settings Customizing PlanAhead Display Options View display options can be adjusted to control the appearance and behavior of the environment To view or edit the display options select Tools gt Options The PlanAhead Options dialog box will appear All changes take effect after you select the OK or Apply button Clicking Cancel will not initiate any changes You can view and adjust the settings that control the general environment appearance in the Themes Options The options can be viewed or changed in the Themes environment for different areas in the interface The tabs at the bottom of the Themes Options page allow various view setting types to be modified General Device IOs and Bundle Nets Setting General View Display Options The General tab enables you to customize general color and appearance options of the PlanAhead views www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Configuring the Viewing Environment G PlanAhead Options Text Editor lt Planahead Dark Theme Name Graphical Editors Background Foreground Selection Markers Highlight Hierarchy View World View H Schematic Viewer Console Background Foreground Command text Error text Warning text Windows Background Foreground Color Mm 0 0 0 255 255 255 255 255 255 E 255 255 0 255 25
269. hlight Primitives Removes highlighting from the selected primitives If modules are selected the primitive logic objects inside of those modules will be unhighlighted e Schematic Creates a new Schematic view containing the selected logic e Show Connectivity Selects all of the nets that connect to the selected instances This command can be run successively to sequentially select the instances that all of the displayed nets connect to Running it again will then highlight the next group of expanded nets in the logic cone and so on e Show Hierarchy Invokes the Hierarchy view and displays the entire design with the modules containing the selected objects highlighted e Fix Instances Enables you to lock placement of the logic When logic is fixed it is considered user assigned and is exported to ISE by default e Unfix Instances Enables you to remove locked placement e Highlight Highlights the selected objects using the active highlight color e Highlight with Highlights the selected objects using the selected highlight color e Mark Places a mark symbol on all selected elements in the Device view e Select Opens a submenu which lists all selectable objects for the location where the popup menu is invoked This is helpful when trying to select a particular object among a set of overlapping objects e View Opens a submenu of commands Zoom Opens a submenu of commands to expand or shrink the current view
270. ice family with which you are designing These configuration guides contain detailed information on dedicated and shared configuration pins for each mode Plan the Gigabit Transceivers Gigabit transceivers have a set of dedicated pins and might share clock pins with other Gigabit transceivers or I O Clock regions Some device families have a list of user I Os adjacent to the Gigabit transceivers that you must avoid for optimal signal integrity More information can be found in Gigabit transceiver user guides www xilinx com 125 Chapter 5 VO Pin Planning g XILINX 3 Determine pinout requirement for your memory interfaces High speed memory interfaces have specific pinout requirements driven by the memory style width and speed requirements Xilinx Memory Interface Generator MIG generates the required pinouts Refer to the Memory Interface Solution User Guide for more information 4 Evaluate other IP into your design for pinout requirements Some IP for example the PCI IP have specific pinout requirements Use the Xilinx Core Generator tool in the ChipScope Pro Core Generator software to incorporate designs with the required pinouts The Core Generator like MIG generates the required pinouts for relevant IP Define additional I O interfaces Define required I O standards and other attributes a Define the required I O standards and any additional I O attributes for each I O interface address the drive strengths
271. ics to ensure that the RPMs and Carry Chains will fit in the Pblock rectangle 5 Larger Pblocks may need to be partitioned further to provide a finer level of placement constraint granularity As a rule of thumb keep the size of a single Pblock to less than 30 of the chip Smaller Pblocks are generally better Partitioning the Design by Creating Pblocks The process of floorplanning begins by partitioning some or all of the logic in the design to group and constrain it which prevents migration during implementation PlanAhead provides the ability to hierarchically partition the design into smaller more manageable physical blocks Pblocks PlanAhead maintains a physical hierarchy that is independent from the logic hierarchy This enables Pblocks to include logic modules and primitive logic from anywhere in the logic hierarchy Critical or associated logic can be tightly grouped together into a single Pblock which prevents logic migration limits interconnect lengths and reduces delays Floorplanning is initiated by creating rectangular Pblocks in the Device view Pblocks may also be created without rectangles The ISE tools will attempt to group the logic together during implementation Partitioning can be performed manually by creating Pblocks or automatically by using the Partitioner Creating a Pblock will result in an AREA_GROUP constraint being written in the exported UCF constraint file The logic assigned ranges specified and att
272. ide UG632 v 11 4 XILINX Defining Alternate Compatible Parts Gb Make Part Compatible Description Make this floorplan pinout compatible with one of the folowing parts by adding PROHIBIT constraints to the appropriate package pins Compatible Parts xc5vlx155ff1153 xcSvlxSOFF1153 xc5vix85ff1153 Figure 5 12 Select Alternate Compatible Parts 2 You can select any number of alternate parts realizing that the number of available Package Pins for placement might diminish as more parts are selected Prohibits are placed automatically on any unbonded pins in the alternate devices selected A dialog box displays showing the number of package pins prohibited Prohibits placement is dependent on the alternate parts selected The Prohibits can also be viewed in either the Package Package Pins or Device views The Alternate Parts defined can be viewed and managed in the Floorplan Properties view under the Part Compatible tab Note The Make Part Compatible command supports Virtex 5 and Virtex 6 parts only at this time The alternate parts defined for a floorplan can be displayed and modified using the Add Compatible Part toolbar button in the Floorplan Properties view General Part Compatibility Constraint Files Attributes Selection Figure 5 13 Add Compatible Part toolbar button PlanAhead User Guide www xilinx com 135 UG632 v 11 4 Chapter 5 VO Pin Planning g XI
273. ide UG632 v 11 4 Analyzing the Synthesized Design DCI Rules Table 8 6 DCI Rules Rule Name Rule Abbrev Rule Intent Severity DCI Cascade DCICPC Warns the user to load the UCF file into Warning with part other compatible parts and to run DRC compatibility manually to ensure the DCI cascades are valid ClkBuf Rules Table 8 7 Delay Control Rules Rule Name Rule Abbrev Rule Intent Severity BufR amp BuflO BUFRIOC Checks that BUFR and BUFIO driven Error Locations by the same regional clock terminal are placed at mutually routable locations For IOB Rules see IOB Rules DSP48 Rules Table 8 8 DSP48 Rules Rule Name Rule Abbrev Rule Intent Severity DSP output DPOR DSP48 has a register on the output Information registers side to use this register the register should be synchronously controlled Virtex 4 DSP input DPIR DSP48 has a register on the input side Information registers to use this register the register should be synchronously controlled Virtex 4 DSP output DPOP DSP48 has a register on the output Information pipelining side using this pipeline mechanism will improve performance Virtex 4 DSP multiplier DMOP DSP48 output is not pipelined Warning output Pipelined output will improve pipelining performance DSP input DPIP DSP48 has a register on the input side Information pipelining using this pipeline mechanism will improve performance
274. iewing Environment g XILINX 124 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 5 I O Pin Planning This chapter contains the following sections Recommended Method for Pin Planning With Xilinx FPGAs Using the PinAhead Environment Viewing Device Resources Defining Alternate Compatible Parts Importing I O Ports Defining and Configuring I O Ports Placing I O Ports Placing I O Related Clock Logic Removing I O Placement Constraints Configuring DCI_CASCADE Constraints Running I O Port and Clock Logic Related DRCs Running Simultaneous Switching Noise SSN Analysis Running Weighted Average Simultaneous Switching Output WASSO Analysis Exporting Package Pin Information Exporting an I O Port List Recommended Method for Pin Planning With Xilinx FPGAs The recommended pin planning methodology with Xilinx FPGA devices is as follows PlanAhead User Guide UG632 v 11 4 1 Address the device configuration mode you plan to use Most configuration mode shares some pins with the user I O The number of shared pins ranges from a few for serial modes in high pin count packages to a larger number of for parallel modes and smaller packages You must avoid signal contention to ensure successful configuration For more information on device specific configurations refer to the configuration user guide for the dev
275. ilinx com 177 UG632 v 11 4 Chapter 6 Creating and Analyzing the RTL Design g XILINX e Select Schematic from the popup menu B Nets 117 Primitives 1 cpuEngine or1200_top FFtEngine FFtTop matEngine matTop usbEngineO usbf_top lusbEnginel usbf_top wbArbEngine wb_conmax B Nets 1548 mO wb_conmax_maste mi wb_conmax_maste m2 wb_conmax_maste m3 wb_conmax_maste m4 wb_conmax_maste m5 wb_conmax_maste m6 wb_conmax_maste m7 wb_conmax_maste rf wb_conmax_rf 4 b1 s0 wb_conmax_slave_ s1 wb_conmax_slave_ 10 wb_conmax_slave s11 wb_conmax_slave 12 wb_conmax_slave 13 wb_conmax_slave s14 wb_conmax_slave s15 wb_conmax_slave 4 gt Getting Started jG RTL Hierarchy RTL Schematic 2 d Figure 6 17 RTL Schematic View BELARRIA a o hM axe Be e e e SS i E ee i BE m w tt u o E E E lE A The RTL Schematic view works similarly to the Schematic view For more information on traversing and exploring the RTL Schematic refer to Using the Schematic View page 227 Searching for Objects Using the Find Command Once the RTL design has been elaborated the Find command can be used to search for a variety of logic objects using a wide range of filtering techniques Refer to
276. iming report TWX TWR which makes it quite easy accomplish the same task within the PlanAhead environment When launched from Project Navigator these files will be passed to PlanAhead automatically if they are present in the project PlanAhead does not currently support being a cross probe target from ISE Timing Analyzer Timing paths are listed in the Timing Results tab within PlanAhead Selecting individual paths will cause them to be highlighted in the device view PlanAhead goes beyond what Floorplanner could provide in that you can also cross probe a path or group of paths toa schematic based view From the Timing Results tab select the path s to display and select the Schematic option in the right click menu or press the F4 key By providing both physical device floorplan and schematic representations of the timing path all within the same environment you are provided a rich set of views and tools with which you can analyze the timing of your design Should you choose to use floorplanning constraints as a means to help improve timing performance the functionality is completely integrated within the same PlanAhead environment For more information see Chapter 9 Analyzing Implementation Results 92 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Transitioning from Floorplanner to PlanAhead Viewing ISE Implementation Results PlanAhead can import implementation results after running the command line ISE
277. implementation results after running the command line ISE tools The Create New Project wizard has an option to create a Project from ISE results The wizard walks you through project creation prompting for the netlist constraints placement and timing data For information on loading results from ISE Creating a Project with ISE Placement and Timing Results Summary PlanAhead provides most of the functionality you had with PACE and Floorplan Editor and the transition to using it should be quite straightforward When launched from Project Navigator PlanAhead displays only those features that are specific to the requested process and hides the more fully featured PlanAhead environment In contrast when launched in standalone mode the full capability of PlanAhead is exposed While PlanAhead is a very easy tool to learn for pin planning and floorplanning it has considerable more analysis design optimization and design closure capabilities Refer to the PlanAhead documentation including the introductory video for further information http www xilinx com planahead Transitioning from Floorplanner to PlanAhead 90 For the ISE Design Suite 11 1 all FPGA floorplanning functionality will be provided by PlanAhead A fully licensed and fully functional version of PlanAhead is supplied as a standard part of the release This section explains how to use PlanAhead for common tasks that were previously done using Floorplanner mainly d
278. imported from ISE are considered unfixed Placement constraints can be selected and set to fixed using the Fix Instances popup menu command All fixed constraints are exported by default to the ISE implementation tools in order to lock the placement If you wish to lock down unfixed placement constraints export the unfixed placement constraints from the Run Launch Options dialog box the Export Constraints dialog box or the Export Pblock dialog box Understanding Site and BEL Level Constraints Site constraints result in a LOC constraint being assigned to the instance in the saved and exported Floorplan UCF files The logic element is locked to the CLB SLICE site only and not to any specific gate within it INST receiver uartInst G_98_1 LOC SLICE_X49Y69 PlanAhead User Guide www xilinx com 315 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX 316 BEL constraints result in a LOC constraint and a BEL constraint being assigned to the instance in the saved and exported Floorplan UCF files BEL constraints will assign a logic element to a specific gate within the CLB INST channel receiveRE 8 BEL FFX INST channel receiveRE 8 LOC SLICE X59Y2 Assigning Site Location Placement Constraints LOCs A leaf level primitive instance can be placed into a specific device resource site by dragging it from the netlist tree and dropping it onto a specific site Placing instances into s
279. in the design It is a good idea to remove module constraints before updating the netlist Netlists can then be incrementally updated by using the Update Netlist command to import individual modules of the design To do so 1 Select File gt Update Netlist www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Managing Projects The Update Netlist wizard will appear 2 Set the Replace a specific module option in the Update Netlist dialog box to selective update of modules in the design Update Netlist Update Netlist This wizard will guide you through the process of updating your Plan4head project with a new netlist To update your Plandhead project you will need to import a new netlist You may either replace your entire design with the new netlist or specify a particular module from the new netlist to replace one From the current netlist What type of update do you want to perform Replace the entire design Replace a specific module To continue click Next Figure 2 31 Update Netlist Wizard 3 Click Next to continue The Import Netlist dialog box appears Update Netlist Import Netlist Specify the Edif netlist that contains the top module and optionally a list of directories to be used as a search path during netlist reading Netlist file C Data Plandhead_Projects Plan4head_Tutorial labs design_fi Netlist directories C Data Pland4head_Projects Pland4head_Tutorial
280. ined by the Pblock Assign selected instances Select to assign the selected instances to the new Pblock Occasionally users inadvertently have logic selected which is not intended for assignment 6 Click OK to create a new Pblock The Pblock will be displayed and selected in the Device view and the Physical Hierarchy view The initial Pblock size and location are not critical during manual creation Pblocks can be appropriately sized and located by using dynamic Resource Utilization Statistics in the Pblock Properties dialog box Pblocks can be placed appropriately by viewing the connectivity display in the Device view Sometimes it is helpful to initially create all of the Pblocks with small rectangles to help visualize the connectivity flow between the Pblocks prior to attempting sizing www xilinx com 289 Chapter 10 Floorplanning the Design g XILINX il Package J Figure 10 3 Pblocks in the Device View Using the New Pblock Command The New Pblock command will simply create in new Pblock in the Physical Hierarchy view but will not create a rectangle in the Device View You should pre select logic for assignment to the new Pblock If no logic is pre selected an empty Pblock is created To create new Pblocks with or without pre selected logic select New Pblock from the popup menu Note Certain floorplanning advantages can be gained by creating Pblocks without rectangles Logic assigned to the Pblock will re
281. ing Or you can repeat the steps above to set the view back in place To move a view to a complete different docking area such as moving the Constraints view to the Properties view drag the tab of the view you are moving to the banner of the destination docking area 1 Click the tab 2 Drag it to the banner of the destination docking area 3 Release the tab to place the view and its tab Creating Custom View Layouts Select the Layout menu commands to save and restore default and alternate view configurations For a list of Layout menu commands and a description of each see Layout Menu in Appendix A 122 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Configuring the Viewing Environment Restoring a View Layout A number of commands are available to restore the layout of PlanAhead Views can be docked back to their original locations by toggling the various options previously selected to off again The view banner manipulation commands also act as toggles and can be selected to revert back to the previous setting Restoring the Default View Layout Select Layout gt Load Layout gt PlanAhead Default to undo any changes to restore the default PlanAhead layout Using Undo Redo Commands The previous view manipulation commands can be undone by selecting Layout gt Undo Layout gt Redo can be used to repeat a command PlanAhead User Guide www xilinx com 123 UG632 v 11 4 Chapter 4 Using the V
282. ing Flow PlanAhead has extensive design analysis and floorplanning capabilities that can be utilized at various stages of the design process RTL can be elaborated and analyzed prior to synthesis Synthesized netlists can be explored using target devices and constraints Implementation runs can be imported into the PlanAhead environment for further analysis and floorplanning Implementation results derived from using command line tools can also be imported Specific flow features for design analysis and floorplanning are covered in various sections of this document Input and Output Files Inputs to PlanAhead PlanAhead User Guide UG632 v 11 4 This section briefly describes the formats and processes used while importing design data The input files are as follows e RTL Source Files Verilog VHDL or other design text files e Xilinx Cores NGC NGO e XST Constraint Files XCF e I O Port Lists CSV e I O Port Lists HDL Verilog or VHDL e Top Level Netlists EDIF e Module Level Netlists EDIF e Top Level Netlists NGC e Constraint Files UCF NCF www xilinx com 21 22 Chapter 1 Understanding the PlanAhead Design Flow g XILINX e Xilinx ISE Placement Results NCD XDL e Xilinx TRCE Timing Results TWX TWR While reading the input files PlanAhead writes out any errors warnings and messages in to the planAhead 1og file These messages ar
283. ing the cursor within the Package view actively displays the I O pin coordinates on the top and left sides of the view Additional I O pin and bank information is displayed in the Status bar located at the bottom of the PlanAhead Environment The active object being reported is highlighted in the Package view Holding the cursor over the Package view invokes a tool tip that displays the pin information Ports and I O buffer instances can be dragged into the Package view for assignment They can also be reassigned to other I O pins within the Package view VCC and GND pins are displayed as red and green square pins Clock capable pins are displayed as hexagon pins The colored areas between the pins display the I O banks You can select Pins or banks by clicking them with the mouse Select I O pins or banks to highlight them in the Device view Pins or I O banks that are selected in the Device view are also highlighted in the Package view www xilinx com 131 Chapter 5 VO Pin Planning g XILINX You can display the differential pair pins in the Package view by toggling on the Show Differential I O Pairs toolbar button Ra Figure 5 7 Show Differential I O Pairs Toolbar Button The Package view can be made to appear from the top or bottom of the package by clicking the Show Bottom Top View toolbar button or selecting the Show Bottom Top View popup menu command v Figure 5 8 Show Bottom Top View Toolbar Button There are several i
284. ing the ouput will i results_1 104 violations 4 gt 2 Console D 1 0 Ports Figure 8 49 DRC Results Each violation is expanded in the DRC Results view Errors display a red icon Warnings display an amber icon Informational messages display a yellow icon By default all errors and warnings are displayed Click the Hide Warning and Information Messages toolbar button to hide all warnings and info messages and view only errors Click the toolbar button again to view all errors and warnings once again Figure 8 50 Hide Warning and Information Messages Button Select an error in the DRC Results view list and the specific violation information is displayed in the Properties view Select a blue link in the Properties view to highlight the violating design elements in the Device view Netlist view and Schematic view Violations will no longer be displayed in the DRC Results view after the error condition is rectified and the DRC check is rerun Each time the Run DRC command is run and errors are detected a new results tab is added to the DRC Results view A separate results output file is also created in the PlanAhead invocation directory PlanAhead User Guide UG632 v 11 4 www xilinx com 261 Chapter 8 Analyzing the Design DRC Rule Descriptions The following tables describe the DRC rules rule intent and severity e Floorplan Pblock Rules e Bank Rules e DCI Rules e ClkBuf Rules e
285. ions The Schematic Options enables you to tag source pins with Fanout values and destination pins with Slack values For more information see Annotating Slack Fanout and Values onto Schematic Pins page 233 Adjusting Display using Toolbar Commands The view display can also be adjusted using the following Device view or Main Toolbar buttons Some buttons are active only when appropriate object types are displayed The Toolbar commands are described in Select Menu in Appendix A J B amp Main Toolbar 3 X Device view S Toolbar i Figure 4 25 View Display Control Toolbar Buttons You can hover the cursor over the icons to view the tool tip describing the buttons function 116 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Saving Custom Display Settings Selecting a Theme PlanAhead has default view settings for both light and dark background themes To use either select the PlanAhead Light Theme or PlanAhead Dark Theme options in the Theme pull down menu These default options are defined in the planahead ini file For more information see Configuring the Viewing Environment View Display Options File planAhead ini amp lt theme_names gt patheme Creating and Using a Customized Theme You can save your own custom view settings to create PlanAhead initialization files for use in future PlanAhead sessions To do so click the Save As button next to the Theme pull down
286. ites adds Instance location constraints LOCs to the exported UCF files for ISE The assigned locations will be assigned as fixed and locked during subsequent ISE attempts Before assigning instances click the Create Site Constraint Mode toolbar button to initiate the Create Site constraint mode a Figure 10 36 Create Site Constraint Mode Toolbar Button The dynamic cursor will not allow instance placement to an illegal site or one that is already occupied A legal placement site is indicated when the dynamic cursor changes from a slashed circle to an arrow or diamond The dynamic cursor will not allow instances to be placed if the SLICE will be over packed with logic Certain logic groups such as carry chain logic move as a single object which requires open placement sites for all logic on the carry chain After location constraint assignment is complete return to the default Assign instance to Pblock mode by clicking the Assign Instance Mode toolbar button af Figure 10 37 Assign Instance Mode Toolbar Button To view location constraint properties select the placement constraint and view the Instance Property view Assigning BEL Placement Constraints BELs A leaf level primitive instance can be placed into a specific device gate site by dragging it from the netlist tree and dropping it onto a specific site Placing instances into gates assigns BEL constraints for ISE as described above The assigned locations will be assigne
287. ith the Floorplan name followed by the top level design called ROOT ROOT is considered as the top level Pblock within PlanAhead As lower level Pblocks are created they are displayed in a hierarchical fashion under the Pblock Folder with Child Pblocks appearing under their parent Pblock x 5 orig_fp 8 ROOT 8 pblock_1 pblock_ASIC_BIF_ADDR_O_hNib_ibuf 0 8 pblock_ASIC_BIF_ADDR_O_hNib_ibuf 1 8 pblock_ASIC_BIF_ADDR_O_hNib_ibuf 2 J pblock_ASIC_BIF_ADDR_O_hNib_ibuf 3 pblock_FPGA_RCV_802_11 Figure 8 33 Physical Hierarchy View Selecting a Pblock will also select all of the logic assigned to it Understanding the Physical Hierarchy Icons The Physical Hierarchy tree utilizes several icons that can help you identify the state of the various objects This display automatically updates as the physical hierarchy is manipulated As Pblocks are created they appear in a hierarchical fashion in the Physical Hierarchy view Each folder type in the Physical Hierarchy view displays a number in parenthesis detailing the number of objects in that folder as shown in Figure 8 34 Each instantiation of an RPM is displayed in the Physical Hierarchy View If RPMs are assigned to Pblocks they appear in an RPM folder under the Pblock Selecting an RPM in the Physical Hierarchy view will also select all of the logic contained in the RPM Pblocks with instances assigned Pblocks with instances assigned and wi
288. ive schematic fit view e Select Primitive Parents only available when instances are selected Selects all of the parent logic modules of the selected logic www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Floorplanning Environment Annotating Design Information in the Schematic Annotating Slack Fanout and Values onto Schematic Pins The PlanAhead Options dialog box Schematic settings enable you to tag source pins with Fanout values and destination pins with Slack values Slack values are not displayed until after TimeAhead is run The PlanAhead Options dialog box is available by selecting Tools gt Options and clicking Schematic in the Options dialog box 1 To annotate these values you must first set the Attribute type field to Pin 2 Select the desired values to annotate on the left side of the dialog box below and use the arrow indicators to move them to the right side labeled Displayed DB Attributes 3 Click OK G PlanAhead Options m _ ey Attribute Types in Themes ED es Available DB Attributes Displayed DB Attributes Selection Rules Slack Am Fanout wa ale 7 D Shortcuts a a Strategies W Text Editor v Figure 8 15 PlanAhead Options Schematic Pin Annotation An example of the resulting pin annotation is shown below PlanAhead User Guide www xilinx com 233 UG632 v 11 4 Chapter 8 Analyzing the Design
289. ives 200 DSP pO 2 5 47 0 output is not pipelined B E cpuEngine or1200_top Pipelining D5P48 ouput will improve 8 Engine fftTop performance Both multiplier adder output can Nets 73 be pipelined a Primitives 2 lt i gt a finst bf B Nets 2314 General Details lt ili Properties amp Selection B9 Netlist Constraints A Name Severity Details ee S All Violations 104 SI a DSP48 73 amp DSP output pipelining OPOP Ee REE eee DSP p0_2_5 47 0 output is not pipelined Pipelining DSP48 ou 5 a DPOP 2 Warning DSP pO_2_6 47 0 output is not pipelined Pipelining DSP48 ouput will improve perfo DSP multiplier output pipelining OMOP DMOP 1 Warning The multiplier output of DSP pO_2_5 47 0 is not pipelined Pipelining the ouput will i DMOP 2 Warning The multiplier output of DSP pO_2_0 35 0 is not pipelined Pipelining the ouput will i DMOP 3 Warning The multiplier output of DSP pO_2_7 47 0 is not pipelined Pipelining the ouput will i L amp I ne Iso dte z P Cam cren m r as Iom te on 2 oun Console PlanAhead User Guide UG632 v 11 4 results_1 104 violations x 41 gt D 1 0 Ports Figure 5 34 DRC Results Each violation is expanded in the DRC Results view Errors display a red icon Warnings display an amber icon Informational messages display a yellow icon By default all errors and warnings are displaye
290. k Commands gt GN 2 Bundle Net 21 Id Name 1 NO a 2 usbEngine1 dma_out BU2 U0 gen_fifo18_36 fofifo1s 3 cpuClk_BUFGP 4 wbClk_BUFGP S Ni 6 usbEngineO dma_out BU2 U0 gen_fifo18_36 fofifo1s_ 7 usbEngineO dma_out BU2 U0 gen_fifo18_36 fofifo1s_ 8 usbEngine0 dma_out BU2 U0 gen_fifo18_36 fofifo18_ gt z rs n z E General Nets Selection Figure 10 31 Bundle Net Properties Nets Tab Adjusting Bundle Net Defaults The color line width and signal count range can be defined in View specific settings in the Themes dialog box Tools gt Options gt Themes For more information on setting Bundle Net defaults see Setting the Device View Bundle Nets Display Options Using the Automatic Pblock Commands PlanAhead enables automatic partitioning and Pblock placement using the Auto create Pblocks command This method is used primarily to create a top level Floorplan to view the data flow of the design and to understand the relative size and relationship between the various logic modules in the design Normally the designer will have some concept of the critical modules and circuitry in the design and begin floorplanning with those modules The automatic floorplanning features are not meant to be used as the only floorplanning methodology They are to be used as a tool to help the designer understand the physical design Floorplanning is a manual process that leverages designer insi
291. k the Place I O Ports in an I O Bank button in either the Package or Device view ih Figure 5 21 Place I O Ports in an I O Bank Button The group of I O ports is attached to the cursor when it is dragged over a package pin or I O pad A tool tip displays how many pins can be placed in the selected I O bank 3 Click on a pin or pad to assign the selected I O ports www xilinx com 143 Chapter 5 VO Pin Planning g XILINX Place 36 of 36 ports fps X a Huanu ewan WERK huet ph ppan Aen BASA en Hew Mewes Hee ween we as Keee wee ene ante S606 Veen Hank SHH tthe Figure 5 22 Placing I O Ports in I O Banks 4 Ifmore I O ports are selected than will fit in the I O bank the command is continued The cursor will drag the remaining I O ports to the next I O bank selected and so on until all of the I O ports are placed or until you press the Esc key Moving the cursor within the Package view will actively display the I O pin coordinates on the top and left sides of the view Additional I O pin and bank information is displayed in the Status bar located at the bottom of the PlanAhead Environment The active object being reported is highlighted in the Package view Holding the cursor over the Package view will invoke a tool tip that displays the pin information Ports are assigned in the order they appear in the I O Ports view The assignment order can be adjusted by applying sorting techniques in the I O Ports vie
292. kout length Breakout width Other PCB parasitic inductance Socket inductance Capacitance per output driver gt 600 0 mV 15 0 pF 62 0 nils 12 0 nils 33 0 nils 12 0 nils 0 0 nH 0 0 nH Allowed Utilization Status 100 100 100 100 100 100 100 100 100 100 100 LANH 22 3 42 7 20 1 3 9 3 14 7 42 7 24 24 31 3 10 7 L L OK OK OK OK OK OK OK OK OK OK OK Or Figure 5 41 v fil Package Device FH WASSO results_1 x 1 gt 6 WASSO Results Notice that the report lists allowable loading utilization and status for I O banks and neighboring pair Exporting Package Pin Information The device package pin information can be exported from PlanAhead to a CSV format file The exported information includes information about all of the package pins in the device as well as design specific I O Port assignments and their configuration The package pin section of the exported list makes a great starting point for defining I O Port definitions in a spreadsheet format Refer to the Importing I O Ports section in this chapter for information on the exported CSV file format PlanAhead User Guide UG632 v 11 4 www xilinx com 163 Chapter 5 VO Pin Planning g XILINX Exporting an I O Port List The I O Port list can be exported from PlanAhead to an HDL UCF or CSV format file for use with RTL coding or PCB schematic symbol
293. l e Pblocks or instances may be moved when the cursor changes into a hand symbol e The cursor changes into a cross symbol when rectangles are expected to be drawn for zooming in defining pin assignment areas or drawing Pblock rectangles e When objects are dragged over illegal placement sites the cursor displays a slashed circle symbol www xilinx com 111 Chapter 4 Using the Viewing Environment g XILINX e When objects are dragged over legal placement sites the cursor displays a move point to point symbol Configuring the Viewing Environment 112 PlanAhead has many user configurable viewing options The tool ships with default settings which can be customized For more information see Customizing PlanAhead Display Options View layout configurations can be saved and restored for use in subsequent PlanAhead sessions A separate layout is stored for the PinAhead Project and Floorplan environments A layout file is also created to restore the overall PlanAhead window size and location The view configurations are stored in your home directory when exiting PlanAhead For more information on the layout of configuration files see Outputs for Environment Defaults Several alternate Floorplan environment layouts are supplied with the PlanAhead software The available layouts present the most pertinent information in the most productive way You may save view configurations Themes for use in future PlanA
294. l change to a slider symbol allowing view border stretching The active view displayed in any viewing area is toggled by using the tab interface at the bottom of the view area Selecting the view tab will make it active M Netlist Constraints Figure 4 5 Netlist View Tab is Selected Double click the view tab to display the view in the full screen Workspace views can be restored by double clicking the view tab again Non Workspace views can be restored by selecting the Maximize restore icon in the view banner For more information see Manipulating Views using the View Banner Commands The viewing areas can be split either horizontally or vertically to display multiple views at once Each split area can dock multiple views The possible configuration options are quite extensive Each view has a control box to manipulate the view The views can be floated hidden maximized or closed Closing the view or viewing area will force the other views to resize and claim the space Control box commands are covered later in this chapter The Workspace behaves differently than the rest of the view docking areas The view types that can be assigned to it are fixed They include the Device Schematic Hierarchy and Package views as well as the timing path reports RTL Editor WASSO analysis results ISE software reports and the Getting Started page Multiple views of each view type can be opened and interacted with simultaneously in the Workspace
295. lace Unplace 6 selected ports Unplace all except For 6 selected ports Unplace all ports Do not unplace any ports Cancel Figure 10 48 Clear Placement Constraints Wizard I O Port Removal Options Based on Pre Selected Objects 4 Inthe Unplace Ports page select the category of I O ports to be unplaced 5 Click Next Clear Placement Constraints Fixed Placement All of the ports you are about to unplace are marked as Fixed Do you want to unplace these fixed ports Fixed Ports Do not unplace any fixed ports Figure 10 49 Clear Placement Constraints Wizard Filter Fixed Constraints 6 Inthe Fixed Placement page specify whether or not to unplace the fixed instance s Fixed instances are those you placed or fixed in your design or those imported in the input UCF files PlanAhead User Guide www xilinx com 323 UG632 v 11 4 324 Chapter 10 Floorplanning the Design g XILINX 7 Click Next 8 Verify the contents of the Summary page and click Finish The specified I O ports assignments are removed from the design Previously assigned ports are not cleared prior to reading a new UCF file New port assignments write over previous assignments It is best to first clear all port assignments prior to importing new port assignment constraints Moving Pblocks with Placement Constraints Assigned A Pblock with location constraints assigned can be moved All placemen
296. lanning tasks For a full description on how to invoke PlanAhead in a standalone mode see Chapter 2 Creating and Managing Projects Depending on what stage you are in the design flow you can start in the Empty Design Pre Synthesis or Post Synthesis modes These modes are similar to capabilities that were provided in PACE and Floorplan Editor Empty Design amp Pre Synthesis I O Pin Planning PlanAhead User Guide UG632 v 11 4 In Empty Design mode you launch PlanAhead standalone with no pre existing HDL or netlist files Select Do not import sources at this time in the New Project wizard to open PlanAhead in the Empty Design mode In Pre Synthesis mode you have a Verilog or VHDL file that contains at a minimum the top level ports of the design a CSV spreadsheet or a UCF constraint file In PlanAhead select File gt Import I O Ports gt From HDL CSV UCF to import I O Ports into an empty project In these modes PlanAhead is typically used as an early pin planning tool Note Be aware that in the absence of a synthesized netlist no clock Ports or related clock logic is recognized You must be very careful to place clock Ports accordingly When a synthesized netlist is used as input many more clock diff pair GT and clock related logic placement capabilities and design rule checks are available Common tasks supported in this Empty Design mode are e CSV Import Users often start pin planning with a simpl
297. lans from the right click menu in the Floorplans 72 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Working with Floorplans View You can also display information about the Floorplan in the Floorplan Properties view Select Window gt Floorplans to open the Floorplans view Id Name Device State 1 floorplan_1 4 lx25 Open 2 original_fp 4 lx25 Open BS Dees Open Floorplan Properties Ctrl E X Delete Delete Save s New Floorplan Copy Floorplan Close Floorplan Export to Spreadsheet GQ Properties Selection Figure 2 41 Managing Multiple Floorplans Multiple Floorplans may be created or opened simultaneously to explore design device or constraint alternatives Each Floorplan created references the active imported netlist The active Floorplan can be toggled by clicking the desired Floorplan tab G Project_2 C Data PlanAhead_Designs PlanAhead_Tutorial labs projects Project_2 Project_2 p File Edit View Tools Window Select Layout Help Cog eoerRekhx 600KHO89 Mx cp ESS E Project Project_2 E Floorplan orig_Fp xc2v1000Fq456 4 Figure 2 42 Selecting Desired Floorplan to View Opening multiple Floorplans will use additional system memory so be careful not to open too many Viewing or Editing Floorplan Properties Information can be displayed for any object in the PlanAhead software by selecting an object and examining the information
298. layout or project_layout The overall PlanAhead window size and location is saved in the C Documents and Settings lt Username gt Application Data HDI lt version_number gt layouts application_layout directory On Linux the data is created and stored in HDI directory Shortcut Schema default xml Accelerator key definitions or shortcut schema are created when using the Options dialog box These schema define a mapping from keyboard shortcuts to PlanAhead commands For example the keystroke Ctrl F by default maps to the Edit gt Find command You may define and configure multiple schemas all of which are stored in the default xml file On Windows this is often in C Documents and Settings lt Username gt Application Data HDI lt version_number gt shortcuts On Linux the data is created and stored in HDI shortcuts Strategy Files lt strategyname gt psg Strategy files contain your specified default command line options for all of the ISE implementation commands You can apply a strategy to any given ISE attempt using PlanAhead You can either create strategies from scratch or copy one of the factory supplied strategies User defined strategies are stored in your home directory On Windows this is often in C Documents and Settings lt Username gt Application Data HDI lt version_number gt strategies For Linux the data is created an
299. le gt Import Placement or File gt Import TRCE Results command For more information see Chapter 3 Using PlanAhead With Project Navigator www xilinx com 273 Chapter 9 Analyzing Implementation Results XILINX Analyzing Placement and Timing Results 274 Exploring Xilinx TRCE Results PlanAhead enables you to import timing reports TWX or TWR generated by the Xilinx trce command Once imported all signal tracing and viewing capabilities which include path selection highlighting and tracing are available for analyzing the trce results In the Timing Results view each imported timing report is displayed in a separate tab each tab displaying the user specified results display name Planahead provides links to data sheets for more information about timing delay name parameters PlanAhead e Links the timing report delay name parameters to the appropriate device data sheets e Enables you to search data sheets for the matching timing delay name parameter and displays the data sheet search results Note If the searched timing delay name parameter is not available in any data sheet PlanAhead indicates that no results are found For more information about importing trce results refer to Importing Run Results and Importing ISE TRCE Timing Results into an Existing Project Viewing Timing Paths in the Device View You can view timing paths in the Device view in the Workspace when you select a path ro
300. le for certain object types Note Some of the object types are device specific so they have no effect in some devices Setting the Device View Bundle Nets Display Options The characteristics of the Bundle Nets displayed in the Device view can be configured using the Bundle Nets tab The signal count ranges for the desired bundles can be adjusted using the From and To columns Each column represents a Bundle Net range which can be configured independently The check boxes can be toggled for the desired display effect In the Display column toggle the check boxes off to hide the Bundle Net range in the Device view In the Select column toggle the check boxes off to make the Bundle Nets unselectable in the Device view They will still be visible if the Display toggle is on PlanAhead User Guide UG632 v 11 4 www xilinx com 115 Chapter 4 Using the Viewing Environment g XILINX ZB PlanAhead Options Plan amp head Light Theme Delete From To Display Select Width Color 1 1 1 M161 0 70 2 2 WE 153 102 0 21 60 4 M255 102 0 61 6 WE 255 0 0 8 MMO 0 204 10 B51 204 0 12 Wo 0 0 KKEKKEE KKEKKEEE General Device I Os Bundle Nets Figure 4 24 Theme Options Bundle Net Settings The line width the Bundle appears in the device view can be set for each Bundle Net range by adjusting the values in the Width column Configuring Schematic Slack and Fanout Display Opt
301. le or the floorplan name used for the run URI Strategy Displays the strategy assigned to the Run Strategies appearing with an indicate that the command option values in the Strategy have been overridden in the Run Properties Options tab Status Indicates run status or the command that is currently running Progress Indicates overall progress of the entire ISE command sequence from ngdbuild through xdl The Progress bar is non linear in that some steps may take considerably longer then others Start lIndicates the time ISE started working on the design Elapsed Indicates the total elapsed time for all ISE commands run on the design Device Utilization for Synthesis runs only Indicates the resulting LUT utilization for the run Fmax for Synthesis runs only From the XST synthesis report indicates the expected clock frequency for the run www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Monitoring and Configuring Runs Timing Score for Implementation runs only Indicates the current Timing Score on the run in progress or after completion Unrouted Nets for Implementation runs only Indicates the current number of unrouted nets on the run in progress or after completion Description Displays the description associated with the run This description is initially set to a strategy s description when that strategy is applied to the run however the description can be modified later
302. led using the self explanatory options e Miscellaneous Controls whether PlanAhead automatically searches the Xilinx website for new software updates and defines how many previously opened Projects are displayed in the Getting Started view Moving Views within Viewing Areas PlanAhead User Guide UG632 v 11 4 Multiple views can share the space within the viewing area by displaying them together either vertically or horizontally Viewing areas can be split by clicking on a view tab and dragging it into another viewing area An outline will guide you to place the view at the correct position The resulting window location can be determined prior to accepting it by watching the moving window outline during the dragging process To move a view to share the space in a viewing area 1 Click the tab for example the Constraints tab in Figure 4 29 2 Drag the tab to the desired location The gray outline will guide you 3 Release the tab at the desired location www xilinx com 121 Chapter 4 Using the Viewing Environment g XILINX Constraints 409 Clk period PERIOD 2 Pad clk offset OFFSET 10 Path delay FROM TO 0 Time groups 390 False path TIG 7 Off chip delay 0 B Physical Hiera a Metrics NB Physical Hiera us Metrics D Netlis OAOE Figure 4 29 Dragging Constraints View to Share View with Other Views To restore the view to its original location select Window gt Undo Dragg
303. lick OK to accept the Remote Host configuration settings www xilinx com 213 Chapter 7 Implementing a Design g XILINX Interfacing with ISE Outside of PlanAhead 214 The PlanAhead software enables you to selectively export files required for external ISE software implementation If you are using PlanAhead for design implementation interfacing with ISE for external implementation is not necessary as described elsewhere in this chapter PlanAhead also enables the creation of a Project based on existing command line based implementation results For more information see Creating an Implemented Design based Project Exporting Constraints Exporting floorplan constraints to ISE consists of exporting a UCF physical constraints file for the entire design or for individual Pblocks To export the floorplan constraints 1 Click the desired Floorplan tab 2 Select File gt Export Constraints The Export Constraints dialog box is displayed G Export Constraints File Name igns v4_color_design projects project_adder original_Fp ucf Export fixed location constraints only i Cancel Figure 7 38 Export Constraints Dialog Box 3 View and edit the definable options in the Export Constraints dialog box File name Enter the file name and location to create the UCF format constraints file Export fixed location constraints only Select this option to export only the user assigned fixed placeme
304. lick and select Schematic from the popup menu To create a Schematic view 1 Using the Schematic View Package PlanAhead User Guide UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX vga_color_bars_inst VGA_COMP_SYNCH VGA_HSYNCH fo VGA_OUT_BLANK_Z SYSTEM_CLOCK VGA_OUT_BLUE VGA_OUT_GREEN VGA_OUT_PIXEL_CLOCK VGA_OUT_RED VGA_VSYNCH vga_color_bars lt uj fi Package Device 2 Schematic x Figure 8 8 Schematic View viv Selecting objects in the Schematic view will also select them in all other views If placement results have been imported the logic and paths are displayed in the Device view Viewing Logic Hierarchy in the Schematic View All upper levels of hierarchy are displayed as concentric rectangles when a Schematic view is generated 228 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Floorplanning Environment amp dct_block_7 dct_unit_1 ea elk det_cos table S260 det_cos_table 8260 det_cos table S250 det_cos_table 8260 det_cos table 3250 det_cos_table 8260 7 det_cos table 8260 _ det_cos_iable 8260 _ dci cos table 5250 7 det_cos table 5260 7 det_cos table 8260 _ ddyo i adi din 3 rap2 re ana det mac 35 115 195 225 57 detu_11s_ 8s_7_1 dctub_11s_8s_7 lt Hil Package Device 2 Schematic x Figure 8 9 Viewing Hierarchy in the Schematic 2 Bs X G x v Is Notice that no pins are displayed f
305. lick the Create ChipScope Debug Port popup menu command or toolbar button The Create Debug Port dialog box appears Create Debug Port Debug Core chipscope_ila_v1 csdebugcore_0_2 Type Port width Options counter_width Disabled exclude_from_data_storage match_type basic match_units 1 Select an option above to see description of it ok J cancei Figure 11 10 Customizing Ports and Options of Debug Cores Select the port type in the dropdown Any configurable options for the port will be displayed in the Options area The port width will start as a default but will expand and contract as nets are added and removed from the port Click OK To remove a debug port in the ChipScope tab select the port and select Delete from the popup menu Connecting and Disconnecting Nets to Debug Cores Nets and busses vectors of nets may be selected then dragged and dropped from the Schematic view or the Netlist view onto the debug core ports Figure 11 11 This will automatically expand the port as needed to accommodate the net selection You can also right click on any net or bus and select Assign to ChipScope Debug Port To disconnect nets from the debug core port select the nets that are connected to the debug core port and select Disconnect Net from the popup menu 336 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Core Insertion Flow File Edit View Tools Window
306. linx com PlanAhead User Guide Chapter 7 Implementing a Design R nnine Synthesis ee vk heehee ei bei Bh ee ees 185 Creating and Launching Synthesis Runs 000 000 cece cece 185 Synthesis Methodology Tips 0 0 cece ccc cece eee eee 190 Running Implementation 0 0 0 0 cece eee eens 191 Creating and Launching Implementation Runs 00000005 191 Implementing Phlocks 2s icce ss cseces ta deseedees beur E EEEE iene eee 194 Monitoring and Configuring Runs 0 0 0 0 c cece eee eee 196 Using the Design Runs View 6 6000 c ce een eens 196 Viewing and Modifying Run Properties 6 6 c cece 197 M naging RUNS eirese Scheie Ewen ibn tp dhe Seren indie pcg ah E EREA EE A elk eta 202 Launching Existing Runs 0 e eee eee eee 202 Resebeinig RUNS o sia iosies cache otto pna iea e aa a aaae ada ahd iine oie REE alate 204 Deleting RUNS resi ce Pha a ead eee 204 Importing Run Resalss lt i can0 scaesoeesy eres cpeayinraeeregeessdaneansan 205 Importing Synthesis Run Results sussun e cece cece 205 Importing Implementation Run Results 0 0 e cece ee eee eee ee 207 Running Bitgen on an Implementation Run 0 0500005 208 Creating Strategies 2 i 1s cis vec eine eee eee ee ad eee eae 209 Creating Synthesis and Implementation Strategies 0 00 0008 209 Creating Common Group Strategies 0 0
307. lished in several ways e Make all RTL changes inside of PlanAhead using the RTL Editor or e Select the Remove from Project popup menu command to delete the modified RTL sources from the project and then select Add Sources to import the newly updated versions or e Add the newly updated sources to the project by selecting Add Sources and the select the Disable popup menu command to disable the outdated sources Using the RTL Editor The PlanAhead RTL environment provides a robust RTL Editor for creating or modifying RTL sources The RTL editor utilizes color coding to distinguish the various types of RTL constructs Multiple files can be opened simultaneously Each open file displays a view tab in the PlanAhead Workspace view which allows easy access to all open files The Project environment enables cross probing to and from the RTL Editor with other views such as the Schematic Elaborate Results Hierarchy and RTL Netlist views ya llibrary IEEE a an 2use IEEE std_logic_1164 all z 3 e 4use IEEE STD_LOGIC_ARITH all g Suse IEEE STD_LOGIC_UNSIGNED all E 6 3 7entity CNT_BCD is x 8 port k 9 CLK in STD_LOGIC baj l RESET in STD_LOGIC ENABLE in STD_LOGIC a 12 FULL out STD_LOGIC 13 BCD_U out TD_LOGIC_VECTOR 3 downto 0 Wiia BCD_D out STD_LOGIC_VECTOR 3 downto 0 15 BCD_H out STD_LOGIC_VECTOR 3 downto 0 16 BCD_T out STD_LOGIC_ VECTOR 3 downto 0 L 18end CNT_BCD 19 20 architecture C
308. list Constraints UCF Select this option to export all or only fixed placement constraints Pblocks Lists the Pblocks selected for export Click the Add and Clear buttons to select and remove Pblocks from the export list respectively Click Next or Finish to continue If Next is selected the Export Pblocks Summary dialog box displays Pblock export selections Click Finish to perform the export PlanAhead will always create a separate EDIF and UCF files for each of the exported Pblocks named lt pblockname gt _CV edn and lt pblockname gt _CV ucf A lt pblockname gt _cCV directory will be created for each exported Pblock containing the Pblock specific files Importing ISE Implementation Results Creating an Implemented Design based Project Creating a project that imports implementation results is described in Creating a Project with ISE Placement and Timing Results Importing Placement Results into Existing Project Placement results from ISE can be imported into PlanAhead Placement constraints will be assigned for all placed logic objects Placement results can be imported for the top level of the design or for individual Pblocks XDL format files are used to import placement results PlanAhead will automatically run the ISE XDL command to create the file from your lt design_name gt routed ncd file To import placement results 1 216 Select File gt Import Placement The Import Placement dialog
309. ll remain active allowing additional logic objects to be selected for viewing connectivity Toggle the toolbar button to turn off Show connections for selected instances mode Moving Placement Constraints To move placement constraints 1 Select a placement constraint by clicking on the Instance in the Device view Netlist view or Schematic view 2 Drag and drop the selected placement constraint to another legal site The primitive instance is assigned to the new site Net flight lines can be displayed from the location constraint to connected Pblocks Moving a logic object that is part of a carry chain will result in the entire carry chain being selected for move The cursor will indicate legal placement sites for the entire carry chain and all objects will move to new relative locations Logic such as RAMs and MULIs can be assigned to sites outside of the Pblock rectangle This allows flexibility when locking placement for these types of logic elements 3 After location constraint assignment is complete return to the default Assign instance to Pblock mode by clicking the Assign Instance Mode toolbar button Sf Figure 10 43 Assign Instance Mode Toolbar Button 318 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Working with Placement LOC Constraints To view location constraint properties select the placement constraint and view the Instance Property view Deleting Selected Placement Constraints Select
310. lly Using the Select Area Command You can draw a rectangle in any of the Workspace views in order to select objects To do so 1 Choose Select gt Select Area or click the Select Area toolbar button R Figure 4 15 Select Area Toolbar Button All objects that the rectangle surrounds or touches are listed in the Select Area dialog box which enables you to filter selection by type J Select Area Objects to select 10 E Pblocks 5 Rectangles 5 Figure 4 16 Select Area Dialog Box 2 Object types can be filtered from being selected by turning off the check box 3 Click OK to select all of the checked objects 108 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Understanding Object Selection Options Selecting Primitive Parent Modules The Select Primitives Parent command enables you to select the parent modules for all selected primitive logic To access the command select Select Primitive Parents from the popup menu available in most views Floorplans are much easier to maintain when logic modules are assigned to Pblocks rather than Primitive logic instances You can easily select a group of timing paths which will in turn select all of the primitive logic instances contained on the paths The Select Primitive Parents command will automatically select the parent modules for all primitive logic selected The originally selected primitive logic is no longer selected The command interpolat
311. log file which captures the contents of the messages created when running PlanAhead commands View Journal File Opens the planAhead jou journal file which cumulatively captures all of the TCL commands from PlanAhead sessions that were invoked Select Menu The Select menu has the following menu items Table A 6 Select menu commands Command Description Unselect All Unselects all selected elements Unselect Type Unselects elements of a particular type Select Area Invokes the Select Area command putting the cursor in draw rectangle mode in the active Workspace view Highlight Highlights all selected objects using the active highlight color Unhighlight All Unhighlights all highlighted objects PlanAhead User Guide UG632 v 11 4 www xilinx com 345 Appendix A Menu and Toolbar Commands Table A 6 Select menu commands Unhighlight U nhighlights selected objects Unhighlight Color U nhighlights elements based on object color Mark Marks selected objects in the Device view Unmark U nmarks current selected object in the Device view Unmark All U nmarks all marked objects Show Source Invokes the HDL Editor highlighting the source of the selected logic Show Definition Restricted to RTL instances of non primitives invokes the HDL Editor highlighting the definition of the Verilog module VHDL entity that is being ins
312. lows easy selection of the clock regions Selecting a clock region will highlight the related I O banks and regional clock resources The Clock Region Properties view displays the resources statistics and logic content of the selected clock region Clock Region Properties Oo x gt i gt ma XOY2 g Physical Resource Estimates A annn Fo waun Ea Pe os ome aden Haven som f wuwu vuu SOC ian ic Type of Site Count F x CEO AEO O A DCI 2 GLOBALSIG 29 IODELAY 60 Dy PMVBRAM 2 Fed I TIEOFF 580 ry DSP48E 8 RAMBFIFO36 8 SLICEL 700 ae SLICEM 260 a ia General Statistics Resources I O Banks F Clock Regions Od Gx i Id Name Row Column 4 1 xovO 0 0 a 2 X0 1 1 0 a a a 4 XOYS 3 0 lt ai lt gt c yowa A a w il ies Clock Regions Selection Constraints Device x 1 gt amp MPaka age x 1 Figure 5 11 Viewing Clock Region Resources Defining Alternate Compatible Parts PlanAhead enables you to select an alternate devices for the design PlanAhead will attempt to ensure that a legal I O pin assignment is defined and will work across all of the selected devices 1 Select the Make Part Compatible popup menu command in the Package view A list of available compatible devices available in the same package are displayed This feature only supports alternate parts available in the same package 134 www xilinx com PlanAhead User Gu
313. ls that were displayed There are view banner Toolbar buttons not described here For information on the View Banner commands see Manipulating Views using the View Banner Commands Using the Workspace Views What are the Workspace Views The PlanAhead Workspace is the graphic viewing area which displays the graphical views and some report and log information The views displayed in the Workspace are the following e RTL Editor e Device e Package e Schematic e Instance Hierarchy e Getting Started jump page 102 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Workspace Views e Reports and log files e WASSO Results Opening Workspace Views The Device and Package views may be opened in the Workspace by using the Windows Main Menu commands Multiple views of the same view type may be opened within the Workspace area For example two Device views can display different areas of the device To open a new Device or Package view select Window gt New Device View or Window gt New Package View The Schematic views are opened a little differently To open a Schematic view 1 Select at least one object to display in schematic format 2 Select the Schematic command from the popup menu press F4 or click the Schematic toolbar button gt A Figure 4 8 Schematic Toolbar Button The Schematic displays in the Workspace Running subsequent Schematic commands will open additional Schem
314. ly converts them to EDIF format during the netlist import process Top level NGC format files generated with XST get converted using the nge2edif command When exporting the design from PlanAhead for ISE implementation the netlist for the top level logic is exported in EDIF format to be used during ngdbuild This is different than the export process for core level NGC or NGO files See below for more information about core or module level netlists Constraint Files UCF NCF PlanAhead supports importing UCF and NCF format files for timing and physical constraints PlanAhead can import multiple UCF files allowing separation of physical constraints I Os and timing constraints Module level constraints that are specific to cores such as NCF files may also be imported For more information see Importing Module Level Constraints PlanAhead supports all of the UCF constraints supported by Xilinx Refer to the Xilinx Constraints Guide for more detailed information about UCF constraints and supported syntax Xilinx ISE Placement Results NCD XDL PlanAhead User Guide UG632 v 11 4 PlanAhead can import ISE placement results using XDL format data XDL data is created automatically when implementation runs are launched from PlanAhead Once the ISE commands have completed satisfactorily an XDL format file can be created from the lt placed_design_name gt ncd file XDL files can be created and placement can be imported for indivi
315. m another FPGA family is found This may result in suboptimal performance C m General N Properties Ay Selection Nets 757 Primitives 11 cpuEngine or1200_top FFtEngine fftTop matEngine Nets 1 B Primitives 73 T rocketio_wrapper_i ROCKETIO T tileO_Frame_checkO FRAME_Cr T tileO_Frame_check1 FRAME_Cr T tileO_Frame_genO FRAME_GEN Nets 60 amp Primitives 7 E _i0035 RTL_GND i equal_51 RTL_equal_9 i J read_counter_i RTL_wi tileO_frame_gent FRAME_GEN tile1_frame_checkO FR Be SooQoqoace tile1_frame_check1 FRA tile1_Frame_gend FRAN tile1_Frame_gen1 FRAME_GEN tile2_frame_check0 FRAME_Cr tile2_frame_check1 FRAME_Cr tile2_Frame_genO FRAME_GEN tile2_frame_gen1 FRAME_GEN Tal tile Frame checkn FRAME rM 252 253 dual_port_block_ram i 254 i 255 ADDRA read_counter_i 256 DIA tied_to_ground_vec_i 31 0 257 DIPA tied_to_ground_vec_i 3 0 258 DOA TX_DATA 259 DOPA TX_CHARISK 260 WEA tied_to_ground_i 261 ENA tied_to_vec_i 262 SSRA tied_to_ground_ij 263 CLKA USER_CLK 264 265 ADDRB tied_to_ground_vec_i 8 0 266 DIB tied_to_ground_vec_i 31 0 267 DIPB tied_to_ground_vec_i 3 0 268 sDOB ft 269 DOPB Je 270 WEB tied_to_ground_i 271 ENB tied_to_gro
316. mand in active PlanAhead session Redo Reverses the last Undo command action Cut Cuts the selected text from the HDL Editor into the clipboard Copy Copies the selected object into the clipboard Currently only floorplans and timing constraints can be copied in PlanAhead Paste Pastes the contents of the clipboard Find Invokes the Find dialog box to search for specific instances or nets Find in Files Invokes the Find in Files dialog box to search for text strings in the selected files View Menu The View menu has the following menu commands Table A 3 View menu commands Command Description Zoom In Increases the scale factor of the active graphical window by a factor of 200 Zoom Out Decreases the scale factor of the active graphical window by a factor of 50 Zoom Fit Fits the entire contents of the active graphical view Zoom Area Invokes Zoom area mode allowing the drawing of a zoom rectangle in the active view Fit Selection Adjust the zoom level to fit all of the selected items in the active window Fit Highlight Adjust the zoom level to fit all of the highlighted items in the active window Fit Markers Adjust the zoom level to fit all of the marked items in the active window Refresh Redraws the graphics in the active window Tools Menu The Tools menu has the following menu commands Table A 4 Tools menu commands Command Description Create Pblocks Invokes the Create
317. may wish to close Projects or Floorplans in order to reduce the memory being used 60 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Managing Projects Closing a Project Projects can be closed from within PlanAhead with the File gt Close Project command Closing a Project will prompt you to save any unsaved Floorplans You may elect to exit without saving the data or you may choose to save the data Netlist updates are automatically saved in the Project as they are executed Updating the Netlist for a Synthesized Netlist Based Project Updating the Top Level Netlist To update an existing Project with a newly synthesized netlist for the entire design do as follows 1 Select File gt Update Netlist The Update Netlist wizard will appear Update Netlist Update Netlist A This wizard will guide you through the process of updating your Plandhead project with a new netlist To update your Plandhead project you will need to import a new netlist You may either replace your entire design with the new netlist or specify a particular module From the new netlist to replace one from the current netlist What type of update do you want to perform Replace the entire design Replace a specific module Pla nAhead To continue click Next Cancel Figure 2 29 Update Netlist Wizard 2 Select the Replace the entire design option from the Update Netlist dialog box to update the entire design netlist
318. ment Chapter 8 Analyzing the Design describes the PlanAhead design analysis capabilities Chapter 9 Analyzing Implementation Results describes the timing and placement analysis capabilities available in PlanAhead Chapter 10 Floorplanning the Design describes how to use the product to create floorplanning constraints Chapter 11 Debugging the Design with ChipScope describes the ChipScope software debugging capabilities now integration into PlanAhead This document contains the following appendices PlanAhead User Guide UG632 v 11 4 Appendix A Menu and Toolbar Commands provides a brief description of menu and toolbar commands Appendix B Installing Releases with XilinxUpdate describes the PlanAhead release strategy and explains how to update the software Appendix C Configuring SSH Without Password Prompting describes how to setup a passwordless SSH which is required for running PlanAhead processes on multiple hosts www xilinx com 7 Preface About this Guide XILINX Additional Resources The following additional resources are available For more information go to the Xilinx website http www xilinx com planahead To find additional documentation see the Xilinx website at http www xilinx com support documentation index htm To search the Answer Database of silicon software and IP questions and answers or to create a webcase with Technical Support
319. menu CZ PlanAhead Options Themes Plan4head Light Theme Na qd Save Theme As Theme name My_Theme Available Themes 4i General Device 1 0s Bundle Nets iil Description Colors for the Floorplar a Color to use for selecte Highlight colors Instance Hierarchy View World View colors Schematic View colors Colors for the comman Color for Tcl command Color for error messag Color for warning mess Colors for all other win If you create your own theme it is a good idea to back up the initialization file that contains the custom settings For detailed information about the default and custom initialization Figure 4 26 Creating a Custom Theme files see View Display Options File planAhead ini amp lt theme_names gt patheme PlanAhead User Guide UG632 v 11 4 www xilinx com XILINX Chapter 4 Using the Viewing Environment Setting PlanAhead Behavior Options Setting Selection Rule Options Selection Rule Options control the object selection settings for all views When you select an object other objects may also become selected e g selecting a Pblock also selects the assigned netlist instances For more information see Selecting Objects Configuring Shortcut Keys Most commonly used commands also have pre defined shortcuts using keyboard key combinations The shortcuts defined are displayed next to the
320. mmary page The Floorplan is initialized and the PlanAhead floorplanning environment is invoked PlanAhead User Guide www xilinx com 51 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX File Edit View Tools Window Select Layout Help Tege GR GOP P gt KAGSE E Project project_adder E Floorplan floorplan_1 xc4vlx25ff668 10 E Floorplan ori Physical Hierarchy og g x Netlist E 5 original_fp P top By ROOT gt Nets E Primitives control_inst control reconfig_module module aj uart_baudClock_inst E uart_rx_inst uar E uart_tx_inst uar E vaa_color_bars_inst Properties lt Properties amp Selection BI Netlist Constraints E Package I O Ports of x World QL Name Dir Neg Diff Pair Location Bank Yo Std Drive Strength Slew Type S o All ports 32 cda VGA_OUT_GREEN 8 Output Multiple 8 FAST VGA_OUT_RED 8 Output Multiple 8 FAST VGA_OUT_BLUE 8 Output Multiple 8 FAST 5 Scalar ports 8 lt E Console D 1 0 Ports SLICE _X42Y16 Post Synthesis Flow 65M of asm KE f Figure 2 19 PlanAhead Floorplanning Environment Note If any warning messages appear in the PlanAhead Console view examine the messages or the PlanAhead log file to identify the design errors or specific issues that may cause problems during implementation Creating a Project with ISE Placement and Timing Results Netlists with ISE implementation results along with co
321. moving the modules after they are imported ISE Launch Scripts jobx bat sh amp runme bat sh amp lt SE_commana gt rst PlanAhead User Guide UG632 v 11 4 ISE launch scripts are automatically created when using the PlanAhead Run Design commands These scripts contain commands and command line options specified in the PlanAhead Strategy The jobx bat sh scripts are located under the Project Runs directory in a jobs subdirectory and will sequentially launch each Run selected The script will call each Run specific runme bat sh script These scripts can also be launched independently www xilinx com 31 Chapter 1 Understanding the PlanAhead Design Flow g XILINX The lt ISE_command gt rst files are created in the run directory in order for PlanAhead to track the progress and status of runs PlanAhead will read these files upon opening the Project and will display the status of the run PlanAhead Terminology 32 Project Each PlanAhead software session initiates an active Project The Project can be created with various input formats depending on the design flow being applied e RTL source files can be imported to create a Project that is suitable for the RTL through bitstream flow e Asynthesized netlist can be imported and used in the netlist through bitstream flow e Anempty Project can be created to explore device resources or to begin I O pin planning as described in Chapter 5 I O Pin Planning
322. n any differential pin pair Prohibiting I O Pins and I O Banks PinAhead provides an Interface to selectively prohibit individual I O pins groups of I O pins or I O banks You can select and prohibit pins in the Package Pins Device and Package views To prohibit I O pins or I O banks 1 Select the I O pins or I O banks in the Package Pins or Package views 2 Select Set Prohibit from the popup menu A red X symbol is placed on the prohibited pins in the Package view and a checkmark is placed in the Prohibit column of the Package Pins view as shown in 140 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Defining and Configuring I O Ports je T gt al R R E T s U w V swe CAPILI Y er re AA 60600000 9999008 Ae nes m lt m Package Pins Zil Name Prohibit Port I O Std Dir Bank Type Diff Pair a S AB7 5UserIO L22N Se aA Vv 5 UserIO L22P A Y7 5UserIO L21N Sh Ww Vv SUserIO L21P SR ABS v 5 User IO L19N D aas 5 User IO L19P Figure 5 18 Setting Prohibits on Package Pins Creating I O Port Interfaces Multiple ports or busses can be grouped together by creating an Interface This aids in pin assignment by treating all of the interface ports as one group Assigning all of the pins simultaneously helps condense and isolate the interface for clock region or PCB routing concerns It also makes it much easier to visualize and manage all of the signals associated with a particula
323. n individual I O pins or I O banks to prevent I O assignment to them You can select and configure any of the Ports or Interfaces using the Configure I O Ports command This command provides a way to set I O standard drive strength and slew type PinAhead supports output to a comma separated values CSV format file for use in PCB schematic symbol creation or the HDL port list Using the I O Ports View The I O Ports view shows the I O signal ports defined in the design These ports can be defined within PlanAhead by importing an EDIF netlist or by importing a CSV I O port list To invoke the I O Ports view select Window gt I O Ports The following figure shows the display Name B E All ports 418 Ds QDRO_DIN 35 T QDRO_ADR 20 QDRO_DOUT 36 B QDR1_DIN 36 QDR1_ADR 20 T QDR1_DOUT 36 DIRAC_SPARE 4 T FRMO_SBFC 3 FRM1_SBFC 3 LED 4 B FRMO_RDat_P 16 G FRMO_RStat 2 Q FRMO_TDat_P 16 B FRMO_TStat 2 Ds FRM1_RDat_P 16 T FRM1_RStat 2 FRM1_TDat_P 16 B FRM1_TStat 2 PCI_AD 32 Ds PCI_CBE 4 D PCI_CBE O D PCI_CBE 1 D PCI_CBE 2 D PCI_CBE 3 Scalar ports 48 D CORE_CLK_P D CORE_RST D DELAYREF_CLK_P lt QDRO_KP lt QDRO_KN I H D A z B my E G ey Ge G 6 Ge Ee E D H Dir Input Output Output Input Output Output In Out Output Output Output Input Output Output Input Input Output Output Input In Out Input Input
324. n the Workspace area displaying Al the pre selected elements New Device View Opens a new Device view in the Workspace area Clear Placement Open the Clear Placement Constraints dialog box This dialog box gt Constraints is seeded based on pre selected objects a Zoom In Ctrl I Enlarges the display in the active window Ox Zoom Out Ctrl O Shows more of the display in the active window m Zoom Area Ctrl R Zooms into a user defined rectangular area se Zoom Fit Ctrl G Fits the active window view IN A Fit Selection F9 Fits the active Workspace view to display all selected objects R Select Mode Enables normal select mode i Select Area Enables menu select mode g Highlight Highlights a selected object r Mark Crtl M Marks selected objects in the Device view Unhighlight All Ctrl K Unhighlights all highlighted objects X 348 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Table A 9 Toolbar commands Toolbar Commands amp Unmark All Removes markers from all marked objects R Unselect All F12 Unselects all selected objects PlanAhead User Guide UG632 v 11 4 www xilinx com 349 Appendix A Menu and Toolbar Commands g XILINX 350 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Appendix B Installing Releases with XilinxUpdate Note This appendix applies to the PlanAhead full version only This appendix cont
325. nAhead User Guide www xilinx com 161 UG632 v 11 4 Chapter 5 VO Pin Planning g XILINX G Run WASSO Analysis Results Name results_1 Output File Device Parameters Maximum ground bounce mY 600 Capacitance per output driver pF 15 Board Parameters Board Thickness mils Finished via diameter mils Pad to via breakout length mils Breakout width mils Other PCB parasitic inductance nH Socket inductance nH Figure 5 40 Run Wasso Analysis Dialog Box The Output File field can be used to specify a report file name and location to write to disk Tool tips are provided when dragging the cursor over each of the entry fields indicating what values to enter Viewing the WASSO Analysis Results The Device and Board Parameter values can be modified to reflect your specific design The analysis is performed across the entire device first and then within each I O bank as they relate to their neighboring I O banks The WASSO Results view displays in the Workspace as shown in Figure 5 41 page 163 162 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Exporting Package Pin Information Package Banks Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Heighbors Bank 0 1 Bank 1 2 Rosi 2 gt Device Parameters Maximum ground bounce Board Parameters Board Thickness Finished via diameter Pad to via brea
326. nabled for these types of operations e PlanAhead does not provide options to rotate mirror or flip composite objects during placement While this was more useful in older device architectures we no longer recommend using these techniques with the current device families e RPM creation Using the Export IP command you can export a block of hierarchy as a separate netlist If objects within that block also have placement constraints those constraints can also be exported This is analogous to Floorplanner s RPM creation capability The main limitation here is that this is limited to pre defined blocks of design hierarchy Export IP does not support an arbitrarily non hierarchical associated set of logic www xilinx com 91 Chapter 3 Using PlanAhead With Project Navigator g XILINX e Pre existing RPMs are better identified within PlanAhead than they were in Floorplanner Existing RPMs are listed in the Physical Hierarchy view and can be floorplanned or examined using the Pblock Properties view statistics e BEL level constraints can also be written out directing objects to specific sites within a slice e g which particular FF within the slice There are two modes within PlanAhead that control this behavior Create Site Constraint Mode and Create BEL Constraint Mode If a object s placement is read in from a placed NCD file unlike with Floorplanner BEL locations are preserved by default e Re creating design hierarchy from a flat
327. nables the implementation tools to fit the RPMs into the area Using Common Popup Menu Commands PlanAhead User Guide UG632 v 11 4 Many of the popup menu commands are available from multiple views The commands listed below are common across many of the PlanAhead views and environments Some of the following commands are only available when logic is pre selected The popup menu commands vary depending on which view is active and what object type is selected The common right click commands and a brief description of each is as follows e Instance Properties Pblock Properties Net Properties Displays the appropriate Properties dialog box e Delete Deletes the selected objects after a confirm dialog box is displayed e Unplace Removes the selected placement constraints e Assign Assigns the selected instance to an existing Pblock A Pblock selection dialog box enables you to select which Pblock to assign the selected instances e Unassign Removes the selected instances assignments from a Pblock e Draw Pblock Enables you to draw a rectangle in the Device view The Pblock is created with the selected instances assigned e New Pblock Creates a new Pblock in the Physical Hierarchy view with the selected instances assigned No rectangle is created e Clear Rectangle Removes the selected rectangles from the Pblock The Pblock is not deleted e Set Pblock Size Enables you to draw a new rectangle in the desired
328. nd Device view display by selecting Window gt New Device View A separate tab will be established for Device view 2 The view can then be split using the dragging technique described in the Splitting the Workspace 226 www xilinx com PlanAhead User Guide UG632 v 11 4 Using the Floorplanning Environment seleorv eral euy 227 or select the Schematic hierarchy structure or to trace s elt amp it le 1 Ble Creating and Analyzing the RTL o 7 G see Chapter 6 n Device 2 x KJ XILINX Selo FS E de S n 7 Schematic Toolbar Button 4E www xilinx com Figure 8 6 Displaying Multiple Device Views Figure 8 Select one or more logic elements A Schematic view can be generated for any level of the logical or physical hierarchy view toolbar button shown below The Schematic view can be used to view design interconnect The Schematic view displays the logic instances or nets selected If only one instance was Logic can be selected directly from the Schematic view for use in floorplanning in the selected the module appears with all pins displayed signal paths for either the elaborated RTL netlist or synthesized netlist For more Device view information about analyzing RTL netlist Design 2 Right c
329. nd elaboration which enable resource estimation and RTL schematic exploration Run DRC Invokes the Run DRC dialog box and enables you to configure and launch the PlanAhead design rule checker Open PinAhead Opens the PinAhead environment layout which enables you to define I O pinout configurations to meet design and device I O requirements Run WASSO Analysis Invokes the Run WASSO Analysis dialog box and generates a WASSO analysis report Run SSN Analysis Invokes the Run SSN Analysis dialog box and generates a Simultaneous Switching Noise SSN report of potential I O issues Virtex 6 designs only Run Synthesis Invokes the Run Synthesis dialog box to create and launch a Synthesis Run Run Implementation Invokes the Run Implementation dialog box to run a implementation strategy using one or more hosts Linux only Run Multiple Strategies Invokes the Run Multiple Strategies dialog box to set up for synthesis runs Run Tcl Script Invokes the Run Script dialog box to execute a Tcl script selectable through file browser Options Invokes the Options dialog box for setting display options selection options shortcut options strategies etc Window Menu The Window menu has the following menu commands Table A 5 Window menu commands XILINX Command Description Netlist Displays the Netlist view RTL Netlist Displays the RTL view Sources Dis
330. nd to the original top level netlist name of the imported EDIF file Exported Constraints When constraints are exported preservation of the original UCF file content and structure is attempted including comments You can specify the output constraints file in the Export Constraints dialog box Exported Pblocks When a Pblock is exported PlanAhead will derive the netlist hierarchy based on the Pblock assignments The resulting UCF will reference the PlanAhead physical hierarchy structure to match the exported EDIF netlist names This provides ultimate flexibility when using a block based implementation strategy The exported Pblock files consist of a single netlist file and constraint file A block level directory structure is automatically created and maintained simplifying a block based ISE approach Exporting selected Pblocks will create lt pblockname gt _CV subdirectories containing lt pblockname gt _CV edn and lt pblockname gt _CV ucf files Exported IP The Export IP command is run on a selected module instance in the design and will export the Pblock logic and placement constraints The exported files will include the EDIF netlist and UCF physical constraints in the original logical netlist format This allows for easier implementation in the next design by keeping the interface identical The exported UCF file can be used to recreate the Pblock placement constraints Identical placement can be duplicated for multiple modules by
331. ndicated by a yellow arrow cursor Other modes include zoom area draw Pblock and an hourglass to indicate that PlanAhead is waiting for your input Information Message Field The second field in the status bar is used to display context sensitive information For example when the cursor is in the device view or the schematic view this field contains the name of the instance directly under the cursor The information message field also contains detailed description of PlanAhead commands when the mouse is over its corresponding toolbar button or menu item Coordinates Field To the right of the Information Message Field is the Coordinates Field As the cursor is moved over BRAM DSP48 etc in the Device view this field displays the name and coordinates If the cursor is over a pin in the Package View this field displays pin information such as coordinates type and name Mode The Mode indicates what type of Project or process step is being used When PlanAhead is invoked from ISE Project Navigator the ISE Integration mode is displayed Java Memory Consumption Gauge The PlanAhead graphical user interface has a 512MB memory limit on Windows or 1GB if the tool is invoked on 64 bit Linux There is a memory gauge in the bottom left corner that shows how much of this memory is utilized If the gauge goes within 10 of the limit you should save work and restart the tool This gauge only shows Java memory consumption Task Manager or Top re
332. ne0 u4 dout 23 3 926 1 407 64162 5 lt gt TRCE impl_2 240 paths TimeAhead results_1 10 paths x i 1 Figure 9 1 Highlighted Timing Paths in the Device View Viewing Timing Paths in Schematic View If you select Schematic from the Timing Results popup menu PlanAhead will generate a Schematic view displaying all of the instances found in the selected paths The Schematic view clearly displays the instances along with the hierarchical modules Figure 9 2 Timing Paths Displayed in Schematic View PlanAhead User Guide www xilinx com 275 UG632 v 11 4 XILINX Chapter 9 Analyzing Implementation Results When the Schematic view is generated on a path all of the objects are displayed When a Schematic view for individual logic instances is generated only the selected instances are All of the instances from a group of paths can be displayed in this manner making it easy Pblock creation popup commands make assignment to Pblocks very straightforward For ZH 2g 5 oO n 0D T DY aD sas FG ob eS E S g l Ey pee Qu o la fa fo o9 a a Eg 5 wb ES Vv sactQ D amp 2 bo Be g oO no og D a N FRR Says bo E v N Oo EL ogc oO ON n Na 2239 5 S2 Darg T iz k o om Begs zE Ee J PL 6 D Boas gt C 5g T gogg PSE EE E SEER ity IV ic Connect Exploring Log Using the Show Connectivity Command The Show Connectivity command highlights all of
333. ng Interactive Design Rule Checking 0 00 0 eee eee eee 143 Placing I O Ports into I O Banks 0 0 0 e eee eee 143 Placing I O Ports in a Defined Area 0 0 0 eee eee eee 144 Sequentially Placing I O Ports 0 000 145 Automatically Assigning I O Ports 000s 146 Placing Gigabit Transceiver I O Ports 0000s 148 Placing I O Related Clock Logic 0 eee eee 148 Removing I O Placement Constraints 0 000 0 e cece cece eee 149 Configuring DCICASCADE Constraints 0 00 ee eee eee 149 Editing a IDC Cascad 6 ia xiii sue ata eed ie er wtp e aE ged Oily ee wien ald A n gabon 151 Running I O Port and Clock Logic Related DRCs 151 Running Simultaneous Switching Noise SSN Analysis 157 Running SSN Analysis Virtex 6 00 666 cee 157 Viewing the SSN Results lt co2 0e0s cee ecteee steed steed cee caeedeieeen vas 158 Resolving SSN IsstieSis 2c ss cead ces diet ae eee diee ed ede a wade 159 Viewing I O Bank Properties 0 06 c ccc cece cece eens 160 Defining the I O Port Switching Phase Groups 000 00000000 160 Running Weighted Average Simultaneous Switching Output WASSO Analys Sieen lt A SRS 1S TE IEE ARUP OEE AE KREIS 161 Running WASSO Analysis Spartan 3 Virtex 4 Virtex 5 0 0 00005 161 Viewing the WASSO Analysis Results nuanua cece eee e
334. nical Support case files to include 25 XilinxUpdate Automatic check for updates 120 360 www xilinx com PlanAhead User Guide UG632 v 11 4
335. nmax_rf v Verilog work C Data PlanShead_Designs NewDemo sr 10 W wb_conmax_pri_enc Verilog work C Data Planahead_Designs NewDemo sr y lt gt Floorplans Figure 6 2 Defining the Display Format for Sources Using the Sources View Specific Popup Menu Commands PlanAhead User Guide UG632 v 11 4 Source files can be added viewed or modified using the Sources view popup menu commands The common popup menu commands are covered in the Using Common Popup Menu Commands page 251 The Sources view specific commands and a brief description of each are as follows e Source File Properties Invokes the Source File Properties view e Enable Source Files Sets the source file status to active for elaboration and synthesis Source files can be toggled between Enabled and Disabled to define source file configurations e Disable Source Files Sets the source file status to inactive for elaboration and synthesis Source files can be toggled between Enabled and Disabled to define source file configurations Disabled Source files appear in a shaded grey color to indicate disabled status e Remove from Project Deletes the selected source files from the PlanAhead project It also removes the files from the PlanAhead project disk location if the files were initially imported into the project e Find in Files Invokes the Find in Files dialog box to enter text strings to search in the selected files The Find in Files Results vi
336. nment For information about the intent and use of the DCI CASCADE constraint refer to the Xilinx Constraints Guide The basic premise of the constraint is to link two or more adjacent I O Banks together for clocking purposes The I O bank with the input clock is called the master and all others are slaves The constraint can be set by preselecting the desired I O Banks prior to running the command or by selecting them within the command dialog box To configure the DCI_CASCADE constraint 1 Optionally select the desired I O Banks to configure 2 Right click and select the Create a DCI Cascade popup menu command G DCI Cascade Editor Id Name Master gt ECE gt Eos a gt ME ers I O Bank 16 Remove f ij Cancel Figure 5 30 Creating a DCI Cascade Preselected I O Banks appear in the dialog box as shown in Figure 5 31 page 150 Select the Add button to include additional I O banks PlanAhead User Guide www xilinx com 149 UG632 v 11 4 Chapter 5 VO Pin Planning g XILINX G Select 1 0 Banks Id Name 6 I O Bank 36 7 IJO Bank 34 I O Bank 16 9 IJO Bank 12 10 I O Bank 35 12 I O Bank 33 I O Bank 14 14 1 O Bank 15 15 I O Bank 32 E w E m m w 11 I O Bank 25 m Aa w w w 16 I O Bank 24 i Cancel Figure 5 31 Selecting I O Banks for the DCI Cascade 3 Select an I O Bank to be the Master 4 Click OK Notice that as I O Banks are selected they are highlighted in
337. noo000000 E cpu_dwb_dat_o FifoBuffer 237 ie ies E cpu_iwb_adr_o FifoBuffer 238 E cpu_iwb_dat_i FifoBuffer 239 Bypases of the IC when IC is disabled E cpu_iwb_dat_o FifoBuffer Ff 240 2 dwb_biu or1200_wb_biu 24l assign icbiu_cyc_o ic_en icfsm_biu_read a T iwb_biu or1200_jwb_biu 242 assign icbiu_stb_o ic_en icfsm_biu_read E or 1200_cpu or1200_cpu 243 assign ichiu we o 1 b0 a o1200_dc_top or1200_dc_top 244assign icbiu_sel_o ic_en icfsm_biu_read E g Oe ene 245 assign icbiu_cab_o ic_en icfsm_burst 1 a I or1200_du or1200_du 246 assign icqmem_rty_o icqmem_ack_o icqnem S E or 1200_ic_top or1200_ic_top edie ea i 247 assign icqmem_tag_o icqmem_err_o OR1200 I 248 249 250 CPU normal and error termination 251 5 Nets 50 B B Primitives 25 0 i1 XILINX_GND C i11 XILINX_AND ag X i i14 XILINX_INY Instance Properties GE i15 XILINX INV 500 Schematic F J i16 XILINX _AND CD i18 XILINX_OR E Show Hierarchy ic_en icfsm_first_hit ic_en icfsm_first_miss F w a we o non D i19 XILINX _MUX si S C i2 XILINX_PWR ye a Fi x CD i20 KILIN MUX Highlight Ctrl H D i22 ILINX_INV C i23 XILINX_OR D i26 XILINX_INV i i27 XILINX_OR C i4 XILINX_AND iS XILINX_OR ORD umn rR An lt iil gt between claddr generated by
338. nt LOC constraints or uncheck it to export all of the fixed and unfixed placement constraints imported from ISE 4 Click OK to export the constraints PlanAhead will create the designated top level UCF format constraint file in the export directory This file can be used as input for custom ISE implementation scripts For more information about the exported files see Outputs for ISE Implementation Exporting Netlist Exporting the PlanAhead Netlist to ISE consists of exporting a single EDIF format netlist file for the entire design or for individual Pblocks To export the design netlist 1 Click the Floorplan tab 2 Select File gt Export Netlist The Export Netlist dialog box is displayed www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Interfacing with ISE Outside of PlanAhead G Export Netlist File Name s v4_color_design projects project_adder project_adder edf Cancel Figure 7 39 Export Netlist Dialog Box 3 View and edit the definable option in the Export Netlist dialog box File name Enter the file name and location to create the EDIF format netlist file 4 Click OK to export the netlist For more information about the exported files see Outputs for ISE Implementation Exporting Pblocks for ISE Implementation PlanAhead has the unique ability to export Pblock level files for implementation These Pblocks consist of logic from anywhere in the logic hierarchy Ex
339. ntax Once changes have been made click Apply to accept the changes or click Cancel to deny the changes Note Failure to click the Apply button will not initiate any changes to constraints values Adding New Timing Constraints To add new timing constraints 1 Click the Create new constraint toolbar button in the Constraints view E Figure 8 31 Create New Constraint Toolbar Button The New Timing Constraint dialog box will appear 246 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Floorplanning Environment G New Timing Constraint Constraint Types Basic period amp Timespec period Clock Nets CK_MIC_O v amp Derived period i amp Input pad to clk offset amp Clk to output pad offse amp Path delay FROM TO amp Basic group TNM amp Multi group TIMEGRP C Duty cycle amp Object false path amp Group false path amp Feedback Period Specification width lo i Cancel Figure 8 32 Create New Timing Constraint Dialog Box 2 Select the type of constraint you wish to create on the left The appropriate fields will be displayed on the right 3 Define the constraint values using the correct syntax Refer to the Xilinx Constraints Guide for more information on constraints and constraint formats 4 To accept the changes click OK Removing Timing Constraints To remove the constraint from the Floorplan select a
340. nth_2 vV synth_1 SY impl_1 Figure 7 25 Launching Existing Runs The Launch Selected Runs dialog contains the following options Launch Directory Specify a location to create and store the synthesis run data Note Defining any non default location outside of the project directory structure makes the project non portable as absolute paths are written into the project files Placement Export Specify to export placement LOC constraints for only user assigned fixed placement or for all fixed and unfixed placement constraints from an ISE implementation run Launch Runs on Local Host Select this option to launch the Run on the local machine processor Number of Jobs Define the number of local processors to use for Runs This option is only used when launching multiple runs simultaneously Individual runs will be launched on each processor No multi threaded processors are used with this option Launch Runs on Remote Hosts Linux only Select this option to use remote hosts to launch job or jobs Configure Hosts Select this option to configure remote hosts For more information see Executing Runs on Multiple Linux Hosts Generate scripts only Select this option to export and create the run directory and run script but not to launch the run from PlanAhead The script can be run at a later time outside of the PlanAhead environment 3 Click OK to create the Run with the select
341. nthesis Run 1 Select one of the following commands Select the Run Synthesis main toolbar button gt Figure 7 1 Run Synthesis Main Toolbar Button Select the Tools gt Run Synthesis command The Run Synthesis dialog box appears G Run Synthesis Run Name isynth_3 Description XST Defaults _ Top Module Name therm Synthesis Options l 7 e Strategy X5T Defaults XST 11 Part xcSvix30FF324 1 Launch Options Launch with 2 jobs on local host xcobrianj30 i Cancel Figure 7 2 Run Synthesis dialog box The Run Synthesis dialog box contains several options and editable fields Run Name Enter a name for the synthesis run or accept the default name Description Enter any description for the synthesis run Top Module Name Enter or accept the top level RTL module name for the design Synthesis Options Click the file browser and in the Synthesis Options dialog box enter an optional top level VHDL Library name Verilog or VHDL Options or a Loop Count Strategy Select the Synthesis strategy to use for the Run You can select an XST version 10 or 11 strategy For more information see Creating Strategies www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Running Synthesis E choose Strategy Tool Version XST 11 v Choose Strate Strategy Description Select Plandhead Strategies Planthead Def Planahead Defaults
342. nu com mands 232 Selecting objects 108 Fitting display to show selected ob jects 109 Highlighting objects See Highlight ing objects Marking objects See Marking objects Selecting multiple objects 108 Selecting objects using the Find com mand 270 Selecting Primitive Parents 109 Selecting Primitives 280 Setting selection ability for objects 111 Setting selection rules 110 Using Select Area 108 Using the Select menu commands 109 Selection view 109 Software update 351 Automatic check for updates 120 Source File Properties 168 Sources view 165 View specific popup menu com mands 167 SSN analysis 157 Running SSN analysis 157 Viewing results 158 Starting PlanAhead 35 Command line options 36 Invocation 35 Using a startup Tcl script 37 Using the Getting Started jump page 38 Synthesis 185 Design resource utilization statistics 253 Exporting 254 257 Runs 185 Importing results for Run 205 On Multiple Linux Hosts 211 355 Strategies 185 209 Creating common group strate gies 211 Creating Strategies 209 Modifying command options 211 Synthesis Options 174 T Timing Analysis 264 Excluding paths from analysis 266 Running TimeAhead 264 Timing Results 266 274 U Displaying path details 269 Removing paths from report 268 Sorting timing report 267 E path reports in Workspace 27 Viewing timing paths in Device view 274 Viewing timing paths in Schematic view 275 Viewin
343. number of signals in them Selecting a Net bundle will display information about the net content in the Net Bundle Properties view You can also traverse down the hierarchy and create submodules for the larger top level instances for more detailed granularity This top level floorplan can be a good indicator of the quality of the I O pinout configuration and can help identify potential routing congestion issues Resource statistics and clock requirements for each module can also be examined to understand potential placement issues Refer to the Using the Automatic Pblock Commands page 311 for more information about creating a top level floorplan Running Design Rule Checks DRC The PlanAhead software contains a set of batch DRC commands that can help verify design integrity prior to running the ISE software The rules are categorized by type of logic checks being performed Running I O Port and Clock Logic DRCs Many of the DRC rules are related to I O pin assignment and clock logic Refer to Chapter 5 I O Pin Planning for information on running I O Port and lock logic related DRCs PlanAhead User Guide www xilinx com 259 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX Running Netlist and Floorplan DRCs 1 Select one of the following commands to run the DRC checks on the design Tools gt Run DRC Select the Run Design Rule Checker toolbar button Figure 8 47 Run Design Rule Checker Toolbar But
344. nvironment There are four processes in the Project Navigator Processes pane from which PlanAhead can be invoked They include e I O Pin Planning Pre Synthesis e 1 0 Pin Planning Post Synthesis e Floorplan Area IO Logic Post Synthesis e Analyze Timing Floorplan Design Post Implementation The data passed between the two tools and the view layout presented in PlanAhead is dependent on which step is being invoked Refer to ISE and PlanAhead Integration Process for more information on the mechanics of the integration including data passing and processes PlanAhead has two default view layouts for the many design tasks One is the I O pin planning environment also called PinAhead which contains views pertinent to I O pin planning and assignment The other is the PlanAhead Floorplan environment which contains views pertinent to design analysis and floorplanning It is important to ensure the proper view layout is loaded for the desired design task For more information about using the PlanAhead Viewing Environment see Chapter 4 Using the Viewing Environment www xilinx com 79 Chapter 3 Using PlanAhead With Project Navigator g XILINX For more information about configuring and loading view layouts refer to Configuring the Viewing Environment ISE and PlanAhead Integration Process Project Navigator and PlanAhead are two independent environments each operating under a separate system process Steps have
345. nx com 297 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX Child Pblocks appear in a slightly different color to differentiate the rectangles Color configuration is available in the Tools gt Options gt Themes gt Device dialog box Pblocks may contain multiple rectangle ranges Multiple rectangle ranges are displayed with dashed lines connecting them to indicate that they are part of the same Pblock The assigned instance rectangles and connectivity display in the largest rectangle RKRIBLRLL OF Figure 10 16 Creating Pblocks with Non Rectangular Shapes Assigning Logic to Pblocks Once a Pblock has been created netlist instances can be assigned to it This can be done by either dragging and dropping logic or by using the Assign popup command To use the drag and drop method 1 Click and drag logic instances from the Netlist Schematic Hierarchy or Find Results views 2 Drop them into the Pblock rectangle area To use the Assign command method to assign logic to existing Pblocks 1 Select logic instances in the Netlist view 2 Select the Assign popup command The Select Pblock dialog box will display the allowable selections of the Pblock assignment 298 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Pblocks d Select Pblock x Assign selected instances to ie ROOT E pblock_1 E pblock_ASIC_BIF_ADDR_O_hNib_
346. nx com 97 UG632 v 11 4 Chapter 4 Using the Viewing Environment XILINX 3 Console View RTL Elaboration Results View Design Runs View I O Ports View DRC Results Find Results RTL Netlist View 5 Workspace RTL Editor Schematic View Hierarchy View Reports Floorplan Environment View Layout TI proje t_mew C WatalPland war Fle View Too Window tepur aadel GogoKkness sxaneag Ryze ee x E Pond projot pew Ptopscal Ger archy arpa E Roorsfie_t am H Physical Hierarchy A So Ptlock Properties e Ri A ROOT Phrracal Resource Estimates Stelype Avalie ut 240 32640 ace uan SCAN DPGCTRL DG VControl_pad_0_o 4 VCortrol_ped_t_o 4 ED OpMode_pad 0o T Mode pad io O Otat pad 0o E LT naout Comsole D 1 0 Ports When a netlist based project is open an empty Project is open or a Floorplan is active the default Floorplan environment layout configuration is displayed For more information about using the views in the Floorplan environment see Chapter 10 Floorplanning the Design 10 Nproject_new p oject_new ppr PlanAhead 11 1 LR Oe oOo 9 EJ LLERS Erat WY Ren gine fda ot WG Enge fusbingnesRAM WW tinget fusb_dna_rb in S p vklrgretfusb in E tlroretib_ot MIXER s wt netist A Coretrorts Bron Foeke x Location Bork Yoxd Drive Strength Stew Type Pd Type Phase 17 LWCMOS2S 12 20W 15 LwCMOS25 12 20w 17 wwoMos2s 1
347. o z Taua 2 e ie oa 3 xOY2 2 o ju Ca u m 4 x0Y3 3 o v LAIJ v 5 x1v0 o 1 5 a E 6 X1Y1 1 1 7 X1 2 2 1 ma 8 X1Y3 3 1 a I si z ols gt Clock Regions Selection Constraints Device x 1 gt Package 1 gt o IO Ports ogax al Name Dir Neg Diff Pair Location Bank Yo std Drive Strength Slew Type Pull Type Phase B All ports 418 a pre Input HSTL_I default be lt Output HSTL_I default Pz ond ADRID C E E E a E E E E gt A lt QDRO_ADR 1 Output HSTL_I default lt QDRO_ADR 2 Output HSTL_I default ZH lt QDRO_ADR 3 Output HSTL_I default Package Pins En E LOR SR S A Name Prohibt Port IOStd Dir Veco Bank Type Diff Pair Clock Voltage LowCap Min Trace Dly Max Trace Dly IOB Alias SiteType 0O00 S SB Al Pins 324 a S E 1 0 Banko 4 be t a I O Bank 1 22 S a I O Bank 2 22 Ds 2 User IO LOP cc False 40 04 46 72 IOB_X1YS9 I0_LOP_CC_RS1_2 cm pulser in tp er race saa Se an IOR i e7 IOL 1P or A25 z TEEN P Package Pins a z R Post Synthesis Flow 43M of 64M w Figure 5 1 PinAhead Environment The I O Ports view displays the I O signals that are currently defined in the design Busses are grouped and displayed in bus folders Differential pair signals and busses are also grouped You can create Custom Interfaces by selecting groups of signals and or busses and then selecting the Create I O Interface command Additional commands are av
348. oap xexaney Rr veoxers Project project_2 Floorplan floorplan_1 xcSvsH35tff665 1 x Physical Hierarchy 9 x Netlist a Tag 5 floorplan_1 E ROOT B E 88 H Primitives 200 cpuEngine FFtEngine FftTo mgtEngine mg Pae nA BB usbEngine1 us wbArbEngine wb_ Properties oi Bb S R k ER A RTE i gt N Properties Selection PI Netlist Constraints H Package Device x Name Type Slack From E Constrained Paths 240 J TS_usbClk PERIOD TIMEGRP usbClk 3 9 ns HIGH 50 30 P Pathi Setup 0 265 usbEngine1 usb_dma_wb_in BUZ UO gen_fifo18_36 fgfifo18_36 fblk inst_Few ki 1 inst_fed one_p usbEngine1 u4 dout 7 P Path2 Setup 0 223 usbEngine1 usb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_36 Fblkfinst_few k1 1 inst_fed one_p usbEngine1 u4 dout 9 2 Paths Setup 0 221 usbEngine1 fusb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_36 Fblkfinst_few k1 1 inst_fed one_p usbEngine1 u4 dout 9 P Path4 Setup 0 098 usbEngine1 jusb_dma_wb_in BU2 UO gen_fifo18_36 fafifo18_36 fbikjinst fewjki 1 inst_fedjone Pp usbEngine1 u4 dout 23 Paths Setup 0 086 usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 Fofifo18_36 Fblkjinst_few k1 1 inst_Fed one_p usbEngine0 u4 dout 23 P Paths Setup 0 050 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_36 fblk inst_few ki 1 inst_fed one_p usbEngine1 u4 inta_msk 4
349. oduce it You may continue to floorplan without the cores imported PlanAhead creates black boxes for the missing logic Then you ll need to copy the NGC core files netlists to the ISE run directory ChipScope Core Netlists ngc PlanAhead is integrated with ChipScope enabling the ILA cores to be inserted and configured interactively An NGC format netlist for the core is compiled when the core is implemented It is placed in the Project netlist directory and copied to each implementation run directory as runs are launched Refer to the Chapter 11 Debugging the Design with ChipScope for more information www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Input and Output Files Constraint Files ucf Currently PlanAhead writes UCF format ASCII files containing timing and physical constraints that are used for ISE These files are created during the following commands e Run Implementation and Launch Runs PlanAhead e File gt Export Constraints e File gt Export Pblocks e File gt Export IP Run Implementation and Launch PlanAhead Runs The exporting of EDIF and UCF data is done automatically when the Launch Runs command is used When a Run is launched a run directory is created containing the original logic hierarchy in the output netlist The exported files for the run consist of a single EDIF format netlist file and a UCF format constraint file for the entire top level design The file names correspo
350. og hn ede p Rae ene 127 Using the PinAhead Environment 0 0 0 e cece eee eee 127 Using the I O POS View tel oe e iaaa Eea uate bapa tern atta and EE eD e 129 Using the Package Pins View 2 6 ccc e oe eia E 130 Using the Package View 0 6 c ccc eens 131 Using the Device View 6 666 en eens 132 Viewing Device Resources 22 4 cx eis c deed eet eeedetie daa erraren rrr 132 Viewing Package Pin Properties 66 cette ees 132 Viewing I O Bank Resources 66 eect eens 133 Viewing Clock Region Resources 0 660 c cece cee ccc cee cence 134 Defining Alternate Compatible Parts 0 0 00 e cece eee eee 134 lmp rting VO Potts ais ree oe ain Renna ws EE EE EE E E oor REE 136 CSV Format Files y sci sda died tant erir E dina edhe E E eaea 136 HDL Format PICS sere pusee e er e Sie a e aera aap e ea 137 UG632 v 11 4 www xilinx com PlanAhead User Guide UCE Format File eco c 22 oe ccnp cs sy ude weatetie oe Geode gnbrtonce Sotbettce e 4 Gea aye eee EEEN 138 Defining and Configuring I O Ports 005 060 s cove beens invade es sae einai 138 Creating I O Ports ereire tiai ie dea ctent E deed etna EE aed dee 138 Configuring I O Ports ced cd Sep aa tersencna te hen ttion Soe aap ela e te eb gre ied done 139 Prohibiting I O Pins and I O Banks 0 6 0 oes 140 Creating I O Port Interfaces 0 6 eee da Eee 141 Placing VO VOUS 6d diceeai cw isiaw does ediktas hind eee Cee E 142 Enabli
351. ogic instances that are placed and assigned to a Pblock display a checkmark and blue stripe in a yellow rectangle Notice the logic types are also displayed dataOut_h 0 FDE EA dataOut_h 1 FDE dataOut_h 2 FDE A dataOut_h 3 FDRE Selecting Logic in the Netlist View Instances can be selected and commands applied to them using the menu Toolbar or mouse context sensitive menu popup menu The Shift key or the Ctrl key can be used to select multiple elements in the Netlist view for use with most commands Selected logic is highlighted in the Netlist view Logic selected by any means in PlanAhead is also displayed as selected in the Netlist view The Netlist tree will automatically expand to display all selected logic You may need to scroll the tree to view all selected logic Collapsing the Netlist tree does not unselect logic Using the Netlist View Specific Popup Menu Commands For more information on the popup menu commands available from the Netlist View see Using Common Popup Menu Commands Using the Constraints View PlanAhead User Guide UG632 v 11 4 PlanAhead provides a view of all of the timing constraints defined in the floorplan constraints are floorplan specific and can vary between floorplans in the same project You can experiment with different constraints devices IO pins etc The Constraints view interface also allows you to modify defined values and to create new constraints To view the
352. om left connectivity right of the device www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 Running I O Port and Clock Logic Related DRCs IOB Rules Table 5 2 1OB Rules Rule Name Rule Abbrev Rule Intent Severity IOB clock TOCS IOB sites are divided into pairs for the Warning sharing purpose of sharing clock routing resources These pairs are normally LVDS pairs as well In some cases there could be routing issues based on how the flops are packed inside the IOB To resolve this issue flops need to be assigned to specific BEL IOB set reset IOSR IOB site has input output and tri state Error sharing registers each of these registers share same set reset signal Will not be able pack registers with different reset signals Differential1 O IODI Differential I O P and N signals Error pads should be LOCed in dedicated differential pair I O Standard IOSTDTYPE Ensures that a Diff pair I O Standard Warning Type has been applied to diff pair pins only Number of IOs IOCNT Indicates whether more I O Ports are Warning defined than there are pins in the target device Non inputs IOPR Checks that a port is not placed on a Error placed on input prohibited pin only pins Diff term loced IOLVDSCC Checks that differential output Error to low standards are not used on low capacitance IOB capacitance sites
353. ommands are described below Table 4 2 Common View Specific Toolbar Commands Toolbar Button Command Description Collapse All Collapses the entire expanded tree as in the Netlist x Constraint and Physical Hierarchy views Expand All Expands the entire expanded tree as in the Constraint a and Physical Hierarchy views PlanAhead User Guide www xilinx com 101 UG632 v 11 4 Chapter 4 Using the Viewing Environment g XILINX Table 4 2 Common View Specific Toolbar Commands Toolbar Button Command Description Automatically Toggles the particular view to automatically expand ia scroll to and scroll the tree to expose newly selected objects or selected objects whether to remain static The default in all windows is to automatically expand and scroll Automatically Toggles the Properties view to automatically update amp update the to display properties for newly selected objects in contents of this other views or to remain static on the selected object window The default is to automatically update Previous Object Navigates backwards through the list of previously selected objects In the Workspace Views cycles back through the various Zoom levels that were displayed Next Object Navigates forward through the list of selected gt objects This button is enabled after you backtrack J y using the Previous Object button In the Workspace Views cycles forwards through the Zoom leve
354. omment with Line Comment Comment with Block Comment These self explanatory commands perform the function described in their titles Run Elaboration Invokes a dialog box to enter the name of the top module and to then launch the RTL analysis routine to compile the design Refer to Elaborating and Analyzing the RTL Design The common popup menu commands are described in the Using Common Popup Menu Commands page 251 Using the Find in Files Command to Search Source Files The Find or Find in Files popup menu commands can be used to search for any given text string in a selected set of source files Any text string including wildcards can be entered as search criteria Filtering options are provided to limit the search based on all files in the project or all open files The forward or backward direction of the search can also be specified www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Elaborating and Analyzing the RTL Design G Find in Files Find what iclk Target Direction All project files Forward All open files Backward Options C Match case C Match whole word C Use Figure 6 8 Find in Files Dialog Box The search results are displayed in the Find in Files Results view A list of files that contain the search string and the number of occurrences in each file are displayed Select any occurrence in the list to load that file into the RTL Editor and highli
355. onfiguration files Copyright C 2005 2009 Mark A Lindner This file is part of libconfig This library is free software you can redistribute it and or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation either version 2 1 of the License or at your option any later version This library is distributed in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE See the GNU Lesser General Public License for more details You should have received a copy of the GNU Library General Public License along with this library if not see http Awww gnu org licenses UG632 v 11 4 www xilinx com PlanAhead User Guide PlanAhead User Guide www xilinx com UG632 v 11 4 XILINX Preface About this Guide The PlanAhead User Guide provides detailed information about the PlanAhead software including an interface overview and instructions for using the design and software capabilities This chapter contains the following sections e About PlanAhead e Guide Contents e Additional Resources e Conventions Note For information on software installation and system requirements refer to the Xilinx ISE Design Suite Installation Licensing and Release Notes About PlanAhead PlanAhead is a design and analysis software product used to design FPGA devices
356. onment Configure and launch one or multiple runs Define and apply commonly used strategies to runs Monitor and manage results Import and analyze results Multiple CPU capabilities on Linux Linux remote host e Design analysis Interactive schematic viewer Graphical hierarchy viewer Netlist tree viewing and expansion Resource utilization statistics before Place and Route Advanced searching for device or design objects Design metrics display Object properties to display relevant information Design rule checking Connectivity display Placement analysis and highlighting e Static timing estimation TimeAhead e Timing constraints editor e Robust floorplanning environment Hierarchical floorplanning Flexible capabilities to assign and fix LOC constraints e Block based capabilities Block level implementation IP creation and reuse Integration with the Project Navigator Environment The PlanAhead software provides an environment to help improve your design results throughout the design flow Integrated within the Project Navigator environment PlanAhead is automatically launched at four different design process steps These include I O pin planning Pre Synthesis I O pin planning Post Synthesis Floorplan Area IO Logic Post Synthesis and Analyze Timing Floorplan Design Post Implementation Each of these steps offers unique and powerful capabilities previously only available in the standalone PlanAh
357. ontinued The cursor will continue to display as a cross to draw another area to place the remaining I O Ports and so on until all of the I O Ports are placed or until you press the Esc key Ports are assigned in the order that they appear in the I O Ports view The assignment order can be adjusted by applying sorting techniques in the I O Ports view prior to assignment The direction that the rectangle is drawn dictates the I O ports assignment order The I O Ports is assigned in order from the inside pin of the first rectangle coordinate selected Creative definition of the area rectangles can provide very useful pinout configurations from a PCB routing perspective Sequentially Placing I O Ports PlanAhead User Guide UG632 v 11 4 To place I O ports sequentially 1 Inthe I O Ports view select an individual I O port a group of I O ports or Interfaces 2 Use one of the following commands Select Place I O Ports Sequentially from the popup menu in the I O Ports view Click the Place I O Ports Sequentially button in either the Package or Device view www xilinx com 145 146 Chapter 5 VO Pin Planning g XILINX a Figure 5 25 Place I O Ports Sequentially Button The first I O port in the group is attached to the cursor when it is moved over a package pin or I O pad A tool tip displays the I O port and package pin names 3 Clicking on a pin or pad to assign an I O port Place QDR1_DIN 1 at AK8 1 of 1 Pres
358. ontrol which type of logic is to be constrained within the Pblock rectangle gt GN a pblock_cpuEngine_cpu_dbg_dat_i Name pblock_cpuEngine_cpu_dbg_dat_i Parent ROOT v Grid Range SLICE XBY7O 47 109 DSP48 XOVZ8 x4 43 RAMB36 XOV14 x3 21 General Statistics Instances Rectangles Attributes Selection Figure 10 23 Setting AREA_GROUP Range Types If the Pblock is resized or moved to a location that includes new device logic types such as BRAM DSP etc a dialog box is displayed prompting to add the new range types to the Pblock definition Toggling the ranges off will result in the Pblock being shown differently in the Device view As the Pblock is selected the shading will only affect the logic types for the ranges set on the Pblock as shown below PlanAhead User Guide www xilinx com 305 UG632 v 11 4 Chapter 10 Floorplanning the Design XILINX Pblock Properties El x aff a pblock_RCCInst oj 4 x te Name pblock_RCCInst Parent ROOT v Grid Range BERL AIA ww SLICE TBUF C MULT18x18 gi pilo CCinst C RAMB16 General Statistics Inste 4 gt E Figure 10 24 Pblock Shading Reflects Logic Contained in Pblock Setting Attributes for Pblocks Attribute properties can be assigned to Pblocks in the Pblock Properties Attributes tab Assigning attributes set various options for ISE Note S
359. or the upper levels of hierarchy in the figure above This makes the Schematic view more readable in most cases Module pins and logic can be individually expanded or collapsed Logic can be selectively expanded either from individual pins instances or the entire logic content inside or outside the module To expand module pins for a selected module use the Toggle Autohide Pins popup menu command or the Toggle Autohide Pins for selected instance toolbar button in the Schematic view amp Figure 8 10 Toggle Autohide Pins for Selected Instances Toolbar Button Expanding Logic from Selected Pins PlanAhead User Guide UG632 v 11 4 Several options exist to expand logic from a pin Double clicking on a pin will cause the logic net to expand all the way until the next primitive logic elements Thick wires indicate busses Busses will expand to include all bits of the bus Expansion of signals will go beyond hierarchical boundaries as shown below Other expansion options exist to expand logic all the way to the next set of Flip Flops or all the way to the I Os If too much logic is selected for expansion a dialog box may appear indicating that the logic selected is quite large and may not be suitable for schematic viewing www xilinx com 229 Chapter 8 Analyzing the Design g XILINX To view the logic expansion options select a pin or an instance and select the Expand Cone popup menu command to view the options vga_color_bars_in
360. ormats The input formats include RTL source files synthesized netlists I O ports lists and implementation results The view layout being displayed is determined by the type of Project being created For more information on the PlanAhead project types see Chapter 2 Creating and Managing Projects You can select the tabs just below the toolbar buttons to see the Project or Floorplan environment Project project_i1 x Floorplan orig_fp xc2v1000f9456 4 Figure 4 1 Project Environment is Selected www xilinx com 95 Chapter 4 Using the Viewing Environment g XILINX The PinAhead environment can be invoked by selecting the Tools gt Open PinAhead command PinAhead Environment View Layout I O Pin planning capabilities are included in PlanAhead to enable I O and pin assignment and clock planning The PinAhead environment which is invoked from any active Floorplan displays information specifically for I O pin planning purposes For more information on the I O pin planning view see Chapter 5 I O Pin Planning Select Tools gt Open PinAhead to display the PinAhead environment layout GB projecte ew C WataVlanabear De 0 ct_new proje t _new ppr PlanAhead 11 1 1 RO Fie Edt Toos Window tes pip aax ooryxaonp E ri Focine tii dima sh n Lot Help D Properties J Netlist Souc Cock Regors E id Nee Row Cn 10 2am 3am wm sxs 605 7 xo D Vorteol_pad_0_0
361. orplan dialog box will appear 2 Click Next to continue Defining the Floorplan Name and Selecting a Target Device The Floorplan Name dialog box of the New Floorplan wizard is now invoked PlanAhead User Guide www xilinx com 65 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX New Floorplan Choose a Part and a Floorplan Name Enter a name for your floorplan and choose a Xilinx device Choose Part xc5vix30ff324 1 Floorplan name floorplan_2 es Figure 2 35 New Floorplan Wizard Floorplan Name and Device 3 Set the following editable options in the Floorplan Name dialog box Floorplan name Enter the desired name for the floorplan e Device to use From Netlist Select to use the entry defined in the top level EDIF netlist file Select Part Use the files browser to invoke the Select Part chooser which enables you to select a desired device 4 Click Next to continue Importing Constraints The Import Constraints dialog box of the New Project wizard is now invoked 66 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Working with Floorplans New Floorplan Import Constraints Import physical and timing constraints from a UCF file You can also import a UCF file later with the Import Constraints command Constraints files landhead_Projects Plan4head_Tutorial labs design_files 802RC V_cos 13 ucf Figure 2 36 New Floorplan Wizard
362. our specified options is also created in each PlanAhead Run directory Each Run directory contains all implementation design data including the netlist and the constraints files When a satisfactory implementation result is achieved the entire Run directory can be easily copied and archived because it is self contained EDIF Netlists edf PlanAhead User Guide UG632 v 11 4 Currently PlanAhead exports EDIF format ASCII netlist files These files are created during the following commands e Run Implementation and Launch Runs PlanAhead e File gt Export Netlist e File gt Export Pblocks e File gt Export IP Run Implementation and Launch Runs The purpose of launching PlanAhead Runs is to automatically export the files required to implement the PlanAhead Runs and to launch the ISE commands with the options specified in the Strategy applied to the Run EDIF and UCF data is exported automatically when the Launch Runs command is used When a Run is launched a run directory is created containing a single EDIF format netlist file and UCF format constraint file for the entire top level design The file names correspond to the original top level netlist name contained in the originally imported EDIF file If NGC NGO format module netlist files are used they are copied to each Run directory The PlanAhead General Run Properties indicate where the actual Run directory resides on disk Exported Netlists The purpose of exportin
363. out Enables you to delete any of the previously saved user defined layouts Undo Reverses the last view manipulation command Redo Reserves the last Undo command action 346 www xilinx com XILINX PlanAhead User Guide UG632 v 11 4 XILINX Toolbar Commands Help Menu The Help menu has the following menu items Table A 8 Help menu commands Name Description PlanAhead User Guide Invokes the PlanAhead User Guide in a separate window PlanAhead Invokes the PlanAhead Methodology Guide in a separate window Methodology Guide Tutorial Enables you to invoke the available PlanAhead tutorials in a separate window Release Notes Invokes the current Release Notes in a separate window Check for Updates Checks the Xilinx website for software updates and if found prompts you to install the updates License Invokes the Xilinx License Configuration Manager XLCM to locate or manage the software licenses FLEXnet Publisher is now used for software licensing XLCM can identify a license or help with the license flow PlanAhead on the Web Opens the Xilinx PlanAhead website in your default browser Getting Started Invokes the Getting Started jump page About PlanAhead Displays information about PlanAhead version and copyright information Toolbar Commands PlanAhead has a fixed toolbar that contains the most commonly used commands The toolbar
364. perform floorplanning from Project Navigator after implementation in the Process pane expand Implement Design expand Place amp Route and double click Analyze Timing Floorplan Design PlanAhead Post Synthesis or select the Tools gt PlanAhead gt Post Implementation Analyze Timing Floorplan Design command When PlanAhead is invoked Project Navigator passes the synthesized NGC or EDIF format netlist the UCF file s the ISE placement data and timing results to PlanAhead PlanAhead is invoked with the default PlanAhead design analysis and floorplanning environment displaying In order for PlanAhead to extract the ISE placement data a command called xd1 must first be run It produces a file with a xdl extension and may take a few moments to run A progress bar is displayed in PlanAhead while this command is running In order to expedite re invoking PlanAhead the interface will first check for the existence of the XDL file and will not regenerate it if it is still current When you select Tools gt PlanAhead gt Post Implementation Analyze Timing Floorplan Design with www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead Viewing Environments the implementation process out of date you are prompted to either reimplement the design and launch PlanAhead or launch PlanAhead on the existing result data without rerunning the implementation tools When the PlanAhead project is saved or exited the original Proj
365. placement or by locking individual logic objects to specific device sites Floorplanning Methodology Tips PlanAhead User Guide UG632 v 11 4 Below are some helpful floorplanning methodology tips 1 Use the methods described in the Chapter 8 Analyzing the Design to gain an understanding of the design data flow and the resource requirements of the various modules Modules with block memory and block arithmetic sites must be taken into consideration since their placement sites can be somewhat restrictive 2 Where possible use your knowledge of the design to create Pblocks for critical modules The analysis from TimeAhead the Schematic view and or place and route results can provide guidance 3 When floorplanning for performance it is good practice to only constrain the hierarchies that contain the critical path In some cases the hierarchy that is connected to fixed silicon resources I Os or PPCs should be floorplanned as well Floorplanning all the logic in a design as one might do in an ASIC flow will generally hurt performance Since FPGA tools work differently from ASIC tools just as FPGA architecture is different from ASIC architecture It is rare that floorplanning an entire FPGA design will help performance www xilinx com 287 Chapter 10 Floorplanning the Design g XILINX 4 Use the Pblock Properties statistics to make the Pblock as small as practical to limit interconnect length Use these same statist
366. planning or ChipScope tool core insertion and debugging Through analysis and floorplanning physical constraints are applied to help control the implementation of the design The PlanAhead environment enables exploration and experimentation with various implementation strategies All of the implementation attempts and data are completely managed from within the PlanAhead environment PlanAhead is also used after implementation to analyze the ISE software placement and timing results in order to improve the performance of the design Additional physical constraints derived from the imported results may also be used to lock placement during subsequent implementation attempts The flow chart shown below illustrates the common design flows as well as the various input and output formats of PlanAhead PlanAhead User Guide www xilinx com 19 UG632 v 11 4 Chapter 1 Understanding the PlanAhead Design Flow g XILINX PlanAhead Design Flows Basic Flow RTL SU Loe Development Cores amp Analysis oa d UCF ll ISE Results Analyze Results CSV I O Pin Planning Synth Netlist i i Analyze ISE Design amp Results Floorplan So Figure 1 1 PlanAhead Design Flows with Inputs and Outputs The addition of a logic synthesis environment and front to back process is one of the biggest a
367. played inside the Pblock are sized based on the amount of logic they contain relative to the other instances in the same Pblock If many instances are assigned to a Pblock they may appear as lines instead of rectangles 296 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Working with Pblocks IR lt E Package Device x T Figure 10 14 Pblocks With Assigned Instances Displayed Graphically With the default selection rules set selecting the Pblock rectangle will also select all of the netlist instances contained in it Instances can easily be dragged and assigned into other Pblocks Note Be careful when manipulating Pblocks to ensure the Pblock rectangle is selected and not the smaller rectangles indicating the instances assigned to it It is often helpful when manipulating Pblocks to turn off the selection ability for instances This ensures Pblocks and not the instances assigned to them are selected in the Device view To define how instances and Pblocks are selected select Tools gt Options gt Themes gt Device and define the selection ability in the Device dialog box For more information see Setting Device View Display Options I O Nets are drawn connected to the center of the instance inside the Pblock rather than in the Pblock center as with Bundle Nets E Package Device x E Figure 10 15 WO Connectivity Displays to Center of Instance Rectangles PlanAhead User Guide www xili
368. plays the Sources view Floorplans Displays the Project Floorplans view Physical Hierarchy Displays the Physical Hierarchy view 344 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Main Menu Commands Table A 5 Window menu commands Package Pins Displays Package Pins view I O Ports Displays I O Ports view ChipScope Displays the integration ChipScope view Constraints Displays the Constraints view Clock Regions Displays the Clock Regions view Metrics Displays the Metric view Selection Displays the Selection view World Displays the World view Console Displays the Console view Timing Results Displays the timing results in the Timing Results view DRC Results Displays the DRC results in the DRC Violations browser WASSO Results Displays the WASSO Results view SSN Results Displays the SSN Results view Find Results Displays the found objects in the Find Results view Find in Files Results Elaboration Log Displays the found objects in the Find in Files view Displays the results log of the Elaborate Design command Design Runs Metric Results Displays the runs in the Design Runs view Displays the Metrics Results view New Device View Opens a new Device view in the Workspace New Package View Opens a new Package view in the Workspace View Log File Opens the planAhead 1og
369. ported in the input UCF files 9 Click Next 10 Verify the contents of the Summary page and click Finish The specified primitive instance assignments are removed from the design I O Port placement To clear I O Port constraint assignments 1 Select Tools gt Clear Placement Constraints The Clear Placement Constraints wizard is invoked Clear Placement Constraints Clear Placement Constraints This wizard will guide you through the process of deleting placement constraints from the current floorplan You can clear instance placement I O port placement or both What type of placement do you want to clear Instance placement Vo port placement Both PlanAhead To continue click Next Figure 10 47 Clear Placement Constraints Wizard Clear I O Ports or Both 2 Inthe Clear Placement Constraints wizard specify the type of placement to clear Instances placement I O Port placement or Both 3 Click Next The next dialog box will differ depending on what types of objects were selected prior to invoking the command If nothing was selected it is not shown If I O Ports are selected it defaults to remove them Additional options are presented depending on the preselected set as shown below 322 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Working with Placement LOC Constraints Clear Placement Constraints Unplace Ports Specify the I O ports to be unplaced Ports to Unp
370. porting a Pblock creates an EDIF netlist and UCF physical constraints file for each Pblock selected for export To export Pblocks to EDIF and UCF 1 Select one or more Pblocks 2 Select File gt Export Pblocks This Export Pblocks wizard is displayed qd Export Pblocks Select file types to generate and Pblocks to export Floorplan orig_fp Directory name C HDI project_1 File types to generate Netlist EDIF Constraints UCF Export only fixed placement Export all placement Pblocks 2 Id Name Primitives Pins fy 1 pblock_1 a 2 pblock_LED Figure 7 40 Export Pblocks Wizard PlanAhead User Guide www xilinx com 215 UG632 v 11 4 Chapter 7 Implementing a Design g XILINX 3 View and edit the definable options in the Export Pblocks dialog box 7 Directory name Enter the directory name or use the file browser to select a directory to export the files A subdirectory called lt pblockname gt _CV is created for each exported Pblocks In order to help keep track of the various EDIF and UCF files associated with a typical PlanAhead design scenario it is good practice to specify a unique directory name for each ISE attempt The export directory will be used to seed the Import Placement and Import TRCE Results command file browsers File types to generate Netlist EDIF Select this option to export the net
371. ports Java and C memory consumption and displays a higher value PlanAhead User Guide www xilinx com 107 UG632 v 11 4 Chapter 4 Using the Viewing Environment g XILINX Understanding Object Selection Options PlanAhead enables you to select highlight and mark objects Selecting Objects Selecting an Object Objects can be selected in many ways in PlanAhead Click the object to select it in the current view When selected in any view objects also become selected in the other appropriate views To move objects hold the left mouse down and drag it release to drop it on the desired location The cursor will change to a hand symbol when the move mode is activated When objects overlap a priority scheme is used where the smaller size objects are selected If objects become difficult to select in the Device view use the Physical Hierarchy or Netlist views to select them Objects can always be selected from either of these two views regardless of the Selection Rule setting in the PlanAhead Options dialog box If you experience difficulty selecting the correct object the Select commands in the popup menu can be used to select a specific item within the stack of items under the cursor Selecting Multiple Objects In most selectable views and dialog box lists multiple objects may be selected by pressing and holding the Shift key to select a range of elements in a tree or table The Ctrl key is used to select multiple elements individua
372. qA Nme 5 A ports E G VControl_pad_0_o 4 Corro pad i oii T Optode_pad_0 0 2 OpMode pad 1 o DG Otat paddo HD Otat pdo 5G neou D Corsole O 1 0 Ports Netlist A Constants Dr Neg Off Par locaton Bark YO Rd 17 WONOSES 15 wwoMOSsZ5 17 evoMos2s 15 wemos2s 17 OSs 3S LOMOSSS woss nA d 11 LLRO SEER E ALEAN 5 fe I 8 Se BS M5 gt w Sron GP evke x Orive Strength Stow Type Ad Type Phase 12 20W 12 20w 12 20w 12 20w 12 20w 12 20w detak deiak deiak delak detak detak detak Figure 3 2 PlanAhead Floorplan Environment The areas of the viewing environment are the following 1 Physical Hierarchy View Metrics View Sources View 2 Object Properties View Selection View 3 Console View I O Ports View Package Pins View Results Views Timing Find Design Rule Check Met rics 4 Netlist View Constraints View PlanAhead User Guide UG632 v 11 4 www xilinx com 85 Chapter 3 Using PlanAhead With Project Navigator g XILINX 5 Workspace Device View Package View Schematic View Instance Hierarchy View Reports 6 World View For more information about using the PlanAhead Viewing Environment see Chapter 4 Using the Viewing Environment Transitioning from PACE Floorplan Editor to PlanAhead 86 For the ISE Design Suite 11 1 all FPGA pin planning and floorplanning functionality is provided by PlanAhead A fully licensed and full
373. r all pins in the device Values are a number or blank This is not required in the input CSV file e Pin Number The name or location of the package pin The software writes this out for all pins in the device This is not required in the input file If used for input it is used to define placement Values are legal pins in the device e JOB Alias The alternate part name for the package pin This field is specified by the software and is unused if specified in the input CSV file e Site Type The name for the pin from the device data sheet This field is specified by the software and is unused if specified in the input CSV file e Min Max Trace Delay The distance between the pad site of the die and the ball on the package in picoseconds This is specified by the tool to help the board engineer match trace delays The Trace Delay fields are in the output file only They are not expected in the input file e Prohibit Certain sites may be prohibited for many reasons to prevent user I O from being added to the site www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Importing I O Ports Prohibits ease board layout issues reduce cross talk between signals and ensure that a pinout will work between multiple FPGAs in the same package In the UCF this is represented by a CONFIG PROHIBIT constraint Values are TRUE or the field is left blank This field should be left blank when the Pin Number is left blank e In
374. r CLB Pblock Metrics 6 LUT Utilization per Pblock a FF Utilization per Pblock gt Estimated Slice Utilization per Pblock Min Slack per Pblock a Total Negative Slack per Pblock i Pblock boundary crossing net count Physical Hierarchy amp Sources Figure 9 12 Metrics View The Metric Properties view provides a description of the Metric function along with the bins defined to highlight potential problems as shown in the example below Metric Properties Og x oi x ai i a LUT Utilization per Pblock Summary A of LUT resources utilized in a pblock Details Accounts for instances assigned to the pblock in addition to any LOC constraints Does NOT account for reduced resources due to overlapping pblocks Helps to determine appropriate pblock size during floorplanning Bins Id From To Show Color 1 o 70 255 255 255 2 700 85 M C0255 255 153 3 85 100 E255 153 0 a amp Properties Selection Figure 9 13 Properties View Set Metric Range Values Displaying the Metric Maps in the Device View To display a Metric map in the Device view select the metric and select the Show popup menu command A color based metric map is displayed PlanAhead User Guide www xilinx com 283 UG632 v 11 4 Chapter 9 Analyzing Implementation Results g XILINX Metrics OX WUT Utilization per CLB Primitive Metrics
375. r Chipscope debugging Show dialog before resetting Runs for Out of date Configurations Strategies Show dialog before deleting Runs that are related to invalid configurations Show warning dialog before exiting Plandhead mm Ask before overwriting synthesis or implementation results 5i Text Editor 1O Placement Automatically enforce legal I O placement Connectivity Display Draw nets as Mesh O Tree Show connections while dragging instances C Show connections for selected instances Miscellaneous Automatically check xilinx com for software updates on startup i Number of recent projects to list 110 e Figure 4 28 General Options The General options are as follows e Look and Feel You can adjust general style and color options Note Most Windows platform PlanAhead testing and development is done using the default Office 2003 settings If problems arise with the display reset the Look and Feel Style back to Office 2003 e Warning Dialogs The manner is which warning dialog boxes are presented can be controlled using the self explanatory options e I O Placement The interactive I O placement DRCs can be toggled on or off using this option 120 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Configuring the Viewing Environment e Connectivity Display The manner in which the connectivity is displayed in the Device view can be control
376. r an already existing Pblock 1 Select the Pblock in the Physical Hierarchy view or Device view 2 Click the Set Pblock Size toolbar button ee Figure 10 18 Set Pblock Size Toolbar Button The cursor changes to enable you to draw a new rectangle in the desired location in the Device view 3 Use the cursor to draw a new rectangle This command is also used to draw a rectangle for an existing Pblock with no rectangle yet defined such as one created with the New Pblock s commands For more information see Creating Multiple Pblocks with the Create Pblocks Command If a Pblock has multiple rectangles this command is used to regenerate the Pblock with a single rectangle This is often useful when a Pblock gets fragmented into multiple rectangles If the Pblock is resized to a location which includes new device logic types such as BRAM DSP etc a dialog box is displayed prompting to add the new range types to the Pblock definition Pblocks behave differently when location placement constraints are assigned inside of them If location constraints are assigned to the Pblock a dialog box is displayed prompting you to either remove or leave the location constraints intact Fixed and unfixed location constraints are listed separately in the dialog box allowing you to handle them differently To cancel an active resize operation click the Esc key on the keyboard The active command will be terminated www xilinx com PlanAhead
377. r logic interface To create an Interface 1 Select the desired signals in the I O Ports view 2 Select Create I O Port Interface from the popup menu Neg Diff Pair cation Ran NO Std Driva Stranath ow Tvoga Pull Type CZ Create I O Port Interface 4 Create a new I O Port interface for project project_cpu_r Name finterface_1 Assign 5 selected I O port buses to the new interface LineState_pad_ Dataln_pad_O_ Assign 18 selected I O ports to the new interface C e Figure 5 19 Create I O Ports Interface PlanAhead User Guide www xilinx com 141 UG632 v 11 4 Chapter 5 VO Pin Planning g XILINX 3 Enter a name for the Interface and adjust assignment selection 4 Click OK The Interfaces appear as expandable folders in the I O Ports view Additional I O ports can be added to the Interface by selecting them in the I O Ports view and dragging them into the Interface folder Name i Neg Diff Pair Location Bank I OStd Drive Strength Slew Type Pull Type S All ports 138 Gli USB_O 30 H 8 LineState_pad_O_i 2 17 LYCMOS25 12 SLOW H 8 Dataln_pad_O_i 8 LYCMOS25 12 SLOW DataOut_pad_O_o 8 17 LYCMOS25 12 SLOW HO Scalar ports 12 USB_1 44 Scalar ports H B RXP_IN 8 LvDS_25 Scalar ports 0 Figure 5 20 Manage I O Port Interfaces To include additional I O ports in an Interface 1 Select a port or bus 2 Select Assign to Interface from the popup menu
378. r partners Site Types and Min Max package delay are listed for each package pin Table values appear gray when they are the default values black when they are non default values and red when they are illegal values Note The unit of measurement for the Min Max package trace delay in the Package Pins view is in picoseconds ps The information in the Package Pins view can be sorted by clicking any of the column headers Clicking again will reverse the sort order You can sort by a second column by pressing the Ctrl key and clicking another column to perform a secondary sort Add as many sort criteria as necessary to refine the list order www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the PinAhead Environment Using the Package View PlanAhead User Guide UG632 v 11 4 The Package view displays the physical characteristics of the device being used in the design Various types of pins are displayed using different colors and shapes Rt r _ Cert Hy a pN 8 E a TECE CCEE CECEN CE COCOG IITE OF eet Ces eel ra eo mee te ee Tee oul dl hel fe Lael ees ene ete 123 45 6 7 6 9 10 11 12 13 14 15 16 17 18 Figure 5 6 Package View You can open the Package view by selecting the Package view tab in the Workspace or by selecting Window gt New Package View command Multiple Package views can be opened simultaneously Mov
379. r views including the Netlist and Physical Hierarchy views When marking timing paths the start point is marked in green the end point in red and all intermediate points in yellow as shown below PlanAhead User Guide www xilinx com 281 UG632 v 11 4 Chapter 9 Analyzing Implementation Results gt R amp E F z a a F E R H a E a E E a B a H E m A m E gu a E BLA E eae E a A 4 FF Has fE F 4 m 3 AA SH B BEHA ai HEFE E HE HE EFFET a HEA a EFEFEF 8 EEEL RED ZEEE 8 pip 4E REZ i FEJ F Bi SHES FETE B FUE EE H mire pres a lt fi Package Device x Figure 9 10 Marked Symbols in Device View Removing Marks Marks can be removed using one of the following methods e Choose Select gt Unmark All e Click the Unmark All toolbar button Figure 9 11 Unmark All Toolbar Button Displaying Design Metrics 282 Using the Metrics View amp XILINX The PlanAhead Metrics view displays a list of design metrics that can be displayed using a colored graph of the potential problem areas in the design The current metrics include utilization and timing checks at both the Pblock and placed design level www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Displaying Design Metrics Primitive Metrics 1 fii Min Slack per placed BEL CLB Metrics 2 gt t LUT Utilization per CLB i FF Utilization pe
380. rce File Properties A new target Library is set when you select a new one from the chooser menu and click Apply When an RTL source diplays in red then PlanAhead could not find the required files Adding Sources to the Project Adding Source Files or Directories RTL sources can be added to the project at any time 1 Select the Add Sources command to invoke the Add Sources dialog box In this dialog box the buttons are defined as follows Add Files Invokes file browser to select RTL files to add to the project VHDL libraries can be specified or selected at the time of import Add Directories Invokes directory browser to add all RTL source files from the selected directories and their sub directories to the Project All files in the directory hierarchy with recognized source file extensions are added to the project Remove Removes the selected source files from this dialog box Import Source to the Project Copies the original source files into the PlanAhead project and references them locally 168 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Adding Sources to the Project G Add Sources Project Sources Id Name Library Location i FifoBuffer work C Data Plandhead_Designs src wh 2 ea geen DatalPlandhead_Designs src Add Files Add Directories C Import Sources into Project Figure 6 4 Adding Source Files and Directories to the Project When adding so
381. rce and binary forms with or without modification are permitted provided that the following conditions are met Redistributions of source code must retain the above copyright notice this list of conditions and the following disclaimer Redistributions in binary form must reproduce the above copyright notice this list of conditions and the following disclaimer in the documentation and or other materials provided with the distribution Neither the name of JGoodies Karsten Lentzsch nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT INDIRECT INCIDENTAL SPECIAL EXEMPLARY OR CONSEQUENTIAL DAMAGES INCLUDING BUT NOT LIMITED TO PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE DATA OR PROFITS OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY WHETHER IN CONTRACT STRICT LIABILITY OR TORT INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Libconfig v1 3 2 License lipconfig A library for processing structured c
382. rchical instance will collapse all currently displayed logic and expand the logic within the selected module To go up a level of hierarchy use the Expand Outside command in conjunction with the Collapse Inside command Regenerating a Schematic View Occasionally after several expand and collapse commands the Schematic view may look a bit jumbled You can force a Schematic view regeneration to clean up the display by selecting the Regenerate schematic toolbar command in the Schematic View PlanAhead User Guide www xilinx com 231 UG632 v 11 4 232 Chapter 8 Analyzing the Design g XILINX Figure 8 13 Regenerate Schematic Toolbar Button This command will redraw the active Schematic view Selecting Objects in the Schematic View Objects are selected by left clicking on them The Ctrl key can be used to select multiple objects Multiple instances ports and nets can be also selected by using the Select Area command and drawing a rectangle around them As instances are selected in the Schematic view they are also selected in all other views This cross selection works both ways If objects are selected or highlighted in either of these two views they are also highlighted in the Schematic view The Schematic view popup menu also has some selection options which are covered later in this section of the document Removing Objects From the Schematic View You can remove selected objects and their associated connectivity using th
383. re while preserving the active Floorplan constraints To copy a Floorplan 1 Select the Floorplan tab to make the desired Floorplan active 2 Select File gt Copy Floorplan The Copy Floorplan dialog box displays G Copy Floorplan Source original_Fp Name Copy_of_original fp Part xc4vix25FF668 10 e C Copy Pblock Rectangles C Copy Instance and Port Placement i Cancel Figure 2 50 Copy Floorplan Dialog Box 3 Inthe Copy Floorplan dialog box set the following editable fields Name Enter the new Floorplan name A default name is filled in Part Optionally select a new target device Copy Pblocks Rectangles Select to copy the Pblock rectangles into the new device using the same tile coordinates if possible Copy Instance and Port Placement Select to copy the placement constraints into the new device using the same coordinates if possible 4 Click OK to complete the copy Renaming a Floorplan Floorplans can be renamed in the design project To do so 1 Select a floorplan in the Physical Hierarchy view or in the Floorplans view The Floorplan Properties dialog box displays in the Properties view 2 Ifthe Floorplan Properties are not displayed right click on the floorplan and select Floorplan Properties from the popup menu PlanAhead User Guide www xilinx com 77 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX Delete Copy
384. reducing internal and external trace lengths as well as routing congestion Using the PinAhead Environment PlanAhead User Guide UG632 v 11 4 Many of the views available in the PinAhead environment are also used in the Floorplan environment For more information about the Floorplan environment see Floorplan Environment View Layout The PinAhead environment consists of a split Workspace showing both the Package and Device views There are other views that provide additional I O information the Clock Region view Package Pins view and the I O Ports view There are two ways to launch the PinAhead view layout e Select Tools gt Open PinAhead e Create anew empty Project using the New Project wizard as shown in Figure 5 1 page 128 www xilinx com 127 Chapter 5 VO Pin Planning g XILINX project_3 C Data PlanAhead_Projects project_3 project_3 ppr PlanAhead 11 1 LRO File Edit View Tools Window Select Layout Help Seereae max QO gt Project project_3 E FI gt KHOaR SaaneP Be z7eizer IJO Port Properties og 4 x pe al E a gt Blr gt gt SES a cee was EA Direction Output w z v p Site 3 o MLS D 2X ale CAIM E ee te tere F amp c DOR c Ia ELEL H amp o Me J as Ie CY K EJ I EOTS L General Configure 2 M ee ie M lock Regions a a N Ra N z a i Name Row Column F Be aes JP 1 xovo o 0 ad ET s sm R m 2xovi 1
385. rength differential pairing banks etc to individual pins or groups of pins busses e lt A Weighted Average Simultaneous Switching Output WASSO analysis is available in PlanAhead using Tools gt Run WASSO Analysis As an enhancement beyond PACE and Floorplan Editor the PlanAhead analysis is based on the more complete WASSO rules e A Simultaneous Switching Noise SSN analysis is available in PlanAhead using Tools gt Run SSN Analysis e Design rule checking DRC To run DRC select Tools gt Run DRC e For designs with a complete netlist PlanAhead provides a complete set of IO Banking rule checks e Clocking rules are also checked to verify that clock buffer placement is legal and optimal They are not available in Empty Design or Pre Synthesis modes e Prohibit configuration pins by mode PACE and Floorplan Editor had a specific feature that enabled you to prohibit the device configuration pins for example a JTAG port from being used by general user IO pins In PlanAhead this is a manual process Select the pins you wish to prohibit in either the Device or Package view and mark them as prohibited using the Set Prohibit right click menu command e Package migration support PlanAhead provides a facility to automatically prohibit those pins on footprint compatible packages within the same device family In the Package view use the Make Part Compatible right click menu command e Package pin flight time display not appli
386. reviously opened Projects are displayed for re opening PlanAhead checks to ensure the Project data is still available before displaying You can configure how many Projects to list in the General dialog box available by selecting Tools gt Options gt General The PlanAhead documentation is available by selecting the appropriate links to launch a PDF viewer The documentation is also available in PDF format in the lt Install1Dir gt doc directory Understanding the Different Types of PlanAhead Projects 38 PlanAhead can be used at different points in the FGPA design flow for various reasons To accommodate this different types of PlanAhead Projects can be created They are differentiated by types of input sources used to create the Project You can select the type of Project desired during the Create New Project process Once a particular Project type is selected it cannot be migrated to a different type later Note PlanAhead also uses a derivative type of Project to support Partial Reconfiguration designs This capability is only available to a limited set of customers in the 11 release and is covered in the Partial Reconfiguration User Guide Empty Projects for I O Pin Planning I O pin planning can be accomplished early in the design cycle by creating an empty Project I O ports can be created within PlanAhead or imported with either CSV UCF or RTL input files After I O pin assignment PlanAhead can create CSV UCF and RTL o
387. ributes defined in PlanAhead will be reflected in the constraints Several commands are available to create Pblocks as described in the following sections Using the Draw Pblock Command The Draw Pblock commands will assign pre selected logic to a new Pblock in the Device view You can select the desired logic to assign to the Pblock prior to invoking the command To create a Pblock 1 Select the logic in any view such as the Netlist view to assign to the Pblock 2 Select Draw Pblock from the popup menu or click the Draw Pblock toolbar button or Figure 10 1 Draw Pblock Toolbar Button 3 Move the cursor to the location within the Device view where a Pblock corner is desired 4 Press and hold the left mouse button move the mouse cursor to the opposite corner of the Pblock and release the mouse button The New Pblock dialog box will appear 288 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 Partitioning the Design by Creating Pblocks G New Pblock Grids SLICE 352 DSP48 16 RAMB36 8 Assign selected instance i Cancel Figure 10 2 New Pblock Dialog Box 5 View and edit the options in the New Pblock dialog box Name Enter a suitable name for the Pblock If no name is entered a default name of pblock_n or Pblock_ lt instancename gt will be used Grids Select the desired device resource ranges to be constra
388. rimitives and Highlight Primitives Commands Unhighlighting Objects To unhighlight objects use one of the following commands e Choose Select gt Unhighlight All to unhighlight all objects e Choose Select gt Unhighlight Color to unhighlight based on color e Click the Unhighlight All toolbar button x Figure 9 8 Unhighlight All Toolbar Button Highlighting Placed Modules Using the Select Primitives and Highlight Primitives Commands After XDL placement has been imported use the Highlight Primitives command to selectively highlight the underlying primitive logic elements for Pblocks and logic modules You can select logic modules or Pblocks and use the Highlight Primitives command and then select a color to highlight their associated placement When multiple instances are selected you can select the same color for all or use Cycle Colors to use different highlight colors for each of the selected modules Modules and primitives in the Netlist view are marked with the matching highlight color in the Device Schematic and Package views 280 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Marking Selected Objects Netlist ogg x z0 D FPGA_RCV_802_11 H 5 Nets 111 H Primitives 426 E m channel channelInterfaceRx E GB LED decode SeqDispCkK_49_123 S ij receiver RC _802_11 Nets 55 E E Primitives 2 lz busMuxWrapInst busMuxWrap S E RChainTopInst RChainTop H amp S N
389. roperties View Toolbar Toolbar Button Command Description Previous object Reverts to the previously selected objects Next object Reverts to the next selected objects This key gt is only enabled after a Previous object y J command Automatically update the Toggles the Properties view to auto update B contents of this window as new objects are selected or remain static for selected objects on the originally selected object www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Netlist View PlanAhead User Guide UG632 v 11 4 Table 8 2 Properties View Toolbar Using the Floorplanning Environment Toolbar Button Command Description New Adds a new object This option is only available for certain object types and in specific view panes Delete Deletes an object from within one of the x property tabs m Export statistics Saves data to file for later analysis Available from the Statistics tab for the Pblock Clock Region and Instance Properties View only Select Unselect object Sometimes the object whose properties you are viewing may become unselected Use this button to select unselect this object The netlist is a hierarchical representation of the logic design beginning with the top level netlist name followed by top level modules The Netlist view displays the logic instances and nets contained in the design The netlist can be navi
390. roxy server settings Advanced Click Check for Updates to find out if updates are available Check for Updates Cancel Help Figure B 1 XilinxUpdate Welcome page The Advanced button will allow specific proxy settings to be validated or set 1 Select the Check for Updates button to communicate with the Xilinx website and return a list of all product updates available 2 Inthe Available Updates dialog box select the desired tool updates 3 Click OK to download and install any updates Automatically Checking for Updates PlanAhead can be configured to automatically search for new incremental releases each time PlanAhead is invoked To do so set the Automatically check xilinx com for software updates on startup option in the Tools gt Options gt General dialog box as shown below 352 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Automatically Checking for Updates q PlanAhead Options i Themes W Style Office 2003 v Theme Default 3 hii pa Look and Feel Selection Rules Warning Dialogs Show warning dialog before closing a floorplan Shortcuts gt Show warning dialog before closing a project Show warning dialog before upgrading an old project Schematic 3 Show dialog before adding net for Chipscope debugging Show dialog before resetting Runs for Out of date Configurations Strategies Show dialog before deleting Runs that are rela
391. rresponding constraints can be imported to create a PlanAhead Project This is used to analyze the place and route results using the implementation environment Select the Import ISE Place amp Route results option in the Design Source dialog box 52 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Create New Project Wizard to Create a New Project New Project Design Source Specify the type of sources for your design You can start with RTL or a synthesized EDIF O Import RTL Sources You will be able to run RTL analysis synthesis and implementation Import synthesized EDIF or NGC netlist You will be able to run post synthesis design analysis planning and implementation Import ISE Place amp Route results You will be able to do post implementation analysis of your design Do not import sources at this time You will be able to do pin planning now and import a netlist later Figure 2 20 Creating a Project with ISE Place and Route Results Selecting a Top Level Netlist and Module Search Path PlanAhead User Guide UG632 v 11 4 If the Import ISE Place amp Route results option was selected the next page in the New Project wizard enables you to input a top level netlist file and a search path to find module level netlists 1 Inthe Import Netlist page edit the definable option Netlist file Enter a name to identify the top level netlist in this project Use the File Brows
392. rt timing results for Select the level of the design to import This command is seeded with pre selected objects so carefully select the proper level of the design Netlist lt netlist_name gt Select this option to import results for a top level Tree result Instance Select this option to import results for a instance Click the browse button to select a specific instance Pblock Select this option to import results for a Pblock Click the browse button to select a specific Pblock 3 Click OK to import the timing results The TRCE results are displayed within the TimeAhead environment 218 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Interfacing with ISE Outside of PlanAhead Name P Path P Path2 P Path3 P Path4 P Paths P Path P Path P Paths P Patho P Path 10 P Path 11 Type Constrained Paths 240 TS_usbClk PERIOD TIMEGRP usbCik 3 9 ns HIGH 50 30 Setup Setup Setup Setup Setup Setup Setup Setup Setup Setup Setup Slack From Total Delay Logic Delay Net Stages A 0 265 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 dout 7 0 223 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 dout 9 0 221 usbEngine1 usb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_ usbEngine1 u4 dout 9 0 098 usbEngine1 usb_dma_wb_in BU2 UO gen_fifo18_36 fgfifo18_ usbEngine1 u4 dout 23 0 086 usbEngineO usb_dma_wb_in BU2
393. rted to enable visualization and exploration of the timing path logic For more information see Chapter 8 Analyzing the Design PlanAhead User Guide UG632 v 11 4 www xilinx com 207 Chapter 7 Implementing a Design g XILINX Once a implementation run is complete you can import ISE placement and timing results as follows 1 Select an implementation run in the Design Runs view 2 Select one of the following commands Select Import Run from the popup menu Select the Import Run toolbar button in the Design Runs view ea Figure 7 32 Import Run Toolbar Button Note Double clicking on any completed run in the Design Runs view will invoke the import Run dialog on that run The Implementation Run placement and timing results are displayed The UCF constraints that were used to generate the run are imported as well If modifications are made to the constraints in PlanAhead you are prompted to save them as a floorplan Multiple runs results can be imported A tab is displayed with the run name at the top of the PlanAhead environment for each run imported Selecting the tab will display the associated run results data Importing Run Results for a Floorplan The run results associated with a floorplan are imported as described above The only difference is that only one run result per floorplan can be displayed at a time A tab is displayed with the floorplan name at the top of the PlanAhead environment Each time a
394. s Configure Hosts Select this option to configure remote hosts For more information see Executing Runs on Multiple Linux Hosts Generate scripts only Select this option to export and create the run directory and run script but not to launch the run from PlanAhead The script can be run at a later time outside of the PlanAhead environment Do not launch the run Select this option to Create the Run in the Design Runs view but not to export the data or launch the Run yet Click OK to create the Run with the selected launch options Creating Multiple Implementation Runs PlanAhead enables you to create and launch multiple implementation runs simultaneously Various implementation options can be explored to find the best results Select Tools gt Run Multiple Strategies to create multiple implementation Runs 2 Select Implementation from the first Run Multiple Strategies dialog box Run Multiple Strategies Set Up Implementation Runs Define the Part and Constraints For the implementation runs to be created Synthesized Netlist v synth_2 xc5vix30ff324 1 f Floorplan Part xc5vlx30ff324 1 Constraints E Figure 7 12 Set Up Multiple Implementation Runs The Set Up Implementation Runs dialog box has several options fields www xilinx com 193 Chapter 7 Implementing a Design g XILINX Synthesized Netlist Select the name of the synthesis run to implement Floorplan Select the name of
395. s e Understanding Object Selection Options e Configuring the Viewing Environment The Viewing Environment PlanAhead User Guide UG632 v 11 4 The PlanAhead software has a dynamic viewing environment that consists of various view layouts that present the pertinent design and device information for the design task at hand PlanAhead can be used as a standalone software tool or launched for specific purposes from the ISE software The full suite of PlanAhead features is available when launched as a standalone while only a subset of specific features are available when launched from Project Navigator Refer to Chapter 3 Using PlanAhead With Project Navigator for more information about integration with Project Navigator PlanAhead can be used to control each major step of the FPGA design process including RTL development and analysis logic synthesis physical design analysis floorplanning and implementation control with the ISE software PlanAhead enables you to define view layout configurations in order to customize the types of views displayed and their appearance The tool provides default view layouts for I O pin planning RTL development and analysis and design analysis and floorplanning These views are called the PinAhead environment the Project environment and the Floorplan environment respectively PlanAhead enables you to create several different types of Projects that vary depending on the input f
396. s ESC to quit Figure 5 26 Placing I O Ports Sequentially 4 If more I O ports are selected the command is continued The cursor will drag the next I O ports and so on until all of the I O ports are placed or until you press the Esc key Ports are assigned in the order that they appear in the I O Ports view The assignment order can be adjusted by applying sorting techniques in the I O Ports view prior to assignment Automatically Assigning I O Ports PinAhead has the capability to automatically assign all or any selected I O ports to package pins The autoplacer will obey all 1 O standard and differential pair rules and will place global clock pins appropriately To automatically assign I O ports to a subset of unassigned I O ports 1 Select the unassigned I O ports in the I O Ports view 2 Select Tools gt Autoplace I O Ports or in the I O Ports view select Autoplace I O Ports from the popup menu The Autoplace I O Ports wizard displays www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Placing I O Ports Autoplace I O Ports Autoplace I O ports This wizard will guide you through the process of automatically placing I O ports The automatic placer will honor I O bank constraints if any Which ports do you want to place All 703 IO ports 92 selected ports PlanAhead To continue click Next Figure 5 27 Autoplace I O Ports Wizard 3 Select the group of I O ports to plac
397. s described below Implementing a standalone Pblock enables ISE to maximize the performance targets for that logic This provides a great indicator of how the module may perform in a best case scenario If timing targets are not met for the standalone Pblock timing may be extremely difficult to meet in the context of the entire design 194 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX PlanAhead User Guide UG632 v 11 4 Running Implementation For logic in the design that is prone to performance related issues you can implement that piece of logic lock down the implemented logic and then implement the top level design With placement locked down the chances of maintaining performance increase dramatically There is a chance that interconnects may not follow the same routing channel tracks as expected during top level implementation in which case routing delays may vary For more information on logic locking techniques see Working with Placement LOC Constraints page 315 Design runs can be created and configured for individual Pblocks that leverage the same monitoring options that PlanAhead provides for floorplan implementation You can create implementation runs for one or more selected Pblocks Note Before implementing Pblocks with ISE the following Xilinx environment variable should be set to prevent logic trimming into the Pblock XIL_ MAP NOCLIP_ON_ALL SIGS_U witha value of 1 Creating Runs for
398. s instance WARNING 185 Expression size 11 truncated to fit in target size 10 WARNING 196 Expression size 5 truncated to fit in target size 4 it HP Figure 6 12 Viewing Elaboration Results Selecting any of the Warning or Error lines in the Elaboration view will load the appropriate RTL Source file into the RTL Editor and highlight the source code in question 174 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Elaborating and Analyzing the RTL Design Filtering the Results for Errors Only The RTL Elaboration results can be filtered to display only error messages Select the Hide Warning Messages button to filter the results for errors only Figure 6 13 Elaboration Results Hide Warning Messages Button Using the RTL Netlist View After successful elaboration the RTL Netlist view is invoked to display the RTL logic hierarchy 225 assign icbiu_adr_o ic_addr B 226 assign ic_inv spr_cs amp spr_write 227 assign ictag_we icfsm_tag_we ic_inv Rtop l 228 assign ictag_addr ic_inv spr_dat_i 0R1200 Nets 117 229 assign ictag_en ic_inv ic_en E Primitives 1 230 assign ictag_v ic_inv E cpuEngine or1200_top 231 Nets 179 232 E Primitives 2 233 s from ICRAM when IC is enable EJ cpu_dbg_dat_i FifoBuffer 234 E cpu_dbg_dat_o FifoBuffer 235 E cpu_dwb_dat_i FifoBuffer 236 assign icbiu dat_o 32
399. s invoked with the default PlanAhead design analysis and floorplanning environment displaying Note In Project Navigator set the Translate process property Macro Search Path sd to the appropriate directory if lower level NGC format core files are used in the design and are not added as sources When the PlanAhead project is saved or closed the original Project Navigator source UCF file s are updated This will also reset the Project Navigator design process state if appropriate Refer to Passing Logic and Constraints for more information about the integration mechanics and process Refer to Design Analysis and Floorplanning View Layout for more information about using the PlanAhead environment prior to implementation Refer to Chapter 9 Analyzing Implementation Results and Chapter 10 Floorplanning the Design for more information about using the PlanAhead environment after to implementation Analyze Timing Floorplan Design Post Implementation PlanAhead has a robust design analysis and floorplanning environment that can be used prior to or after implementation Analyzing the design after implementation allows you to view the placement and timing results in order to comprehend potential design issues Often physical LOC or AREA_GROUP floorplanning constraints can help drive the implementation tools toward better and more consistent results and reduce implementation runtimes To analyze the design or to
400. s is an easy way to select a cone of logic starting at a particular instance or I O Port Expanding Logic in the Schematic View Logic can be traced throughout the design hierarchy using the Schematic view Signals can be interactively expanded by double clicking on the pins of the instance to be traced PlanAhead User Guide www xilinx com 277 UG632 v 11 4 Chapter 9 Analyzing Implementation Results g XILINX 278 BRRR s FORE ce receive IM 9 i FORE s receivelM 10 r buffer_chanITFRx z aa aaar FORE cika clk jours Mi Package Device Schematic lt 1 gt E FORE receive lhl 1 alna ena enb wea dpram_24b_256w receiveRE 0 FORE receiveRE 1 FORE lt gt Figure 9 5 Logic Expanded in the Schematic View Instance and module connectivity and content can also be interactively expanded and displayed Anything selected in the Schematic view will also be highlighted in the Device view Traced logic is easier to see in the Device view after the implementation placement results have been imported For more information about exploring logic in the schematic see Using the Schematic View Tracing Logic Paths using the Properties Dialog Box Connectivity Tabs The Net Properties and Instance Properties commands launch a Net Instance Properties window that contains a Connectivity tab In this tab selective expansion of logic in the design are displayed To b
401. se on other outputs in the I O bank The SSN Predictor incorporates I O bank specific electrical characteristics into the prediction to better model package effects on SSN Since all power distribution networks within a packaged FPGA have different responses to noise it is relevant to understand not only the I O standards and number of I O ina design but also the response of the device power system to this switching In the Virtex 6 family of devices I Os are grouped into separate isolated I O Banks each with its own unique power distribution networks These each have unique responses to switching activity Xilinx characterizes all banks in the Virtex 6 family through three dimensional extraction and simulation This information is incorporated into the SSN predictor such that it can take the expected switching profile of a device and predict how the switching will affect the system s power network and in turn how other outputs in the I O bank are affected The SSN predictor is the best method available for accurately predicting how output switching will affect interface noise margins The calculation and results are based on a wide range of variables These estimates are intended to identify potential noise related issues in your design and should not be used as final design sign off criteria PlanAhead uses the SSN calculation if a Virtex 6 part is selected If using a device other than Virtex 6 refer to Running Weighted Average Sim
402. sign Once ChipScope debug cores are created and connected the standard PlanAhead implementation flow may be run to create a bitstream for the device The implementation flow may be started by selecting Tools gt Run Implementation Invoking the ChipScope Analyzer 340 If the ChipScope Pro Analyzer software is installed it may be launched directly from PlanAhead Before launching the ChipScope Pro Analyzer tool be sure a current bitstream has been created for the design by right clicking on an implementation run and selecting Run Bitgen from the popup menu To launch ChipScope Pro Analyzer do one of the following e Inthe ChipScope view tab right click and select Launch ChipScope Analyzer from the context menu e Inthe Design Runs view tab right click and select Launch ChipScope Analyzer from the context menu The BIT bitstream and CDC netlist name files are automatically passed to the ChipScope Pro Analyzer when launched from PlanAhead www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Appendix A Menu and Toolbar Commands This appendix provides a quick reference to the following PlanAhead software commands e Main Menu Commands e Toolbar Commands Main Menu Commands The following tables provides a quick reference for the PlanAhead software main menu commands View specific popup menu commands are covered elsewhere in this document Some of the commands are available only during
403. sing the Select Area Command 2 Select the Set Prohibit popup menu command The prohibited sites display a red X Figure 10 50 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using IP Reuse Capabilities Figure 10 50 Prohibited Sites in the Device View Using IP Reuse Capabilities IP Reuse Overview You can also export and reuse instance modules complete with placement locations and AREA_GROUP constraints PlanAhead provides the unique capability to export module level EDIF files and UCFs that contain placement constraints which can then be imported and reused in other designs This capability can also be used to facilitate team design or to duplicate placement for identical modules Creating and Reusing an IP Module Exporting an Instance for IP Reuse In order to facilitate the reuse of placement constraints they must first be imported into PlanAhead using XDL For more information see Importing ISE Placement and Timing Results Hierarchical netlist instances are the only items available for exporting as an IP module PlanAhead User Guide www xilinx com 325 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX To export the instance level netlist and placement constraints 1 Select the instance to be exported from the Netlist view 2 Select File gt Export IP The Export IP wizard will display G Export IP Floorplan Instance receiver RChainTopIn
404. single or set of I O Ports 1 Select one or more I O Port in any of the PinAhead views 2 Inthe I O Ports view Package Pins view or SSN view select the Configure I O Ports popup menu command as shown in Figure 5 39 page 161 160 www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Running Weighted Average Simultaneous Switching Output WASSO Analysis Gi Configure Ports I O Standard v Drive Strength 12 default Slew Type SLOW default v Pull Type NONE default w Phase default v Figure 5 39 Configure Ports dialog box In the Configure Ports dialog box make sure the I O Standard is correct If the port s are in phase leave the Phase as default or enter a unique phase such as phase 1 5 Click OK Once the appropriate phase groups are assigned rerun the SSN analysis Note Asynchronous groups should not be treated as separate synchronous phases as it is possible for them to switch simultaneously Running Weighted Average Simultaneous Switching Output WASSO Analysis Running WASSO Analysis Spartan 3 Virtex 4 Virtex 5 PlanAhead contains a set of Weighted Average Simultaneous Switching Output WASSO checks to validate signal integrity of the device based on the I O pin and bank assignments made in the design To run an analysis select Tools gt Run WASSO Analysis The Run WASSO Analysis dialog box opens as shown in Figure 5 40 page 162 Pla
405. software command options and timing or physical constraints The synthesis and implementation attempts or Runs can be queued to launch sequentially or simultaneously with multi processor machines Synthesis runs use the Xilinx XST synthesis tool You can create and save Strategies which are a set of option configurations for each implementation command These Strategies are then applied to Runs for synthesis or implementation using ISE tools You can monitor progress view log reports and quickly identify and import the best synthesis and implementation results This chapter contains the following sections e Running Synthesis e Running Implementation e Monitoring and Configuring Runs e Managing Runs e Importing Run Results e Running Bitgen on an Implementation Run e Creating Strategies e Executing Runs on Multiple Linux Hosts e Interfacing with ISE Outside of PlanAhead For more information about saved Strategies see Outputs for Environment Defaults For more information about the exported files see Outputs for ISE Implementation Running Synthesis Creating and Launching Synthesis Runs Synthesis Runs can be created and launched simultaneously or created configured and launched independently PlanAhead User Guide www xilinx com 185 UG632 v 11 4 186 Chapter 7 Implementing a Design g XILINX Creating and Launching a Single Sy
406. st WGA COMP_SYNCH MGA HSYNCH WVGA OUT_BLANK_ Z WGA OUTIBLUE VGA_OUT_GREEN_0_OBUF Q Azz 0 SYSTEA_CLOCK OBUF VGA_OUT_GREEN_4_OBUF 0 vga_color_bars OBUF VGA_OUT_GREEN_2_OBUF 0 OBUF VGA_OUT_GREEN_3_OBUF 0 OBUF VGA_OUT_GREEN_4_OBUF po OBUF VGA_OUT_GREEN_5_OBUF I o Bus Pin Properties Ctrl E on Expand Cone To Flops To Primitives To IOs Select All Primitives in Schematic YGA _OUT_GREEN_7 _OBUF 0 view OBUF lt E Package Device JA Shematic Figure 8 11 Expansion of Signals in Schematic View v ie The available Expand Cone logic expansion options are e To Flops Appends the view to display the entire cone of logic to the first Flops or to any sequential element such as Block RAMs FIFOs and embedded processors e To Primitives Appends the view to display the entire cone of output logic to the first Primitives This is also the default behavior when a pins in double clicked e To lOs Appends the view to display the entire cone of output logic to the IOs This can involve a large amount of logic PlanAhead will warn and allow you to cancel the command if more than 10 levels of logic are to be appended Expanding and Collapsing Logic for Selected Instances or Modules All of the logic contained either inside of a selected module or outside in the next level of hierarchy can be expanded or collapsed instantaneously A new set of commands can b
407. st CONYDECOD IC Directory name JanAhead_Tutorial labs projects Project_2 export_viterbi_IP File types to generate Netlist EDIF Constraints UCF Constraint files to generate Physical constraints RPM constraints Figure 10 51 Export IP Wizard 3 View and edit the definable fields in the Export IP dialog box Instance Enables you to define the instance to export Use the browse button to select the instance to export The field can be seeded with a pre selected instance prior to invoking the Export IP command Directory Name Displays the directory to export the files which can be edited PlanAhead will automatically create a lt instance name gt subdirectory to include the exported files for each instance File types to generate Indicates which file types to export Netlist EDIF and or Constraints UCF Constraint files to generate Indicates which type on constraints to annotate to the output UCF file Physical constraints Will output physical constraints for all assigned instances RPM constraints Will replace the LOC constraints with appropriate RLOC and RPM set constraints 4 Click Next to continue An Export IP Summary dialog box will display the files that will be created using the command 5 Click Finish to export the files 326 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using IP Reuse Capabiliti
408. t The next page in the New Project wizard prompts you to select a product family and default part 54 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Create New Project Wizard to Create a New Project New Project Choose a Part and a Floorplan Name Enter a name for your floorplan and choose a Xilinx device Product Family virtexS Choose Part xcSvh30fF324 1 Floorplan name floorplan_1 Figure 2 22 New Project Wizard Product Family and Default Part Page 3 Select the desired target product family architecture and default part 4 Click Next Note Once a Product Family is selected for a Project it cannot be changed A new Project will need to be created to target a different architecture The Default Part however can be changed during Synthesis and Implementation Run creation and during Floorplan creation Defining the Initial Floorplan Name and Selecting a Target Device The Floorplan Name page of the New Project wizard is now invoked PlanAhead User Guide www xilinx com 55 UG632 v 11 4 Chapter 2 Creating and Managing Projects g XILINX New Project Floorplan Name Enter a name for your floorplan and choose a Xilinx device Floorplan name floorplan_1 Choose Part _ xc2v1000fg456 4 Cancel Figure 2 23 New Project Wizard Floorplan Name Page 5 Inthe Floorplan Name page view and edit the definable options Floorplan name Enter the desired name
409. t project 1 CAData PA_Projectsiproject_1 project_1 ppr project 2 CAData PA_Projectsiproject_2 project_2 ppr Open an Example Project Open one ofthe tutorial projects BFT Core Small RTL project CPU HDL Large mixed language RTL project CPU Synthesized Large synthesized netlist project Other Resources Release Notes Important information regarding this release of PlanAhead User Guide More detailed info on PlanAhead commands dialogs and buttons Methodology Guide PlanAhead Tutorials Further assistance adopting PlanAhead flows Invaluable for first time users Quick Front to Back Flow Overview HA Bin Plannina Quick Overview RA Pin Blannina lt A Console Command No Project Figure 2 2 The PlanAhead Getting Started Window 13M of 14m fit PlanAhead is now available for new or existing Projects to be opened The PlanAhead Getting Started jump page assists you with creating or opening desired Projects as well as viewing the PlanAhead documentation Note The Getting Started jump page can be displayed by selecting Help gt Getting Started PlanAhead Command Line Options PlanAhead has several command line options to control the behavior To view the PlanAhead command line options type the following command at the command prompt planAhead help A help menu will display in the shell window 36 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Invokin
410. t cannot be changed A new Project will need to be created to target a different architecture The Default Part however can be changed during Synthesis and Implementation Run creation and during Floorplan creation Importing Constraints The Import Constraints page of the New Project wizard is now invoked www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Create New Project Wizard to Create a New Project New Project Import Constraints Import physical and timing constraints from a UCF file You can also import a UCF file later with the Import Constraints command Constraints files C Data Pland amp head_Projects project_1 project_1 data floorplan_1 fp ucf Figure 2 18 New Project Wizard Import Constraints Page 5 Use the Add button to select top level UCF or NCF constraint files for import You can arrange the order in which to import these files by selecting them and using the Up or Down buttons Files can be removed from the list by using the Remove button in the dialog box If module level NCF or UCF constraints are being used do not include them here Refer to the Importing Constraints on page 68 for more information on importing module level constraints 6 To continue the wizard click Next The UCF files are imported into PlanAhead This may take a few moments The New Project Summary page is displayed next 7 To initiate the Floorplan click Finish in the Su
411. t constraints are reassigned within the new location Pblocks behave differently when location placement constraints are assigned inside of them The desired move location should contain adequate resources to assign the placement constraints The cursor will indicate legal placement sites as the Pblock is being dragged for a move If there are not adequate resources a dialog box is displayed prompting you to either remove or leave the location constraints intact Fixed and unfixed location constraints are listed separately in the dialog box which enables you to handle them differently Locking Placement During ISE Implementation Placement constraints assigned in PlanAhead are designated as fixed and when exported they will result in the locked placement during subsequent exported ISE attempts PlanAhead provides several ways to selectively clear placement constraints that provide control over which LOCs are left in place The Clear Placement Constraints wizard enables you to clear placement constraints by Pblock by selection or all but selected placement constraints You may also take advantage of Pblock based implementation and lock the placement for selected Pblocks Use the Fix Instances popup command to fix logic Setting Prohibits Prohibit constraints can be created for any logic site on the device To do so 1 Select the desired sites in the Device view You can use Select Area to select more than one site as described in U
412. tances in the Schematic View PlanAhead User Guide www xilinx com 235 UG632 v 11 4 Chapter 8 Analyzing the Design g XILINX Viewing Timing Path Logic in the Schematic View Timing paths can be selected from the PlanAhead Timing Results view and displayed in the Schematic view All of the objects on the selected path or group of paths are displayed along with the logic hierarchy boundaries and the interconnect wires RChainT opinst equaCalAinst bitREV_EQUAL cxMULT_BREi es ee multi2b_RE1_RE2 Bes SFS x TAEAE eS poms Ba VEREN Sens multi2b_HD25 Cer ors oxMULT_12_12_10_RChainTop bitRev_Equal_12 Les ya eth dpram_24b_64w_wa_tb_HD33 equalMEM equacalAFFT RChainTop RCV_802_11 Figure 8 19 Logic Hierarchy in Schematic View Note Occasionally paths displayed from trace TWX or TWR format timing reports are missing some interconnect wires This is due to logic that has been optimized out or the path during ISE implementation The objects displayed in the Schematic view are all of the actual objects contained in the selected paths However PlanAhead cannot interpolate the connectivity after objects have been optimized away and no longer exist You can use the Schematic view in conjunction with the Path Properties to easily trace the path connectivity Most times the schematic is drawn is such a way that it is easy to see the path direction For more
413. tantiated Layout Menu The Look and Feel menu has the following menu items Table A 7 Layout menu commands Command Description Load Default Layout Loads the user defined default view layout if available Save as Default Layout Saves the current view configuration as the default to be used each time PlanAhead is invoked This layout will be used each time PlanAhead is invoked On Windows the file is saved to the following area C Documents and Settings lt username gt Application Data HDI layouts application_layout default layout On Linux or Solaris the file is stored in the following area HDI layouts application_layout default layout Clear Default Layout Clears the current user defined default layout Save Layout As Enables you to save the current view configuration with a user defined name These layouts can be loaded manually each time PlanAhead is invoked The area is located on Windows in the folder shown below On Windows the layout files are saved to the following area C Documents and Settings lt username gt Application Data HDI layouts floorplan_layout lt layoutname gt layout On Linux or Solaris the files are stored in the following area HDI layouts application_layout lt layoutname gt layout Load Layout Enables you to load any of the previously saved layouts the default PlanAhead layout or the supplied PlanAhead alternate layouts Remove Lay
414. te Hosts Linux only Select this option to use remote hosts to launch job or jobs PlanAhead User Guide www xilinx com 187 UG632 v 11 4 Chapter 7 Implementing a Design g XILINX Configure Hosts Select this option to configure remote hosts Refer to Executing Runs on Multiple Linux Hosts Generate scripts only Select this option to export and create the run directory and run script but not to launch the run from PlanAhead The script can be run at a later time outside of the PlanAhead environment Do not launch the run Select this option to Create the Run in the Design Runs view but not to export the data or launch the Run yet 2 Click OK to create the Run with the selected launch options Once the Run is complete the following dialog box is displayed prompting you to take the next step G Synthesis Completed Successfully Synthesis run synth_1 has just Finished In order to do floorplanning pin planning or design analysis you must import the netlist Otherwise you can run implementation now What do you want to do with the synthesis results Import the netlist now To do this later select the run right click and choose Import Run Results Run implementation on the netlist To do this later select the run right click and choose Run Implementation O Do nothing now C Don t show this dialog again Figure 7 5 Synthesis Completely Successfully Dialog Box 3
415. ted Child Pblocks Pblocks can be created within pblocks to provide further control for constraining logic This can be extremely helpful when trying to improve performance of critical modules The top level pblock contain all the lower level pblocks during utilization estimates PlanAhead User Guide www xilinx com 293 UG632 v 11 4 Chapter 10 Floorplanning the Design g XILINX e 4 RKIDLA LP LO K lt Figure 10 10 Creating Nested Pblocks Note The ISE implementation software does not support extensive use of this feature Occasionally map and placement errors will result when creating nested Pblocks Creating Clock Region Pblocks A Pblock can be defined to include all resources within a specific clock region or regions There is a set of steps required to define a Pblock as a clock region 1 Draw a Pblock with a rectangle that encompasses the boundary of the clock region PlanAhead displays the clock region boundaries To change the color or display characteristics of the clock region boundaries refer to the Customizing PlanAhead Display Options 294 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Partitioning the Design by Creating Pblocks TT Figure 10 11 Creating Clock Region Pblocks The tool tip changes to indicate the Pblock range is a Clock Region 2 Select OK in the New Pblock dialog box to define th
416. ted to invalid configurations Show warning dialog before exiting Plandhead Ask before overwriting synthesis or implementation results Text Editor I O Placement Automatically enforce legal 1 0 placement Connectivity Display Draw nets as Mesh Tree Show connections while dragging instances Show connections for selected instances Miscellaneous Automatically check xilinx com for software updates on startup Number of recent projects to list 10 Figure B 2 Automatically Check xilinx com for Software Updates PlanAhead User Guide www xilinx com 353 UG632 v 11 4 Appendix B Installing Releases with XilinxUpdate g XILINX 354 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Appendix C Configuring SSH Without Password Prompting This appendix contains the following section e Setting Up SSH Key Agent Forward Setting Up SSH Key Agent Forward The multiple host capabilities for executing PlanAhead software runs uses Secure Shell SSH a service provided by Linux operating system and not PlanAhead Prior to configuring multiple hosts in PlanAhead you must configure SSH so that you are not prompted for a password each time you log in to a remote machine SSH configuration is accomplished with the following commands at a Linux terminal or shell Note This is a one time step and once successfully set up does not need to be repeated 1
417. terface A user specified grouping for an arbitrary set of user I O As an example this field provides a means to specify a relationship for the data address and enable signals for a memory interface Values are a text string or blank This field is optional e Signal Name The name of the User I O in the FPGA design Values are a string or blank for an unassigned Package Pin e Direction The direction of the signal Values are IN OUT INOUT or blank when a user I O is not assigned to the site e DiffPair Type Instructs the software about which pin is the N side of a differential pair and which pin is the P side This is only used for differential signals The software uses this column instead of a naming convention to figure out which pin is the N side of the pair and which pin is the P side Values are P N or blank when a user I O is not assigned to the site e DiffPair Signal Used to specify the name of the other pin in the differential pair Values are the name of the user I O or blank when unused e I OStandard The I O standard for a specific user I O When this field is blank for a user I O the software uses the appropriate device defaults Values are a legal I O standard for the user I O in the device or blank e Drive The drive strength of the I O standard for a specific user I O Not all 1 O standards accept a drive strength If this field is blank the tools will use the default Values are a number or blank e
418. th rectangles defined in the Device view appear as blue three dimensional cubes with a yellow center H pblock_RCCInst Pblocks with instances assigned and with no rectangles defined in the Device view appear as blue two dimensional squares with a yellow center pblock_channel 248 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Using the Floorplanning Environment Pblocks with no instances assigned Pblocks with no instances and with rectangles defined assigned appear as blue three dimensional cubes with a blue P in the center B pblock_viterbi Pblocks with no instances assigned with no rectangles defined appear as blue two dimensional squares with a blue P in the center B pblock_1 Working with Relatively Placed Macro RPMs PlanAhead User Guide UG632 v 11 4 Relatively Placed Macros RPMs that exist in the design are listed under the RPMs folders RPMs can be assigned to Pblocks If RPMs are assigned to Pblocks they appear in an RPM folder under the Pblock Each instantiation of an RPM is displayed in the Physical Hierarchy View Selecting an RPM in the Physical Hierarchy view will also select all of the logic found in the RPM Physical Hierarchy Od x x E pblock ep ROOT iS RPMs 1 E sdram_ctrl ROM pblock_spi_receivcer 5 Physical Hierarchy Metrics Figure 8 34 RPM Folders Displayed in Physical Hierarchy The RPM Properties view displays all inst
419. that cannot support Site them Prohibit not IOPCPR For designs that use part compatibility Error specified for checks that if any package pin does not part exist on at least one compatible part it compatibility is marked as prohibit and nothing is placed on it MGT not IOPCMGT Indicates whether part compatibility is Warning allowed for part used with two parts that have different compatibility MGT supply voltages thereby disallowing the use of MGT Regional Clock IOBUFR Checks that a regional clock terminal Error Term has no and the related BUFR are placed at BUFR site mutually routable locations Regional Clock IOBUFIO Checks that a regional clock terminal Error Term has no and the related BUFIO are placed at BUFIO site mutually routable locations www xilinx com 155 Chapter 5 VO Pin Planning Bank I O Standard Rules Table 5 3 Bank I O Standard Rules XILINX Rule Name Rule Abbrev Rule Intent Severity Bank I O BIVC IOSTANDARD based VOUT voltage Error Standard Vcc compatibility check for IOs in that bank Bank I O BIVB Checks that the I O Standard is Error Standard Support supported in the I O bank Bank I O BIVT IOSTANDARD based DCI Termination Error standard voltage compatibility check for IOs in Termination that bank Bank I O BIVR IOSTANDARD based VREF voltage Error Standard VREF compatibility check for IOs in that bank Bank I O BIVRU IOSTANDARD based VREF voltage Error Stand
420. the RTL level such that critical timing paths are confined to individual modules Critical paths that span large numbers of hierarchical modules can be difficult to floorplan 2 Register the outputs of all the modules to help limit the number of modules involved in a critical path 3 Long paths in single large hierarchical blocks can make floorplanning a difficult task Consider dividing large hierarchical blocks in the RTL 4 Ifthe design is expected to change often consider an incremental approach to synthesis In an incremental approach individual blocks can be synthesized separately or the synthesis attributes GY N_HIER HARD can be used to preserve the hierarchy Hierarchy preservation will help an incremental flow but may hurt performance since global optimizations across hierarchy are disabled This trade off needs to be considered before you embark on an incremental RTL synthesis methodology 5 Constrain the synthesis engine to rebuild or to otherwise preserve the hierarchy in the synthesized netlist Flattened netlists may be optimal from a synthesis perspective but they make it very difficult to reliably floorplan and constrain placement Consider www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Running Implementation using the options and synthesis pragmas to rebuild the hierarchy for example the XST command line option netlist_hierarchy rebuilt which is available in 9 2 and later versions Runnin
421. the appropriate PlanAhead mode Unavailable commands are shown as disabled or grayed out File Menu The File menu has the following menu commands Table A 1 File menu commands Command Description New Project Invokes the Create New Project Wizard to facilitate creating of a new Project Open Project Opens an exiting Project file that has previously been saved to disk from PlanAhead Opening a Project will also open all previously opened Floorplans associated with the Project It will also restore the latest status of all ISE software implementation runs Reopen Project Provides a list of previously opened Project to select for reopening Save Project Enables saving of the current Project Save Project As Enables saving of the current Project to another name or location Close Project Closes the active Project You will be prompted to save any unsaved changes New Floorplan Reopen Floorplan Invokes the New Floorplan Wizard to facilitate creating of a new Floorplan Provides a list of previously opened Floorplans to select for reopening Save Floorplan Saves the Floorplan in the Project You will be prompted to save any unsaved changes Save Floorplan As Saves Floorplan to a specified name and location The original Floorplan remains stored as a closed Floorplan in the Project PlanAhead User Guide UG632 v 11 4 www xilinx com 341 Appendi
422. the nets connected to the selected elements To use this command instance or combination thereof pblock 2 Select Show Connectivity from the popup menu Select a net 1 all of the nets connecting to that element For example if an instance or Pblock is selected will be highlighted ARDIE wee oP ee goog PY FFF Eme PPP S eee T e TTT TTT gt 4 gt F Package Device x 22 Schematic Figure 9 3 Net Connectivity in the Device View PlanAhead User Guide www xilinx com 276 UG632 v 11 4 g XILINX Exploring Logic Connectivity The Show Connectivity command can be continuously run on newly selected objects by toggling the Show connections for selected instances toolbar button on and off fe Figure 9 4 Show connections for selected instances Mode Toolbar Button Selecting a Cone of Logic The Show Connectivity command can be run sequentially to continue to select and expand a logic cone 1 Select a net pblock instance or combination thereof 2 Select Show Connectivity from the popup menu The command will highlight all nets connected to the selected element as described above 3 Select Show Connectivity from the popup menu a second time The command will select the set of connected instances to those nets 4 Select Show Connectivity from the popup menu a third time The command will highlight the next level of nets connected to the selected instances and so on Thi
423. the number of aggressive outputs on one bank s power system The offending group can use I O standards that have a lower SSN impact Changing to a lower drive strength a parallel terminated DCI I O standard or a lower class of driver can improve SSN for example changing SSTL Class II to SSTL Class I The offending group can be phase shifted by 90 degrees if at DDR rate or by 180 degrees if at SDR rate This puts half the aggressive output switching out of phase with the other half and instead of interfering constructively it interferes destructively If the Result is a Fail condition assign phase groups to ports that are switching concurrently See Defining the I O Port Switching Phase Groups www xilinx com 159 Chapter 5 VO Pin Planning g XILINX Viewing I O Bank Properties Selecting an I O bank in the SSN Results view displays information about the I O ports pins and groups assigned to the I O bank in the I O Bank Properties view Select the General tab to view information about the number and types of Ports assigned to the I O Bank Select the Package Pins or I O Ports tab to view the detailed information about the Pins or Ports within the bank as shown in Figure 5 38 Name Prohibit Port ii Diff Pair Clock Voltage Min Trace Dly Max Trace Dly IOB Alias Site Type LEN 2UserIO L7P 16 T13 2 User IO L7N i 41 21 IOB_X1Y44 17 N11 2 User IO L8P A 15 97 IOB_X1 43 18 M11 2UserIO L8N i 8 01 IOB_X1 42 I0_L8N_
424. the other PlanAhead views The DCI Cascades are displayed in the Physical Hierarchy view as shown in Figure 5 32 DCI_CASCADE Properties Ehecha gt Pah x w m DCI Cascade 14 Id Name Master BI Netlist es Sources _ Properties h floorplan_1 E ROOT 3J DCI Cascade 1 CI Cascade 14 B m ale Figure 5 32 Viewing DCI Cascades 150 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Running I O Port and Clock Logic Related DRCs Editing a DCI Cascade You can modify DCI Cascades by selecting the desired DCI Cascade in the Physical Hierarchy view and using the DCI_CASCADE Properties view To save all changes click the Apply button in the DCI_CASCADE Properties view The Master can be changed by selecting a new master I O Bank I O banks can be removed from the DCI Cascade by selecting the I O banks in the DCI_CASCADE Properties view and clicking the Delete I O Banks button Additional I O banks can be included in the DCI Cascade by selecting them in the DCI_CASCADE Properties view and clicking the Add I O Banks button The Add I O Banks dialog box is displayed allowing new I O banks to be selected The newly selected I O banks are highlighted in the other PlanAhead views DCI Cascade constraints can be removed by selecting the constraint in the Physical Hierarchy view and using the Delete command Running I O Port and Clock Logic Related DRCs Running DRCs Plan
425. the search paths to the HDL files and libraries PlanAhead will then import the I O ports from the HDL files www xilinx com 137 Chapter 5 VO Pin Planning g XILINX UCF Format File PlanAhead lets you import a UCF format files as a way to populate the I O Ports view To import I O port definitions from a UCF file select File gt Import I O Ports gt From UCF Because the UCF format does not define port direction the Direction fields will display lt undefined gt Select the Set Direction command from the I O Ports popup menu to define I O port direction For more information see Setting I O Port Direction Defining and Configuring I O Ports I O ports can be created and configured using the PinAhead interface Empty Projects can be created and an I O port list can be easily generated Creating I O Ports To create I O ports 1 Inthe I O Ports view select Create I O Ports from the popup menu The Create I O Ports dialog box opens G Create 1 0 Ports Name port_1 mp Direction Input v Diff Pair port_i_P port_1_N _ om e 318 Configure I O Standard L YDS_25 default Drive Strength Slew Type Pull Type NONE default w Phase default Figure 5 15 Create I O Ports dialog box 2 View and edit the options in the Create I O Ports dialog box Name Enter the name of the desired port or bus to create Direction Select the desired port dir
426. tic Placed Instance Fixed Instance a3 Tile Site Strategies BEL RAM Mult iPower PC Gigabit Transceiver Clock Region Path T V4 DSP Text Editor V4 BRAM IDCM 1V4 CCM V4 SYSMON GT Clock i 4 Reg Clock General ms 255 200 0 KS ES ES ES ES ES ES ES SYS RS ES SYS KS ES ES KS ES SYS ES ES SKS T EKAAAAAAAR00ORAKKARKARIAAAARARAR R General Device I Os Bundle Nets 4 gt Figure 4 22 Theme Options Device Settings The check boxes can be toggled to the desired display effect In the Display column toggle the check boxes off to hide the object types in the Device view In the Select column toggle the check boxes off to make the object types unselectable in the Device view They will still be visible if the Display toggle is on Note The Frame and Fill color options are not available for certain object types Note Some of the object types are device specific so they have no effect in some devices Setting Package View Display Options The I Os tab allows you to adjust the default color visibility and selection options for each object type in the Package view 114 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Configuring the Viewing Environment G PlanAhead Options Plandhead Dark Theme Selection Rules DF D J20 Shortcuts an rategie G eneral LD Text Editor JE Object Type II O Pin Input
427. timing constraints defined in the design select the Constraints view tab or select Window gt Constraints The Constraints view will appear www xilinx com 243 XILINX Chapter 8 Analyzing the Design Constraints 409 Clik period PERIOD 2 Basic period 0 Timespec period 1 amp TIMESPEC TS_GCLK_F PERIOD GCLK_F 16 ns HIGH 50 Derived period 1 TIMESPEC TS_CK_MIC_O PERIOD CK_MIC_O TS_GCLK_F 1H gt Pad clk offset OFFSET 10 Input pad to clk offset 7 Clk to output pad offset 3 A OFFSET OUT 14 5 ns AFTER GCLK_F TIMEGRP ASIC_ST_DAT_REQ_T_I OFFSET OUT 11 5 ns AFTER OFFSET OUT 11 5 ns AFTER CK_MIC_O Path delay FROM TO 0 Time groups 390 Basic group TNM 390 4 Multi group TIMEGRP 0 False path TIG 7 Object False path 0 Group False path 7 OFf chip delay 0 Figure 8 27 Constraints Grouped by Type The constraints are displayed in two different ways As shown above categorically sorted by type allowing expansion and collapsing of the levels of constraint types Notice the number of each type of constraint is displayed in parenthesis To view a list of all timing constraints click the Group by type toolbar button in the Constraints view i Figure 8 28 Group by Type Toolbar Toggle Button When timing constraints are displayed as a list they look as follows 244 www xilinx com PlanAhead User Guide UG632 v 11 4 XIL
428. tion The ChipScope debug wizard is the easiest and fastest way to add debug cores in the PlanAhead design tool Figure 11 4 The first step in using the wizard is to select a set of nets for debug either using the unassigned nets list or direct net selection The next step is to invoke the wizard using Tools gt Set Up ChipScope and to follow the instructions screen by screen to connect and configure the debug cores Netlist Od g x Window Select Layout Help Create Phlocks Nets 112 Auto create Pblocks amp 1 Select Nets saat Ao Place Pblocks amp for Debug o b Auto place O Ports amp Clear Placement Constraints clk1_BUFGP Schematic F4 k amp clk2 Show Connectivity Ctrl T a clk2_BUFGP mm Show Hierarchy F6 amp clk3 a Fane ent een clk3 BUFGP Run TimeAhead led_O_OBUF Run Elaboration F10 led_1_OBUF Run DRC iE s eae ane Open PinAhead amp ed_s_ un SSN Analis led_4_OBUF MB Run SSN Analysis led_5_OBUF gt Run Synthesis Fil led_6_OBUF gt gt Run Implementation amp led_7_OBUF i inl pin L pin_OBUF 2 Invoke B Primitives 12 Wizard E i_big_bad_adder big_bad_ade ELi cane ee intnr 2 Options preamen pa gt Figure 11 4 Selecting Nets for Debug and Launching the ChipScope Wizard 332 www xilinx com PlanAhead User Guide UG632 v 11 4 XILIN
429. tion The ChipScope Pro 11 1 Analyzer tool and the Xilinx Platform USB cable are required for runtime design debugging For more information about ChipScope Pro see the ChipScope Pro 11 1 Software and Cores User Guide located at http www xilinx com support documentation index htm Limitations of the PlanAhead ChipScope integration are as follows e This flow is not compatible with the Project Navigator ChipScope Pro Core Inserter flow e This flow is not available when in ISE Integration mode e Pre existing debug cores connected to a ChipScope Pro ICON core may be viewed but not changed e This flow is not compatible with pre existing ICON generated without a BBSCAN primitive that requires connection to a BSCAN primitive instantiated outside of the core e Since the PlanAhead tool adds debug cores to the post synthesis design netlist some nets may be unavailable for debugging due to trimming or other optimization that takes place during the synthesis process e Currently only the ChipScope Pro ILA cores may be created and connected using this flow e Probing inside NGC core files is limited to interface signals only e PlanAhead 11 ISE 11 and ChipScope Pro 11 tools must be used with this flow Mixing and matching tool versions is not supported Using the Core Insertion Flow 330 Insertion of ChipScope debug core in the PlanAhead tool is presented in a layered approach to address different needs of the diverse group o
430. tlist updates Invokes the Export Netlist dialog box to export a EDIF format netlist file to use in ISE Invokes the Export Constraints dialog box to export floorplan constraints to use in ISE Exports a matching netlist and physical constraint file for a selected Pblock or Pblocks Exports a logic instance in logical format along with the placement constraints facilitating hard IP reuse Placement constraints can be created using LOC BEL RLOC and SLICE constraints Export I O Ports Exports a Comma Separated Values CSV format User Constraints File UCF format or HDL file port list from PinAhead for use in PCB schematic symbol or RTL Header generation Print Prints the current view This command is only available when the Schematic view Device view Package view or Instance Hierarchy view is active Exit Closes the application Edit Menu The Edit menu has the following menu commands Table A 2 Edit menu commands Command Description Properties Invokes the Properties view which displays more information about the currently XILINX selected object 342 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Main Menu Commands Table A 2 Edit menu commands Delete Removes the currently selected object s Unplace Unplaces the selected primitive instances and or I O ports Undo Reverses the previously run Tcl com
431. tly no floorplans defined against this synthesized netist To enable all Plandhead features such as I O pin planning timing analysis and floorplanning it is necessary to first create a flooorplan Create Floorplan after importing PI a nAhead To import this run click Next Figure 7 29 Import Synthesis Results The Create a Floorplan after importing option is selected by default Deselect the option if you do not wish to create a floorplan PlanAhead User Guide www xilinx com 205 UG632 v 11 4 206 Chapter 7 Implementing a Design XILINX Creating a Floorplan with Synthesis Results The Choose a Part and a Floorplan Name dialog box of the Import Synthesis Results wizard is now invoked Import Synthesis Results Choose a Part and a Floorplan Name Enter a name for your floorplan and choose a Xilinx device Choose Part xcSvsx35tfF665 1 Floorplan name floorplan_1 i Cancel Import Synthesis Results Choose Part and Floorplan Name Figure 7 30 3 Set the following editable options in the Floorplan Name dialog box Choose Part Use the files browser to invoke the Select Part chooser which enables you to select a desired device Floorplan name Enter the desired name for the floorplan 4 Click Next to continue The Import Constraints dialog box of the New Project wizard is now invoked www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX 7 Importing Run Results
432. to better scroll and read results while the command is running Viewing Report Files Report files generated by the ISE tool can be viewed from with PlanAhead Select the Run and then select the Reports tab in the Run Properties view to display the list of available report files gt Blr DV synth2 Name Modified Synthesis xst B XST Report 1 2 09 8 13 PM General Options Monitor Reports Selection Figure 7 22 Selecting Report Files to View Selecting any of the available report files will display it in the Workspace view PlanAhead User Guide www xilinx com 201 UG632 v 11 4 Chapter 7 Implementing a Design g XILINX ifelease 11 1 xst 1 27 nt 2 Copyright c 1995 2008 Xilinx Inc All rights reserved 3 gt Reading design synth_2 prj 4 5 TABLE OF CONTENTS 6 1 Synthesis Options Summary 7 2 HDL Compilation E x 68 3 Design Hierarchy Analysis d 3 4 HDL analysis ep 10 5 HDL Synthesis IL 5 1 HDL Synthesis Report 12 6 Advanced HDL Synthesis y 13 6 1 Advanced HDL Synthesis Report 14 7 Low Level Synthesis 15 68 Partition Report 16 9 Final Report i 9 1 Device utilization summary 168 9 2 Partition Resource Summary 19 9 3 TIMING REPORT 20 21l 22 Ssssssssssssssssssssssss esses sess esses ss sssssssssseseesssssssssses 23 Synthesis Options Summary 24 ssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssss eai Source
433. to PlanAhead which may take a few moments A status bar is displayed for each netlist imported Any information regarding warnings and errors will be displayed in the Console view and written to the planAhead 1og file A successful file parser message should be displayed Updating a Module Level Netlist The PlanAhead Update Netlist command enables you to import either a new module level or top level netlist as the basis for module replacement You can select any module contained in the newly imported netlist to replace any module in the existing project The only caveat is that the module port interface remains the same This often requires certain synthesis parameters to ensure that logic is not optimized across hierarchical logic module boundaries Refer to the appropriate synthesis documentation for more information on preserving hierarchy PlanAhead can import module level incremental netlists from synthesis This capability enables designers to implement an incremental synthesis strategy as well Note When a design is re synthesized lower level net and instance names often change This causes a mismatch if the Floorplan contains instance level constraints such as LOCs To avoid potential problems during update PlanAhead will unload the module constraints prior to updating the netlist After the update the constraints can be re imported and those that match will get assigned This usually is only an issue if placement constraints are defined
434. ton The Run DRC dialog box will appear G Run DRC Results Name results_1 Rules to Check 52 of 52 tag Oa A a 5 H All Rules 52 4 Floorplan 5 B m PBlock 5 M Longest carry chain height LOCH iM Pblock overlap FLBO M Resource utilization UTLZ iM Area group tile alignment FLEA M Clock 5 Mi ClkBuf 2 M Bank 9 M IOB 23 W DSP48 5 A DSP output registers DPOR A DSP input registers DPIR MJ DSP output pipelining OPOP DSP multiplier output pipelining DMOP 4 DSP input pipelining DPIP B m RAMB16 1 iM RAMB16 output registers RBOR MI Netlist 2 SM Net 1 MI Driverless Nets NDRY a m Instance 1 iM Black Box Instances INBB Figure 8 48 Run DRC Dialog Box Netlist and Floorplan Rules E if if 2 View or edit the Results Name field Enter a name for the results for a particular run for easier identification during debug in the DRC Violations browser The output file name will match the name entered 3 Inthe Rules to Check group box use the check boxes to select the design rules to check for each design object For a description of each rule see DRC Rule Descriptions Expand the hierarchy using the Expand All toolbar buttons or click the next to each category or design object Click the check box next to the design object to run all DRCs click individual DRCs to run individual ones or click All Rules to run a complete DRC
435. traint name for the paths listed o o Name A sequentially number that can be used to sort back to the original order Type Displays whether the path is Setup or Hold related Slack Displays the total positive or negative slack on the path From Displays the path source pin To Displays the paths destination pin Total Delay Lists the total estimated delay on the path Logic Delay Lists the delay attributed to logic delay only Net Displays the percentage of the delay attributed to routing interconnect Stages Displays the total number of instances on the path including the source and destination which both contribute to the overall delay This may be different than the method used to calculate levels of logic in ISE Note In TimeAhead a carry chain interconnect is counted as individual stages of logic Sorting the Timing Report The Timing Results can be sorted by clicking any of the column headers For example click on the Slack column header to sort the list by slack Click the Slack column header a second time to reverse the sort order You can sort by a second column by pressing the Ctrl key and clicking a second column header You can sort by as many columns as necessary to refine the list order Name P Path3 P Path4 P Paths P Path P Paths P Paho P Path 10 Type Slack 1 From To Total Delay Logic Delay Net Stages Setup 0 250 usbEngine1 j usb_dma_wb_in BU2 U
436. type of source VHDL Verilog Core SDC or XNF e Library Displays the VHDL library defined for each file e Location Displays the location of the imported or externally references files e Local Indicates whether the files were imported into the Project or referenced remotely Displaying Sources According to Category The sources can be grouped according to category The selection menu in the upper right corner of the Sources view is used to select the format to display the project sources e Select Group by Type to organize the source by VHDL Verilog Cores SDC or XNF e Select Group by Source Root to organize the list by source directory or location e Select Flat View to list all sources sorted alphabetically www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Project Environment a ee ari Flat view id Name Type Library Location Group by Type 1 h round_4 vhdl VHDL bFtLib C Data Plana Sroup by Source Root 2 vi round_3 vhdl VHDL bFtLib C Data Plana Flat view 3 Wf round_2 vhdl VHDL bFELib C Data Plan4head_Designs NewDemo sr 4 Wi round_1 vhdl VHDL bftLib C Data Plan4head_Designs NewDemo sr 5 wf core_transform vhdl VHDL bftLib C Data Plandhead_Designs NewDemo sr 6 wh bft_package vhdl VHDL bFtLib C Data Plan4head_Designs NewDemolsr 7 wb_conmax_top Yerilog work C Data Plan4head_Designs NewDemo sr 8 wb_conmax_slave_if v Verilog work C Data Plan4head_Designs NewDemo sr 9 wb_co
437. ultaneous Switching Output WASSO Analysis To run the SSN predictor 1 Select Tools gt Run SSN Analysis The Run SSN Analysis dialog box opens 3 Run SSN Analysis Results Name results_1 Export to File Cancel Figure 5 36 Run SSN Analysis Dialog Box 2 Optionally enter a name in the Results Name field to identify the results in the SSN Results view 3 Optionally select Export to File and enter an output file name in the Output File field and browse to select a location to write an external CSV format report file 4 Click OK www xilinx com 157 Chapter 5 VO Pin Planning XILINX Viewing the SSN Results The SSN Results view is shown in Figure 5 37 lt Name aV I O Bank 2 0 aV IJO Bank 3 0 aV 1 0 Bank 4 0 way IJO Bank 11 0 aV IJO Bank 12 0 aav I O Bank 13 0 ae I O Bank 15 20 S Group 1 20 WJ XcvSelect_pad_1_o T phy_rst_pad_i_o lt Control_pad_1_o 3 lt Control_pad_1_o 2 Noise V Margin v I O Std Result Notes Contributed Bank Total Available Remaining PASS No I O ports assigned to bank PASS No I O ports assigned to bank PASS No I O ports assigned to bank PASS No I O ports assigned to bank PASS No I O ports assigned to bank PASS No I O ports assigned to bank LYCMOS25 0 197 PASS LYCMOS25 0 197 5 results_1 12 of 12 Banks Passed x E Console DRC Results D gt I O Ports Design Runs fi 158
438. und_i 272 SSRB tied_to_ground_ij 273 CLKB tied_to_ground_i 274 le 275 276 277 endmodule 278 279 3 280 a y ne E t RTL Schematic 2 RTL Schematic 2 4b E Name 5 All Violations 37 GH RTL 3 B Power 2 Constantly enabled synchronous RAM RPRC Q RPRC 1 Warning RPRC 2 Warning Performance 35 Inefficient library element instantiation RP RPWL 1 O RPWL 2 Warning RPWL 3 Warning RPWL 4 Warning Severity Details nce dual_port_block_ram_i of type RAMB16 An instance dual_port_block_ram_i of type RAMB16_536_536 from another FPGA Family is Found T 4n instance dual_port_block_ram_i of type R4MB16_536_536 From another FPGA Family is Found T An instance dual_port_block_ram_i of type RAMB16_536_536 From another FPGA Family is Found T Block RAM UO blk_mem_generator valid cstr ramloop 0 ram r v5 ram SP WIDE_PRIM18 5P has UO Block RAM UO blk_mem_generator valid cstr ramloop O ram r v5 ram SP WIDE_PRIM18 5P has UOJ From another FPGA Farm found T Q results_1 37 violations Figure 6 19 Selecting the Objects that are Violating DRCs Some of the navigation functions in this view are as follows Properties view Select any of the violations to display information about the violation in the Violations PlanAhead User Guide UG632 v 11 4 www xilinx com 179 Chapter 6 Creating and Analyzing the
439. urces you can click on the Library field and enter a library name for the file G Add Sources Id Name Library Location wh 4 fcore_transform vhdl wal Data PlanShead_Designs Plan4head_Tutor work Add Files Add Directories Import Sources into Project Figure 6 5 Changing Source Library in Add Sources Dialog Box Copying Sources into Project Directory In order to provide flexibility on how the project is managed PlanAhead can reference either the original source files in a remote location or the source file copied to the project directory Copying the files to the project is recommended if you plan to move or archive the PlanAhead project as all of the files are self contained within the project If sources are left in a remote location rather than copied updates and maintenance can be easier as only one copy is maintained PlanAhead User Guide www xilinx com 169 UG632 v 11 4 Chapter 6 Creating and Analyzing the RTL Design g XILINX Sources are copied locally when you select the Import Sources into Project in the Add Sources dialog box Source files and directories can also be selected in the Sources view and copied into the Project using the Import into Project popup menu command Creating a New Source File New Verilog or VHDL source files can be created by using the Create Source command The New Source File dialog box appears 1 Define the following information Name Enter a name for the
440. uring SSH Without Pass word Prompting 355 Block based design Creating and Reusing an IP Module 325 Exporting Pblocks for implementa tion in ISE 215 Implementation Pblocks 194 Bundle Nets See Connectivity C ChipScope Implementing 340 Integration 329 Opening ChipScope Analyzer 340 Using Core Insertion 330 Clock Regions 225 Close Floorplan 75 Close Project 61 Commands 341 Common popup menu and view specific toolbar commands 251 Main menu 341 Toolbar 347 Connectivity 276 Adjusting Bundle net defaults 311 Analyzing hierarchical 258 Displaying Bundle net properties and content 310 Expanding logic in the schematic 276 277 Using connectivity display to place Pblocks 309 Console view 105 Using Tcl help 106 Using the Command line 105 Constraints 68 DCI_CASCADE 149 Importing constraints 68 Importing module level constraints 69 Constraints view 243 Adding new timing constraints 246 Modifying timing constraint values 245 Removing timing constraints 247 Create a New Project 39 Create I O Port Interface 141 Create I O Ports 138 Create Source 170 CSV port list See PinAhead CSV file Cursor 111 Using the Context Sensitive Cursor 111 Custom layout 122 D DCI_CASCADE constraint 149 Default layout 123 Delete Floorplan 76 Design flow 19 Basic 20 Design analysis floorplanning 21 Diagram 20 Run experimentation 20 Design resource utilization statistics 253 Exporting 254 257 Design Runs vie
441. utput files for use later in the design flow when RTL sources or netlists are available The output files can also be used to create schematic symbols for use in the printed circuit board PCB design Empty Projects can also be created to simply explore the logic resources available in the different device architectures RTL Source Based Projects PlanAhead can be used to manage the entire FPGA design flow from RTL creation through bitstream generation Projects can be created by importing RTL source files as well as precompiled NGC NGO format Xilinx cores You can elaborate and analyze the RTL to ensure proper constructs launch and manage various synthesis and implementation runs and analyze the design and run results You can also create Floorplans to experiment with different constraint or device strategies Synthesized Netlist Based Projects You can also create Projects from designs that were synthesized outside of PlanAhead using XST or any supported third party synthesis tool PlanAhead will import either EDIF or NGC NGO format netlists The netlist can be all inclusive in one file or hierarchical in nature consisting of multiple module level netlists You can analyze the logic netlist www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Using the Create New Project Wizard to Create a New Project launch and manage various implementation runs and analyze the design and run results You can also create Floorplans to exp
442. utton The Group by Constraint toolbar button toggles between a categorized list of constraints and a flattened list of paths Removing Paths from the Timing Report Paths can be selectively removed from the timing report to make for easier sorting and viewing of critical paths 1 Select the paths to remove paths from the timing report To select multiple paths use the Shift or Ctrl keys and select the paths 2 Press the Delete key or select Delete from the popup menu in the Timing Results view 268 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Analyzing the Synthesized Design Displaying Path Details When a path is selected from the list the Path Properties view is populated with information about the path All logic elements are listed with detailed delay information and hyperlinks Summary Name P Path Slack 0 161 Source A usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 fofifo18_36 fblkjinst_few k1 1 inst_fed one_prim inst_fifoprim gfifo36 sngfifo36 fifo36_wrap_inst DOP 1 Destination usbEngine0 usbEngineSRAM BUZ2 UO blk_mem_generator valid cstr ramloop 0 ram r v5 ram SP WIDE_PRIM18 5P Requirement 3 800 Delay 3 961 Source Clock usbClk rising at 0 000ns Destination Clock usbCik rising at 3 800ns Source Clock Path Delay Type Delay Cumulative Location PBlock Logical Resource 0 000 s AB19 D usbclk net fo 0 0 000 E 4619 D usbClk_ibuf ibufg I IBUFG 0 818 E A819 A usbClk
443. ve Floorplan commands described in Chapter 10 Floorplanning the Design the NGC and NGO core logic is filtered out of the netlist and black box modules are created The original source NGC and NGO core files are copied into the save or export directory This ensures that these original NGC and NGO core files are used during ISE implementation Note The output log for the ngce2edif command can be viewed in the PlanAhead terminal window where PlanAhead was invoked Occasionally the ngc2edif command produces EDIF that is unusable or that now has discrepancies with the accompanying NCF constraints Please report these issues to Xilinx along with the data to reproduce it You may continue to floorplan without the cores imported PlanAhead creates black boxes for the missing logic Then you ll need to copy the NGC core files netlists to the ISE run directory XST Constraint Files XCF PlanAhead supports adding XST Constraints Files XCF format as sources to configure XST synthesis runs I O Port Lists CSV A Comma Separated Values CSV format file can be imported to populate the I O Ports view within PinAhead You can then assign these I O Ports to physical package pins to define the device pin configuration Refer to Chapter 5 I O Pin Planning for more information about the CSV file content and format www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Input and Output Files I O Port Lists HDL
444. ve up to 10 of the dissipated BlockRAM power Shallow RAM RPRS Virtex 5 and Virtex 6 devices For wide Warning implemented in over 18 bits and shallow 64 bits or less Block RAM RAM it is generally advantageous to choose SelectRAM LUT based RAM referred to as distributed RAM whenever possible unless the RAM is being used as a FIFO in which case the cross over point becomes a depth of 32 bits or less When building interfaces less than 18 bits wide the LUT based SelectRAM could be a better choice for depths up to 128 bits however generally past that the dedicated BlockRAM is a better choice for power Inefficient RPDS Small multipliers mapped to DSP or to other Warning mapping of hard multipliers IP such as MULT18X18 small multiplier should be pushed to MSBs The rest of the in DSP block LSBs should be mapped to ground In this way the carry propagation is reduced to its minimum Usual implementation especially when inferring the multiplier uses LSBs and sign extensions to map the MSBs www xilinx com 181 Chapter 6 Creating and Analyzing the RTL Design 182 Table 6 2 Performance Rules XILINX Rule Name Inefficient library element instantiation Rule Abbrev RPWL Rule Intent Found instance lt instance name gt of type library_component_name which belongs to another FPGA family This may result in suboptimal performance The ISE software may automatically remap this element onto a
445. vice view either as rectangles within their respective assigned sites or logic functions symbols within the site BEL Placement Constraint BEL Basic Element BEL constraints can be assigned to the leaf level instances that have placement sites assigned to specific logic device gates Assigning a BEL constraint will result in a LOC and a BEL constraint being fixed and written in the exported UCF files for the instance Depending on the zoom level these LOCs appear in the Device view either as rectangles within their respective assigned Sites or as logic functions symbols within the site O Port I O Ports are the user I Os intended to be assigned to physical package pins Each I O signal is defined as a Port Package Pin Package Pins are the physical pins of the package to which I O Ports are assigned The Package Pins are grouped into I O Banks Refer to the device specifications for more information about the Package Pins and I O Banks www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Chapter 2 Creating and Managing Projects This chapter contains the following sections e Invoking PlanAhead e Using the Getting Started Jump Page e Understanding the Different Types of PlanAhead Projects e Using the Create New Project Wizard to Create a New Project e Managing Projects e Working with Floorplans Invoking PlanAhead Note Refer to the Xilinx ISE Design Suite Inst
446. vice view toolbar button fi Figure 10 7 Set Pblock Size Toolbar Button 3 Draw a rectangle in the Device view Creating Non Rectangular Pblocks PlanAhead supports having non rectangular Pblock shapes with multiple rectangles per Pblock To add additional rectangles to existing Pblocks with rectangles use the Add Pblock Rectangle toolbar button g Figure 10 8 Add Pblock Rectangle Pblocks with multiple rectangles will appear as separate rectangles with a dashed line connecting them 292 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Partitioning the Design by Creating Pblocks KRKIDBLAPL OF K lt E Package P Device x i Figure 10 9 Pblock with Multiple Rectangles Selecting a Pblock with multiple rectangles defined will select all of its rectangles They may be moved individually or together as a group To reshape one of the rectangles of a multiple rectangle Pblock select a rectangle and use the Set Pblock Size command or manually stretch to resize it To select a rectangle individually use one of the following methods e Select the Select popup command to select a single Pblock rectangle e Use the Pblock Properties Rectangles tab to select them individually Pblocks defined that span PowerPC and MGT sites may automatically receive multiple rectangle regions This is done to enable the correct rectangle ranges to be defined for implementation Creating Nes
447. w Import Run 205 207 Run BitGen 208 Device compatibility 134 Device view 132 221 Displaying clock regions 225 Opening multiple Device views 226 Placing I O Ports 143 Printing 226 Viewing device resources 223 Display options 112 Documentation Understanding terminology 32 DRC 259 I O Pin and Clock Rules 152 154 I O related 128 143 RTL related 178 Rule Descriptions 154 180 262 Running DRC 259 Viewing violations 153 179 261 E Elaborate the RTL design 173 Using filters 175 Viewing results 174 error file for debugging Xilinx Technical Support 25 F Find 270 Searching for objects using the Find command 270 Using Find in Files 172 Using the Find Results view 173 272 Fixed constraints 315 Floorplan Editor transition to PlanAhead 86 Floorplan See Project Floorplan Floorplanner transition to PlanAhead 90 Floorplanning 287 Connectivity See Connectivity Manipulating Pblocks 296 Assigning logic to Pblocks 298 Creating child Pblocks 293 Deleting a Pblock 302 Moving Pblocks 299 Removing a Pblock rectangle 301 Renaming a Pblock 302 Stretching a Pblock 300 Unassigning logic to Pblocks 299 Viewing Pblock Properties 302 Partitioning design with Pblocks 288 Draw Pblock command 288 New Pblock command 290 Using New Pblocks command for selected modules 290 Understanding Pblock graphics 296 Using connectivity display to place Pblocks 309 PlanAhead User Guide UG632 v 11 4 www xilinx
448. w or rows in the Timing Results view The path is highlighted in the Device view Multiple paths can be selected and all instances found in the path will be selected and highlighted www xilinx com PlanAhead User Guide UG632 v 11 4 g XILINX Analyzing Placement and Timing Results Path Properties Og 4x o Bil zs P Path7 Summary a 6 Slack 0 161 Source Gi usbEngineO usb_dma_wb_in BU2 U0 gen_fifo18_36 Fofifo18_36 fbikfinst_few k1 1 inst_fedfone_prim inst_fifo FE usbEngineO usbEngineSRAM BUZ UO blk_mem_generator valid cstr ramloop O ram r v5 ram SP WIDE_PRIM18 Requirement 3 800 Delay 3 961 Source Clock usbClk rising at 0 000ns Destination Clock _usbClk rising at 3 800ns Source Clock Path Delay Type Delay Cumulative Location PBlock Logical Resource 0 000 0 000 E A819 D usbclk net fo 0 0 000 AB19 D usbClk_ibuffibufg t IBUFG 0 818 AB19 usbClk_ibuffibufg o net fo 1 0 000 BUFGCTRL_X0Y9 D usbClk_ibuf bufg I BUFG 0 250 BUFGCTRL_X0Y9 lt usbCik_ibuf bufg O net fo 407 2 033 3 101 E RAMB36_x2V1 pblock_usbEngine0 gt usbEngine0 usb_dma_wb_in E Fotal 3 101 3 101 Data Path L Delay Type Delay Cumulative Location PBlock Logical Resource FIFO36_EXP 0 818 0 818 E RAMB36_x2V1 pblock_usbEngine0 lt usbEngine0 usb_dma_wb_in BL net fo 40 1 520 2 338 E SLICE_x19Y8 pblock_usbEngine0 gt usbEngine0ju2 wsel 10 LUT6 0 094 2 432 E SLICE_x19Y8 pblock_usbEngine0 lt usbEngine0 u2 wsel O net fo 42 0 381 2 81
449. w prior to assignment The assignment order is also driven from the initial Pin that is selected for I O bank assignment Selecting a pin at one end of an I O Bank will result in a continuous bus assignment across the I O bank PCB routing concerns for busses are being considered Pin ordering during assignment attempts to keep the bus bits vectored within the assignment area Assignment patterns can be customized to address bus routing concerns Placing I O Ports in a Defined Area To place I O Ports into a defined area 1 Inthe I O Ports view select individual I O ports groups of I O ports or Interfaces 2 Use one of the following commands Select Place I O Ports in an Area from the popup menu in the I O Ports view Click the Place I O Ports in an Area button in either the Package or Device view 144 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Placing I O Ports it Figure 5 23 Place I O Ports in an Area Button The cursor turns into a cross symbol which indicates that you can define a rectangle for port placement 3 Draw a rectangle in either the Package or Device view to define the assignment area CA A Ht Ooo Saar ew oe u unne Seek sah wee Swi See S000 lets Sete wnat ee D waen vunt Saa E CEK a nat HAS ee sees webs Sees See oe uuu S258 BENU sees VONE we Figure 5 24 Placing I O Ports in an Area 4 If more I O Ports are selected than will fit in the area defined the command is c
450. x A Menu and Toolbar Commands Table A 1 File menu commands Copy Floorplan Enables copying of the Floorplan and applicable physical constraints to a new target device Close Floorplan Closes the active Floorplan or a group of selected Floorplans in the Project Closed Floorplans are stored in the Project and are available for reopen in the Floorplans view Revert Floorplan Discards all operations performed in the Floorplan since the last save and reverts the Floorplan to its original state Delete Floorplan Closes the active Floorplan or a group of selected Floorplans in the Project and removes the Floorplan data from disk Add Sources Enables the adding of source files or entire directories to the Project Create Source Opens the New Source File dialog box which enables you to create a source file Import I O Ports Imports port list from a Comma Separated Values CSV or HDL file for pin assignment with PinAhead Import Constraints Imports constraints for the displayed Floorplan A file selection dialog box appears to select a constraints file UCF format Import Placement Imports ISE placement results XDL format for either an individual Pblock or the entire design Import TRCE Results Imports results from Xilinx TRCE reports Update Netlist Export Netlist Export Constraints Export Pblocks Export IP Invokes Update Netlist Wizard for module level ne
451. xperiment information for the Floorplan e expX subdirectories Contains PlanAhead experiment information about each run Project RTL Directory lt projectname gt srcs The Project sources directory stores all of the HDL Source files imported into the Project These folders are maintained by PlanAhead and do not require your attention Caution Modifying any of these files could result in Project data corruption Outputs for ISE Implementation This section briefly describes the files created during PlanAhead ISE implementation design operations These files are maintained by PlanAhead and should not be modified manually 28 www xilinx com PlanAhead User Guide UG632 v 11 4 XILINX Input and Output Files The output files for ISE implementation are as follows e Run Directory lt projectname gt runs e EDIF Netlists edf e Xilinx Cores ngc ngo e ChipScope Core Netlists ngc e Constraint Files ucf e ISE Launch Scripts jobx bat sh amp runme bat sh amp lt ISE_command gt rst Run Directory lt projectname gt runs PlanAhead allows you to launch and queue multiple ISE implementation attempts or Runs You are prompted to enter a location to create the Runs directory The default location is in the Project directory Each run directory will contain a complete EDIF netlist and UCF constraint file for the run A run script to launch the ISE commands with y
452. y functional version of PlanAhead is supplied as a standard part of the release This section explains how to use PlanAhead for common tasks that were previously accomplished with either PACE or Floorplan Editor PlanAhead can be invoked through Project Navigator or directly from the command line prompt Integrated within the Project Navigator environment PlanAhead is launched at four different design process steps They include e I O Pin Planning Pre Synthesis e 1 0 Pin Planning Post Synthesis e Floorplan Area IO Logic Post Synthesis e Analyze Timing Floorplan Design Post Implementation Each of these steps offers unique and powerful capabilities previously only available in the standalone PlanAhead environment When PlanAhead is invoked from Project Navigator the interface provides access only to the PlanAhead features specific to the selected task Alternatively when launched as a standalone PlanAhead environment you can work with the full range of PlanAhead RTL to bitstream design and analysis capabilities For CPLD users the ISE Design Suite 11 1 still supports the use of PACE for graphical pin assignment tasks This document covers the most common tasks that you would have accomplished using PACE or Floorplan Editor mainly pin planning and area based floorplanning Each main task will be covered in its own sub section below and provide you with a brief description of how to accomplish the same task using the PlanAhe
453. ze the Pblocks to include non SLICE based logic resources Note The Automatic Pblock Placer is not available for Virtex 6 or Spartan 6 devices To run the block placer 1 Select Tools gt Place Pblocks The Place Pblocks dialog box appears www xilinx com 313 Chapter 10 Floorplanning the Design g XILINX G Place Pblocks Parent Pblock ROOT Pblocks to place Pblock Utilization pblock_cpuEngine_cpu_dbg_dat_i pblock_cpuEngine_cpu_dbg_dat_o pblock_cpuEngine_cpu_dwb_dat_i pblock_cpuEngine_cpu_dwb_dat_o pblock_cpuEngine_cpu_iwb_adr_o pblock_cpuEngine_cpu_iwb_dat_i pblock_cpuEngine_cpu_iwb_dat_o pblock_usbEngineO_usb_out pblock_usbEngine1_usb_dma_wb_in 87 ICICICICIGHCHCHGNCHE pblock_usbEngine1_usb_out 87 Set Utilization on All Pblocks i Cancel Figure 10 34 Place Pblocks Dialog Box 2 View and edit the definable options in the Place Pblocks dialog box Parent Pblock Select the level of hierarchy to place Pblocks Pblocks can be placed at the top ROOT or any partitioned Pblock level of hierarchy Pblocks to place The Pblocks that exist under the parent Pblock are displayed Place The check boxes control the Pblocks to be placed Deselecting Place preserve existing Pblock rectangle locations Pblock Lists all Pblocks Utilization Enables specific SLICE utilization targets to be set for each Pblock Set Utilization on all Pblocks

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