STM-STM32-STM32F103C8-Learning Centre MCU
Contents
1. 10 2 4 Bootloader version 11 3 STM32F105xx and STM32F107xx device bootloader 12 3 1 Bootloader configuration 12 3 2 Bootloader hardware requirements 14 3 3 Bootloader selection 15 3 4 Bootloader version 17 4 STM32F101xx and STM32F103xx XL density device bootloader 18 4 1 Dual bank boot feature 18 4 2 Bootloader configuration 20 4 3 Bootloader hardware requirements 21 4 4 Bootloader selection 22 4 5 Bootloader version 24 5 STM32L15xx Medium density Ultralow power device bootloader 25 5 1 Bootloader configuration 25 5 2 Bootloader hardware requirements 26 5 3 Bootloader selection 26 5 4 Important considerations 27 5 5 Bootloader version 28 6 Device dependent bootloader parameters 29 2 32 Doc ID 13801 Rev 10 ky AN2606 Contents 7 REVISION history 302. All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WH
3. Figure 13 Write Memory command device side modified Note added and bytes 3 and 4 sent by the host modified in Section 2 7 Erase Memory command Note added to Section 2 8 Write Protect command 09 Mar 2010 Application note restructured Value line and connectivity line device bootloader added Replaces AN2662 Introduction changed Glossary added 20 Apr 2010 08 Oct 2010 Related documents available from www st com added XL density line datasheets and programming manual Glossary added XL density line devices Table 2 added information for XL density line devices Section 2 1 Bootloader configuration updated first sentence Section 3 1 Bootloader configuration updated first sentence Added Section 4 STM32F101xx and STM32F103xx XL density device bootloader Table 12 added information for XL density line devices Added information for high density value line devices in Table 2 and Table 12 14 Oct 2010 Removed references to obsolete devices 26 Nov 2010 Added information on ultralow power devices 2 Doc ID 13801 Rev 10 31 32 AN2606 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice
4. TI AN2606 YZ Application note STM32 microcontroller system memory boot mode Introduction The bootloader is stored in the internal boot ROM memory system memory of STM32 devices It is programmed by ST during production Its main task is to download the application program to the internal Flash memory through one of the available serial peripherals USART CAN USB etc A communication protocol is defined for each serial interface with a compatible command set and sequences The main features of the bootloader are the following amp It uses an embedded serial interface to download the code with a predefined communication protocol e lIttransfers and updates the Flash memory code the data and the vector table sections This application note presents the general concept of the bootloader It describes the supported peripherals and hardware requirements to be considered when using the bootloader of any STM32 device currently in production However the specifications of the low level communication protocol for each supported serial peripheral are documented in separate documents For specifications of the USART protocol used in the bootloader please refer to AN3155 For the specification of CAN protocol used in the bootloader please refer to AN3154 For the specification of DFU USB Device protocol used in the bootloader please refer to AN3156 Related documents available from www st com Low medium and high density STM32F
5. 2 STM32F101xx and STM32F103xx XL density device bootloader Throughout this section STM32F10xxx XL density is used to refer to XL density STM32F101xx and STM32F103xx devices Dual bank boot feature For STM32F101xx and STM32F103xx XL density devices these devices have two Flash memory banks Bank 1 and Bank 2 an additional boot mechanism is available which allows booting from Bank 2 or Bank 1 depending on the BFB2 bit status bit 19 in the user option bytes amp 0x1FFFF800 1 When the BFB2 bit is reset and the boot pins are configured to boot from the Flash memory BOOTO 0 and BOOT1 x then after reset the device boots from the System memory and executes the embedded bootloader code which implements the dual bank Boot mode a First the code checks Bank 2 If it contains a valid code see Note 1 below it jumps to application located in Bank 2 and leaves the Bootloader b If the Bank 2 code is not valid it checks Bank 1 code If it is valid see note below it jumps to the application located in Bank 1 c If both Bank 2 and Bank 1 do not contain valid code see note below the normal Bootloader operations are executed as described in the following sections no jump to Flash banks is executed Refer to Figure 3 Bootloader selection for STM32F10xxx XL density devices for more details 2 When the bit BFB2 is set default state the dual bank boot mechanism is not performed The code is considered as
6. all its related pins are dedicated to USB communication only and cannot be used for other application purposes The user can control the BOOTO and Reset pins from a PC serial applet using the RS232 serial interface which controls BOOTO through the CTS line and Reset through the DCD line The user must use a full null modem cable The necessary hardware to implement for this control exists in the STM3210C EVAL board For more details about this refer to document STM3210C EVAL board user manual available from the STMicroelectronics website www st com Doc ID 13801 Rev 10 ky AN2606 STM32F105xx and STM32F107xx device bootloader 3 3 Note Bootloader selection The STM32F105xx and STM32F107xx embedded bootloader supports four peripherals interfaces USART1 USART2 CAN2 and DFU USB Any one of these peripheral interfaces can be used to communicate with the bootloader and download the application code to the internal Flash The embedded bootloader firmware is able to auto detect the peripheral interface to be used In an infinite loop it detects any communication on the supported bootloader interfaces The RX pins of the unused peripherals in this bootloader have to be maintained at a known low or high level and should not be left floating during the detection phase as described below If USART1 is used to connect to the bootloader the USART2_RX PD6 CAN2_RX PB5 OTG_FS_DM PA11 and OTG_FS_DP PA12 pins ha
7. is used also for DFU and CAN bootloaders but only for the selection phase An external clock 8 MHz 14 7456 MHz or 25 MHz is required for DFU and CAN bootloader execution after the selection phase After downloading the application binary if you choose to execute the Go command all peripheral registers used by the bootloader shown in the above table will be initialized to their default reset values before jumping to the user application If the user application uses the IWDG the IWDG prescaler value has to be adapted to meet the requirements of the application since the prescaler was set to its maximum value by the bootloader ky Doc ID 13801 Rev 10 13 32 STM32F105xx and STM32F107xx device bootloader AN2606 3 2 14 32 Bootloader hardware requirements The hardware required to put the STM32F105xx and STM32F107xx into System memory boot mode consists of any circuitry switch or jumper capable of holding the BOOTO pin high and the BOOT1 pin low during reset To connect to the STM32F105xx and STM32F107xx during System memory boot mode the following conditions have to be verified e The RX pins of the unused peripherals in this bootloader have to be kept at a known low or high level and should not be left floating during the detection phase as described below If USART 1 is used to connect to the bootloader the USART2_RX PD6 CAN2_RX PB5 OTG_FS_DM PA11 and OTG_FS_DP PA12 pins have to be kept at a hig
8. power device bootloader To use the USART bootloader on USART1 or USART2 connect the serial cable to the desired interface Once the bootloader detects the data byte 0x7F on this interface the bootloader firmware executes the autobaudrate sequence and then enters a loop waiting for any USART bootloader command Once one interface is selected for the bootloader the other interface is disabled The figure below shows the bootloader detection mechanism More details are provided in the sections corresponding to each peripheral bootloader Figure 4 Bootloader selection for STM32L15xxx devices System init clock GPIOs IWDG SysTick Ox7f received on USART1 NO Ox7f received Y on USART2 NO Disable all interrupt sources sources Execute BL_USART_Loop Execute BL_USART_Loop for USART2 for USART1 MS18283V1 5 4 Important considerations The bootloader of the Low and Medium density ultralow power devices has some specific features that should be taken into consideration as described below In addition to standard memories internal Flash internal SRAM option bytes and System memory the STM32L15xxx device bootloader firmware supports Data Doc ID 13801 Rev 10 27 32 STM32L15xx Medium density Ultralow power device bootloader AN2606 5 5 28 32 Memory 4 Kbytes from 0x08080000 to 0x08080FFF Refer to the PM0062 Programming manual for more information Flash memory write operations are performed through a program memory half pag
9. 0 ky AN2606 STM32F101xx and STM32F103xx XL density device bootloader 4 3 Note Bootloader hardware requirements The hardware required to put the STM32F10xx XL density devices into System memory boot mode consists of any circuitry switch or jumper capable of holding the BOOTO pin high and the BOOT1 pin low during reset As explained in Section 4 1 Dual bank boot feature the system memory boot mode can also be executed by software when the BFB2 bit is reset both banks start addresses are erased and boot pins are configured to boot from Flash memory To connect to the STM32F10xx XL density devices during System memory boot mode the following conditions have to be verified e The RX pin of the unused peripheral in this bootloader has to be kept at a known low or high level and should not be left floating during the detection phase as described below Ifthe USART1 is used to connect to the bootloader the USART2_RX PD6 pin has to be kept at a high or low level and must not be left floating during the detection phase Ifthe USART2 is used to connect to the bootloader the USART1_RX PA10 pin has to be kept at a high or low level and must not be left floating during the detection phase When the BFB2 bit is cleared and Bank 2 and or Bank 1 contain a valid user application code the Dual Bank Boot is always performed bootloader always jumps to the user code and never continues normal operations Consequent
10. 101xx and STM32F103xx datasheets Low medium and high density STM32F100xx and STM32F102xx datasheets STM32F105xx 107xx connectivity line datasheet XL density STM32F101xx and STM32F103xx datasheets STM32L151xx and STM32F152xx datasheet STM32F101xx STM32F102xx STM32F103xx and STM32F105xx 107xx reference manual RM0008 Low medium and high density STM32F100xx value line reference manual RM0041 STM32L151xx and STM32L152xx advanced ARM based 32 bit MCUs reference manual RM0038 STM32F101xx STM32F102xx STM32F103xx and STM32F105xx 107xx Flash programming manual PM0042 e Low medium and high density STM32F100xx value line Flash programming manual PM0063 XL density STM32F101xx and STM32F103xx Flash programming manual PM0068 STM32L151xx and STM32L152xx Flash programming manual PM0062 November 2010 Doc ID 13801 Rev 10 1 32 www st com Contents AN2606 Contents 1 General bootloader description 7 1 1 Bootloader activation 7 1 2 Exiting system memory boot mode 7 1 3 Bootloader identification 7 2 STM32F101xx STM32F102xx STM32F103xx medium density and high density value line bootloader 9 2 1 Bootloader configuration 9 2 2 Bootloader hardware requirements 10 2 3 Bootloader selection
11. AN_Loop for reset CAN2 ai17514 Doc ID 13801 Rev 10 JI AN2606 STM32F105xx and STM32F107xx device bootloader 3 4 2 Bootloader version The table below lists the bootloader versions and the changes between versions V1 0 and V2 0 of the STM32F 105xx and STM32F107xx devices Table 6 STM32F105xx and STM32F107xx bootloader version evolution Bootloader version number Description V1 0 Initial bootloader version Bootloader detection mechanism updated to fix the issue when GPIOs of unused peripherals in this bootloader are connected to low level or left floating during the detection phase For more details please refer to limitation 2 12 Boot loader unavailability on STM32F105xx and STM32F107xx devices with a date code below 937 as described in Revision 2 of the STM32F105xx and STM32F107xx revision Z errata sheet available from www st com V2 0 Vector table set to 0x1FFF B000 instead of 0x0000 0000 Go command updated for all bootloaders USART1 USART2 CAN2 GPIOA GPIOB GPIOD and SysTick peripheral registers are set to their default reset values DFU bootloader USB pending interrupt cleared before executing the Leave DFU command DFU subprotocol version changed from V1 0 to V1 2 Bootloader version updated to V2 0 Doc ID 13801 Rev 10 17 32 STM32F101xx and STM32F103xx XL density device bootloader AN2606 4 4 1 Note 18 32 1
12. ERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 32 32 Doc ID 13801 Rev 10 ky
13. General bootloader description Bootloader activation The bootloader is automatically activated by configuring the BOOTO and BOOT1 pins in the specific System memory configuration see Table 1 and then by applying a reset Depending on the used pin configuration the Flash memory system memory or SRAM is selected as the boot space as shown in Table 7 below Table 1 Boot pin configuration Boot mode selection pins Boot mode Aliasing BOOT1 BOOTO X 0 User Flash memory User Flash memory is selected as the boot space 1 System memory System memory is selected as the boot space 1 1 Embedded SRAM Embedded SRAM is selected as the boot space Table 1 shows that the STM32 microcontrollers enter the System memory boot mode if the BOOT pins are configured as follows e BOOTO 1 e BOOT1 0 The values on the BOOT pins are latched on the fourth rising edge of SYSCLK after a reset Exiting system memory boot mode System memory boot mode must be exited in order to start execution of the application program This can be done by applying a hardware reset During reset the BOOT pins BOOTO and BOOT1 must be set at the proper levels to select the desired boot mode see Table 1 Following the reset the CPU starts code execution from the boot memory located at the bottom of the memory address space starting from 0x0000 0000 Bootloader identification Depending on the used STM32 device the bootloade
14. RAM content to 0x0 before ROP disable operation Doc ID 13801 Rev 10 11 32 STM32F105xx and STM32F107xx device bootloader AN2606 3 STM32F105xx and STM32F107xx device bootloader 3 1 Bootloader configuration The bootloader embedded in the STM32F105xx and STM32F107xx devices supports four serial peripherals USART1 USART2 CAN2 and DFU USB This means that four serial peripherals are supported USART1 USART2 CAN2 and DFU USB The following table shows the hardware resources required by STM32F105xx and STM32F107xx devices used by the bootloader in System memory boot mode Table 5 STM32F105xx 107xx configuration in system memory boot mode Bootloader Feature Peripheral State Comment The system clock frequency is 24 MHz using the PLL This is used only for USART1 and USART2 bootloaders and during CAN2 USB detection for CAN and DFU bootloaders Once CAN or DFU bootloader is selected the clock source will be derived from external crystal HSI enabled The external clock is mandatory only for DFU and CAN bootloaders and it must provide one of the following frequencies 8 MHz 14 7456 MHz or RCC 25 MHz HSE enabled For CAN Bootloader the PLL is used only to generate 48 MHz when 14 7456 MHz is used as HSE For DFU Bootloader the PLL is used to generate a Common to 48 MHz system clock from all supported external all clock frequencies bootloaders The clock security system CSS interrupt is
15. adapted to meet the requirements of the application since the prescaler was set to its maximum value by the bootloader Doc ID 13801 Rev 10 9 32 STM32F101xx STM32F102xx STM32F103xx medium density and high density value line boot 2 2 Bootloader hardware requirements The hardware required to put the STM32 into System memory boot mode consists of any circuitry switch or jumper capable of holding the BOOTO pin high and the BOOT1 pin low during reset To connect to the STM32 during System memory boot mode an RS232 serial interface example ST3232 RS232 transceiver has to be directly linked to the USART1 RX PA10 and USART1_TX PAQ pins Note USART1 CK USART1_CTS and USART1_RATS pins are not used therefore user can use these pins for other peripherals or GPIOs For more details about hardware recommendations refer to application note AN2586 STM32 hardware development getting started available from the STMicroelectronics website www st com 2 3 Bootloader selection Figure 1 Bootloader for STM32F10xxx with USART1 Wait for 7Fh from host Auto baud rate sequence send ACK byte amp disable unused peripherals Wait for a command Command received GO cmd optional GET cmd Ge eee cee sload routinesa routine 1 into RAM ee ee 1 JP to Address ai14630b 10 32 Doc ID 13801 Rev 10 ky AN2606STM32F101xx STM32F102xx STM32F103xx mediu
16. and b boot pins are configured as follows BOOTO 0 and BOOT1 x Note When conditions a b and c below are fulfilled it is equivalent to configuring boot pins for system memory boot BOOTO 1 and BOOT1 0 In this case normal Bootloader operations are executed a BFB2 bit is reset b Both banks don t contain valid code c Boot pins configured as follows BOOTO 0 and BOOT1 x When the BFB2 bit is cleared and Bank 2 and or Bank 1 contain valid user application code the Dual Bank Boot is always performed bootloader always jumps to the user code and never continues normal operations Consequently if you have cleared the BFB2 bit to boot from Bank 2 then to be able to execute the Bootloader code you have to either set the BFB2 bit to 1 or program the content of address 0x0808 0000 base address of Bank2 and 0x0800 0000 base address of Bank1 to 0x0 ky Doc ID 13801 Rev 10 19 32 STM32F101xx and STM32F103xx XL density device bootloader AN2606 4 2 Note 20 32 1 Bootloader configuration The bootloader embedded in STM32F10xxx XL density supports two serial interfaces USART1 and USART2 The following table shows the required hardware resources of STM32F10xxx XL density devices used by the bootloader in system memory boot mode Table 8 STM32F10xxx XL density configuration in system memory boot mode Feature peripheral State Comment Clock source HSI enabled The sys
17. der AN2606 5 2 5 3 Note 26 32 Bootloader hardware requirements The hardware required to put the STM32 into System memory boot mode consists of any circuitry switch or jumper capable of holding the BOOTO pin high and the BOOT1 pin low during reset To connect to the STM32 during System memory boot mode the following conditions have to be verified The RX pins of the unused peripheral in this bootloader have to be kept at a known low or high level and should not be left floating during the detection phase as described below If USART1 is used to connect to the bootloader the USART2_RX PD6 pin has to be kept at a high or low level and must not be left floating during the detection phase If USART2 is used to connect to the bootloader the USART1 RX PA10 pin has to be kept at a high or low level and must not be left floating during the detection phase e The peripheral to be used has to be connected through an RS232 serial interface example ST3232 RS232 transceiver which must be directly connected to the USART1_RX PA10 and USART1_TX PA9 pins when USART1 is used directly connected to the USART2_RX PD6 and USART2_TX PD5 pins when USART2 is used The USART1_CK USART1_CTS and USART1 RTS pins are not used therefore the application can use these pins for other peripherals or GPIOs The same note is applicable for USART2 The user can control the BOOTO and Reset pins from a PC serial a
18. e write operation The bootloader firmware manages half page write operations at non aligned addresses Consequently all write operations must only be Word aligned the address should be a multiple of 4 The number of data to be written must also be a multiple of 4 non aligned half page write addresses are accepted Be aware of the duration needed for a write operation by referring to the product datasheet Data memory can be read and written but cannot be erased using the Erase Command When writing in a Data memory location the bootloader firmware manages the erase operation of this location before any write A write to Data memory must be Word aligned address to be written should be a multiple of 4 and the number of data must also be a multiple of 4 To erase a Data memory location you can write zeros at this location Option byte address is 0x1FF80000 and allow three levels of protection Protection Level 0 Protection Level 1 Protection Level 2 Refer to Programming Manual PM0062 for more details about protection levels Read protect command corresponds to the Level 1 protection Read unprotect command corresponds to the Level 0 protection Mass erase command is not supported by STM32L15xxx device Bootloader firmware To perform a mass erase operation two options are available Erase all sectors one by one using the Erase command Set protection level to Level 1 Then set it to Level 0 using the Read pro
19. enabled for the CAN and DFU bootloaders Any failure or removal of the external clock will generate system reset The independent watchdog IWDG prescaler is configured to its maximum value and is periodically IWDG refreshed to prevent watchdog reset in case the hardware IWDG option was previously enabled by the user 18 Kbytes starting from address 0x1FFF B000 System memory contain the bootloader firmware 4 Kbytes starting from address 0x2000 0000 are used RAM i by the bootloader firmware Once initialized the USART1 configuration is 8 bits even parity and 1 Stop bit USART 1 USART1 RX pin Input PA10 pin USART1 receive bootloader USART1 TX pin Output PAQ pin USART1 transmit USART2_RX PD6 CAN2_RX PB5 OTG_FS_DM PA11 and OTG_FS_DP PA12 pins must be kept at a high or low level during the detection phase USART1 Enabled 12 32 Doc ID 13801 Rev 10 ky AN2606 STM32F105xx and STM32F107xx device bootloader Table 5 STM32F105xx 107xx configuration in system memory boot mode continued Bootloader Feature Peripheral State Comment USART1 and bac Used to automatically detect the serial baud rate from USARTZ SysTick timer Enabled the host for USARTx bootloader bootloaders Once initialized the USART2 configuration is 8 bits USART2 Enabled even parity and 1 Stop bit The USART2 uses its remapped pins USART2 USART2_RX pin Input PD6 pin USART2 receive remap
20. figure USART1 Execute BL USART Loop for USART 1 Configure USART2 Execute BL USART Loop for USART2 ai17462 4 Doc ID 13801 Rev 10 23 32 STM32F101xx and STM32F103xx XL density device bootloader AN2606 4 5 24 32 Bootloader version Table 9 lists the bootloader versions for the STM32F101xx and STM32F103xx XL density devices Table 9 Evolution of the XL density bootloader versions Bootloader version Sas Description number V2 1 Initial bootloader version Doc ID 13801 Rev 10 AN2606 STM32L15xx Medium density Ultralow power device bootloader 5 STM32L15xx Medium density Ultralow power device bootloader Through all this section STM32L15xxx will be used as reference to Medium density ultralow power devices STM32L151xx and STM32L152xx devices 5 1 Bootloader configuration The bootloader embedded in STM32L15xxx devices uses configuration 2 USART1 and USART2 peripherals are supported The following table shows the required hardware resources of STM32 devices used by the bootloader in system memory boot mode Table 10 STM32L15xxx configuration in system memory boot mode Feature Peripheral State Comment Clock source HSI enabled The system clock is equal to 16 MHz USART1_RX pin Input PA10 pin USART1 receives USART1_TX pin Output PAQ pin USART1 transmits USART2_RX pin Input PD06 pin USART2 receives USART2_TX pin Output PDO5 pin USART2 tran
21. h or low level and must not be left floating during the detection phase If USART2 is used to connect to the bootloader the USART1_RX PA10 CAN2 RX PB5 OTG_FS_DM PA11 and OTG FS DP PA12 pins have to be kept at a high or low level and must not be left floating during the detection phase If CAN2 is used to connect to the bootloader the USART1_RX PA10 USART2_RX PD6 OTG_FS_DM PA11 and OTG_FS_DP PA12 pins have to be kept at a high or low level and must not be left floating during the detection phase If DFU is used to connect to the bootloader the USART1_RX PA10 USART2_RX PD6 and CAN2_RX PB5 pins have to be kept at a high or low level and must not be left floating during the detection phase Connect to the peripheral to be used through an RS232 serial interface example ST3232 RS232 transceiver has to be directly connected to the USART1 RX PA10 and USART1 TX PA9 pins when USART1 is used or to the USART2 RX PD6 and USART2 TX PD5 pins when USART2 is used aCAN interface CAN transceiver has to be directly connected to the CAN2_RX PB5 and CAN2_TX PB6 pins acertified USB cable has to be connected to the microcontroller optionally an ESD protection circuitry can be used The USART1_CK USART1_CTS and USART1 RTS pins are not used therefore the application can use these pins for other peripherals or GPIOs The same note is applicable for USART2 Once the USB Device is enabled
22. ion phase as described below If USART1 is used to connect to the bootloader the USART2_RX PD6 pin has to be kept at a high or low level and must not be left floating during the detection phase If USART2 is used to connect to the bootloader the USART1_RX PATO pin has to be kept at a high or low level and must not be left floating during the detection phase To use the USART bootloader on USART1 or USART2 connect the serial cable to the desired interface Once the bootloader detects the data byte 0x7F on this interface the bootloader firmware executes the auto baudrate sequence and then enters a loop waiting for any USART bootloader command Once one interface is selected for the bootloader the other interface is disabled Figure 3 shows the bootloader detection mechanism More details are provided in the sections corresponding to each peripheral bootloader Doc ID 13801 Rev 10 ky AN2606 STM32F101xx and STM32F103xx XL density device bootloader Figure 3 Bootloader selection for STM32F10xxx XL density devices System Reset BFB2 bit is reset BFB2 0 f value 0x0808 0000 is within int SRAM address Jump to user code in Bank 2 f value 0x0800 0000 is within int SRAM address Jump to user code in Bank 1 Continue normal Bootloader execution Disable all interrupt sources System init clock GPIOs IWDG SysTick Ox7f received Yi on USART1 NO Ox7f received on USART2 Con
23. ky Doc ID 13801 Rev 10 3 32 List of tables AN2606 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 4 32 Boot pin configuration seedi ssas eee eee 7 Embedded bootloaders asana auaa eee 8 STM32F10xxx configuration in system memory boot mode 9 STM32F10xxx bootloader version evolution 11 STM32F105xx 107xx configuration in system memory boot mode 12 STM32F105xx and STM32F107xx bootloader version evolution 17 Boot pin and BFB2 bit configuration 19 STM32F10xxx XL density configuration in system memory boot mode 20 Evolution of the XL density bootloader versions 24 STM32L15xxx configuration in system memory boot mode 25 STM32L15xxx bootloader version evolution 28 Bootloader device dependant parameters 29 Document revision history 30 Doc ID 13801 Rev 10 ky AN2606 List of figures List of figures Figure 1 Bootloader for STM32F10xxx with USART1 10 Figure 2 Bootloader selection for STM32F105xx and STM32F107xx devices 16 Figure 3 Bootloader selec
24. ly if you have cleared the BFB2 bit to boot from Bank 2 then to be able to execute the Bootloader code you have to either set the BFB2 bit to 1 or program the content of address 0x0808 0000 base address of Bank2 and 0x0800 0000 base address of Bank1 to 0x0 Connect to the peripheral to be used through an RS232 serial interface example ST3232 RS232 transceiver has to be directly connected to the USART1 RX PA10 and USART1 TX PA9 pins when USART 1 is used or to the USART2 RX PD6 and USART2 TX PD5 pins when USART2 is used The USART1_CK USART1_CTS and USART1 RTS pins are not used therefore the application can use these pins for other peripherals or GPIOs This is also applicable for USART2 Doc ID 13801 Rev 10 21 32 STM32F101xx and STM32F103xx XL density device bootloader AN2606 4 4 Note 22 32 Bootloader selection The STM32F10xx XL density embedded Bootloader supports two peripheral interfaces USART1 and USART2 Any one of these peripheral interfaces can be used to communicate with the bootloader and download the application code to the internal Flash The embedded Bootloader firmware is able to auto detect the peripheral interface to be used In an infinite loop it detects any communication on the supported bootloader interfaces The RX pin of the unused peripheral in this bootloader has to be maintained at a known low or high level and should not be left floating during the detect
25. m density and high density value line 2 4 Once System memory boot mode is entered and the microcontroller has been configured as described above the bootloader code begins to scan the USART1 RX line pin waiting to receive the 0x7F data frame one start bit Ox7F data bits even parity bit and one stop bit The duration of this data frame is measured using the Systick timer The count value of the timer is then used to calculate the corresponding baud rate factor with respect to the current system clock Next the code initializes the serial interface accordingly Using this calculated baud rate an acknowledge byte 0x79 is returned to the host which signals that the STM32F10xxx is ready to receive user commands Bootloader version The Table 4 lists the bootloader version evolution of the STM32F10xxx devices Table 4 STM32F10xxx bootloader version evolution Bootloader version number Description V2 0 Initial bootloader version Update Go Command to initialize the main stack pointer Update Go command to return NACK when jump address is in V2 1 the Option byte area or System memory area Update Get ID command to return the device ID on two bytes Update the bootloader version to V2 1 Update Read Memory Write Memory and Go commands to deny access with a NACK response to the first 0x200 bytes of V2 2 RAM memory used by the bootloader Update Readout Unprotect command to initialize the whole
26. ped pin bootloader USART2_TX pin Output PD5 pin USART2 transmit remapped pin USART1_RX PA10 CAN2_RX PB5 OTG_FS_DM PA11 and OTG_FS_DP PA12 pins must be kept at a high or low level during the detection phase Once initialized the CAN2 configuration is Baudrate 125 kbps 11 bit identifier Note CANT is clocked during the CAN bootloader AN2 Enabl 5 nanan execution because in STM32F105xx and STM32F107xx devices CAN1 manages the CAN2 communication between CAN2 and SRAM bootloader CAN2_RX pin Input PB5 pin CAN2 receives remapped pin CAN2_TX pin Output PB6 pin CAN2 transmits remapped pin USART1_RX PA10 USART2_RX PD6 OTG_FS_DM PA11 and OTG_FS_DP PA12 pins must be kept at a high or low level during the detection phase USB OTG FS Enabled USB OTG FS configured in Forced device mode OTG_FS_VBUS pin Input or alternate PA9 Power supply voltage line function automatically ji F i OTG FS DM pin controlled by the USB PA11 USB Send Receive data line DFU OTG FS DP pin OTG FS controller PA12 USB Send Receive data line bootloader i terru pte Enabled USB_OTG_FS interrupt vector is enabled and used P for USB DFU communication USART1_RX PA10 USART2_RX PD6 and CAN2_RX PB5 pins must be kept at a high or low level during the detection phase The system clock is derived from the embedded internal high speed RC for USARTx bootloader This internal clock
27. pplet using the RS232 serial interface which controls BOOTO through the CTS line and Reset through the DCD line The user must use a full null modem cable The necessary hardware to implement for this control exists in the STM32L152 EVAL board For more details about this refer to the STM32L152 EVAL board user manual UM1009 available from the STMicroelectronics website www st com Bootloader selection The STM32 embedded bootloader supports two peripherals interfaces USART1 and USART2 Any one of these peripheral interfaces can be used to communicate with the bootloader and download the application code to the internal Flash The embedded bootloader firmware is able to auto detect the peripheral interface to be used In an infinite loop it detects any communication on the supported bootloader interfaces The RX pins of the unused peripheral in this bootloader have to be maintained at a known low or high level and should not be left floating during the detection phase as described below If USART1 is used to connect to the bootloader the USART2_RX PD6 pin has to be kept at a high or low level and must not be left floating during the detection phase If USART2 is used to connect to the bootloader the USART1_RX PATO pin has to be kept at a high or low level and must not be left floating during the detection phase Doc ID 13801 Rev 10 ky AN2606 STM32L15xx Medium density Ultralow
28. quired STM32F 10xxx hardware resources used by the bootloader in System memory boot mode Table 3 STM32F10xxx configuration in system memory boot mode Feature Peripheral State Comment Clock source HSI enabled The system clock is equal to 24 MHz using the PLL USART1_RX pin Input PA10 pin USART1 receives USART1_TX pin Output PAQ pin USART1 transmits SysTick timer Enabled Used to automatically detect the serial baud rate from the host USART1 Enabled Ke pea the USART1 configuration is 8 bits even parity RAM i 512 bytes starting from address 0x2000 0000 are used by the bootloader firmware 2 Kbytes starting from address 0x1FFF F000 contain the System memory bootloader firmware The independent watchdog IWDG prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset in case the hardware IWDG option was previously enabled by the user IWDG The system clock is derived from the embedded internal high speed RC no external quartz is required for the bootloader code After downloading the application binary if you choose to execute the Go command the peripheral registers used by the bootloader shown in the above table are not initialized to their default reset values before jumping to the user application They should be reconfigured in the user application if they are used So if the IWDG is being used in the application the IWDG prescaler value has to be
29. r may support one or more embedded serial peripherals used to download the code to the internal Flash memory The bootloader identifier ID provides information about the supported serial peripherals Doc ID 13801 Rev 10 7 32 General bootloader description AN2606 For a given STM32 device the bootloader is identified by means of the 1 Bootloader protocol version version of the serial peripheral USART CAN USB etc communication protocol used in the bootloader This version can be retrieved using the bootloader Get Version command 2 Bootloader identifier ID version of the STM32 device bootloader coded on one byte in the OxXY format where X specifies the embedded serial peripheral s used by the device bootloader X 1 only one USART is used X 2 two USARTs are used X 3 two USARTs one CAN and DFU are used Y specifies the device bootloader version Let us take the example of a bootloader ID equal to 0x10 This means that it is the first version of the device bootloader that uses only one USART The bootloader ID is programmed in the last two bytes of the device system memory and can be read by using the bootloader Read memory command or by direct access to the system memory via JTAG SWD The table below provides identification information about the bootloader embedded in STM32 devices Table 2 Embedded bootloaders Bootloader ID Bootloader Device Supported se
30. rial peripherals protocol ID Memory location version Low density USART1 NA NA USART V2 2 Medium density USART1 NA NA USART V2 2 High density USART1 NA NA USART V2 2 USART1 USART2 remapped neath Connectivity line CAN2 remapped DFU USB NA NA Devi CAN V2 0 evice DFU V2 0 Medium density USART1 V1 0 0x1FFFF7D6 USART V2 2 value line High density USART1 V1 0 0x1FFFF7D6 USART V2 2 value line XL density USART1 USART2 remapped V2 1 Ox1FFFF7D6 USART V3 0 Medium density ultralow power USART1 USART2 V2 0 0x1FFOOFFE USART V3 0 line 1 For connectivity line devices the USART bootloader returns V2 0 instead of V2 2 for the protocol version For more details please refer to the STM32F105xx and STM32F107xx revision Z errata sheet available from www st com 8 32 Doc ID 13801 Rev 10 AN2606STM32F101xx STM32F102xx STM32F103xx medium density and high density value line 2 2 1 Note 1 2 STM32F101xx STM32F102xx STM32F103xx medium density and high density value line bootloader Throughout this section STM32F10xxx will be used to refer to low density medium density high density STM32F101xx and STM32F103xx devices to low and medium density STM32F102xx devices and to medium and high density value line devices Bootloader configuration The bootloader embedded in STM32F10xxx devices supports only one interface the USART1 The following table shows the re
31. rocontrollers USB interface at any time during the bootloader firmware selection sequence the bootloader then enters the DFU bootloader loop waiting for any DFU bootloader command To use the USART or the CAN bootloader it is mandatory that no USB cable is connected to the USB peripheral during the selection phase Once the USART or CAN bootloader is selected the user can plug a USB cable without impacting the selected bootloader execution except commands which generate a system reset Once one interface is selected for the bootloader all other interfaces are disabled The figure below shows the bootloader detection mechanism More details are provided in the sections corresponding to each peripheral bootloader Doc ID 13801 Rev 10 15 32 STM32F105xx and STM32F107xx device bootloader AN2606 16 32 Figure 2 Bootloader selection for STM32F105xx and STM32F107xx devices System init clock GPIOs IWDG SysTick Configure CAN2 Configure USB USB cable Yes detected Ox7F received on USART1 Configure USART 1 Execute BL_USART_Loop for 0x7F received on USART 1 USART2 Configure USART2 Execute BL USART Loop for USART2 HSE 8 MHz Frame detected on 14 7456 MHz or CAN2 RX pin 25 MHz Reconfigure system No HSE 8 MHz Generate system clock to 48 MHz and 14 7456 MHz or reset USB clock to 48 MHz 25 MHz Execute DFU boot loader using USB G Execute interrupts enerate system BL_C
32. smits SysTick timer Enabled Used to automatically detect the serial baud rate from the host USART1 Enabled Once initialized the USART1 configuration is 8 bits even parity and 1 Stop bit USART2 Enabled Once initialized the USART2 configuration is 8 bits even parity and 1 Stop bit 2 Kbytes starting from address 0x2000 0000 are used by the RAM bootloader firmware 4 Kbytes starting from address 0x1FFO 0000 contain the System memory bootloader firmware The independent watchdog IWDG prescaler is configured to its IWDG I maximum value and is periodically refreshed to prevent watchdog reset in case the hardware IWDG option was previously enabled by the user Power Voltage range is set to Voltage Range 2 Note 1 The system clock is derived from the embedded internal high speed RC no external quartz is required for the bootloader code 2 After downloading the application binary if you choose to execute the Go command the peripheral registers used by the bootloader shown in the above table are not initialized to their default reset values before jumping to the user application They should be reconfigured in the user application if they are used So if the IWDG is being used in the application the IWDG prescaler value has to be adapted to meet the requirements of the application since the prescaler was set to its maximum value by the bootloader Doc ID 13801 Rev 10 25 32 STM32L15xx Medium density Ultralow power device bootloa
33. story Table 13 Document revision history Date 22 Oct 2007 Revision 1 Changes Initial release 22 Jan 2008 All STM32 in production rev B and rev Z include the bootloader described in this application note Modified Section 1 1 Bootloader activation and Section 1 4 Bootloader code sequence Added Section 1 3 Hardware requirements Section 1 5 Choosing the USART baud rate Section 1 6 Using the bootloader and Section 1 2 Exiting system memory boot mode Note 2 linked to Get Get Version amp Read Protection Status and Get ID commands in Table 3 Bootloader commands Note 3 added Notion of permanent Permanent Write Unprotect Readout Protect Unprotect removed from document Small text changes Bootloader version upgraded to 2 0 26 May 2008 Small text changes RAM and System memory added to Table 3 STM32F 10xxx configuration in system memory boot mode Section 1 6 Using the bootloader on page 8 removed Erase modified Note 3 modified and Note 1 added in Table 3 Bootloader commands on page 9 Byte 3 on page 11 modified Byte 2 on page 13 modified Byte 2 Bytes 3 4 and Byte 5 on page 15 modified Note 3 modified Byte 8 on page 18 modified Notes added to Section 2 5 Go command on page 18 Figure 11 Go command device side on page 20 modified Note added in Section 2 6 Write Memory command on page 21 Byte 8 on page 24 modified Figure 14 Erase Memory command hos
34. t side and Figure 15 Erase Memory commana device side modified Byte 3 on page 26 modified Table 3 Bootloader commands on page 9 Note modified and note added in Section 2 8 Write Protect command on page 27 Figure 16 Write Protect command host side Figure 17 Write Protect command device side Figure 19 Write Unprotect command device side Figure 21 Readout Protect command device side and Figure 23 Readout Unprotect command device side modified 29 Jan 2009 This application note also applies to the STM32F102xx microcontrollers Bootloader version updated to V2 2 see Table 4 Bootloader versions 4 Doc ID 13801 Rev 10 AN2606 Revision history Table 13 Document revision history continued Date 19 Nov 2009 Revision Changes IWDG added to Table 3 STM32F10xxx configuration in system memory boot mode Note 2 added BL changed bootloader in the entire document Go command description modified in Table 3 STM32F10xxx configuration in system memory boot mode Number of bytes awaited by the bootloader corrected in Section 2 4 Read Memory command Note modified below Figure 10 Go command host side Note removed in Section 2 5 Go command and note added Start RAM address specified and note added in Section 2 6 Write Memory command All options are erased when a Write Memory command is issued to the Option byte area Figure 11 Go command device side modified
35. tect command and then the Read Unprotect command This operation results in a mass erase of the internal Flash memory refer to Programming Manual PM0062 for more details Bootloader version The following table lists the evolution of the STM32L15xxx bootloader versions Table 11 STM32L15xxx bootloader version evolution Bootloader version number Description V2 0 Initial bootloader version Doc ID 13801 Rev 10 ky AN2606 Device dependent bootloader parameters 6 Device dependent bootloader parameters The bootloader protocol s command set and sequences for each serial peripheral USART CAN and USB are the same for all STM32 devices Some parameters however are device dependent For a few commands the value of some parameters may depend on the device used These parameters are listed below e PID product ID which changes with the device Valid memory addresses RAM Flash memory system memory option byte area accepted by the bootloader when the Read Memory Go and Write Memory commands are accepted e Size of the Flash memory sector used when executing the Write Protect command The table below shows the values of these parameters for each STM32 device bootloader in production Table 12 Bootloader device dependant parameters Product i Option byte System Device device ID RAM memory Flash memory Flash sector size area memory Low density 0412 0x20000200 up 0
36. tem clock is equal to 24 MHz using the PLL USART1_RX pin Input PA10 pin USART1 receives USART1_TX pin Output PAQ pin USART1 transmits USART2_RX pin Input PD6 pin USART2 receives remapped pins USART2_TX pin Output PD5 pin USART2 transmits remapped pins SysTick timer Enabled Used to automatically detect the serial baud rate from the host USART1 Enabled Once initialized the USART1 USART2 configuration is 8 bits USART2 Enabled even parity and 1 Stop bit 2 Kbytes starting from address 0x2000 0000 are used by the RAM g bootloader firmware 6 Kbytes starting from address 0x1FFF E000 contain the System memory g bootloader firmware The independent watchdog IWDG prescaler is configured to its maximum value and is periodically refreshed to prevent watchdog reset in case the hardware IWDG option was previously enabled by the user IWDG ii The system clock is derived from the embedded internal high speed RC no external quartz is required for the bootloader code After downloading the application binary if you choose to execute the Go command all peripheral registers used by the bootloader shown in Table 8 are initialized to their default reset values before jumping to the user application If the user application uses the IWDG the IWDG prescaler value has to be adapted to meet the requirements of the application since the prescaler was set to its maximum value by the bootloader Doc ID 13801 Rev 1
37. tion for STM32F10xxx XL density devices 23 Figure 4 Bootloader selection for STM32L15xxx devices ky Doc ID 13801 Rev 10 5 32 AN2606 6 32 Glossary Low density devices are STM32F101xx STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes Medium density devices are STM32F101xx STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes High density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers Low density value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes Medium density value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes High density value line devices are STM32F100xx microcontrollers where the Flash memory density ranges between 256 and 5128 Kbytes XL density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte Medium density ultralow power devices are STM32L15xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes Doc ID 13801 Rev 10 ky AN2606 General bootloader description 1 1 1 2 1 3
38. valid when the first data at the bank start address which should be the stack pointer points to a valid address into the internal SRAM memory stack top address If the first address points to any other location out of the internal SRAM the code is considered not valid A dual bank Boot mode example FLASH Dual Boot is provided within the STM32F 10x Standard Peripheral Library available on www st com Doc ID 13801 Rev 10 ky AN2606 STM32F101xx and STM32F103xx XL density device bootloader For the STM32F101xx and STM32F103xx XL density devices the Flash memory system memory or SRAM is selected as the boot space as shown in Table 7 below Table 7 Boot pin and BFB2 bit configuration Boot mode kiwa Selection pins Boot mode Aliasing BOOT1 BOOTO x 0 User Flash memory User Flash memory is selected as the boot space 1 0 1 System memory System memory is selected as the boot space 1 1 Embedded SRAM Embedded SRAM is selected as the boot space System memory is selected as the boot space x 0 Syslermmemory then dual bank mechanism is executed System memory is selected as the boot space ii 9 System memory then dual bank mechanism is executed 1 1 Embedded SRAM Fange SRAM is selected as the boot Table 7 shows that the XL density devices enter the System memory boot mode in two cases 1 If the BOOT pins are configured as follows BOOTO 1 and BOOT1 0 2 Orif a the BFB2 bit is reset
39. ve to be kept at a high or low level and must not be left floating during the detection phase If USART2 is used to connect to the bootloader the USART1_RX PATO CAN2_RX PB5 OTG_FS_DM PA11 and OTG FS DP PA12 pins have to be kept at a high or low level and must not be left floating during the detection phase If CAN2 is used to connect to the bootloader USART1_RX PATO USART2_RX PD6 OTG_FS_DM PA11 and OTG_FS_DP PA12 pins have to be kept at a high or low level and must not be left floating during the detection phase If DFU is used to connect to the bootloader the USART1_RX PATO USART2_RX PD6 and CAN2_RX PB5 pins have to be kept at a high or low level and must not be left floating during the detection phase To use the USART bootloader on USART1 or USART2 connect the serial cable to the desired interface Once the bootloader detects the data byte 0x7F on this interface the bootloader firmware executes the auto baud rate sequence and then enters a loop waiting for any USART bootloader command To use the CAN2 interface connect the CAN cable to CAN2 Once the bootloader detects a frame on the CAN2 RX pin PB5 the bootloader firmware enters a CAN loop and starts to check the external clock frequency value if the HSE is 8 MHz 14 7456 MHz or 25 MHz CAN bootloader firmware enters an infinite loop and waits until it receives a message otherwise a system reset is generated If a USB cable is plugged into the mic
40. x08000000 up 4 Kbytes 4 pages 0x1FFFF800 0x1FFFF000 y to 0x20002800 to 0x08008000 of 1 Kbyte each O0x1FFFF80F 0x1FFFF800 Medium 0x410 0x20000200 up 0x08000000 up 4 Kbytes 4 pages 0x1FFFF800 Ox1FFFFOOO density to 0x20005000 to 0x08020000 of 1 Kbyte each O0x1FFFF80F 0x1FFFF800 High density Oxdta 0x20000200 up 0x08000000 up 4 Kbytes 2 pages 0x1FFFF800 0x1FFFF000 9 y to 0x20010000 to 0x08080000 of 2 Kbytes each Ox1FFFF80F 0x1FFFF800 Connectivity 0x418 0x20001000 up 0x08000000 up 4 Kbytes 2 pages 0x1FFFF800 0x1FFFB000 line to 0x20010000 to 0x08040000 of 2 Kbytes each Ox1FFFF80F 0x1FFFF800 Medium densit 0x420 0x20000200 up 0x08000000 up 4 Kbytes 4 pages 0x1FFFF800 0x1FFFF000 value EN to 0x20002000 to 0x08020000 of 1 Kbyte each Ox1FFFF80F 0x1FFFF800 High density 0x428 0x20000200 up 0x08000000 up 4 Kbytes 2 pages 0x1FFFF800 0x1FFFF000 value line to 0x20008000 to Ox08080000 of 2 Kbytes each Ox1FFFF80F 0x1FFFF800 XL densit 0x430 0x20000800 up 0x08000000 up 4 Kbytes 2 pages 0x1FFFF800 0x1FFFE000 y to 0x20018000 to 0x08100000 of 2 Kbytes each Ox1FFFF80F 0x1FFFF800 Medium density 0x416 0x20000800 up 0x08000000 up kia dite oe Ox1FF80000 0x1FF00000 ultralow to 0x20004000 to 0x08020000 pag Ox1FF8000F 0x1FF01000 Bytes each power line ky Doc ID 13801 Rev 10 29 32 Revision history AN2606 7 30 32 Revision hi
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