FM680 User Manual - 4DSP LLC
Contents
1. INTER FPGA 1013 _ VIO INTER FPGA 1014 BLASTO VIO INTER FPGA 1015 BLASTO VIO INTER FPGA CLK A to Bn BLASTO VIO INTER FPGA CLK A to Bp BLASTO VIO INTER FPGA CLK B to An BLASTO VIO _ INTER FPGA B to Ap BLASTO VIO 3 3 PCl express architecture The Virtex 5 device is connected to the XMC connector P15 and offers a PCI Express Endpoint block integrated in the FPGA The endpoint will support a 4 lanes generation 1 PCI express bus A PCI express switch is used to optionally route the 4 lanes from the P15 connector to the Virtex 6 device instead of the Virtex 5 device The remaining 4 transceiver lanes on the P15 connector are routed to the Virtex 6 device as well This makes it possible to have an 8 lanes generation 1 PCl express bus connecting to the Virtex 6 device If this option is selected the 4 lanes connection towards the Virtex 5 device is not available The standard reference design has the PCI Express connection towards the Virtex 5 FPGA 4DSP can provide a reference design for the 8 lanes connection to the Virtex 6 FPGA Please consult with your sales contact for more details The following performances have been recorded with the FM680 transferring data on the bus using the standard 4DSP PCIe interface design gt PCle 1 lane 150Mbytes s2. 22 a 2 2 Firmware and 044440000 nnne nnne 3 1 1 5 device family and 3 1 2 Virtex 6 device family and 32 Inter FPGA InterfaeB eir trib err Rr aa ER pe tik a 3 3 PCl express 4 4444444 4 000 3 4 XMC P15 connector fe 3 5 nE EE ERE 3 6 Pn4 user VO connector 3 7 I m ma BLAST SIOS 3 9 External 3 9 1 Front Panel daughter card 3 9 2 Power connection to the front panel I O daughter 3 9 3 Front Panel optical transceivers 3 9 4 Optical transceiver MGT Reference 3 10 iato ana 3 11 FPGA configuration uso ee u u sita 3 11 1 Flash storage ETERNI Bal ee CPD Ce o SOURCE IE com 3 12 rd NERS 4 Power requirements eee 41 External power connector for stand alone MENSES Um SE 5 1 Temperature RE
3. ius 3 7 Serial FLASH A 128 Mbits serial flash device S25FL128P is available to the Virtex 6 device This flash allows the storage of vital data like processor boot code and settings into a non volatile memory The flash is operated using a standard SPI interface that can run up to 104 MHz allowing for a page programming speed up to 208 KB s Reading data from the flash can be done at speeds up to 13 MB s The SPI programming pins is connected to a bank that supports 1V8 whereas the serial flash is operating at 3V3 This will not cause problems for the signals from the Virtex 6 to the flash device but the signal from the flash device to the Virtex 6 are passed through a level translator SN74AVC4T245 3 8 BLAST sites Thanks to the availability of 5 BLAST sites a wide variety of memory and processing modules can be connected to the Virtex 6 device For each BLAST site it is possible to choose from the list of available BLAST modules For more information about the available BLASTs on the FM680 please consult the following page BLAST modules http www 4dsp com BLAST htm Table 8 BLAST Configuration Options BLAST 3 SITE 1 2 3 4 5 YES YES YES YES YES Single Extended YES YES YES YES YES BLAST Double BLAST Double Extended YES YES YES YES BLAST 1 Single and double extended BLAST placed in BLAST sites 4 and 5 will protrude 3mm from edge of the board 2 BLAST SITES 1 and 2 4 and 5 are p
4. 113 3 PETOx7 Ox P MGTREFCLK 112 0 XMC Pn6 PER1x 0 PETix0 PETI 0 11420 1 1 1 1 PETIx1 lt PETU MGT_114_1 PERIx 2 PERIx2 PETIx2 lt PETIx2 PER0x3 PEROx 3 gt PETox3 lt 3 114 3 RefCLK p MGTREFCLK 114 0 RefCLK H SEIS Butr RefCLK p VGTREFCLK 115 1 1 4 PEROX 4 gt PETIx4 lt PET1x4 MGT_115_0 1 5 1 5 115 1 PETIx5 PETIX S PERIx 6 PERIx6 115 2 PETIx6 PETIx 6 1 7 PERIx7 gt 115 3 PETIx7 7 Figure 3 PCl express subsystem diagram NOTE There is a swap between the PETOTXO and PETOTX1 on the FM680 3 4 XMC P15 connector The Table 3 shows the pin out as defined by VITA 42 3 Only the highlighted pins are connected on the FM680 Table 4 indicates the signals usage and on board connections V1 6 August 2012 FM680 User Manual www 4dsp com 10 Jor 680 User Manual V1 6 Table 3 XMC P15 pin out as per VITA 42 3 PETOpO PETOnO PETOp1 PETOn1 VPWR GND GND GND GND MRSTI PETOp2 PETOn2 PETOp3 PETOn3 VPWR GND GND GND GND MRSTO PETOp4 PETOn4 5 5 VPWR GND GND GND GND 12V PETOp6 PETOn6 PETOp7 PETOn7 VPWR GND GND GND GND 12V RFU RFU RFU RFU RFU VPWR GND GND TDO GND GND GA0 PEROpO PEROnO
5. uen Jur Der rese EIS p Des es 16 a Table 11 Front Panel IO daughter assignment Bank Connected to a global clock on the FPGA LVDS output not supported Connected to a regional clock pin on the FPGA LVDS output not supported 9 Vbatt is connected to both Virtex devices Vbatt pin FM680 User Manual August 2012 www 4dsp com 680 vs Table 12 Front Panel IO daughter card assignment Bank C FM680 User Manual August 2012 www 4dsp com 18 680 ius 3 9 2 Power connection to the front panel daughter card The Front Panel I O daughter card on side 1 of the PCB is powered via a 7 pin connector of type BKS Samtec Each pin can carry up to 1 5A The power connectors pin assignment is as follows Table 13 Daughter card power connector pin assignment on PMC side 1 3 9 3 Front Panel optical transceivers Special build option and not in combination with the front panel daughter card Four 2 5 GB s optical transceivers LTP ST11M are available on the FM680 in the front panel area They are connected to the MGT l Os of the Virtex 6 Infiniband protocols as well as Gigabit Ethernet and Fibre channel can be implemented over the transceivers Lower rate optical transceivers 2 125 GB s
6. vs 3 9 4 Optical transceiver Reference Clock A low jitter oscillator connects to the 874003BG 05LF Depending on the resistor configuration this device can output a 312 5 156 25 or 125 MHz clock The default configuration outputs a 156 25 MHz reference clock The Figure 6 and Table 15 show the selection resistor locations and type Table 15 Optical transceiver reference clock frequency selection resistors Resistor Type MGT REFCLK R510 Pull up default FSELO R518 Pull down R294 Pull up default FSEL1 R494 Pull down R292 Pull up default FSEL2 R293 Pull down a a nz o acu S BERR agcsuuss D FH E H Figure 6 Optical transceiver reference clock selection resistors locations 3 10 FPGA LED Four LEDs are connected to the Virtex 5 device In the default FPGA firmware the LEDs are driven by the Virtex 5 device The following table shows the meaning of the LEDs in the standard reference design LED 0 PClexpresslink down PClexpress link up n a red LED 1 No PCI express traffic PCI express traffic PCI express traffic red LED 2 No PCI express traffic PCI express traffic PCI express traffic red LED 3 FM680 PCB revision 2 FM680 revision 1 n a red only when FPGA A firmware revision is 2 3 or higher Table 16 LED board status
7. 3 11 2 CPLD device As shown on Figure 7 Cool Runner ll CPLD is present on board to interface between the flash device and the FPGA devices The CPLD is used to program and read the flash The data stored in the flash is transferred from the host motherboard via the PCl express bus to the Virtex 5 device and then to the CPLD that writes the required bit stream to the storage device A 31 25 MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA devices At power up if the CPLD detects that an FPGA configuration bit stream is stored in the flash for both FPGA devices it will start programming the devices in SelecMap mode Do NOT reprogram the CPLD without 4DSP s approval The CPLD configuration is achieved by loading with a Xilinx download cable a bit stream from a host computer via the JTAG connector The FPGA devices configuration can also be achieved via the JTAG chain 680 User Manual August 2012 www 4dsp com 23 680 ius 3 11 21 DIP Switch A switch J1 is located next to the JTAG programming connector J6 see Figure 9 The switch positions are defined as follows ELT e FORDE i ALLE 55558 E un e o Figure 9 switch J1 location Sw1 OFF Default setting The Virtex 5 device con
8. Also there are 16 single ended pins available that can be used as general FM680 User Manual August 2012 www 4dsp com 6 680 User Manual vs purpose IO or as a connection to the Pn4 bus Please be aware that 8 of those extra bits are available only on the SX475T and the LX550T FPGA types Only on LX550T and SX475T Figure 2 Inter FPGA Interface By default 4DSP delivers a reference design that uses the interfpga bus to allow high speed data transfer and command distribution between the PClexpress interface in the FPGA A and the FPGA B The standard reference design does not implement the PN4 connection since those connections will depend on the user specific application The user is free to modify the reference design and add specific features in FPGA A and FPGA B The connections between the FPGA A and FPGA B are described in the following table Table 2 interFPGA connections INTER_FPGA0 INTER_FPGA1 INTER_FPGA2 INTER_FPGA3 INTER_FPGA4 INTER_FPGA5 INTER_FPGA6 INTER_FPGA7 INTER_FPGA8 INTER_FPGA9 INTER_FPGA10 INTER_FPGA11 INTER_FPGA12 INTER_FPGA13 INTER_FPGA14 INTER_FPGA15 INTER_FPGA16 INTER_FPGA17 INTER_FPGA18 INTER_FPGA19 FM680 User Manual August 2012 www 4dsp com 7 FM680 User Manual INTER_FPGA20 INTER_FPGA21 INTER_FPGA22
9. and 1 0625 GB s are available in the same form factor The Figure 4 shows the block diagram of the optical transceivers on the FM680 and Figure 5 shows the location of the optical transceivers on the PCB Table 14 shows the pin assignments for each serial lane and the optical transceiver it connects to Clk buffer 125 MHz 874003BG 05LF Virtex 6 1 116 3 MGT 116 2 MGT 116 1 X Y Y 116 0 0 MGTREFCLK 116 0 q Figure 4 Optical transceiver connections 680 User Manual August 2012 www 4dsp com 19 680 vs 9999999999999999999999 9999999999999999999999 ttt t t t t 4 ttt tt t t t t t n ttt tt t t t t ttt tt t t n t t t t tn Figure 5 Optical transceiver locations Table 14 Optical transceiver MGT connections FPGA Pin Net Name MGT Block Optical transceiver K4 MGT_FP_RXp3 K3 MGT_FP_TXp3 116_3 OT3 J6 MGT FP RXn3 J5 MGT FP RXp3 L2 MGT FP RXp2 L1 MGT FP TXp2 116 2 OT2 L6 MGT FP RXn2 L5 MGT FP RXp2 M4 FP RXp1 M3 MGT_FP_TXp1 116_1 OT1 N6 MGT_FP_RXn1 N5 MGT_FP_RXp1 N2 MGT FP RXpO N1 MGT FP TXpO 116 0 OTO P8 FP RXnO P7 MGT FP RXpO 680 User Manual August 2012 www 4dsp com 20 680
10. devices work load By using high efficiency power converters all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm After power up the FM680 typically consumes 6 Watts of power For precise power measurements it is recommended to use the Xilinx power estimation tools for both the Virtex 5 and Virtex 6 FPGA devices The maximum current rating given in the table below is the maximum current that can be drawn from each voltage rail in the case resources are used to their maximum level Special precautions need to be taken to support the VPOWER input since the XMC standard dictates that this power supply can either be 12V or 5V To overcome this a voltage detection circuit detects whether VPOWER is 12V or 5V and enables a switching regulator or FM680 User Manual August 2012 www 4dsp com 27 FM680 User Manual Jor V1 6 a Field Effect Transistor FET If VPOWER is 12V the switching regulator converts down to 5V otherwise the FET allows 5V to pass through Device Interface Voltage Maximum current rating DCI and memory reference 0 9V 6A voltage Virtex 6 device core 1 0V 10A Virtex 5 device core 1 0V 2A BLAST core and 6 I O 1 8V 6A banks Virtex 5 device bank 0 9 1 0 1 8 2 5 3 A connected to the front panel 3V daughter card front Panel I O daughter card 5V 1 Front Panel IO daughter card
11. point o o 504062 xy 10 ILLAT 79 sured SAAT ZE 10 User O PCI Express Rocket IO VITA 42 3 42 2 42 3 1 Only available on XC6VLX550T and SX475T FPGA devices 2 4 lanes go either to the V6 or to the V5 Figure 1 FM680 block diagram Build on the success of its predecessor boards of the FM48x series the FM680 also uses the BLAST technology A total of 5 BLAST sites connect directly to the Virtex 6 FPGA FM680 User Manual August 2012 www 4dsp com 5 680 ius BLAST Board Level Advanced Scalable Technology is small PCB module that allows customization of the FM680 in memory extensions processing units and communication interfaces For more information about the available BLASTs on the FM680 please consult the following page BLAST modules http www 4dsp com BLAST htm 2 Installation 2 1 Requirements and handling instructions e FM680 must be installed on a motherboard compliant to the VITA 42 3 standard e Do not flex the board Observe ESD precautions when handling the board to prevent electrostatic discharges Do not install the FM680 while the motherboard is powered up 2 2 Firmware and software Drivers API libraries and a program example working in combination with a pre programmed firmware for both FPGAs are provided The FM680 is delivered with an interface to the Xilinx endp
12. 3V3 Front Panel IO daughter card 12V 1 Front Panel IO daughter card 12V 1 power supply 1 0V 1 2V 2 5V 2 0A 2 5A 0 01A respectively Table 22 Power supply Optionally the FM680 can be used as a standalone module and is powered via the external power connector August 2012 FM680 User Manual www 4dsp com 28 FM680 User Manual LET V1 6 to 1vO 12v to 5vO EN5396QI LTC3605 V6 lout 6A V5 1A 1v0 gt 5v to 1v0 EN5396QI FET 5v0 XMC V6 VPWR m V5 1A 5V CONTROL 5v to 1v8 EN5395QI 1v8 2 5 BLAST 5 1v8 to 1 2 TPS74401 2 P 5V to 0v9 TPS54972 0vg p ddr term 7A 5 5 3v3 to 2 5 TPS74401 MGT Q 1 2 gt VADJ 3A 3 3 XMC 3v3 8A BLAST voltage 5 1v5 1v8 5 A 3v3 to 1v2 539501 2 XMC 12v 1v8 to 1v5 TPS74401 Figure 12 Power supply ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature The ADT7411 data are constantly passed to the Virtex 6 device Measurements can be accessed from the host computer via the PCI bus A software utility delivered with the board allows the monitoring of the voltage on the 2 5V 1 8V 1 2V 1 0V and 0 9 r
13. 680 User Manual August 2012 www 4dsp com 21 680 vs The LEDs are located on side 2 of the PCB in the front panel area Their locations are depicted in Figure 7 CPLD LEDO CPLD LED1 CPLD LED2 CPLD LED3 FPGA LED1 FPGA LEDO FPGA LED3 FPGA LED2 Figure 7 FPGA and CPLD LED locations To turn on a LED drive the signal low To turn a LED off make the signal high C13 FPGA LEDO 11 16 FPGA LED1 11 D17 FPGA LED2 11 11 FPGA_LED3 11 Table 17 FPGA LED connections The standard to be assigned depends on BLAST configuration FM680 User Manual August 2012 www 4dsp com 22 680 ius 3 11 FPGA configuration 3 11 1 Flash storage The FPGA firmware is stored on board in a flash device The 512Mbit device is partly used to store the configuration for both FPGAs In the default CPLD firmware configuration the Virtex 5 device and the Virtex 6 device are directly configured from flash if a valid bit stream is stored in the flash for each FPGA The flash is pre programmed in factory with the default firmware example for both FPGAs JTAG Header Virtex 6 512Mbit Flash JTAG JTAG S29GL512M i 8 bit parallel configuration CoolRunner ll CPLD XC2C256 CP132 Virtex 5 DIP switch Figure 8 Configuration circuit
14. FM680 User Manual L Sr vs FM680 User Manual for Virtex 6 XMC card 4DSP LLC 955 S Virginia Street Suite 214 Reno NV 89502 USA 4DSP BV Ondernemingsweg 66 2404 HN Alphen Rijn Netherlands Email support 4dsp com This document is the property of 4DSP and may not be copied nor communicated to a third party without the written permission of 4DSP 4DSP 2010 680 ius Revision History esos December First release 1 0 15 2009 January 20 Minor modifications 1 1 2010 April 23 Corrected typos 1 2 2010 August 16 Corrected typos 1 3 2010 August 17 Added image 10 for the JTAG connector location July 11 Updated block diagram 1 5 2012 Added detailed description for the connector usage Removed reference to emcore connector and the QTE connector Updated PClexpress connection diagram Added location images for LEDs and switch Added table to describe interFPGA pinout August 28 Updated chapter 9 3 to add more detail with regards to 2012 the frontpanel optical transceivers mE mE mE E ue FM680 User Manual August 2012 www 4dsp com 680 User Manual SEH Table of Contents Emm T 1 2 Related Documents 1 8 General 2 0 4 00 ME Sc ci us u u 2 1 Requirements and handling
15. GA design with the Xilinx Chipscope A press fit connector is delivered with the board that can be plugged into the connector holes The JTAG connector can be placed on both sides of the PCB The connector location seen from the bottom of the PCB is shown in Figure 10 August 2012 FM680 User Manual www 4dsp com 25 680 ius VCC TMS GND TDI 9 TDO F mmm 2 E b e a e Emm gh M gu EE bs 2 E INR me Loa o e 10 E as omn s an BOE da B P mz 2 Bii A H oe ER n si i p 1 BB Rz mmm Om z e E 33 HH i t 15 wan ma a BR m om ENT TIT BU 0 69 mue one I Figure 10 JTAG connector 46 location The JTAG connector pinout is as follows Table 20 JTAG pin assignment 3 12 Clock tree The FM680 clock architecture offers an efficient distribution of low jitter clocks Both FPGA devices receive a low jitter 125MHz clock A low jitter programmable clock able to generate frequencies from 62 5MHz to 255 5MHz in steps of 0 5MHz is also available This clock management ap
16. INTER_FPGA23 INTER_FPGA24 INTER_FPGA25 INTER_FPGA26 INTER_FPGA27 INTER_FPGA28 INTER_FPGA29 INTER_FPGA30 INTER_FPGA31 INTER_FPGA32 INTER_FPGA33 INTER_FPGA34 INTER_FPGA35 INTER_FPGA36 INTER_FPGA37 INTER_FPGA38 INTER_FPGA39 INTER_FPGA40 INTER_FPGA41 INTER_FPGA42 INTER_FPGA43 INTER_FPGA44 INTER_FPGA45 INTER_FPGA46 INTER_FPGA47 INTER_FPGA48 INTER_FPGA49 INTER_FPGA50 INTER_FPGA51 INTER_FPGA52 INTER_FPGA53 INTER_FPGA_IO0 INTER_FPGA_IO1 INTER_FPGA_IO2 INTER_FPGA_IO3 INTER_FPGA_IO4 INTER_FPGA_IO5 INTER_FPGA_IO6 INTER_FPGA_IO7 D14 LIEF E15 D15 E14 F14 A11 A12 C12 D18 B13 A13 G14 G15 B14 A14 G13 F13 15 15 16 16 F16 G16 A18 A17 E17 E16 C17 F17 D12 E12 C18 B18 F18 H13 H15 H16 L14 K15 L13 J14 J15 V1 6 August 2012 FM680 User Manual www 4dsp com 680 ius INTER_FPGA_IO8 _ VIO INTER_FPGA_IO9 _ BLASTO INTER FPGA 1010 _ VIO __ INTER FPGA 1011 INTER FPGA 1012 _
17. MBIST 1 PEROn1 VPWR GND GND GA1 GND GND MPRESENT 2 2 3 3VAUX PEROp3 PEROn3 VPWR GND GND GA2 GND GND MSDA PEROp4 PEROn4 RFU 5 PEROn5 VPWR GND GND GND GND MSCL PEROp6 PEROn6 PEROp7 PEROn7 RFU GND GND GND GND RFU REFCLK 0 REFCLK O WAKE ROOTO RFU Table 4 XMC P15 connections V5 08 PClexpress reset input 4 2 MRSTI n a Connected to GND n a 12 MPRESENT Not connected n a C11 MBIST n a Conencted to TDO C8 TDI n a Conencted to TDI n a C10 TDO n a VPOWER is used to n a generate local 5V VPWR n a General ground for n a FM680 GND n a Connects to 12V of n a F8 daughter card 12V n a Connects to 12V of n a F6 daughter card and is used for on board voltage control circuits 12V n a Used directly n a l dd Refer to Connects to Virtex 5 and n a Figure 3 Virtex 6 PETOp n 7 0 to Virtex 5 and n a PEROp n 7 0 FM680 User Manual August 2012 www 4dsp com 11 680 ius 3 5 XMC P16 connector The Table 5 shows the pin out as defined by VITA 42 3 Only the highlighted pins are connected on the FM680 Table 6 indicates the signals usage and on board connections Table 5 XMC P15 pin out as per VITA 42 3 PET1pO 1 0 1 1 1 1 GND GND GND GND PET1p2 PET1n2 PET1p3 PET1n3 GND GND GND GND PET1p4 PET1n4 PET1p5 PET1n5 GND GND GND GND
18. NTRER bo Convection cooling 53 Peli reife aues eT o Oo FM680 User Manual August 2012 www 4dsp com Technical s pport U rari V1 6 680 ius Acronyms and related documents 1 1 Acronyms ADC DAC DCI DSP EPROM FBGA FPDP FPGA JTAG LED LVTTL LVDS LSB LVDS MGT MSB PCB PCI PLL PMC SDRAM Analog to Digital Converter Digital to Analog Converter Digitally Controlled Impedance Double Data Rate Digital Signal Processing Erasable Programmable Read Only Memory Fineline Ball Grid Array Front Panel Data Port Field Programmable Gate Array Joint Test Action Group Light Emitting Diode Low Voltage Transistor Logic level Low Differential Data Signaling Least Significant Bit s Low Voltage Differential Signaling Multi Gigabit Transceiver Most Significant Bit s Printed Circuit Board Peripheral Component Interconnect PCI Express Phase Locked Loop PCI Mezzanine Card Quadruple Data rate Synchronous Dynamic Random Access memory SRAM Synchronous Random Access memory Table 1 Glossary 1 2 Related Documents IEEE Std 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC ANSI VITA 20 2001 Conduction Cooled PMC AN
19. PET1p6 PET1n6 PET1p7 PET1n7 GND GND GND GND RFU RFU RFU RFU GND GND GND GND PER1pO PER1nO PER1p1 1 1 GND GND GND GND PER1p2 PER1n2 PER1p3 PER1n3 GND GND GND GND PER1p4 PER1n4 1 5 1 5 GND GND GND GND PER1p6 PER1n6 PER1p7 PER1n7 GND GND GND GND REFCLK 1 REFCLK 1 RFU ROOT1 Table 6 XMC P16 connections Refer to Connects to Virtex 6 Figure 3 4 1 7 0 Refer to Connects to Virtex 6 n a Figure 3 1 7 0 680 User Manual August 2012 www 4dsp com 12 FM680 User Manual Jor V1 6 3 6 Pn4 user connector The Pn4 connector is connected to the Virtex 5 device Pn4 100 R1 4 1026 9 3 R14 N11 m j CEN 011 14 010 P13 V13 4 1046 12 Pn4 1048 Pn4 1050 55 61 16 18 15 N12 Pn4 1062 Ee l ui Pn4 1017 Pn4 1019 20 Pn4 1023 24 4 025 26 5 Pn4 1037 7 Pra jer Pn4 IO60 Pn4 1061 62 4 1 Pn4 103 i 10 x 12 14 16 18 4 1021 22 4 1027 28 4 1029 4 1031 4 1033 4 1035 36 30 32 34 38 4 1039 40 2 44 46 48 50 52 54 Pn4 1055 56 Pn4 1057 58 4 1063 64 Table 7 Pn4 assignment FM680 User Manual August 2012 www 4dsp com 13 680
20. SI VITA 42 0 2005 XMC Switched Mezzanine Card Auxiliary Standard ANSI VITA 42 3 2006 XMC PCI Express Protocol Layer Standard IEEE Std 1386 2001 IEEE Standard for a Common Mezzanine Card Family Xilinx Virtex 5 Documentation Xilinx Virtex 6 Documentation August 2012 FM680 User Manual www 4dsp com 4 680 User Manual vs 1 3 General description The FM680 is a high performance XMC optionally conduction cooled dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements It offers various interfaces fast on board memory resources one Virtex 5 FPGA with embedded PCl express endpoint or Serial Rapid IO and one Virtex 6 device It can be utilized for example to accelerate frequency domain algorithms with off the shelf Intellectual Property cores for applications that require the highest level of performances The 680 is mechanically and electrically compliant to the standard and specifications listed in section 1 2 of this document A top level diagram is depicted in Figure 1 Front Panel 180 pin QTH connector on side 1 and on side 2 facing inward or 4 optical tranceivers 2 5 Gb s 128 Mb Serial flash clocks Optional battery for IP encryption key Sng 2001 rud uoo pepue 8 pepue 89 Configuration circuit Jirtex 5 8 x4 PCI express 13 2 End
21. ails It also displays both FPGAs junction temperature August 2012 FM680 User Manual www 4dsp com 29 680 ius 4 1 External power connector for stand alone mode An external power connector J2 is available on side 2 of the PMC next to the connectors It is used to power the board when it is in stand alone mode This is a right angled connector and it is mounted on board only if the card is ordered as a stand alone version FM680 SA The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board Do not connect an external power source to J2 if the board is powered via the XMC connectors Doing so will result in damaging the board The external power connector is of type Molex 43045 1021 Each circuit can carry a maximum current of 5A The connector pin assignment is as follows Table 23 External power connector pin assignment WARNING UNREGULATED UNPROTECTED EXTERNAL POWER SUPPLY CONNECTION This board is designed with an UNSUPPORTED feature for an external power connector labeled as J2 Mounting a connector on the PCB breaches the PMC electrical and mechanical specifications of the PMC standard This is a FACTORY ONLY feature that is used in the manufacturing process when powering the board is req
22. aired when using double BLAST 3 Only available on XC6VLX550T and SX475T FPGA devices YES YES YES YES 680 User Manual August 2012 www 4dsp com 14 680 ius Table 9 BLAST Memory Processing Options BLAST 1 SITE 1 2 3 4 5 DDR3 YES YES YES YES NO DDR2 YES YES YES YES NO QDR YES YES YES YES YES ADV212 JPEG2000 YES YES YES YES YES 32GB NAND YES YES YES YES YES FLASH 1 Only available on XC6VLX550T and SX475T FPGA devices Due to its small form factor and ease of design the BLAST modules enable a rapid solution for custom memory or processing requirements 3 9 External IO interfaces The Virtex 6 device interfaces to the front panel daughter card on the FM680 via a high speed connector 174 I Os are available from the FPGA to from the daughter card that can be mounted in the IO area defined by the XMC standard As an alternative solution it is also possible to have 4 optical transceivers in the IO area 3 9 1 Front Panel daughter card Only available with front panel daughter card purchase and not in combination with the optical transceivers The Virtex 6 device interfaces to a 180 pin connector placed in the Front panel I O area on both side 1 of the PCB It serves as a base for a daughter card and offers diversity to the FM680 PMC The FPGA banks are powered either by 1 8V or 2 5V via a large 0 ohms res
23. figuration is loaded from the flash at power up ON Virtex 5 device safety configuration loaded from the flash at power up To be used only if the Virtex 5 device cannot be configured or does not perform properly with the switch in the OFF position Sw2 Reserved should be OFF Sw3 Reserved should be ON Sw4 Reserved should be OFF Table 18 Switch description 3 11 2 2 LED and board status Four LEDs connect to the CPLD and give information about the board status FM680 User Manual August 2012 www 4dsp com 24 Jor FM680 User Manual V1 6 LED 0 FPGA A configured FPGA A not configured FPGA A or B bit stream or red user ROM register is currently being written to the flash LED 1 FPGA B configured FPGA B not configured FPGA A or B bit stream or red user ROM register is currently being written to the flash LED 2 FLASH idle FLASH busy Safety configuration loaded red into FPGA A or attempted to load LED 3 No CRC error detected CRC error Presumably a n a red wrong or corrupted FPGA bit stream has been written to the flash Once on this LED remains on Table 19 LED board status The LEDs are located on side 2 of the PCB in the front panel area Their locations are depicted in Figure 7 3 11 3 JTAG A connector is available on the FM680 for configuration purposes The JTAG can also be used to debug the FP
24. g prior to any modifications Terms and Conditions are available from http www 4dsp com TCs txt Technical support requests should be sent to support 4dsp com Any electrical connections made to the board or other components shall be made only with approved connectors as specifically identified in the products official documentation Any modification to hardware including but not limited to removing of components soldering or other material changes to in part or in whole to the PCM and or its components will immediately invalidate and make void any warranty or extended support if any Further and changes or modifications to software and or firmware supplied with the Product unless provided for in the Products official documentation shall immediately invalidate and make void any warranty or extended support if any 9 Warranty Basic Warranty included 1 Year from Date of Shipment 90 Days from Date of Shipment Extended Warranty optional 2 Years from Date of Shipment 1 Year from Date of Shipment 680 User Manual August 2012 www 4dsp com 32
25. istor 2 5V is the default if not specified otherwise at the time of order Using the Xilinx DCI termination options to match the signals impedance allows many electrical standards to be supported by this interface The VRN and VRP pins on the banks connected to the daughter card connector are respectively pulled up and pulled down with 500 resistors in order to ensure optimal performances when using the Xilinx DCI options The VREF pins are connected to 0 9V for DDR2 DCI terminations Please contact 4DSP Inc for more information about available daughter card types The 180 pin Samtec connector pin assignment is as follows All signals shown as LVDS pairs in the table can also be used for any standard that does not breach the electrical rules of the Xilinx I O pad The FP Xi signals in the table below are routed as single ended 680 User Manual August 2012 www 4dsp com 15 FM680 User Manual s Jor ee se em e Fecal cece Table 10 Front Panel IO daughter card pin assignment Bank A Connected to a global clock pin on the FPGA LVDS output not supported Connected to a regional clock pin on the FPGA LVDS output not supported FM680 User Manual August 2012 www 4dsp com FM680 User Manual i z m rence puma hos me Ls B Jor Eme
26. oint core in the Virtex 5 device as well as an example VHDL design in the Virtex 6 device so users can start performing high bandwidth data transfers over the PCI bus right out of the box For more information about software installation and FPGA firmware please refer the Get Started Guide 3 Design 3 4 FPGA devices The Virtex 5 and Virtex 6 FPGA devices interface to the various resources on the FM680 as shown on Figure 1 They also interconnect to each other via 58 general purpose pins including 4 clock pins 2 pairs in each direction 1000 terminated A 16 bits single ended bus is also available between the two FPGA devices for communication with the Pn4 bus or general purpose communication 3 1 1 Virtex 5 device family and package The Virtex 5 device is from the Virtex 5 LX family It can be either an XC5VLX2OT or XC5VLX30T in a Fineline Ball Grid array with 323 balls FF323 3 1 2 Virtex 6 device family and package The Virtex 6 device is dedicated to Digital Signal Processing video processing or communication applications and can be chosen from the SXT or LXT family devices Its package is based on Fineline Ball Grid array with 1759 balls In terms of logic and dedicated DSP resources the FPGA B can be chosen from the following types LX240T LX550T SX315T and the SX475T FF1759 3 2 Inter FPGA interface The Virtex 5 device is connected to the Virtex 6 device using a 54 pin bus plus 2 differential clock signals
27. proach ensures maximum flexibility to efficiently implement multi clock domains algorithms and use the memory devices at different frequencies Both clock buffer devices CDCV1804 and the frequency synthesizer CDCE925 are controlled by the Virtex 5 device 680 User Manual August 2012 www 4dsp com 26 Sr vs FM680 User Manual 125 MHz gt s v Virtex 5 _ 6 CDCM1804 CDCE925 gt AE30 AF30 16 MHz p W30 V30 Virtex 6 la Y30 FPGA B Y5 gt CPLD Figure 11 Clock tree CDCE925 CDCV1804 FPGA Pin Net Name DIR Device Pin Number Pin Name V5 T6 CLK SYNTH A 925 13 1 Ve 0 CLK SYNTH B 925 7 Y4 V6_AA31 CLK SYNTH B 925 8 5 V5 P7 CLK125 AN CDCV1804 10 Y2 V5_P8 CLK125_AP CDCV1804 9 Y2 Ve V30 CLK125 BON CDCV1804 16 Y0 V6_W30 CLK125 CDCV1804 15 YO V6_AF30 CLK125 B1N CDCV1804 22 Y1 V6 AE30 CLK125 B1P CDCV1804 21 Y1 Table 21 Miscellaneous clock connections 4 Power requirements The Power is supplied to the FM680 via the XMC 5 connector Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board The FM680 power consumption depends mainly on the FPGA
28. sustained gt PCle 4 lanes 600Mbytes s sustained gt PCle 8 lanes 800Mbytes s sustained Higher performance transfers are possible but will require modifications to the PCle interface design Please consult with your sales contact for more details Furthermore the VITA 42 3 standard defines an optional P16 connector which can carry an additional 8 lanes of high speed signaling All these lanes are routed to the Virtex 6 device directly An overview of the PCl express subsystem is shown in Figure 3 FM680 User Manual August 2012 www 4dsp com 9 FM680 User Manual Jor Virtex 5 PCle Switch FPGA A PEROx 0 FPGA A PETOx 0 112 0 PEROx 1 1 112 1 PEROx 2 XMC Pn5 a 2 1 0 PER0x 3 PERKO BMGT 114 1 E gt lt PEDX3 OA q 112 1 gt select Pci select PETOx1 Virtex 6 PEROx 2 FPGA B PETOx2 PER0x 0 FPGA B PERDE S PETOx 0 112 0 PEROx 1 BETORT MGT 112 1 RefCLK PEROx 2 CLK buffer PETOx 2 112 2 PEROx 3 PETUS MGT_112_3 TT 2 PEROx 4 gt PETOx4 4 PETOx 4 PEROx 5 PEROx 5 gt 113 1 PETOx 5 PET0x 5 GT_113 FEROX 6 CE gt 113 2 PETOx6 ox 7 7 gt
29. uired in an UN MOUNTED PCI bus mode thus in stand alone mode DO NOT connect an external power source to J2 doing so may result in damaging the board and will automatically VOID WARRANTY Consult factory for further information FM680 User Manual August 2012 www 4dsp com 90 680 User Manual 5 Environment 5 1 Temperature Operating temperature e 0 10 60 Commercial e 40C to 85 Industrial Storage temperature e 40C to 120C 5 2 Convection cooling 600LFM minimum 5 3 Conduction cooling V1 6 The FM680 can optionally be delivered as conduction cooled PMC The FM680 is compliant to ANSI VITA 20 2001 standard for conduction cooled PMC 6 Safety This module presents no hazard to the user 7 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system FM680 User Manual August 2012 www 4dsp com 31 680 Sr ius 8 Technical support Technical support for all 4DSP Product hardware software and firmware is available under 4DSP Terms and Conditions of Sales ONLY in its original condition AS SHIPPED unless agreed to by 4DSP and documented in writin
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