SMT702 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. Ze i K E EN kb ay e Ra W RR amp q EE TER AO T er CMM nie bat EA ber Pid e Je EE it K SE i XS H npp E Nu mI z mn H Sc EK ss i Jerssee EETRI Sa imn LEN M ee oe R b E mE Figure 22 ADC Reset structure modification 10 Safety This module presents no hazard to the user when in normal use 11 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot 12 Ordering Information Three variations of this product are available 1 SMT702 with an XC5VLX110T 3 fastest speed grade available FPGA and works as a PXI Express Peripheral Module The part number for this option is SMT702 Requires a PXI Express chassis such as the NI 10620 from National Instrument 2 SMT702 with an XC5VLX110T 3 fastest speed grade available FPGA and works as a PXI Express Hybrid Peripheral Module PXI P1 connector The part number for this option is SMT702 HYBRPXI32 Requires a PXI Express chassis such as the NI 10620 from National Instrument 3 SMT702 with an XC52. DDR2 Phy Init Done Bank B DDR2 Lock Status Bank A DDR2 Lock Status Bank B DDR2 IDelay Control Ready Bank A DDR2 IDelay Control Ready Bank B DDR2 Empty Status Bank DDR2 Empty Status Bank B DDR 2 Full Status Bank A DDR2 Full Status Bank B 44 XX 45 44 5455 454 FPGA Die temperatore Min 51 2 C Max 53 6 C Current 52 7 C 1 Programming CLOCK Registers Writing Reading back and Checking CLOCK Registers OK Sending control words to Clock Chip Waiting to be completed All control words sent Waiting to be locked Programming amp D CA Writing Reading back and Checking ADCA Registers OK Sending control words to ADCA Waiting to be completed All control words sent Programming ADCB Writing Readina back and Checking ADCB Registers OK Sending control words to ADCB Waiting to be completed All control words sent Running an amp DC Calibration cycle Forcing FPGA DCMs to reset Programming DCMs DCMs ready Starting storing samples into DDR2 memory Checking that both FIFOs are full ADC B Shift Adjustment 400 5 DDR2 Memory iv Fi up DDR banks Stopping storing samples into DDR2 memory Transfer Speed Cha 42 34 Transfer Speed Chb 40 37 Transfer Speed Cha 43 01 Transfer Speed Chb 43 56 Transfer Speed Cha 42 83 Transfer Speed Chb 43 65 Transfer Speed Cha 43 48 Transfer Speed Chb 43 78 Transfer Speed Cha 43 53 FPGA Core
3. 44 eese nnne nnns 39 4 3 1 2 11 ADCA ADCO083000 Register OxF Test Pattern register Ox7C A ES CIO NORTON E E 39 4 3 1 2 12 ADCB ADCO83000 Register Ox1 Configuration Register er bebe Aere NE 28s 16 EEN 40 4 3 1 2 13 ADCB ADCO83000 Register 0x2 Offset Adjust 0x88 write and read 41 4 3 1 2 14 ADCB ADCO83000 Register 0x3 Full Scale Voltage Adjust BEE eebe hate I 2 LEE 41 4 3 1 2 15 ADCB ADCO083000 Register OxD Extended Clock Phase Adjust Fine OxB4 write and read eese nnns 42 4 3 1 2 16 ADCB ADCO0S83000 Register OXE Extended Clock Phase Adjust Coarse OxB8 write and read sss ennenen 42 4 3 1 2 17 ADCB ADC083000 Register OxF Test Pattern register OxBC Metz 0 nmn MM tee ee D AA MAD mM 43 4 3 1 2 18 Frequency Synthesizer LMX2531 Register RO OxCO write and read 43 4 3 1 2 19 Frequency Synthesizer LMX2531 Register R1 OxC4 write and read 44 4 3 1 2 20 Frequency Synthesizer LMX2531 Register R2 OxC8 write and read 44 4 3 1 2 21 Frequency Synthesizer LMX2531 Register R3 OxCC write and read 45 4 3 1 2 22 Frequency Synthesizer LMX2531 Register R4 OxDO write and read 45 4 3 1 2 23 Frequency Synthesizer LMX2531 Register R5 OxD4 write and read 46 4 3 1 2 24 Frequency Synthesizer LMX2531 Register R6 OxD8 write and read 47 4 3 1 2 25 Frequency Synthesizer LMX2531 Register R7 OxDC write and read 48 4 3 1 2 2
4. Min Max Current 5 Acquisitions FPGA Aux Voltage ecaux Save captured data to files per channel Min Es bas WEA Cant z Restore Default 1000 Channels 500 Channel 4 Channel B 500 1000 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 Samples 1000 Channels 500 Channel amp Channel B g 500 1000 50 50 250 300 350 400 3450 500 550 600 650 700 750 500 850 900 950 1000 Samples As soon as the application is launched it reads from the FPGA the board name type Of FPGA PCB revision and the firmware version Once running status flags are displayed in the status section as well as the temperature of the FPGA and its internal voltages 1 0V and 2 5V A log is available on the right hand side Xo 5MT702_0 Configuration HARDWARE SELECTION e SMT702 C SMT702 2Ghz Platform CONFIGURATION 1 Power Supplies iv ADC A iw ADC B Clock Circuitry Apply 2 Resets Do no auto clear ADCs DEMs ADCs DDR2 Banks A and B iw SHB 1 lv SHB 2 3 Serial Interfaces Reference clock circuitry e Clock Circuitry te Y ADC A Testmodel lv ADC B Testmodel Iv ADCs Calibration 4 Shift Adjustment iw ADC A Shift Adjustment 400 Apply Backplane External Onboard External Apply Apply EER C Custom STATUS DCM ADC A Lock Status DCM ADC B Lock Status Clock Chip Lock Status DDR2 Phy Init Done Bank
5. Offset 0x0400 Frequency Synthesizer LMX2531 Register R12 OxE8 write and read om T 9 o Should be programmed as above 4 3 1 2 29 ADCA DCM Phase Shift 0x108 write PE Offset 0x0400 ADCA DCM Phase Shift 0x108 write Sign RR ANETTE I tse 020500 ABCA DEM Phase SOTO Sign of Phase Shift Rane OOOO o Sbi prase shitt value 10 describe a phase shitt between 0 and 255 The default firmware implements one DCM ADV see Xilinx Virtex 5 documentation for more details per ADC data path i e one DCM ADV for ADCA and one for ADCB Both are set to have a programmable phase shift which means it can be changed from the host application Both DCMs are set in mode VARIABLE CENTER There is one bit to set the sign of the phase shit and 8 bit to set the value The phase shift range is 255 255 Once the control word of send the DCM is being reset and programmed with the new phase shift By default the shift register is set to O 4 3 1 2 30 ADCB DCM Phase Shift Ox10C write Offset 0x0400 ADCB DCM Phase Shift 0x10C write 1 Phase Shift Sign aT EI on Phase Shift 7 0 T aaa ADC DOM Phase Si OC Re o an OOOO Tn n The default firmware implements one DCM ADV per ADC data path i e one DCM ADV for ADCA and one for ADCB Both are set to have a programmable phase shift which means it can be changed from the host application Both DCMs are set in mode VARIABLE CENTER There is one bi
6. o HE per bit 0x0 is mv nd mn aae 4 3 1 2 8 ADCA ADCO083000 Register Ox3 Full Scale Voltage Adjust Ox4C write and read Offset 0x0400 ADCA ADC083000 Register 0x3 Full Scale Voltage Adjust Ox4C write and read ENS Adjust Value Default 10000000 ES a ses rend neci fms ae cerei Fieri Value Se o v ry vr j vr v vr T Offset 0x0400 ADCA ADCO83000 Register 0x3 Full Scale Voltage Adjust Ox4C write and read Bit 7 15 Description Full Scale Voltage Adjust 9 bit value 20 adjustment around the nominal 700mVpp differential value 0x0 is 560mVp p and Ox1FF is 840mVp p 4 3 1 2 9 ADCA ADC083000 Register OxD Extended Clock Phase Adjust Fine 0x74 write and read Offset 0x0400 ADCA ADC083000 Register OxD Extended Clock Phase Adjust Fine 0x74 write and read mr Phase Adjust Fine Default 00000000 ME peu e Adjust Default Offset 0x0400 ADCA ADC083000 Register OxD Extended Clock Phase Adjust Fine 0x74 write and read Bit 7 15 Description Fine Adjust Magnitude 9 bit value With all bits set adjust 110ps 4 3 1 2 10 ADCA ADCO083000 Register OxE Extended Clock Phase Adjust Coarse 0x78 write and read Offset 0x0400 ADCA ADC083000 Register OxE Extended Clock Phase Adjust Coarse 0x78 write and read BINE I A ESTE El ener reserved Reserved Reserved Reserved Reserved Reseed Reserved Off
7. 8 1PETps 1PEIn5 GND 9 4PETp6 1PETn6 GND 10 RSV RSV GND OPSUUOD EX EdX RSV O GND C E 0 Z gt L Q Pn ADT 23 O w K D 2 labo GND GND GND GND PER GND GND GND B Pal lt t AD 7 22 21 6 LA z DnA ERR il d EEEEEEEEBE E lt ol t em G r3 BE OF D 10 D 13 BE 1F ERR G Z O VIVO 11 D G Z O 0 MB GC IPMB SDA VO t ol e gt LA i lt lt l EVSEL Key Area P1 J1 Connector AD 18 AD 21 C BE 3 AD 26 AD 30 REQ BRSVP1A5 IPVB PWR BERF D 19 D 22 ND D 24 29 ADOS l D 31 RST VIS VIVO N T SVP1B5 EALTHY 5 ob 7 GND 1 ob 19 ob 185 GND SE e 15 6ND SESCH 710 Z e Nb e mb e z w o x 2 e ToO 9 5 9 8 mio lt 31218 Z az d O 2 BI 2 0 r c m ii TCK 1 evb Ev EET n S 6 8 LA LA z SIRI lt A e 2io lo o Ol Slo molo n g zi iz Zl DI Z 312 z TT 3 RST 12V ND The SMT702 implements up to eight 2 5 Gigabit PCI Express lanes allowing a maximum theoretical data transfer of 2 gigabytes per second It also implements optionally a 32 bit 33 MHz PCI interface 4 3 FPGA Design The following block diagram shows how the default FPGA desi
8. Instrument PXIe 10620 4 2 10 JTAG A connector J8 is specifically dedicated for FPGA and CPLD detection and programming Both the CPLD and the FPGA are part of the JTAG chain A 14 position 2x7 connector 2mm is available and shows TDI TDO TCK and TMS lines as well as a Ground and a reference voltage as shown below 0 0787 2 mm JIAG NC 14 13 GND NC 12 11 GND TDI 10 GND TDO GND TCK GND TMS GND VREF 2 GND 0 020 0 5 mm SQ TYP Figure 11 JTAG Connector It can connect directly to a Xilinx Parallel IV cable using the ribbon cable provided by Xilinx The connector is a Molex part Molex 87831 1428 Figure 12 Photo of a Xilinx Parallel IV cable and its ribbon cable for JTAG connection 4 2 11 PXI Express Hybrid Connectors As being a PXI Express Hybrid Peripheral Module the SMT702 is a 3U card with 2 PXI connectors XP4 and XP3 or P1 The following table shows their pinouts N Ww 2 GND 4 GND 5 GND PXI PXI TRIG GN A B PXle CLK100 PXIe CLK100 GND GND GND il D e ell E o SEIEEREIEIEIEER EEREEREERE gio N e kl Ee e e eo GE R z z z S O G O eiaoljo ao o ao o o o o O 0 0 0 0 0 0 0 0 ziziziziziziz Z Z Z Z Gl de Z Z Z 0 90 0 0 0 0 0 O 0j 0 O OO 0 9 O PXle SYNC100 PXle SYNC100 GND PXle DSTARB PXle DSTARB GND BE A RSV GND 1PERPO GND 1P GND GND A1PERp4 E 5 D 24 CRE 41 JU
9. Number of BUFG BUFGCTRLs 26 Out of 32 Number used as BUFGs 2 0 Number of IDELAYCTRLs 6 OUT ot 22 21 Number of BSCANs T Xu Or 4 25 Number of BUFDSs T E Or 8 12 Number of BUFIOs LO ur or 80 20 Number of DCM_ADVs Bout Of 152 66 Number of LOCed DCM ADVs S Ut OF 8 100 Number of GTX DUALs 2 Ole QUE 8 25 Number of LOCed GTX_DUALS D ONU dE 2 100 Number of PCIEs 1 out of 3 335 Number of LOCed PCIEs LOUT EE 1 100 Number of PLL ADVs LOQUE Df 6 16 Number of SYSMONs EE OL 1 1003 Number of RPM macros 137 Average Fanout of Non Clock Nets GEN IA The parts mentioned above XC5VLX110T XC5FX70T XC5FX100T are also footprint compatible with the SXT series XC5VSX50T and XC5VSX95T The SXT series implements a DSP48E core which if used on the SMT702 may result an increase of the power consumption Please contact Sundance if you require details about the SXT series 4 2 3 Configuration CPLD Flash On the SMT702 the FPGA is connected to a CPLD via a serial link The CPLD is responsible for controlling read and write operations to and from the Flash memory and to route data to the FPGA configuration port The following diagram show how connections are made on the board between the CPLD the Flash memory and the FPGA Data 7 0 Configuration port Address 25 0 Ctrl 9 0 b d Y 1 4 Eege Switch 1 0 Figure 5 Configuration Flash A reset coming from the bus
10. PXI or PXI Express triggers a configuration cycle and the FPGA is configured with the default firmware stored in factory at location 0 The on board Flash memory 256 Mbit part is big enough to store several versions of firmware A switch SW1 at the back of the board allows the selection among 4 locations Switches select the bitstream to be booted at power up Each can contain up to 8Mbytes of data which is big enough to store an XC5LX110T bitstream about 3 8 Mbytes and some text comments or description of the firmware version The user can store a user bitstream at location 1 see table below for instance using the SMT6002 piece of software also called Flash Utility The SMT6002 also allows to add comments text above the bitstream in flash memory Note that switches don t have any influence when programming the flash This architecture allows the SMT702 to be used as a development platform for signal processing and algorithms implementation The function Reboot can be used from the SMT6002 GUI to boot from any flash location within seconds Both FPGA and CPLD can be reprogrammed reconfigured at anytime via JTAG J8 connector Using a Xilinx parallel USB programming cable but it can cause problems as it will break the access to the board from the host At power up or under a reset on the PXI or PXI Express bus it takes 140ms for the FPGA XC5VLX110T 3 to be fully configured and ready to answer the requests from the ho
11. Dara showta notve wen O O O O O O OoOO o aan o aah o o naman Oo moy a ot most mp o o Norma ode ot penton OOOO O o o Liege O aenean EU o etc coming out of ADCa isat low logic level at the me i s been scanned FREE EU o re dock coming out of ADC isat alow loge level at the Eme sb scanned a 4 3 1 2 2 Set Control Register Ox10 write Offset 0x0400 Reset Register 0x10 write Soft Reset SHB2 SHB1 DDR2 External Monitor Reset Reset Reset ChA amp B Trigger Capture Reset Read Selection enable Enable Da o0 v v o v v v v 1 DCM Reset ADC Reference Reference Ref Ref Clock Selection Calibration Clock Clock Out Clock request OnBoard Divider Circuitry auto Divider Reset clears 2 ti eee s Sampling CLOCK ADCB ADCA Clock ADCB ADCA Clock Power Power Power Update Update Update Selection Supplies Supplies Supplies auto auto clear auto Source Enable Enable Enable clears clears Ene o e v e Tr Ly Offset 0x0400 Reset Register 0x10 write Description ADCA Update Auto Clears L9 o Normal Mode of Operation All Current ADCA Register are passed from the FPGA to the ADCA Chip Description ADCB Update Auto Clears BEEN o Normal Mode of Operation All Current ADCB Register are passed from the FPGA to the ADCB Chip Description Clock Update Auto Clears L9 o Normal Mode of Operation All Current Clock Register are passed from the FPGA to the Clock Chip o o 5omamo
12. Express 3U Board Booted Board Booted Board Booted SMT702 LX110T ADCS OFF ADCs ON ADCs ON Clock OFF Clock ON Clock ON SHBs OFF SHBs OFF SHBs ON Supply Currents 0 88 amp 1 03 amps 1 07 amps Dimensions PXI Express 3U Board Booted Board Booted Board Booted SMT702 FX70T ADCS OFF ADCs ON ADCs ON Clock OFF Clock ON Clock ON SHBs OFF SHBs OFF SHBs ON Supply Currents 1 06 amp 1 08 amp The SMT7002 GUI has been used to configure the boards from which currents consumed were measured Boards were setup as follows internal clock locked on external 10 MHz reference ADCs clocked at 3GSPS and set in Test mode continuous acquisitions DMAs MTBE MTBF 9 Hardware Modification It has been found that modifying the converter reset structure improves the synchronisation between the ADCs The non symetrical structure previously used would add a non wanted delay on the second ADC channels The new structure consists in removing some ICs and replacing them by 2 sets of differential wires ADCs can now be more accurately synchronised in frequency A software function has been added to the software package returning the skew between the 2 ADC sampling clocks A typical skew measured at the FPGA is 170pS T Fr L HD augsdsasudsM d NU 2 AE _ i pet 5 AA Re a IA o L Es el e CS T nad hl e Cf x G lt a ER E m i Teen ya wi Se gt T E TTT TE AA i Sees
13. OxE Extended Clock Phase Adjust Coarse OxB8 write and read Offset 0x0400 ADCB ADCO83000 Register OxE Extended Clock Phase Adjust Coarse 0xB8 write and read El ener reserved reserved reserved Reserved Reserved erd Reserved Offset 0x0400 ADCB ADCO83000 Register OxE Extended Clock Phase Adjust Coarse OxB8 write and read EUG sampte loe one soon OO O O OOOO O O a o steve Each sn adds approximately 70ps of Cock ast o a o owa O 4 3 1 2 17 ADCB ADC083000 Register OxF Test Pattern register OxBC write and read Offset 0x0400 ADCB ADCO83000 Register OxF Test Pattern Register OxBC write and read Dem v v 0 v NM Offset 0x0400 ADCB ADCO83000 Register OxF Test Pattern Register OxBC write and read Description TPO Test Pattern Output Enable O 0 Normal mode of Operation All ADC outputs in Test Pattern mode 4 3 1 2 18 Frequency Synthesizer LMX2531 Register RO OxCO write and read The LMX2531 in the SMT702 is a clock synthesizer that generates a frequency within the range 1499 1510MHz The chip has a built in VCO and uses a reference clock to lock its pll ose 050500 Frequency Symhesizer NAZSSI Register RO OxCO wt and read HERE Offse Ox0400 Frequency Synthesizer DSS Register RO ONCO rte and read EUG o vete o an o9 na 19990961 OOOO OOOO O O O o ve en 100 20 AGE 4 3 1 2 19 Frequency Synthesizer LMX2531
14. Peripheral Slot Compatible PXI 1 Module 4 2 8 SHB Connector An SHB Connector is available from the FPGA It maps 32 single ended data lines and a set of control signals including a clock It can be used to transfer samples to an other Sundance module for instance the SMT712 A second SHB connector is available on the standard version of the SMT702 not available on the option HYBRPXI32 and CPCI32 Note that in order to achieve transfers to an SMT712 board the standard SHB interface can t be used but requires its DDR version implement into default firmware The SHB transfers have been tested at 375MHz DDR mode 32 bit words giving a continuous transfer speed of 3GBytes per second 4 2 9 Power dissipation The SMT702 has been designed to work in a PXI Express chassis which has built in cooling facilities It provides enough airflow and has a fan regulation PXI Express chassis are specified so they can dissipate 30 Watts of heat The following picture shows the direction of the forced air flow across a 3U PXI Express module Figure 10 Forced airflow for a 3U module A PXI Express rack has a capacity of dissipating 30 watts of heat per slot using forced air cooling system via typically two 110 cfm fans with filter In case the SMT702 is used in an other type of chassis some similar airflow must be implemented as the board requires it The SMT702 has been developed using the following PXI Express rack from Nation
15. Register R1 OxC4 write and read tae 10800 Frequency Synthesizer DSTI Register RI ONCA write and read aT w ww O o Ea NMwi Otis x0400 Frequency Synthesizer 2531 Register RI aae and read FF va tn 0 an osana 4194303 iy o o ve even ona and 2039008 OOOO OO OSSO O EURO o osocorespontsto 900A tte 1 nd State 10 10 14400A GOW per state 4 3 1 2 20 Frequency Synthesizer LMX2531 Register R2 OxC8 write and read Tote 00200 Frequency Syatesizer ISI Reiner CE te and all em ww a DEN 1 1 0 GE 03 WE Offset 0x0400 Frequency Synthesizer LMX2531 Register R2 0xC8 write and read R Counter Value RI5 0 R Country Value These bits determine the phase detector frequency Only possible values are 1 2 4 8 16 or 32 Bit 17 6 Fractional Denominator DEN 11 0 9 o0 Value between 0 all Os and 4194303 all 1s 4 3 1 2 21 Frequency Synthesizer LMX2531 Register R3 OxCC write and read Offset 0x0400 Frequency Synthesizer LMX2531 Register R3 OxCC write and read mw mmus EE Den e Ea mad ose 30300 Frequency Synthesizer UMXZ531 Register OxCC ute and read o T veneen o an o9 ana 0 t19 OOOO OOOO OO o oo res pin not used on tne SMT702 Set Regne OOO o mm ma O o oo weas OOOO o oso ony ists of the fractional numerator and denominator are considered o oo vc copar requency not dez 4 3 1 2 22 Fre
16. Sce LOG Le DstrrtbDltuzom Number of occupied Slices duo Gut OF 16700900 45 Number of LUT Flip Flop pairs used Zh pe EOS Number with an unused Flip Flop A ASS out OL Zl l53 20 Number with an unused LUT Og 2450 OUE Of Xl Ss 38 Number of fully used LUT FF pairs Oy 276 OUb OL 21 0759 40 Number of unique control sets 994 Number of slice register sites lost to control set restrictions Zoll Gut oL 647000 3 A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice A control set is a unique combination of clock reset set and enable signals for a registered element The Slice Logic Distribution report is not meaningful if the design is over mapped for a non slice resource or if Placement fails OVERMAPPING of BRAM resources should be ignored if the design is over mapped for a non BRAM resource or if placement fails IO Utilization Number of bonded IOBs 465 out of 640 12 Number of LOCed IOBs 465 out of 465 100 LOB Flip Flops 694 IOB Master Pads T IOB Slave Pads 1 Number of bonded IPADs 10 Number of LOCed IPADs 2 UE O LO 20 Number of bonded OPADs 8 Specific Feature Utilization Number of BlockRAM FIFO 22 E Or ZU 18 Number using BlockRAM only 26 Number using FIFO only 16 Total primitives used Number of 36k BlockRAM used 22 Number of 18k BlockRAM used 4 Number of 36k FIFO used 14 Number of 18k FIFO used 2 Total Memory used KB 1 404 out of 8 208
17. eee Ra R eia Kaa Re OOOO O 4 3 1 2 34 System Monitor FPGA core voltage thresholds Ox184 write Offset 030400 System Monitor FPGA core voltage hresholds 0x184 write 3 Reserved 1 Vccint upper threshold 5 0 Vccint lower threshold 9 8 on o Vccint lower threshold 7 0 EE Offset 0x0400 System Monitor FPGA core voltage thresholds 0x184 write Bit 19 10 FPGA Core voltage upper threshold BEEN The Voltage is coded on 10 bits FPGA Core voltage lower threshold o The Voltage is coded on 10 bits 4 3 1 2 35 System Monitor FPGA Aux Voltages 0x188 read Offset 0x0400 System Monitor FPGA Aux Hid 0x188 read EE Sm Reserved Maximum Vccaux 9 4 e O Wemmel mammen CL Mammen O WE E Emmer EE PRESSE RE OOOO O O O E trevonaseiscodedon ions OOOO O 4 3 1 2 36 System Monitor FPGA aux voltage thresholds 0x188 write arm System Monitor FPGA aux volage thresholds Rene EN 0 5 5 5 mm 0000 EUR begleed Vccaux upper threshold 5 0 Vccaux lower threshold 9 8 o Vccaux lower threshold 7 0 ose ox0400 System Montar FG aux voltage thresholds Oir FTF tre vote code oO o The Voltage is coded on 10 bits 4 3 1 2 37 Amount of samples stored in DDR2 Bank A 0x18C write MEN Offset 0x0400 Amount of samples stored in DDR2 Bank A 0x18C read Dwma www ww MEA Amount of samples DI Offset 0x0400 Amount of samples s
18. locked They are available in the Global Control Register After being latched samples go through a multiplexer to be pipelined and then stored into the DDR2 memory available on the board The DDR2 interface uses some Xilinx specific blocks such as idelays DCMs and Phy which have to be locked and ready as well These have to be checked the same way using the bits available from the Global Control Register Each ADC is being dedicated a DDR2 Memory bank which can be seen as a Fifo Both Fifos have status bits to check whether they are empty or full bit available from Global Control Register Each Fifo is connected to a DMA channel DMA channel are implemented as Xlinks Samples coming from the ADCs are also routed straight on the SHB connector DDR 32 bit bus The following diagram shows the data path implemented in order to capture samples from the ADCs Ref Out PXI Ref 10MHz PXle Ref 100MHz Ext Ref Ext Clk ADCB Clock 4x8 bits 375MH DDR LVDS Figure 7 Data samples path The SMT702 comes with a piece of software the SMT7002 It is a demo application that shows how to set up the module and allows capturing samples into text files Source code of the SMT7002 is available to purchase under the product name SMT7026 4 2 7 PXI Express Bus As standard the SMT702 is a 3U PXI Express peripheral module which means it comes with two PXI Express connectors XP4 P
19. memory map for the writable and readable registers on the SMT702 The access to a specific register is made by reading or writing to the address Address from Host Offset Register Address Offset Description Offset 0x0000 SMT7xx Common Registers Register d i Address Writable Registers Readable Registers 0x04 Global Reset bit31 Reserved 0x80 Reconfiguration Bitstream number Reserved Offset 0x0400 SMT702 Registers Register i Address Writable Registers Readable Registers 0x24 Board Name and Version 0x40 Firmware Version and Revision Numbers 0x44 ADCA ADC083000 Register 0x1 Read back FPGA Register ADCA ADCO83000 Register 0x1 0x48 ADCA ADC083000 Register 0x2 Read back FPGA Register ADCA ADCO83000 Register 0x2 0x4C ADCA ADCO83000 Register 0x3 Read back FPGA Register ADCA ADCO83000 Register 0x3 0x74 ADCA ADC083000 Register OxD Read back FPGA Register ADCA ADCO83000 Register OxD 0x78 ADCA ADCO83000 Register OXE Read back FPGA Register ADCA ADCO83000 Register OXE Ox7C ADCA ADCO83000 Register OxF Read back FPGA Register ADCA ADCO83000 Register OXF 0x84 ADCB ADC083000 Register 0x1 Read back FPGA Register ADCB ADCO83000 Register 0x1 0x88 ADCB ADC083000 Register 0x2 Read back FPGA Register ADCB ADCO83000 Register Ox2 Ox8C ADCB ADC083000 Register 0x3 Read back FPGA Register ADCB ADCO83000 Register 0x3 OxB4 ADCB ADC083000 Register
20. opt Hybrid Peripheral Module 3U which integrates two fast 8 bit ADCs a clock circuitry 2 banks of DDR2 Memory 1GByte each IO connectors 2 SHBs SATA and RSL and a Virtex5 Xilinx FPGA under the 3U format The PXIe specification integrates PCI Express signalling into the PXI standard for more backplane bandwidth It also enhances PXI timing and synchronisation features by incorporating a 100MHz differential reference clock and triggers The SMT702 can also integrate the standard 32 bit PXI signalling as an option Both ADC chips are identical and can produce 3 Giga samples per second each with an 8 bit resolution The manufacturer is National Semiconductor and the part number is ADC083000 Analog to Digital converters are clocked by circuitry based on a PLL coupled with a VCO in order to generate a low jitter signal Each ADC integrates settings such as offset and scale factor which makes the pair of ADC suitable to be combined together in order to make a 6GSPS single Analog to Digital converter This will be subject to a specific FPGA design An on board PLL VCO chip ensures a stable fixed sampling frequency maximum rate in order for the board to be used as a digitiser without the need of external clock signal The PLL will be able to lock its internal VCO either on the 100MHz PXI express reference on the 10MHz PXI reference or on an external reference signal The sampling clock for the converters can be either coming from the PLL VC
21. 083000 Register 0x2 Offset Adjust 0x88 write and read Offset 0400 ADCH ADCOSIODO Register 0x2 Offset Adjust 0x88 write and read Offset Value oJ senes reserves Reseved seed reserved Resened Reserved Reserved ter 30300 ADCH ADCOSS000 Register 0x2 Offset Adjust 0x88 rt and read o o estra 0 76m0 per bit 0x0 is Omv and O Kl manet 4 3 1 2 14 ADCB ADC083000 Register Ox3 Full Scale Voltage Adjust Ox8C write and read EN Offset 0x0400 ADCB ADCO83000 Register 0x3 Full Scale Voltage Adjust Ox8C write and read Adjust Value KA nl eat nns hang use lapa unu Value Bem v v Ps pe pe Offset 0x0400 ADCB ADCO83000 Register 0x3 Full Scale Voltage Adjust 0x8C write and read Bit 7 15 Description Full Scale Voltage Adjust 9 bit value 20 adjustment around the nominal 700mVpp differential value 0x0 is 560mVp p and Ox1FF is 840mVp p 4 3 1 2 15 ADCB ADC083000 Register OxD Extended Clock Phase Adjust Fine OxB4 write and read Offset 0x0400 ADCB ADCO83000 Register OxD Extended Clock Phase Adjust Fine OxB4 write and read Phase Adjust Fine Elli ll nid al ddl Adjust Ema v v Offset 0x0400 ADCB ADCO83000 Register OxD Extended Clock Phase Adjust Fine OxB4 write and read Bit 7 15 Description Fine Adjust Magnitude o 9 bit value With all bits set adjust 110ps 4 3 1 2 16 ADCB ADC083000 Register
22. 3GSPS On board VCO 1498 MHz filtered Full Scale 0 5dB 3GSPS On board VCO Figure 15 Main Characteristics 54 454dBs Cha 47 859dBs Chb 5 Board Layout 5 1 Top View fu yao aya JOY UH Jaw KI 7 gum d L SLAM all Z Bs 9999999999999992999 999999999 9999999999299 EN 4 7 H 18 NI wan i 1 C Anas aaia e2v edet 99 999999 999 999999999299 99 99999999 99999999999999929 29 999999999 9 999 999999999 99929 49 999999999 9999999999 99999 999929 9 999999999 999 99999999999 999929 9 999999999 999 99999999999 99929 9 9 999999999 999999999999 9992929 eee eee eee eee eee eeee eee eee eee eee eee eee eee ee eee KR aus 999999999 99 99999999999 99929 9 999999999 999 9999 999999499 929299 99999999999999999999929 9 999999999999999999099929 9 KA LA Mp 222225 Was SXOMLA 99999999999999999999929 9 9 9999999999999999999929 9 9 9999999999999299 99999999999999999999 29 9999999999999999999299 KA 9 9999999999999999999299 KA 9 9999999999999999999299 KA 999999999 99999999999299 KA KA 7 ere eee RI ee LA AAA AAA AAA ee eeeeee ee LA AAA AAA AAA AAA AAA AAA AAA AA 999999999 9999999999929 299 999999999 99 99 9999999999 99299299 9 999999999 9999999 9999999 9999 99929 6 4 9
23. 6 Frequency Synthesizer LMX2531 Register R8 OxEO write and read 48 4 3 1 2 27 Frequency Synthesizer LMX2531 Register R9 OxE4 write and read 49 4 3 1 2 28 Frequency Synthesizer LMX2531 Register R12 OxES8 write and read 49 4 3 1 2 29 ADCA DCM Phase Shift OX108 write 50 4 3 1 2 30 ADCB DCM Phase Shift Ox10C write 50 4 3 1 2 31 System Monitor FPGA Die Temperatures 0x180 read 91 4 3 1 2 32 System Monitor FPGA Die Temperature thresholds 0x180 write 91 4 3 1 2 33 System Monitor FPGA Core Voltages 0x184 read 52 4 3 1 2 34 System Monitor FPGA core voltage thresholds 0x184 write 52 4 3 1 2 35 System Monitor FPGA Aux Voltages 0x188 read SE 4 3 1 2 36 System Monitor FPGA aux voltage thresholds 0x188 write 53 4 3 1 2 37 Amount of samples stored in DDR2 Bank A 0x18C write 54 4 3 1 2 38 Amount of samples stored in DDR2 Bank B 0x190 write 54 e E Te re be eR e 94 e E ECT Al Siena charcas 9 3 BOard Lay E 57 VE TOD EE o puc e egen EE St D tee 59 CE OD 2e s Rol dee a E E E 59 CMM ue UNES SS T 61 6 3 How is it going to stand on your desk see 61 7 Software Packages suede hien hacac tipp p DoD ee 62 8 Poy SIC ONC TEE 64 9 SEN de ER Tee E Te LE 65 O Sae uan E IM IE E E IE 66 BN ONE OS 66 12 Ordering Mi 66 Table of Figures
24. 992929 4 4 eee eee eee ee 9999999999 999999 9999999 9999 999 299 9 99999999999999 99 9999999 9999 992929 9 99999999 99 99999 99999999 9999 999299 9 999999999999999 9999999 999 99 99929 DESEE 9 9999999999999999999 99 9999999999 9 9999999 99 99 99 99 9999999999 9999 99299 1S8 ll ra tagba k T E SYL E gl ex R D e Ss cars 9 099 0606029 I 99995992929 tettetett 599906099449 NOIA SAA Gersrsses y 96094404 46BOAOO 99999999 e eeeqee0080 6 sng ald Figure 16 Board Layout Top View L t 2583 s Y e 9099 9 e 5 2 Bottom View External Power a Supply DDR2 Memory A EIJ L O o 9090909 KEZET Er d EELEE eui so n ESTO o ha ee eee o EELER e ESF pa xzilwM LE OS E E EEEE m Pete eerie ofl Fa d MEA E eee A E cR EP aM sesososet e GR Ger COSC CeCe SE a gt az dRI SI Vi 66666666 eas 7 iz o zi AO 00000008 ON 1 attr Ven mm du s 3 2 99999999 e d a LE LAAL gata mnl cx A LA LALA ALA Ee aa O Gi ari En S ed M z E ee ee ee UI pua uq a SEM ES UM TT eee ee S L 93 Ka CHO B e E S B i 66666 6 T sm a2 eu E Gs E EM y Wl go cmm tS 33 24 amd 3 en LS Pa sg i r Se ss ken D EDO EOS e e 8 ots bg ayo KAS cu y eee Mu ms Bo ee S aM 5 Ue CR G E BE 1 ERN KR BmI en ee mano 54 oeeeee IN rrEJ cu comm mu 60004000 a S WO e ET CH a E
25. C coupled and Single ended Termination implemented Format at the connector Differential on option 3 3 V PECL Frequency range 62 5 MHz maximum ADCs Output characteristics The figures below have been obtained using WaveVision version 5 with default options On board VCO used ADCs running at 3GSPS 16k point FFT E4433B Signal Generator coupled with a 6 order filter Coherent sampling captures Bandwidth ENOB 373 MHz filtered Full Scale 0 5dB 7 1 bits Cha 6 76 bits Chb 3GSPS On board VCO 749 MHz filtered Full Scale 0 5dB 7 2 bits Cha 6 906 bits Chb e 6 7 bits Cha 6 563 bits Chb 1498 MHz filtered Full Scale 0 5dB SNR 373 MHz filtered Full Scale 0 5dB 44 6dBs Cha 42 5dBs Chb 3GSPS On board VCO 749 MHz filtered Full Scale 0 5dB 46 5dBs Cha 46 3dBs Chb 3GSPS On board VCO 1498 MHz filtered Full Scale 0 5dB 3GSPS On board VCO 43 2dBs Cha 41 8dBs Chb SINAD 373 MHz filtered Full Scale 0 5dB 44 6dBs Cha 42 4dBs Chb 3GSPS On board VCO 749 MHz filtered Full Scale 0 5dB 45 1dBs Cha 43 3dBs Chb 3GSPS On board VCO 1498 MHz filtered Full Scale 0 5dB 3GSPS On board VCO 42 6dBs Cha 41 6dBs Chb SFDR 373 MHz filtered Full Scale 0 5dB 58 165dBs Cha 46 722dBs Chb 3GSPS On board VCO 749 MHz filtered Full Scale 0 5dB 53 183dBs Cha 47 234dBs Chb
26. CTRLs 23 006 Of 32 71 Number used as BUFGs 23 Number or IDELAYCTRLsS o out of Ze 21 Number of BUFDSs L OE Oar 8 12 Number of BUFIOs To OE orf 80 20 Number of DCM ADVs e Out Of 12 66 Number of LOCed DCM_ADVs Out Of 8 100 Number of GTP DUALs 2 OUE OF 8 25 Number of LOCed GTP DUALSs 2 OUE Ot 2 1005 Number of PCIES d urb OE 1 100 Number of PLL_ADVs L Out Of 6 16 Number of SYSMONs Ts OAC OE 1 100 Number of RPM macros 128 Average Fanout of Non Clock Nets 3 00 4 2 2 3 Resources used XCV5FX70T Below is a summary ISE11 4 of the resources used in the FPGA by the default firmware Standard SMT702 XCV5VFX70T FPGA PXIe option Slice Logic Utilization Number of Slice Registers 15 344 out of 44 800 34 Number used as Flip Flops 1 590 9 Number used as Latches 1 Number used as Latch thrus 6 Number of Slice LUTs 114932 Out Of 44 900 26 Number used as logic 11 972 cout or 447800 25 Number using O6 output only 9 458 Number using O5 output only 209 Number using O5 and O6 d 52 5 Number used as Memory AZo OU OX 3529 3 Number used as Dual Port RAM 308 Number using O6 output only 204 Number using O5 output only 20 Number using O5 and Op 84 Number used as Shift Register kat Number using O6 output only BE Number used as exclusive route thru 31 Number of route thrus 593 Number using O6 output only 349 Number using O5 output only JS Slice Logic Distribution Number of o
27. Figure 1 SMT702 General Block Diagram eeeeeeeeeee ener 9 Figure 2 SMT702 Block Diagram Standard SMT702 PXI Express 10 Figure 3 SMT702 Block Diagram 32 bit PXI Option eene 11 Figure 4 SMT702 CPCI32 Block Diagram 32 bit CPCI Option 12 SE COMM CUTA E Le PIAS geceeesbeebterh eech edi audiat ereescht 18 Figure 6 Clock circuitry Block Diagram ee 21 Figure Data samples pati nanc eI D tun M M DIE 22 Figure 8 Standard SMT702 PXI Express Peripheral Module 23 Figure 9 SMT702 HYBRPXI32 opt Hybrid Peripheral Slot Compatible PXI 1 lee PULS NN RN RN TT TT 23 Figure 10 Forced airflow for a 3U module sss essen 24 Fere llc LAG E e E WEE 25 Figure 12 Photo of a Xilinx Parallel IV cable and its ribbon cable for JTAG CONEA OS 26 Figure 13 Block Diagram FPGA Design standard Firmware e 28 Meme 14 Register Memory Map asia pa RO ME EM 30 FIC UEC Lo Man Characteristics e t ed d te ee a Qe rn ee 56 Figure 16 Board Layout Cl OV ICW EE 57 Fore 17 board Layout BOON VIEW las 50 Ligure I9 MOVERVIEW OL EE ee 60 I1gure 19 SMJITO2 ge re ae E 61 Ligure H SIME 702 PXUEXDEeSS CHASSIS EE 61 Fore 2T SMTZ02 Demo Ap Te e Te EE 63 Figure 22 ADC Reset structure modification eese enne nnne 65 1 Introduction The SMT702 is a PXI Express
28. H TTT eE aeae 000000 4 3 1 2 5 Firmware Version and Revision Numbers 0x40 read only SEET UR CSirmare Revision meras Offset 0x0400 Reset Register 0x40 read only Sg Rania ean R E HET 4 3 1 2 6 ADCA ADC083000 Register Ox1 Configuration Register 0x44 write Offset 0x0400 ADCA ADC083000 Register 0x1 Configuration Register 0x44 write Ew v v v v v v ETUR Seed Reserved Revered Resewed Revered Reserved Reened Reserved ise oxt400 ADCA ADCORIOUO Register 0x1 Configuration Register 0x44 orite EUG o aeaea OOOO O o aian OOOO EU o srt rt able EU o opee ancowpdpk mesedwm we O O O O O OO EL o oome OOOO 1 Reduced output amplitude 510mV This setting is recommended on the SMT702 It reduces the overall noise on the board and therefore increases the performance of the ADCs Standard output amplitude 710mV Description OE Output Edge 9 o 1 4 Demux Mode DDR Mode must be Selected 1 2 Demux Mode DDR Mode must be selected 4 3 1 2 7 ADCA ADCO083000 Register 0x2 Offset Adjust Ox48 write and read Offset 0x0400 ADCA ADCO83000 Register 0x2 Offset Adjust 0x48 write and read we mz me ms mua ms mz ma mo 1 Offset Value Default 00000000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved E Offset 0x0400 ADCA ADC083000 Register 0x2 Offset Adjust 0x48 write and read
29. L fl La e H EI OH BW O C rn Sl N SES JB nanna MEE 119 2517 BIO S led 0 9999 TP7 C es a os j GC TELER e ST I HE PE 11 E d EREET S sgg y ee ee ee d z lt o el 3 060800 EE s wm Z 666666 O 1 po T ON OSAMA Flash CPLD Figure 17 Board Layout Bottom View 6 Photo 6 1 Overview of the board nue o III nimimm HATT m IEA mI L E emi TEPES eeeeeeeeggg eeegegeeggegg HEI IMS UO CBR RW RW RR m m UL ER ER P P P ER ER Se DUU iH LT Mt it un 1111 Figure 18 Overview of the board 6 2 Front panel On the front panel of the SMT702 6 SMA connectors are available for ADC ChannelA ADC ChannelB External Reference and Clock in and out There is also a dual SATA I connector Figure 19 SMT702 Front Panel 6 3 How is it going to stand on your desk The SMT702 has been designed to be plugged into a PXI Express chassis from National Instrument The NI PXIe 10620 is an example 8 Slot PXI Express Chassis for PX and PXI Express Modules Ni PXle 10620 l Figure 20 SMT702 PXI Express Chassis 7 Software Packages Here is a list of the software packages that will be required for the SMT702 to work e SMT6300 is the software package that installs the Sundance driver for the SMT702 board e SMT6002 is the software package that installs the server application to write into flash memory this
30. O chip fixed frequency of 1 5ghz or from an external source The chip used is a National Semiconductor part LMX2531LQ1500 The reference clock selected is also output on a connector in order to pass it to an other module The Virtex5 FPGA is responsible for controlling all interfaces including PXI 32 bit and PXIe up to 8 lanes not all PXI Express controller support 8 lane as well as routing samples The FPGA fitted on the SMT702 is part of the Virtex 5 familly from Xilinx XC5VLX110T 3 fastest speed grade available Two DDR2 memory banks are accessible by the FPGA in order to store data on the fly Each bank can store up to 1GByte An SHB connector is available in order to transfer data samples to an other Sundance module SMT712 for instance All analog connectors on the front panel are SMA 2 Related Documents 2 1 Referenced Documents 1 National Semiconductor ADC083000 http www national com pf DC ADCO083000 html 2 National Semiconductor LMX2531L01500 http www national com pf LM LMX2531L01500E html 3 Virtex5 FPGA http www xilinx com products silicon solutions fpgas virtex virtex5 index htm 4 PXIe specifications http www pxisa org Spec PXIEXPRESS HW SPEC R1 PDF 5 Micron 2Gigabit DDR2 chip MT47H128M16 http download micron com pdf datasheets dram ddr2 2gbddr2 pdf 6 Sundance xlink presentation ftp ftp2 sundance com Pub documentation paf files X Link pdf 7 Sundance xlink specificati
31. OxD Read back FPGA Register ADCB ADCO83000 Register OxD OxB8 ADCB ADC083000 Register OxE Read back FPGA Register ADCB ADCO83000 Register OxE OxBC ADCB ADC083000 Register OXF Read back FPGA Register ADCB ADCO83000 Register OXF 0xCO Frequency Synthesizer LMX2531 register RO Read back FPGA register Frequency Synthesizer LMX2531 register RO 0xC4 Frequency Synthesizer LMX2531 register R1 Read back FPGA register Frequency Synthesizer LMX2531 register R1 0xC8 Frequency Synthesizer LMX2531 register R2 Read back FPGA register Frequency Synthesizer LMX2531 register R2 OxCC Frequency Synthesizer LMX2531 register R3 Read back FPGA register Frequency Synthesizer LMX2531 register R3 OxDO Frequency Synthesizer LMX2531 register R4 Read back FPGA register Frequency Synthesizer LMX2531 register R4 0xD4 Frequency Synthesizer LMX2531 register R5 Read back FPGA register Frequency Synthesizer LMX2531 register R5 OxD8 Frequency Synthesizer LMX2531 register R6 Read back FPGA register Frequency Synthesizer LMX2531 register R6 OxDC Frequency Synthesizer LMX2531 register R7 Read back FPGA register Frequency Synthesizer LMX2531 register R7 OxEO Frequency Synthesizer LMX2531 register R8 Read back FPGA register Frequency Synthesizer LMX2531 register R8 OxEA Frequency Synthesizer LMX2531 register R9 Read back FPGA register Frequency Synthesizer LMX2531 register R9 OxE8 Frequency Synthes
32. SE Number of IDELAYCTRLs 6 OUE QE 22 21 Number of BUFDSS d SOUR OE 8 12 Number of BUF IOs O OU OL 80 20 Number of DCM ADVs 0 EE Or T2 66 Number of LOCed DCM_ADVs o QUE dx S OUS Number of GTX DUALs A OU Ok 8 2 5 5 Number of LOCed GTX DUALSs 2 OU OX 2 100 Number ot PCIES d QUE Or 3 33 Number of LOCed PCIESS d uu OE 1 100 Number of PLL ADVs 1 out Of 6 16 Number of SYSMONs T SOLE OT 1 100 Number of RPM macros 12 0 Average Fanout of Non Clock Nets 200 4 2 2 4 Resources used XCV5FX100T Below is a summary ISE14 3 of the resources used in the FPGA by the default firmware Standard SMT702 XCV5VFX100OT FPGA PXIe option Slice Logic Utilization Number of Slice Registers 16 120 out of 64 000 26 Number used as Flip Flops S H Number used as Latches Z Number used as Latch thrus 6 Number of Slice LUIS TE ut Or 64 000 20 Number used as logic 12 055 Out Of 64 000 183 Number using O6 output only 150720 cro Number using O5 output only 348 Number using O5 and Op 1 640 Number used as Memory 816 out of 19 840 4 Number used as Dual Port RAM 308 Number using O6 output only 204 Number using O5 output only Sek Number using O5 and O6 84 Number used as Shift Register 508 Number using 06 output only 50 7 Number using O5 and Op al Number used as exclusive route thru 42 Number of route thrus 441 Number using O6 output only 3099 Number using O5 output only 5E Number using O5 and Op Ji
33. Unit Module Description Dual 3 GHz PXIe ADC Module Unit Module Number SMT702 Issue Date 11 12 12 Original Author PhSR User Manual for SMT702 Sundance Multiprocessor Technology Ltd Chiltern House Waterside Chesham Bucks HPS 1PS This document is the property of Sundance and may not be copied nor communicated to a third party without prior written GC MANAGEMENT permission Sundance Multiprocessor Technology Limited 2006 Certificate Number FM 55022 Revision History Original Document released 12 09 08 PhSR DMA and system monitor added 30 01 09 PhSR information updated with FX70t part 6 Soft Reset added in he control register 14 07 10 nep Comment added on board modification ADC 27 07 10 PhSR reset NN Added FX100T version 11 12 12 Table of Contents 1 2 3 4 IHtFOGUCHOD EEN 7 EEN NR Ta Tata CN 8 2 1 Referenced Kee hun TE EE 8 Acronyms Abbreviations and Defid1iti0NS ccccccooonnnnnnnccnccananaaana conc rra rana rr 8 oc ACEON VIS GING A iodo 8 Functional DCS e E 9 Ze General PO 0 Ba Ai 9 4 2 Block Diagram Standard SMT702 PXIe conoonccccccccconccnaooccnnoconnnananaacnnrnnnnrnananaannnnnns 10 4 3 Block Diagram SMT702 HYBRPXI32 option 32 bit PXT 11 4 1 Block Diagram SMT702 CPCI32 Option 32 bit DCH ee 12 2 2 Module DESC ev Dh Ra ami uq OO He OO MEE DU EE 13 ADV 9 6 CS 13 AA EE 13 iar RE E t
34. VLX110T 3 fastest speed grade available FPGA and works as a Compact PCI Module The part number for this option is SMT702 CPCI32 Requires a Compact PCI rack Note that it can also be plugged into a PXI Express chassis such as the NI 10620 from National Instrument 4 SMT702 with an XC5VLX110T 3 fastest speed grade available FPGA and works in standalone It can be fitted in a PCI slot Can be PCI 32 or 64 or PCI X on a PC motherboard without being electrically connected to it This option requires an external power cable and a connection to an other piece of hardware from Sundance via SHB or RSL or SATA optional The part number for this option is SMT702 STANDALONE Note that the Standalone version of the SMT702 does not have any dual SATA connector 5 SMT702 with an XC5VFX70T 3 fastest speed grade available FPGA and works as a PXI Express Peripheral Module The part number for this option is SMT702 FX70T Requires a PXI Express chassis such as the NI 10620 from National Instrument 6 SMT702 with an XC5VFX70T 3 fastest speed grade available FPGA and works as a PXI Express Hybrid Peripheral Module PXI P1 connector The part number for this option is SMT702 HYBRPXI32 FX70T Requires a PXI Express chassis such as the NI 10620 from National Instrument 7 SMT702 with an XC5VFX70T 3 fastest speed grade available FPGA and works as a Compact PCI Module The part number for this option is SMT702 CPCI32 FX70T Requires a Compact PCI
35. Voltage Vccint Min 10 937 Y Max 11 00 Current 0 38 V Apply files per channel 6 Acquisitions Save captured data to Start Sh Restore Default Settings Apply Al FPGA Aux Voltage V ccaux Min 245V Max 247 V Curent 2 46 V Get Status I OO G SEA QQ 129 00 Channel A 2 128 00 Channel B gt 127 00 126 00 9 127 75 0 100 200 300 400 500 600 700 600 900 1000 1100 Samples Channel A Channel B 0 00 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 1 00 GHz Figure 21 SMT702 Demo application Parameters to configure the clock chip and dcm phase shifts can be loaded Hardware selection section example files are provided in Program Files SundanceNSMT7026NHost Smt702ConfigNCustom Parameters from a configuration file as well as the clock and reference source Samples can be stored into DDR2 memory played back stored into files and displayed into 2 graphs The first one shows the raw samples and the second the FFT of the captured samples 2048 points Each captured can be stored into individual files smt7002 cha txt or smt7002_chb txt and also a concatenated version of all captures made smt7002 total cha txt or smt7002 total chb txt In order to have the software source code for the SMT7002 the SMT7026 package will have to be purchased They come as a visual C project with all necessary files to recompile the application and modify it 8 Physical Properties Dimensions PXI
36. XI timing and synchronisation signals and XP3 x8 PCI Express and additional synchronisation signals The SMT702 dedicates 8 lanes to the PXI Express bus which gives an effective bandwidth per direction of 16Gb s It also implies core and user clocks to be 250 MHz Note that not all PXIe Express chassis and controller can handle 8 lanes on peripheral modules Currently only 1 and 4 lanes are supported The Express core developed by Sundance and based on Xlinks is able to achieve over 700Mbytes per second for a 4 lane core clocked at 250MHz and half of it when clocked at 125MHz The standard SMT702 can plug in any PXI Express Peripheral Slot or any PXI Express Hybrid Slot PXI Express chassis such as the NI 10620 from National Instrument or equivalent Reference clock selection is made on the board via a jumper J11 Position 1 2 selects the PXI reference clock 100Mhz provided by the PXI Express chassis Factory setting Position 2 3 selects the on board 250Mhz crystal K Figure 8 Standard SMT702 PXI Express Peripheral Module Optionally the module can be a 3U Hybrid Peripheral Slot Compatible PXI 1 Module which means it comes with two connectors XP4 PXI timing and synchronisation signals and P1 32 bit 33MHz PCI Signals This version of the SMT702 can only plug in a PXI Express Hybrid Slot PXI Express chassis such as the NI 10620 from National Instrument or equivalent Figure 9 SMT702 HYBRPXI32 opt Hybrid
37. an appropriate range of temperature when using the default firmware provided Nevertheless the board requires some forced cooling It is recommended to use a PXI 10620 chassis or equivalent from National instrument as it already integrates a built in cooling system Using slot blockers from National Instrument would improve even more the cooling capacity of the system In order to improve the heat dissipation is a system some slot blockers can be used from National Instrument which redirect the air flow of non used slots to where it is needed 4 2 2 2 Resources used XC5VLX110T Below is a summary ISE11 4 of the resources used in the FPGA by the default firmware Standard SMT702 XCV5VLX110T FPGA PXIe option Slice Logic Utilization Number of Slice Registers VO 2d E eS 221 Number used as Flip Flops 15 244 Number used as Latches 4 Number used as Latch thrus 6 Number of Slice LUTs 14 099 out Of 9120 16 Number used as logic dcs DUE i T LZ 16 Number uSing O6 output only a WE Number using O5 output only 295 Number using O5 and O6 14525 Number used as Memory 439 ouUt oLk 65920 2 Number used as Dual Port RAM 308 Number using O6 output only 204 Number using O5 output only 20 Number using O5 and Op 84 Number used as Shift Register Tor Number using O6 output only Tot Number used as exclusive route thru S0 Number of route thrus 95 Number using O6 output only LO Number using O5 output only 32 kenen L
38. ccupied Slices Ouod ou uu ail 200 55 Number of LUT Flip Flop pairs used d USE Number with an unused Flip Flop Sg Qo DUE OF T9052 19 Number with an unused LUT dace ENER Ot 9 052 37 Number of fully used LUT FF pairs Sw 24 OU Or Sus 42 Number of unigue control sets 821 Number of slice register sites lost to coHtrol ser restrictions l021 Out OE 44 S00 4 A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice A control set is a unique combination of clock reset set and enable signals for a registered element The Slice Logic Distribution report is not meaningful if the design is over mapped for a non slice resource or if Placement fails OVERMAPPING of BRAM resources should be ignored if the design is over mapped for a non BRAM resource or if placement fails IO Utilization Number ort bonded IOBSs 463 out of 640 12 Number of LOCed IOBs 463 out Of 463 100 LOB EID Elops 695 IOB Master Pads 1 IOB Slave Pads Number of bonded IPADs LO QUU Ot 50 20 Number of bonded OPADs O GUL OF OZ 25 Specific Feature Utilization Number of BlockRAM FIFO 36 OUL OF 148 25 Number using BlockRAM only LL Number using FIFO only 1 0 Total primitives used Number of 36k BlockRAM used Eh Number of 18k BlockRAM used d Number of 36k FIFO used 14 Number of 18k FIFO used Z Total Memory used KB 1 314 out of O 24 Number of BUFG BUFGCTRLs ZO OMS OT 32 78 Number used as BUFGs
39. deotoperanon O O O O OOOO O R o IT o REESEN o f o ergeet usine tne onboard enai o f mia OOOO Taa o O CI CEN ET Eo o CI EUR i TN Rane Rat OOOO Forces the FPGA to recalibrate its IOs This is required when the sampling clock of the ADCs has been changed MN SE SC SES Re External trigger selected Trig Input A Level high on the Trig Input is required to start an acquisition length of the pulse being at least 1 8 of the ADC sampling clock Bit 18 Description DDR2 read Enable DDR2 Memory read operation not enabled DDR2 memory read operation enabled meaning samples contained in DDR2 memory can be transferred to the host ONE NEN a NEN 9 o Normal Mode of Operation Resets Xlinks blocks usually used before starting an acquisition to clear Xlinks FIFOs BEEN o Normal Mode of Operation BEEN Keeps System Monitor circuitry in Reset Note 1 The on board reference clock is used by the on board clock generator which can only take reference clock within the range 5 80MHz Bit13 must be set for all reference reaching the chip above 80MHz 1 Description System Monitor Reset 1 4 3 1 2 3 Clear Control Register 0x20 write Same as Set Control Register 0x10 but used to clear individual register bits 4 3 1 2 4 Board Name and Version 0x24 read only HERE Offset 0x0400 Reset Register 0x24 read only aa Reas 024 edon e TRR aa Raes aa S TTT S
40. g E e et D EEN 13 4 2 2 2 Resources used XC5VLXT LOT s eeeeeee eene nnn ennenen 13 42 25 Resources used AC V DEX H O TTT 15 4 2 2 4 Resources used XCV5FXDLOOT s eceeeeee eene enn nenas 16 4 2 3 R es RT I elea N DT enean 18 goo VEER 19 O 20 4 2 6 Data samples path Data capture sn 21 Te PLEPI SS EE 22 22 0 5 LEE e et e EE 24 dos DOWOEOISSIDOU OE ME 24 ALOA HH tm 25 4 2 1 LIPXLEXpress Hybrid CONNECT Sesma 27 4 9 RA DO ii 28 AL CONTRE OIS E S RARA RARA 28 4o Lob A O O diesen denedeve d veduuc eue daaedeqedese Deux deve deducir dens 28 e E RE ERR eg en llei 31 4 3 1 2 1 General Control Register 0x8 read only 31 4 3 1 2 2 Set Control Register 0x10 WI pte is 34 4 3 1 2 3 Clear Control Register 0x20 write sese essen ennenen 36 4 3 1 2 4 Board Name and Version 0x24 read only 36 4 3 1 2 5 Firmware Version and Revision Numbers 0x40 read only 36 4 3 1 2 6 ADCA ADCO83000 Register Oxl Configuration Register E R A E 37 4 3 1 2 7 ADCA ADCO83000 Register 0x2 Offset Adjust 0x48 write and read 37 4 3 1 2 8 ADCA ADCO83000 Register 0x3 Full Scale Voltage Adjust AE CS Berg debas 38 4 3 1 2 9 ADCA ADCO83000 Register OxD Extended Clock Phase Adjust Fine 0x74 write and read 38 4 3 1 2 10 ADCA ADCO83000 Register OxE Extended Clock Phase Adjust Coarse 0x78 write and read
41. gn is organised DDR2 Memory BankA DDR2 Memory BankB 64 bit wide 64 bit wide 1Gbytes 250MHz 1Gbytes 250MHz 32 bit SHB Ref Out PXI Ref 10MHz PXle Ref 100MHz gt E MI Ext Ref 5 gt gt Ext Clk 4xlanes 4x8 bits 375MHz 4 PXle Lanes DDR LVDS Data amp Control 2 bit PXI SHB 4x8 bits 375MHz SMA connector on the front panel 1 Note that all blocks are control by the Register Block Command are received from the PXle bus and decoded 2 Samples are stored directly in the memory and played back to be sent over PXle RSL optionally SATA or optionally PCI Figure 13 Block Diagram FPGA Design standard Firmware 4 3 1 Control Registers The Control Registers drive the complete functionality of the SMT702 They are setup via the PXIe bus standard firmware provided The settings of the ADCs triggers clocks and the configuration of the RSL PXI interfaces optional SATA and the internal FPGA data path settings can be configured The data passed on to the SMT702 over the PXIe bus must conform to a certain packet structure and to specific addresses and offsets Only valid packets will be 4 3 1 1 Memory Map The write packets must contain the address where the data must be written to and the read packets must contain the address where the required data must be read The following figure shows the
42. he ADCs are 8 bit parts from National Semiconductor ADCO83000 On the SMT702 each ADC can achieve up to 3 GSPS in DDR mode Both ADCs are used in the extended mode For more information please refer to the ADCO83000 datasheet National Semiconductor This implies that they are configured using a Serial Interface implemented in the FPGA The typical Bit Error Rate BER of the ADCO83000 is 1075 Each ADC takes a DDR clock i e to achieve 3GSPS a clock of 1 5Ghz is required The ADCs can only work with a DDR clock within the range 500 1500MHz which means they can sample at a rate between 1 and 3 GSPS Both ADCs are AC coupled using an RF Transformer They have functionalities such as offset and scale adjustments as well as test pattern mode There is also calibration cycle that can be run once the system is in temperature The FPGA is able to synchronise the ADCs so they samples in phase The FPGA is able to return the phase shift between ADCA and ADCB to the host application by sampling their clock with its local clock and phase shifting it with a DCM 4 2 2 FPGA 4 2 2 1 General Description The FPGA fitted as standard on the SMT702 is part of the Virtex5 LXT family XC5VLX110T The package used if FFG1136 and the speed grade is 3 fastest part The SMT702 can also receive an FPGA from the Virtex5 FXT family XC5VFX70T and XC5VFX100T in the same package he FPGA is fitted with a heatsink coupled with a fan to keep it within
43. her in the process of locking or updating its phase shift Can be polled when one needs to reprogram phase shifts to make sure it is in the middle 1 of a cycle Setting Bit 9 Description ADCb DCM Busy Normal Mode of Operation The DCM is busy meaning either in the process of locking or updating its phase shift Can be polled when one needs to reprogram phase shifts to make sure it is not in the middle of a cycle Bit 13 Description DDR2 phy init done Memory Bank A Setting A problem occurred or Memory Bank A is kept in reset Normal Mode of Operation EN Ce A problem occurred or Memory Bank A is kept in reset 1 1 1 1 Bit 14 Description DDR2 lock status Memory Bank A 1 1 Normal Mode of Operation Setting Setting Bit 15 Description DDR2 fifo empty Memory Bank A N DDR2 fifo contains samples EE NE Fifo not ready Data should not be written 1 Normal Mode of Operation 1 Normal Mode of Operation Setting Description DDR2 phy init done Memory Bank B Description DDR2 Fifo Ready Memory Bank A 1 1 Normal Mode of Operation Bit 19 Description DDR2 lock status Memory Bank B BEEN o A problem occurred or Memory Bank B is kept in reset 1 Setting Description IDelay Control Ready Memory Bank A x A problem occurred or Memory Bank A is kept in reset 1 EE NI A problem occurred or Memory Bank B is kept in reset Reese OOOO O L o os mpg OOOO er FT o J Fitonotready
44. is to store bitstreams and to reboot dynamically the board The application is called Flash Utility e SMT 7002 is the software package that installs a demo application smt702 Configuration for the SMT702 as shown below 2 SMT702 0 Configuration HARDWARE SELECTION fe SMT702 C SMT702 2Ghz Platform CONFIGURATION STATUS 1 Power Supplies DCM ADC A Lock Status jw ADCA DCM ADC B Lock Status lv ADC B j I Clock Circi Apply Clock Chip Lock Status DDR2 Phy Init Done Bank A 2 Resets Do no auto clear DORZ Phy Init D Bank B ADCs v Init Done Bank B DCMS ADCs DDR2 Lock Status Bank A DDR2 Banks A and B DDR2 Lock Status Bank B iv SHB 1 DDR2 IDelay Control Ready Bank w SHB 2 mum DDR2 IDelay Control Ready Bank B DDR2 Empty Status Bank DDR2 Empty Status Bank B DDR2 Full Status Bank A DDR2 Full Status Bank B SMT 02 parameters selected D Board Name SMT 702 FPGA Type 110 PCB Revision 2 Firmware version def DEF Default Firmware Firmware revision 3 3 Serial Interfaces Reference clock circuitry e Backplane External Clock Circuitry G Onboard iv ADCA Testmodel iw ADCB Testmode iv ADCs Calibration 4 Shift Adjustment iv ADC A Shift Adjustment 400 FPGA Die temperatore ADC B Shift Adjustment 400 S Min Max Current C External XX XX XX XX XX X XX 5 DDR2 Memory iv Fill up DDR banks FPGA Core Voltage Vccint
45. izer LMX2531 register R12 Read back FPGA register Frequency Synthesizer LMX2531 register R12 0x108 ADCA DCM Phase Shift Reserved 0x10C ADCB DCM Phase shift Reserved 0x180 FPGA Die temperature thresholds System Monitor Read back FPGA die temperature measured 0x184 FPGA Core voltage thresholds System Monitor Read back FPGA Vccint Core Voltage measured 0x188 FPGA Aux voltage thresholds System Monitor Read back FPGA Vccaux Core Voltage measured 0x18C Reserved Amount of samples left to be read out out of DDR2 BankA 0x190 Reserved Amount of samples left to be read out out of DDR2 BankB Figure 14 Register Memory Map Note that ADC registers are write only ADC chips which means that the contents of the ADC registers can only be read back from the FPGA THe same applies to the Clock chip 4 3 1 2 Register Descriptions 4 3 1 2 1 General Control Register 0x8 read only WEN Offset 0x0400 General control EE Ox8 Read only EE ADCb synch ADCa synch System System System DDR2 Fifo DDR2 Fifo DDR2 Fifo reference reference Monitor Monitor Monitor Almost Almost Full state state Vccint Die Empty Empty Memory Vccaux alarm temperat Memory Memory Bank B alarm ure Bank B Bank A alarm DDR2 Fifo DDR2 Fifo DDR2 Fifo DDR2 DDR2 phy Ddr2 Fifo IDelay Full Ready empty lock init done Ready Control Memory Memory Memory status Memory Memory Ready Bank A Bank B Bank B Memory Bank B Bank A Mem
46. l PXI triggers and synchronisation signals The PCI core source core cannot be supplied by Sundance as the license held does not cover such use for it In case the user intends to recompile the source code or design his own firmware he would have to purchase a license for the core The SMT702 HYBRPXI32 can only be plugged into a PXI Express or CompactPCl Express rack Note that not all ressoures shown on the above diagram are implemented in the standard firmware 4 1 Block Diagram SMT702 CPCI32 Option 32 bit PCI DDR2 Memory BankA DDR2 Memory BankB 64 bit wide 64 bit wide 1Gbytes 250MHz 1Gbytes 250MHz 32 0 SUS Ref Out PXI Ref 10MHz 2xlanes Ext Ref Ext Clk 4xlanes 32 bit PXI G SMA connector on the front panel Figure 4 SMT702 CPCI32 Block Diagram 32 bit CPCI Option This option implements a 32 bit PCI core 33 Mhz Note that PXI trigger signals and reference clock 10Mhz are not accessible by the PFGA not available on a standard CPCI rack An external reference clock would have to be used or an external clock to feed the converter with The PCI core source core cannot be supplied by Sundance as the license held does not cover such use for it The SMT702 CPCI32 can be plugged in either a PXI CompactPCI or PXI Express rack Note that not all resources shown on the above diagram are implemented in the standard firmware 4 2 Module Description 4 2 1 ADCs
47. ogrc DristrriDUutrion Number of occupied Slices O02 Ome OL Lis 280 355 Number of LUT Flip Flop pairs used 19 9455 Number with an unused Flip Flop S769 QUE GE 9 943 193 Number with an unused LUT EE out Of 9 945 385 Number of fully used LUT FF pairs SOS QUE dt boy 945 42 Number of unigue control sets Dd Number of slice register sites lost LO gODntrol set restrictions dl GUL Or 6921120 2 A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice A control set is a unique combination of clock reset set and enable signals for a registered element Ihe Slice Logic Distribution report is not meaningful if the design is over mapped for a non slice resource or if Placement fails OVERMAPPING of BRAM resources should be ignored if the design is over mapped for a non BRAM resource or if placement fails IO Utilization Number of bonded IOBs 463 out of 640 12 Number of LOCed IOBs 461 out of 463 99 TOB tee Lopss 993 IOB Master Pads IOB Slave Pads d Number of bonded IPADs T OUT OL 50 20 Number of bonded OPADs D QUID Ok 32 25 Specific Feature Utilization Number of BlockRAM FIFO 39 Oui Of 148 25 Number using BlockRAM only zi Number using FIFO only 16 Total primitives used Number of 36k BlockRAM used ZA Number of 18k BlockRAM used Number of 36k FIFO used 14 Number of 18k FIFO used 2 Total Memory used KB Ly d out tr Du 3289 24 Number of BUFG BUFG
48. ons ftp ftp2 sundance com Pub documentation pdf files DOO0OO51S spec pdf 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations PXIe PXI Express SNR Signal to Noise Ratio It is expressed in dBs It is defined as the ratio of a signal power to the noise power corrupting the signal SINAD Signal to Noise Ratio plus Distorsion Same as SNR but includes harmonics too no DC component ENOB Effective Number Of Bits This is an alternative way of defining the Signal to Noise Ratio and Distorsion Ratio or SINAD This means that the ADC is equivalent to a perfect ADC of ENOB number of bits SEDR Spurious Free Dynamic Range It indicates in dB the ratio between the powers of the converted main signal and the greatest undesired spur 4 Functional Description 4 1 General Block Diagram Below is the general block diagram showing all resources available on the board Note that not all option are implement in the standard firmware DDR2 Memory BankA DDR2 Memory BankB 64 bit wide 64 bit wide 1Gbytes 250MHz 1Gbytes 250MHz 32 bit SHB Ref Out PXI Ref 10MHz PXle Ref 100MHz Ext Ref Ext Clk 2xlanes 4xlanes 8 PXle Lane 32 bit PXI SMA connector on G the front panel Figure 1 SMT702 General Block Diagram The following block diagram shows all three options The first option PXIe can be plugged into any PXI Express slot the second 32 bit PXI into any H
49. ory Bank B Bank A DDR2 Fifo DDR2 lock DDR2 ADCb ADCa ADCa ADCb empty status phy init calibrati calibration DCM Busy DCM Busy Memory Memory done on completed Bank A Bank A Memor complete y Pn d ADCB ADCb ADCa DCM Lock Clock Chip ADCB ADCA Programme M im DCM Lock Detect Programme Calibratio Calibratio Lock Status Clock nRunning n Running Status Chip Offset 0x0400 General control Register 0x8 Read only register Description ADCA Calibration Running Normal Mode of Operation ADCA not calibrating A calibration cycle lasts 14000 sampling clock cycles ADCA is busy running a Calibration cycle A calibration cycle lasts 14000 sampling clock cycles Nothing should be done while ADCa is in the middle of a calibration cycle Description ADCB Calibration Running Normal Mode of Operation ADCB not calibrating A calibration cycle lasts 14000 sampling clock cycles 1 1 ADCB is busy running a Calibration cycle A calibration cycle lasts 14000 sampling clock cycles Nothing should be done while ADCb is in the middle of a calibration cycle Description Clock chip programmed BEEN o Clock chip not yet programmed Clock chip has been programmed with all registers after an update request has been sent o o meo ip slo ference om mena vcor O o o Pavom OOOO O o o Pavom OOOO EN EN Ex Setting Bit 8 Description ADCa DCM Busy Setting Normal Mode of Operation The DCM is busy meaning eit
50. pF and C4 50pF Cl mm Im E we Image SSCS Km oo S O O Km foe Km foe Pew foe aR aaa anen OOOO E 1 TN CR OOOO OOOO O OOO OO OOOO ne som SSS Coe fomm o S ae menen oS meena ooo EM Reserved NN 1 2 3 BECH NM 4 3 1 2 25 Frequency Synthesizer LMX2531 Register R7 OxDC write and read otter os0400 Frequency Synthesizer 2531 Register R7 OC anda BENI Reserved XTLMAN 1 1 0 a XANH NN 79 mmm mmm Aem Detam mmm o mme MEE Offset 0x0400 Frequency Synthesizer LMX2531 Register R7 OxDC write and read Ep eee o oo ro e programmes os O OOOO 4 3 1 2 26 Frequency Synthesizer LMX2531 Register R8 OxEO write and read Offset 0x0400 Frequency Synthesizer LMX2531 Register R8 OxEO write and read 2 Reserved lt a 2 MEE Offset 0x0400 Frequency Synthesizer LMX2531 Register R8 OxEO write and read Manual crystal mode second adjustment XTLMAN2 9 o To be programmed with zeros 4 3 1 2 27 Frequency Synthesizer LMX2531 Register R9 OxE4 write and read T aan Frequency Synthesizer TEST Register RO ONES vr and read Eg es MEE Offset 0x0400 Frequency Synthesizer LMX2531 Register R9 OxE4 write and read ERR 9 o Should be programmed as above 4 3 1 2 28 Frequency Synthesizer LMX2531 Register R12 OxE8 write and read aarm Frequency Synthesizer UNXIT Register RI2 ONER Guri and read Eg a
51. quency Synthesizer LMX2531 Register R4 OxDO write and read Offset 0x0400 Frequency Synthesizer LMX2531 E R4 OxDO write and read Reserved ICPFL 3 0 NEN ICPFL 3 0 TOCT13 0 Default 00000000 o Offset 0x0400 Frequency Synthesizer LMX2531 Register R4 OxDO write and read 0x0 Timeout 0 Ox1 Timeout always enable 0x2 timeout 0 0x3 timeout 0 0x4 timeout 4x2 phase detector OX3FFF 16383x2 phase detector o Oso corresponds to OVA tate 13 and OXF State 610 14400A 90A per at 4 3 1 2 23 Frequency Synthesizer LMX2531 Register R5 OxD4 write and read Offset 0x0400 Frequency Synthesizer LMX2531 Register R5 OxD4 write and read amann Frequency Stee E rte and ead O EM A EN mw EN uM EN_PLLL EN VCOLD EN OSC EN VCO EN_PLL ME Default itv 30300 Frequency Synthesizer ANAZ531 Register RS OXDA write and read Eg aa OOOO R n OOOO o inier of o o iworo OOOO o O OOOO Eg o moea OOOO aaa All register set to the default values 4 3 1 2 24 Frequency Synthesizer LMX2531 Register R6 0xD8 write and read WEE Offset 0x0400 Frequency Synthesizer LMX2531 cae R6 0xD8 write and read EM NN Reserved XTLSEL 2 0 Default 00000 EN VCO_ACL SEL 3 0 EN LPF R4_ADJ 1 0 R4 ADI pL LTR Default BEEN ERR T UM ME oe we wr Offset 0x0400 Frequency Synthesizer LMX2531 Register R6 0xD8 write and read nl 0x0 C3 5O
52. rack Note that it can also be plugged into a PXI Express chassis such as the NI 10620 from National Instrument 8 SMT702 with an XC5VFX10OT 3 fastest speed grade available FPGA and works as a PXI Express Peripheral Module The part number for this option is SMT702 FX100T Requires a PXI Express chassis such as the NI 10620 from National Instrument 9 SMT702 with an XC5VFX100T 3 fastest speed grade available FPGA and works as a PXI Express Hybrid Peripheral Module PXI P1 connector The part number for this option is SMT702 HYBRPXI32 FX100T Requires a PXI Express chassis such as the NI 10620 from National Instrument 710 SMT702 with an XC5VEX100T 3 fastest speed grade available FPGA and works as a Compact PCI Module The part number for this option is SMT702 CPCI32 FX100T Requires a Compact PCI rack Note that it can also be plugged into a PXI Express chassis such as the NI 10620 from National Instrument Note that an SMT702 can also be used in a PC This will require a PXIe to PCIe adaptor Sundance part number SMT580 as show below The SMT580 only routes the PCI express lanes reference clock and power supplies None of the PXI signals are routed
53. set 0x0400 ADCA ADC083000 Register OxE Extended Clock Phase Adjust Coarse 0x78 write and read Fo sample loe one soon O OOO O O OOOO O a o steve ach LSB adds approximately 70ps of Clock Ads OOOO O o a o wa S 4 3 1 2 11 ADCA ADC083000 Register OxF Test Pattern register Ox7C write and read Offset 0x0400 ADCA ADCO83000 Register OxF Test Pattern Register 0x7C write and read Default T L 1 1 EL EN T 1 1 Default e pe dk T SE T E Bi M Offset 0x0400 ADCA ADCO83000 Register OxF Test Pattern Register 0x7C write and read Setting Description TPO Test Pattern Output Enable L w Normal mode of Operation All ADC outputs in Test Pattern mode 4 3 1 2 12 ADCB ADC083000 Register Ox1 Configuration Register 0x64 write and read 1 DRE RTD DCS DCP nDE Default dL dL NE AN dL WS q Default 7 7 je am 7 I si le SIT MEN Offset 0x0400 ADCB ADCO83000 Register Ox1 Configuration Register 0x84 write and read aaae OOOO O anes anana OOOO 1 buy cyte sabizer applica TE O OOOO O O BENE oe pase Arco TT o o fome OOOO Reduced output amplitude 510mV This setting is recommended on the SMt702 It reduces the overall noise on the board and therefore increases the performance of the ADCs Standard output amplitude 710mV Description OE Output Edge 9 o 1 4 Demux Mode DDR Mode must be Selected 1 2 Demux Mode DDR Mode must be selected 4 3 1 2 13 ADCB ADC
54. source The chip used is a National Semiconductor part LMX2531LO01500 The selection Internal External clock is made via a bit in the control register The same applies to the selection of the reference clock Note that the PLL VCO chip also has the possibility to output half of the fixed VCO frequency i e 1500 2 750MHz Below is a block diagram of the clock circuitry Ref Out PXle Ref 10MHz back plane PXle Ref 100MHz back plane Ext Ref Ext Clk G SMA connector on Note that all blocks are control by the Register Block Command are the front panel received from the PXIe bus and decoded Figure 6 Clock circuitry Block Diagram 4 2 6 Data samples path Data capture This section details how samples from the ADCs are being captured and stored By default and after a power up or reset operation all interfaces are in reset state The only exception is the PXI Express Interface Relevant interface should first be taken out of the initial reset state The next step is to program both ADCs and the clock generator and make sure it locked to a reference signal This is not needed in case of using an external sampling clock An ADC calibration cycle can be run ADCs are then ready to output samples and a clock to the FPGA Here are the details of the following step One Xilinx DCM per ADC clock is used inside the FPGA to ensure a good capture of data The status of these DCMs should be checked to make sure they are
55. st The following table shows the settings that can be used and the start addresses of the bitstream in the Flash memory Position Position Bitstream start Description Switch 2 Switch 1 address in flash ON ON 0x1800000 User Bitstream 2 Location 3 ON OFF 0x1000000 User Bitstream 1 Location 2 OFF ON 0x0800000 User bitstream 0 Default Location 1 selection OFF OFF 0x0000000 Default Location 0 bitstream Note that the CPLD routes the contents of the flash starting from the location selected SW1 until the FPGA indicates that it is configured Addresses are incremented by a counter that rolls over to O when the maximum address is reached For instance in the case where Location 1 is selected and a corrupted bitstream is loaded at that location or if there is no bitstream at that location the default bitstream will end up being loaded The default bitstream returns DEF as firmware version see register Firmware Version and Revision numbers It is recommended to keep the Switch SW1 so the User bitstream 0 is selected and store a custom user bitstream at Location 1 is needed The card would then boot from this location Otherwise the card would boot automatically from the default firmware Location 0 Storing a new bitstream using the SMT6002 first involves erasing the appropriate sectors before programming them with the bitstream This is automatically handled by the SMT6002 Storing a new bitstream at location 1 User Bit
56. stream 0 will only require from the user to select the file bit for instance and press the Comit button The advanced tab offers more options such as a full erase or a partial erase of the flash memory None of them should be required in normal mode of operation Note that a full erase will erase the entire contents of the flash including the default firmware and that it can take up to 3 4 minutes The partial erase will erase the User bitstreams only 4 2 4 DDR2 Memory Two banks of DDR2 memory are available on the SMT702 directly connected to the FPGA Interfaces are part of the default FPGA design Each bank is 64 bit wide and 128 Meg deep so each bank can store up to 1 Giga bytes or 8 bit ADC samples Each memory bank is dedicated to one ADC Both DDR2 interfaces are independent The type of memory fitted on the board can be clocked at a maximum or 333MHz In order to achieve storage real time of the ADC samples the DDR2 interface is clocked at 250MHz Default bitstream 4 2 5 Clock circuitry An on board PLL VCO chip ensures a stable fixed sampling frequency maximum rate i e 1500MHz in order for the board to be used as a digitiser without the need of external clock signal The PLL will be able to lock its internal VCO either on the 10MHz PXI reference or the 100MHz PXI express reference or on an external reference signal The sampling clock for the converters can be either coming from the PLL VCO chip or from an external
57. t to set the sign of the phase shit and 8 bit to set the value The phase shift range is 255 255 Once the control word of send the DCM is being reset and programmed with the new phase shift By default the shift register is set to O 4 3 1 2 31 System Monitor FPGA Die Temperatures 0x180 read Offset 0x0400 System Monitor FPGA Die Temperatures 0x180 read EEE O0 S o S SL nV LL SS S Lr IESU Reserved Maximum Die Temperature 9 4 EE Minimum Die Temperature 5 0 Current Die Temperature 9 8 08 Current Die Temperature 7 0 aan sytem Monitor FPGA Die Temperatures lt 0x180 ead E REESEN E A SETA E EE 4 3 1 2 32 System Monitor FPGA Die Temperature thresholds 0x180 write Offset 0x0400 System Monitor FPGA Die Temperature thresholds 0x180 write M EC dee Tempesti OT over resi Die Temperate upper ER 1 Die Temperature upper threshold 5 0 Die Temperature lower threshold 9 8 RETURN Die Temperature lower threshold 7 0 Offset 0400 system Monitor FPGA Die Temperature thresholds 0x180 rieh C etempntuciscokdn one A Tre remperaare ss code 10 Die Temperature lower threshold o The Temperature is coded on 10 bits 4 3 1 2 33 System Monitor FPGA Core Voltages Ox184 read O Dram System Monitor EPGA Core Voltages 0x184 read Reserved Maximum Vccint 9 4 R mmm Ww CO IN NT NN a System Monitor PGA Core Voltges 0x184 read Tee Ra RR OOOO OOO OOO O O OOOO
58. tored in DDR2 Bank A 0x18C read Bit 25 0 Amount of samples o Returns the amount of samples currently left to be transferred to the host 4 3 1 2 38 Amount of samples stored in DDR2 Bank B 0x190 write 1 raren Amount of samples stored in DDR2 Bank B 0190 read TO mm on Amount of samples Offset 0x0400 Amount of samples stored in DDR2 Bank B 0x190 read Bit 25 0 Amount of samples 9 Returns the amount of samples currently left to be transferred to the host 4 3 2 System Monitor Virtex 5 FPGAs implement a function block called System Monitor Xilinx It allows the user to monitor the FPGA Die temperature the FPGA core voltage Vccint and the Auxiliary voltage Vccaux It also provides the minimum and maximum values measured since a system monitor reset has been applied The SMT702 firmware implements a state machine that collects minimum maximum and current readings for the die temperature Vccint and Vccaux They are all accessible 4 3 3 External Signal characteristics The main characteristics of all external signals of the SMT702 are gathered into the following table Analogue Inputs AC coupled option 600 or 800mV AC coupled via Input voltage range RF transformer 500 ADC bandwidth 3 Ghz ADC datasheet Impedance Bandwidth External Reference Input External Sampling Clock Input External Trigger Inputs Input Voltage Level 1 5 3 3 Volts peak to peak D
59. ybrid PXI Express slot and the third can go in any CPCI system 4 2 Block Diagram Standard SMT702 PXIe DDR2 Memory BankA 64 bit wide 1Gbytes 250MHz DDR2 Memory BankB 64 bit wide 1Gbytes 250MHz Ref Out PXle Ref 100MHz Ext Ref Ext Clk G SMA connector on the front panel 32 pi SUS 2xlanes 4xlanes 8 PXIe Lane 32 bit SHB Figure 2 SMT702 Block Diagram Standard SMT702 PXI Express This option implements a PCI Express Endpoint core Xilinx based on 4 lanes It can support up to 8 lanes or only one The FPGA also has accesses to all PXI triggers and synchronisation signals In case the user has in mind to recompile change the firmware the PCI Express Core is free and provided by Xilinx A free license locked on a PC MAC key has to be requested The SMT702 PXIe version can only be plugged into a PXI Express or CompactPCI Express Rack Note that not all resources are implemented in the standard FPGA firmware 4 3 Block Diagram SMT702 HYBRPXI32 option 32 bit PXI DDR2 Memory BankA DDR2 Memory BankB 64 bit wide 64 bit wide 1Gbytes 250MHz 1Gbytes 250MHz w SHB 320 Ref Out PXI Ref 10MHz 2xlanes Ext Ref Ext CIk 4xlanes 32 bit PXI S Figure 3 SMT702 Block Diagram 32 bit PXI Option This option implements a 32 bit PCI core 33 Mhz The FPGA also has accesses to al
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