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1. Id 4 x44 e Select File gt Save You are prompted to select the bus delimiter type window will open Select synplify VHDL exemplar default and click OK e Close PACE Bus Delimiter m Select ID Bus Delimiter C XST Default lt gt C ST Optional Sunplify Verilog Default f Synplify HDL Exemplar Default _ Don t show this dialog again can be set through preferences dialog Cancel Help Step 8 Implementing the Design e Select the object_beh source file in the Sources window 92 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams e Double click the Implement Design process in the Processes tab e Notice that after Implementation is complete the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings Step 9 Download Design to the Spartan 3 Advance Development Board This is the last step in the design verification process e Connect the 9V AC DC power cable to the power input on the advance development board J1 e Connect the download cable between the PC and development board J4 e Select Synthesis Implementation from the drop down list in the Sources window e Select object beh in the Sources window e Inthe Processes window click the sign to expand the Generate Programming File process
2. Let us we will see source code for Four Digit 7 segment LED display to configure in Spartan 3 FPGA with synthesis and implementation Step 1 copy the above source code and paste it in project window in ISE 8 1i as shown below i Xilinx ISE E lifting based _dsp seg seg ise Untitled1 B File Edit view Project Source Process Window Help DeA HA LBA FFU BHRARAIAD ANa 23x BR OO 9i vj t B Inch CHP 4ex z 47 amp 7 amp 25 X u S b p i000 iwE ns E Sources 3 Engineer Sources for Synthesis Implementatic w 4 T Er SJ 7seg 5 Create Date 12 06 23 07 20 2008 3 xc3s200 4tq1 44 eo eat gn Name l I Hodule Name 7SEGCOUNTER Behavioral 8 Project Name 7 SEG DISPLAY THE COUNTER 9 Target Devices 10 Tool versions Erg Sources eS Snapshots gt is Description T 13 Dependencies 14 Processes 15 Revision D3 Add Existing Source 16 Revision 0 01 File Created 7 Create New Source 17 Additional Comments 3 Design Utilities 18 library ieee LIBRARY DECLARATION 19 use ieee std logic_1164 all 20 use ieee std logic arith all 21 use ieee std logic unsigned all 22 23 entity object co is Entity name is object counter 24 25 port clk in std logic to give delay in counting 26 y out std _ logic_vector 7 downto 0 8 LED output eu sel out std logic vector 3 downto 0 select the 4 digi
3. Uncomment the following library declaration if TLE LOU IL SHE T 005 ein lt a lick primitive So ibe las Cocke ibrary UONE IM 05e UNIS IM VComponents all entity seven_seg is porq le Eye E SECO sel Ole e ro logis t weoien or cowace 9 s A Boc Dh coupe Ce end seven seg architecture Behavioral of seven seg is STGNA gor ox ou xdv a oy oy eH IBIEOIS TEE begin Seal lt usd er ed S MTS od Dat X0 I3 AND NOT ZPO STESSO POINTS Xl1 JE O CASH NOME AND NOT TITAND TO X2 lt I3 AND NOT AND TIF AND NOT TO X3 lt I3 AND NOT AND I1 AND IQ X4 lt Ley IND SANZ NOT TI AND NOT TO Xb TAND T NGM JETE AINE ILO X6 lt T gt AND STA TITAND NOT 0 lt 7 lt NO SS AND SZ HL END LO 2o c T gt AND NOT T72 NOT TI AND NOT TO ILS AND NOTT INOW JE TESTE EI CIE Z Z Q ml m NN NN A M AM AM AM AAM AMM X OR X4 M DEDE Kae Xd OR XA OR X9 xb OI co oes OR X5 OR X7 OR X9 XI OR X2 OR OR X7 X0 OR XI OR end Behavioral 59 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEMENTATION OF 7 SEGMENT DECODER BY LUT Description Develop a 7 segment decoder using Look up table Describe the seven segment decoder in VHDL using developed Look up table A seven segment display is connected to the output of the circuit Four switches are connected to the input The 4 bit input is decoded into 7 segment equivalent Flow Cha
4. Look in 9 C tutorial ic wal counter bit IMPACT Process Operations O isim tmp_save y templates x PROGRESS END Er ff BATCH CHD liil Output Eror Warning Cancel All File type All Design Files 7 bit rbt inky tec bed Transcript e If you get a Warning message click OK e Select Bypass to skip any remaining devices e Right click on the xc3s200 device image and select Program The Programming Properties dialog box opens e Click OK to program the device When programming is complete the Program Succeeded message is displayed Program Succeeded On the board 4 Digits 7 SEG indicating that the counter is running e Close iMPACT without saving 94 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams
5. in your source files You can check for errors in the Console tab of the Transcript window If you continue without valid syntax you will not be able to simulate or synthesize your design Step 7 Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan 3 Advance development board To constrain the design ports to package pins do the following before that refer the chapter 4 for giving the pin location e Verify that object_co is selected in the Sources window e Double click the Assign Package Pins process found in the User Constraints process group The Xilinx Pin out and Area Constraints Editor PACE opens e Select the Package View tab e Inthe Design Object List window enter a pin location for each pin in the Loc column using the chapter 4 refer page number 9 91 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams E Xilinx PACE E Mifting based_dsp sep object_co ucf File Edit View IOBs Areas Tools Window Help Os Mo oa tea Rees A4nmeprs KAaH ae Design Browser See Device Architecture for xc3s200 4 tq144 Sy 1 0 Ping 1 Global Logic E Logic bject List I O Pi Output Output Output Output Output Output M Output BE Output By Output y Output Bib Output Br Dutput
6. moie etr on ESO OF Ou Stes loge Vector ton UE end demultiplexer architecture data of demultiplexer is O D Q H 3 not s0 Vand nor s 1 anc nous 2 9 s 0 anc notr s1 and nort s 2 now s 0 anc s 1 ano notr s 2 s 0 and s 1 and not es S not s OU anc not s 1 and s 2 2 s 0 and nor s1 and 20 not s 0 and s il anai s 2 3 s 0 sand s 1 and s 2s OOOCOCO SO CH E ELE C EE E 51 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We put enable as high in all condition and here we give input 010 in selection line according to that selection line we get output End Time 1000 ns iul e E pX s 0 2 il stu al stt i sci aX v 7 Output Waveform We get output in simulation window according to that selection line Now 1000 ns el e ex s 0 2 El iX v 0 7 SEW ey stt el v ey v3 ey via ey ys ey vt evt alaj ajl aj ajl aj A 52 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEMENTATION OF MULTIPLEXER Description Describe the code for a multiplexer and implement it in FPGA kit in which switches are connected for select input and for data inputs a LED is connected to the output Flow Chart Read A B SELECT amp ENABLE 53 PAntzECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M
7. next full adder Initial carry in Sum Final Carry out 32 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Full Adder The full adder circuit adds three one bit binary numbers Cin A B and outputs two one bit binary numbers a sum S and a carry Cout Cout Flow Chart 33 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity adder is Port x in STD LOGIC VECTOR 3 downto 0 y in STD LOGIC VECTOR 3 downto 0 cin in STD LOGIC sum out STD LOGIC VECTOR 3 downto 0 cout out STD LOGIC end adder architecture Behavioral of adder is component fulladder port x y cin in std logic sum cout out std logic end component signal c std logic vector 2 downto 0 begin in sum 0 c 0 0 sum 1 c 1 1 sum 2 c 2 2 sum 3 cout a2 fulladder port map a3 fulladder port map Exe ule Eu nl O O A OC end Behavioral library ieee use ieee std logic 1164 all entity fulladder is port x y cin in std logic sum cout out std logic end fulladder architecture comb of fulladder is begin sum lt x xor y xor cin cout lt x and y or cin and x xor y end comb b 34 PANTECE SOLUTIONS www pantechsolutions net
8. that deflect electron beams to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As shown in below figure information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass The size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated determine the display resolution Modern VGA displays support multiple display resolutions and the VGA controller indicates the resolution by producing timing signals to control the raster patterns The controller produces TTL level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the 16 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams pixel 0 623 G40 pixels are displayed each time the beam traverses the screen VGA Display Retrace No Current information through the horizontal defection cail pixel 478 0 pixel 478 538 is displayed during th
9. 1 mux Flow chart 44 PARntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing 2 1 multiplexer program Geren TERE D use IEEE STD LOGIC 1164 ALL ise TEER gt IPT COCIOC eSI TH ACL Use Is cle SIND LOGIC SUIS TONED ACE EU menie shi Tol ovind library declara ion If ISIN Sd IMs ub chi ahi Z aN aaa Tollit deve SUE IEIDP Megs Mexerele suse AMNES Use TUNES IM Commons s or entity mux is POE es hie ol DE LOGE Ve es LOG le sel in SID LOGIC i oe ES SPT TOCIL end mux architecture Behavioral of mux as begin process x y sel begin if sel 0 then Z elsif sel 1 then Z end 1f end process 45 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 8 1 mux port map program liprary IEEE use IEEE STD_LOGIC_1164 AL1L USC TEER o IDECOCIC ARITH ALE ise eld TODE JOG IE C TUN TONED ACE Une omen ne following library declaration 1i Instan rating a a la n aee DIOE IE QUIE oode e 05 UE S use UNISIM VComponents all entity multiplexer is Benian i ay One cec nas aa DDSEooPC T CO lye I bs ese oe Ibo cule za OUL SD TOCIT end multiplexer architecture Behavioral of multiplexer is Comoe aie lex Porr Ken Edl dee ake yon E RO Gre sel inm std Logic z oUt o Ed logie end component Sup d zd Sd ME Eco ncm c begin Sugmce iuo uo
10. ALL usce TEER SUDO CIE use IEEE STD LOGIC UNSIGNED ALL eneit tiro Is Porra o ee nu omo LED TOURS SUC LoogLe end first architecture Behavioral of first is begin process clock variable i integer 0 begin gu cM event wane me lee e e up lt 500000007 chen IM eee acl Sa alle gD lt Qu elon S00CO00 OR 0 wie 1590010100918 Ti Eq ly LED lt 1 elsif 1 100000000 then 1 0 ence it enc end process end Behavioral 70 PANTECE SOLUTIONS www pantechsolutions net Technology Beyond the Dreams K scheme VLSI Lab M anual SIM ULATE A VHDL TEST BENCH CODE FOR TESTING A GATE Description Develop a VHDL test bench code for testing any one of the simple gate Simulate the test bench code in the HDL software Flow Chart START Menem me m a a atana a m a a n a a n n m a a a a a n asas aa eee A aE anA aE aan SET input clock Delay for 1sec dE NN 71 PAnteECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing AND gate program desee COEIBUE UE use IEEE STD LOGIC 1164 ALLI Visi TEER OIDTLCOCTC ANE IE ATI ALL Se TEEL e IID WONG TRES T UNSTOCNED ALLE entity gate is Rois a in SID LOGIC D in oD LOGIC Ce Ole TOIDE OCTO end gate architecture Behavioral of gate is begin C lt a and D end Behavioral 72 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anua
11. C D A B C D A B C D A B C D A B C D 28 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Flow Chart 29 PANTECK SOLUTIONS Technology Beyond the Dreams SET input A SET input B SET input C SET input D Output Y End www pantechsolutions net K scheme VLSI Lab M anual Code Listing 30 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input a high in waveform window End Time 1000 ns 50 ns 150 ns 250 ns 350 ns 450 ns 550 ns 650 ns 750 ns 850 ns 950 ns ala Output waveform Finally we get output in simulation window y high according to that POS Equation Now 1000 ns dla alb ic ond oly 31 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams SIMULATION OF VHDL CODE FOR ARITHMETIC CIRCUITS Description Design and Develop the circuit for the following arithmetic function in VHDL Codes and Simulate it Addition Subtraction Multiplication 4 x 4 bits 2 1 Addition Program for 4 bit addition using 4 bit Ripple adder It is possible to create a logical circuit using multiple full adders to add N bit numbers Each full adder inputs a Cin which is the Cou of the previous adder This kind of adder 1s called a ripple carry adder since each carry bit ripples to the
12. LEDs connected with port pins details tabulated below the cathode of each LED connects to ground via a 2200 resistor To light an individual LED drive the associated FPGA control signal to High SPARTAN3 Point LED LED Selection H1 330E mw 9 9n M ake Pin Low LED OFF 10 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 6 2 Digital Inputs e This is another simple interface of 8 Nos of slide switch mainly used to give an input to the port lines and for some control applications also e The FPGASP3 KIT slide switches SW3 SW10 directly connected with FPGA 1 0 lines details tabulated below user can give logical inputs high through slide switches The switches are connected to 43 3V in order to detect a switch state by default lines are pull downed through resistors The switches typically exhibit about 2 ms of mechanical bounce and there is no active de bouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board A 10KO series resistor provides nominal input protection Slide SPARTAN3 M ake Switch Close High M ake Switch Open Low 11 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 6 3 RS 232 Communication USART USART stands for Universal Synchronous Asynchronous Receiver Transmitter FPGASP3 Kit provides an RS232 port that
13. LUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description Q 3 Q 2 Q 1 Q 0 PGIDC PSS Pee POT P98 POS PIU Code Listing POr cueva cH B E OC use IEEE STD LOGIC LITO64 ALLDL ote Malls SIND HOI TE ARTIE ALE oreet 5 SII IOI TE C INS IGN cen e entity first 1s a ena ais e a ae e S INS oeer oe oce q Toute cue ios e uei od oet O end Prset archite tore Behavioral ot fest 1s signal tmp Ed logic vector gt downto 0 5 0000 begin PLOS OOk csr variable i integer 0 begin IE rS v pe icio esse OGIO Oe elsif clock event and clock IE hk 0000000 wae 1 2 4 4 1 elsif i 50000001 then 1 0 tmp pet TUTO ie LE quis process tmp Behavioral 76 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEMENTATION OF A SPELLER WITH AN ARRAY OF LEDS Description Design and develop VHDL Code for a 5 bit Johnson ring counter 4 bit The LEDs are connected at the output of the counter The speller should work for every one seconds Flow Chart ON Enable Clock Value incerse In ring order PIN Description FPGA P55 P86 P97 P98 100 P102 LOC 77 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Johnson Ring Counter CODE Listing library IEE use IEEE STD LOGIC lied ALD
14. PSTYRO FPGASP3 SPARTANS Starter Kit Hardware amp Software User M anual 1 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Contents Ls AOU O seb oxistis into De DU EIER De baba n asl ete mam NIE 3 UBI CNS ea RE 3 L2 TScnnical or Customer SUDDOFPL ossis ni ES EPOR EDS DIE DIE 3 2 Ke eyComponents and aU 65cm mgr chc TENEN AEE EENS ESEE NREN EE ENOR PRIME ceu 4 2 1 General Block Diagram cccsscsesssscssrscsesseserscsessesersssesansenesarsensseesansereseesarsceesarsarsseesarsenssansensenesansenseaeys 5 3 JUMPE DE cere aco cee p 6 4 Connector Details ssseseeeeeeeneeennennnnnnnnee nennen nennen nn nn nnne niii nn nnn 7 Se POWT UDN aeons rr ee ee er eee 8 b SOM Oa Peripheral sessin E IIO UD DD EO ROI M UM UIN ME UU 9 6 1 Light Emitting DIOGGS aesosestibivimenitrixiix PresVretit eis bud mcenia Fir Ft bv doen eu pote bru rig 10 5 2 e IOUS IDIBUS starsat E ote ote axe nini ud pde E NU RUERUn Er eIU PIS ERU QI DIR indi n T FERE NE 11 6 3 RS 232 Communication USART ssseeseeeeeeeennnennnnnennnnnnnnn nnne nnne nnn nnn nnn 12 6 4 TAGPO aM E aire a eu oru C ro Fo Gaul eR lc n ces OR cel b cor RED End a 13 oho teg Ce s 010 6 E 14 COEN GAIET EE 0 TOUT 15 SM ELS ue PA pis NIS d MERE NR 18 7 Boa yO caste tens epee persed dp ieIDIOE hdi VIDEOR NR E ND IM 21 8 VLSI Lab EXO CriMents ccc
15. SOLUTIONS Technology Beyond the Dreams SET input A SET input B SET input C SET input D Output Y End www pantechsolutions net K scheme VLSI Lab M anual Code Listing 26 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input a high in waveform window End Time 1000 ns 50 ns 150 ns 250 ns 350 ns 450 ns 550 ns 550 ns 750 ns 850 ns 950 ns ala alb alc a d ly Output waveform Finally we get output in simulation window y high according to that SOP Equation Now 1000 ns dla alb ic aa to LE 27 PAnteCF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR COM BINATIONAL CIRCUIT Product of Sum Description Optimize a 4 variable combinational function POS describe it in VHDL code and Simulate it Example F 0 5 8 9 12 in POS Truth Table for Product of Sum Simplification A IB IC ID Y Product of Sum LM oO A B C D o A B C D o UN o uj o o A B C D m A B C D l I 0 A B C D 0 A B C D l d p I 0 A B 4C D 0 A B C D i 1 o 1 0 A BSCHD a I JO 0 A B C D 1 I 1 I 0 A B C D_ EN Y A B C D A B C D A B C D A B C D A B C D A B C D A B
16. SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 9 Getting Started with Xilinx ISE Starting the ISE 8 1 software To start ISE double click the desktop icon Or start ISE from the start menu by selecting Start gt All Programs gt Xilinx ISE 8 1i gt Project Navigator ES Xilinx ISE File Edit View Project Source Process Window Help DAHA SO GFE SRARAAD 4Vix aR oem mm v uH meh e No project is open File gt Open Project or File gt New Project Bi Sources fS Snapshots A No flow available E A Find in Files Enors fy Wamings Create a New Project Create a new ISE project which will target the FPGA device on the Spartan 3 FPGASP3 Kit 83 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams To create a new project 1 Select File gt New Project The New Project Wizard appears 2 Type tutorial in the Project Name field 3 Enter or browse to a location directory path for the new project A tutorial subdirectory is created automatically 4 Verify that HDL is selected from the Top Level Source Type list ES New Project Wizard Create New Project Enter a Mame and Location for the Project Project Name Project Location Se en Select the Type of Top Level Source for the Project Top Level Source Type HOL v 5 Click N
17. Technology Beyond the Dreams K scheme VLSI Lab M anual Input Wave form We give input xz 1 yz 1 and cinz l in waveform window End Time 1000 ns 150 ns A ns a ns i ns al ns 650 ns a ns i ns m ns iul cin AN cout Bo qa B vI3 0 qe sum 3 0 Output Wave form We give input x 1 y 1 and cinz so we get sum 3 waveform window Now 1000 ns t x 3 0 t v 3 0 el cin i sum 3 0 el cout 35 PAntzCF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 2 2 Subtraction Program for 4 bit subtraction using arithmetic operator It is possible to create a logical circuit using multiple full subtractor to subtract N bit numbers Each full subtractor inputs a Bin which is the Bout of the previous subtractor This kind of subtractor is called a ripple carry subtractor since each Borrow bit ripples to the next full subtractor B3 B7 B1 BO Single connection suae between subtractors so if for e g AO BO 0 1 B out B out B out B out then F50 can borrow from F51 via this connection but cannot D3 D2 D1 DO borrow from FS if A1 also happens to be 0 Full Subtractor A combinational circuit which performs the subtraction of three input bits is called full subtractor The three input bits include two significant bits and a previous borrow bit 36 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Techn
18. Use shh Eo iD TO AEG ARTIN ALL Uist TETUR ER e SDy HOG IC WINS TONED ACE entity first is ene eel EU TE pol keene Reset unm std logic Output out std logic vector 4 downto 0 end first architecture Behavioral of first ws signal temp std logic vecror 4 downto 0 00000 begin process clk Reset variable i k integer 0 begin if Reset 1 then temp lt 5000007 elsif clk event and clk It oh lt 5018181810 00 8 aiken ees ELS 50000000 then temp 0 Cop Dr temp 2 templo not temp 4 end process Rese Mu End Behavioral 78 PAnctECF SOLUTIONS www pantechsolutions net Technology Beyond the Dreams K scheme VLSI Lab M anual VHDL IM PLEMENTATION OF 7 SEGMENT DISPLAY Description Design and develop a seven segment decoder in VHDL Design and develop a 4 bit BCD counter the output of the counter is given to seven segment decoder A seven segment display is connected to the output of the decoder The display shows 0 1 2 9 for every one second Flow Chart C sart 0 E T OST R Enable Digit Selection Digit1 Digit6 Display Message 000000 FFFFFF PIN Description CLK Y 0 Y 1 79 PAnteECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams P12 P13 P14 P15 P17 P18 P20 P21 Code Lisitng library ieee use ieee std logic 1164 a11 use ieee std logic arith all use ieee
19. anual Technology Beyond the Dreams PIN Description worm A 8 t DSO su OUTPUT FPGA LOC P87 P89 P0 P92 P93 P105 Code Listing library ieee use ieee std_logic_1164 all use wecetstd logic arith all use ieee std logic unsigned all erp Uc cs pore 4 8 DERNEDE SEG in STD_LOGIC_vector 1 downto Output 2 OUE STD LOGIC end mux_gate architecture behav of mux_gate is begin process SEL A BCD begin Gase ET is when QO gt Output when 01 gt Output when 10 gt Output when 11 gt Output when others gt null ene Case end process end behave 54 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEM ENTATION OF DEM ULTIPLEXER Description Switches are connected for select inputs and a data input Eight LEDs are connected to the output of the circuit Flow Chart When A amp B 0 IN zOutO When A z 0 amp B z 1 IN zOutl WhenA z 1 amp B z 0 IN Out2 WhenA 1 amp B 1 IN Out3 io SE 55 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description FPGRIOC Pes PET WB Poo Por P98 Poe P100 P102 PIOS PID PIOS Code Listing library ieee use ieee std logic 1164 al1l entity demultiplexer is port le 3 in sca Logic s 3 in sco logie vector 0 to 2 y 3 out sto logic vector 0
20. arithmetic circuits simulation of VHDL code for multiplexer simulation of VHDL code for Demultiplexer VHDL implementation of multiplexer VHDL implementation of Demultiplexer VHDL implementation of 7 segment decoder VHDL implementation of 7 segment decoder by LUT VHDL implementation of encoder simulation of VHDL code for delay VHDL implementation for blinking a led simulate a VHDL test bench code for testing a gate VHDL implementation for blinking a array of LED VHDL implementation of a speller with an array of LED VHDL implementation of 7 segment display 23 PANTECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR COM BINATIONAL CIRCUIT Sum of Product Description Optimize a 4 variable combinational function SOP or POS describe it in VHDL code and Simulate it Example F 0 5 8 9 12 in sop Truth Table for Sum of Product Simplification A B C D _ __ SumofProduct _ CECH SCEE O C o 0 O 1 ABCD o O0 1 1 ABC a joii joo H0 1 ft fo J LL H E u M Oo Boolean Expression Y A B C D A BC D AB C D AB C D ABC D Y B C D A A C A BD AB D ABD Y B C D A BC D AB C D ABC D 24 PANTECR SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Flow Chart 25 PANTECE
21. b M anual Technology Beyond the Dreams 2 Key Components and Features e 200 000 gate Xilinx Spartan 3 FPGA in a 144 TQFP XC3S200 4TQG144C 4 320 logic cell equivalents Twelve 18K bit block RAM s 216K bits Twelve 18x18 hardware multipliers Four Digital Clock Managers DCM s Up to 97 user defined I O signals e 3 bit 8 color VGA display port e RS 232 Serial Port DB9 9 pin male connector with RS 232 transceiver level translator Uses straight through serial cable to connect PC or workstation serial port e PS 2 connector for mouse keyboard interface port e 8Nos Slide Switches for digital inputs e 8nos of Point LEDs for Digital outputs e bOMHzcrystal oscillator clock source e 3Nos 20 pin l o connector for interface external peripherals modules e 40 pin Expansion connector for interface additional i o modules e JTAG port for download user program through cable e 9V AC DC power input through adapter e Power on indicator LED e On board 5V 3 3V 2 5V and 1 2V regulators 4 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 2 1 General Block Diagram 9V Input JTAG 45V 3 3V 1 2V Port USB UART Power Supply Serial Comm 40Pin Expansion 3 bit 8 color Connector VGA Interface PS 2 8 Nos LED Digital Outputs XC3S200 3 Nos 20 pin connector 8 Slide Switch Digital Outputs 5 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Techno
22. can be driven by the Spartan 3 FPGA A subset of the RS232 signals is used on the Spartan 3 kit to implement this interface RxD and TxD signals e RS 232 communication enables point to point data transfer It is commonly used in data acquisition applications for the transfer of data between the microcontroller FPGA and a PC e The voltage levels of a FPGA and PC are not directly compatible with those of RS 232 a level transition buffer such as MAX3232 be used UART SPARTAN3 Serial Port Section SPARTAN3 12 PANTECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 6 4 JTAG Programmer The FPGASP3 Kit includes a JTAG programming and debugging chain Pantech JTAG3 low cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header DB 25 parallel port connector to 6 pin female header connector The JTAG cable connect directly to the parallel port of a PC and to a standard 6 pin JTAG programming header in the kit can program a devices that have a JTAG voltage of 1 8V or greater 6 Pin SPARTAN3 UM JTAG Signals EN sinu nes JTAG Cable III P111 NAH 9 79 os 5 RR ow p p re The Pantech low cost parallel port to JTAG cable fits directly over the header stake pins as shown in above figure When properly fitted the cable is perpendicular to the board Make sure that the signals at the end of the J TAG cable align with the labels listed on the board T
23. cscserserssscserscsessrserscseserscssseesersceesensersseesenserseeesenseas Error Bookmark not defined 9 Getting Started with Xilinx ISE ccccsecsscssscssrssrecsrssrsssesersersssesrsereverserssensersenesenseresensarsseeserserssensarssnesansensses 03 2 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 1 Introduction Thank you for purchasing the Xilinx Spartan 3 Evaluation Kit You will find it useful in developing your Spartan 3 FPGA application FPGASP3 Kit STK is an exclusive general purpose kit for the SPARTAN family The intention of the design is to endorse the engineers and scholars to exercise and explore the capabilities of FPGA architectures with many interfacing modules on board point LEDs Slide switches UART VGA and PS 2 with ease to create a stand alone versatile test platform 1 1 Packages e Spartan3 Starter Kit XC3S200 Serial Port Cable e JTAG Programming Cable e Printed User Manual e CDcontains o Software Programmers ISE o Example Programs o User Manual 1 2 Technical or Customer Support E mail questions to support pantechsolutions net Send questions by mail to Pantech Solutions Pvt Ltd 151 34 M ambalam High Road Sri Ranga Building T Nagar Chennai 600 017 Tamilnadu India Phone 91 44 4260 6470 Fax 391 44 4260 6350 Website www pantechsolutions net 3 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI La
24. e VLSI Lab M anual Technology Beyond the Dreams 6 7 PS 2 Interface The FPGASP3 Kit includes a PS 2 port and the standard 6 pin mini DIN connector labeled U11 on the board User can connect PS 2 Devices like keyboard mouse to the FPGASP3 KIT PS 2 s DATA P8 and CLK P10 lines connected to SPARTAN3 FPGA I O Lines 6PIN MINI PS 2 ESAE PS 2 PORT SELECT Connector FPGA Lines n Tek T E Edge 0 eus CK Edge 10 PS 2 keyboard connector MINI DIN6 de F CLK PS2C Connector Pin Purpose T Pin 1 KBDAT data Tsy Li HLD Pin 2 not used DATA PS2D LEY A Pin 3 GND Pin4 VCC 45V AM Pin5 KBDCLK clock 1 stop bit Pin 6 not used O start bit 1ouse connector pinout is identical to PS 2 keyboard Both a PC mouse and keyboard use the two wire PS 2 serial bus to communicate with a host device the Spartan 3 FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start stop and odd parity bit However the data packets are organized differently for a mouse and keyboard Furthermore the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the Keyboard The PS 2 bus timing appears as shown in above figure The clock and data signals are only driven when data transfers occur otherwise they are held in the idle state at logic High The timing defines signa
25. equivalent for the corresponding input switch will be glowing in the LED as output Logical Diagram 63 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Flow Chart ncn nonnonn nanan tie SS SII NSS NS SS NS SSNS RS NNN SSS SSN Read input lines 64 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description PINS ex III IL IL LI LIE IE LOC Code Listing library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity first is port x in std logic vector 7 downto 0 a b c d out std logioc end first architecture Behavioral of first is begin a lt x 1 x 3 or x 5 or x 7 or x 9 b x 2 x 3 or x 6 or x 7 c lt x 4 x 5 or x 6 or x 7 d lt x 9 or x 8 end Behavioral 65 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR DELAY Description Develop a VHDL code for making a delayed output for 1second or 2 seconds by assuming clock frequency provided in the FPGA Kit Simulate same code to get a delayed waveform Flow Chart START SSS SET input clock Delay for 1sec 66 PAnteECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the D
26. es e Double click the Configure Device iMPACT process IMPACT Welcome to iMPACT Please select an action from the list below Configure devices using Boundany Scan JTAG Automatically connect to a cable and identify Boundary S can chain M 3 Prepare a PROM File Prepare a System ACE File C3 Prepare a Boundary Scan File SWF C3 Configure devices using Slave Serial made Cancel e Inthe Welcome dialog box select Configure devices using Boundary Scan J TAG e Verify that Automatically connect to a cable and identify Boundary Scan chain is selected e Click Finish e Ifyou get a message saying that there are two devices found click OK to continue e The devices connected to the JTAG chain on the board will be detected and displayed in the iM PACT window 93 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams e The Assign New Configuration File dialog box appears To assign a configuration file to the xc3s200 device in the JTAG chain select the object beh bit file and click Open IMPACT C tutorialftutorial ipf Boundary Scan a File Edit View Operations Options Output Debug Window Help ae BBM n Ht SSO ew x PA Boundary Scan zu SlaveS erial oe SelectMAP Tal Desktop Configure SvstemACE xc3s200 xct 2s IMPACT Modes _ file file 7 IMPACT Processes Assign New Configuration File
27. ext to move to the device properties page 6 Fill in the properties in the table as shown below v Product Category All v Family Spartan3 v Device XC3S200 84 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Package TQ144 selected Speed Grade 4 Top Level Module Type HDL Synthesis Tool XST VHDL Verilog Simulator ISE Simulator VHDL Verilog v Verify that Enable Enhanced Design Summary is NN NS S N Leave the default values in the remaining fields When the table is complete your project properties will look like the following ES New Project Wizard Device Properties Select the Device and Design Flow for the Project Property Name Value Product Category all 7 Family Spartan3 Device 035200 Package TQ144 Speed 4 Top Level Source Type HD L E Ln XST IMHDLA erlog Simulator ISE Simulator YHDL Verilog Enable Enhanced Design Summary Enable Message Filtering Display Incremental Messages 7 Click Next to proceed to the Create New Source window in the New Project Wizard Create an HDL Source You will create the top level HDL file for your design Determine the language that you wish to use for the tutorial Then continue either to the Creating a VHDL Source section below or creating a Creating a Verilog Source similar to VHDL source creating 85 PAntECF SOLUTIONS www pantechsoluti
28. he other end of the Pantech cable connects to the PC s parallel port The Pantech cable is directly compatible with the Xilinx iM PACT software 13 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 6 5 Clock Source The FPGASP3 Kit has a dedicated 50 M Hz series clock oscillator source and an optional socket for another clock oscillator source SPARTAN3 Crystal Oscillator FPGA Lines 1 B DEN 14 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 6 6 VGA Interface The FPGASP3 Kit includes a VGA display port through DB15 connector Connect this port directly to most PC monitors or flat panel LCD displays using a standard monitor cable As shown in table the Spartan 3 FPGA controls five VGA signals RED R its 1ST pin in connector GREEN G its 2nd pin BLUE B its 3rd pin Horizontal Sync HS 13th pin and Vertical Sync VS its 14th pin all available on the VGA connector PARTAN DB 15 VGA Signals S 3 VGA port bows from Wire Side Vertical Sync VS Horizontal Sync HS INN Nm Each color line has a series resistor to provide 3 bit color with one bit each for Red Green and Blue The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA specified OV to 0 7V range The HS and VS signals are TTL level Drive the R G and B signals High or Low to gene
29. he same convention as for the multiplexer where we abbreviated the values of the data inputs Here 1s one possible circuit diagram for the demultiplexer In this program a 1 x 8 de multiplexer have two 1 bit inputs a 3 bit select line and a 8 bit output Additional control signals may be added such as enable The output of the multiplexers depends on the level of the select line 48 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams m 0 1 5 L am pem ID TEE 00e 91 Qs 535450 Sa E O4 I 5555 Og S5S4S9 Og 858459 Og I 5554Sg eO I S555 DATA input OUTPUTS SELECT code 95 94 Sp xd Mote Iis the data input A cOo l2o00 Oooooococo O 000000 cOOc ooooo OOoO ooo00 oooo0 ooo OOOooo0 o0o cOoooooc o ooocceccs 49 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Flow Chart START 1 L iz RRR RR RRR ORR RR A al When A amp B 0 IN zOutO When A z 0 amp B z 1 IN zOutl WhenA z 1 amp B z 0 IN Out2 WhenA 1 amp B 1 IN Out3 50 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing library ieee use ieee std_logic_1164 all entity demultiplexer is Ome ik 3 tha rs CE Iu oU SES teste
30. is time Stable current ramp Information is displayed during this time Total horizontal time a a T Horizontal display time retrace time time ES porch 7 back porch lp 4 dA E Horizontal sync signa L front porzh sets the retrace frequency correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location The Spartan 3 Evaluation Kit uses three bits per pixel producing one of the eight possible colors shown in above table The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel The VGA controller generates the HS horizontal sync and VS vertical sync timings signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with practical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency 17 PANTECE SOLUTIONS www pantechsolutions net K schem
31. l Technology Beyond the Dreams Testbench code 2 UN LIBRARY ieee USE ieee std logic 1164 ALL USE ieee std logic unsigned all USE eee numeric std Ali ENTITY code vid IS END code_vhd ARCHITECTURE behavior OF code_vhd IS Component Declaration for the Unie Under Test UUT COMPONENT cd PORT a IN ste Logie D 23 IN ta Logic e QUIE Pc ce END COMPONENT INPUTS SIGNAL a srel logie s OV SIGNAL b srel logie s YOY QUT PUTS SENAM eE a Oe BEGIN Instantiate the Unit Under Test UUT uut cd PORT MAP a gt a b gt b Cho C o PROCESs BEGIN scq ipw Want lOO ms for global reset to finish Welt for 100 ns cc MM b 0 Place stimulus here Wake tor 100 mns will wait forever ENDS PROCH So END 73 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Output Waveform We get output in simulation window c 1 according to that gate operation Now 1000 ns ella a5 ac 74 PANTECH SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEMENTATION FOR BLINKING A ARRAY OF LEDS Description Design and develop a VHDL Code for 4 bit binary up counter Four LEDs are connected at the output of the counter The counter should up for every one seconds Flow Chart Counter Value Increase from 0 to 15 75 PANTECE SO
32. l requirements for mouse to host communications and bidirectional keyboard communications The attached keyboard or mouse writes a bit on the data line when the clock signal is High and the host reads the data line when the clock signal is Low 18 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Keyboard The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus If the host never sends data to the keyboard then the host can use simple input pins A ps 2 style keyboard uses scan codes to communicate key press data nearly all keyboards in use today are ps 2 style Each key has a single unique scan code that is sent whenever the corresponding key is pressed The scan codes for most keys appear in below figure If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key Is released the keyboard sends an fO key up code followed by the scan code of the released key the keyboard sends the Same scan code regardless if a key has different shift and non shift characters and regardless whether the shift key is pressed or not The host determines which character is intended Some keys called extended keys send an e0 ahead of the scan code and furthermore they might send more than one scan code When an extended key is released an e0 f0 key up code is sent followed by the scan code E
33. logy Beyond the Dreams 3 Jumper Details PROM Execution JTAG Executions 6 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 4 Connector Details 40 Pin Expansion Connector J5 10123 1 2 10124 10125 3 4 10128 10129 5 6 10130 10131 7 8 10132 10135 9 10 10137 10140 11 12 10141 101 13 14 102 104 15 16 105 17 18 45V 19 20 45V GND 21 22 GND 3V3 23 24 3V3 106 25 26 107 1011 27 28 1012 1013 29 30 1014 1015 31 32 1017 1018 33 34 1020 1021 35 36 1023 1024 37 38 1025 1026 39 40 1027 EXTENSION CONN 20pin Box Connector J6 J7 J8 JTAG Connector J2 TMS TDI TDO TCK GND VCC CON6 7 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 5 Power Supply The external power can be AC or DC with a voltage between 9V 1A output at 230V AC input The SPARTAN3 board produces 45V using an LM 7805 voltage regulator which provides supply to the peripherals USB socket meant for power supply and USB communication user can select either USB or Ext power supply through SW1 Separate On Off Switch SW1 for controlling power to the board ON OFF Power 45V ON External through Adaptor SW1 Power 45V ON Internal through USB There are multiple voltages supplied on the Spartan 3 Evaluation Kit 3 3V 2 5V and 1 2V regulators Similarly the 3 3V regulator feeds all the VCCO voltage supply input
34. mp 7 9 a Ss b p 1000 wins i6 Revision 0 01 File Created Sources for Synthesis Implementatic se Eq Additional Comments S TESTING EE gt 6 B EJ xc3s200 4tql 44 20 library IEEE OR ee counter Behavioral cour 21 use IEEE STD LOGIC 1164 2ALL 22 use IEEE STD LOGIC ARITH ALL lt 23 use IEEE STD LOGIC UNSIGNED ALL Erg Sources PS Snapshots gt 24 a ne zt Uncomment the following library declaration if instantiating 26 any Xilinx primitives in this code P one library UNISIM rOcesses 28 use UNISIM VComponents all 3 amp ddExisting Source 29 3 Create New Source 30 entity counter is Xj View Design Summary 31 Port clk in STD_LOGIC ES Design Utilities 32 displayname out STD_LOGIC ES Y User Constraints 33 selectionline out STD LOGIC Gg Synthesize XST 34 end counter H Implement Design 35 ke B 36 architecture Behavioral of counter is H Generate Programming File an Update Bitstream with Proces 38 begin 39 40 41 end Behavioral 42 43 lt gt sr Processes 7 T Pag counter X Design Summary Started Launching Design Summary se Console Transcript Eros Wamings A Find in Files Ln 1 coli CAPS NUM Refer Lab Examples 87 PAntECF SOLUTIONS Wwww pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams
35. ology Beyond the Dreams Flow Chart 37 PANTECE SOLUTIONS Technology Beyond the Dreams SET input B Verify output Y www pantechsolutions net K scheme VLSI Lab M anual Code Listing ibrary IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity sub is Port a in STD LOGIC VECTOR 3 downto 0 b in STD LOGIC VECTOR 3 downto 0 bin in STD LOGIC Diff out STD LOGIC VECTOR 3 downto 0 bout out STD LOGIC end sub architecture Behavioral of sub is component fullsub port a b bin in std logic Diff bout out std logic end component signal D std logic vector 2 downto 0 begin X1 fullsub port map x2 fullsub port map x3 fullsub port map xA fullsub port map end Behavioral library ieee use ieee std logic 1164 all entity fullsub is port a b bin in std logic Diff bout out std logic end fullsub architecture comb of fullsub is begin Diff lt a xor b xor bin bout lt nota and b or not bin and a xor b vend comb 38 PAnctZzCF SOLUTIONS www pantechsolutions net Technology Beyond the Dreams K scheme VLSI Lab M anual Input Waveform We give input a 1010 b 0101 in waveform window End Time 1000 ns 150 ns 250 ns 350 ns 550 ns 650 ns 750 ns B50 ns 950 ns Eb ap gr ad b ag gag ar b d I LL3 Jp gqop qux gu iu bin 0 MI bout D TDR T Den imo momo 0 a O
36. ons net K scheme VLSI Lab M anual Technology Beyond the Dreams Creating a VHDL Source Create a VHDL source file for the project as follows 1 Click the New Source button in the New Project Wizard 2 Select VHDL Module as the source type 3 Type in the file name counter 4 Verify that the Add to project checkbox is selected ES New Source Wizard Select Source Type q IP Caregen amp Architecture Wizard Schematic YA State Diagram Test Bench WaveForm User Document Verlag Module File name A Verilog Test Fixture Hal VHDL Module VHDL Library Location e VHDL Package ENitting based dep TESTING Ta VHDL Test Bench E ifing based_dsp TESTING F Embedded Processor counter Add to project 5 Click Next 6 Declare the ports for the counter design by filling in the port information as shown below 86 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams ES New Source Wizard Define Module Entity Name Architecture Name Behavioral Port Mame Direction clk dizplayname selectionline 8 Click Next then Finish in the New Source Information dialog box to complete the new source file template P Xilinx ISE E lifting based _dsp TESTING TESTING ise counter vhd fa File Edit View Project Source Process Window Help De ke BI BSARARCAAR 4M xs BEB 4 C MM swo MY 5j e r zs o 7 7 amp 2 a
37. plication operation Now 1000 ns e a 3 0 ex 3 0 ex v 7 0 42 PARntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR MULTIPLEXER Description Design and develop a 2 bit multiplexer and port map the same for developing up to 8 bit multiplexer Multiplexer A multiplexer is a combinatorial circuit that is given a certain number usually a power of two data inputs let us say 2 and n address inputs used as a binary number to select one of the data inputs The multiplexer has a single output which has the same value as the selected data input In other words the multiplexer works like the input selector of a home music system Only one input is selected at a time and the selected input is transmitted to the single output While on the music system the selection of the input 1s made manually the multiplexer chooses its input based on a binary number the address input The truth table for a multiplexer is huge for all but the smallest values of n We therefore use an abbreviated version of the truth table in which some inputs are replaced by to indicate that the input value does not matter Here is such an abbreviated truth table for n 3 The full truth table would have 20 2048 rows 43 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 2 1 mux to construct 8
38. rate the eight possible colors shown in below table ow ue m meme oee w A E E LIII LE E E L1 T E 1 E E 1 E L VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as 15 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams an example of how the FPGA might drive VGA monitor in 640 by 480 modes For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics Websites Video Electronics Standards Association http www vesa org VGA Timing Information http www epanorama net documents pc vga_timing html Signal Timing for a 60Hz 640x480 VGA Display CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permittivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCD displays have evolved to use the same signal timings as CRT displays Consequently the following discussion pertains to both CRTs and LCD displays Within a CRT display current waveforms pass through the coils to produce magnetic fields
39. reams Code Listing pr ry I EER Use IREE STD LOGIC 11604 ALL US IKEE OID HOG ING Me ei ALL USTERCE SID OG TE CO TUN STONED ACL Slee ies ees porc m Eodcm ume o s a CU em EG CMS end first architecture Behavioral of first as begin process clock variable i integer 0 begin jp Lock even sand Glock 1 Rer 1E i NOD ND einer gc S Eq esc a lt l el ir ab o lJ O0000 COR Sage eso es FOO 0 0010 00 then DM Pom I a lt 0 elsif 2 100000000 then i 0 end me end if end process end Behavioral 67 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input in waveform window clk 1 End Time 1000 ns BM clock Wa Output Waveform We get output in simulation waveform a delayed signal Now 1200 ns el clock ala 68 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEMENTATION FOR BLINKING A LED Description Develop a VHDL Code for delay and verify by simulating it This delay output is connected to LED Delay is adjusted such away LED blinks for every 1 or 2 seconds Flow Chart C2 69 PAnteECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description FPGA LOC P55 P97 Code Listing pror vr IEEE use IEEE SID LOGIC 1164
40. rt 60 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Look Up Table PIN Description I O 1 2 I3 A C E F G PINS e III I I ILI I I LOC 61 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing DOr a MU hah 2 uses E OTD LOGT ITC ALL entity SEVEN SEG LUT is Pore ee a oD a OG KG v ai od ORE ies LOEO Uv Silke 2 obec SIU LOGIN WG TD OI ES e e e ONQUE CT 0 gt VOU SIE DICITO he Ry ECOL T e ole vga e v6 E end SEVEN SEG LUT architecture Behavioral of SEVEN SEG LUT is begin Sess cu ceu process I BEGIN case I is when 0000 2 when OE when 0010 2 when TOOTIS when OD when NEM when tod when OMM when 1000 2 when 1001 when others gt end case lt 10000007 eigo ur eNO DUO e Et 010 lt TH LLOOI lt 0010010 0069081 0 TULL lt 0000000 Em gu eo idv In ise Iss eec Ee es ee ee ces ec ee end process end Behavioral 62 PAntzECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEMENTATION OF ENCODER Encoder Design and develop HDL code for decimal Octal to BCD encoder There will be10 input switches or 8 switches and 4 LEDs in the FPGA kit The input given from switches and it is noted that any one of the switch is active The binary
41. s MEE cmo UN begin MUS IS muU Port map a mu x2 m x port map eg MUS ok Port map er mux4 mux port map cor muxo MUX Port mip VE ae muxo mux Pori map z4 ma ml Pore MAE zo end Behavioral 46 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give input a high in waveform window End Time 1000 ns cQjojojojoojocjoajoalojoojzdoc zo Output Waveform We get output in simulation window y high according to that multiplexer operation End Time 1000 ns 5S ns 150 ns 250 ns 350 ns 150 ns 550 ns 550 ns TS ns 850 ns 950 ns ELE LEE br b rrr b rrr barra Era dr ba rar bara dd iua iub iu iul d Ule uf MP ilh iu co iul c1 ul c2 Mz D A c c A A c c3 c c3 47 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams SIM ULATION OF VHDL CODE FOR DEM ULTIPLEXER Description Design and develop an 8 output demultiplexer using truth table Demultiplexer The demultiplexer is the inverse of the multiplexer in that it takes a single data input and n address inputs It has 2 outputs The address input determine which data output is going to have the same value as the data input The other data outputs will have the value 0 Here is an abbreviated truth table for the demultiplexer We could have given the full table since it has only 16 rows but we will use t
42. s to the FPGA s I O banks and powers most of the components on the board The 2 5V regulator supplies power to the FPGA s VCCAUX supply inputs The VCCAUX voltage input supplies power to Digital Clock M anagers DCM s within the FPGA and supplies some of the I O structures In specific all of the FPGA s dedicated configuration pins such as DONE PROG B CCLK and the FPGA s JTAG pins are powered by VCCAUX The FPGA configuration interface on the board is powered by 3 3V Consequently the 2 5V supply has a current shunt resistor to prevent reverse current Finally a 1 2V regulator supplies power to the FPGA s VCCINT voltage inputs which power the FPGA s core logic The board uses four discrete regulators to generate the necessary voltages 8 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 6 On board Peripherals The Evaluation Kit comes with many interfacing options e 0 Nos of Point LED s Digital Outputs e 0 Nos of Digital Inputs Slide Switches e UART for serial port communication through PC e JTAG Programmer e Clock Source e 3 bit 8 Color VGA Interface e PS 2 Keyboard interface 9 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 6 1 Light Emitting Diodes e Light Emitting Diodes LEDs are the most commonly used components usually for displaying pin s digital states e The FPGASP3 KIT has 8 nos of Point
43. sc Fi F2 F3 F4 FS Fe F7 F8 Fo Fto F11 76 05 06 J 04 J oc 03 j J e3 oA 01 J 09 78 If 1 ff2e 3s 4 5 6 7 amp amp 9 If 0 zs 4 og 16 1E 26 25 a amp 36 3p 3E 46 45 4 55 66 TaBlOlwI EJIR r TI UYTNYS g Tr Iu oD 15 JL 1D J 24 JL 2D 2 35 3c 43 J 44 4D 54 5B 5D CapsLock 5B w d 3B Es 4c 33 shit E sr 12 Jz Ji 22 2 H H EH EH A 5 FH sr Ctrl Ea o WW 7 Alt CH 12 E XS ED 11 E014 The host can also send commands and data to the keyboard Below figure provides a short list of some often used 19 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Commands Turn on off Num Lock Caps Lock and Scroll Lock LEDs Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate Resend Upon receiving a resend command the keyboard resends the last scan code sent FR Reset Resets the keyboard The keyboard sends commands or data to the host only when both the data and clock lines are High the Idle state Because the host is the bus master the keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data
44. std logic unsigned all entity object co is Pome els basso er Oubespoelogxcevecbor07sdownuov 0 Gut otd logie ve ctor downto O end object_co architecture beav of object_co is type state is state0 statel state2 state3 state4 state5 state6 state7 state8 state9 signal next state ps state state0 begin SHE ou process clk next state variable i integer 0 begin IP elk event oand CI S if i lt 100000000 then JE Ru MN elsif 1 gt 100000000 then i t Ol INES pouce lt OS M oL IE if next state state0 then vy lt x c0 ps lt stalel 80 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams elsif next state statel y lt SOLO ps lt state2 elsif next state state2 y lt Og ps lt state3 elsif next_state state3 y lt XeU IL ps lt state4 elsif next state state4 wy lt xX 99 ps lt stated elsif next state stateb y lt pou E ps lt state elsif next state state6 y lt XOU DUIS ps lt state 7 elsif next state state7 y x Sonn ps lt state8 elsif next state states Ww lt Too ps lt state9 elsif next state state9 y lt De ps lt state0 end if end If end process end beav 81 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Getting Started with Xilinx ISE Tutorial 82 PANTECE
45. t 28 le 29 end object co 30 lt x architecture beav of object co is 1 1 1 architecture name beav Ss lt Sd Processes l as a aaO Untitledi 2 B 5 E Console Enors a Warnings I Find in Files Ln 79 Col 46 CAPS NUR Step 2 Save the file by selecting File Save the file with vhd extension 88 PAntzECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams pave in My Recent Documents a Desktop hy Documents My Computer hy Network File name Untitled Pl aces Save as type Verilag av vE Pte th thw ven tte thal veo tt VHDL hd vhdl wht who vhs vhi vh vh Step 3 Add your source code in your source window place a cursor above the IC number xc3s200 4tq144 Right click gt Add source gt Open vhd file Add Existing 5ources Look in E LZ _xmsgs D My Recent Documents Desktop My Documents E My Computer My Network File name Untitled x Open Places Files af type Sources tet vhd vhdl s abl aby x60 oF th Cancel Step 4 verify that your code is added with synthesis and implementation 89 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams E Adding Source Files The following allows you to see the status of the source files being added
46. to 7 3 end demultiplexer architecture data of demultiplexer is D nous 0 anci nots lL anci nort s 7 S O and not s 1 and not s 2 not SiO anc sil anci nok S 2 s 0 and s 1 and not s 2 not Ss 0 and nort s 1 anci s 2 z s 0 anc nor s 1 anci 3 2 not s0 anci sll and s 2 lt s 0 andi s 1 anc 2 00000 0 ON nN nn M MM D end data 56 PAntecCF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VHDL IM PLEMENTATION OF 7 SEGMENT DECODER Description Develop Boolean expression for 4 input variables and 7 output variables Design and develop seven segment decoder in VHDL for 7 equations A seven segment display is connected to the output of the circuit Four switches are connected to the input The 4 bit input is decoded to 7 segment equivalent Flow Chart SWITCH TO 7 SEGMENT DISPLAY 57 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams PIN Description FPGA P86 P87 P89 P90 P23 P24 P25 P26 P27 P28 P30 Look Up Table 58 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing rror dU BES c use IEEE STD LOGIC 1164 ALLl Uncomment the following library declaration if using arithmetic fLUunecetons with Sigmed or Unsigned values SSuUse EEE NOUMER We SS Ak
47. to the project and allows you to specify the Design View association For sources which are successtully added to the project C9 Untitled vhd object co beav ynthesis lmp Simulation v Mone Synthesis Implementation Orly Simulation Only Step 5 Click ok Step 6 Checking the Syntax of the 7SEGMENT COUNTER Module When the source files added complete check the syntax of the design to find errors and typos e Verify that Synthesis Implementation is selected from the drop down list in the Sources window e Select the object_co design source in the Sources window to display the related processes in the Processes window e Click the next to the Synthesize XST process to expand the process group Sources For Synthesis mplementatic i i Yseq BES acS lt e200 4491 44 Erez object co beaw L b Create Hen Source Yie Design S ummary E 3 F Design Utilities User Constraints Lm M M Eom Sunthesize ST s pew Snkhesis A epaort fa wiew ATL Schematic EJ wiern T echnologye S chem Co Check Syntax c ua Generate Post Synthesis 9 E e a Implement Design E i a Generate Programming File Update Bitstream with Proces i is IILILILEBEe e Double click the Check Syntax process 90 PANTECE SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Note You must correct any errors found
48. until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by eight bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit Echo Upon receiving an echo command the keyboard replies with the same scan code EE ED EF F3 FE FF 20 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 7 Board Layout DB 9 HALE P1 uu T d i MAX3232 Y EE E n p 23 m Lo JTAG UART VEA a PHR POWER yN AN of J5 MN m d D1 Pl24 P12B PROM p tc Di pe 2 P130 D ik pi B of m W exl ua ur a P z A E DONE pat wlil2 rn q 57 oy J a lla 2 a u Z lu i Tun wey xm se bey E SPARTANS es E won amp aur T m iv zm be i 3 zu 7T D i i l m p amp i P14 o m ui a a UE Toe uic pie p25 qui j erk i n prov uta r ES othe j SPARTANS EVALUATION BOARD PA 21 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams VLSI LAB Examples L Scheme 22 PANTECr SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Contents 8 VLSI Lab Experiments l 2 10 11 12 13 14 15 simulation of VHDL code for combinational circuit simulation of VHDL code for
49. utput Waveform We get output in simulation window according to that subtraction Operation Now 1000 ns E X a 3 0 E X b 3 0 ell hin Fl X difiT3 0 AN dita AN diti ay ditm AN aito ell bout 39 PAnctzECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams 2 3 Multiplication Program for simple 4x4 multiplications using arithmetic operator Consider the multiplication of two numbers as 4 x4 a b where a and b are 4 bit numbers and the output of multiplication is taken in y as 8 bit number Flow Chart START SET input A SET input B Verify output Y 40 PARntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Code Listing library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity codef Is Port a in STD LOGIC VECTOR 3 downto 0 b in STD LOGIC VECTOR 3 downto 0 y out STD LOGIC VECTOR 7 downto 0 end codef architecture Behavioral of codef is begin y a b end Behavioral 41 PAntECF SOLUTIONS www pantechsolutions net K scheme VLSI Lab M anual Technology Beyond the Dreams Input Waveform We give inputa 2 amp b 2 End Time 1000 ns 150 ns 250 ns 350 ns 450 ns 550 ns 650 ns BA a 3 0 Output Waveform We give input a amp b so we get output yz 4 according to that multi

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