SECTION 2 INTRODUCTION
Contents
1. NEGX 0 Destination X Destination NEGX ea Destination Destination NOT ea Source V Destination Destination OR ea Dn 0 EY 0 Destination Destination NEG ea 57312 Dn lt ea gt Immediate Data V Destination gt Destination ORI lt data gt lt ea gt ORI to CCR Source V CCR gt CCR ORI lt data gt CCR ORI to SR If supervisor state ORI lt data gt SR then Source V SR gt SR else TRAP 5 4 SP lt ea gt SP PEA ea RESET If supervisor state then Assert RESET Line else TRAP ROL ROR Destination Rotated by count Destination ROd Rx Dy ROd lt data gt Dy ROd lt ea gt Destination Rotated with X by count Destination ROXd Dx Dy ROXd lt data gt Dy ROXd lt ea gt RD SP OPC SP 4 d SP RTD displacement MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 13 Table 2 2 Instruction Set Summary Sheet 4 of 4 If supervisor state then SP 2 SR SP 2 2 SP SP 2 PC SP 4 SP restore state and deallocate stack according to SP else TRAP RTR SP gt CCR SP 2 SP RTR SP gt PC SP 4 SP RTS SP gt PC SP 4 gt SP RTS SBCD Destination4Q Source190 X Destination SBCD Dx Dy SBCD Ax Ay Scc If condition true Scc ea then 1s Destination else 0s Destination If supervisor state STOP data then Immediate Data SR STOP else TRAP SU2. PC SSP SSP 4 5 SSP SR gt SSP SSP 2 SSP vector PC STOP Enter the stopped state waiting for interrupts If lt condition gt then The condition is tested If true the operations after then operations else performed If the condition is false and the optional lt operations gt else clause is present the operations after else are performed If the condition is false and else is omitted the instruction performs no operation Refer to the Bcc instruction description as an example 2 10 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA Table 2 2 Instruction Set Summary Sheet 1 of 4 ABCD 10 Destination4Q X Destination ABCD Dy Dx ABCD Ay Ax ADD Source Destination Destination ADD lt ea gt Dn ADD Dn lt ea gt ADDA Source Destination Destination ADDA lt ea gt An ADDI Immediate Data Destination Destination ADDI lt data gt lt ea gt ADDQ Immediate Data Destination Destination ADDQ lt data gt lt ea gt ADDX Source Destination X Destination ADDX Dy Dx ADDX Ay AND Source A Destination Destination AND lt ea gt Dn AND Dn lt ea gt ANDI Immediate Data A Destination Destination ANDI data ea ANDI to CCR Source A CCR CCR ANDI lt data gt CCR ANDI to SR If supervisor state ANDI lt data gt SR then Source A SR gt SR else TRAP ASL ASR Destination Shifted by coun
3. 3 3 Input and Output Signals MC68EC000 3 2 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 2 GND 2 A19 A0 CLK 07 00 m FCO PROCESSOR FCI RATIS FC2 ASYNCHRONOUS S BUS MC6808 CONTROL MC6800 E PERIPHERAL VPA BUS CONTROL I ARBITRATION CONTROL BERR SYSTEM CONTROL RESET HALT __ INTERRUPT CONTROL Figure 3 4 Input and Output Signals MC68008 48 Pin Version Vcc ADDRESS GND 2 BUS A21 A0 CLK DATA BUS gt 07 00 FCO PROCESSORS RAV ASYNCHRONOUS STATUS RA FC2 DS 5 es MC68008 STATE CONTROL MC6800 E BR BUS PERIPHERAL J VPA BG I ARBITRATION CONTROL BGACK CONTROL SYSTEM BERR PLO CONTROL RESET IPLI INTERRUPT HALT PO CONTROL Figure 3 5 Input and Output Signals MC68008 52 Pin Version 3 1 ADDRESS BUS A23 A1 This 23 bit unidirectional three state bus is capable of addressing 16 Mbytes of data This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles and breakpoint cycles During interrupt acknowledge cycles address lines A1 A2 and A3 provide the level number of the interrupt being acknowledged and address lines 23 4 are driven to logic high MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 3 3 Address Bus A23 A0 This 24 bit unidirectional three state bus is capable of addressing 16 Mbytes of data This bus provides the address for
4. bus operation during all cycles except interrupt acknowledge cycles and breakpoint cycles During interrupt acknowledge cycles address lines A1 A2 and provide the level number of the interrupt being acknowledged and address lines 23 4 and 0 are driven to logic high In 16 Bit mode 0 is always driven high MC68008 Address Bus The unidirectional three state buses in the two versions of the MC68008 differ from each other and from the other processor bus only in the number of address lines and the addressing range The 20 bit address A19 A0 of the 48 pin version provides a 1 Mbyte address space the 52 pin version supports a 22 bit address 21 0 extending the address space to 4 Mbytes During an interrupt acknowledge cycle the interrupt level number is placed on lines A1 A2 and A3 Lines AO and A4 through the most significant address line are driven to logic high 3 2 DATA BUS D15 D0 MC68008 07 00 This bidirectional three state bus is the general purpose data path It is 16 bits wide in the all the processors except the MC68008 which is 8 bits wide The bus can transfer and accept data of either word or byte length During an interrupt acknowledge cycle the external device supplies the vector number on data lines D7 DO The 68 000 and MC68HC001 use D7 DO 8 bit mode and D15 D8 are undefined 3 3 ASYNCHRONOUS BUS CONTROL Asynchronous data transfers are controlled by the following signals address
5. strobe read write upper and lower data strobes and data transfer acknowledge These signals are described in the following paragraphs Address Strobe AS This three state signal indicates that the information on the address bus is a valid address Read Write R W This three state signal defines the data bus transfer as a read or write cycle The R W signal relates to the data strobe signals described in the following paragraphs Upper And Lower Data Strobes UDS LDS These three state signals and R W control the flow of data on the data bus Table 3 1 lists the combinations of these signals and the corresponding data on the bus When the R W line is high the processor reads from the data bus When the R W line is low the processor drives the data bus In 8 bit mode UDS is always forced high and the LDS signal is used 3 4 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 3 1 Data Strobe Control of Data Bus me sevaspaa No vata aia Low Low High Valid Data Bits Valid Data Bits 15 8 7 0 Low No Valid Data Valid Data Bits 7 0 Low High High Valid Data Bus No Valid Data 15 8 Low Low Low Valid Data Bits Valid Data Bits 15 8 7 0 High Low Low Valid Data Bits Valid Data Bits 7 0 7 0 Low High Low Valid Data Bits Valid Data Bits 15 8 15 8 These conditions are a result of current implementation and may not appear on future devices Data Strobe DS MC68008 This three
6. the optional mode qualifiers are d and d ix xxx or lt data gt Immediate data that follows the instruction word s Notations for operations that have two operands written lt operand gt lt op gt lt operand gt where lt op gt is one of the following The source operand is moved to the destination operand The two operands are exchanged The operands are added The destination operand is subtracted from the source operand x The operands are multiplied The source operand is divided by the destination operand lt Relational test true if source operand is less than destination operand gt Relational test true if source operand is greater than destination operand V Logical OR Logical exclusive OR A Logical AND MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 9 shifted by rotated by The source operand is shifted or rotated by the number of positions specified by the second operand Notation for single operand operations lt operand gt The operand is logically complemented lt operand gt sign extended The operand is sign extended all bits of the upper portion are made equal to the high order bit of the lower portion lt operand gt tested The operand is compared to zero and the condition codes are set appropriately Notation for other operations TRAP Equivalent to Format Offset Word SSP SSP 2 gt SSP
7. 00 instruction set listed by opcode operation and syntax In the syntax descriptions the left operand is the source operand and the right operand is the destination operand The following list contains the notations used in Table 2 2 2 8 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA Notation for operands PC Program counter SR Status register V Overflow condition code Immediate Data Immediate data from the instruction Source Source contents Destination Destination contents Vector Location of exception vector inf Positive infinity inf Negative infinity lt fmt gt Operand data format byte B word W long L single S double D extended X or packed P FPm One of eight floating point data registers always specifies the source register FPn One of eight floating point data registers always specifies the destination register Notation for subfields and qualifiers lt bit gt of lt operand gt Selects a single bit of the operand lt ea gt offset width Selects a bit field lt operand gt The contents of the referenced location lt operand gt 10 The operand is binary coded decimal operations are performed in decimal lt address register gt The register indirect operator lt address register gt Indicates that the operand register points to the memory lt address register gt Location of the instruction operand
8. 000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 3 7 3 7 M6800 PERIPHERAL CONTROL These control signals are used to interface the asynchronous M68000 processors with the synchronous M6800 peripheral devices These signals are described in the following paragraphs Enable E This signal is the standard enable signal common to all M6800 Family peripheral devices A single period of clock E consists of 10 MC68000 clock periods six clocks low four clocks high This signal is generated by an internal ring counter that may come up in any state At power on it is impossible to guarantee phase relationship of E to CLK The E signal is a free running clock that runs regardless of the state of the MPU bus Valid Peripheral Address VPA This input signal indicates that the device or memory area addressed is an M6800 Family device or a memory area assigned to M6800 Family devices and that data transfer should be synchronized with the E signal This input also indicates that the processor should use automatic vectoring for an interrupt Refer to Appendix B M6800 Peripheral Interface Valid Memory Address VMA This output signal indicates to M6800 peripheral devices that the address on the address bus is valid and that the processor is synchronized to the E signal This signal only responds to a VPA input that identifies an M6800 Family device The MC68008 does not supply a VMA signal This signal can be produced by a transistor to transistor
9. 2 is the most significant bit For each interrupt request these signals must remain asserted until the processor signals interrupt acknowledge FC2 FCO and 19 A16 high for that request to ensure that the interrupt is recognized NOTE The 48 pin version of the MC68008 has only two interrupt control signals IPLO IPL2 and IPL1 IPLO IPL2 is internally connected to both IPLO and IPL2 which provides four interrupt priority levels levels 0 2 5 and 7 In all other respects the interrupt priority levels in this version of the MC68008 are identical to those levels in the other microprocessors described in this manual 3 6 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA 3 6 SYSTEM CONTROL The system control inputs are used to reset the processor to halt the processor and to signal a bus error to the processor The outputs reset the external devices in the system and signal a processor error halt to those devices The three system control signals are described in the following paragraphs Bus Error BERR This input signal indicates a problem in the current bus cycle The problem may be the following 1 No response from a device 2 No interrupt vector number returned 3 An illegal access request rejected by a memory management unit 4 Some other application dependent error Either the processor retries the bus cycle or performs exception processing as determined by interaction between the bus error signal and
10. B Destination Source Destination SUB ea Dn SUB Dn ea SUBA Destination Source Destination SUBA ea An SUBI Destination Immediate Data Destination SUBI data ea SUBQ Destination Immediate Data Destination SUBQ lt data gt lt ea gt SUBX Destination Source X Destination SUBX Dx Dy SUBX Ax Ay SWAP Register 31 16 Register 15 0 SWAP Dn TAS Destination Tested Condition Codes 1 bit 7 of TAS ea Destination TRAP SSP 2 5 SSP Format Offset SSP TRAP lt vector gt SSP 4 gt SSP PC 5 SSP SSP 2 gt SSP SR gt SSP Vector Address PC TRAPV If V then TRAP TRAPV UNLK An SP SP gt An SP 45 SP UNLK An NOTE d is direction L or R 2 14 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA SECTION 3 SIGNAL DESCRIPTION This section contains descriptions of the input and output signals The input and output signals can be functionally organized into the groups shown in Figure 3 1 for the MC68000 the MC68HCO000 and the MC68010 Figure 3 2 for the MC68HC001 Figure 3 3 for the 68 000 Figure 3 4 for the MC68008 48 pin version and Figure 3 5 for the MC68008 52 pin version The following paragraphs provide brief descriptions of the signals and references where applicable to other paragraphs that contain more information about the signals NOTE The terms assertion and negation are used
11. Bus requests can be issued at any time during a cycle or between cycles Bus Grant BG This output signal indicates to all other potential bus master devices that the processor will relinquish bus control at the end of the current bus cycle Bus Grant Acknowledge BGACK This input indicates that some other device has become the bus master This signal should not be asserted until the following conditions are met 1 A bus grant has been received 2 Address strobe is inactive which indicates that the microprocessor is not using the bus 3 Data transfer acknowledge is inactive which indicates that neither memory nor peripherals are using the bus 4 Bus grant acknowledge is inactive which indicates that no other device is still claiming bus mastership The 48 pin version of the MC68008 has no pin available for the bus grant acknowledge signal and uses a two wire bus arbitration scheme instead If another device in a system supplies a bus grant acknowledge signal the bus request input signal to the processor should be asserted when either the bus request or the bus grant acknowledge from that device is asserted 3 5 INTERRUPT CONTROL IPLO IPL1 IPL2 These input signals indicate the encoded priority level of the device requesting an interrupt Level seven which cannot be masked has the highest priority level zero indicates that no interrupts are requested IPLO is the least significant bit of the encoded level and IPL
12. SECTION 2 INTRODUCTION The section provide a brief introduction to the M68000 microprocessors MPUs Detailed information on the programming model data types addressing modes data organization and instruction set can be found in M68000PM AD M68000 Programmer s Reference Manual All the processors are identical from the programmer s viewpoint except that the MC68000 can directly access 16 Mbytes 24 bit address and the MC68008 can directly access 1 Mbyte 20 bit address on 48 pin version or 22 bit address on 52 pin version The MC68010 which also uses a 24 bit address has much in common with the other devices however it supports additional instructions and registers and provides full virtual machine memory capability Unless noted all information pertains to all the M68000 MPUs 2 1 PROGRAMMER S MODEL All the microprocessors executes instructions in one of two modes user mode or supervisor mode The user mode provides the execution environment for the majority of application programs The supervisor mode which allows some additional instructions and privileges is used by the operating system and other system software 2 1 1 User Programmer s Model The user programmer s model see Figure 2 1 is common to all M68000 MPUs The user programmer s model contains 16 32 bit general purpose registers 00 07 0 A7 a 32 bit program counter and an 8 bit condition code register The first eight registers DO D7 are used as dat
13. SP Vector Offset SSP ILLEGAL SSP 4 gt SSP PC 5 SSP SSP 2 5 SSP SR 5 SSP Illegal Instruction Vector Address PC JSR SP 4 gt SP PC SP JSR lt ea gt Destination Address LINK SP 4 gt SP An gt SP LINK An lt displacement gt SP gt An SP d gt SP LSL LSR Destination Shifted by count Destination 150 Dx Dy LSd lt data gt Dy LSd lt ea gt MOVE from CCR Destination MOVE CCR lt ea gt CCR MOVE to Source CCR MOVE ea CCR CCR MOVE from SR Destination MOVE SR lt ea gt SR If supervisor state then SR Destination else TRAP MC68010 only MOVE to SR If supervisor state MOVE ea SR then Source SR else TRAP O X X M S E 2 12 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA Table 2 2 Instruction Set Summary Sheet 3 of 4 MOVE USP If supervisor state MOVE USP An then USP An or An gt USP MOVE An USP else TRAP MOVEC If supervisor state MOVEC Rc Rn then Rc gt Rn or Rn gt Rc MOVEC Rn Rc else TRAP MOVEM Registers Destination MOVEM register list lt ea gt Source Registers MOVEM ea register list MOVEP Source Destination MOVEP Dx d Ay MOVEP d Ay Dx MOVEQ Immediate Data Destination MOVEQ lt data gt Dn MOVES If supervisor state MOVES Rn lt ea gt then Rn Destination DFC or Source SFC Rn MOVES lt ea gt Rn else TRAP NBCD Destination40 X Destination NBCD ea
14. SP PC VBR SFC DFC VBR SFC DFC NOTES 1 VBR SFC and DFC apply to the MC68010 only EA Effective Address Dn Data Register An Address Register Contents of PC Program Counter dg 8 Bit Offset Displacement dig 16 Bit Offset Displacement N 1forbyte 2 for word and 4 for long word If An is the stack pointer and the operand size is byte N 2 to keep the stack pointer on a word boundary lt Replaces Xn Address or Data Register used as Index Register SR Status Register USP User Stack Pointer SSP Supervisor Stack Pointer CP Program Counter VBR Vector Base Register 2 3 DATA ORGANIZATION IN REGISTERS The eight data registers support data operands of 1 8 16 or 32 bits The seven address registers and the active stack pointer support address operands of 32 bits 2 3 1 Data Registers Each data register is 32 bits wide Byte operands occupy the low order 8 bits word operands the low order 16 bits and long word operands the entire 32 bits The least significant bit is addressed as bit zero the most significant bit is addressed as bit 31 MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 5 When a data register is used as either a source or a destination operand only the appropriate low order portion is changed the remaining high order portion is neither used nor changed 2 3 2 Address Registers Each address register and the stack pointer is 32 bit
15. Write Low meme x rer s NC EN Data Transfer acinowieage Drok tow no s sP SP s mom P tw e w _ EE MEAE f iw f oe IPL2 este sm wa uw s x ma E O im e ERE S s m CHEN GEI Function Code Output FCO FC1 High No Yes FC2 o LR RD s E j sp h Open drain 3 10 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA
16. a registers for byte 8 bit word 16 bit and long word 32 bit operations The second set of seven registers A0 A6 and the user stack pointer USP can be used as software stack pointers and base address registers In addition the address registers can be used for word and long word operations All of the 16 registers can be used as index registers MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 1 31 16 15 8 7 D1 D2 03 EIGHT p4 DATA REGISTERS D5 D6 D7 31 16 15 0 A0 Al A2 SEVEN A3 ADDRESS A4 REGISTERS A5 A6 7 USER STACK USP POINTER pc PROGRAM COUNTER 7 STATUS Figure 2 1 User Programmer s Model MC68000 MC68HC000 MC68008 MC68010 po 31 0 2 1 2 Supervisor Programmer s Model The supervisor programmer s model consists of supplementary registers used in the supervisor mode The M68000 MPUs contain identical supervisor mode register resources which are shown in Figure 2 2 including the status register high order byte and the supervisor stack pointer SSP A7 3l 16 15 0 SSP POINTER 15 87 0 I CCR SR STATUS REGISTER Figure 2 2 Supervisor Programmer s Model Supplement The supervisor programmer s model supplement of the MC68010 is shown in Figure 2 3 In addition to the supervisor stack pointer and status register it includes the vector base register VRB and the alternate function code registers AFC The VBR is used to determine
17. data etc are provided in the instruction set The 14 flexible addressing modes shown in Table 2 1 include six basic types 1 Register Direct 2 Register Indirect 3 Absolute 4 Immediate 5 Program Counter Relative 6 Implied The register indirect addressing modes provide postincrementing predecrementing offsetting and indexing capabilities The program counter relative mode also supports indexing and offsetting For detail information on addressing modes refer to M68000PM AD M68000 Programmer Reference Manual 2 4 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA Table 2 1 Data Addressing Modes ede Gene Syntax Register Direct Addressing Data Register Direct Dn Address Register Direct Absolute Data Addressing Absolute Short EA Next Word xxx W Absolute Long EA Next Two Words xxx L Program Counter Relative Addressing d16 PC Relative with Offset P dg PC Xn Relative with Index and Offset Register Indirect Addressing Register Indirect EA An An Postincrement Register Indirect EA An An N An Predecrement Register Indirect An An N EA An An Register Indirect with Offset EA An d16 916 Indexed Register Indirect with Offset EA An Xn dg dg An Xn Immediate Data Addressing Immediate DATA Next Word s lt data gt Quick Immediate Inherent Data Implied Addressing Implied Register EA SR USP SSP SR USP S
18. extensively in this manual to avoid confusion when describing a mixture of active low and active high signals The term assert or assertion is used to indicate that a signal is active or true independently of whether that level is represented by a high or low voltage The term negate or negation is used to indicate that a signal is inactive or false 2 GND 2 23 1 CLK 015 00 ASYNCHRONOUS FCO I BUS PROCESSOR FCI CONTROL STATUS Tm MC6800 BUS PERIPHERAL VMA I ARBITRATION CONTROL VPA CONTROL SYSTEM BERR i RESET INTERRUPT CONTROL PEET X HAIT CONTROL Figure 3 1 Input and Output Signals MC68000 MC68HC000 and MC68010 MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 3 1 Voc 2 ADDRESS 805 A10 CLK DATABUS gt D15 D0 u RW ASYNCHRONOUS FCO UDS BUS PROCESSOR 105 CONTROL STATUS 6800 BR BUS PERIPHERAL VMA BG ARBITRATION CONTROL VPA BGACK CONTROL BERR PLO _ m REE m unn CONTROL HALT IPL2 MODE Figure 3 2 Input and Output Signals MC68HC001 Vcc 2 ADDRESS GNDQ 805 A2 A0 CLK DATABUS gt 015 00 is ar E RW ASYNCHRONOUS FCO UDS BUS PROCESSOR LDS CONTROL STATUS FC2 68 000 DTACK BR BUS BG I ARBITRATION CONTROL PLO SYSTEM wg RESET y INTERRUPT CONTROL HALT PL2 CONTROL MODE AEC Figure
19. logic TTL circuit an example is described in Appendix B M6800 Peripheral Interface 3 8 PROCESSOR FUNCTION CODES FCO FC1 FC2 These function code outputs indicate the mode user or supervisor and the address space type currently being accessed as shown in Table 3 3 The function code outputs are valid whenever AS is active 3 8 M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL MOTOROLA Table 3 3 Function Code Outputs Function Code Output FC2 FCi Fco Address Space Type Fux Uere Low High Supervisor Program 3 9 CLOCK The clock input is TTL compatible signal that is internally buffered for development of the internal clocks needed by the processor This clock signal is a constant frequency square wave that requires no stretching or shaping The clock input should not be gated off at any time and the clock signal must conform to minimum and maximum pulse width times listed in Section 10 Electrical Characteristics 3 10 POWER SUPPLY Vcc and GND Power is supplied to the processor using these connections The positive output of the power supply is connected to the Vcc pins and ground is connected to the GND pins MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 3 9 3 11 SIGNAL SUMMARY Table 3 4 summarizes the signals discussed in the preceding paragraphs Table 3 4 Signal Summary Signal Name Input Output Active State On HALT On Bus Relinquish
20. organization of data in the memory of the MC68008 is shown in Figure 2 7 2 6 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA MOTOROLA BIT DATA 1 BYTE 8 BITS INTEGER DATA 1 BYTE 8 BITS 1 WORD 16 BITS 15 14 B 12 1 10 9 8 7 6 5 4 3 2 1 0 EVEN BYTE ODD BYTE 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 LONG WORD 32 BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOW ORDER ADDRESSES 1 ADDRESS 32 BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HIGH ORDER LOW ORDER MSB MOST SIGNIFICANT BIT LSB LEAST SIGNIFICANT BIT DECIMAL DATA 2 BINARY CODED DECIMAL DIGITS 1 BYTE 15 14 B 0 1 10 9 8 7 6 5 4 3 2 1 0 MSD BCD 0 BCD1 isp BCD 2 BCD 3 BCD 4 BCD5 BCD 6 BCD7 MSD MOST SIGNIFICANT DIGIT LSD LEAST SIGNIFICANT DIGIT Figure 2 6 Data Organization in Memory M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 7 BIT DATA 1 BYTE 8 BITS 7 6 5 4 3 2 1 0 INTEGER DATA 1 BYTE 8 BITS 7 6 5 4 3 2 1 0 HIGHER ADDRESSES LOWER ADDRESSES 1 WORD 2 BYTES 16 BITS BYTE 0 MS BYTE LOWER ADDRESSES BYTE 1 LS BYTE BYTE 0 MS BYTE BYTE 1 LS BYTE HIGHER ADDRESSES 1 LONG WORD 2 WORDS 4 BYTES 32 BITS LOWER ADDRESSES HIGH ORDER WORD LONG WORD 0 LOW ORDER WORD HIGH ORDER WORD LONG WORD 1 LOW ORDER WORD HIGHER ADDRESSES Figure 2 7 Memory Data Organization of the MC68008 2 5 INSTRUCTION SET SUMMARY Table 2 2 provides an alphabetized listing of the M680
21. s wide and holds a full 32 bit address Address registers do not support byte sized operands Therefore when an address register is used as a source operand either the low order word or the entire long word operand is used depending upon the operation size When an address register is used as the destination operand the entire register is affected regardless of the operation size If the operation size is word operands are sign extended to 32 bits before the operation is performed 2 4 DATA ORGANIZATION IN MEMORY Bytes are individually addressable As shown in Figure 2 5 the high order byte of a word has the same address as the word The low order byte has an odd address one count higher Instructions and multibyte data are accessed only on word even byte boundaries If a long word operand is located at address n n even then the second word of that operand is located at address 2 ADDRESS 000000 BYTE 000000 BYTE 000001 000002 BYTE 000002 BYTE 000003 WORD 7FFF FF SFFFFFE BYTE FFFFFE BYTE FFFFFE Figure 2 5 Word Organization in Memory The data types supported by the M68000 MPUs are bit data integer data of 8 16 and 32 bits 32 bit addresses and binary coded decimal data Each data type is stored in memory as shown in Figure 2 6 The numbers indicate the order of accessing the data from the processor For the MC68008 with its 8 bit bus the appearance of data in memory is identical to the all the M68000 MPUs The
22. state signal and R W control the flow of data on the data bus of the MC68008 Table 3 2 lists the combinations of these signals and the corresponding data on the bus When the R W line is high the processor reads from the data bus When the R W line is low the processor drives the data bus Table 3 2 Data Strobe Control of Data Bus MC68008 m ww s o 1 Valid Data Bits 7 0 Read Cycle o Valid Data Bits 7 0 Write Cycle Data Transfer Acknowledge DTACK This input signal indicates the completion of the data transfer When the processor recognizes DTACK during a read cycle data is latched and the bus cycle is terminated When DTACK is recognized during a write cycle the bus cycle is terminated 3 4 BUS ARBITRATION CONTROL The bus request bus grant and bus grant acknowledge signals form a bus arbitration circuit to determine which device becomes the bus master device In the 48 pin version of the MC68008 and 68 000 no pin is available for the bus grant acknowledge signal this microprocessor uses a two wire bus arbitration scheme All M68000 processors can use two wire bus arbitration MOTOROLA M68000 8 16 32 BIT MICROPROCESSORS USER S MANUAL 3 5 Bus Request BR This input can be wire ORed with bus request signals from all other devices that could be bus masters This signal indicates to the processor that some other device needs to become the bus master
23. t Destination ASd Dx Dy ASd lt data gt Dy ASd lt ea gt Bcc If condition true then PC d PC Bcc lt label gt BCHG lt number gt of Destination Z BCHG Dn lt ea gt lt number gt of Destination bit number gt of Destination BCHG lt data gt lt ea gt BCLR bit number of Destination Z BCLR Dn lt ea gt 0 bit number of Destination BCLR lt data gt lt ea gt BKPT Run breakpoint acknowledge cycle BKPT lt data gt TRAP as illegal instruction BRA PC d gt PC BRA lt label gt BSET lt bit number gt of Destination Z BSET Dn lt ea gt 1 bit number gt of Destination BSET lt data gt lt ea gt BSR SP 4 gt SP PC SP PC d PC BSR lt label gt BTST bit number gt of Destination Z BTST Dn lt ea gt BTST lt data gt lt ea gt DBcc If condition false then Dn 1 Dn DBcc Dn lt label gt If Dn z 1 then PC d PC MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 11 Table 2 2 Instruction Set Summary Sheet 2 of 4 Eon Source Destination gt Destination Immediate Data Destination Destination EORI to SR If supervisor state EORI data SR then Source SR SR else TRAP E Rx Ry EXG Dx Dy EXG Ax Ay EXG Dx Ay EXG Ay Dx EOR G EXT Destination Sign Extended Destination EXT WDn extend byte to word EXT LDn extend word to long word ILLEGAL SSP 2 5 S
24. the halt signal Reset RESET The external assertion of this bidirectional signal along with the assertion of HALT starts a system initialization sequence by resetting the processor The processor assertion of RESET from executing a RESET instruction resets all external devices of a system without affecting the internal state of the processor To reset both the processor and the external devices the RESET and HALT input signals must be asserted at the same time Halt HALT An input to this bidirectional signal causes the processor to stop bus activity at the completion of the current bus cycle This operation places all control signals in the inactive state and places all three state lines in the high impedance state refer to Table 3 4 When the processor has stopped executing instructions in the case of a double bus fault condition for example the HALT line is driven by the processor to indicate the condition to external devices Mode MODE 68 001 68 000 The MODE input selects between the 8 bit and 16 bit operating modes If this input is grounded at reset the processor will come out of reset in the 8 bit mode If this input is tied high or floating at reset the processor will come out of reset in the 16 bit mode This input should be changed only at reset and must be stable two clocks after RESET is negated Changing this input during normal operation may produce unpredictable results MOTOROLA M68
25. the location of the exception vector table in memory to support multiple vector 2 2 M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL MOTOROLA tables The SFC and DFC registers allow the supervisor to access user data space or emulate CPU space cycles 31 16 15 0 AT SUPERVISOR STACK SSP POINTER 15 87 0 1 CCR SR STATUS REGISTER 31 0 VECTOR BASE REGISTER SFC ALTERNATE FUNCTION prc CODE REGISTERS Figure 2 3 Supervisor Programmer s Model Supplement MC68010 2 1 3 Status Register The status register SR contains the interrupt mask eight levels available and the following condition codes overflow V zero Z negative N carry C and extend X Additional status bits indicate that the processor is in the trace T mode and or in the supervisor S state see Figure 2 4 Bits 5 6 7 11 12 and 14 are undefined and reserved for future expansion SYSTEM BYTE USER BYTE TRACE MODE EXTEND SUPERVISOR NEGATIVE CONDITION ZERO STATE CODES OVERFLOW INTERRUPT ha CARRY Figure 2 4 Status Register 2 2 DATA TYPES AND ADDRESSING MODES The five basic data types supported are as follows 1 Bits 2 Binary Coded Decimal BCD Digits 4 Bits 3 Bytes 8 Bits 4 Words 16 Bits 5 Long Words 32 Bits MOTOROLA M68000 8 16 32 BIT MICROPROCESSOR USER S MANUAL 2 3 In addition operations on other data types such as memory addresses status word
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