Infineon Microcontrollers
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1. Infineon Infineon Microcontrollers C16x Family Comparison please refer to current version of Data Sheet User s Manual and Errata Sheet Comparison C164 OTP ROM C164CI 8E C164CI 8R Type OTP For Remarks Step Ax Bx Cx Dx Ax Cx 1 Documentation aor Sarua an see current errata sheet P internal external lines separated ADC connected 3 Vpp Vss lines alias to internal supply via double bond v 4 int ext ADC choke device wa wa 5 internal external supply connected via ring y FMC ininrovements structure separate supply for ADC i i 6 Reset 7 et ao Internal ROM memory cell 003Eh Reset Configuration v Single ChipMode Reset Configuration has to be configured in the ROM mask at address ingk chip mode solution for C164CI 8R only ifbitCM 9 003Eh see Documentation Update in the current Errata Sheet 8 Single Chip Mode Reset i gk aac ea v v C164CI 8R Single Chip Mode Reset only if bit CM 0 Default configuration 5 x Default Configuration and software setting of register CLKCFG 001 Prescaler Mode fepu fosc 2 ites es Pd RSTCON s SALSEL 01g CSSEL 10g No segment address and chip select lines luring Reset _ os single chip mode After EINIT the Unlock Sequence is necessary to change WRC Ip SYSCON WRCFG On i e WR BHE RSTCON BTYP 11 BUSCONO BTYP 11g i e 16 bit MUX bus2. SMOD no While EA Low Modification of system configuration in register RSTCON a by software n n 10 during Reset After EINIT the Unlock Sequence is necessary to change v Startup configuration during reset on port 0 ext bus mode RSTCON i 2048 TCL extended duration may be useful e g to provide additional settling for external configuration 11 Reset Prolongation Bitfield RSTLEN in register RSTCON v signals at high CPU clock frequencies 12 Bootstrap Loader Rote A TON v v v PullDown for Port 0 pin 8kOhm without external load see AP1637xx 13 Single Chip Reset EA High same as lt s v PullDown for RD pin 2kOhm without external load see AP1637xx Activation RD tied to LOW Bus Mode Reset ifbitCM 9 Note Max BSL baudrate depends on fepy after reset default fosc 2 To verify the OTP contents the OTP read sequence has to be used OTP programming CHM enabled by default in BSL mode see User s Manual OTP Programming Example 14 when EA High Single chip Mode m v m OPCTRL 0x0003 enable module 1st OPAD 0x7F00 address in OTP OPCTRL 0x0002 enable module RD active OPCTRL 0x0003 enable module varl OPDAT read current data 0A03h 0A04h Cx OAOxh High Byte Basic Type Low Byte Chip Generation 12 Registers a OATH 0A02h daoen _oaosh f Sx 1BOxh _ Cx with CAN Sx without CAN 16 IDMEM IDPROG 4010h 9340h 1010h 0000h Memory Identification Programming Voltage 17 fopymax Vpp
3. 5V MHz 20 3 5 18 Variable Frequency Pin P3 15 CLKOUT FOUT s Can be enabled only when SYSCON 8 CLKEN 0 Output Register FOCON enable alternate function P3 15 1 DP3 15 1 19 On Chip Memory 20 XRAM 2Kbytes 0x00E000 0x00E7FF 2 Kbytes 2 Kbytes to enable XRAM bit XPEN in register SYSCON has to be set before execution of EINIT 21 Ext Bus Interface 22 ksi switch Wace ee v selected with BUSCONx 11 1 Default compatible mode with BUSCONx 11 0 23 Early Write er eee ae v selected with BUSCONx 8 1 Default compatible mode with BUSCONx 8 0 24 Interrupts Alternate Interrupt The input source for the fast external interrupts controlled via register EXICON can be EXISEL bs 28 Inputs v v v derived either from the associated port pin EXnIN or from an alternate source 26 EXI0SS CAN_RxD Int Control CC8IC v v v 27 EXI2SS RxD0 Int Control CC10IC v 28 EXI3SS SCLK Int Control CC11IC v 29 CAPCOM Units see see erratum CAPCOM 4 30 CAPCOM2 Port 1H can be used as CC24 27 Comp Output wA CAPCOM SW Access to PIH overwrites CAPCOM HW Settings 31 Registers CCx CCxIC CCMy Pins available 8 16 4 VO 4 I 16 8VO 8 16 4 10 4 I 32 CAPCOM6 Functional differences lead to application restrictions V1 0 V3 0 V3 1 V5 0 cca ane Clee ami CAP COMC Fon ETA corrected block commutation table 33 for left rotation too v corrected for Rotate Left 34 Trap Control for CAPCOM6 Timers wA TRCON
4. I 8E OTP step CA zero match but on period match too In center aligned mode with every zero match of Timer T12 all channels are reset to their initial states A e C164Cl SI 8R ROM all existing steps Necessary exception to feature reset with zero match A e C164Cl SI LM ROMless all existing steps If a compare match for a channel occurs together with zero match of T12 this channel is always set to its active state C167E3 BondOut lf a compare match of a channel happens simultaneously with a period match of T12 this channel is always reset to inactive state Initial values in COINI Bits CC6MCON 0 5 now have a shadow latch as well and for update bit STE12 is to be set B The automatic capture on channel 0 in block commutation mode will now generate an interrupt by setting bit CC6IR in CC6IC with every new Hall Pattern please refer to User s Manual C164CI Version 1 1 1998 08 Figure 17 10 or User s Manual C164 1999 09 V 2 0 V5 e C164CI 8EM since step DA new switches TT12DIS and TT13DIS available e C164CM 4EF outputs in case of trap condition CTRAP can now be switched to e C164CM 4RF initial values when TT12DIS or TT13DIS is set to 1 standard commutation tables have been implemented for both turning directions i e with zero degrees phase shift In general e Shadow latch transfers or update from shadow latches respectively in edge aligned mode take place with period match of T12 e After a sh
5. TRENS 0 TT13DIS TT12DIS enhanced CTRAP function additional switch TT12DIS Trap function for Timer T12 is disabled 35 Watchdog Timer 36 WDTCON WDTCON 7 WDTPRE v WWDTCON 7 1 enables an additional prescaler by 2 for the WDT input clock 37 X Peripherals 38 CAN full CAN module CAN1 CAN1 39 P4 Open Drain function wA GAN iniarioca li PEET P4 5 6 The receive and transmit line of the CAN module may be assigned to several port pins of the C16x 40 Dault CAN Fe Gilt Tub dissonisehea 5 P8 0 1 under software control This assignment is selected via bitfield IPC Interface Port Connection in cake antici P8 2 3 register PCIR if bit CCE in register CSR is set Ist 41 CAN register IR char 0xEF02 replaced by PCIR int wa 0XEF02 with bitfield IPC 42 Clock Prescale COntollBIECPS Ininegieai CSR s s CPS 1 Fast mode the input clock is used directly 1 1 The minimum input frequency to achieve a 5 z baudrate of 1 MBaud is f cpy 8 MHz Default compatible mode division by 2 43 Ports Pin Driver Control 44 Special Thresholds PICON register wA 45 P4LIN v a 46 a Edge 2 groups Bus Non Bus Pins register PDCR HLE 47 aa Lich aap each Nibble of Port and Control Lines registers POCONx s O o 48 New Temperature PTCR new vA The temperature compensation is based on a 100 KHz reference clock Compensation see bitfield TCDIV in register PTCR disabled by default SYSCON1 SLEEPCON SYSCONI SLEEP Mode Configura
6. adow latch transfer occurred the effects of new values in CCx registers cannot take place before the next comparison event i e when writing value 0 to a CCx and setting bit STE12 after period match but before zero match of T12 for example the next zero match will cause the transfer but for the comparison still the old value is relevant Yet with the second zero match of T12 after setting STE12 the compare match of that channel will occur together with the zero match e In opposite to that the changing of other shadowed CAPCOM6 registers like the COINI Bits CC6MCON 0 5 possible since V4 of the CAPCOME B will affect the output pins with the very next shadow latch transfer This means for the workaround for 0 and 100 duty cycle as well as for general usage e It is extremely important at which moment in time relatively to T12 matches you trigger updating from the shadow latches by setting STE12 Module Versions of CAPCOM6 V2 1 2001 03 23 DRAFT
7. tion after EINIT Unlock sequence required specific Idle Mode start instruction IDLE 00 Normal IDLE mode 49 Sleep Mode CPU disabled v v 01 SLEEP mode with RTC running Peripherals and WDT disabled 10 Reserved RTC enabled or disabled 11 SLEEP mode with RTC and oscillator stopped 50 Emulation Mode 51 CS Inputs CAN1 P3 9 Comparison C164 OTP ROM May 03 2005 Microcontrollers for Automotive Application Engineering Features Migration C164 Family V2 3 T Infineon technologies Infineon C 16x Fa mily CAPCOM6 Functionality Module version of Used for product CAPCOM6 V2 e C167E2 BondOut outputs in case of trap condition CTRAP are not switched to initial values CC6MCON COINI but to port register P1L instead affects whole P1L i e also COUT63 gt selection for single outputs with bits TRENn in TRCON not useable any more Original concept No distinction between initial values and signal polarities That means the initial values have to be set in such a way additional functional changes in contrast to C164ClI User s Manual V1 1 i e accumulating from version to version that for a bridge circuitry either highside or lowside switches are initially switched on On the other hand a trap condition requires to have all switches OFF e g emergency switch off in case of short circuits V3 e C164Cl 8E OTP step BA BC Update from shadow latches in center aligned mode not only on e C164C
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