FPGA6800 User`s Manual - RTD Embedded Technologies, Inc.
Contents
1. IDAN P2 Pin Signal FPGA6800HR Row Row CN4 Pin CN4_pin_01 1 CN4 pin 02 or GND Controlled by CN4 gnd enable 1 2 CN4 pin 03 3 CN4 pin 04 or GND Controlled by CN4 gnd enable 1 4 CN4 pin 05 5 CN4 pin 06 or GND Controlled by CN4 gnd enable 1 6 CN4 pin 07 7 CN4 pin 08 or GND Controlled by CN4 gnd enable 1 8 CN4 pin 09 9 CNA pin 10 or GND Controlled by CNA gnd enable 2 10 CN4 pin 11 11 12 CNA pin 12 or GND Controlled by CNA gnd enable 2 12 13 CN4 pin 13 13 14 CN4 pin 14 or GND Controlled by CN4 gnd enable 2 14 15 CN4 pin 15 15 16 CNA pin 16 or GND Controlled by CNA gnd enable 2 16 17 CN4 pin 17 17 18 DIGITAL GND 18 19 CN4 pin 19 19 20 DIGITAL GND 20 21 CN4 pin 21 21 22 DIGITAL GND 22 23 CN4_pin_23 23 24 DIGITAL GND 24 25 CN4 pin 25 25 26 DIGITAL GND 26 27 CN4 pin 27 27 28 DIGITAL GND 28 29 CN4 pin 29 29 30 DIGITAL GND 30 31 CN4 pin 31 31 32 DIGITAL GND 32 33 CN4 pin 33 33 34 DIGITAL GND 34 35 CN4_pin_35 35 FPGA6800 User s Manual RTD Embedded Technologies Inc 26 36 DIGITAL GND 36 37 CN4 pin 37 37 38 DIGITAL GND 38 39 CN4 pin 39 39 40 DIGITAL GND 40 41 CN4 pin 41 41 42 DIGITAL GND 42 43 CN4 pin 43 43 44 DIGITAL GND 44 45 CN4 pin 45 45 46 DIGITAL GND 46 47 CN4 pin 47 47 48 DIGITAL GND 48 49 5 VOLTS 2 Amp Max 49 50 CN4 pi2. SRAM Address High This is A16 address bit sent to the SRAM This must be a 16 bit I O instruction such as outpw or inpw in C Table 22 SRAM Address High Register 15 14 13 12 11 10 9 8 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd R R R R R R R R 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd A16 R R R R R R R RW 0 0 0 0 0 0 0 0 FPGA6800 User s Manual RTD Embedded Technologies Inc 17 SRAM Data This is DO D15 data bits read from or written to the SRAM at the address stored in Address Low and Address High registers This must be a 16 bit I O instruction such as outpw or inpw in C Table 23 SRAM Data 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 RW RW RW RW RW RW RW RW 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 Di DO RW RW RW RW RW RW RW RW Control 8 bit I O JP1 This register has the state of the jumpers in JP1 If a jumper is installed it will read low if it is not installed it will read high Table 24 JP1 Status 7 6 5 4 3 2 1 0 JP1 8 JP1 7 JP1 6 JP1 5 JP1 4 JP1 3 JP1 2 JP R R R R R R R R JP2 This register has the state of the jumpers in JP2 If a jumper is installed it will read low if it is not installed it will read high Table 25 JP2 Status
3. CNx_pin_19 o FPGA6800 User s Manual 6 GND RTD Embedded Technologies Inc Table 1 CNx Pin Assignments x 4 5 or 6 Signal Pin Pin Signal CNx pin 21 21 22 GND CNx pin 23 23 24 GND CNx pin 25 25 26 GND CNx pin 27 27 28 GND CNx pin 29 29 30 GND CNx pin 31 31 32 GND CNx pin 33 33 34 GND CNx pin 35 35 36 GND CNx pin 37 87 38 GND CNx pin 39 39 40 GND CNx pin 41 41 42 GND CNx pin 43 43 44 GND CNx pin 45 _45 46 GND CNx pin 47 47 48 GND 5V 2A max 49 50 CNx pin 16 GND Controlled by Jumper Connectors CN4 CN5 and CN6 Pull pulldown Resistors Connectors CN4 CN5 and CN6 provide 10K ohm pullup to 5V or pulldown to ground on all 33 digital input output lines using solder blobs on the bottom of the board The tables below indicate the blob to use for each pin Note Each blob will pullup or pulldown multiple pins Table 2 CNA CN5 and CN6 Solder Blob Assignments CN6 CN5 CN4 Pin Pin CN4 CN5 CN6 1 2 L3 J4 5 6 B2 B10 B6 Fa B5 B9 B1 L 9 10 11 12 LAS 14 115 16 17 18 None 19 20 None 21 22 None 23 24 None B3 BI St 25 26 None 27 28 None 29 30 None FPGA6800 User s Manual RTD Embedded Techn
4. CNx Pin 23 23 50 GND 24 9 CNx Pin 25 25 30 GND 26 51 CNx Pin 27 27 10 GND 28 31 CNx Pin 29 29 52 GND 30 11 CNx Pin 31 31 32 GND 32 53 CNx Pin 33 33 12 GND 34 33 CNx Pin 35 35 54 GND 36 13 CNx Pin 37 37 34 GND 38 FPGA6800 User s Manual RTD Embedded Technologies Inc 23 55 CNx Pin 39 39 14 GND 40 35 CNx Pin 41 41 56 GND 42 15 CNx Pin 43 43 S 36 GND 44 57 CNx Pin 45 45 16 GND 46 37 CNx Pin 47 47 58 GND 48 17 5V 2 A max 49 38 GND 50 59 NC 18 NC 39 NC 60 NC 19 NC 40 NC 61 NC DE 20 NC Mea 41 NC 62 NC 21 NC 42 NC FPGA6800 User s Manual 24 RTD Embedded Technologies Inc IDAN FPGA6800 68 pin D connector Figure 6 Dimensional Drawing of 68 pin D IDAN connector a Dei n a FRONT 68 pin Subminiature D female Module Part Amp 749070 7 Mating Part Amp 786090 7 IDC Crimp 0 354 BACK Figure 7 IDAN FPGA6800 68D Connector Pins 0 000 2 559 FPGA6800 User s Manual RTD Embedded Technologies Inc 25 Table 31 IDAN 68D 68 Pin High Density D Connector female IDAN FPGA6800HR 68D 68 Pin High Density D Connector Female
5. Inc 8 JP1 Position Xilinx UCF file Signal Name 8 JP1 lt 8 gt Table 5 JP2 Signal Assignments JP2 Position Xilinx UCF file Signal Name il JP2 lt 1 gt JP2 lt 2 gt JP2 lt 3 gt JP2 lt 4 gt JP2 lt 5 gt JP2 lt 6 gt JP2 lt 7 gt JP2 lt 8 gt INIIAI Go Po Table 6 JP3 Signal Assignments JP3 Position Xilinx UCF file Signal Name 1 JP3 lt 1 gt 2 JP3 lt 2 gt 3 JP3 lt 3 gt 4 JP3 lt 4 gt LED D1 This tri color LED is connected to the FPGA Individual red blue and green LEDs can be enabled for a total of seven color options plus off Driving the signal low will light the LED tri stating the LED to disable it Table 7 LED D1 Signal Assignments LED Color Xilinx UCF file Signal Name Red led_red Green led_green Blue led_blue FPGA6800 User s Manual RTD Embedded Technologies Inc 9 Board Installation Installing the Hardware The FPGA6800 can be installed into a PC 104 system It can be located above or below the CPU Static Precautions Keep your board in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware Steps for Installing 1 Shut down the PC 104 system and unplug
6. 7 6 5 4 3 2 1 0 JP2 8 JP2 7 JP2 6 JP2 5 JP2 4 JP2 3 JP2 2 JP2 1 R R R R R R R R JP3 This register has the state of the jumpers in JP3 If a jumper is installed it will read low if it is not installed it will read high Table 26 JP3 Status 7 6 5 4 3 2 1 0 0 0 0 0 JP3 4 JP3 3 JP3 2 JP3 1 R R R R R R R R FPGA6800 User s Manual 18 RTD Embedded Technologies Inc DIO Ground Control This register determines if CNx pins 2 16 even will be digital I O or grounds A 0 will make the pins digital I O and a 1 will make them grounds Table 27 DIO Ground Control Register 7 6 5 S 2 1 0 0 0 CN6 CN6 CN5 CN5 CN4 CN4 10 12 14 16 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 2 4 6 8 R R RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Pin 50 This register has the state of Pin 50 of each connector Table 28 Pin 50 Status 7 6 5 4 3 2 1 0 0 0 0 0 0 CN6 CN5 CN4 Pin 50 Pin 50 Pin 50 R R R R R R R R Power Good This register has the state of the 3 3 VDC and 2 5 VDC power good signals These signals will read 1 if the power is good and 0 it the power is bad Table 29 Power Good Status 7 6 5 4 3 2 1 0 0 0 0 0 0 0 2 5 VDC 3 3 VDC R R R R R R R R FPGA6800 User s Manual RTD Embedded Technologies Inc 19 Additional Information Xilinx Spartan II FPGA For
7. SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE FPGA6800 User s Manual RTD Embedded Technologies Inc 31
8. a 12 Detailed Register Description 13 Digital I O CNA 8 bit WO 14 Porti t EIER amas aaa eeh eege A aga saaa eege eeh aaa Sila 14 Port 2 A hese a aaa as ai aa S is e sia 14 POW E EE 14 Port A QUE aaa Ga e aa AE N E aaa Da aso ana 14 Digital I O CNB 8 bit WO 15 ad i MAS U e i AE N EE EFA 15 POW 22 b ia eege eege ee ege eege edel ee 15 ole eebe aa A asa Sai ge aa a ta excl a ee a a a as 15 Port A EE 15 Digital O EN6 8 Dit O coi ias ai bf i a e eta a i a E air 16 Port T DE i i a a A o D a ima Eeer 16 Port 22M i aaa a a aa i a a d m da en 16 Port Mt ein a da aj aaa ee 16 POM A Eege A D a dee eer 16 82054 Counter TMC hse iais aalus su sa sn a i a a sa is i i a 17 128K X16 SRAM 16 bit UD i 17 FPGA6800 User s Manual RTD Embedded Technologies Inc 4 SRAM Addi ss LOW is Aaaa aa e bis 17 SRAM Vee tao a PTS 17 SRAM Dallas EE 18 Control 8 bit WO 18 NI i A e deg 18 2 A e Ee 18 UPS a SM STA tt dee 18 ERA inean A E E E 19 Bil E EE 19 Power Ee EE 19 Additional Information mnn nn ann AAnnnnnnnnnnzzntnnnnnzzn tt 20 XilinX Spartan WE PGA sia a A 20 82054 Timer Counter N i ve iais i aaa aa a G 20 EC 20 dutt le CR 20 DC Chara IeriStiCSi taskas ia aa Inis i a ia a a ea a i a a aan Gaia as 21 Absolute Maximum RatingS aa AA nene rene rre rene 21 DC Input Output Levels crac rana cnn 21 a pede dak tee dain A T 22 IDAN Connector Pin ot si saku a is ni AA E da eee ae ENE
9. more information about the Xilinx XC2S200 FPGA contact Xilinx Inc at www xilinx com The ISE WebPACK FPGA design tool may be freely downloaded from the Xilinx web site 82C54 Timer Counter For more information about programming and interfacing with the 82C54 Timer Counter Chips contact Oki Semiconductor at wwwe okisemi com ISA Bus For more information on the theory and operation of the ISA bus refer to the following books ISA amp EISA Theory and Operation by Edward Solari ISBN 0 929392 15 9 ISA System Architecture by Tom Shanley Don Anderson ISBN 0 201 40996 8 Interrupts For more information about interrupts and writing interrupt service routines refer to the following book Interrupt Driven PC System Design by Joseph McGivern ISBN 0929392507 FPGA6800 User s Manual RTD Embedded Technologies Inc 20 DC Characteristics Absolute Maximum Ratings DIO vin Operating Temp Output Standard 1 DIO Vin DC overshoot must be limited to either 5 5V or 10mA and DC undershoot must be limited to either 0 5V or 10mA 2 DIO pins may be driven to 2 0V or 7 0V provided these voliages last no longer than 11ns with a forcing current no greater than 100mA 3 Inputs are terminated with 330 resistors and protection diodes 4 DIO inputs should not be tied to voltages when the board is not powered FPGA6800 User s Manual RTD Embedded Technologies Inc 21 IDAN External Connect
10. of the fields where applicable An N A for the reset value indicates that the reset value is not applicable read the field descriptions for more information Bits marked as Reserved in the field name are unused and reads will always return their reset value These bits should not be modified during writes for future compatibility Digital I O CN4 8 bit I O Port 1 Out This register holds the data being sent to CN4 pins 1 15 odd Table 9 CN4 Port 1 Output Register 7 6 5 4 3 2 1 0 Pin 15 Pin 13 Pin 11 Pin 9 Pin 7 Pin 5 Pin 3 Pin 1 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Port 2 In This register reads the data from CNA pins 17 31 odd Table 10 CN4 Port 2 Input 7 6 5 4 3 2 1 0 Pin 31 Pin 29 Pin 27 Pin 25 Pin 23 Pin 21 Pin 19 Pin 17 R R R R R R R R Port 3 In This register reads the data from CN4 pins 33 47 odd Table 11 CN4 Port 3 Input 7 6 5 4 3 2 1 0 Pin 47 Pin 45 Pin 43 Pin 41 Pin 39 Pin 37 Pin 35 Pin 33 R R R R R R R R Port 4 Out This register holds the data being sent to CN4 pins 2 16 even Table 12 CN4 Port 4 Output Register 7 6 5 4 3 2 1 0 Pin 15 Pin 13 Pin 11 Pin 9 Pin 7 Pin 5 Pin 3 Pin 1 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 FPGA6800 User s Manual RTD Embedded Technologies Inc Digital I O CN5 8 bit I O Port 1 Out This register holds the da
11. 5 Port 2 putita id 15 Table 5 GN5 Pom S INPUT idi iii o a tan a p a 15 Table 16 CN5 Port 4 Output Register JJ nanna rna 15 Table 17 CN6 Port 1 Output Register nanna 16 Table 18 CN6 elle TE 16 ET Re CIE Port 3 le LE 16 Table 20 CN6 Port 4 Output Register 16 Table 21 SRAM Address Low Register nanna ran 17 Table 22 SRAM Address High Register snanar arana 17 Table 235RAMData EE 18 ET EE 18 BET EE 18 Tabl 26 JPS STATUS L Eisenos ak ege S k a ee o ao Aaa 18 Table 27 DIO Ground Control Register nn 19 Table lie 50 Stats E 19 Table 29 Power Qood StA US K ki asi kata b aa as sa kia Ta sb a ae beets 19 FPGA6800 User s Manual RTD Embedded Technologies Inc 7 Table 30 IDAN 62D 62 Pin Subminiature Connector emalel aaa aaa aa akanai 22 Table 31 IDAN 68D 68 Pin High Density D Connector emale aaa kaka 23 Table 32 IDAN 68D 68 Pin High Density D Connector emale aaa kaka 25 Table 33 IDAN 68D 68 Pin High Density D Connector emale aaa aaa 26 FPGA6800 User s Manual RTD Embedded Technologies Inc 8 Introduction Product Overview The FPGA6800 is designed to provide platform to create any digital I O that is reguired for your application It interfaces with the ISA bus and features a Xilinx Spartan II 200 000 gate FPGA with a 50 MHz oscillator a user installed oscillator 20 user defined jumpers an 82C54 counter timer and two 128K x 8 SRAMs There are three connec
12. 5 pin 39 39 40 DIGITAL GND 40 41 CN5 pin 41 41 42 DIGITAL GND 42 43 CN5 pin 43 43 44 DIGITAL GND 44 45 CN5 pin 45 45 46 DIGITAL GND 46 47 CN5 pin 47 47 48 DIGITAL GND 48 49 5 VOLTS 2 Amp Max 49 50 CN5 pin 16 GND Controlled by Jumper 50 51 68 RESERVED FPGA6800 User s Manual RTD Embedded Technologies Inc 28 Table 33 IDAN 68D 68 Pin High Density D Connector female IDAN FPGA6800HR 68D 68 Pin High Density D Connector Female IDAN P4 Pin Signal FPGA6800HR Row Row CN6 Pin CN6_pin_01 1 CN6 pin 02 or GND Controlled by CN6 gnd enable 1 2 CN6 pin 03 3 CN6 pin 04 or GND Controlled by CN6 gnd enable 1 4 CN6 pin 05 5 CN6 pin 06 or GND Controlled by CN6 gnd enable 1 6 CN6 pin 07 7 CN6 pin 08 or GND Controlled by CN6 gnd enable 1 8 CN6 pin 09 9 CN6 pin 10 or GND Controlled by CN6 gnd enable 2 10 CN6 pin 11 11 12 CN6 pin 12 or GND Controlled by CN6 gnd enable 2 12 13 CN6 pin 13 13 14 CN6 pin 14 or GND Controlled by CN6 gnd enable 2 14 15 CN6 pin 15 15 16 CN6 pin 16 or GND Controlled by CN6 gnd enable 2 16 17 CN6 pin 17 17 18 DIGITAL GND 18 19 CN6 pin 19 19 20 DIGITAL GND 20 21 CN6 pin 21 21 22 DIGITAL GND 22 23 CN6_pin_23 23 24 DIGITAL GND 24 25 CN6 pin 25 25 26 DIGITAL GND 26 27 CN6 pin 27 27 28 DIGITAL GND 28 29 CN6 pin 29 29 30 DIGITAL
13. E a a Sea ea 22 IDAN FPGA6800 62 pin D connechor 0 nn n nn nn tna 22 IDAN FPGA6800 68 pin D connechor 0 nn rna 25 Limited War Vcc ie ai e de conse aa D e o a e boosie ai 228 FPGA6800 User s Manual RTD Embedded Technologies Inc 5 Table of Figures Figure 1 FPGA6800 Block Diagram aa aaa a aaa aaa aa aaa ananasas aaa aaa aaa aaa 4 Figure 2 FPGA6800 Connector and Jumper Locations LL 5 Figure 3 FPGA6800 Board Bottom Solder Blob Locations 6 Figure 4 Dimensional Drawing of 62 pin D IDAN connector cece kaka 22 Figure 5 IDAN FPGA6800 Connector Pins 22 Figure 6 Dimensional Drawing of 68 pin D IDAN connector eee ee aka 25 Figure 7 IDAN FPGA6800 68D Connector Pins 25 FPGA6800 User s Manual RTD Embedded Technologies Inc 6 Table of Tables Table 1 CNx Pin Assignments x 4 5 OF G nanna nr nn 6 Table 2 CN4 CN5 and CN6 Solder Blob Assignments ss nanna 7 Table 3 CN7 Pin Assignments cn a cnn rca saunaan Au aaiae a iaaa adneu daah A Nona 8 Table ART te lu 8 BETREIT 9 Table 6 JP3 Signal Aesignments aaa aaant aaeeea aaa aaa ania aaa aaa aaa aaa aaa 9 Table 7 LED D1 Signal Assignment 0 nn nn nnrn ann nn nanna nn 9 Table 8 FPGA6800 I O Map anna ANKA AN aa aaa aaa aaa 13 Table 9 CNA Port 1 Output Register nn 14 Tables TOSGNA el le e 14 Table 11 CN4 Port 3 Input 14 Table 12 CN4 Port 4 Output Register nanna 14 Table 13 CN5 Port 1 Output Register nanna 15 Tabie 14 GN
14. FPGA6800 User s Manual Field Programmable Gate Array Board 8 STI RTD Embedded Technologies Inc Real Time Devices Accessing the Analog World BDM 610020061 Rev B FPGA6800 User s Manual RTD EMBEDDED TECHNOLOGIES INC 103 Innovation Blvd State College PA 16803 0906 Phone 1 814 234 8087 FAX 1 814 234 5218 E mail sales rtd com techsupport rtd com Web Site http www rtd com FPGA6800 User s Manual RTD Embedded Technologies Inc 2 Manual Revision History Rev A Initial Release Rev B Changed Signals SA0 SA23 to SA0 SA19 and LA17 LA23 in FPGA Addition of switches noted Added IDAN connector information and pin out Published by RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 Copyright 2006 by RTD Embedded Technologies Inc All rights reserved Specification and features described in this manual may change without notice The RTD Embedded Technologies Logo is a registered trademark of RTD Embedded Technologies dspModule cpuModule and utilityModule are trademarks of RTD Embedded Technologies PC 104 PC 104 Plus and PCI 104 are registered trademark of PC 104 Consortium All other trademarks appearing in this document are the property of their respective owners FPGA6800 User s Manual RTD Embedded Technologies Inc 3 Table of Contents ImtrOAUCIONL Limas ika a a ai aaa aa a a a aaa inet aaa AA a Asas 1 Prodii t Overview iii e a a a a a e aT a
15. GND 30 31 CN6 pin 31 31 32 DIGITAL GND 32 33 CN6 pin 33 33 34 DIGITAL GND 34 35 CN6_pin_35 35 FPGA6800 User s Manual RTD Embedded Technologies Inc 29 36 DIGITAL GND 36 37 CN6 pin 37 37 38 DIGITAL GND 38 39 CN6 pin 39 39 40 DIGITAL GND 40 41 CN6 pin 41 41 42 DIGITAL GND 42 43 CN6 pin 43 43 44 DIGITAL GND 44 45 CN6 pin 45 45 46 DIGITAL GND 46 47 CN6 pin 47 47 48 DIGITAL GND 48 49 5 VOLTS 2 Amp Max 49 50 CN6 pin 16 GND Controlled by Jumper 50 51 68 RESERVED FPGA6800 User s Manual RTD Embedded Technologies Inc 30 Limited Warranty RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD EMBEDDED TECHNOLOGIES INC This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD EMBEDDED TECHNOLOGIES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD EMBEDDED TECHNOLOGIES All replaced parts and products become the property of RTD EMBEDDED TECHNOLOGIES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND
16. TO ANY PRODUCTS WHICH HAVE BEEN DAMAGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD EMBEDDED TECHNOLOGIES acts of God or other contingencies beyond the control of RTD EMBEDDED TECHNOLOGIES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN RTD EMBEDDED TECHNOLOGIES EXCEPT AS EXPRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND RTD EMBEDDED TECHNOLOGIES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL RTD EMBEDDED TECHNOLOGIES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY LASTS
17. a a a 1 Board RE 1 200 000 Gate Xilinx Spartan IEPOGA kaka kaka aaa aaa aa aaa aaa aaa 1 Digital O Gonnectors i Ae ete a Pa ae Mita ab 1 SRAM M tte a o de i appease teases 2 Clock OPINAS yrs vite Satie a ia a 2 USeIJUMP FS sizes creer eben este ee se ee teen dd lati e elek Eau 2 82C54 Timer Counters nn anaAKAAA AN AAAnHAnAEnHAnaEHAnanzzmnAnz 2 Phvsical Attributes iss chosen Saeed iol eh beta een Ae eect ee 2 Available Options rd Bae el eal ketal ahaha dents 2 Getting Technical Support EE 3 Hardware Description vic c c crsesceien cea a i a a aj a a a a a a i i a a 4 Block Di i remi iii taa 4 Connector and Jumper Locations 2 snanar nanna tran aaa aaa aaa 5 External lO Gonnecti k Sii ii a a a i l a 6 Connectors CNA CN5 and CN6 Digital Input Output nee 6 Connectors CNA CN5 and CN6 Pull pulldown Resistors sen 7 Connector CN7 Xilinx JTAG Programming Adapter snanar 8 Jumper JP1 JP2 and JP3 User Jumpers A 8 LED Didi l a i S at 9 Board Wl Le ET 10 stalling the ele VIE 10 Static PrecaltiONS cid io a fe A A a a ia a a Na an ft 10 Steps for Installing Ss se anaana ane aieiaa aaan as Paaa TL e Stacy ete dado 10 FPGA6800 Demo Functional Overview nanna nnn nar n nr nanna armata 11 FPGA6800 Demo VHDL ie ened ius e li a a sa a a a a 11 Board Operation and Progorammimg aaa aaa a aaa aaa aaa aaa aaa Aaaa aa aaa aaa aaa aaa 12 SAM hace EE 12 VO Map Mee tidad a a aaa N
18. configurable as I O or ground One pin jumper selected as I O or ground 16 grounds 5 volts 2 A max fused FPGA6800 User s Manual RTD Embedded Technologies Inc 1 SRAM Memory Two fast 128K x 8 SRAMS can be configured as 128K x 16 or 256K x 8 accessible through the FPGA Clock Options 50 MHz oscillator User oscillator installed in 8 pin DIO socket 3 3V or 5V ISA System Clock typically 8 33 MHz ISA I O Write used for I O register write cycles User jumpers 20 jumpers for user configuration o Two banks of 8 jumpers o One bank of 4 jumpers 82C54 Timer Counters Ge Ze Three 16 bit Timer Counter Channels Fully programmable 10 MHz maximum input frequency Input and outputs connected to FPGA Ge Ze Ge Ze Ge Ze Physical Attributes Ge Ze Size 3 6 L x 3 8 W x 0 6 H 90mm L x 96mm W x 15mm H Weight 0 22 lbs 0 10 Kg Ge Ze lt Temperature o Operating 40 C to 85 C o Storage 55 C to 125 C w Power Requirements o Typical 1 5 W 5 VDC Available Options The FPGA6800 is a general use FPGA module You design your own FPGA or RTD s team of experienced FPGA designers will do custom FPGA designs Please contact RTD Embedded Technologies for more information on custom FPGA designs at 1 814 234 8087 or E Mail sales rtd com FPGA6800 User s Manual RTD Embedded Technologies Inc 2 Getting Technical Support For help with this product or any ot
19. her product made by RTD you can contact RTD Embedded Technologies via the following methods Phone 1 814 234 8087 E Mail techsupport rtd com Be sure to check the RTD web site http www rtd com for product updates including newer versions of the board manual and application software FPGA6800 User s Manual RTD Embedded Technologies Inc 3 Hardware Description Block Diagram Below is a block diagram of the FPGA6800 Primary board components are in bold while external I O connections and jumpers are italicized CN4 33 Digital I O One 5V and 16 Dedicated Grounds CN5 33 Digital I O CN6 33 Digital I O One 5V and 16 One 5V and 16 Dedicated Grounds Dedicated Grounds si 128K x 16 or 256K x 8 SRAM 82C54 User Clock Timer Counter Figure 1 FPGA6800 Block Diagram FPGA6800 User s Manual RTD Embedded Technologies Inc 4 Connector and Jumper Locations The following diagram shows the location of all connectors and jumpers on the FPGA6800 For a description of each jumper and connector refer to the following sections CN5 JP11 Digital I O Jumper S r CN CN6 Digital I O User Oscillator y JP3 8 JP4 umpers JP1 JP2 Jumpers Jumpers JP6 JP10 Jumper Jumper D1 Figure 2 FPGA6800 Connector and Jumper Locations FPGA6800 User s Manual RTD Embedded Technologies Inc 5 000000090070 S 9601 90606 e ie KET Figure 3 FPGA6800 Board Bottom Solder Blob Locations Ex
20. n 16 GND Controlled by Jumper 50 51 68 RESERVED Table 32 IDAN 68D 68 Pin High Density D Connector female IDAN FPGA6800HR 68D 68 Pin High Density D Connector Female IDAN P3 Pin Signal FPGA6800HR Row Row CNS Pin CNS pin 01 1 CN5 pin 02 or GND Controlled by CN5 gnd enable 1 2 CN5 pin 03 3 CN5 pin 04 or GND Controlled by CN5 gnd enable 1 4 CN5 pin 05 5 CN5 pin 06 or GND Controlled by CN5 gnd enable 1 6 CN5 pin 07 7 CN5 pin 08 or GND Controlled by CN5 gnd enable 1 8 CN5 pin 09 9 CNS pin 10 or GND Controlled by CNS gnd enable 2 10 CN5 pin 11 11 12 CN5 pin 12 or GND Controlled by CN5 gnd enable 2 12 13 CN5 pin 13 13 14 CNS pin 14 or GND Controlled by CNS gnd enable 2 14 15 CN5 pin 15 15 16 CNS pin 16 or GND Controlled by CNS gnd enable 2 16 17 CN5 pin 17 17 18 DIGITAL GND 18 FPGA6800 User s Manual RTD Embedded Technologies Inc 27 19 CN5 pin 19 19 20 DIGITAL GND 20 21 CN5 pin 21 21 22 DIGITAL GND 22 23 CN5 pin 23 23 24 DIGITAL GND 24 25 CN5 pin 25 25 26 DIGITAL GND 26 27 CN5 pin 27 27 28 DIGITAL GND 28 29 CN5 pin 29 29 30 DIGITAL GND 30 31 CN5 pin 31 31 32 DIGITAL GND 32 33 CN5 pin 33 33 34 DIGITAL GND 34 35 CN5 pin 35 35 36 DIGITAL GND 36 37 CN5 pin 37 37 38 DIGITAL GND 38 39 CN
21. ologies Inc 7 Table 2 CN4 CN5 and CN6 Solder Blob Assignments 31 32 None 33 34 None 35 36 None 37 38 None 39 40 None b Bie BB 41 42 None 43 44 None 45 46 None 47 48 None 5V 2A max 49 50 B8 B12 B4 Connector CN7 Xilinx JTAG Programming Adapter Connector CN7 provides a connection to the Xilinx JTAG programming adapter The pin assignments for CN7 are shown in Table 3 Note This connector is keyed to ensure proper connection with Xilinx s programming adapters Table 3 CN7 Pin Assignments Signal Pin Pin Signal GND 1 2 3 3V VRef GND 3 4 TMS GND 5 6 TCK GND 7 8 TDO GND 9 10 TDI GND 11 12 N C GND 13 14 N C Jumper JP1 JP2 and JP3 User Jumpers There are three jumper banks that can be defined by the user JP1 and JP2 have eight positions numbered 1 8 and JP3 has four positions numbered 1 4 When the jumper is not installed the signal going to the FPGA is high When the jumper is installed the signal going to the FPGA is low The jumper assignments are as follows Table 4 JP1 Signal Assignments JP1 Position Xilinx UCF file Signal Name 1 JP1 lt 1 gt JP1 lt 2 gt JP1 lt 3 gt JP1 lt 4 gt JP1 lt 5 gt JP1 lt 6 gt JP1 lt 7 gt NIOJ AIIN FPGA6800 User s Manual RTD Embedded Technologies
22. or Pin Out Cables within the IDAN unit provide signal connections between the exterior of the IDAN frame and the headers on the FGPA6800 port P2 P3 and P4 connect to the FPGA6800 headers CN4 CNS and CN6 respectively The pin to pin mappings from IDAN port to FPGA6800 are shown in the following tables IDAN FPGA6800 62 pin D connector Figure 4 Dimensional Drawing of 62 pin D IDAN connector 5 117 REF 000 2 559 62 pin D subminiature female module P N Adam Tech HDT625D mating P N Adam Tech HDT62PD gd ji 304 000 Figure 5 IDAN FPGA6800 Connector Pins FPGA6800 User s Manual RTD Embedded Technologies Inc 22 Table 30 IDAN 62D 62 Pin Subminiature Connector female IDAN 62D 62 Pin Subminiature Connector female FPGA 6800 IDAN P2 CNA CNS amp P3 amp P4 Pin Signal CN6 Row 1 Row 2 Row 3 x 1 2 3 1 CNx Pin 1 1 22 CNx Pin 2 GND 2 43 CNx Pin 3 3 2 CNx Pin 4 GND 4 23 CNx Pin 5 5 44 CNx Pin 6 GND 6 3 CNx Pin 7 7 24 CNx Pin 8 GND 8 45 CNx Pin 9 9 4 CNx Pin 10 GND 10 25 CNx Pin 11 11 46 CNx Pin 12 GND 12 5 CNx Pin 13 13 26 CNx Pin 14 GND 14 47 CNx Pin 15 15 6 CNx Pin 16 GND 16 27 CNx Pin 17 17 48 GND 18 7 CNx Pin 19 19 28 GND 20 49 CNx Pin 21 21 8 GND 22 29
23. ort_3 In Port 3 Inputs pins 33 47 odd 0x030B Port_4 Out Port 4 Outputs pins 2 16 even 82C54 Counter Timer 8 bit I O 0x030C TC COUNTER 0 Counter 0 Register 0x030D TC COUNTER 1 Counter 1 Register 0x030E TC COUNTER 2 Counter 2 Register 0x030F TC CON WORD Control Word Register 128K x 16 SRAM 16 bit I O 0x0310 SRAM Address Low SRAM Address AO A15 0x0312 SRAM Address High SRAM Address A16 0x0314 SRAM Data SRAM Data DO D15 0x0316 Reserved Unused Control 8 bit I O 0x0318 JP1 Read JP1 setting 0x0319 JP2 Read JP2 setting 0x031A JP3 Read JP3 setting 0x031B DIO Ground Control Read Write DIO ground settings for CNA CN5 and CN6 0x031C Pin 50 Read Pin 50 for CN4 CN5 and CN6 0x031D Power Good Read 3 3V and 2 5V power good signals 0x031E Reserved Unused 0x031F Reserved Unused Detailed Register Description The following sections provide a detailed description of the individual registers In the following register description sections each register is described by a register table The first row of the table lists the bits Le D15 through DO The second row lists the field name for each bit The third row lists the properties of that bit R bit can be read W bit can be written to and C bit can be cleared The last row lists the value of the bit after reset The register table is then FPGA6800 User s Manual RTD Embedded Technologies Inc 13 followed by a description of each
24. r which steps the tri color LED through all its colors The SRAM is configured as 128K x 16 and is accessible through 16 bit I O instructions Jumper settings and power good status can be read using I O instructions Connector I O ground switching for pins 2 16 even is controlled by an I O register FPGA6800 User s Manual RTD Embedded Technologies Inc 11 Board Operation and Programming ISA Interface The FPGA attaches directly to the ISA bus and the FPGA6800 Demo is I O mapped The address is fixed at 300H 31Fh All registers are 8 bit except the SRAM registers which are 16 bit I O Map Overview Table 8 shows the I O map of the FPGA6800 I O registers FPGA6800 User s Manual RTD Embedded Technologies Inc 12 Table 8 FPGA6800 I O Map Address Register Name Register Function Hex Digital I O CN4 8 bit I O 0x0300 Port 1 Out Port 1 Output pins 1 15 odd 0x0301 Port 2 In Port 2 Inputs pins 17 31 odd 0x0302 Port 3 In Port 3 Inputs pins 33 47 odd 0x0303 Port_4 Out Port 4 Outputs pins 2 16 even Digital I O CN5 8 bit I O 0x0304 Port 1 Out Port 1 Output pins 1 15 odd 0x0305 Port 2 In Port 2 Inputs pins 17 31 odd 0x0306 Port 3 In Port 3 Inputs pins 33 47 odd 0x0307 Port 4 Out Port 4 Outputs pins 2 16 even Digital I O CN6 8 bit I O 0x0308 Port 1 Out Port 1 Output pins 1 15 odd 0x0309 Port 2 In Port 2 Inputs pins 17 31 odd 0x030A P
25. rt 2 Input 7 6 5 4 3 2 1 0 Pin 31 Pin 29 Pin 27 Pin 25 Pin 23 Pin 21 Pin 19 Pin 17 R R R R R R R R Port 3 In This register reads the data from CN6 pins 33 47 odd Table 19 CN6 Port 3 Input 7 6 5 4 3 2 1 0 Pin 47 Pin 45 Pin 43 Pin 41 Pin 39 Pin 37 Pin 35 Pin 33 R R R R R R R R Port 4 Out This register holds the data being sent to CN6 pins 2 16 even Table 20 CN6 Port 4 Output Register 7 6 5 4 3 2 1 0 Pin 15 Pin 13 Pin 11 Pin 9 Pin 7 Pin 5 Pin 3 Pin 1 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 FPGA6800 User s Manual RTD Embedded Technologies Inc 82C54 Counter Timer The four 8 bit registers in the 82C54 counter timer are directly accessible through I O instructions Please refer to the 82C54 Datasheet from Oki Semiconductor for information on programming the 82C54 timer counters You can download the latest datasheet from www2 okisemi com 128K x 16 SRAM 16 bit I O The two 128K x 8 SRAM parts are configured as one 128K x 16 in the demo application They are assessable through three 16 bit I O addresses SRAM Address Low This is AO A15 address bits sent to the SRAM This must be a 16 bit I O instruction such as outpw or inpw in C Table 21 SRAM Address Low Register 15 14 13 12 11 10 9 8 A15 A14 A13 A12 A11 A10 A9 A8 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A AO RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0
26. ta being sent to CN5 pins 1 15 odd Table 13 CN5 Port 1 Output Register 7 6 5 4 3 2 1 0 Pin 15 Pin 13 Pin 11 Pin 9 Pin 7 Pin 5 Pin 3 Pin 1 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Port 2 In This register reads the data from CN5 pins 17 31 odd Table 14 CN5 Port 2 Input 7 6 5 4 3 2 1 0 Pin 31 Pin 29 Pin 27 Pin 25 Pin 23 Pin 21 Pin 19 Pin 17 R R R R R R R R Port 3 In This register reads the data from CN5 pins 33 47 odd Table 15 CN5 Port 3 Input 7 6 5 4 3 2 1 0 Pin 47 Pin 45 Pin 43 Pin 41 Pin 39 Pin 37 Pin 35 Pin 33 R R R R R R R R Port 4 Out This register holds the data being sent to CN5 pins 2 16 even Table 16 CN5 Port 4 Output Register 7 6 5 4 3 2 1 0 Pin 15 Pin 13 Pin 11 Pin 9 Pin 7 Pin 5 Pin 3 Pin 1 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 FPGA6800 User s Manual RTD Embedded Technologies Inc 15 Digital I O CN6 8 bit I O Port 1 Out This register holds the data being sent to CN6 pins 1 15 odd Table 17 CN6 Port 1 Output Register 7 6 5 4 3 2 1 0 Pin 15 Pin 13 Pin 11 Pin 9 Pin 7 Pin 5 Pin 3 Pin 1 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Port 2 In This register reads the data from CN6 pins 17 31 odd Table 18 CN6 Po
27. ternal I O Connections The following sections describe the external I O connections of the FPGA6800 Connectors CN4 CN5 and CN6 Digital Input Output Connectors CN4 CN5 and CN6 provide up to 33 digital input output lines along with a 5V pin and ground pins All I O pins go to the FPGA through pull up down resistors and switches which are open during configuration This allows the pull up down resistors to control the level of the I O pins until the FPGA is operational The signal names reflect the signal names in the Xilinx UCF file with the device pin out All three connector pin outs are identical Note Pin 1 can be identified by a square solder pad Pins 2 50 have round solder pads Table 1 CNx Pin Assignments x 4 5 or 6 Signal Y 5 Signal CNx_pin_01 CNx_pin_02 or GND Controlled by CNx_gnd_enable_1 CNx_pin_03 CNx_pin_04 or GND Controlled by CNx gnd enable 1 CNx_pin_05 CNx pin 06 or GND Controlled by CNx gnd enable 1 CNx pin 07 CNx pin 08 or GND Controlled by CNx gnd enable 1 CNx pin 09 CNx pin 10 or GND Controlled by CNx gnd enable 2 CNx pin 11 CNx pin 12 or GND Controlled bv CNx gnd enable 2 oo CNx_pin_13 CNx_pin_14 or GND Controlled by CNx_gnd_enable_2 CNx_pin_15 al CNx pin 16 or GND Controlled by CNx gnd enable 2 N CNx_pin_17 GND
28. the power cord 2 Ground yourself with an anti static strap Set the Jumper and solder blobs as described in the previous chapter so Line up the pins of the FPGA6800 s PC 104 connectors with the corresponding bus connectors of the stack 5 Apply pressure to both bus connectors and gently press the board onto the stack The board should slide into the matching bus connectors Do not attempt to force the board as this can lead to bent broken pins 6 Attach any cables to the FPGA6800 7 If any boards are to be stacked above the FPGA6800 install them 8 Attach any necessary cables to the PC 104 stack 9 Re connect the power cord and apply power to the stack 10 Boot the system and verify that all of the hardware is working properly FPGA6800 User s Manual RTD Embedded Technologies Inc 10 FPGA6800 Demo Functional Overview FPGA6800 Demo VHDL Delivered with your FPGA6800 is a demo VHDL application It has the following features ls Each connector is configured as 16 inputs and 16 outputs that can be read or written through I O instructions a Pins 1 16 are configured as outputs b Pins 17 47 odd are configured as inputs The 50 MHz oscillator is divided by 8 in one of the CLKDLLs to get 6 25 MHz The three 16 bit timers in the 82C54 are cascaded and set to mode 3 by the example software Dividers are set to 500 250 and 50 to provide a 1 Hz clock The FPGA uses the 1 Hz clock to clock a 3 bit counte
29. tors that provide a maximum of 33 I O pins each for a total of 99 I O Board Features 200 000 Gate Xilinx Spartan II FPGA o Ei Oh EE Er OO ooo o Xilinx Spartan II System level features SelectRAM hierarchical memory 16 bits LUT distributed RAM 57 344 bits of configurable block RAM Fast interfaces to external RAM Low power segmented routing architecture Full readback ability for verification observability Dedicated carry logic for high speed arithmetic Efficient multiplier support Cascade chain for wide input functions Abundant registers latches with enable set reset Four dedicated DLLs for advanced clock control Multiply by 2 output cascade 2 for multiply by 4 0 90 180 and 270 degree phase outputs Divide by 1 5 2 2 5 3 4 5 8 or 16 output Four primary low skew global clock distribution nets IEEE 1149 1 compatible boundary scan logic 16 high performance interface standards Zero hold time simplifies system timing Fully supported by powerful Xilinx development system o e o e ISE WebPACK free download from http www xilinx com Foundation ISE Series Fully integrated software Alliance Series For use with third party tools Fully automatic mapping placement and routing Digital I O Connectors J K i d La e o O o o o 99 total ESD protected I O lines Human body model 3 identical I O connectors each with 24 dedicated I O Two groups of 4
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