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netX Design-In Guide

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4. 70 4 5 1 sane elit 70 4 5 2 71 4 5 3 eps ____ 72 4 6 External tamm ai aia 74 456 74 4 6 2 ra 81 4 7 Hostlnterface a adn ettet etis 84 47 1 c r 85 427 2 ExtensioniBus Mode dne ree and Sc ed eae 93 4 7 3 Multiplex Mode coner A E 94 4 7 4 External pull ups pull downs unused 96 4 68 OARS eT 97 49 USB at cute 98 4 9 1 Device u pies dodo Reden 98 AQ 2 FOST MOGG 2s eine 100 4 10 Ethernet Interface Aa Sau atau RATS Eaa 102 4 031 Twisted ee dated iia See 102 APT O2 LT EC 105 4 10 3 Ethernet PHYS uriused niente 113 4 10 4 Ethernet Status LEDS
5. eie 39 21 2 sk 41 2 68 PROFIBUS sree orem ATAT 43 2 9 MMC SD Card 45 2 105 232 47 2 11 USB Device La naa huqman a iu Aa shaq 49 2432 USB Host Mode nere Hk elle 51 2 13 Embedded Trace Macrocell 53 2 14 ECD Interface ii pm ie ette iin ea ul eben netten 55 3 MEI 59 3 1 Operating ne rere e reete 59 3 2 Third Party Operating 5 8 1 60 3 3 Memory Requirements of Hilscher 61 4 62 4 11 LED 62 4 22 lt e 65 4 3 Crystals Clock generators ar een 66 43 1 System Clock sha el tO utet es SL 66 4 322 Real Time 61 101 67 4 4 Power On Reset and Resetln n unn 69 4 5 Debug and Test Interfaces
6. Figure 16 netX100 500 Basic Circuit RDY RUN USB SEC MEM SPI FLASH 081106 2 Revision 2 English 2012 10 Released Public netX Design In Guide 100 500 19 158 netX100 500 Quick Start 13 4 9 r e L Jo UUOO J LIOSILULWWA aea XYOWSN en 5 LLOZ OL VC eig oIseq OOS OOLXIOU nueuosjeseo Seunew SWEN 000 0122 00SXLAN OYOWN zi saw Sam ynan ees G WS 95 54 54 WAN 54 150 za WW u mE 3 SH sod Wa INN 5 SAL Woo WaN TAN D N WoC d WW 29 TWIN Sr T 1 _ rea 0 295 uswan INN 9 1 os usan a Zoos WS 9E i LG W3N YE n _ xvm EM ew wan WS 58 E Ley wan 2 X lav wan 06 Bi V TG WS 61 a d gv WAN GC ERN civ wan en QU viv Wan E EU
7. 152 MERO LII OMEN RD 152 6 2 Memory 2 edd ted eode dee ded de tee 152 6 3 15 155 6 4 LISHOTFIQUIES eet te tbt rede bebe 156 7 158 netX Design In Guide 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Introduction 4 158 1 Introduction 1 1 About this Document This document is directed to hardware developers creating a hardware design with a communication controller of the Hilscher netX family It does not explain netX technology and features which is covered by the corresponding Technical Data Reference Guides It describes the standard circuitry around all netX interfaces like memory interface SDRAM FLASH USB UARTs XMACs Ethernet and field bus LCD as well as power supply reset and clock circuits along with the standard netX I O resources PIOs GPIOs that have been assigned a default functionality at Hilscher This includes Status LEDs control signals and sync signals for RTE applications Although the system designer is basically completely free to select any available I Os for purposes it is important that he complies with the standard port definitions whenever loadable Firmware from Hilscher is to be used as this kind of
8. 114 4 105 RealTime Ethernet idee aa 115 netX Design In Guide 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Introduction 3 158 4 44 Fieldbus Interface en Rete f ERE PATER ER EG THO PUNIRE 118 4 111 AS interface Master u oit netter poet Eee ndi aceto Pee aedes De Ex Re 120 411 2 CANopen Interface E Rr XU Headend idee 121 4 11 3 C Int rface eee ete gi cnaseapeedeaphassddseantiendaasendonsdeessusadee 122 4 11 4 CompoNet Interface nette me dne Eno 123 4 14 5 DeviceNet Interface eden eei o Eee 124 4111 6 PROFIBUS Interface 125 4 11 7 Fieldbus Status 02 4 1 QU a h YG h a T aus 126 4 42 AID Converter BD ed eae ies 127 4 13 D il evade edad cali ede 130 4 14 Encoder Interface eO e tuo ets eee ea bite 132 4 45 LCD ua D pe 134 4 16 Touch Panel Interface anna nno 135 Lem 137 4 18 Power Supply ite edd
9. Figure 20 netX100 500 Basic Circuit Unused netX Parts netX Design In Guide 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start Bill of Materials Page 1 REF DES PART Type PART NAME C101 EEPROM AT88SC0104CA SU C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Flash Memory AT45DB321D SU C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 C106 Ceramic Capacitor 22 pF 50 V 0603 C107 Ceramic Capacitor 22 pF 50 V 0603 C108 Ceramic Capacitor 1 nF 50 V 0603 G101 Crystal ABM7 25 000 MHZ D2Y T K1 Microcontroller netX100 500 P101 LED HSMF C156 Q101 Reset MAX809SEUR T R101 Resistor 15 kO 63 mW 0603 R102 Resistor 15 kO 63 mW 0603 R103 Resistor 1 27 kO 63 mW 0603 R104 Resistor 1 27 kO 63 mW 0603 R105 Resistor 220 O 63 mW 0603 R106 Resistor 220 63 mW 0603 R107 Resistor 10 kO 63 mW 0603 R108 Resistor 10 kO 63 mW 0603 R109 Resistor 10 kO 63 mW 0603 R110 Resistor 10 kO 63 mW 0603 R111 Resistor 1 5 kO 63 mW 0603 R112 Diode SN65220DBVT R114 Resistor 24 63 mW 0603 R115 Resistor 24 63 mW 0603 X101 USB B KUSB BS 1 N BLK X102 Pin Header 2 pin X103 Pin Header 2 pin Table 1 BOM Basic Circuit Page 1 Page 2 REF DES PART Type PART NAME C201 SDRAM 1842832200C1 7TLI C202 Ceramic Capacitor 100
10. 1 85 Figure 56 netX DPM Motorola Type Interface 86 Figure 57 Texas Instruments TMS320x2833x 16 Bit Non Multiplexed 87 Figure 58 netX DPM Intel Type Circuits 88 Figure 59 netX DPM Motorola Type Interface Circuit eene 88 Figure 60 netX ISA Bus Interface 89 Figure 61 netX Internal Chip Select Generator Circuits 91 Figure 62 netX Extension Bus Intel M Type Interface Circuit 8Bit non Multiplex 93 Figure 63 netX Extension Bus Intel type Interface Circuit 16Bit non 94 Figure 64 netX DPM Motorola Type Interface Circuits non 94 Figure 65 netX DPM Intel Type Interface Circuit Multiplexed l annassa 95 Figure 66 netX Extension Bus Motorola Interface Circuit M ltiplexed cresce rtt eo ceti ee tn igi decre ent 96 netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Reference Section 157 158 Figure 67 netX100 500 UVARTU una ns Eia e Nea ie ia ia 97 Figure 68 netX100 500 UARTO 97 Figure 69 netX100 500 USB DOWNstream Port Device
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12. L 43 OL 6 8 Z 9 5 v 4 3 TEE zur p WISYSISHEH 66 69 abed OLLdO 9393 LANYSHL gt Buppap 21020 21 009 00 SENEN OWEN JOP eq ueo Y Old Aue o ueo q31 LOW pue 0X4 bed E 2 qr A DR 4 PN LX 225 T 2 2294 IH Se s ones Our 1 gt k zL eos T BI WOO 1 1 1 1 transistors close to netX100 500 and AC termination R501 R510 and R17 R526 close to the The second figure shows the circuit on the AFBR 5978Z side Important is to place the level level transistors netX100 500 Quick Start 1 1 1 1 I i 9754 lt mel woo as In 28269 UV s oat B ze ze 90984 P OCSH 6154 y 8194 SA 0Sd T
13. M 33 Figure 26 CANopen 1 2 ett BEE y E Re DERE emer eine d ua AL T 35 Figure 27 CC Link Circuit een sen dee ee de rane ran dee 37 Figure 28 CompoNet r suwas asap 39 Figure 29 DeviceNet Circuits ea LH Ionen 41 Figure 30 CE ERR EFE RAMS rar bet kennst 43 Figure 31 netX100 500 MMC SD Card SPI 45 Figure32 UART RS232 Gireuil 35 3 tei Lese Epi te poetae ton 47 Figure 33 USB Device Mode Circuit 5 49 Figure 34 USB Host Mode Circuit ea ir redo ne aan Le td e Ped ie u Ix beein 51 Figure 35 BOM USB Host Mode nnne en nnns 52 Figure 36 ETM Circuit Ra Al De reip e Wawan ute lesben 53 Figure 37 LCD Interface Circuits icon cioe conan eno nee ET 55 Fig re 38 Touch Panel CiICUit ioter ee e EXER ER 56 Figure 39 netX100 netX500 RDY RUN 63 Figure 40 Sample Schematic netX100 500 Secure 65 Figure 41 netX100 500 System Oscillator Circuit
14. 9 Hia S0FO ZINA 877 L 3 oan ves VOvL N IM d 201 a POL oz POL oz en a 509 Lovo Ades 00S 00LX S u __ 6 Ul 4amod NENG A Addns vL L eL 6 8 Z 9 S L Figure 19 netX100 500 Basic Circuit Power Supply netX Design In Guide netX 100 500 Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX100 500 Quick Start 22 158 lt m a 9 gt ae 29 gg e 8 SEEE SEE SEEE KRESS KBSS5 A885 585 8 5 8935 HARE oz 8o 5 V a x x x 888225 8 8E 28 gle 55555 8 5 S FEES 9 a s a ds gt 3 NP 2 p 25 Bu o amp 5 n o BD 2 s 24 5 La gu e 0 x gt a 2 amp SIRI 2 o ce 2 55 8 8 88 X g 7 6 4 5 3 5 BES amp og 2 20 iz 4 e B HE 84 1 g g 3858 2 ar le O lt a gt
15. 99 Figure 70 netX100 500 USB DOWNstream Port Device Mode Advanced 100 Figure 71 netX100 500 USB UPstream Port Host Figure 72 netX100 500 2 Channel Ethernet Circuit Twisted Pair emen Figure 73 netX Single Channel Ethernet Circuit Twisted Figure 74 netX100 500 Ethernet Circuit Fiber Figure 75 netX100 500 Ethernet Circuit Fiber Figure 76 netX Ethernet Circuit Fiber Optic Component Placement Figure 77 netX Ethernet Circuit Fiber Optic Component Placement with AC Termination 110 Figure 78 netX100 500 Interface Fiber Optie Transceivers pisicii nn 111 Figure 79 netX100 500 Ethernet Circuit PHYS Not 113 Figure 80 netX100 500 Ethernet Status LED Circuit 114 Figure 81 netX RTE Status LED 5 116 Figure 82 1 100 500 Fieldbus Interface un eni need nern 119 Figure 83 Basic Circuit for netX 5 120 Figure 84 Basic Circuit of netX CANopen Interface 7 121 Figure 85 Basic Circuit for netX CC Link 122 Figure 86 Basic Circuit for netX CompoNet nennen nnns 123 Fig
16. 2 ta S 40n 2kV PHY_EXTRES 19 C15 An 2kV 7 o GND PHY_ATP 9 PE netX100 500 GND Figure 72 netX100 500 2 Channel Ethernet Circuit Twisted Pair netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 103 158 Component Value Tolerance Rating R1 R2 1000 100 MHz 200 R3 R4 5 R6 R7 R8 500 1 125 mW R9 R10 R11 R12 R13 R14 100 1 63 mW R15 R16 R17 R18 R19 750 1 63 mW R20 R21 R22 R23 12 4 kO 196 63 mW C1 C3 C5 C6 C7 C8 100 nF 6 3V C2 C4 10 uF 6 3V C9 C10 C11 C12 10 nF 20 C13 C14 10 nF 2 kV C15 1 nF 2 kV H1 H2 H1102 HX1188 Pulse Eng TS6121C Bothhand Table 33 Ethernet Circuit Component Specification The selected Ethernet transformer s H1 H2 the Table 33 lists three examples must be 1 1 ratio types with center tap and should be symmetric which means that transmit and receive path may be swapped This is necessary to support the auto crossover feature that is mandatory for most Real time Ethernet protocols Instead of a separate transformer secondary side resistors 75 and RJ45 jack integrated jacks can be used that combine all components plus Status LEDs in the housing of the jack They are available as single channel or 2 channel models Hilscher commonly uses a 2 c
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18. yeuosiesec nm 1 i 1 9ysd31 x 21 509 fr 9014 M D 2 T zZ Wis I 1 I I 1 1 i ZHNOOI un 0001 Z 2 E LLOSNSOOSdON t 2702 3772 5080 80 0 2019 X coll eros ed i i D 709 aNoost t 140 Xu0faov E z gt gt gt ax xv 8 zano 77908 4 Y 5 60d T SY 56427 ALB STVSLUINdA S0 LO M LO M COCO 18157 5 A a ATA a TE a Han EOLM a Y TREE t 21 Y ix i FELV OLO 3 L TZLOIGOV un oz LOLX OF N als 510 lt l lt Xr ax 109 avoosi 709 aNoos 05 S 1 Y 4 zano 4001 zx 8 199 lt 1 zaon M an 9013 I E 013 GOLM E 109 SI Neos Sd IZSLON ANI TL 3109 aNoost SADIZSZON 040 2090 ola hi 7014 qe o ESE E bora k St ao LOY 7 lal T E 4001 5050 25 x L om 709 AS OSI I VV IOSI vL L eL 6 Z 9 5 v L Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public net
19. 34 EXT 33 EXT D10 39 EXT D11 38 EXT 012 37 EXT 013 42 EXT 014 41 EXT 015 UUUUUUUUOCUOUO RON O 73 _ 70 _ 1 69 _ 2 HIFPIO 66 _ 65 _ 4 64 _ 5 61 _ 6 60 57 8 56 EXT A9 HIFPIO 53 EXT A10 HIFPIO_50 EXT A11 HIFPIO_49 EXT A12 HIFPIO 48 EXT A13 HIFPIO 54 EXT A14 HIFPIO 55 EXT A15 HIFPIO_58 EXT A16 HIFPIO_59 EXT A17 _62 EXT A18 HIFPIO 63 EXT A19 HIFPIO 67 A20 _68 EXT A21 HIFPIO 71 EXT A22 HIFPIO 72 A23 51 EXT CS0 80 EXT CS1 79 EXT C82 HIFPIO 84 EXT 43 EXT 35 EXT ALE 45 EXT 44 52 EXT RD 46 EXT RDY 47 EXT RQ R302 d HIFPIO 36 1 2 TCLK 40 10k MICRO NETX500 2210 000 GND Figure 12 Unused Host Interface Note If the Host Interface is not connected it is recommended to configure the pins in PIO mode output by software or connects pull up pull down resistors The reason is that the Host Interface pins are floating because they do not have internal pull up or pull down resistor More about Host Interface circuits can be found on gt Page 84 Chapter 4 7 netX Design In Guide 100 500 DOC081106ANO2
20. n 10660 5 1 onr tay Pet amp 2 wo ar qo Y N 9 aoe vo u i Ar ey v wool lt aoi 0Qv 0 ON 8 Z aaa 00 Ene P 2022 3 oz 8 av loss i 5 N OQV Iz V COCH VY 81023 N oav vada IN amp OQv I Fax 71 290 Tr z am v0cd seruva 2001 2090 seva 1024 LOZO 00SX 98U 064 vole OL 6 8 Z 9 9 v L Figure 38 Touch Panel Circuit netX Design In Guide netX 100 500 Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX100 500 Quick Start 57 158 Bill of Material Page 1 REF DES PART TYPE PART NAME C101 Ceramic Capacitor 10 uF 6 3 V 0805 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 22 6 3 V 0805 C105 Ceramic Capacitor 470 nF 50 V 1210 K1 Microcontroller netX500 P101 LC Display NEC NL2432HC22 41K R101 Resistor 10 63 mW 0603 R102 Inductor Sumida CR32NP 100K R103 Diode Philips Semiconductors PMEG4005AEV R104 Resistor 22 63 mW 0603 R105 Resistor 10 63 mW 0603 R106 Diode Philips Semiconductors BZV55C24 T101 Step up Fairchild Semiconductor FAN5330 X101 Connector Hirose Connectors Part No FH23 45S 0 38HW 05 Table 21 BOM LCD Interfa
21. 0 2 NOTISX VV NOTISX VO x 71 9 Jy AV IN cred x EN xu onx 4 012 NIJO NO Vo Gan Xt wx 71 9 17 97 6 0 90 Loly OLIN gt avo p 0X wet 0000 LZZ 00SXL 3N OHOIN 21 850 1 60 4 vss Aud OS LVSSA Hd Gauss izj NaH alors ovr noon zey Aue quoq ease 0 4 SVOGGN 66 602 INSE SXOVI vno 7 7 xz S 5 87 MOL ae 2019 9010 5 9 gjNXH i NXA Hd NX Hd y S Sd xE n exei Qd WX 25 M act 1 OMe 121 NXL 1 tax ona jzo XL Hd V LOLX 9014 avoaan ot 7 OL 41001 ZHNOOL uno 009 Z GOLD VOLO 9021 OOS aS 3 SVOG0A AHd 2014 POL a 3400 24008 uno 009 Z ZoLO LOLO DOOR 9021 JEDE 4 4 812 ivacan X 0098 00 Lx3eu v l e 6 1 9 9 L Figure 22 Ethernet TP Single Channel Circuit netX Design In Guide netX 100 500 Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX100 500 Quick Start Bill of Materials 28 158 REF DES PART TYPE PART NAME C101
22. 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 v e 2 9 6 v L L Jo L 51 158 3dON LSOH SN UJOO I9UOSIU MW 5 13 yeuospesec JeuosiH paupa wasn 2090 JA8G0ZcS9NS 000 0122 00SXLSN ONOIN 019 soaa usn gza 049 gsn ones gg 19330 897 000 012Z 00SXLAN ONOIN er ISIOIdOOHI gt DOES eu 91049 lol fio Zoo su 109 608 8080 90108 au eid 5109018 volo o 8049 20140 0089 V A netX100 500 Quick Start v L e 2 12 USB Host Mode Hilscher 2008 2012 081106 2 Revision 2 English 2012 10 Released Public Figure 34 USB Host Mode Circuit netX Design In Guide netX 100 500 netX100 500 Quick Start Bill of Material 52 158 REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Cer
23. 3d 1 aNoost 1 1 1 1 di 21559 5 B OATS Oe ax de 125 ae NA 5 NVOLOS3d NvO AS OSI HOO 5050 T m EI Son V V gt 2019 9mm 51 EE D Lu HNVO Qi 2 ii 4 1 1 TNVO LOLX hl 7 9 Ian QN908 8 I 2001 wz voran Y 1 1 v3 v d4LV OSI 1 1 1 vL L eL 6 8 Z 9 9 v L Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX Design In Guide netX 100 500 Figure 26 CANopen Circuit netX100 500 Quick Start Bill of Materials 36 158 REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 15 nF 1000 V 1808 C105 Ceramic Capacitor 22 uF 6 3 V 0805 C106 Ceramic Capacitor 22 6 3 V 0805 C107 Ceramic Capacitor 22 uF 6 3 V 0805 K101 Optocoupler HCPLO601 K102 Optocoupler HCPLO6OL K103 Transceiver PCA82C251T P101 LED red green HSMF C155 R101 Resistor 270 63 mW 0603 R102 Resistor 470 63 mW 0603
24. 979 Um BZX84C3V3 usa pPos 820 mm D 2 1 SN65220D m 819 2 mm D 4 Receptacle B usa vss o mm GND netX100 netX500 GND Figure 69 netX100 500 USB DOWNstream Port Device Mode The shown example schematics show the standard circuit as it is most commonly used also with many Hilscher netX designs Whenever a reconnect to the USB host is necessary this circuit requires unplugging and replugging the USB cable since USB host and detect a connect through the 1 5k pull up resistor that becomes active when the cable is plugged on both sides If your application requires reconnecting without unplugging replugging the pull up resistor must be made switchable by using the advanced circuit which allows to simulate manual plugging unplugging described in the following chapter 4 9 1 2 Advanced Circuit The circuit shown in the previous subchapter is perfect when the USB port is only used along with the serial boot mode of the netX However when using the USB port also during normal operation of the device e g for diagnostic purposes the following problem may occur Since the pull up resistor on the D line that lets the USB host PC detect the connection of a USB device netX is automatically activated when the netX device is plugged to the hosts USB port chances are that the firmware of the netX device has not yet initialized the netX USB port In that case the host
25. Table 43 Memory Component Reference SPI FLASH 1 Is not detected using the autodetect function Parameters have to be entered in config file Parallel Flash Manufacturer Size Part Number Spansion 16MB S29GL128P90TFIR1 32MB GL256N10FFI01 Table 44 Memory Component Reference Parallel FLASH netX Design In Guide netX 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Reference Section 154 158 SDRAM Manufacturer Size Part Number ISSI 8MB 1542532200 1 32Bit 32MB 1542532800 32Bit 64MB 1542532160 32Bit Micron 8MB MT48LC2M32B2 32Bit 16MB MT48LC4M32B2 32Bit 32MB MT48LC8M32B2 32Bit 64MB MT48LC16M32 16Bit Table 45 Memory Component Reference SDRAM netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Reference Section 155 158 Appendix 6 3 List of Tables Tablet BOM Basic Circuit t ea me chs aS dea vide te gti ayes babes 23 Table 2 BOM Basic Circuit Page 2 rere erret 23 Table 3 BOM Basic Circuit 3 2 0 een sinne 24 Table 4 BOM Basic Circuit Page 4 nenne Inne 24 Table 5 BOM Ethernet TP Two Channel cccsteccssssressseceteesseceesesuneetssoneaensecteecbseatenseeeesesebeeenesestassbecesessneee
26. 4 Most designs actually work with the simplified circuit that relies on the internal pull ups on the RDY and RUN pins hence omit the pull ups R1 A and R2a and use 10 pull down resistor s However due to the high tolerance of internal on chip pull up pull down resistors and due to the antiparallel LEDs that let the RDY and RUN signals influence each other chances are that such designs may not enter the desired boot mode due to invalid logic levels on RDY and RUN Q5 want to control the netX boot mode by applying the appropriate logic levels through external active components to the RDY and RUN pins Is that possible A5 No Shortly after detection of the desired boot mode by the boot loader the loader or the firmware will use the RDY and RUN pins as outputs to drive the System LED s and will most likely drive against the logic levels applied by the external circuit Besides that the System LED s will then not work this will drive short circuit currents through the netX RDY RUN pins that may damage the chip Q6 But I m using push buttons for the boot mode setting and would like to debounce the signals by Schmitt trigger buffers A6 This wouldn t make any sense at all Since the button s must already be pressed when performing a reset or powering up the system the signals will already be stable when the first stage loader checks them netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English
27. controller between the transceiver interfaces while they again share the same SCL signal line Since the SDA is a bi directional signal the use of an integrated analog switch is the easiest solution As the interface of the netX100 500 uses dedicated signal pins they could be equipped with appropriate internal pull up resistors 5 which basically makes external signal pull ups obsolete however two week pull ups 47 kQ are still required to avoid floating of the currently disconnected transceiver SDA signal The schematic below also shows the secure EEPROM holding license information and MAC addresses connected to the same bus which is no problem since components of different type or model usually have different device addresses which is also the case here This solution has been tested with a MAX325 analog switch however any analog integrated switch with similar or better characteristics Rdson pin capacitance bandwidth may be used The following figure shows the schematic for netX100 500 AT88SC0104C NI JN one Channel 0 12c_scL H15 pc spa W MAX325 dv dd sims 565 TDn Transceiver SD QFBR 59782 Channel 1 netX500 100 Some alternative parts 000000077 ADG723 Analog Devices 17 TDn Transceiver DG9434 Vishay Iit Re SD MAX4643 Maxim QFBR 59782 Figure 78 netX100 500 Interface Fi
28. 05 os V 0 LH ZHN001 009 Z 9001 au t XI 12 von Hd FO 75080 39001 go SOLD VOLO y Iri Si ZHN001 009 Z 9021 3101 sogo 20001 090 LOLO ari ene Vor aso tg OVSSA AHd LYSSA AHd ver SV G0A asar es tH 00 lt 001 1 v El 0 6 Figure 21 Ethernet TP Dual Channel Circuit netX Design In Guide 100 500 Hilscher 2008 2012 081106 2 Revision 2 English 2012 10 Released Public netX100 500 Quick Start Bill of Materials 26 158 REF DES PART NAME PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 10 uF 10 V 0805 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 10 uF 10 V 0805 C106 Ceramic Capacitor 10 nF 50 V 0603 C107 Ceramic Capacitor 10 nF 50 V 0603 C108 Ceramic Capacitor 10 nF 50 V 0603 C109 Ceramic Capacitor 10 nF 50 V 0603 K101 Microcontroller netX100 500 R101 Ferrite 100 MHz 600 1 A 1206 R102 Ferrite 100 MHz 600 1 1206 R103 Resistor Array
29. 2900 1 r oA xov 8 LOLM 2019 X ene ausos 3 gt ko 4 A A 3001 B NVOLOS3d ausos ANT sl UNI 4 we oul n LOLX M00L 9019 p 09 lt ja ax SOLM AS OS ur 0 2 8014 Y Pen 1 v v d4LV OSI 1 vL L eL 6 8 Z 9 5 v L Figure 29 DeviceNet Circuit netX Design In Guide netX 100 500 Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public 42 158 netX100 500 Quick Start Bill of Materials REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 22 uF 6 3 V 0805 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 C106 Ceramic Capacitor 100 nF 25 V 0603 C107 Ceramic Capacitor 22 uF 6 3 V 0805 C108 Ceramic Capacitor 22 6 3 V 0805 C109 Ceramic Capacitor 15 nF 1000 V 1808 C110 Ceramic Capacitor 15 nF 1000 V 1808 K101 Schmitt Trigger NXP Semiconductors part no 74LVC1G17GW K102 Optocoupler HCPLO601 K103 Optocoupler HCPLOGOL K104 Photocoupler amp Photo Transistor TLP281 K105 Transceiver PCA82C251T P101 LED red green HSMF C155 R101 Resistor 270 O 63 mW 0603 R
30. E SOLAS MOL wa 23 3 ma OT aviSdWi3 39 13 VISIT uvisd Wi3 loc ILIVISdTNLI OIVISd WI zim 0454 WA 80ld be ULvISd WIT SLDIdOVML TD Sex SlbidL WIE EL SEDIT FEN per VD WL 000 ELDIEBOVEIL po Far NE SED 001 eld Wa 61Old ISIS HH KLDL Pe FINAL WET EISEN Hdl Wa OLINSOVALL Ike ora ET TIGL IA WL RER TE Sean DIENEN 8DId3OvaL euD RIDEI 8 60 OE TYPE DEW en awa 620 SIDId3OVHL ory TDWI qa Dia Wi sbida0vell DNG Star Wwa Mew M e pans SEE SL TES Be LZOld IE TIS TDW WL bid3ovuL IE gE sar WES TDN Da wa vL L eL 6 8 Z 9 9 v Figure 36 ETM Circuit Design In Guide netX 100 500 Hilscher 2008 2012 081106 2 Revision 2 English 2012 10 Released Public netX100 500 Quick Start 54 158 Bill of Materials REF DES PART TYPE PART NAME K1 Microcontroller netX100 500 101 Connector TE connectivity Part No 2 767004 2 Table 20 BOM ETM Circuit More about debug and test interface circuits can be found on gt Page 70 chapter 4 5 1 JTAG Interface gt Page 71 chapter 4 5 2 ETM Interface gt Page 72 chapter 4 5
31. Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 84 158 47 Host Interface The netX100 500 provides a versatile parallel asynchronous interface referred to as host interface or HIF that can either be active netX controls the interface and accesses other memory mapped components or passive netX behaves like a Dual Port Memory DPM and is accessed by an external host processor In DPM mode the host interface can either be 8 or 16 Bit wide Signals that are not used for host interface operation of a design e g upper address lines can be separately configured as I Os The host interface always works in little endian mode As third mode the netX100 500 host interface can also operate as a PCI interface device or PCI host Since the use of the netX PCI interface is subject to certain restrictions and requires an appropriate contract that mode is not covered in this design guide Please contact the Hilscher sales department if you plan to use the netX PCI interface in your design Due to the fact that the behavior of the netX host interface is configurable to a large extent most applications do not require any additional glue logic The host interface signal buffers of the netX100 500 5 V tolerant and PCI compliant and are equipped with internal clamping diodes to raise signal undershoot overshoot tolerance The cathodes of the upper clamping diodes are inter
32. gt 1X4 Z 8 Ft Der 1 1 1 D i 1 N 1 a Ze n pss L 1 1 I 1 70 i oi on 8 B 1 cOSX 9163 t 35 00 090 200 2090 FOL So 200 os ANOL 0 50 60SO 8089 2090 9090 i x p uud ICH es 1 7154 e NIT 0X4 22 L J Br i 05 0 1 Susan pai 027 avo OCT 1 1 T 9 Woo 0x4 1 gt D t Q310WOO 0X4 lt e NON T 79 h 22727 i set 8 se 8 ze 8 ze ze P 18084 2094 i 19084 5054 vOSH y sem 5 i 1 4 t d ds 0 4 XS t K ae YLval xr 0x4 NEN 22 T 1 i oer oer i L05X 2094 20984 1094 t 1 001 as FOL 300 gg i M i 9090 47080 6092 2092 089 COVX LOPX SOLA POLA EOLA 1 L J 0 0 ed OLSH na hn s ete 1 aye Hi L J 6054 v m m 6 8 1 9 S L Hilscher 2008 2012 Figure 24 Fiber Optic Circuit on AFBR 5978Z Side DOC081106AN02EN Revision 2 English 2012
33. netX500 16 W199 POR netX100 GND EIE gt ZZ 1nF GND GND Figure 45 netX JTAG Circuits In designs that will not require the use of the JTAG interface the JTAG signals may be left unconnected The internal pull down on the JT_TRSTn will then constantly hold the JTAG interface in Reset state netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 71 158 4 5 2 ETM Interface The ETM Interface Embedded Trace Macro cell that is provided by the internal ARM CPU of the netX100 500 dramatically extends the debugging capabilities provided by the JTAG interface It is generally recommended to implement when building netX Evaluation boards but will most likely not be needed to debug prototype hardware Even the 38 pin ETM board connectors AMP Mictor 2 767004 2 are costly let alone appropriate ETM debugging units so implementing an ETM interface will usually only be interesting for customers that write own software for their netX design While the ETM interface on the netX500 is shared with the LCD Controller signals which means that driving a display is not possible when using the ETM port and vice versa netX500 designs driving an LC Display and providing an ETM connector at the same time should provide a possibility to disconnect the display in order to avoid any negative effect on the ETM signals from the display Also t
34. 1MB AT45DB081B Y 1MB AT45DB081D Y Y 2MB AT45DB161B Y Y 2MB AT45DB161D Y Y 4MB AT45DB321B Y 4MB AT45DB321C Y Y 4MB AT45DB321D Y 8MB AT45DB642D Y Y XD EON 4MB EN25P32 Macronix 2MB MX25L1605D Y 4MB MX25L3205D n 8MB MX25L6405D Y 5 128kB PM25LV010 Y 64kB PM25LV512 Saifun 512kB M25P40 Y S 64kB SA25F005 Y 128kB SA25F010 Y Y 512kB SA25F020 Y ST 128kB M25P10VP P netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Reference Section 153 158 Manufacturer Size Type Bootwizard 2nd Stage rcX 4MB M25P32 4 8 25 64 Y E 1 25 80 Y Y Y ST 2MB M45PE16 Y V 256kB M45PE20 gt 512kB M45PE40 Y 1 M45PE80 Y Y Y SST 256kB SST25LF20A Y 512kB SST25LF40A Y 1MB SST25LF80A Y 128kB SST25VF010 Y 128kB SST25VF010A Y 256kB SST25VF020 Y 512kB SST25VF040 Y 64kB SST25VF512 Y 64kB SST25VF512A Y 8 CFI ParFlashes Y Y 2MB S25FL016A Y 4MB S25FL032A E Strata CFI ParFlashes Y 2 Winbond 4MB W25P32 E Y 2MB W25Q16 Y Y 4MB W25Q32 Y Y Y 1MB W25Q80 Y Y z 4MB W25X32 Y Nymonix 128kB NX25P 10 Y 256kB NX25P20 Y 512kb NX25P40 2
35. Shield2 5 DGND Hilscher 2008 2012 Standard Circuits 4 11 7 Fieldbus Status LEDs 126 158 For each of the up to 4 possible Field bus ports two status LED signals are defined which function depends on the type of Field bus interface Function Pin name and number netX100 500 Field bus 0 COMO M21 Field bus 0 COM1 PIO1 M20 Field bus 1 COMO PIO2 M19 Field bus 1 COM1 PIO3 M18 Field bus 2 COMO 4 17 Field bus 2 COM1 5 N17 Field bus 3 COMO Note 2 PIO6 P17 Field bus 3 COM1 Note 2 PIO7 R17 Table 39 Status LEDs for Fieldbus Ports Fieldbus Protocol LED Name LED Color PROFIBUS DP Master and Slave COM green red CANopen Master and Slave CAN green red DeviceNet Master and Slave MNS green red AS Interface Master COM green red CC Link Slave L RUN L ERR green red CompoNet Master and Slave Two LEDs required by spec MS and NS green red Table 40 Fieldbus Status LED Colors Note 1 2 netX Design In Guide netX 100 500 CompoNet requires four status LED signals DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Field bus 3 is generally not available on netX100 and also not on netX500 when running RTE applications requiring hardware synchronization Hilscher 2008 2012 Standard Circuits 127 158 4 1
36. netX Motorola interface 8 Bit multiplexed RD WR RDY WAIT INT Host ADO 15 88 158 DPM A0 15 DPM CSn DPM BHEn DPM ALE DPM RDn DPM WRLn DPM WRHn DPM RDYn DPM INT DPM D0 15 Intel interface 16 Bit multiplexed Figure 59 netX DPM Motorola Type Interface Circuit Multiplexed netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 89 158 4 7 1 4 ISA Mode The netX host interface also provides a virtually glueless interface to ISA Bus or PC104 systems The following schematic shows how to connect the host interface in that case _ 0 19 DPM_SELA12 15 1008 DIP Switch or Jumper optional for address selection DPM_ALE DPM_CSn DPM_BHEn DPM_RDn DPM_WRLn 516 D DPM_WRHn IOCHRDY DPM RDYn DPM D0 15 00000000 Hor DIP Switch or Jumper for IRQ selection RESETDRV RESETIN ISA Bus netX Figure 60 netX ISA Bus Interface Circuit Since the ISA Bus requires its interface cards to perform address decoding the netX host interface also provides an internal chip select generator that can be used instead of the DPM_CSn chip select signal The DIP Switch or jumpers connected to signals DPM_SELA16 19 allow to set the netX DPM to a certain base address on the ISA B
37. ont gt a6 UN 219750 t3 LIVSSA Hd Kawan Xd VSSA Hd ali 8 T Lie 591 XL OWX OWX zT au B 30001 090 2 L0LM VOV 9070 2 NY Y E p 1 vor 94 i ma MIOINNZZEGRAS 2 XIXA 9 TALS XL X3 1 1 1 I ar XL 0X4 t de 5 yeauseyep ees aoan or 090 lt 1 dOVSS pueBoy i 1 X Xau o 9509 1 30001 POL Tom vun are ea ke 1 2 6070 anevsaxi oA Y 9021 n CCC Tij Y ZOVM Y d d Vr SdVIZS ON ae SA 34001 5090 POL 080 ZHINOOL 009 2 cOVO LOYO i 902 pag 3ngavsiaxt 0x4 oa v TN NESO ORT 5 LOval 3 L013 9072 X ence v L e OL 6 8 4 9 9 v e V Figure 23 Fiber Optic Circuit on netX100 500 Side netX Design In Guide netX 100 500 Hilscher 2008 2012 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public 30 158
38. which however is not really a conflict since RTE applications usually require both Ethernet ports and a field bus stack can not run on XMACO RTE Status LEDs or XMAC1 when these XMACs are already used by an Ethernet application Firmware Label Dual LED Label Meaning COM 0 COM 1 PIO1 PIO2 PROFINET SF BF SF System Failure BF Bus Failure EtherCAT RUN ERR RUN Run ERR Error Powerlink BS BE BS Bus Status BE Bus Error SERCOS STA ERR STA Status Phase Master ERR Error SERCOS S3 3 Slave orange red and green at the same time EtherNet IP MS NS MS Module Status NS Network Status Open RUN ERR RUN Run Modbus TCP ERR Error VARAN RUN ERR RUN Run ERR Error Table 38 Status LEDs for Real Time Ethernet Applications All RTE Status LED I Os are defined as active low The following schematic shows how to connect the LEDs netX100 netX500 M21 3 3V COMO 1 20 M19 M18 Figure 81 netX RTE Status LED Schematic netX Design In Guide 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 117 158 The appropriate value for Rv depends on type and color of the LED standard value 270 Use either two red green Dual LEDs or two pairs of si
39. Released Public Hilscher 2008 2012 Standard Circuits 4 11 3 CC Link Interface 122 158 A CC Link interface can be implemented as shown in the following schematics which are based on the reference schematics from the CC Link specification The purpose of the AND gate in the RX signal is simply to convert the 5V signaling voltage from the photo coupler to 3 3V level More detailed schematics pin numbers can be found in the in the Reference Section in Chapter 5 680 ZCYS51RS M3PAT 680 AA EH mos RD6 2Z 45V ISO 1 0601 CCL_SDG 2 fg i F2201 XMi 100 220 P amp 1 GND 5V A ae 75 15181 4 VCC CCL_TX L gi 4 L L GND HCPL 0720 VCC VCC 5 x CCL_RX amp 1 x x GND GND For Details refer to the 3 37 CC Link specification t 3 3V GND_ISO 4 1 GND Figure 85 Basic Circuit for netX CC Link Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Kl gt 3 3n 50V mm 510 ua FG PE Hilscher 2008 2012 Standard Circuits 4 11 4 CompoNet Interface 123 158 A CompoNet interface can be implement
40. SDRAM 32 16 16 17 MEMDR_RASn MEMDR_CASn MEMDR_CSn MEMDR_WEn DQMO MEM DQM1 MEMDR CLK MEMDR CKE MEM D0 15 netX A0 12 MEM A0 12 82 158 SDRAM 16Mx32 MEM A16 MEM A17 MEMDR RASn MEMDR CASn MEMDR CSn MEMDR WEn MEM DQMO MEM DQM1 MEM DQM2 MEM DQM3 MEMDR CLK MEMDR CKE MEM D0 31 SDRAM 32Mx16 MEM A16 MEM A17 MEMDR RASn MEMDR CASn MEMDR CSn MEMDR WEn netX Figure 52 netX SDRAM 1 16 Bit 1 32 Bit 2 16 Bit MEM DQMO MEM DQM1 MEM DQM2 MEM DQM3 MEMDR CLK MEMDR CKE MEM D0 15 MEM D16 31 netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 83 158 SDRAM 64Mx8 SDRAM 64Mx8 0 12 16 MEM A17 MEMDR_RASn MEMDR_CASn MEMDR_CSn MEMDR_WEn DQMO MEM 1 MEM DQM2 MEM DQM3 MEMDR CLK _ MEM_DO 7 MEM D8 15 MEM D16 23 MEM D24 31 netX SDRAM 64Mx8 SDRAM 64Mx8 Figure 53 netX SDRAM 4 8 Bit netX Design In Guide 100 500 081106 2
41. bg tenni etes Aaaa 138 4 18 1 Core Voltage Regul tor nn 138 4 18 2 Alternative Core Voltage Regulator 139 4 18 3 Common Supply Voltage Regulator 3 3 enm ener 139 4 18 4 Voltage Regulator 5 V 140 5 General Design Considerations 141 5517 rte RE RR ERR REX DR ERR RARE yana ayayay kah ya 141 9 1 Tu BASICS su eoe Usenet hee ibit n Norm 141 5 1 2 A nera a 141 5 1 3 E A E 143 5 2 EMC behavior sxs 144 5 271 Eayer Stack teinte iet ua Sasa a wh des 144 5 2 2 ic RR ER Renee TE 145 5 2 3 Power Supply Input it 146 5 24 Reset lines Ne EC 146 92 5 61 010 E E E 147 5 2 0 Ethernet Interfaces 147 5 2 7 149 5 2 8 G 149 5 3 Vias and Traces under the netX100 500 0 01 renes 151 6 Reference Section u u
42. gt hilscher COMPETENCE IN COMMUNICATION Application Note netX Design In Guide netX 100 500 Hilscher Gesellschaft f r Systemautomation mbH www hilscher com 00 081106 2 Revision 2 English 2012 10 Released Public Introduction 2 158 Table of Contents 1 4 14 About this uite oett tc nto 4 1 0 Legal Notes er cd 5 1 21 Copyright ner ri ee de op eric eee elie ene 5 1 2 2 Important ern ipee on debe eA Doo d ade deme 5 1 2 3 of Nro ne 5 12 4 WV eere KO ds M eee 6 1 2 5 Export Regulati n isn iiie nah 6 2 NEtX 100 500 Quick Start na inne 7 27 ette e Lb HI 7 22 Ethernet Interface 25 2 2 1 Twisted Pair Two Channel iecore listed iene 25 2 2 2 gt Twisted Pair Single Chiannel 4 Dee Leere sa E os duse ben 27 2 2 3 Fiber Optic with AFBR 5979Z 2 u uu 0 ea ah ue 29 2 9 JA Interface 33 24 COANODOlN c onn EPA 35 2 5 GGA Recess 37 2 67
43. holding the appropriate firmware The FLASH size information is based on the code sizes of the current Firmware Releases include the additional memory required for the Hilscher second stage loader currently 52 and the FLASH disk leave some headroom for future extensions and are generally rounded up to the next available FLASH size step If Linkable Object Modules are to be used users must of course consider the additional memory required for their user application where applicable All listed protocols also require different amounts of SDRAM however the smallest available SDRAM components are meanwhile 8MB anyway This amount of memory meets the requirements of all current protocols and is hence indicated as minimum SDRAM size for netX designs Loadable Firmware LOM netX SPI FLASH size ASi Master 100 500 2MB CANopen Slave 100 500 2MB CANopen Master 100 500 2MB DeviceNet Slave 100 500 2MB DeviceNet Master 100 500 2MB CC Link Slave 100 500 2MB PROFIBUS Slave 100 500 2MB PROFIBUS Master 100 500 2MB EtherCAT Slave 100 500 2MB EtherCAT Master 100 500 2MB Ethernet IP Adapter 100 500 2MB Ethernet IP Scanner 100 500 2MB Modbus RTU TCP 100 500 2MB POWERLINK Slave with integrated Hub 100 500 2MB PROFINET RT IRT Slave with integrated Switch 100 500 4MB PROFINET RT Master with integrated Switch 100 500 2MB SERCOS Slave 100 500 2MB Table 25 FLASH Sizes for Hilscher St
44. k PZ 75060 ad NZZ 500 WO OLVO 000701ZZ 005XL3N OHOIN ret 8 BLIVNEESISTON Nl Live He ESSA 1L S L SSA 9I SS mfb Z SSA SISSA BEN EISSA Y lez SS ZESA 8Z SSA LISSA 12 OSSA 92 SSA 6 SSA SZ 8 SSA Addn Jamo 72 SS LSSA AS s d z SSA SSA ZZ SS SSSA L SSA SSA 02 SS SSA ao 6L SS ZSSA 8I SSA ISSA 2001 997 255 950 s1 000A HA 600 gory 5 xz B oz u ge 7 z E 4 5080 300 coo 34001 zo FOL 5080 x 2 AZZ 060 bere 0099 2 9i SWO 4 vivo i i B E T it law lor E 5 n eH eroan Et ea gory G m ES Y m 3 807 ae pe e 2 yds 19 2 7472 91 000 d TE yes eds Aada eb A g u ES HM 9 x s d d 8001 sore vord FR z 0 w cWO NE by S 8179 ZO Q si ae 95 A ri acan 28 T k 2194 OFO 158 9 eaan 01 000A Fai MOI 5 oon 9074 8 9 il 6 9 200A Hs Lt 2 An PE I 310 5 8 Zee 8 Z oaoa tz P gt 4001 5905 zona 3 Je
45. that the FAlLn signals are not 5 V tolerant hence 3 3 V levels may only be used here netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 132 158 4 14 Encoder Interface The netX100 500 provides an Encoder unit allowing to connect two separate incremental rotary encoders quadrature encoders used for capturing position angle speed and direction of a rotating axle mostly used with motion control applications As it can be seen on the picture in the previous chapter using the Encoder unit rules out the parallel use of PWM unit 0 and also blocks 0 2 and or PIO3 5 and PIO6 7 which are the standard resources for RTE and field bus status LEDs In that case other I O resources must be used for the LEDs However since the pinning option for the Encoder unit allows enabling encoder 0 and encoder 1 and the two optional MP signals individually the parallel use of a single encoder and up to 5 PIO signals is possible Using the encoder also requires 2 to be disabled allowing the encoder unit to be controlled by the ARM CPU which excludes the use of a field bus protocol on XMAC2 or which would require customized XMAC code that can only be created by Hilscher custom development Each encoder interface provides three signal inputs named A B and N A and B are the two quadrature signals while is the index signal indicatin
46. 00022 00912 ORION saan AES cer M3MOd 3 58 lt 091 6z0ld gt a m gt za Old d o x g ai aoi Id 001 2 Id d3 NASH d91 vv 91997 So 28 ET 01 99 001 9id 091 33 8 001 Sid 021 x en or aa X Z ST eid 01 1204 546 PA CE 09 21 gt uaa x 5 42 051 E 091 oid ao 80 05 Ege 51 ty a01 62 TH dO sd 351 90 oram 38 ae sm S 10 091 miram 22 LOLO et 9d 351 E 8 SIDA 001 K SON AL GT tq solas 55 aes zd ao1 0 28 arcs 5 091 1d 001 55 SEM 8 E 90 LOLX oy 5 000 0122 009 19 p IOLO3NNOO AV 1dSIG sx soso b b MATE COT kodo 24 2099 gra 16090 SLA Siw 92 ei 2090 5 629 1000 vl L OL 8 2 9 5 L Hilscher 2008 2012 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public netX Design In Guide 100 500 Figure 37 LCD Interface Circuit 56 158 netX100 500 Quick Start
47. 13k 1 1206 R105 10uH R106 0 018 45V N C108 1 C109 05 22uF 0805 22uF 2 Figure 99 netX 5V Supply netX Design In Guide 100 500 1 GND T DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 141 158 5 General Design Considerations 5 11 Thermal Behavior 5 1 1 Basics Since netX100 500 designs are often used in industrial environments fitness for high temperature ranges is frequently an issue Depending on the used interfaces and chip type netX100 500 designs can have a power dissipation from typically 1 1 W PHYs for Ethernet turned off up to 1 6 W integrated PHYs in use which results in appropriate warming of the netX silicon While there is a hard limit for the chip s junction temperature at 125 C above which malfunction and permanent damage may occur it is always desired to keep the junction temperature as low as possible as a semiconductor s statistical life time generally decreases with rising temperature Since additional power dissipation that is being avoided in the first place does not result in additional heat that needs to be dissipated hardware designers should make sure that all power supply circuits deliver nominal voltage levels 3 3 V I O and 1 5 V core and do not make use of the possible headroom 3 6 V I O and 1 65 V core The BGA packages used with
48. 4x 50 O 62 mW 1206 R104 Resistor Array 4x 50 62 mW 1206 R105 Resistor 10 63 mW 0603 R106 Resistor 10 63 mW 0603 R107 Resistor 10 63 mW 0603 R108 Resistor 10 63 mW 0603 R109 Resistor 12 4 63 mW 0603 R110 Resistor Array 4x 270 62 mW 1206 X101 RJ45 ERNI 203313 Table 5 BOM Ethernet TP Two Channel More about Ethernet circuits can be found on gt Page 102 chapter 4 10 Ethernet Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 27 158 netX100 500 Quick Start Twisted Pair Single Channel 2 2 2 The following figure shows the netX100 500 Ethernet circuit with only on channel v l e 6 1 9 5 v e L 2 a SI UJOOJOUOS II AW aea abe IV u awe 5 4 wopewonewarshs LLOZ LI EO E J os 9soc Jeuos l lNeHMHI JeusiH vegan semen ponpa 0000 122 008XL3N OHOIA S Sar ox En xi w n xt enx NOT ex ZA tar xs WX E yx 661 024NEB SHOVUVTINGON g cartes
49. A10 24 9 MEM_D18 A10 VDDQ2 p19 C2 MEM D19 MEM A11 21 D19 A11 VDDQ3 Mpoo _ 2 __ 220 12 69 020 12 VDDQ4 MMD MEM 021 VDDQ5 559 MMD 55 MEM 222 MENFE VDDQ6 H72 023 B4 MEM D24 MEM A13 22 VOOr C204 1 C205 MEM 024 65 BSO VDDQ8 025 14 23 6 0603 400nF 0603 400nF 025 BS1 VSSQ1 026 MEM_D26 VSSQ2 2 2 1255 D3 MMD 16 027 DQNO VSSQ3 D4 MEM D29 MEM 028 DOMI VSSQ4 D29 029 DQN2 VSSQ5 E4 D30 030 E5 MEM DS VSSQ6 MEM D31 CS VSSQ7 GND 19 84 RAS VSSQ8 2 MEM A09 18 MEM AO 0 179 CAS A1 o WER F2 MEM 0 68 MEM 2 CLK 2 FA MEM 67 MEM A3 CKE MEM A04 MEM A4 MEM AS MEM A0 gt MEM ae MEM A06 EET MEM LAS HI MEM AO 4 MEM A7 Dat MEM MEM 8 LAS J MEM A09 MEM A9 DQ3 KE MEM 19 MEM A10 504 LATO MEM A1 MEM A11 MEM Dos MEM A12 DQ6 MEM A13 Dar 14 Das MEM A15 009 MEM A16 2010 MEM A17 Dati MEM A18 0012 MEM 19 0013 MEM A20 0014 MEM A21 2015 MEM_A22 0016 MEM A23 0017 2018 MEMSR_SCO 0019 MEMSR SC1 0020 MEMSR SC2 0021 MEMSR_OE 0022 MEMSR WE 2023 0024 MEM DQNO 0025 MEM DOM1 0026 0027 MEM 0028 0029 MEMDR_CS 2 MEMDR RAS 2031 MEMDR_CAS Hg MEMDR SDRAM64M32 3V3I7T MEMOR CLK Lr MEMDR CKE MICRO
50. DN PF Powerfail GND 210 netX XMi 100 For Details refer to the DeviceNet specification from the ODVA TLP281 5 4 02K mm V gt U 1 5V V DRAIN GND Figure 87 Basic Circuit for netX DeviceNet Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public T n 1kV PE Hilscher 2008 2012 Standard Circuits 4 11 6 PROFIBUS Interface 125 158 A PROFIBUS interface can be implemented according to the following simplified schematics More detailed schematics can be found in the in the Reference Section in Chapter 5 Note The isolated 3 3V to 5V DC DC converter should either be a regulated model or should be equipped with an appropriate downstream LDO regulator Otherwise the secondary voltage may be too high resulting in out of spec signal levels on the PROFIBUS line IL3585E PB_ENB 330 XMi 100 XMi PB_TX 100k 2 U RXD TXD P EN RXD TXD N PB RX XMi RX 100k 9 pin male V regulated Figure 88 Basic Circuit for netX PROFIBUS Interface netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public l SUB D Shield
51. Fiber Optic Transceivers already provide an internal AC termination on the TXDATA input lines which results in a slightly different circuit PHY_VDDCAP t PHYO VDDCART 1 VDDCART PHY VDDIOAT PHY VDDIOAC PHY VSSAT PHY VSSACP PHYO VSSAR PHYO VSSAT1 PHYO VSSAT2 PHY1 VSSAR PHY1 VSSAT1 PHY1 VSSAT2 PHYO TXP PHYO TXN PHYO RXP PHYO RXN PHY1 TXP 1 TXN 1 1 PHY_EXTRES netX100 PHY_ATP netX500 Figure 75 netX100 500 Ethernet Circuit Fiber Optic XMO_RX XMO 100 XMO 101 R1 1 5V F17 1000 O 100 MHz 200 mA A e C1 C2 T 100n 77 10 R2 3 3V J20 1000 Q 100 MHz 200 mA A d Ld F18 c4 10u XM1 TX XM1 netX100 XM1 100 FX Transceiver e g AFBR 5978Z QFBR 5978AZ netX500 xw 101 GND FX Transceiver e g AFBR 5978Z QFBR 5978AZ Component Value Tolerance Rating R4 R5 R11 R12 R13 127 O 130 Q 196 R8 R9 R10 R16 R17 R18 82 5 O 82 O 196 R6 R7 R14 R15 195 Q 196 R19 1k0 82 O R20 1 6 130 R23 12 4 196 125 mW C1 C3 100 nF 6 3V C2 C4 10 uF 6 3 R1 R2 1000 100 MHz 200mA Table 35 Fiber Optic Ethernet Circuit Component Specification AC Termination netX D
52. Jo obey LT E SA erus 5 LLOTILZL era 1 25 5 19405 my yeu I 99 Jezjoyy SEIEN 1 9usasi 21 9 y lt kod vold er 0 2 27 090 lt ps ee Old I I 1 I 1 l 1 I i 1 ssoedb asd ANOOL uuo oon z a 109500890 t vp N 2014 sold T void gt s 2 PZ 080 l ZHINOOL 0001 Z LOL 60 00 1 coll LOL X 3d I i I I i 1 m dd aNoos 90 2 801 E i B aseen 1 mb ee Ss ur _ gt xa wx I iK ars JL ax 8 90LY oF 2009 Kt le vier tt Arno 1 om 5400 060 30001 T090 jure 2010 lt 1 A gt gi 200 l 4 i SIND Ud 71 590 Yo 5 XIX gd GOLN ad SI 1 bap LOLX I 1 031 1081 vL L eL 6 8 Z 9 5 v L Figure 30 PROFIBUS Circuit netX Design In Guide netX 100 500 Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX100 500 Quick Start 44 158 Bill of Material R
53. L ene nennen ren 66 Figure 42 netX500 RTC ode 67 Figuire 43 netX100 500 RTC Un sed La tuna nibo 68 Figure 44 netX Reset Glrcults 2 n ere ter teet eh t ne ie e ERE 69 Figure 45 JTAG Circuits 1 irren un tcc le Hee dene dere de dee 70 Figure 46 netX100 500 Boundary Scan JTAG TEST 72 Figure 47 netX100 500 SPIl Flash Ho Hc i Pee tei eoe ee Re ibo a grise te apa 75 Figure 48 netx100 500 MMC SD 75 Figure 49 Solution if SD Card Disturbs SPI Data Transmission from 76 Figure 50 netX FLASH Address Line AO for Low High Byte 78 Figure 51 netX FLASH AO as the LSB of a Word 79 Figure 52 netX SDRAM 1 16 Bit 1 32 Bit 2 16 82 Figure 53 netX SDRAM 4 8 S Q Sq a iG uu 83 Figure 54 netX100 500 VDDHI Pins eene ne aa Bi ad feo 84 Figure 55 netX Intel Type Interface Circuits 1
54. NETX500 2210 000 Figure 10 netX100 500 Connection of 8MB SDRAM More about SDRAM circuits can be found on gt Page 81 Chapter 4 6 2 SDRAM netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start Ethernet 13 158 The basic circuit assumes that Ethernet is not used Figure 11 shows the netX100 500 PHY power connection if the Ethernet interface is not used 3V3 PHY_VDDIOAT PHY_VDDIOAC Fis f 1V5 PHY_VDDCAP a C302 4 ni PHY VSSAT PHY VSSACP PHYO VDDCART PHY1 VDDCART 1 VSSAR PHY1_VSSAT1 PHY1_VSSAT2 ND PHY EXTRES em 124 MICRO NETX500 2210 000 GND Figure 11 netX100 500 Ethernet Not Used More about Ethernet circuits can be found on gt Page 25 Chapter 2 2 Ethernet Interface gt Page 102 Chapter 4 10 Ethernet Interface netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 14 158 Host Interface For the basic circuit only the TCLK A11 pin has to be connected with a pull up resistor to ground All other pins have to be connected to the companion chip 83 EXT 82 81 78 77 76 75 74 EXI 32
55. REF DES PART TYPE PART NAME C501 Ceramic Capacitor 10 uF 10 V 0805 C502 Ceramic Capacitor 100 nF 25 V 0603 C503 Ceramic Capacitor 10 uF 10 V 0805 C504 Ceramic Capacitor 100 nF 25 V 0603 C505 Ceramic Capacitor 100 nF 25 V 0603 C506 Ceramic Capacitor 10 uF 10 V 0805 C507 Ceramic Capacitor 100 nF 25 V 0603 C508 Ceramic Capacitor 10 uF 10 V 0805 C509 Ceramic Capacitor 100 nF 25 V 0603 C510 Ceramic Capacitor 100 nF 25 V 0603 P501 LED HSMF C155 1210 P503 LED HSMF C155 1210 R501 Resistor 130 63 mW 0603 R502 Resistor 130 63 mW 0603 R503 Resistor 130 63 mW 0603 R506 Resistor 82 63 mW 0603 507 Resistor 82 63 mW 0603 R508 Resistor 82 63 mW 0603 R509 Resistor 82 63 mW 0603 R510 Resistor 82 63 mW 0603 R511 Ferrite 1 uH 0 28 Q 600mA 1812 R512 Ferrite 1 uH 0 28 Q 600mA 1812 R513 Resistor 270 63 mW 0603 R514 Resistor 470 63 mW 0603 R517 Resistor 130 63 mW 0603 R518 Resistor 130 63 mW 0603 R519 Resistor 130 63 mW 0603 R522 Resistor 82 63 mW 0603 R523 Resistor 82 63 mW 0603 R524 Resistor 82 63 mW 0603 R525 Resistor 82 63 mW 0603 R526 Resistor 82 63 mW 0603 R527 Ferrite 1 uH 0 28 Q 600mA 1812 R528 Ferrite 1 uH 0 28 Q 600mA 1812 R529 Resistor 270 63 mW 0603 R530 Resistor 470 63 mW 0603 501 Fiber Optic Connector AFBR 5978Z X502 Fiber Optic Connector AFBR 5978Z Table 8 BOM Fiber Optic Page 2 More about SDRAM circuits can be found on Page 105
56. Though this interface is rarely used during operation of final netX products it is strongly recommended to have at least retrofittable access to this interface on any netX design especially on prototypes even for designs where the customer does not intend to write his own software but use Hilscher loadable firmware instead Debugging of a prototype can be somewhere between cumbersome and impossible if the JTAG interface is not accessible and for development of own netX software a JTAG interface is essential anyway Further automatic testing systems used in production testing usually need access to this interface so the JTAG interface pins should at least be connected to test points that can be contacted by prober systems Whenever there is enough space on the design s PCB a standard 20 pin shrouded header with 0 1 or 2 54 mm pitch should be used for the JTAG interface since this allows connecting standard JTAG debugging units to be plugged to the board instantly without the need for any special cable adapters The following figure shows the standard netX JTAG circuit 3 3V 10k 10k 5 TDI TDO 13 014 5 EN nTRST EN e nSRST 580 5 mo VTref 2 Vsupply III JT TDI JT TMS JT TCLK JT TRST 4 3 3V 6 Open Collector GND gt Open Drain GND am RESET RESET output 10 Manual out RESET GND
57. VDD IO VDD CORE SSA SSA L VDD IO VDD IO SSA 3HO2 QGA VDD IO VDD IO e gt are Figure 104 netX100 500 Decoupling Caps Vias and Inner Plane for VDD IO and VDD CORE netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 146 158 5 2 3 Power Supply Input Filter When using the 9 30V power supply shown in chapter 3 17 the following filter circuit is recommended to reduce line based emissions at 500 kHz and harmonics R6 R4 9 30 gt D gt 33V DC 47 uH Ror C2 C3 C4 C1 FEL gt 22 X MIC2198 SMBJ30 47nF 4 7 nF 220 10 uF X R1 CA SMBJ30 CA R5 EXT gt e BE 47 uH R5 and R5 EPCOS SIMID B82432 T1473 K max 340 mA GND Figure 105 Power Supply Filter 5 2 4 Reset Lines As already mentioned in chapter 3 4 reset signal lines should be kept as short as possible and should be equipped with a 1nF ceramic capacitor connected to the reset signal and ground located close to the netX reset input pin to reduce the risk of undesired resets due to noise or electrostatic discharge netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public H
58. all current netX chips have mainly two paths of heat dissipation which are the path through the package balls into the copper of the PCB mainly power and ground planes and the path from the chip surface top to the environment The resulting thermal resistance of the first path strongly depends on the characteristics of the PCB which also makes the thermal behavior of a design strongly dependant on the PCB The only possibility to decrease the influence of the PCB is to use a heat sink which can considerably reduce the thermal resistance of the second heat dissipation path and also improves the overall thermal behavior of the design 5 1 2 Estimates The Technical Data Reference Guides chapter Thermal package specification of the netX chips provide the following formula that allows calculation of the chip junction temperature 7 at a given environment temperature and thermal resistance of the heat sink netX T T c 0 R xP The chip specific value of 0 can be found in the above mentioned chapter of the appropriate Technical Data Reference Guide Please note that the formula above only allows an estimate for the possible junction temperature of a particular design as there is still an influence of the PCB characteristics The parameters have been evaluated using certain test boards and may hence not be directly applied to a specific design This applies even more to the second formula for
59. and Bottom Side Dimension Description mm mil Clearance 0 15 6 e Pitch 1 00 39 37 9 Grid 0 15 6 p Pad 0 45 18 t Trace Width 0 15 6 Via Diameter 0 60 24 w Drill Hole 0 20 8 PCB max width 2 00 79 Table 41 Dimension of Printed Circuit Board Design Note Vias within the chip footprint area should be exactly centered between the pins to avoid possible soldering problems during manufacturing netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Reference Section 152 158 6 Reference Section The following chapters list some key components for netX100 500 designs that have been successfully evaluated by Hilscher and where applicable are supported by Hilscher tools status of January 2012 6 1 Crystals Use Part Number Manufacturer System clock CS10 25000MAGJ UT Citizen Real Time Clock Q0 032768 JTX520 12 5 20T 1 LF Jauch Quartz GmbH Table 42 Crystal Reference 6 2 Memory Components SPI FLASH Manufacturer Size Type Bootwizard 2nd Stage rcX ATMEL 2MB AT25DF161 128kB AT25F1024A R 64kB AT25F512 64kB AT25F512A v 2MB AT26DF 161 Y 2MB AT26DF161A 4MB AT26DF321 Y 128kB AT45DB011B Y 256kB AT45DB021B Y 512kB AT45DB041B Y
60. and the cycle may not yet be terminated that can either work with active high or active low signals Further the output of the RDY WAIT signal can be configured as push pull or open drain open source with sustained tri state option signal edge is actively driven For more details and diagrams please consult the appr netX Technical Reference Guide separate documents for netX100 500 netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 93 158 4 7 2 Extension Bus Mode In Extension Bus mode the netX provides an active parallel 8 or 16 Bit wide asynchronous bus interface with support for a Ready or Wait signal that allows external components to extend data cycles beyond the programmed cycle timing The Extension Bus can either use separate Read EXT RDn and Write EXT WRn WRLn EXT WRHn signals Intel mode or a combined R WRn signal indicating the direction of the access along with Byte strobe signals Motorola mode In Intel mode either a single Write signal can be used EXT WRLn combined with a Byte Enable Signals EXT BHEn or two Write signals EXT WRLn EXT WRHn for writing to the low Byte EXT WRLn and high Byte EXT WRHn separately The Extension Bus can be used to connect parallel peripherals like SRAMs FLASHes DPMs etc and can operate in non multiplexed or multiplexed mode The four different chip select sign
61. ceramic capacitor 100 nF 25 V 0603 C102 ceramic capacitor 10 uF 10 V 0805 C104 ceramic capacitor 100 nF 25 V 0603 C105 ceramic capacitor 10 uF 10 V 0805 C106 ceramic capacitor 10 nF 50 V 0603 C107 ceramic capacitor 10 nF 50 V 0603 K101 Microcontroller netX100 500 R101 Ferrite 100 MHz 600 O 1A 1206 R102 Ferrite 100 MHz 600 O 1A 1206 R103 Resistor Array 4x 50 O 62 mW 1206 R105 Resistor 10 O 63 mW 0603 R106 Resistor 10 63 mW 0603 R109 Resistor 12 4 63 mW 0603 R110 Resistor 270 63 mW 0603 R111 Resistor 270 63 mW 0603 X101 RJ45 ERNI 203199 Table 6 BOM Ethernet TP Single Channel More about SDRAM circuits can be found on gt Page 102 chapter 4 10 Ethernet Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 29 158 netX100 500 Quick Start th AFBR 5978Z The first figure shows the connection on the netX100 500 side ic wi Fiber Opt 2 2 3
62. detects an unknown USB device and the USB cable needs to be disconnected and reconnected again after the netX USB port has been initialized by the firmware If this is not acceptable the following circuit s should be used netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 100 158 3 3V usa 219 15 usa 919 AA13 1 GPIO12 VBUS BZX84C3V3 B20 3 USB_DPOS Em D 2 1 B19 2 USB_DNEG D 5 Receptacle usa vss mm GND netX100 netX500 GND Figure 70 netX100 500 USB DOWNstream Port Device Mode Advanced Circuit When using the circuits shown above accessing the netX through the USB serial boot mode will not work since the serial boot mode is handled by the netX ROM loader and the ROM loader will not activate GPIO12 hence the PC will not detect a connected USB device For that reason the circuit includes a jumper that allows the pull up to be connected to the 3 3 V sourced through the USB Bus For devices where using such a jumper or a switch is not applicable a special non standard diagnostic cable including an external pull up on D must be used when the netX needs to be accessed in USB serial boot mode 4 9 2 Host Mode In host mode the netX500 USB port can be used to access other USB devices like USB Sticks Memory Card Reader etc It is most commonly used a
63. driver available no driver available Flash File System for AT45DB321C wear leveling provided MMC SD Card 100 500 supported supported no driver available LC Display 500 supported supported no driver available Fieldbus Slave 100 500 no stacks available no stacks available no stacks available 1 Chanel Fieldbus Master 100 500 no stacks available no stacks available no stacks available 1 Chanel Ethernet Ports 100 500 Standard Ethernet only Standard Ethernet only Standard Ethernet only Host Interface 100 500 PCMCIA interface Extension Bus or PCMCIA driver available no support of bootable interface no support of media bootable media Real Time Clock 500 supported supported no driver available AD Converter 100 500 no driver available driver for Touch panel only no driver available PWM Interface 100 500 no driver available no driver available no driver available Encoder Interface 100 500 no driver available no driver available no driver available Table 24 List of Resources 3 Party OS netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Resource Overview 61 158 3 3 Memory Requirements of Hilscher Stacks The following table lists all field bus and RTE protocols that are currently status of February 2011 available as Loadable Firmware or Loadable Object Modules from Hilscher along with the required size of the SPI FLASH
64. enough space to keep the power and ground planes free from any signal traces and allow shielding areas on top and bottom layers which contributes to a satisfying EMC behavior of the design An approved 6 layer stack for netX designs is shown in the following figure Components TOP Routing Shield INT3 Routing INT1 Ground 35 um CU 100 um FR4 Prepreg INT2 Power 35 um CU 510 um FR4 Basematerial INT4 Routing 35 um CU 100 FR4 Prepreg BOTTOM 35 CU Components Routing Shield 510 um FR4 Basematerial 35 um CU 100 um FR4 Prepreg 35 um CU Figure 102 Approved netX PCB Layer Stack netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 145 158 5 2 2 Decoupling capacitors As with any digital design the use of a sufficient number of decoupling capacitors is important to provide a stable operation of the design and avoid unnecessary emission The following picture shows an example how to arrange decoupling capacitors around a netX100 500 Figure 103 netX100 500 Decoupling Caps As the picture already indicates the power path goes from vias located as close as possible to the caps to the caps and from there directly to the netX power pins However only power pins on the two outer BGA rings should be connected that way All inner power pins should connect to the plane directly
65. following schematics 1 5V F17 PHY_VDDCAP 17 C2 PHYO VDDCART D20 100 3 3V PHY1 VDDCART J20 PHY_VDDIOAT PHY_VDDIOAC L C4 J21 10 E18 H18 GND H19 G18 519 E19 F19 PHY_VSSAT PHY_VSSACP PHYO VSSAR PHYO VSSAT1 PHYO VSSAT2 PHY1 VSSAR PHY1 VSSAT1 PHY1 VSSAT2 PHYO TXP al 0 2a 0 Het PHYO RXN PHY1_TXP Ee PHY1_TXN Eel PHY1 RXP E20 PHY1_RXN ESI G19 PHY EXTRES G17 netX100 PHY ATP SS netX500 GND Figure 79 netX100 500 Ethernet Circuit PHYs Not Used netX Design In Guide netX 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 114 158 4 10 4 Ethernet Status LEDs Each of the netX Ethernet ports provides two status LED signals Link and Activity The link status LED is lit when a link has been established on the corresponding Ethernet port while the yellow activity LED flickers when data is received or transmitted on the corresponding port The following table shows the standard pin assignment for the status LEDs Function LED color Pin name an number Ethernet Port 0 Link Sat green XMO 100 19 Ethernet Port 0 Activity yellow XMO 101 18 Ethernet Port 1 Link Sat green 1 100 19 Ethernet Port 1 Activity yellow 1 101 18 Table 36 Status LEDs for Ethernet Ports netX100 500 use
66. into play with graphical operating systems like Windows CE or for applications executing code directly out of FLASH the use of parallel FLASH is inevitable Parallel FLASH connected to the netX may be 8 16 or 32 Bit wide while two 16 Bit components may be paired for 32 Bit wide access Note rcX does not support parallel flash It can no file operations are executed with rcX Though 16 Bit wide components are most common for performance reasons 32 Bit components should be used when executing code directly out of FLASH The netX SRAM FLASH memory controller provides three different chip select signals MEM_CS 2 0 allowing to select three different memory components or pairs of components two netX Design In Guide 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 77 158 paired 16 Bit FLASHes use a common chip select signal each with its own set of parameters timing and bus width When the design is to boot from parallel FLASH chip select 0 must be used for selecting this FLASH The memory controller is designed to never waste any address lines regardless of the bus width setting Hence in 8 Bit mode address line AO is used for low and high Byte selection while in 16 Bit mode 0 selects low and high word and in 32 Bit mode 0 is simply the LSB of a DWORD address For that reason the data sheet of the desired FLASH component must be con
67. low high signals type Interface Circuit 16Bit non Multiplex EXT A0 24 EXT CSO 3n EXT ALE III RD WRn DS EXT_RDn EXT_WRLn EXT_RDYn Q RDY WAIT EXT_INT C INT EXT_D0 7 Motorola 8 Bit one data strobe Figure 64 netX DPM Motorola Type Interface Circuits non Multiplex 4 7 3 Multiplex Mode The netX host interface can also be operated in multiplexed mode where the data lines are alternatingly used for data and the lower address signals The following schematics show some examples for common setups in multiplexed mode netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits EXT_A8 24 EXT_CS0 3n EXT_BHEn EXT_ALE EXT_RDn RD EXT_WRLn WR EXT_WRHn EXT_RDYn RDY WAIT EXT_INT INT EXT_CS0 3n EXT_BHEn EXT_ALE EXT_RDn EXT_WRLn EXT_WRHn EXT_RDYn EXT_INT EXT_D0 15 Intel 16 Bit one write signal Figure 65 netX DPM Intel Type Interface Circuit Multiplexed netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public 95 158 EXT_A16 24 MEM A n sj C C Y EXT_RDYn RDY WAIT EXT_INT INT EXT D0 15 Intel 16 Bit write low high signals Hilscher 2008 2012 Standard Circuits 96 158 EXT_A8 24 EXT_A16 24 EXT 50 3 EXT CSO 3n CS EXT AL
68. m By 9 0144 0 5 Sopa AHd 394 TIT aba 2 4 8 Old aH ux oid DA d 30001 zo O Ly OLY ae e aveau 10H 005 00 LXU 59 L ve REL t ai S TDi X x 008 00 LX39u x90 2 8uut E98 005 00 LXU p srun ddns o eq o vey sued 006 00 LXU vL L eL 0L 6 8 1 9 S L Hilscher 2008 2012 Figure 18 netX100 500 Basic Circuit ADC Host Interface PHY RTC DOC081106AN02EN Revision 2 English 2012 10 Released Public netX Design In Guide netX 100 500 21 158 netX100 500 Quick Start vL eL 6 8 Z 9 S L Jo woouoyos WW ed dds amp WOReWONEWEIS S SENS BINE 21524 009 001 39u En yeuosiesec SUNG OF Ye ir 7 ge 1 t yoo 8 1002 r 26
69. possible T TXD IN 2 7 TXD IN ur L i RXD OUT y7 RXD OUT FX Transceiver sp RE Single ended signal line Z 50 Ohm Termination resistors Place as close to level translators as possible Figure 76 netX Ethernet Circuit Fiber Optic Component Placement netX Design In Guide netX 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 110 158 Transceivers with internal AC termination Place level translators BIAS resistors Place as Termination resistors as close to netX pins close to level translators Place as close to level as possible as possible translators as possible Hi Speed single ended signals Keep traces Keep traces as Differential signal lines as short as possible short as possible Zdiff 100 Ohm 2 Transceiver I TXD IN jure od TXD IN um d Hr RXD OUT ME em RXD OUT zo T SD Single ended signal line Z 50 Ohm Termination resistors Place as close to level translators as possible Figure 77 netX Ethernet Ci
70. signals can t just tie these signals to GND or 3 3 V A1 This is of course possible but keep in mind that almost all host interface pins can be configured to output mode hence when tying such signals to GND or 3 3 V there is always the risk of short circuit conditions when misconfiguring the host interface e g during software development netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 97 158 4 8 UARTs The netX provides a total of three UARTs each with RX TX RTSn CTSn that interface directly to common RS 232 or RS 485 transceivers as shown in the following example schematics UARTO is the UART that must be used when the serial boot mode via UART is to be available UARTO may further be used as diagnostic port by Hilscher firmware This example shows connection for UARTO UART1 and UART2 are connected equally UARTO TXD E Y18 UARTO RTSn UARTO RXD PAS lt UARTO_cTSn 18 netX100 netX500 RS 232 Transceiver e g MAX3232E Figure 67 netX100 500 UARTO If UARTO is not be used and the USB port is to support the serial boot mode then the following external pull up resistors are required on netX100 500 UARTO pins 3 3V Y19 GPIO01 UART0_TXD x 27 4 18 e 003 UARTO_RTSn 19 GPIO00 UARTO RXD GPIO02 UARTO_CTSn netX100 ne
71. t handle the PWM signal directly but requires a constant voltage for intensity control an RC filter as shown below must be implemented Note Please note that this functionality has only been realized with Windows CE images for netX500 boards Further the GPIOs are in no way linked to or controlled by the LCD controller hence the backlight control functionality must always be realized completely by software GPIO14 10k 10k Backlight 100nF 100nF netX 500 GND GND Figure 94 LCD Backlight PWM RC Filter Windows CE netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 135 158 4 16 Touch Panel Interface Though the netX500 is not equipped with a touch panel controller such a functionality can easily be implemented by using two I O signals and two channels of the internal AD converter along with a few external components as shown in the following schematic XM3_101 en XM3_100 3 3V 16 A 4 Renee ea 11 gt ZEE 2 1 Lo 400nF 1 1 1 1k A A 47nF N N Resistive Touchpanel GND 3 3V A 100nF AAA 1K A UN ae GND Figure 95 Touch Panel Circuit The NLAS44599 ON Semiconductor is an integrated component containing 4 analog switches perfe
72. the IO signals of XMACO and XMAC1 for Ethernet status signaling The schematics below must be used whenever the design is to be operated with loadable Firmware from Hilscher 3 3V Channel 0 Channel 1 Link Link MT g y gt gt gt rx 29 _ IN N19 XMO 100 101 79 xu1 220 1_ 721 19 1 100 netX100 netX500 1 101 18 Figure 80 netX100 500 Ethernet Status LED Circuit netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 115 158 4 10 5 Real Time Ethernet Besides running standard Ethernet protocols the netX is able to run all current Real Time Ethernet RTE protocols The physical interface for RTE protocols is identical to the standard Ethernet port as described in the preceding chapters except some additional synchronization signals that may be required depending on protocol and application as well as some additional status LED signals Both are described in the following chapters Note Regardless if these signals are used in an application any RTE protocol will always occupy the XPEC3 XMAC3 unit on the netX100 500 hence this unit can never be used for any other purpose like a field bus interface whenever an RTE protocol is running 4 10 5 1 Sync signals The netX100 500 provides up to two additiona
73. time the voltage level at the XR input resembles the Y position of the current touch point When the Y position has been captured TP YON I O XM3 101 must be set to low level again Now the current position is known and the system can return to idle mode Due to non linearity and wear aging it is recommended to also implement a calibration function that shows a few calibration points at known positions on the display while the user consecutively touches these points By comparing the measured coordinates to the coordinates of the calibration points appropriate correction factors can then be calculated allowing to compensate the deviations The required settling time between changing the switch signals and performing the acquisition of the analog touch panel signals must be evaluated In electrically noisy environments it may also be necessary to perform several measurements and use the average trading response time for accuracy netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 137 158 4 17 The netX chip contains several programmable input output lines Each of the 83 PIO can be used as simple input or output without any additional features The first 31 PIO pins PIOO PIO30 shared with Motion Control pins LCD pins and ETM pins 53 other Pins 2 84 shared with Host Interface Pins PIO31 does not
74. word access the address line AO should be connected to GND The following table shows the decoding logic for byte and word access BHE AO Function 0 0 word access 0 1 access high byte 1 0 access low byte 1 1 no access Table 30 Function Table of 16 Bit Decode Logic 4 7 1 2 Non multiplexed mode The following schematics show some examples for common setups in non mulitplexed mode A0 15 DPM 0 15 DPM CSn PM CSn PM BHEn D D DPM RDn RD DPM RDn DPM WRLn WR DPM WRLn DPM WRHn DPM WRHn DPM RDYn RDY WAIT D DPM RDYn DPM INT INT DPM INT netX DPM D0 15 netX Intel interface 8 Bit non multiplexed Intel interface 16 Bit non multiplexed Figure 55 netX DPM Intel Type Interface Circuits 1 netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits _ 1 15 DPM_CSn RD WRL WRH RDY WAIT D DPM_RDn DPM_WRLn DPM_WRHn DPM_RDYn DPM_INT DPM D0 15 netX Intel interface 16 Bit non multiplexed 2 write signals Low Byte High Byte Table 31 netX DPM Intel Type Interface Circuits 2 DPM RDYn DPM INT DPM D8 15 DPM 0 7 netX Motorola ColdFire 16 Bit non multiplexed Figure 56 netX DPM Motorola Type Interface Circuits netX Design In Guide 100 500 DOC08110
75. za 3049 s 2 5 SIO 2575 New Sr UTHVIT Umwrgivy OSLO ki mimm MEX imis germ 006 3 RT 1089 9 ae Vly tmm EZS Xe cECSH 3400 5090 Y 0 LOLX zie LOL vL L eL 6 8 Z 9 9 v L Figure 32 UART lt gt RS232 Circuit netX Design In Guide netX 100 500 Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX100 500 Quick Start 48 158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 K1 Microcontroller netX100 500 K101 Transceiver MAX3232EEUP R131 Resistor 3 3 63 mW 0603 R132 Resistor 100 125 mW 0805 101 D Sub9 Female SUYIN USA Part No 070212FR009G200ZU Table 18 BOM UAHT 5232 More about UART circuits can be found on Page 97 chapter 4 8 UARTs netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 49 158 netX100 500 Quick Start 2 11 USB Device Mode
76. 014 8014 5120 8 050 5 Lolo T MAN ae i YOLO 2013 209 T gz Nn lt 1 20 m 1081 2014 vl L 4 6 Z 9 6 v e L Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX Design In Guide netX 100 500 Figure 25 AS Interface Circuit netX100 500 Quick Start 34 158 Bill of Materials REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 10 uF 10 V 0805 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 100 nF 50 V 0805 C105 Tantalum Capacitor 22 uF 35V C106 Ceramic Capacitor 10 nF 50 V 0603 G101 Crystal RS CM7050 8 MHz K101 Triple Channel Digital Isolators ADUM1301CRW K102 Advanced AS Interface IC ASIAUC E M P101 LED red green HSMF C155 R101 Resistor 270 63 mW 0603 R102 Resistor 470 O 63 mW 0603 R103 Resistor 100 kO 63 mW 0603 R104 Resistor 10 kO 63 mW 0603 R105 Resistor 10 kO 63 mW 0603 R106 Resistor 10 kO 63 mW 0603 R107 Inductor 4 7 mH 0 1 A W rth Elektronik Part No 744775347 R108 Diode LL4148L R109 Diode SM4004 R110 Diode BZG03C39 R111 Diode LL4148L R112 Resistor 22 63 mW 0603 R113 Resistor 1 63 mW 0603 R114 Resistor 12 4 63 mW 0603 R115 Inductor E
77. 0mA when a short circuit on the USB cable occurs When the design is to continue working under that condition the netX VDDIO rail 3 3 V must either be able to deliver this additional current or the USB_VDDIO supply must be connected to the 3 3 V rail through an appropriate fuse or current limiter PTC or a separate supply Like ALL power supply pins on the netX the USB power supply pins must always be connected even when the USB interface is not used 4 9 1 Device Mode 4 9 1 1 Simple Circuit The device mode is the commonly used mode of the netX USB interface and allows to connect the netX to a PC in serial boot mode which can then download and flash firmware read and modify register values and run hardware test applications by the help of freely available software tools from Hilscher In order to be able to use this handy and yet simple debug and service connection the implementation of a USB device port is always recommended whenever allowed by board size constraints Note With netX100 500 designs that do not use the UARTO port of the netX please make sure that the required pull up resistors on UARTO are present otherwise the serial boot mode via USB won t work see chapter 4 8 for details netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 99 158 33V usa 218 1 5V 1 A 120 VBUS _
78. 0nF 2 60 00 0 c O O P OO N 9 No 74 252529209202 20 500 2210 000 G Figure 15 netX100 500 Power Connection 2 D Pull Down Resistors OU 6565569 60 0 0 0 Sk Sa Sy 23 NOOKRWNH AO A21 5 x N Q D 1 C417 0603 400nF 2 1 C419 0603 400nF 2 1 C420 0603 400nF 2 C422 0603 400nF 2 C418 805 10uF 2 C421 0805 10uF 2 17 158 3V3 A The basic circuit does not use the pins D16 WDGACT watchdog active and B18 CLKOUT clock out and have always connected to GND over a 10 resistor in this case Not Connected Pins All other pin of netX100 500 has not to be connected netX Design In Guide 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 18 158 Hilscher 2008 2012 123 4 OL 6 8 Z 9 6 v e L S Jo abed Jayos y mm WEIL HSWIHdS WSFOSS ESTAN uin c LLOZ OL VC
79. 10 Released Public netX Design In Guide netX 100 500 netX100 500 Quick Start Bill of Materials 31 158 Page 1 REF DES PART TYPE PART NAME C401 Ceramic Capacitor 10 uF 10 V 0805 C402 Ceramic Capacitor 100 nF 25 V 0603 C403 Ceramic Capacitor 10 uF 10 V 0805 C404 Ceramic Capacitor 100 nF 25 V 0603 C405 Ceramic Capacitor 100 nF 25 V 0603 C406 Ceramic Capacitor 100 nF 25 V 0603 C407 Ceramic Capacitor 100 nF 25 V 0603 K101 Microcontroller netX100 500 K402 IC Switch 464 K403 Driver SY89322VMGTR K404 Driver SY89323LMGTR K405 Driver SY89323LMGTR K406 Schmitt Trigger and Inverter NC7SZ14P5X K407 Schmitt Trigger and Inverter NC7SZ14P5X R401 Ferrite 100 MHz 600 O 1 A 1206 R402 Ferrite 100 MHz 600 1 1206 R403 Resistor 12 4 63 mW 0603 R404 Resistor 82 63 mW 0603 R405 Resistor 130 63 mW 0603 R410 Resistor 10 63 mW 0603 R411 Resistor 10 63 mW 0603 R412 Resistor 10 63 mW 0603 R413 Resistor 10 kO 63 mW 0603 R414 Resistor 47 63 mW 0603 R415 Resistor 47 63 mW 0603 Table 7 BOM Fiber Optic Page 1 netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 32 158 Page 2
80. 102 Resistor 1 3 kO 63 mW 0603 R103 Resistor 4 02 kO 63 mW 0603 R104 Ferrite 100 O 100 MHz 1 A W rth Elektronik Part No 74279207 R105 Ferrite 100 O 100 MHz 1 A W rth Elektronik Part No 74279207 R106 Resistor 270 O 63 mW 0603 R107 Resistor 470 O 63 mW 0603 R108 Resistor 470 63 mW 0603 R109 Resistor 470 O 63 mW 0603 R110 Resistor 4 02 kO 63 mW 0603 R111 Resistor 4 3 kO 125 mW 0805 R112 ESD protection diode PEAK part no PSD 3R305S R113 Varistor Epcos Type SIOV CN1812K30G Ord Code B72580 V0300K062 R114 Resistor 1M 0500 mW 2010 R115 Resistor 1M 0500 mW 2010 T101 DC DC Step Up PEAK part no PSD 3R305S T102 Voltage Regulator NCP500SN50T 1 X101 Connector MC1 5 5 G 3 81 Table 14 BOM DeviceNet Circuit More about DeviceNet circuits can be found on Page 118 chapter 4 11 Fieldbus Interface Page 124 chapter 4 11 5 DeviceNet Interface gt Page 126 chapter 4 11 7 Fieldbus Status LEDs netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 43 158 netX100 500 Quick Start 2 8 PROFIBUS vL L eL 6 8 Z 9 4 L
81. 2 A D Converter When using the AD converters of the netX100 500 the supply voltages for the ADC circuit and its reference voltages should be filtered to avoid power supply noise to influence accuracy of the sampled values The following circuit shows a recommendation however the filter components may have to be modified to meet the special requirements of a particular system Note All filter components are application specific and should be evaluated Shown values are only an example ADCO 1 5 ADCO INO ADCO IN1 IN ADCO IN1 IN2 WS EN ADCO_IN2 ADCO 1 5 EN ADCO_IN3 ADC0_vppio WS n 133v Ferrit 1000 OHM 100 MHz 200 mA M 4 gt 10 ADC0_VREFP V n gt ADC_VREFP Filtered supply for additional a analog circuits ADCO VREFM LIBRE ADC_AGND vss Y Optional filter i for separate analog ground GND ADCA INO ADC INO anci IN1 W3 ADC1 IN1 ADC1 2 V4 EN ADC1_IN2 1 55 ADC1_IN3 W4 ADC1_VDDIO AA3 ADC1_VREFP ADC1_VREFM ADC1_vss 94 netX100 500 Figure 89 ADC Circuit netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 128 158 If the second ADC channel is not used it still needs to powered as shown in the following sc
82. 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 65 158 4 2 Secure EEPROM The secure EEPROM available for netX controllers can hold licensing information MAC addresses and other information While it is generally recommended to design in this component it is mandatory for all designs that are to run any Hilscher Master stacks e g PROFIBUS Master EtherCAT Master or use the PCI interface of the netX500 A detailed Application Note explaining the purpose and use of the Secure EEPROM is available on the Hilscher website On the netX100 500 the secure EEPROM is connected to the interface as shown by the following schematic 3 3V AT88SC0104C W15 W14 2 SCL 2 SDA GND Other optional components Figure 40 Sample Schematic netX100 500 Secure Memory The netX secure memory can be connected parallel to other I C components as shown in the schematic above It responds to device addresses starting with 0xB 1011 hence designers have to make sure that no other connected 12 component uses this address space netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 66 158 4 3 Crystals Clock generators 4 3 1 System Clock netX100 and netX500 all use either an internal oscillator along with an external crystal or an external oscillator for generating the 25 MHz base clock which i
83. 3 Boundary Scan netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 55 158 2 14 LCD Interface netX100 500 Quick Start vl L OL 8 2 9 5 L 2s HOLO3NNOO I1QOAF GO1 nn 91 g gt 1945 IH LLOZZL 80 era IZAN SEEN DANZEOHZEVZIN LAL SbiFZZOHCEVZ IN E 229 Tod COT LOld O d L 9014 2702 3080 Ae ds q 4 vold GOMASEO SEHEZHA 72295 78 L 0 LL 90 4 95 id Ord aras IE 09 ZOLM od 0N ao Marao ip KaL uaa 52 00 Izbnar ao1 Op Thal di 021 007 dL 007 a E D OS 38 z X B 000 0122 00SXL3N OHOIA ovs WE 250145 ener 28 015 i cold 18 150795 053 185 Y le V am ATO lds m _ er ISON lds gt RISA Go OSI 145 WOT 05 F IM onze Ko SMS GOT INT
84. 6 Oscillator Circuit with Ground 147 Figure 107 Edge Coupled Sourface Micro 148 Figure 108 Edge Coupled Offset Strip 149 Figure 109 Memory u arie tee eerte eR ll tede 149 Figure 110 Routibg Example 2 nen 150 Figure 111 Vias and Traces under netX100 500 Top and Bottom 5 151 netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Contacts 7 Contacts Headquarters Germany Hilscher Gesellschaft fur Systemautomation mbH Rheinstrasse 15 65795 Hattersheim Phone 49 0 6190 9907 0 Fax 49 0 6190 9907 50 E Mail info hilscher com Support Phone 49 0 6190 9907 99 E Mail de support hilscher com Subsidiaries China Hilscher Systemautomation Shanghai Co Ltd 200010 Shanghai Phone 86 0 21 6355 5161 E Mail info hilscher cn Support Phone 86 0 21 6355 5161 E Mail cn support hilscher com France Hilscher France S a r l 69500 Bron Phone 33 0 4 72 37 98 40 E Mail info hilscher fr Support Phone 33 0 4 72 37 98 40 E Mail fr support hilscher com India Hilscher India Pvt Ltd New Delhi 110 065 Phone 91 11 43055431 E Mail info hilscher in Italy Hilscher Italia S r l 20090 Vimodrone MI Phone 39 02 25007068 E Mai
85. 6ANO2EN Revision 2 English 2012 10 Released Public DPM 0 DPM_A1 15 DPM_CSn DPM_BHEn DPM_ALE DPM_RDn DPM_RDYn DPM_INT DPM_D8 15 DPM_DO 7 netX Motorola M68000 16 Bit non multiplexed Hilscher 20 86 158 08 2012 Standard Circuits XREADY XA 14 1 DPM_RDY DPM_A 15 2 XWE 1n XAO XD 15 0 DPM A1 DPM 0 DPM D 15 0 XZCS0 6 7n XRDn XWEOn XINT TMS320 DPM_CSn DPM_RDn DPM_WRLn DPM_INT DPM_WRHn DPM_BHEn DPM_ALE netX100 500 Figure 57 Texas Instruments 320 2833 16 Bit Non Multiplexed Note The netx100 500 interprets the passed address as 8 Bit Datum netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public 87 158 Hilscher 2008 2012 Standard Circuits 4 7 1 3 Multiplexed Mode The netX host interface can also be operated in multiplexed mode where the data lines are alternatingly used for data and the lower address signals The following schematics show some examples for common setups in multiplexed mode DPM_A8 15 DPM_CSn DPM_ALE DPM_RDn DPM_WRLn DPM_WRHn DPM_RDYn DPM_INT Host _00 7 Intel interface 8 Bit multiplexed Figure 58 netX DPM Intel Type Circuits Multiplexed DPM_A8 15 DPM_CSn DPM_BHEn DPM_ALE DPM_RDn RDY WAIT D DPM_RDYn INT DPM_INT DPM_DO 7
86. 9 XMO_RX PHY1_VSSAT2 N e 10 NIN 86 2 R3 127 XMO 100 PHYO TXP XMO 101 i i i i i FX Transceiver PHY0_TXN cm PHYO RXP ue H20 PHYO RXN F20 PHY1 TXP F21 TXD IN PHY1_TXN XM1_TX TXD IN RXD OUT XM1_RX E20 OUT PHY1_RXP M XM1 100 E21 netX100 E TXDIS PHY1_RXN netX500 101 i i i i i FX Transceiver G19 PHY_EXTRES d G17 i SND netX100 PHY_ATP UN GND netX500 T GND Figure 74 netX100 500 Ethernet Circuit Fiber Optic netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 106 158 Component Value Tolerance Rating R3 R4 R5 R6 R7 R13 127 0 130 O 1 R14 R15 R16 R17 R8 R9 R10 R11 R12 82 5 0 82 1 R18 R19 R20 R21 R22 R24 1 82 R24 1 6 130 R23 12 4 196 125 mW C1 C3 100 nF 6 3V C2 C4 10 uF 6 3V R1 R2 1000 100 MHz 200 mA Table 34 Fiber Optic Ethernet Circuit Component Specification netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 4 10 2 2 Transceivers with internal AC termination 107 158 Some
87. C is not used it must still be connected to the power supply MICRO NETX500 2210 000 GND Figure 9 Unused ADC Basic Circuit More about ADC Converter circuits can be found on gt Page 127 chapter 4 12 A D Converter netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start SDRAM 12 158 The standard Hilscher loadable firmware uses 8 MB SDRAM The following figure shows the connection of ISSI SDRAM with 86 pin TSOP package 1542532200 1 MEM_D 00 31 netX100 500 G4 MEM Do H 202 MEM 00 23 MEM D1 7 MEM 02 55 DO 8MB SRAM MEM D3 DD MEM Da MA MEM DOs C201 D5 PA MEM DO 3V3 MEM 06 pa MEM DO RAM 512k x32 x4 MEM 07 MEM DB C3 MEM 009 A00 25 ao MEM 009 MEM A01 26 D9 73 MEM 610 02 2r M VDD2 MEM D10 Hey 01 UEM A03 60 2 yobs C202 1 C203 011 VDD4 45 M3 D1 04 61 44 0603 400nF 0603 400rF MEM_D12 4 VSS1 14 D1 MEM A05 62 MEM D13 5 vss2 2 2 P3 MEM D14 06 63 MEM 014 VSS3 MEM D1 MEM A07 64 aM 86 015 654 gt DI 017 MEM A08 65 D16 52 D1 MEM A09 66 8 3 MEM_D17 A9 VDDQ1 GND ri C1 018 MEM
88. E EXT ALE AS EXT RDn EXT WRLn EXT RDn RD WRn EXT WRLn BSO EXT WRHn BS1 EXT RDYn Q RDY WAIT EXT_RDYn Q RDY WAIT EXT_INT C INT EXT INT INT EXT D0 7 EXT D0 15 Motorola 8 Bit one data strobe Motorola M 16 Bit two data strobes Figure 66 netX Extension Bus Motorola Interface Circuit Multiplexed 4 7 4 External pull ups pull downs unused signals As already mentioned at the beginning of the chapter 4 7 the netX100 500 does not provide any internal pull ups or pull downs on the host interface signals For that reason any unused signals of the host interface should either be externally pulled low or high or should be configured as outputs and be driven low or high by the firmware of the design Since even the connected signals of the host interface may float upon reset they are all configured as inputs by default designers should make sure that these initially floating signals will not cause any start up problems with the host interface circuit of their design If in doubt add external pull ups or pull downs to ensure the appr inactive state of the signals The CLOCKOUT signal and the WDGACT signals should always be pulled low or high when not used since these signals can not simply be driven low or high The TCLK signal should always be grounded this is a dedicated input so grounding is not a problem Q1 Instead of using external pull down or pull up resistors on unused host interface
89. EF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 22 uF 6 3 V 0805 C104 Ceramic Capacitor 22 UF 6 3 V 0805 C105 Ceramic Capacitor 22 uF 6 3 V 0805 C106 Ceramic Capacitor 2 2 uF 1000 V 1808 K101 Transceiver IL3585E P101 LED red green HSMF C155 R101 Ferrite 100 100 MHz 1 A Wirth Elektronik Part No 74279207 R102 Ferrite 100 100 MHz 1 A Wirth Elektronik Part No 74279207 R103 Resistor 270 63 mW 0603 R104 Resistor 470 63 mW 0603 R105 Resistor 330 63 mW 0603 R106 Resistor 100 63 mW 0603 R107 Resistor 100 63 mW 0603 R108 Resistor 1M Q 500 mW 2010 T101 DC DC Step Up PEAK part no PSD 3R305S T102 Voltage Regulator NCP500SN50T1 X101 D Sub9 Female SUYIN USA Part 070212FR009G200ZU Table 15 BOM PROFIBUS Circuit More about PROFIBUS circuits can be found on gt Page 118 chapter 4 11 Fieldbus Interface gt Page 125 chapter 4 11 6 PROFIBUS Interface gt Page 126 chapter 4 11 7 Fieldbus Status LEDs netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 45 158 2 9 MMC SD Card SPI Circuit The following figure shows the standard circuit to connect MMC SD Card with netX100 500 It is important GPIO15 Pin V13 of netX100 500 to connect to the MMC SD insert contact Otherwise it is a normal SPI conn
90. EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 15 158 Host Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 16 158 Power Supply 3 3 V The following figure shows a power supply circuit for 9 24 V input voltage and 3 3 V 3 A output The main part of the power supply is the MIC2198 9V 24V power in line 9V 24V C401 1 C402 Ten 1210 10 1210 10 1210 10 2 2 2 C405 0805 490nF 2 K401 FDC5612 3 PMEG4005 T c407 8 10805 100nF 2 6 2 R404 04005 413 xp R403 4 C406 2 D1 K402 0 FDC5612 D4 R405 3V3 GND Figure 13 3 3 V Power Supply Standard Circuit Power Supply 1 5 V Core The Hilscher standard circuit uses the FAN2001 to produce the 1 5 V core voltage 05 22uF 0805 22uF Figure 14 1 5 V Core Voltage Regulator netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start More about power supply circuits can be found on gt Page 138 Chapter 4 18 Power Supply netX100 500 Power Supply Pins The following figure shows the connection of netX100 500 to the power supply 1V5 1 C416 0603 40
91. For this reason no guarantee can be made and neither juristic responsibility for erroneous information nor any liability can be assumed Descriptions accompanying texts and documentation included in the user manual do not present a guarantee nor any information about proper use as stipulated in the contract or a warranted feature It cannot be ruled out that the user manual the accompanying texts and the documentation do not correspond exactly to the described features standards or other data of the delivered product No warranty or guarantee regarding the correctness or accuracy of the information is assumed We reserve the right to change our products and their specification as well as related user manuals accompanying texts and documentation at all times and without advance notice without obligation to report the change Changes will be included in future manuals and do not constitute any obligations There is no entitlement to revisions of delivered documents The manual delivered with the product applies Hilscher Gesellschaft fur Systemautomation mbH is not liable under any circumstances for direct indirect incidental or follow on damage or loss of earnings resulting from the use of the information contained in this publication 1 2 3 Exclusion of Liability The software was produced and tested with utmost care by Hilscher Gesellschaft fur Systemautomation mbH and is made available as is No warranty can be assumed for the performance a
92. Gate NC7SZ08P5 K102 Transceiver AD51 025 P101 LED red green HSMF C155 P102 LED red green HSMF C155 R101 Resistor 1 kO 63 mW 0603 R103 Ferrite TDK Part No MMZ1608B301C R104 Ferrite TDK Part No MMZ1608B301C R105 Resistor 10 O 63 mW 0603 R106 Resistor 10 O 63 mW 0603 R107 Resistor 10 O 63 mW 0603 R108 Resistor 10 O 63 mW 0603 R109 Resistor 150 O 63 mW 0603 R110 Diode NEC Type No RD6 2S Class B1 R111 Diode NEC Type No RD6 2S Class B1 R112 Diode NEC Type No RD6 2S Class B1 R113 Diode NEC Type No RD6 2S Class B1 R114 Resistor 22 63 mW 0603 R115 Resistor 270 63 mW 0603 R116 Resistor 470 63 mW 0603 R117 Resistor 270 63 mW 0603 R118 Resistor 470 63 mW 0603 R119 Inductor TDK Part No ACM3225 102 2P T101 Transformer OMRON 03 7104 X101 Connector OMRON XW7D PB4 R Table 12 BOM CompoNet Circuit Optional Bill of Material C105 Ceramic Capacitor CKSS22UV6 3 0805 C106 Ceramic Capacitor 22 6 3 V 0805 C107 Ceramic Capacitor 22 uF 6 3 V 0805 R120 Ferrite 100 100 MHz 1 A Wirth Elektronik Part No 74279207 102 DC DC Step Up PEAK part no PSD 3R305S T103 Voltage Regulator NCP500SN50T 1 Table 13 Optional BOM CompoNet Circuit More about CompoNet circuits can be found on Page 118 chapter 4 11 Fieldbus Interface Page 123 chapter 4 11 4 CompoNet Interface netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released P
93. L WAX ool Wx Xe WX TOF WX 0 INXS ex INXL yeu jey p Aue eoejd p Jed s AZL GIN on saa on TOF NX 000 0LZZ 00SXLIN OYN Lam 6014 619 S3HLX3 i 6010 gut 3001 50 80 2 ZLVSSA SI HVSSA 5 5 6 NXS 128 AMT Qi rel NXT TARE pgg MHd 090 0b 8014 T os 05 I voldl rl OL 42014 gvo i os CHITI 024 5 2019 UNS et MOL 50 9019 CJVSSA BID NXH UXHd OAH 9 WHE UXHd Hd NXL OAH ozo NXL V LOLX NONA NONA VO N3389 VO DA v6 Or vor O LOLX 5090 kr oL 9014 08 Qr ord 05 eola 2090
94. LLdO 1 Wo A ee ee ee ctu e a te Lee ee 1 i T El T Old m 8r uaa 090 QNO T z Ea T ELLY LLIN ana 5 1857904 21 090 17 od Y Y 4 Z 2 39 7 050 l adzy as PINE YOLO us N 019 sun i 090 gt 090 dri eoe 7 5 0 0 a PEN 109 d 25 El Po ile ost 5 q EUR may 6014 T 090 N00SV00eS431 M LOLX 6LLY 3145 oL oL 002 ax o M S Qs pe LOLL coly oe 71 _ 3400 v cn p Iz Dera Iu 090 qub e ord 2017 GALVIOS v oL 6 8 2 9 9 v 4 L Figure 28 CompoNet Circuit netX Design In Guide netX 100 500 Hilscher 2008 2012 DOC081106AN02EN Revision 2 English 2012 10 Released Public netX100 500 Quick Start 40 158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 47 pF 50 V 0603 C104 Ceramic Capacitor 47 pF 50 V 0603 K101 2 Input AND
95. PCOS B82790C0474N215 X101 Connector MC1 5 2 G 3 81 Table 9 BOM AS Interface Circuit More about AS Interface circuits be found on Page 118 chapter 4 11 Fieldbus Interface Page 120 chapter 4 11 1 AS interface Master gt Page 126 chapter 4 11 7 Fieldbus Status LEDs netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 35 158 v l e 6 8 2 9 S v 6 L Jo UUOO J UDSJIU AWA NVO HLOZOVOL ANY yeuosjesec JOuosiH Jezieyysengew paupa 2 0 9 2 i 1 090 mi OLIM wet old Th 1 1 1 9 2 4 CANopen netX100 500 Quick Start ssvede asd 240040 0001 Z ogas ee LLOSNSOOSdON t J luno N 89014 FU 5060 NZZ 5080 lee PZ 2019 90 9 0 amp SOLD AANOOL 0001 2 g NAT k HL 5 AAA coll ZOLY 9 09
96. R103 Resistor 470 63 mW 0603 R104 Resistor 470 63 mW 0603 R105 ESD protection diode PESD1CAN R106 Resistor 1M 0500 mW 2010 R107 Ferrite 100 100 MHz 1 A Wirth Elektronik Part No 74279207 R108 Ferrite 100 100 MHz 1 A Wirth Elektronik Part No 74279207 R109 Resistor 270 63 mW 0603 R110 Resistor 470 63 mW 0603 T101 DC DC Step Up PEAK part no PSD 3R305S T102 Voltage Regulator NCP500SN50T1 X101 D Sub9 Male SUYIN USA part no 070211MR009G200ZU Table 10 BOM CANopen Circuit More about CANopen circuits can be found on gt Page 118 chapter 4 11 Fieldbus Interface gt Page 121 chapter 4 11 2 CANopen Interface gt Page 126 chapter 4 11 7 Fieldbus Status LEDs netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 37 158 netX100 500 Quick Start 25 CC Link vL L eL 6 Z 9 9 v L L 9 9 JO2 JOUOS IU NWM L papayo
97. SELA14 DPM SELA15 DPM SELA16 DPM SELA17 DPM SELA18 DPM SELA19 4k addressable Host netX 3V3 Figure 61 netX Internal Chip Select Generator Circuits netX Design In Guide 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 92 158 4 7 1 6 RDY WAIT Signal Since the DPM mode of the netX host interface provides a virtual Dual Port Memory instead of a real DPM external accesses to the DPM are redirected to programmable memory locations inside the netX there is no fixed access time for reading or writing the DPM even when there is no access conflict Real DPM components however also use a Busy signal to compensate access conflicts one side of the memory reads a certain memory location while the other side tries to write the same location or vice versa In order to make sure that the host processor will read valid data respectively the netX successfully accepted write data from the host while keeping access cycles as short as possible it is mandatory for the host processor to support a Ready or Wait signal from an external memory To allow glueless interfaces the netX RDY WAIT signal supports two different basic modes Ready mode where an active Ready signal indicates that the cycle may now be terminated and Wait mode where an active Wait signal indicates that the netX is still busy
98. SPI FLASH is mandatory When connecting memory components to the parallel FLASH SRAM SDRAM interface designers should always mind the capacitive load that is applied to the interface signals by the memory components The memory interface of the netX100 500 is designed to handle a maximum load capacity of 50 pF on data address and DQM3 0 lines and 25 pF on all other control signals The capacitive load directly influences the signal timing the higher the load the longer the signal delay which has limited scope with SDRAMs Since the allowed range of operating conditions min max voltage min max temperature further influences signal timing capacity limits needed to be defined that ensure safe operation throughout the whole voltage and temperature range When exceeding these capacity limits this may to a certain amount be compensated by two clock phase parameters of the SDRAM interface hence such out of spec designs are imaginable but require careful evaluation 4 6 1 FLASH Memory 4 6 1 1 SPI FLASH SPI FLASH components consume considerably little space SO 8 package on the PCB while being able to hold large firmware images of 4 or even greater hence it is always recommended to add such a FLASH to any design if allowed by board size constraints Even designs using a parallel FLASH as firmware memory or designs that receive their firmware through the DPM interface from an external host processor can benefit from an
99. T GND Figure 6 netX100 500 Reset Circuit More about reset circuit can be found on gt Page 69 Chapter 4 4 Power On Reset and Reset In USB The device mode is the commonly used mode of the netX USB interface and allows to connect the netX to a PC in serial boot mode which can then download and flash firmware read and modify register values and run hardware test applications by the help of freely available software tools from Hilscher 33V 1 5 USB_VDDIO USB_VDDC GPIO12 am veus NE 0 3 USB_DPOS mJ D 2 1 SN65220D m usa 879 2 D i Receptacle usa vss am GND netX100 500 GND Figure 7 netX100 500 USB DOWN Stream Port Device Mode More about USB circuit can be found on gt Page 69 Chapter 4 4 Power On Reset and Reset In netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start UARTO 11 158 For using the serial boot mode on UBS port with unconnected UARTO the pin AA19 UARTO_RXD and pin AA18 UARTO_CTS have to be connected with 10 kQ pull up resistors to 3 3 V 3 3V A 19 GPIOO1 UARTO_TXD amp 5 GPIO03 UARTO_RTSn 348 19 GPIO00 UARTO_RXD GPIO02 UARTO_CTSn netX100 netX500 Figure 8 netX100 500 UARTO Unused More about UART circuits can be found on gt Page 97 Chapter 4 8 UARTs AD Converter If the AD
100. TINn which is commonly used by an external host processor to reset the netX also provides a Schmitt trigger gate While the netX100 500 are not equipped with an internal pull up resistor it is recommended to tie it to VDDIO 3 3 V since this can improve EMC behavior When placing the components during PCB design the reset source s should be placed near the reset inputs of the netX to keep the traces off the reset signals short Routing reset signals all over the PCB may result in bad EMC behavior of the design since ESD may cause undesired resets of the chip Experience with several netX designs further has shown that a 1nF ceramic capacitor connected to GND and PORn with the capacitor located close to the netX PORn pin further improves resistivity against ESD The following figure shows the standard reset circuits egg ee REPERI e THEN EP Power on Open Collector RESET RESET Open Drain Output netX500 Kanes cut netX100 RESET 1nF GND Figure 44 netX Reset Circuits netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 70 158 4 5 Debug and Test Interfaces 4 5 1 JTAG Interface The netX100 and netX500 are equipped with a standardized JTAG Interface that allows loading flashing and starting firmware debugging of firmware and provides access to the Boundary Scan Test mode of the chips
101. Up PSD 3R305S T102 Voltage Regulator NCP500SN50T 1 X101 Connector MC1 5 5 G 3 81 Table 11 BOM CC Link Circuit More about CC Link circuits can be found on gt Page 118 chapter 4 11 Fieldbus Interface gt Page 122 chapter 4 11 3 CC Link Interface gt Page 126 chapter 4 11 7 Fieldbus Status LEDs netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 39 158 netX100 500 Quick Start 2 6 CompoNet vl eb e LL OL 6 8 2 9 4 rv 2 L Jo JaYyosyiy MW aea 13NOdNOO ed AEN N PRPA LLOZ LL SL ty JSZ semeyy papa EEE EE gt x 1 1 1 1 i LLOSNSO0SdON t i 50 45 k PZ 5080 JUL Heo 0 NZZ 100 l 9012 do sold zoa NAA oo ee wee COLL ZOLL x l l amp i 1 ayy Ajddns AG Ou SI 1 1 IVNO
102. V 0805 C419 Ceramic Capacitor 100 nF 25 V 0603 C420 Ceramic Capacitor 100 nF 25 V 0603 C421 Ceramic Capacitor 10 uF 10 V 0805 C422 Ceramic Capacitor 100 nF 25 V 0603 K401 Transistor FDC5612 K402 Transistor FDC5612 R402 Resistor 2 2 63 mW 0603 R403 Diode DIODE SCHOTTKY PMEG4005AEV R404 Diode DIODE SCHOTTKY PMEG4005AEV R405 Inductor CDRH8D43NP 100N R406 Resistor 0 018 250mW 1206 R407 Resistor 4 7 63 mW 0603 R408 Resistor 1 5 63 mW 0603 R410 Inductor CR32NP 3R3M R411 Resistor 1 8 63 mW 0603 R412 Resistor 1 96 63 mW 0603 401 Step Down MIC2198YML T402 Step Down FAN2001MPX Table 4 BOM Basic Circuit Page 4 netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 25 158 netX100 500 Quick Start ircuits 2 2 Ethernet Interface Twisted Pair Two Channel 2 2 1 v 6 4 9 5 v GALSIML LANYSHL gt A yeuos eseo LLOZ LL 80 aed Jez seumen pa p3 000 0LZZ 00SXLIN OYIN SUN cor ewx 610 enx ED xix TOT 815 ooranx Del zn xax TOF CNX VO
103. X Design In Guide netX 100 500 Figure 27 CC Link Circuit netX100 500 Quick Start 38 158 Bill of Material REF DES PART TYPE PART NAME C101 Ceramic Capacitor 100 nF 25 V 0603 C102 Ceramic Capacitor 100 nF 25 V 0603 C103 Ceramic Capacitor 100 nF 25 V 0603 C104 Ceramic Capacitor 100 nF 25 V 0603 C105 Ceramic Capacitor 100 nF 25 V 0603 C106 Ceramic Capacitor 22 6 3 V 0805 C107 Ceramic Capacitor 22 uF 6 3 V 0805 C108 Ceramic Capacitor 22 6 3 V 0805 C109 Ceramic Capacitor 100 nF 25 V 0603 C110 Ceramic Capacitor 100 nF 25 V 0603 C111 Ceramic Capacitor 3 3 nF 63 V 0805 K101 Optocoupler HCPL0601 K102 Optocoupler ACPL 072L K103 Optocoupler ACPL 072L K104 Schmitt Trigger FAIRCHILD Ord No NC7SZ14P5X K105 Transceiver TEXAS INSTRUMENTS Ord No SN75ALS181NSR P101 LED red green HSMF C155 R101 Resistor 220 63 mW 0603 R102 Ferrite 100 100 MHz 1 A Wirth Elektronik Part No 74279207 R103 Ferrite 100 100 MHz 1 A Wirth Elektronik Part No 74279207 R104 Resistor 270 63 mW 0603 R105 Resistor 470 63 mW 0603 R106 Resistor 1 63 mW 0603 R107 Resistor 10 63 mW 0603 R108 Resistor 47 63 mW 0603 R109 Resistor 47 63 mW 0603 R110 Resistor 680 63 mW 0603 R111 Resistor 680 63 mW 0603 R112 ESD protection diode RD6 2Z R113 Inductor EMC Components Part No ZCYS51R5 M3PAT T101 DC DC Step
104. X Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 9 158 Base Clock The netX100 500 uses an internal oscillator along with an external crystal for generating 25 MHz base clock 1 5V A netX 500 netX 100 osc vppc Y osc vss 2 OSC XTI OSC XTO GND 25 MHz 22 pF 22 pF GND GND Figure 4 netX100 500 System Oscillator Circuit More about base clock circuit can be found on gt Page 66 Chapter 4 3 Crystals Clock generators Real Time Clock The netX500 real time clock is not necessary for the basic circuit and has to be connected like the netX100 Pins to 1 5 V and 3 3 V Backup RAM 16 kByte KASV Spy L 3 3V RTC POK RTC XTI RTC XTO GND Figure 5 netX100 500 RTC Not Used in Basic Circuit More about real time clock circuit can be found on gt Page 66 Chapter 4 3 Crystals Clock generators netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 10 158 Reset The netX100 and netX500 provide two inputs for reset signals the Power On Reset PORn and the Reset In RSTINn While the use of the RSTINn is optional the Power On Reset is mandatory 3 3V To other parts such as Flash or JTAG connector 3 3V netX500 Q POR netX100 100nF GND MAX809SEUR
105. acks netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 62 158 4 Standard Circuits 4 1 RDY RUN Pins SYS LED netX100 and netX500 provide two dedicated pins that are used for up to two different purposes These pins are named RDY and RUN and operate as inputs after reset The first stage boot loader residing in the ROM of the netX chips checks the logic levels on these pins and enters certain boot modes depending on these levels After that the first stage loader configures these pins as outputs which are used to display status information Once a firmware is started it has complete control over these pins and their function may then be completely application specific Note In netX schematics the RDY and RUN pins are usually shown with a negating circle However the polarity of these pins when used as outputs depends on a register setting Besides the two bits that enable the output driver pin configured as output and set the level of the pin there is a third bit for each pin that determines the polarity active high or active low So it actually depends on these polarity bits if the output pins are active low or active high Further these polarity bits do not affect the pins when used as inputs RDY and RUN inputs are never inverted For historical reasons the active low signals RDY and RUN were already d
106. additional serial FLASH that can hold a second stage boot loader or non volatile user data Finally it may always simply be left unpopulated if really not used in the final product While an SPI Flash can be connected to three different chip select signals it must be connected to chip select 0 50 when the design is to be able to boot from this SPI Flash A standard component used by Hilscher is the AT45DB321 from ATMEL providing a capacity of 4 MB It is being connected as shown in the following schematics netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 75 158 AT45DB321 SPI MISO SPI MOSI SPI CLK SPI CSO netX 100 SPLGST netX 500 SPLCS2 GND GND PORn Figure 47 netX100 500 SPI Flash 4 6 1 2 MMC SD Card Instead of or in addition to an SPI Flash MMC SD cards can be connected to the netX even allowing to boot a firmware image stored on such a card To allow booting the MMC SD card must be connected to SPI chip select 1 51 Note Please note that the current ROM boot loader of the netX500 may have problems booting from certain MMC SD cards due to timing issues see also Errata sheet of netX500 In that case an additional SPI Flash holding the second stage loader must be connected to SPI CSO To detect insertion or removal of the MMC SD card during operatio
107. ader Yamaichi Electronics Part No FPS009 2405 0 Table 16 BOM MMC SD Card Circuit Bill of Materials microSD REF DES PART TYPE PART NAME K2 Microcontroller netX100 500 R201 Resistor 1 63 mW 0603 X201 microSD Card reader Amphenol Part No GTFP08121HEU Table 17 BOM microSD Circuit More about MMC SD Card circuits can be found on gt Page 75 chapter 4 6 1 2 MMC SD Card netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 47 158 netX100 500 Quick Start 2 10 UART lt gt RS232 vL L eL 6 8 Z 9 4 L UJOO I9UOS IU WA ZegTSUK gt LYN ae Loz rez aa 41 25 19405 ny 9596 JEYOS IH SEEN paup3 000 0122 00SXLSINONOIN z xolg 2M cioe 3001 001 21099 9019 019 pio 2810 orado i 98 c VH 5 BAY zou 6099 Bn E 1810 9090 wm ia todo 140150 2 qT13lHS A 9
108. als allow to connect four completely different devices as the configuration for each chip select area is done separately The netX also provides the possibility to boot from a memory device connected to the Extension Bus In that case the device must be connected to use the EXT CSOn chip select signal and the Extension Bus boot mode must be selected 4 7 2 1 Non multiplex Mode The following schematics show some examples for common setups in non multiplexed mode EXT A0 24 EXT 50 3 EXT BHEn EXT ALE EXT RDn EXT WRLn EXT WRHn EXT RDYn RD WR RDY WAIT EXT_INT EXT D0 7 Intel 8 Bit one write signal Figure 62 netX Extension Bus Type Interface Circuit 8Bit non Multiplex netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits EXT_INT INT 0 24 EXT A0 24 EXT 50 3 EXT CSO0 3n EXT_BHEn EXT_BHEn q AU ers 2 EXT_WRLn WR EXT_WRLn WRL EXT_WRHn EXT_WRHn WRH EXT_RDYn RDY WAIT EXT_RDYn ES RDY WAIT g EXT_D0 15 Intel 16 Bit one write signal Figure 63 netX Extension Bus _ 0 24 EXT CS0 3n EXT ALE RD WRn DS EXT RDn EXT WRLn EXT RDYn C RDY WAIT EXT INT INT EXT D0 15 Motorola 16 Bit one data strobe 94 158 EXT_INT INT EXT 00 15 Intel 16 Bit write
109. amic Capacitor 100 nF 25 V 0603 C103 Tantalum Capacitor 47 uF 10V K1 Microcontroller netX100 500 K101 Current Limited Power Texas Instruments Part No TPS2041 ADR Distribution Switch R101 Diode SN65220DBVT R102 Resistor 15 63 mW 0603 R103 Resistor 15 63 mW 0603 R104 Resistor 22 63 mW 0603 R105 Resistor 22 63 mW 0603 101 Connector USB A Connector Figure 35 BOM USB Host Mode Circuit More about USB circuits can be found on gt Page 98 chapter 4 9 USB netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 53 158 netX100 500 Quick Start 2 13 Embedded Trace Macrocell ETM vL L eL 6 8 Z 9 4 L Jo abed ig Woo JEYOs I wm ed TI3OOHOVW 5 Jezjoyy SEIEN gt 000 0122 00SXLAN O OIN Sun 194017 mr SALI Sip SALAN Oar Te air TIL 000 0122 00SXLAN O OIN ce xovd Wa TT 54 omud wa NSE Wa
110. applications The internal chip select generator which is enabled by a certain register setting compares the state of the host interface address lines A12 A19 to either an internal compare value stored in a register or to the state of the host interface SEL A12 19 signals It can be configured for each address line separately if the compare value is internal register bit or external SEL Using the external source SEL Axx for an address bit allows to either connect the SEL Axx signal to a jumper or switch that either set this signal high or low or to the corresponding address line e g SEL A12 to A12 SEL A13 to A13 etc which makes this address bit don t care for the chip select generator When using all 8 address Bits A12 19 for decoding which means that none of the SELA12 19 signals are connected to the corresponding address lines none of the address bits are don t care this results in an addressable DPM size of only 4k while the external base address of the netX DPM can be selected by applying the appropriate logic levels to the SEL A12 19 signals or by setting the appr Register value Combinations are of course also possible e g setting the most significant part of the base address by register value while the rest of the address is set by jumpers switches Starting from the 4k minimum the accessible DPM size can continually be doubled to the maximum of 64k standard size by connecting the appr nu
111. asic Circuit This chapter describes the important basic parts of a netX100 500 circuit to use Hilscher loadable firmware Some interfaces have a minimum circuit that have to be connected Therefore all interfaces circuit in this chapter shows the connection if they are unused The following chapter described this interface circuits RUN RDY Let s start with the circuit on RDY RUN pins These pins operate as input after reset The first stage boot loader of the netX100 500 checks the logic level and enters certain boot modes One important boot mode is the serial boot mode which will allow to re flash the firmware over USB or RS232 To get the netX100 500 in this boot mode the RDY pin has to be pulled down to GND over 1 27 resistor A push button or pin header between the resistor and the RDY pin make it possible to activate this boot mode when it is necessary For displaying system status a yellow and green dual LED is recommended to connect antiparallel over to 220 O resistors to RDY and RUN pin Two 15 pull up resistors connected to 3 3 V stabilize the RDY and RUN lines in resting level The following picture shows the basic RDY RUN circuit for netX100 500 3 3V A A x x Bootoptions wo Boot from the first Loader found in pe FLASH at Memory Controller serial EPROM at SPI I2C MMC Q S J2 J1 N N Serial boot mode o UARTO or USB RDY RUN yellow A V gr
112. ber Optic Transceivers netX Design In Guide 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 112 158 Software considerations netX100 500 With netX100 500 the level of PIOO7 must be set accordingly before accessing the desired transceiver When PIOO7 is set to Output mode and low level the analog switch will connect the netX SDA signal to the SDA signal of Transceiver 0 while setting 07 to Output mode and high level will let the switch connect the SDA signal to Transceiver 1 The PIO signals PIOOO to PIO31 are controlled by the PIO OUT and PIO OUT EN registers please refer to the netX100 500 Program Reference Guide for details Note Please note that the information above is only relevant when accessing the diagnostic interfaces of the Transceivers without using Hilscher firmware or stacks since the appropriate functionality and the diagnostic interface communication routines will be integrated in any appropriate software from Hilscher netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 113 158 4 10 3 Ethernet PHYs unused If the internal Ethernet PHYs are not used in a netX design the signal pins RXP RXN TXP TXN should simply be left open However all power supply pins must still be connected as well as the reference resistor as shown on the
113. ce Circuit Page 2 REF DES PART TYPE PART NAME C201 Ceramic Capacitor 100 nF 25 V 0603 C202 Ceramic Capacitor 47nF 50 V 0603 C203 Ceramic Capacitor 100 nF 25 V 0603 C204 Ceramic Capacitor 47nF 50 V 0603 C205 Ceramic Capacitor 10 uF 10 V 1206 C206 Ceramic Capacitor 100 uF 25 V 0603 C207 Ceramic Capacitor 100 nF 25 V 0603 K201 IC Switch NLAS44599DT R201 Diode ST Microelectronics BAR43S R202 Resistor 220 kQ 63 mW 0603 R203 Diode ST Microelectronics BAR43S R204 Resistor 1 63 mW 0603 R205 Diode ST Microelectronics BAR43S R206 Resistor 220 kQ 63 mW 0603 R207 Diode ST Microelectronics BAR43S R208 Resistor 1 63 mW 0603 R209 Resistor 100 63 mW 0603 R210 Resistor 100 63 mW 0603 R211 Inductor W rth Elektronik Part No 74279205 R212 Resistor 0 Q 250mW 1206 R213 Resistor 1 63 mW 0603 Table 22 BOM Touch Panel Circuit netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 58 158 More about LCD and touch panel circuits can be found on gt Page 134 chapter 4 15 LCD Interface gt Page 135 chapter 4 16 Touch Panel Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Resource Overview 59 158 3 Resource Overview The f
114. ce signals except the data lines such resistors will only make any sense on the data signals If no memory components are connected to the FLASH SRAM SDRAM interface of a netX100 500 design then pull ups or pull downs on the data lines will avoid possible cross currents and may hence reduce power consumption If only 16 Bit components are used this applies to the upper 16 data lines netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 81 158 4 6 2 SDRAM Most netX applications will require the use of SDRAM since most of the internal RAM is usually occupied by the standard 64 kB DPM and buffers leaving only little space for quite simple applications For certain slave applications an alternative to using SDRAM may be the use of parallel FLASH while the firmware is directly executed out of this FLASH instead of copying the firmware from FLASH to RAM and executing from there which is the standard situation SDRAM components connected to netX may be either 16 Bit or 32 Bit wide while two 16 Bit components may be paired to allow 32 Bit wide access Using two 8 Bit components paired for 16 Bit or four 8 Bit components 32 Bit is also possible When using SDRAM 32 Bit wide designs are generally recommended to make use of the full performance of the memory controller The use of one 32 Bit wide component instead of two 16 Bit or fo
115. chapter 4 10 2 Fiber Optic netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 33 158 2 3 AS Interface netX100 500 Quick Start 13 L eb 6 Z 9 S r z L Jo ULIOO J UOS LUWWA AOVAYAINI SV 96 99 91 9yensuled 20 90 HWE Jeu5s H Jezop sepen owen papa T 027 5090 7 sod cold a wer B I 26 n 9010 685 NS gt ie 4 wor dev 8 ELINT k 7 AS ZZ tep voq iSV MSOLOEWNNAV NOLVIOSI MYLONY L MEN Wanonsvusnud 2 m RU e zig Wanonsv a t 7 9 pi vorewx fp 1 zi ono t Di LO wx avo Sz 812 FII s 504 7 2014 M 1019 LOLX Nsv mn zaan NS FOONI wn z SH z Eh TNEISY a gt TNESV 49 6
116. connected as shown in the following figure Backup RAM 16 kByte 3 3V 1 5V La 3 3V RTC POK GND Figure 43 netX100 500 RTC Unused netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 69 158 4 4 Power On Reset and Reset In The netX100 and netX500 provide two inputs for reset signals the Power On Reset PORn and the Reset In RSTINn While the use of the RSTINn is optional the Power On Reset is mandatory Since the PORn input is equipped with a Schmitt trigger gate it could basically be connected to a capacitor other pin of cap connected to GND and a pull up resistor however it is strongly recommended to connect this signal to the output of a reset generator with voltage supervision to make sure the netX will not be released from reset until the power supplies have reached sufficient and stable levels Reset generator components are often available with either a push pull or an open drain output When the design will make use of the JTAG Interface of the netX an open drain type should be selected since this allows to simply connect the reset signal from the JTAG connector which is also specified as open drain to the output of the reset generator Of course a pull up resistor e g 10 k must be attached to the PORn signal when using open drain reset sources The optional RS
117. ctly meeting the requirements of this application However other analog switches or four single FETs may be used as well The purpose of the diodes e g BAR43S is to protect the netX analog inputs from possible damage caused by ESD as it lies in the nature of touch panels that they are being touched by human hands they are always subject to electrostatic discharge The RC filter comprising of the 1k resistor and the 47nF capacitor is just an example and may need to be adapted to the requirements of your design The resources AD converter channels I Os shown above must also be chosen when users want to run Windows CE images provided by Hilscher already containing an appropriate touch panel driver When other operating systems e g rcX are used users need to program their own driver and may then want to select other I O signals than the I Os as this would rule out the use of RTE protocols while the ADC channels may then also be freely selected Please note that the above schematics do not show the always necessary power supply of the AD converter See chapter 4 12 A D Converter for an example how to connect the ADC power supply pins The filtered 3 3 V voltage from the ADC power supply circuit should also be used for the 3 3 V shown in the schematics above netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 136 158 To
118. d 151 Tabl amp 42 Gryst l Reference ie n u Ts ntm tees Pea hk gam S aS ede 152 Table 43 Memory Component Reference SPI 153 Table 44 Memory Component Reference Parallel 153 Table 45 Memory Component Reference 154 netX Design In Guide 100 500 DOC081 106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Reference Section 156 158 6 4 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 List of Figures netX100 500 RDY RUN Basic enn en nnns 7 100 500 SPI Flash lu 8 netX100 500 Secure Memory Basic 8 netX100 500 System Oscillator 9 netX100 500 RTC Not Used in Basic 7 7 9 netX100 500 Reset Circuit odd Ad tee Lone Ele 10 netX100 500 USB DOWN Stream Port Device Mode 10 netX100 500 a en need date beetle 11 Figure 9 Unused ADC Basic 22 2 tne ede
119. de die denied eee denen 11 Figure 10 netX100 500 Connection of 8MB 5 12 Figure 11 netX100 500 Ethernet Not Used eite tide e dette tien edes ko Iure DL potu feud 13 Figure 12 Unused Host Interface nente 15 Figure 13 3 3 V Power Supply Standard 16 Figure 14 1 5 V Core Voltage Regulator enero cte nente nnd nie bed tn 16 15 netX100 500 22 esas Po Lg siut 17 Figure 16 netX100 500 Basic Circuit RDY RUN USB SEC MEM sse enne nennen 18 Figure 17 netX100 500 Basic Circuit SDRAM essen nen 19 Figure 18 netX100 500 Basic Circuit ADC Host Interface PHY RTC r 20 Figure 19 netX100 500 Basic Circuit Power 21 Figure 20 netX100 500 Basic Circuit Unused netX 22 Figure 21 Ethernet TP Dual Channel 25 Figure 22 Ethernet TP Single Channel 27 Figure 23 Fiber Optic Circuit on netX100 500 5 29 Figure 24 Fiber Optic Circuit on AFBR 5978Z 30 Fig re 25 AS Interface Cire it e
120. de the power dissipation by the area of the PCB Following there are two examples from the Hilscher netX product line one that is well within this power density limit and one that is at this limit Mini PCI Card with Ethernet Dimensions 44 6 mm x 59 8 mm Area 26 67 cm Power consumption 1 75 W heat sink 70 C Power Density 0 07 W cm Figure 100 CIFX 90 RE netlC with Ethernet Dimensions 21 0 mm x 42 0 mm Area 8 82 cm Power consumption 1 3 W heat sink 70 C Power Density 0 15 W cm Figure 101 NIC 50 RE netX Design In Guide 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 143 158 5 1 3 Rules of thumb Assuming the recommended 100 C junction temperature limit the following rules of thumb can be provided which are based on Hilscher s design experience with netX chips Designs with 45 x 60 mm area and heat sink usually work up to 70 C Designs with 45 x 60 mm area without heat sink usually work up to 55 C netX500 designs with 30 x 50 mm and heat sink usually work up to 70 C When using the internal PHYs the netX temperature rises by appr 15 C When using the heat sinks recommended by Hilscher the maximum temperature of the netX case decreases by approximately 15 C The above rules assume unimpeded convection of the PCB When a small closed cabinet is used the maximum ambient te
121. e between the contact pad and the netX is short as then the internal pull down resistor nominal 50 is sufficient to keep the TEST signal state inactive during normal operation The second condition refers to the state of some GPIO signals as shown in the following table The design must provide the possibility to set the required logic levels on these signals and the levels must remain in that state throughout the complete Boundary Scan test procedure netX100 500 Signal Pin number Signal State GPIO14 W13 Pulled high GPIO8 AA15 Pulled low or unconnected GPIO9 Y15 Pulled low or unconnected GPIO10 AA14 Pulled low or unconnected GPIO11 14 Pulled low or unconnected netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 73 158 Table 28 netX100 500 Boundary Scan MMIO GPIO Signals netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 74 158 4 6 External Memory Basically the netX100 and netX500 provide two different interfaces where firmware memory be connected to The serial SPI interface and the parallel FLASH SRAM interface that shares most of its pins with the SDRAM controller Note When the design is to be used with loadable firmware from Hilscher an
122. e flexible Important is only the resistor ratio that results in a voltage of 2 0 V VCC 1 3 V The LVTTL to LVPECL signal converters usually have thermal PADs to achieve proper heat dissipation Make sure to consider the thermal design notes in the datasheet of the appropriate devices The power supply 3 3 V for the Fiber optic Transceivers should be filtered according to the manufacturer s recommendation consult data sheet of transceiver Detailed schematics for netX100 500 Fiber Optic interfaces using the AFBR 5978Z QFBR 5978AZ transceivers with internal AC termination can be found on page 29 chapter 2 2 3 Fiber Optic with AFBR 5978Z netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 109 158 4 10 2 3 PCB Layout considerations The following drawings provide hints on proper placement of the Fiber Optic interface components Transceivers without internal termination Place level translators Termination resistors Termination resistors as close to netX pins Place as close to level Place as close to FX as possible translators as possible transceiver as possible Hi Speed single ended signals Keep traces Keep traces as Differential signal lines Keep traces as as short as possible short as possible Zdiff 100 Ohm short as
123. e safely before the power fails completely The following figure shows the complete circuit with some options 3 3V alternative circuit oS 3 3V netX 500 69A Backup RAM 16 kByte Schottky e g BAR43 Se RTC VDDIO RTC POK RTC VDDC LDO o NCP663 2 eie RTC XTI RTC XTO Backup time 3 days 8 GND GND b 0 32 768kHz alternative EE l A circuit Lithium Battery 22 pF 22 pF 25 mA Backup time gt 150 days GND GND Gb Figure 42 netX500 RTC Circuits The NCP663 regulator is just a proposal It has been selected due to its low quiescent current If the power fail Backup RAM feature is not used the can simply be connected to VDDIO 3 3 V The values for the capacitors and the serial resistor in the crystal circuit again depend on the selected crystal The shown values are suitable for the Hilscher standard netX RTC crystal which is a Q0 032768 JTX520 12 5 20T1 LF manufactured by Jauch Quartz GmbH netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 68 158 4 3 2 2 Designs without RTC or with netX100 When making designs with the netX500 that do not make use of the RTC feature or when making designs with netX100 the RTC pins must be
124. ection with chip select 1 on netX100 500 V 17 pin lt m 4 x HN j o Bg 2 g 9 95 e ts gt ds 2 IN 9 z E gt seag _1 1499904 8858882 88 ed a s oo g eS Teer A 28 N 58 gi E 9 x s 9 Q o a A D o 73 S E 3 a 4 2 gt el 8 8 x d 75 ol 55 zt P 55 8 35588588 8588588588255552 as g BERBER 2 555588555522 2 222 8 298 32 751 1 NF 189 x Pv 5 ES EE X 5 5 gt 2g D e E i 84 5 4 JIHDE 2 12 16 a8 E lt m u o Figure 31 netX100 500 MMC SD Card SPI Circuit netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start Bill of Materials MMC SD Card 46 158 REF DES PART TYPE PART NAME K1 Microcontroller netX100 500 R101 Resistor 1 63 mW 0603 X101 MMC SD Card re
125. ed as shown in the following schematics which are based on the reference schematics from the CompoNet specification The purpose of the AND gate in the RX signal is simply to convert the 5V signaling voltage from the AD51 025 to 3 3V level More detailed schematics pin numbers can be found in the in the Reference Section in Chapter 5 5V AD51 025 100 MMZ1608B301C XW7D PB4 R 70 4 3E 55 u BDH 2 MK be mm BDL MMZ1608B301C 3 E 10 10 2 ____ mm BS ACM3225 102 2P RD6 2SB1 M RD6 2SB1N 220p 220p RD6 2SB1 N RD6 2SB1 Y GND Figure 86 Basic Circuit for netX CompoNet Interface netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 4 11 5 DeviceNet Interface 124 158 A DeviceNet interface can be implemented according to the following simplified schematics More detailed schematics can be found in the in the Reference Section in Chapter 5 3 3V A HCPLO601 VCC PCA82C251 L VCC 4 amp TX H EH DN_TX RX L CAN L GND REF RS GND PESD1CAN HCPLOGOL VCC DN_RX XMi_RX 4 amp XV
126. een d J 21 Dual Port Memory RUN p n boot mode netX100 500 2 e 2 Extension Bus R2b SI rib boot mode Figure 1 netX100 500 RDY RUN Basic Circuit More about RDY RUN circuit can be found on gt Page 62 chapter 4 1 RDY RUN Pins SYS LED netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 8 158 SPI Flash Memory The Hilscher loadable firmware is always stored in flash memory which is connected via SPI with the netX100 500 W17 AT45DB321 W16 W18 V18 V17 netX 100 571 551 netX 500 SPI MISO SPI MOSI SPI CLK SPI CSO GND GND PORn Figure 2 netX100 500 SPI Flash More about SPI Flash Memory MMC SD Card circuit can be found on Page 45 chapter 2 9 MMC SD Card SPI Circuit Page 61 chapter 3 3 Memory Requirements of Hilscher Stacks Page 74 chapter 4 6 1 1 SPI FLASH Page 75 chapter 4 6 1 2 MMC SD Card Page 76 chapter 4 6 1 3 Parallel FLASH Secure EEPROM The Secure EEPROM connected via with netX100 500 hold licensing information address and other information 3 3 V AT88SC0104C W15 W14 12C_SCL I2C SDA netX100 500 GND Figure 3 netX100 500 Secure Memory Basic Circuit More about Secure EEPROM and circuit can be found on Page 65 chapter 4 2 Secure EEPROM net
127. efined for the EC1 based devices the RDY and RUN pins are however always shown as active low For displaying system status a system LED dual LED or two single LEDs is defined LED Color Description RDY Yellow netX with operating system is running RUN Green User application is running without errors Table 26 RDY RUN LED Status Basically designers could use LEDs with other colors however it is recommended to use the Hilscher definition especially when interpreting blink codes for troubleshooting it is helpful if customer and support see the same colors The most flexible circuit for netX100 500 designs is shown in the following schematic It allows setting all possible boot modes of the netX100 500 and can usually be found on evaluation hardware netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 63 158 3 3V A A x x Bootoptions LO R2a 0 Ria J2 n og Boot from the first Loader found in W20 e FLASH at Memory Controller D serial EPROM at SPI I2C MMC S S J2 J1 n Serial boot mode o UARTO or USB RDY RUN yellow A V green m 1 W21 Dual Port Memory RUN gt boot mode 100 500 J2 1 J1 i 2 Extension Bus rab IN S Rib ala GND Figure 39 netX100 netX500 RDY RUN Circuit FAQ Frequency Answered Q
128. elivers 3A at 3 3V is shown in the following schematic D3 05 400nF FDC5612 6 wel 4 R103 52 C107 f t 24 2 105 PMEG4005 2 1 R105 3 10uH 2 1 C106 0603 400nF 1 R106 2 9V 24V 1 En R 0 018 43V3 A 8 47k 2 8 C108 C109 102 Cree 1210 40uF 1210 40uF 1210 40uF 2 S 7 2 2 2 2 2 Figure 98 netX 3V3 Supply netX Design In Guide netX 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 140 158 This circuit provides high efficiency over the complete input voltage range due to the synchronous switching consumes appr 320 mm2 board space and costs appr 3 50 4 18 4 Voltage Regulator 5 V The same circuit with 6 8kQ for R101 and 1 3kQ for R102 delivers 5V 1 C100 1 C101 g GND1 Synchronous Buck Controller VOUT gt 1 C104 0805 400nF 2 42 37 R103 SZ 6 2 ax C105 d 100nF 4005 5 C106 1 0603 100nF 2 FB 2 GND 1210 40uF 1210 10uF 1210 40uF 2 2 2 0603 9 MIC2198 1 TEPDOWN MIC219 R101 1 2 8 6 8k 8 1 R102 1 2
129. esign In Guide 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 108 158 Note The termination resistors shall be placed as close as possible to the end of the signal lines connected with short traces no stubs Due to the large number of resistors this can hardly be accomplished with standard 0603 resistors A special Resistor array containing 8 resistor pairs 127 pull up 82 5 pull down with common GND and VCC connection in a small BGA package is available from CTS type RT1250B7 that allows to fulfill this requirement The BIAS resistors on the TXD signals circuit for internally AC terminated Transceivers are to be placed close to the beginning of the signal line which means close to the LVTTI to LVPECL level translators Please also see the following chapter for hints on component placement The 127 0 82 5 Thevenin termination results a bias voltage of 2 0 V and a signal termination of appr 50 Q Alternatively 130 0 82 can be used The recommended value for resistors R6 R7 R14 and R15 in the circuit for internally AC terminated Transceivers depends on the LVTTL to LVPECL level translators that are used 195 is the recommended value when using devices from MICREL When using other components please consult the device datasheet and appropriate Manufacturers application notes if available The values for R24 and R25 ar
130. exist PlOs 0 7 usually drive Fieldbus and RT Ethernet status LEDs in standard applications PIO 0 30 The PIO 0 30 pins are equipped with 50 pull up resistors with a minimum resistor value of 20 6 and maximum resistor value of 116 4 The maximum input output current is PIO 32 84 The PIO 32 84 pins are not equipped with pull up or pull down resistors The maximum input output current is 18 mA netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 138 158 4 18 Power Supply netX100 and netX500 both require an I O voltage supply of 3 3 V and a core voltage supply of 1 5 V For worst case scenarios the 3 3 V supply should be able to source a current of 400mA for the netX part netX memory etc of the circuit When the core voltage regulator is also supplied by the 3 3 V rail the max current of course increases accordingly The core supply should be able to deliver 1 A For certain applications e g applications that do not use the Ethernet ports lower max currents may be sufficient however in that case the corresponding Technical Data Reference Manual of the netX chip should be considered for details about power consumption It is recommended to implement a separate core voltage supply for the netX even if a 1 5V supply is required by other parts of the system e g FPGA The output vol
131. fied resistor values are directly taken from the specs of the internal PHY Using out of spec resistor values will result in an out of spec Ethernet Interface that can not be guaranteed to work properly under all conditions netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 105 158 4 10 2 Fiber Optic For 100BASE FX Ethernet communication the netX requires external optical transceivers Since these transceivers usually work with LVPECL Low Voltage Positive Emitter Coupled Logic levels appropriate signal converters must further be connected between netX and transceivers The signal converters should be placed as close as possible to the corresponding netX pins and the traces of the differential signal lines between buffers and transceivers should provide an impedance of 50 100 differential impedance The signal lines are to be terminated with Thevenin termination as shown in the following schematics 4 10 2 1 Transceivers without internal termination R1 1 5V 1000 100 MHz 200 PHY_VDDCAP H17 C1 C2 PHYO VDDCART 20 PHY1_VDDCART T 100n 10u R2 3 3V nod 10000 100 MHz 200 PHY VDDIOAT PHY_VDDIOAC _ L c4 3 3V 100 T 10 T PHY_VSSAT PHY_VSSACP PHYO VSSAR VSSAT1 PHYO VSSAT2 D19 XMO TX PHY1 VSSAR PHY1_VSSAT1 F1
132. firmware necessarily assumes compliance with Hilscher standard assignments Note Designers should be aware that not all components supported by netX hardware e g parallel FLASH are necessarily also supported by existing software firmware or tools from Hilscher Hence it is strongly recommended to consult the feature table in the following chapter to make sure that all desired hardware features of the planned design are eventually supported by the firmware that will run on the design This applies not only but particularly to customers planning to use loadable firmware from Hilscher instead of doing own firmware development Resources that are currently not supported by loadable Firmware or where no drivers code are yet available may still already be supported by existing Hilscher devices e g Gateways It is hence recommended to check with Hilscher Sales if there is already an existing solution for your problem Further Hilscher offers several custom design services for netX hard and software as well as manufacturing services providing an easy way to your custom product For detailed information and quotes please contact Hilscher Sales Hilscher also offers a schematic review service allowing your hardware design to be checked by netX experienced hardware engineers Hilscher Sales will be happy to provide an individual quote for this service after receiving your schematics PDF format Note Before starting a design it is stro
133. g 2 OC NIN m TV WS wy e SN OC WAN Ob DEM 1 ory Wan OQ NIN 8 IV NAN OF Ny WIN 7 OV WS lev WEM A WERT ANN WIN Y OV WIN 9L VEN WIN pei Ov NIN SV WEM Ov NIN vw Wan E E IV WaN CO WE ov W3N s 3 oed Waw ea WaN ra Haan zi yo LIWN 3001 9050 9 19 azd Ww i8 9 red wan 9020 H Fat 36 zanan 1 y Ww i um 9 ene Pa ea aw ano amp 6v ua sv 1 leid wan 98 N Em ov E i w SN oy m v At Wan 2020 a a 2 Jord wan SL Ww 60 a ov sq Wan LORS Want E ene td SQ W3W pa Wan A ec Waw P za waw INVYS GINS ton 3H loa wan Iez oolv Waw vL eL 9 Hilscher 2008 2012 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Figure 17 netX100 500 Basic Circuit SDRAM netX Design In Guide 100 500 20 158 netX100 500 Quick Start 13 L 4 6 8 Z 9 6 v L Jo bed VJOO ISUOS WW bed OLY AHd SDVAYALNI LSOH OGV poised
134. g position 0 of the rotary encoder There are two additional optional input signals named MPO and 1 that be used for initiating the storage of the current position or system time to up to four different capture registers As all encoder signal inputs expect single ended digital signals with 3 3 V level only appropriate encoders may be connected directly to the inputs When using encoders with differential outputs and or 5V signaling levels appropriate line receivers and or level shifters must be connected between encoder and The following schematics show an example only one encoder and only one signal shown in detail of a possible circuit 3 3V Vcc capacitors are not 5V 5V 5V shown in this schematic A Rotary Encoder An 5 0 1uF PIOO ENCO A 1 B 74LCX04 PIO1 ENCO B PIO2 ENCO GND PIO3 ENC1 A PIO4 ENC1 B PIO5 ENC1 PIO6 MPO PIO7 ENC MP1 Application specific use netX 100 500 Figure 93 Encoder Circuit Example netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 133 158 Note Designers should note that the shown schematics are just an example and that the best circuit for their application may be different Unless designers have appropriate experience with encoder circ
135. hannel integrated jack that also includes the PE capacitor C3a C3b and is available from Pulse Engineering ERNI and Trxcom J8064D628AN 203313 TRJ26204B Pulse Engineering ERNI Trxcom netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 104 158 If only one Ethernet port is required this port should be connected according to the following schematic R1 1000 100 MHz 200 mA 1 5 VDDCAP t PHYO VbDCART 417 ei d 62 PHY1 VDDCART 220 100 10 R2 A33V 1000 100 MHz 200 mA 4 3 PHY_VDDIOAT VDDIOAC F18 C3 100 7 10 PHY_VSSAT PHY_VSSACP PHY0_VSSAR PHY0_VSSAT1 PHY0_VSSAT2 PHY1_VSSAR 55 PHY1_VSSAT1 2 2 ealxle i PHY1 VSSAT2 RJ45 PHYO TXP gt 2 TXN PHY0_TXN d R5 HEH R6 50 R12 10 PHY0_RXP r RXN PHY0_RXN C13 _ 10nF 2kV bd PHY1_TXP Jr 015 1n 2kV PHY1_TXN SHE PE PHY1 RXP PHY1 RXN PHY EXTRES PHY ATP R23 12 4k netX100 500 GND Figure 73 netX Single Channel Ethernet Circuit Twisted Pair We do not stock 12 4kQ resistors and or 500 resistors we use 12 49 0 51 instead The speci
136. he ETM and the display connector should be located close to each other to avoid long stubs which may cause signal reflections going from the connector in use to the one not in use The ETM connector is to be wired to the netX according to the following table Conn ARM Signals netX Signals Conn ARM Signals netX Signals Pin Pin 1 N C 2 N C 3 N C 4 N C 5 GND VSS 6 TRACECLK ETM_TCLK 7 DBGRQ ETM DRQ 8 DBGACK ETM DACK 9 nSRST Not used 10 EXTTRIG 11 TDO JT TDO 12 VTRef VCCIO 13 RTCK Not used 14 VCC VCCIO 15 TCK JT_TCLK 16 TRACEPKTI7 07 17 5 JT_TMS 18 TRACEPKT 6 TPKTOG 19 TDI JT TDI 20 TRACEPKT 5 05 21 nTRST JT_TRSTn 22 TRACEPKT 4 ETM_TPKT04 23 TRACEPKT 15 ETM_TPKT15 24 TRACEPKT 3 25 TRACEPKT 14 ETM_TPKT14 26 TRACEPKT 2 02 27 TRACEPKT 13 ETM_TPKT13 28 TRACEPKT 1 ETM TPKTO01 29 TRACEPKT 12 ETM_TPKT12 30 TRACEPKT 0 ETM TPKTOO 31 TRACEPKT 11 ETM_TPKT11 32 TRACESYNC ETM_TSYNC 33 TRACEPKT 10 ETM_TPKT10 34 PIPESTAT 2 ETM PSTAT2 35 TRACEPKTI9 ETM_TPKTO9 36 PIPESTAT 1 ETM_PSTAT1 37 TRACEPKT 8 ETM_TPKTO8 38 ETM_PSTATO Table 27 ETM Signals Note The AMP Mictor connector has four additional through hole pins in the center which have to be grounded for proper operation of the trace port For the PCB layout it is recommended to have the line
137. he use of an appropriate ASi ASIC following simplified example schematic shows the physical layer circuit for a netX AS interface still using the discontinued 251 chip which is replaced by the ASI4U More detailed schematics can be found in the Reference Section in Chapter 5 For details consult A2SI Master Mode A2SI data sheet 3 3V 5V A ADuM1301 VDD VDD 10k J 2 XMi_RX Asi Powerfail 100 GND Figure 83 Basic Circuit for netX AS Interface netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 121 158 4 11 2 CANopen Interface A CANopen interface can be implemented as shown in the following schematics More detailed schematics pin numbers can be found in the in the Reference Section in Chapter 5 3 3V HCPL0601 VCC 8 PCAB2C251 _ ______ CO_TX NT CAN 220 RX L CAN_L REF i SUB D CO_RX 9 390 13 e 4 I DGND dn l nn GND Figure 84 Basic Circuit of netX CANopen Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10
138. hematic ADCO AA5 ADCO_INO ADCO IN1 ADCO_IN1 2 WS ADCO_IN2 ADC0_IN3 V mm ADC0_IN3 3 3V ADC0_vppio 6 Em Ferrit 1000 OHM 100 MHz 200 mA at 4 gt IO ADCO_VREFP 6 4 gt ADC_VREFP Filtered supply for additional Ze analog circuits ADCO VREFM 444 UMP ADC_AGND ADC0 VSS Y4 Optional filter T for separate analog ground GND apc1_INo IN1 IN2 V4 ADC1_IN3 95 3 3V ADC1_vppio Apc1_vREFp AAS ADC1_VREFM me netX100 500 Figure 90 ADC Circuit One Channel Used netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 129 158 If the ADCs are nit used they still need to be powered as shown in the following schematic 3 3V AA YS W5 V5 ADCO INO ADCO IN1 ADCO IN2 ADCO IN3 ADCO 6 ADCO_VREFP V6 ADCO VREFM ADCO vss 4 Y3 W3 V4 05 ADC1 INO ADC1 IN1 ADC1 IN2 ADC1 IN3 ADC1 vppio vnErP AA3 vREFM ADC4 vss 4 GND netX100 500 Figure 91 ADC Circuit ADCs Unused netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 130 158 4 13 PWM Interface The netX100 500 is equipped with two inde
139. hich are the standard resources for RTE and field bus status LEDs In that case other I O resources must be used for the LEDs The external circuit for PWM applications strongly depends on the application hence examples are not provided here The appropriate pins for the signals of the PWM units which are PWMOE U Un V Vn W Wn RSV for Resolver and FAlLn for unit PWMO and which are PWM1 A U Un V Vn W Wn RSV and FAILn for unit PWM1 pinning option A and PWM1B Un V Vn W Wn RSV and FAlLn for pinning option B can be found in the corresponding pin table in Chapter 7 6 Pin Table sorted by signals of the netX100 500 Technical Data Reference Guide Note The following popular pitfall with netX PWM designs must be avoided Both PWM units are equipped with an active low Failure Signal input that immediately stops the corresponding unit and sets all outputs low when active These signals are PWMOE FAlLn pin P17 shared w PIOO6 for PWM unit and PWM1 A FAlLn pin N18 shared with XMO 101 for PWM unit 1 pinning option A or PWM1B_FAILn pin T20 shared with XM2 ECLK for pinning option B Since all these pins are equipped with internal pull down resistors the failure signals are always active when unconnected Hence on any netX PWM design that does not make use of a failure signal the appropriate signal must be pulled high by an external pull up resistor otherwise the corresponding PWM unit will not operate Please also note
140. ilscher 2008 2012 General Design Considerations 147 158 5 2 5 Clock Circuits Any oscillator pins on the netX chips are located on outer BGA ball rings allowing to keep the traces to a quartz crystal as short as possible The following picture shows a recommendation for placing and routing the oscillator components netX Figure 106 Oscillator Circuit with Ground Shield 5 2 6 Ethernet Interface When routing the two signal pairs TXP TXN RXP RXN of each Ethernet channel some special requirements need to be considered Each signal pair must be routed as a separate pair of traces which should be kept as short as possible place magnetics and termination components as close to the netX as possible Traces of a pair must be routed adjacent to each other with constant spacing and equal length The distance between signal pairs should be at least 5 times the spacing of the pair traces Traces must be impedance controlled maintaining a differential impedance of 100 Ohm Minimize layer changes If a layer change is inevitable change layer with both traces at equal distance from start of trace and avoid changing to layers that use a different reference plane Avoid connectors in the signal traces the traces should begin and end on the same PCB If a connector is inevitable use impedance controlled connectors to minimize any discontinuities in trace impedance Area where Ethernet signals are routed sho
141. ist of Resources 37 P rty OS c stessi Re iem n uu ein 60 Table 25 FLASH Sizes for Hilscher Stacks ull een e an 61 Table 26 RDY RUN EED era as uuu h 62 Table 27 ETM Sone andi desee ede Debes EIE See a SEES v 71 Table 28 netX100 500 Boundary Scan MMIO GPIO nennen nem nennen 73 Table 29 MMC SD Card Insertion Signal 75 Table 30 Function Table of 16 Bit Decode 85 Table 31 netX DPM Intel Type Interface Circuits 2 rettet tentent ens 86 Table 32 Additional USB Signals nee a ee 100 Table 33 Ethernet Circuit Component 103 Table 34 Fiber Optic Ethernet Circuit Component Specification 2 106 Table 35 Fiber Optic Ethernet Circuit Component Specification 107 Table 36 Status LEDs for Ethernet POMS oriire iinne Aa Eaa ia 114 Table 37 Additional RTE Sync Signals 100 500 115 Table 38 Status LEDs for Real Time Ethernet Applications 116 Table 39 Status LEDs for Fieldbus Ports nn He 126 Table 40 Fieldbus Status LED Colors nu ae nenne nennen 126 Table 41 Dimension of Printed Circuit Boar
142. l info hilscher it Support Phone 39 02 25007068 E Mail it support hilscher com netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public 158 158 Japan Hilscher Japan KK Tokyo 160 0022 Phone 81 0 3 5362 0521 E Mail info hilscher jp Support Phone 81 0 3 5362 0521 E Mail jp support hilscher com Korea Hilscher Korea Inc Suwon Gyeonggi 443 734 Phone 82 0 31 695 5515 E Mail info hilscher kr Switzerland Hilscher Swiss GmbH 4500 Solothurn Phone 41 0 32 623 6633 E Mail info hilscher ch Support Phone 49 0 6190 9907 99 E Mail ch support hilscher com USA Hilscher North America Inc Lisle IL 60532 Phone 1 630 505 5301 E Mail info hilscher us Support Phone 1 630 505 5301 E Mail us support hilscher com Hilscher 2008 2012
143. l I O signals for these purposes which are generally connected through the 0 and 101 pins pins The following table lists the different protocols and the additional signals RTE protocol Master Slave signal Pin Function Type Remarks SERCOS III Device 100 019 Out Configurable XM3 IO1 U18 DIV CLK Out Configurable Master 100 019 CYC In Out Configurable CON_CLK 101 U18 DIV_CLK EtherCAT Slave XM3 100 019 Sync 0 Out XM3 IO1 U18 Sync 1 Out PROFINET IRT Controller Device 100 U19 IO Output Out Trigger for Outputs valid also used for certification start of red phase 101 U18 IO_Input Out Trigger for sample inputs Ethernet Controlled Node XM3_IO0 U19 SoC Out configurable Powerlink Start of Cycle received event XM3_IO1 U18 Table 37 Additional RTE Sync Signals netX100 500 netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 4 10 5 2 In Addition to the standard Ethernet Status LEDs Link Status and Activity up to four further LEDs two dual LEDs have been defined by the different RTE Protocols The signals used for driving these LEDs PIOO 3 are identical with the signals used for Field bus status LEDs on XMACO and see also chapter 2 1 3 for pinning details
144. le 25 Ethernet Ports 100 500 RTE protocols Standard Ethernet and RTE see separate list protocols see separate list Host Interface 100 500 DPM interface DPM Extension Bus PCI Real Time Clock 500 not supported no driver available Gateway Functionality 100 500 not supported user programmable 2 Channel Fieldbus 100 500 not supported supported AD Converter 100 500 not supported no driver available PWM Interface 100 500 not supported no driver available Encoder Interface 100 500 not supported no driver available Table 23 List of Resources rcX OS netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Resource Overview 3 2 Third Party Operating Systems 60 158 Resource Functiona netX Linux BSP CE BSP VxWorks BSP lity USB Device 100 500 no driver available supported no driver available USB Host 100 500 no driver available supported max 7 pipes no driver available UARTO 100 500 required by uboot Debug or Standard port supported remote console or required by eboot standard serial port UART1 100 500 supported supported supported UART2 100 500 supported supported supported SDRAM 100 500 required required required min 32 MB with LCD min 32 MB with LCD min 8 MB rec 16 MB Secure Memory 100 500 Ethernet MAC Addresses supported Ethernet MAC Addresses and user zone SPI Flash 100 500 no
145. long with Windows CE images but may however basically be accessed by any operating system see chapter 3 2 for information on current driver support In host mode the design must supply the 5 V bus voltage for the USB port The most simple circuit would directly deliver the 5 V to the corresponding pin of the USB receptacle however the use of a suitable power switch is recommended as shown in the following example schematics Such a power switch allows to detect short circuit or over current conditions and turn off the USB Bus voltage in such a case It also provides the possibility to disconnect and reconnect devices by turning off and on the bus voltage Two additional signals for connecting such a power switch to the netX have been defined Function Pin name and number USB power switching GPIO 12 AA3 USB over current detection GPIO 13 Y13 Table 32 Additional USB Signals GPIO12 has also been assigned another standard functionality which however is not a conflict since the other assignment refers to the USB device mode which can only be used alternatively to the Host mode netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 101 158 The USB Bus power switching signal VUSB ONn is used to turn on and off the USB Bus power When used this active low signal is to be connected to the enable input of a power swi
146. make the circuit and the netX work as a touch panel controller appropriate driver software must perform the following tasks Starting in idle mode the two I O signals 100 and 101 must be held low and the analog value on the two ADC inputs must be captured periodically In this state all switches are turned off and due to the 200k pull up and pull down resistors the value on the YU input will be around maximum while the value on the XR input will be around 0 as long as the panel is not being touched In this case the application is to remain in idle mode If the XR input value is significantly higher than 0 and the YU input value significantly lower than max it can be assumed that the panel is currently being touched Now the TP XON must be set to high level which turns on the two upper switches connecting XR to 3 3 V and XL to GND At the position being touched the conducting XL XR and YL YU layers of the panel contact each other building a voltage divider with the voltage at the touch point being proportional to the X position of the touched point After a panel specific settling time this voltage and hence the corresponding position can be measured at the YU input When the X position has been captured the TP XON I O XM3 100 must be set to low level again while the TP YON I O XM3 101 must set to high level This turns on the two lower switches connecting YU to 3 3 V and YL to GND Now again after a certain settling
147. mation mbH does not guarantee its suitability for any purpose not confirmed in writing It cannot be guaranteed that the hardware and software will meet your requirements that the use of the software operates without interruption and that the software is free of errors No guarantee is made regarding infringements violations of patents rights of ownership or the freedom from interference by third parties No additional guarantees or assurances are made regarding marketability freedom of defect of title integration or usability for certain purposes unless they are required in accordance with the law and cannot be limited Warranty claims are limited to the right to claim rectification 1 2 5 Export Regulation The delivered product including the technical data is subject to export or import laws as well as the associated regulations of different counters in particular those of Germany and the USA The software may not be exported to countries where this is prohibited by the United States Export Administration Act and its additional provisions You are obligated to comply with the regulations at your personal responsibility We wish to inform you that you may require permission from state authorities to export re export or import the product netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 7 158 2 netX100 500 Quick Start 2 1 B
148. mber of SEL Axx signals to the corresponding address lines and setting the corresponding compare value source to external Note When reducing the addressable DPM size please be aware of some drawbacks that come with smaller netX DPMs Some system registers which are hard mapped to the upper end of the 64k area can not be reached with a reduced DPM Further loadable firmware provided by Hilscher usually presumes that the full 64k area is available to the host and does hence not support designs with reduced DPM size It is strongly recommended that hardware designers planning to reduce the addressable DPM size consult their software department to make sure this will not collide with the final application The following schematics show some examples of how to connect the address and SEL Axx lines netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 91 158 A0 19 DPM AO0 19 A12 15 DPM SELA12 15 DPM_SELA16 DPM_SELA17 DPM_SELA18 DPM_SELA19 N CY 64k addressable 0000 Host 0000 A0 19 DPM AO0 19 DPM SELA12 14 DPM_SELA15 DPM_SELA16 DPM_SELA17 DPM_SELA18 DPM_SELA19 32k addressable Host 0000 DPM AO0 19 A0 19 DPM SELA12 DPM SELA13 DPM
149. mperature inside the cabinet must be decreased by approximately 15 C When the power density is higher than 0 15 W cm it will be critical to make a netX design which operates up to 70 C Avoid placing semiconductor components on the bottom side of the PCB within the chip area Resistors or ceramic capacitors may be placed under the netX if they allow operating temperatures up to 100 C X7R ceramic Temperature tests with a netX500 Evaluation board have shown that it is possible to build designs for extended temperature range up to 85 C with heat sink resulting in a netX case temperature of 103 C see document nxdkn en Rev3 Waerme pdf available on the Hilscher website netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 144 158 5 2 EMC behavior Designing for EMC is a quite complex issue already filling countless pages of again countless books and papers and it is not the intention of this document to further enrich this variety of publications however a few basic guidelines hints can be presented that may be useful for the PCB designer routing a netX design 5 2 1 Layer Stack Though depending on the complexity of the design netX designs using 4 layer PCBs are possible the use of a 6 Layer board 4 signal layers one power and one ground plane layer is recommended 4 signal layers provide
150. n an insertion signal has been defined that must be pulled high when an MMC SD card is in the socket Function Pin name and number MMC SD insert GPIO 15 V13 Table 29 MMC SD Card Insertion Signal 3 3V 1 V13 MMC_INS 10k W17 SPI CS1 C 1 Mosi 16 C 2 3 sPi 18 Eg 3 cso 6 18 e 4 MMC SD v17 t 100 V16 6 netX 500 7 8 70 1 uF Figure 48 netx100 500 MMC SD Card netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 76 158 Some SD Cards disturbs the SPI data transmission from FLASH A solution is to disconnect the SD Card from MOSI and MISO lines with switchable bus driver when SD Card chip select SPI_CS1 is high The Figure 49 shows a solution 3V3 K102 VCC 1 5 C101 0603 400nF 3 W17 sPLMSO Hov 2 Ee SPI CS1 K103 5 K101 A lt Tew GPIO1 0603 100nF 65 3 SD MMC Card GPIO4 LMO J GND 1 552 ie JUS X101 N GPIO6 GPIO7 GND GPIO8 74LVC1G125GW DO GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 IRQJGPIO15 MICRO NETX500 2210 000 0603 400nF POR AT45DB321C CNU SPLFLASH Figure 49 Solution if SD Card Disturbs SPI Data Transmission from FLASH GND 4 6 1 3 Parallel FLASH For large firmware images that come
151. nF 25 V 0603 C203 Ceramic Capacitor 100 nF 25 V 0603 C204 Ceramic Capacitor 100 nF 25 V 0603 C205 Ceramic Capacitor 100 nF 25 V 0603 Table 2 BOM Basic Circuit Page 2 netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 netX100 500 Quick Start 24 158 Page 3 REF DES PART Type PART NAME C301 Ceramic Capacitor 100 nF 25 V 0603 C302 Ceramic Capacitor 100 nF 25 V 0603 R301 Resistor 12 4 63 mW 0603 R302 Resistor 10 63 mW 0603 Table 3 BOM Basic Circuit Page 3 Page 4 REF DES PART Type PART NAME C401 Ceramic Capacitor 10 uF 50 V 1210 C402 Ceramic Capacitor 10 uF 50 V 1210 C403 Ceramic Capacitor 10 uF 50 V 1210 C404 Ceramic Capacitor 2 2nF 50 V 0603 C405 Ceramic Capacitor 100 nF 50 V 0805 C406 Ceramic Capacitor 10 uF 10 V 0805 C407 Ceramic Capacitor 100 nF 50 V 0805 C408 Ceramic Capacitor 100 nF 25 V 0603 C409 Ceramic Capacitor 22 uF 6 3 V 0805 C410 Ceramic Capacitor 22 uF 6 3 V 0805 C411 Ceramic Capacitor 22 uF 6 3 V 0805 C412 Ceramic Capacitor 100 nF 25 V 0603 C413 Ceramic Capacitor 100 nF 25 V 0603 C414 Ceramic Capacitor 10 uF 10 V 0805 C415 Ceramic Capacitor 100 nF 25 V 0603 C416 Ceramic Capacitor 100 nF 25 V 0603 C417 Ceramic Capacitor 100 nF 25 V 0603 C418 Ceramic Capacitor 10 uF 10
152. nally wired to three power supply pins VDDH that must either be connected to 3 3 V standard designs or 5 V host processor uses 5 V signaling voltage Note The output level of the netX host interface will however always be 3 3 V and NO other signals of the netX100 500 are 5 V tolerant Since the netX100 500 host interface pins are not equipped with internal pull up or pull down resistors all signals of the HIF are floating after reset As floating signals should generally be avoided designers should either apply external pull up or pull down resistors or ensure that the firmware configures all unused pins as I O Outputs and drives them high or low i 3 3V netX 500 netX 100 netX 500 netX 100 3 3V signalling environment Figure 54 netX100 500 VDDH Pins 5V signalling environment netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 85 158 4 7 1 DPM Mode In DPM mode the host interface can be controlled by separate Read RDn and Write WRn WRLn WRHn signals Intel mode or by a combined R WRn signal indicating the direction of the access and Byte strobe signals Motorola mode In Intel mode either a single Write signal can be used WRLn or two Write signals WRLn WRHn for writing to the low Byte WRLn and high Byte WRHn separately 4 7 1 1 Address Bus In case of a 16 Bit host systems with
153. nd flawlessness of the software for all usage conditions and cases and for the results produced when utilized by the user Liability for any damages that may result from the use of the hardware or software or related documents is limited to cases of intent or grossly negligent violation of significant contractual obligations Indemnity claims for the violation of significant contractual obligations are limited to damages that are foreseeable and typical for this type of contract It is strictly prohibited to use the software in the following areas netX Design In Guide 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Introduction 6 158 for military purposes or in weapon systems for the design construction maintenance or operation of nuclear facilities in air traffic control systems air traffic or air traffic communication systems in life support systems in systems in which failures in the software could lead to personal injury or injuries leading to death We inform you that the software was not developed for use in dangerous environments requiring fail proof control mechanisms Use of the software in such an environment occurs at your own risk No liability is assumed for damages or losses due to unauthorized use 1 2 4 Warranty Although the hardware and software was developed with utmost care and tested intensively Hilscher Gesellschaft fur Systemauto
154. nesebeceneses 26 Table 6 BOM Ethernet TP Single Channel ul u u u a aaa 28 Table 7 BOM Fiber Optic Page 1 ns denne le dee dee Inner eee ie onte decet 31 Table 8 BOM Fiber Optic Page 2 sn ee een nen OR neo e XA eO ua a e M Ee Ed ee ER ee dup 32 Table 9 BOM AS Interface CirCUlt ee 34 Table 40 BOM CANopen CIrCUIL eine ee BR pue iE E Reese Table 11 BOM CC Link Circuit Table 12 BOM CompoNet Circuit Table 13 Optional BOM CompoNet 40 14 BOM DeviceNet Circuit keiser erri DE re Meet dad a RR en 42 Table 15 BOM PROFIBUS Circuit 44 Table 16 BOM MMC SD Card 4 42 0210 00 nu D entes inns entere enteras 46 Table 17 BOM microSD een es legen calles nn ea 46 T ble 18 BOM UART amp RS232 ee ee ad take pre nee RT S 48 Table 19 BOM USB Device cece ne eor REES eines 50 Table 20 coo eret ne E Une P SERERE RR EE graben anne RE 54 Table 21 BOM LCD Interface Circ it ee brennen 57 Fable 22 BOM Touch Panel Circuit een an do duse pde ee e dup 57 Table 23 List of Reso rces rcX OS Roe engere 59 Table 24 L
155. ngle LEDs with the LEDs of each pair placed close to each other for the COMO and COM1 indicators netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 118 158 4 11 Fieldbus Interface The netX controllers are equipped with flexible communication processors xPEC xMAC units also referred to as XC units that allow to realize virtually any field bus interface on the market by simply adding the appropriate physical layer circuit While the netX500 provides a total of four XC units the netX100 has three XC units and an additional unit with limited functionality used for Real time Ethernet protocols The standard XC port for a single channel field bus application on the netX100 500 is 2 as this still allows using the Ethernet interface on XCO and XC1 xMAC3 is generally not available for field bus interfaces on the netX100 and can further not be used for field bus interfaces on the netX500 when running a Real time Ethernet protocol All common field bus interfaces are serial interfaces with a Transmit and Receive signal while some of them use an additional control signal or status signal hence the xMAC units that directly connect to the field bus physical layer circuit provide an XMi TX an XMi RX and two I O signals XMi 00 and 101 whereas currently only one of them is used by current field bus interfaces Each XC unit also pro
156. ngly recommended to consult the latest Errata Sheets available on the Hilscher website www hilscher com of the netX controllers netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Introduction 5 158 1 2 Legal Notes 1 2 1 Copyright Hilscher 2008 2012 Hilscher Gesellschaft fur Systemautomation mbH All rights reserved The images photographs and texts in the accompanying material user manual accompanying texts documentation etc are protected by German and international copyright law as well as international trade and protection provisions You are not authorized to duplicate these in whole or in part using technical or mechanical methods printing photocopying or other methods to manipulate or transfer using electronic systems without prior written consent You are not permitted to make changes to copyright notices markings trademarks or ownership declarations The included diagrams do not take the patent situation into account The company names and product descriptions included in this document may be trademarks or brands of the respective owners and may be trademarked or patented Any form of further use requires the explicit consent of the respective rights owner 1 2 2 Important Notes The user manual accompanying texts and the documentation were created for the use of the products by qualified experts however errors cannot be ruled out
157. ollowing tables list netX Hardware Resources and functions and provide information on existing software support for these features No driver available means that Hilscher does currently not provide a driver or special functions for easy access to the corresponding resource however this resource may of course still be used if the user develops the appropriate code by himself or integrates third party products e g Flash File System for parallel FLASH 31 rcX Operating System Resource Functionality netX Loadable Firmware Linkable Object Modules USB Device 100 500 for firmware update for firmware update debug USB Host 100 500 not supported no driver available UARTO 100 500 for firmware update for firmware update debug UART1 100 500 Modbus RTU supported UART2 100 500 Modbus RTU supported SDRAM 100 500 required min 8MB required min 8MB for standard application Secure Memory 100 500 required min required see required min required see Table 25 Table 25 SPI Flash 100 500 required required minimum size see separate list minimum size see separate list MMC SD Card 100 500 not supported no driver available Parallel FLASH 100 500 not supported no FLASH File System only limited components LC Display 500 not supported no driver available Fieldbus Slave 1 Channel 100 500 see Table 25 see Table 25 Fieldbus Master 1 Channel 100 500 see Table 25 see Tab
158. operation without heat sink netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 142 158 Hilscher netX hardware is usually designed for a maximum junction temperature of appr 100 C which is also the recommended value for customer designs The FIT rate FIT Failure in Time see appr chapter of the Technical Data Reference Guide for the silicon process which netX10 50 100 500 are based on shows a significant rise in the temperature range between 100 C and the absolute maximum junction temperature which was the reason for choosing the 100 C However since the absolute max junction temperature is 125 C it is at a device manufacturer s discretion if he wants to follow this recommendation or rather decides to accept a higher junction temperature and trade a decrease of the MTBF of his devices for a higher temperature range specification A major factor of the thermal behavior of a netX design is the size of the PCB Design experience at Hilscher shows that designs with a power density of more than 0 15W cm2 are critical assuming the 100 C limit for the junction temperature and a maximum ambient temperature of 70 C and considering the common maximum temperatures of peripheral components like SDRAM FLASH Reset Generator etc hence the board size should be chosen accordingly To calculate the power density of a design simply divi
159. ort as possible and the length of the SDRAM clock signal trace should match the length of the longest SDRAM signal trace Figure 109 netX Memory Bus 5 2 8 Planes When routing signal lines make sure they run over an appropriate return path power or ground plane that is contiguous not more than 2 layers away and not interrupted by large gaps as this always increases emission When splitting planes can not be avoided keep traces well within the plane area and do not route at the edge or even outside of the plane as shown below netX Design In Guide netX 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 150 158 Figure 110 Routibg Example netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 151 158 5 3 Vias and Traces under the netX100 500 Using a PBGA package the netX requires small traces and vias on the PCB However as a result of the proper chip pinout design four layers and 0 15 mm traces respectively 0 2 mm through whole vias are sufficient for most applications which can hence be realized by inexpensive standard printed circuit board technology L of Figure 111 Vias and Traces under netX100 500 Top
160. pendent PWM units each with a three phase complementary output e g for controlling electric motors and an additional single phase output for supplying resolver units Due to the necessarily limited pin resources of the netX controllers the use of pin sharing was inevitable which implies some restrictions regarding the parallel use of certain chip resources The following picture roughly shows the dependencies and restrictions that may come into play when using the PWM and or Encoder interface and communication channels PWM1a b PWM3a b XMAC ECLK 0 1 2 3 Figure 92 PWM Encoder xMAC xPAC Resource Sharing The picture shows the following major restrictions Designs that also make use of the encoder interface can only use unit PWM1 Since using PWM1 rules out the use of xMAC3 which must be disabled when controlling these units from the ARM netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 131 158 CPU Real Time Ethernet designs with Encoder and PWM interface are not possible or would require customized xMAC code that can only be created by Hilscher custom development When using unit PWMO xMAC2 must be disabled allowing this unit to be controlled by the ARM CPU which excludes the use of a field bus protocol on xMAC2 or would again require customized xMAC code Further using PWMO or Encoder interface blocks PIOO 7 w
161. raight forward as shown in the following example schematics FLASH 16 16 0 23 MEMSR 50 MEMSR_OEn MEMSR_WEn 3 3V 3 3V RST_OUTn _00 15 e g S29GL256P FLASH 16Mx16 0 23 MEMSR 50 MEMSR_OEn MEMSR_WEn e 3 3V 3 3V RST_OUTn _00 15 MEM_D16 31 netX e g S29GL256P FLASH 16Mx16 3 3V 3 3V Figure 51 netX FLASH A0 as the LSB of a Word Address netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 80 158 Q1 would like to access parallel FLASH connected to the netX by another processor e g host processor while the netX does not use the FLASH or is being held in reset Is that possible 1 This will only work with additional components Since memory interfaces are usually not designed for multi master access the netX always drives all of the memory interface signals except the data lines even while being held in reset state Hence accessing any memory components by another processor is only possible when the memory components can be isolated from the netX memory interface by appropriate bus switches Q2 Do need any pull up or pull down resistors on the netX memory interface A2 Since the netX always drives all of the memory interfa
162. rcuit Fiber Optic Component Placement with AC Termination Note Please also consider the routing hints for differential signal lines in chapter 4 2 6 which correspondingly also apply to the Fiber optic interface 4 10 2 4 Diagnostic Monitoring Interface For netX fiber optic designs that are to be used with Real time Ethernet protocols especially PROFINET the fiber optic transceivers must be equipped with DMI Digital Diagnostics Monitoring Interface providing status information like the AFBR 5978Z or QFBR 5978AZ from Avago Technologies netX Design In Guide 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 111 158 While components can usually be connected to a common signal bus as they can normally be individually addressed through their I C device address this is unfortunately not possible with the AFBR 5978Z QFBR 5978AZ since these devices do not provide a hardware configurable device address Each AFBR 5978Z QFBR 5978AZ uses the same device address which allows coexistence with other components sensors memories etc but not with a second AFBR 5978Z QFBR 5978AZ Since Real time Ethernet protocols usually require two Ethernet channels and hence also two Transceivers solution for the addressing problem had to be found and is described below With netX100 500 an external component is required to switch the SDA signal line of the netX
163. s for the ETM signals as short as possible the signal delay should be lt 100ps The length of the lines should be equal to avoid different signal delays To improve signal quality matching resistors can be netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 72 158 placed in the signal lines located as close as possible to the chip pins 10mm to match the output impedance of the chip signal driver with the PCB trace impedance 4 5 3 Boundary Scan For automated production testing of a final netX product it may be desirable to make use of the netX Boundary Scan feature In that case certain conditions must be met to allow entering the Boundary Scan test mode The first condition refers to the logic level on the TEST pin netX100 500 K19 The design must provide a possibility to pull this signal to high level which activates the test modes which can be realized by a jumper or a contact pad for the test system which then controls this signal Further all JTAG signals must be available to the test system e g by appropriate contact pads JT TDI JT TDO JT TMS d JT_TRST TEST netX500 netX100 Figure 46 netX100 500 Boundary Scan JTAG TEST Signals The 1 pull down resistor placed as close as possible to the netX pin can be omitted when the signal trac
164. s then stabilized by a PLL which generates all internal Clocks of the chip except the clock for the internal Real Time Clock netX500 only which is covered in the following subchapter 4 3 2 The following figure shows the clock circuits for the system clock generation a 1 5V b 1 5V netX 500 OSC VDDC netX 100 OSC VDDC OSC VSS OSC VSS OSC XTI OSC XTO OSC XTI OSC XTO p GND Vw 1041 Food 25 MHz 22 pF 22 pF SR ce GND GND GND Figure 41 netX100 500 System Oscillator Circuit The values of the capacitors and the serial Resistor Rs depend on the used crystal When using the same crystal all Hilscher netX products are equipped with the resistor Rs will not be used and replaced by a wire further the capacitors should have a value of 22pF If a different crystal is used the data sheet of the crystal must be consulted to determine the appropriate values The Hilscher standard netX system crystal is a C810 25 000MAGJ UT manufactured by Citizen Alternatively an external oscillator can be used which is then connected according to schematic b Note When selecting an external oscillator or a different crystal it must be provided that these parts have a frequency of 25 MHz with a maximum tolerance of 100 ppm throughout the complete temperature range the design will be specified for Q1 We already stock crystals or oscillators with a different frequency or higher tolerance can
165. sic modes which are twisted pair 1OBASE T 100BASE TX and fiber optic mode 100BASE FX 4 10 1 Twisted Pair For 10BASE T 100BASE TX Ethernet communication the PHY must be connected as shown in the following example schematic Figure 72 R1 1000 Q 100 MHz 200 mA 1 5 PHY VDDCAP iz PHYO VDDCART C1 C2 PHY1_VDDCART 020 T 100n 10u R2 1000 Q 100 MHz 200 mA 4 3 PHY_VDDIOAT VDDIOAC 18 21 632 PHY_VSSAT PHY_VSSACP PHYO_VSSAR PHYO VSSAT1 PHYO VSSAT2 D19 PHY1_VSSAR amp PHY1_VSSAT1 To Sr zlo ifa PHY1 VSSAT2 919 e RJ45 Q gt T da PHYO TXP TXP 220 EN TXN R15 R16 C9 5 5 l 10 7 M R17 R18 Dre 289 75 le 75 Le 2 PHYo_RxP H21 5 am H20 gm RXN PHYO_RXN 4 A 1 1 I Cl l ELEM 10n 2kV 10n T 5 7 100n 4 F20 C C8 100n R7 Ha R8 50 R13 10 5 on aan 2 E PHY1_TXP EH PHY1_TXN F21 i H enis R19 Ro mm BHH 5 10n NE S RM R22 2828 ze EHEk 2 PHY1_RxP 20 4 3 a 6 am RXN PHY1 RxN E21 i
166. sulted to determine the correct way of hooking up the address lines of the FLASH Many 16 Bit FLASH components e g TE28F128J use address line AO for low high Byte selection when operating the component in 8 Bit mode and do not use AO at all when in 16 Bit mode Such components must hence have AO of the FLASH grounded to prevent floating while AO of the netX is connected to A1 of the FLASH A1 to A2 A2 to A3 etc The following schematics show an example netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 0 23 MEMSR 50 MEMSR_OEn MEMSR_WEn RST_OUTn _00 15 0 23 MEMSR 50 MEMSR_OEn MEMSR_WEn RST_OUTn 0 15 MEM_D16 31 netX FLASH 16Mx16 3 3V 3 3V e g TE28F128J 78 158 FLASH 16Mx16 3 3V 3 3V e g TE28F128J FLASH 16Mx16 3 3V 3 3V Figure 50 netX FLASH Address Line 0 for Low High Byte Selection netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 79 158 Other FLASH components e g S29GL256P always use AO as the LSB of a Word 16 Bit address hence the address lines of such components must be connected st
167. tX500 Figure 68 netX100 500 UARTO Unused If UARTO is completely unconnected and the netX is configured for serial boot mode then the ROM boot loader misinterprets the low level on RXD and CTSn caused by the internal pull downs on these unconnected pins as a connection attempt through the UARTO port and switches to UART mode The serial boot mode can then not be used via the USB port and can hence not be used at all as UARTO is of course not accessible when not connected netX Design In Guide netX 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 98 158 4 9 USB The netX provides a USB 1 1 compliant USB interface that can either be used in device mode Downstream Port or in host mode Upstream Port The device mode is commonly used to connect the netX to a PC while the host mode allows to access for example memory devices like USB sticks etc Both modes require different external circuits that are described in the following chapters Though the netX is equipped with separate power supply pins for the USB interface USB_VDDIO USB_VDDC and USB_GND on the netX100 500 these pins can simply be connected to the corresponding voltage rail and do not require any special filtering etc however please regard the following note related to the USB_VDDIO 3 3 V supply Note The worst case short circuit current that may flow through the netX USB Buffers can reach 17
168. tage of this separate supply should be programmable either by appr digital input pins or by external resistors This allows to continue to use the same design when the used netX type has gone through a die shrink process which always results in a reduced core voltage 4 181 Core Voltage Regulator A Hilscher standard circuit for the core voltage regulator uses a FAN2001 Fairchild Semiconductor step down DC DC converter and is shown below 3V3 2 5V 5 5V 1V5 A A 22uF 2 PGND AGND 7 FAN 2001 1 96 GND GND GND GND GND Figure 96 netX Core Voltage Regulator The complete part name is 2001 the inductor is CR32NP 3R3 Sumida and the capacitors are ceramic types X5R resistors 1 netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 139 158 4 18 2 Alternative Core Voltage Regulator An alternative part especially for designs with space constraints is the EN5312Q Enpirion which delivers 1A has an integrated inductor and provides 3 digital inputs for setting the output voltage requiring only two 10 uF ceramic caps as additional external components see www enpirion com for detailed information GND Figure 97 Alternative Core Voltage Regulator 4 18 3 Common Supply Voltage Regulator 3 3 V A standard circuit for a common supply voltage of 24V which operates from 9V to 30V and d
169. tch The USB over current detection signal USB_OCn is used to signal a USB over current condition detected by the power switch to the netX When used this active low signal is to be connected to the over current output signal of a power switch Note Please note that there is no inherent hardware support for the above mentioned signals All functions associated with these signals are only available when supported by firmware The 5 V power supply must be dimensioned to meet the power requirements of the USB devices that are to be connected to the netX some devices require up to 500mA when fully operational Please also consider the USB V1 1 specification for further details 3 3V 1 5V USB VDDIO USB VDDC 5V Power Switch AA13 yUsB ONn VBUS Y13 USB OCn e g TPS2041A USB DPOS B20 jam 1234 Transient USB DNEG 2 mm D Receptacle A E a LO LO USB_VSS 21 4 mm GND netX100 netX500 END Figure 71 netX100 500 USB UPstream Port Host Mode netX Design In Guide 100 500 DOCO081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 102 158 4 10 Ethernet Interface netX100 500 have two integrated Physical Layer Units PHYs for Ethernet Communication that allow to build systems with two Ethernet ports while using only a few external components like pull ups and transformer s The PHYs be operated in two ba
170. ublic Hilscher 2008 2012 41 158 netX100 500 Quick Start 27 DeviceNet vL L eL 6 8 Z 9 4 L L Jo obey MEI 13N3OIA3G 102191 era ANY yeuosjesec JOuosiH Jezjoyysenmeyy papa OLci ousaara3raaoia m E 710 Fi 2 2018 5090 boia In Th k k d LOld AS AS gos n 3 SLI 6019 vhs _ NG awoosi 4 ssoede asd 70018 0001 2 m t T 710 odas T T TAA Nd 3022 5080 ANZ 080 hee AZ sur 8019 40 2 8 5 019 ZHINODL 0001 2 si LOLL IN Y AS OSI i i 1 are Oey EN ano eH te T t 1vo W3 cz 34001 5090 230001 090 w 9019 ori c 109 a Corax
171. uestions Q1 I m not building an evaluation board Do really need all these jumpers A1 Well that depends on the way your design intends to load its firmware Standard design that use either a serial or parallel FLASH or an MMC card for storing the firmware do not need J2 and R2b Designs that use a FLASH connected to the Extension Bus a hardly used option or Dual Port Memory DPM boot mode will require both jumpers pull down resistors Q2 But I m always using DPM boot mode can t just omit J1 and R1b and replace J2 by a wire A2 You could basically do that but keep in mind that you will then not be able to activate the serial boot mode for test or debug purposes Q3 I m using a serial or parallel FLASH to boot from Do need any jumpers at all A3 Unless you want to program the FLASH before mounting and remove it for reprogramming every time you want to change the firmware it is strongly recommended to have J1 or a push button switch and R1b on your design This allows activating the serial boot mode which will then allow to re flash the firmware netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 64 158 Q4 Your reference schematics and some documentation do not show any pull up resistors on RDY and RUN further the netX100 500 has internal pull ups on RDY and RUN so do I really need these 15 kQ pull ups
172. uitry we strongly recommend to contact the manufacturer of their encoders to find the best solution for their design netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 134 158 4 15 LCD Interface The netX500 is equipped with an LCD controller allowing to connect color ow STN or DSTN as well as TFT displays Connecting a display does usually not require any additional components and is accomplished by simply hooking up the display signals to the appropriate LCD signals of the netX500 Depending on the display type and the corresponding register settings of the LCD controller the LCD data lines LCD_D 17 0 have different mappings Please consult the netX100 500 Technical Data Reference Guide chapter 2 24 for a table listing all possible display modes and the corresponding data signal mapping Chapter 7 4 Signal Definitions lists the 5 control signals of the LCD controller and their functionality in STN and TFT display mode Besides the designated LCD display signals another signal may be required for controlling the backlight of the connected display For this purpose GPIO14 has been assigned an appropriate standard function It can be simply set or cleared in order to turn on and off the display backlight or if supported by the display switched to PWM mode to control the intensity of the backlight If the display can
173. uld be free from any other signals in adjacent layers use only layers that are separated from the Ethernet signal layer s by a power or ground plane when routing other signals in the Ethernet area Use the schematic from chapter 3 10 1 along with the recommended components The following pictures show two examples of setups that keep the differential impedance of the signal pair around 100 Ohm netX Design In Guide 100 500 DOC081 106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations a Edge Coupled Surface Micro 35 um 112 um 150um 6 mil strip 150um 6 mil lt 150um 6 mil lt gt Figure 107 Edge Coupled Sourface Micro Strip 148 158 To improve shielding the Ethernet traces can be routed on an inner layer using part of the top layer as shield b Edge Coupled Offset Strip line netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 General Design Considerations 149 158 150um 6 mil gt 24 96 0 100um 100um 4 mil 4 mil gt lt Figure 108 Edge Coupled Offset Strip Line 5 2 7 Memory Bus When connecting SDRAM and or parallel FLASH SRAM etc route the connection in a bus structure no tree with the bus starting at the netX as shown in the following picture The bus should be as sh
174. ur 8 Bit components is further recommended due to easier PCB design and reduced load capacity two 16 Bit components usually add twice the load to the address and control signals as a comparable 32 Bit component Q1 In the meantime DDR 3 RAM is state of the art Why are the netX chips only equipped with an outdated SDRAM interface A1 Well SDRAM isn t really outdated DDR RAM technology was invented for the short lived PC market where it is commonly accepted that components have extremely short life cycles limited operating condition range and substantial power consumption Since DDR RAMs work with internal PLLs and can hence not be used on older slower memory interfaces DDR RAM technology is not suitable for the embedded industrial market where customers usually look for availability of several years Further even powerful embedded processor technology like ARM can necessarily not compete with common PC processors in terms of processing power hence it would make little sense to connect such processors to DDR RAMs anyway Connecting SDRAM to the is pretty straight forward besides address lines 16 and 17 which are used for the bank select signals BAO and BA1 The schematics on the following page show examples for connecting 8 16 and 32 Bit SDRAMs netX Design In Guide 100 500 DOC081106ANO2EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits A0 12
175. ure 87 Basic Circuit for netX DeviceNet 124 Figure 88 Basic Circuit for netX PROFIBUS 125 Figure Gs qa huk lu shig h assqa peiora 127 Figure 90 ADC Circuit One Channel Used a 128 Figure 91 ADC Circuit ADCs 44 10 0000000 B uuu sisi u say aus 129 Figure 92 PWM Encoder xMAC xPAC Resource 130 Figure 93 Encoder Circuit Example reesi 132 Figure 94 LCD Backlight PWM RC Filter Windows 134 Figure 95 Touch Panel Circuit as aspasia aaa 135 Figure 96 netX Core Voltage 138 Figure 97 Alternative Core Voltage 139 Figure 98 netX 3V3 Supply REPE BRE aeree dee 139 Figure 997 netX 5V Supply teet Bern Alm Rn mn Rn 140 Figure 102 Approved netX PCB Layer 144 Figure 103 netX100 500 Decoupling Caps 145 Figure 104 netX100 500 Decoupling Caps Vias and Inner Plane for VDD IO and VDD CORE 145 Figure 105 Power Supply Filter etie rire eene dee tern tdg Hin herein dede erede dde readers 146 Figure 10
176. us The switches or jumpers are optional as the host interface can also be configured to use an internally stored compare value allowing to set the base address by firmware The circuit shown above will result in a 64k address space occupied by the netX ISA Bus interface which is the netX standard DPM size However as memory space is often scarce in ISA Bus systems the occupied memory space of the netX may be reduced by removing connections between DPM_SELA12 15 and the corresponding A12 15 If the connection between DPM_SELA15 and A15 is removed and optionally DPM_SELA15 is connected to the address switch jumpers the memory window is reduced to 32k If this is also done for DPM_SELA14 the window is reduced to 16k etc Of course every reduction of the memory window size increases the granularity of the base address setting Please also check the following subchapter for further details on the internal chip select generator netX Design In Guide netX 100 500 DOC081106AN02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 90 158 4 7 1 5 Internal Chip Select Generator As already mentioned in the previous subchapter 4 7 1 4 the netX DPM interface can use internal chip select generator instead of the standard DPM CSn external chip select signal Although this was implemented mainly to meet the requirements of ISA Bus systems the chip select generator can also be used for standard DPM
177. vides a clock input output signal XMi that either allows synchronizing external hardware to the XC clock or feeding an external clock to the XC unit Both options are currently not used The pinning of the XMAC signals is fixed for netX100 500 For that reason it is strongly recommended to adopt the proposed MMIO assignment for the XMAC signals as shown in the following example schematic netX Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 119 158 XM2_TX PROFIBUS DP CANopen DeviceNet ASi 2 100 CTRL CC Link CompoNet XM2_RX 2 101 Fieldbus Physical Layer Interface XMO 1_TX 0 1 RX 0 1 100 netX 100 0 1 101 XM2_TX PROFIBUS DP CANopen DeviceNet ASi 2 100 CTRL CC Link CompoNet XM2_RX 2 101 Fieldbus Physical Layer Interface XMO 1 3_TX gt XM0 1 3 XM0 1 3_100 6 gt 0 1 3 101 netX 500 Figure 82 netX100 500 Fieldbus Interface netX Design In Guide 100 500 081106 2 Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 120 158 4 11 1 5 interface Master As there are no pure ASi transceivers on the market and generating the sin signals is not trivial interface with the netX still requires t
178. we also use these parts for the system oscillator A1 No The 25 MHz clock is the base for all other netX clocks and has hence influence on any timing around the like SDRAM timing Baud Rates Ethernet timing etc Deviating from the specified frequency will most likely result in a system that does not work properly Design In Guide netX 100 500 DOC081106ANO02EN Revision 2 English 2012 10 Released Public Hilscher 2008 2012 Standard Circuits 67 158 4 3 2 Real Time Clock 4 3 2 1 Designs with RTC netX500 is equipped with a Real Time Clock that can be powered separately from the rest of the chip and will then continue to run when the system is powered down The RTC module further provides a backup feature by powering a 16K portion of the netX500 internal RAM that can preserve data To avoid uncontrolled access to this part of the RAM as a result of a power fail the Backup RAM will be isolated when the RTC POK pin is pulled low If this feature is to be used a power supervision circuit must be connected to the main power supply The supervision circuit must pull the RTC POK signal low when the main input voltage drops below a certain level This of course does only make sense if the power supplies are designed that way that in case the input voltage fails they will continue to deliver stable voltages to the 1 5 V and 3 3 V rails of the netX for a certain time allowing the isolation process to complet

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