PDA3 User Manual
Contents
1. HIGH W521_H 010 Internal W521_H register High byte of 521 th word of frame contents W521_L 011 Internal W521_L register Low byte of 521 th word of frame contents W522_H 100 Internal W522_H register High byte of 522 th word of frame contents W522_L 101 Internal W522_L register Low byte of 521 th word of frame contents The purpose of the last 4 registers is to provide the user a way to insert relevant information scan info timepoints etc into the raw data Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences User doc 7 8 Specifications Power E Linear power supply 230V 50W E Fuse 500mAT Inputs and Outputs m PDA Two 16 bits ADC s generating 1Mb sec data at 1kHz trigger rate E Trig In Trigger input SMA connector TTL in max 5 Volt min pulse width 250 ns Nominal frequency 1 kHz max frequency 2 2 kHz m CHO CH1 CH2 Digital Chopper signal inputs on SMA connectors TTL in max 5V CHO gt Pump beam chopper CH1 gt Dump beam chopper CH2 gt Spare digital IO channel E AninA AninB Analog Inputs Analog input range 10V until 10V 16 bits ADC E AnOutU AnOUtL Analog Outputs Analog Output range 1V until 5V Analog output of upper and lower photodiode array after integration OV gt no light 2V gt saturation Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences2. fast enough to read the data every 8 ms to prevent data loss Minimal host requirements are Processor running 2 2 GHz or faster Windows 2000 or Windows XP USB 2 0 support The VUSB kernel driver must be installed before the PDA3 hardware can be used Download the latest software from the Electronics Web page see the front page of this manual Installation notes can be found in the downloaded Read Me file Data Frame contents word 1 Identification Word OxA5A5 word 2 Frame Counter starts at OxFCOO word 3 First pixel of lower PDA 16 bits data word 4 First pixel of upper PDA word 5 Second pixel of lower PDA word 6 Second pixel of upper PDA word 7 Third pixel of lower PDA word 8 Third pixel of upper PDA word 511 255 th pixel of lower PDA word 512 255 th pixel of upper PDA word 513 256 th pixel of lower PDA word 514 256 th pixel of upper PDA word 515 Analog B input from16 bits ADC word 516 Analog A input from 16 bits ADC word 517 Digital GPIOO input 0x0000 when LOW OxFFFF when HIGH word 518 Digital GPIO1 input idem word 519 Digital GPIO2 input idem word 520 Digital GPIO3 input idem word 521 W521 register values W521_H and W521_L word 522 W522 register values W522_H and W522 L Frame size is kept identical to the PDA2 system so the analyzing software could stay the sam
3. PDAS Photo Diode Array Detector System User Manual KS vrije Universiteit amsterdam Warning This equipment uses voltages which are dangerous to life It should be serviced only by qualified personnel Lex van der Gracht October 9 2006 Project ID 20054007 Electronics Group Filename Documentt Faculty of Sciences Pages 9 Vrije Universiteit Amsterdam the Netherlands Last save October 13 2006 Phone 31 20 5987973 Email a van der gracht few vu nl Fax 31 20 5987899 Web http Awww few vu nl elec User doc 1 Table of contents 1 Precautlons wuicccstiei wat te eevee aie Ned eevee aoa ates Bean ee Qa Ee naa i 2 General DOSCriPtiON siiessicssisnireiiiidiinei iiia iaie iiaiai idia iii iiaa aini 1 3 SYSlEM DESCHPUON ei iseiti ag dee a diaii iaai ida iaia i rete 1 e E BE i ER O E A E E A AAA A E A AE A E TPA A T ST 1 3 1 2 Hardware Block Diagram oiaro inorena i aoed ia GeL AN 2 Bi aS E E E E E E E A A A E S 3 eE R a e E a EE E A O TE OEE ade 3 SRo Tagger INPUtsatteicctercestatieyiteterecidtteevislimee AES EEAS ESE EEES ELEA aae et 3 CE E e Elo IMPUts EE EEE E E E EE E E O E E 3 4 Installation Procede Ea arnar T aaraa raaa stunting a A Ea aTa Aaa AEA aT A AKEn Na 4 5 Data Frame COMtCMIS eekster knre eke E EE EE EEEa AEAEE COCEA ase AREA NEEESE SUNEN 4 6 VUSB Useriniormatiorni ccs viscsces ctactadyvasetacecheateaves O E E EEEE AREN Mltiscnatavedd ARAR Ek 5 6 1 USB Vendor Commands ssm saiia en aaa e
4. When the Host computer requests data the USB controller shifts data out of the FIFO creating space for new data Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences User doc 3 3 1 3 Power The PDAS uses a dedicated power supply the Linear Power Supply 20067002 This is a special power supply with a single multi wired output cable to the PDA3 system The power supply has a on off switch at the rear and a pushbutton Standby On at the front When the power supply is switched on it goes in standby The PDA3 system can be switched on by pushing the Standby On button on the power supply or by using the pushbutton at the rear side of the PDA3 system The status LED of the power supply should be green when the power is applied If the status LED is red a power error occurred Turn off the device and bring it to the Electronics department for service 3 1 4 Timing After the rising edge of a trigger pulse the PDA3 hardware collects data Directly after the trigger pulse the PDA readout starts PDA readout takes about 380 us When the PDA readout is finished both rear Analog Inputs are sampled Finally the rear Digital Inputs are sampled When all data is collected the data transmission starts The frame will be transmitted over USB within 40 us so the total frame handling takes less than 420 us PDA data An and Dig In USB data sampling sampling transmission 0 us 380 us 420 us Trig edge Trig edge Both Upper a
5. ay detector system designed to measure the double beam output spectrum of a Spectrograph in a laser setup It s a redesign of the PDA2 system using USB 2 0 for data transmission and control 3 System Description 3 1 1 General The PDAS system is not a stand alone instrument it needs a host computer running the PDAS software This is a LabWindows CVI program written by members of the Biophysics department PDA3 Hardware Host Computer VUSB PDA3 driver software There is also a driver necessary for the communication between the PDA software and the hardware the VUSB kernel driver For Host Computer requirements and driver installation procedures see the Installation Procedure chapter Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences User doc 2 3 1 2 Hardware Block Diagram FPGA diode FIFO and arrays Timing controller Linear Power Supply 20067002 3 1 2 1 Block Diagram description The photodiode arrays are an Upper array and a Lower array of 256 photodiodes which signals are clocked out simultaneous by the FPGA Output charges are first converted into a voltage then integrated and sampled by a 16 bits AD converter Inside the FPGA a data frame is build and the sampled data goes into the FIFO Lower data first When all PDA data is collected the An In ADC s are sampled and data is added to the FIFO Finally the Dig In channels are converted into 16 bit values and added to the FIFO
6. e The Identification word can be used to check for data alignment errors The Frame counter word is a legacy item and is ignored in software The last two frame words W521 and W522 are spare data words In the current implementation they reflect internal FPGA register values These values can be set through USB commands by software The idea was to use these registers to add user info to the data e g delay info Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences User doc 5 6 VUSB User Information The VUSB kernel driver is a driver for the PDA3 system Host Computer Kernel Mode User Mode PDA3 system l LabWindows CVI program Calls to this driver can only be made through a specific DLL the VUSBkernel DLL This DLL uses a Set of basic USB calls independent of hardware or software Another user space DLL called PDA3user defines PDA3 specific calls and translates them into VUSBkernel calls 6 1 USB Vendor Commands USB Vendor commands User commands 0xBO Hardware reset 0xB1 Enable IN transfers bulk transfer from PDAS to host 0xB2 Disable IN transfers 0xB3 Get hardware s USB status register 0xB4 Get PDAS registers in FPGA OxB5 Set PDAS registers in FPGA OxB6 Reset Hardware FIFO Test commands 0xCO reset hardware s USB status register only for testing OxC1 read GPIFREADYSTAT register for testing the GPIF OxC2 read ep6fifobuf f
7. nd Lower Arrays of the PDA are clocked simultaneously The output charge of each array element is converted into a voltage and integrated The integrated signals are simultaneously sampled by the ADC s 3 1 5 Trigger Input The trigger input signal should be a 1KHz TTL trigger pulse generated by the laser system The pulse width should have a minimum value of 250 ns The maximum trigger rate is 2 2 KHz now limited because data transfer is only allowed after the data collection The driver uses a routine with a 6 sec timeout to read the data so if the trigger rate is too slow the PDA3 system will give an error PDA3 Read failed 3 1 6 Analog Inputs These inputs are sampled after the PDA readout is finished In normal mode the inputs are sampled and the digital values are added to the Frame contents The analog inputs also have an integrated mode but this mode still has to be implemented inside the FPGA Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences doc 4 User 4 5 Installation Procedure The PDAS sytem is a USB device The PDA3 system needs a High Speed USB connection to the host computer If the system enumerates to a Full Speed connection 12Mbits sec the PDA system error LED will be lit just after connecting The PDAS system uses a dedicated driver the VUSB kernel driver to assure a constant data flow in a Windows environment The hardware is using a small 8 kB FIFO memory The host should be
8. or testing the bulk buffer 0xC3 fill ep6fifobuf for testing the bulk buffer 6 2 USB status register bits read only b7 b6 b5 b4 b3 b2 b1 bO Res Res Res Res ExtFifoFullBit EP6FifoFullBit InEnableBit EnumHighSpeedBit HIGH when HIGH when Bulk transfer HIGH when device is External FIFO is Endpoint6 FIFO is enabled status High Speed Enumerated FULL FULL Must be HIGH for PDA3 Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences User doc 7 PDAS registers Register Regs b7 b6 b5 b4 b3 b2 b1 bO el 2 1 0 GPIO 000 Re Res GPIO1_FPGA_HOS GPIOO_FPGA_Hos GPIO GPIO GPIO GPIO s 1 tn 3 2 1 0 If GPIO1 Input If GPIOO Input GPIO3 GPIO2 GPIO1 GPIOO NOT NOW NOT NOW input input input input GPIO1 output can be GPIOO output can be status status status status programmed from programmed from FPGA Trigger Read Read Read FPGA HIGH HIGH Input Only Only Only or controlled by Host or controlled by Host on program LOW program LOW PDAS Read Only CONTROL 001 Us TestDAT SLOWADCIntBn SLOWADCIntAn LED2 LED1 LEDO TrigE bAc nable t drive PDA3 SLOW ADC_B SLOW ADC_AINPUT is Drives Drives Drives Externa s generates INPUT is NORMAL NORMAL when LOW the the the l USB dummy when LOW Integrated when HIGH LED2 LED1 LEDO triggers Activ test data Integrated when output output output are ity when HIGH Enable LED HIGH d when
9. rataa aE a aaa AD Ta ace deeds 5 6 2 USB status register Dits iina ennai naan aa eaaa A aA aa a AAE ASEA eda 5 7 DEAE a E E A EA E EEE PAE E E EEEE E EIEEE E E EE 6 8 ToT er eI NA R AAEE TT E E EATE A EE AE EE OEA E 7 1 Precautions Safety check has been done following the NEN EN 50110 1 and NEN 3140 Hazardous voltages exist in this apparatus Besides the regular safety precautions the following should be observed when working with this unit 1 When power is required the unit should be plugged into an outlet with a properly grounded receptacle The use of two prong plug adapters is not recommended 2 The use of extension cords may compromise the safety of the operator and is not recommended 3 Ensure that the fuses installed in the unit are of the correct rating 4 A damaged power cord or plug may constitute a shock or fire hazard Do not allow continued operation of the unit until the damaged cord or plug has been replaced 5 Ensure that none of the ventilation openings in the apparatus are blocked Excessive heat build up in the unit may cause failures 6 Do not exceed maximum allowable mains input voltage 7 The apparatus is designed for horizontal use only 8 The apparatus should not be opened by the user in case of a malfunction it will be serviced by the Electronics group Electronics Group Vrije Universiteit Amsterdam Faculty of Sciences User doc 1 2 General Description The PDAS is a dual photodiode arr
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