Reconfigurable Computing
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1. ahbctrl Configuration area at x ffEf000 d kbyte ahbctrl mat Aeroflex CGaisler LEON SPARC V8 Processor ahbctrl matl Aeroflex Gaisler JTAG Debug Link ahbctrl asalv Aeroflex Gaialer Generic AHB ROM ahbctrl memory at Ox0O0000000 size 1 Mbyte cacheable prefetch ahbctrl aslvl Aeroflex Gaisler AHB APB Bridge ahbctrl memory at Ox60000000 size 1 Mbyte ahbctrl salva Aeroflex Gaisler LEONS Debug Support Unit ahbctrl memory at Ox90000000 size 256 Mbyte ahbctrl alw3 Aeroflex Gaisler Xilinx MIG DDR2 Controller ahbctrl memory at Oxd0000000 size 256 Mbyte cacheable prefetch ahbctrl slw6 Aeroflex Gaisler Test report module ahbctrl memory at Ox2Z0000000 size 1 Mbyte apbctrl APB Bridge at Oxs0000000 rew 1 apbctrl slw0 Aeroflex Gaisler Xilinx MIG DORZ Controller apbctrl I O ports at Ox80000000 size 256 byte apbctrl salwl Aeroflex Gaisler Generic UART apbctrl I o ports at Ox80000100 size 256 byte apbctrl alw2 Aeroflex Gaisler Multi processor Interrupt ctrl apbctrl I O ports at Ox80000200 size 256 byte apbctrl alw3 Aeroflex Gaisler Modular Timer Unit apbctrl I O ports at Ox80000300 size 256 byte apbctrl FAU Computer Science 12 COUNTER apbctrl I O ports at Ox80000d00 size 256 byte apbctrl FAU Computer Science 12 EDGE DETECTION apbctrl T O ports at Ox80000500 size 256 byte Figure 3 Counter and Hardware Accelerator Modules on LEON32. Dbg Link MAC Link Link Processor AMBA AHB AMBA APB AHB Memory AHB APB Controller Controller Bridge PS 2 UART IrqCtrl I O port 8 32 bits memory bus SS SS SS SS PROM I O SRAM SDRAM ae PS 2 IF RS232 WDOG 32 bit I O port Figure 1 An example of a LEON3 system designed with GRLIB IP library 1 Software Let s compile a simple Hello World example e Goto folder software e Compile the program hello_world c using a sparc compiler sparc leon elf gece Wall o hello_world exe hello_world c e Copy the binary file into the RAM sparc leon elf objcopy 0 srec gap fill 0 hello_world exe ram srec 2 Simulation Here we will test the software simulating the design with Modelsim e In the folder leon3 digilent xc7z020 load the Modelsim module load modelsim 10 2c_x86_64 pc linux e Remove all temporary files make distclean e Compile the design make vsim e Start Modelsim vsim testbench mpf or make vsim launch e Start the simulation executig the script do start_sim at the prompt of the simulator Note if you change any HDL file you need to recompile the design again e Run the simulation run all 3 Counter Now using the Advance Peripheral Bus APB let s create and connect a counter module that will be used to measure the performance of both software and hardware computation Note that this module will be accessible via software e Access the folder vhdl Here you will see the
3. e Inthe folder vhdl are the files top_for_edge_detection vhd and edge_detection vhd Complete these files and add them in the simulation e Inthe file leon3mp vhd set the constant values CFG_COUNTER and COUNTER_EDGE_DETECTION to 1 and 5 respectively e Complete the program edge_detection c located in the folder software In this same file you also have to complete the instructions for starting the hardware accelerator e In order to achieve a better performance compile the software using the optimization flag 02 that is used for optimizing the software execution e Compile the design e Before starting a simulation Open the script start_sim and uncomment the lines to show the waveforms of the hardware accelerator e In this step the counter as well as the hardware accelerator are integrated in the system as depicted in Figure 2 e Repeat the simulation The expected output is presented in Figure 3 e At the prompt of the simulator the number of cycles needed to execute both software and hardware is shown Thus answer how faster is the hardware accelerator in comparison with the software execution References 1 Aeroflex Gaisler GRLIB IP Library User s Manual 2014 2 J Tong I Anderson and M Khalid Soft core processors for embedded systems In Microelec tronics 2006 ICM 06 International Conference on pages 170 173 Dec 2006
4. file counter vhd Complete the file and add it in the simulation e In the file leon3mp vhd set the constant values CFG_COUNTER and COUNTER_INDEX to 1 and 4 respectively e Write a software to read the counter values For that you can simply complete the pro gram counter c located in the folder software Then compile the program and load it into the RAM e Compile the design e Before starting the simulation Open the script start_sim and uncomment the lines to show the waveforms of the counter e Repeat the simulation The expected output is presented in Figure 2 4 Hardware Accelerator Similar to step 3 we will connect the hardware accelerator for the edge detection using APB E sim Default EE Instance DE testhench JM cpu reset_pad ahbo leon3_0 led1_pad dsugen W dsuact_pad ahbjtaggend leon3_zedboard_stub_i ahb2axi0 4 apbo irqgen l gpt gpiod f ual hready_pad rsti_pad ahbs bpromgen rc_lab_counter0 rc_lab_edge_detection rc_lab_edge_detection_0 4 Figure 2 Integration of Counter and Hardware Accelerator Modules on LEON3 using APB Wolkd 71 gt run LEONS Xilinx Zedboard Demonatration design GRLIB Version 1 3 7 Build dldd Target technology zyng 7000 memory library zynq7Too00 ahbctrl AHB arbiter multiplexer rev 1 ahbetrl Common I O area at xfff00000 1 Mbyte ahbctrl AHB masters 2 AHB slaves amp
5. esign Informatik 12 Cauerstr 11 91058 Erlangen FRIEDRICH ALEXANDER UNIVERSITAT ERLANGEN NURNBERG Reconfigurable Computing Lab 4 Problem 1 Softcore Processors and Hardware Acceleration Overview A softcore processor is a hardware description language HDL model of a specific pro cessor CPU that can be customized for a given application and synthesized for an ASIC or FPGA target In many applications soft core processors provide several advantages over custom designed processors such as reduced cost flexibility platform independence and greater immunity to obso lescence Embedded systems are hardware and software components working together to perform a specific function 2 Usually they contain embedded processors that are often in the form of soft core processors that execute software codes and in heterogeneous multiprocessor system on chip MPSoC scenario a dedicated hardware accelerator 1s often used to speedup applications In this exercise we demonstrate the advantages of controlling a hardware accelerator using a soft core processor by simulating a typical RISC processor LEON3 system on a Xilinx Zynq device The DDR3 memory attached to the Cortex A9 processor system PS is used as LEON3 memory and accessed through a custom AHB AXI bridge ahb2axi vhd and using a LEON3 processor we will create and attach a hardware module to accelerate an edge detection algorithm Before starting an example of a 2 D convoluti
6. on edge detection is specified in Eq 1 Here the convolved output pixel at location m n for a given window size of w x w 18 computed as follows wa 2 Lwy 2 i Ww 2 j l w 21 where x represents the input pixel stream and represents the convolution window laplace which the coefficients are defined as bellow 0 1 0 f A 0 1 0 Your tasks in this laboratory are described as follows Work Description For implementing a Sparc LEON3 core we use the GRLIB IP Library The GRLIB is an integrated set of reusable IP cores designed for system on chip SOC development The IP cores are centered around a common on chip bus and use a coherent method for simulation and synthesis The library is vendor independent with support for different CAD tools and target technologies A plug amp play method is used to configure and connect the IP cores without the need to modify any global resources The GRLIB is designed to be a bus based system 1 e it is assumed that most of the IP cores will be connected through an on chip bus The AMBA 2 0 AHB APB bus is used as the common on chip bus Figure 1 shows an example of a LEON3 system designed with GRLIB 1 All the next folders mentioned in this tutorial are accessed from this location scratch local rc lab04 LeonCore grlib gpl 1 3 7 b4144 designs leon3 digilent xc7z020 1 USB PHY RS232 JTAG PHY LVDS CAN PCI Serial JTAG Ethernet Spacewire CAN 2 0 PCI LEON3 USB Dbg Link
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