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Force Computers SYS68K / CPU-6 Manual

1. fine counter 32 bit counter month day year hours minutes seconds input port allocation table input break flags port flag bits port uart type port rate table 0 79 event table 80 95 output events 96 111 input events 112 127 system events task 128 events events 112 115 timers clock adjust constant task list pointer user tcb ptr supervisor interrupt mask user interrupt mask Spawn task no must be even user task time task priority must be even current task number reserved task queue offset flag no task lock reschedule flags batch task 4 spooler task system checksum pnet node bus error vector illegal vector control C count window id s window addresses input stream output stream 1 redirect file expand count processor ident byte abs addr of table port row col T b output port pointers 1 15 uart base addresses 1 15 memory map bias m T 7 m K ny M 7 my z7 P 7 m y ny m m Tu we ud n 5 ud System RAM Definitions cont d The following change with
2. Pin Assignment for EPROM Area 2 SRAM Upper Byte 21 62256 6264 512 256 128 64 64 128 256 512 6264 62256 15 16 28 X X X X X X X X X X X X 113 21 15 15 WE WE X X X X X X A8 26 1 14 14 14 52 14 X X X X X X 7 25 X X X X X X X X X X X X A6 24 10 X X X X X X X X X X X X 5 23 A12 X X X X X X X X X X X X A4 22 X X X X X X X X X X X X A3 21 11 X X X X X X X X X X X X A2 20 CE X X X X X X X X X X X X A 19 D15 X X X X X X X X X X X X D8 18 D14 X X X X X X X X X X X X D9 17 D13 X X X X X X X X X X X X 010 16 D12 X X X X X X X X X X X X GND 15 D11 X X X X X X Interface Information V 24 RS232 C Communication Interface The pin assignments for the 25 pin V 24 RS232 C communication connector on the rear of the terminal are as follows Connector Pin Terminal 1 Ground 2 Data Out lt 3 Data In gt 4 RTS lt 5 CTS Required note 1 gt 6 DSR Ignored gt 7 Signal Ground 8 CD Ignored gt 18 5 note 3 lt 19 READY BUSY note 2 20 DTR Always high lt Notes 1 CTS signal must be present at the terminal high before data can be sent to the host 2 READY High BUSY Low but may be
3. DO8 A MASTER that sends or receives data eight bits at a time over either 00 07 or 008 015 or A SLAVE that sends and receives data eight bits at a time over either 00 07 or 008 015 or an INTERRUPT HANDLER that receives eight bit STATUS IDs over DOO DO7 or an that sends eight bit STATUS IDs over 00 07 D16 A MASTER that sends and receives data 16 bits at a time over DOO D15 or A SLAVE that sends and receives data 16 bits at a time over DOO D15 or an INTERRUPT HANDLER that receives 16 bit STATUS IDs over D00 D15 or INTERRUPTER that sends 16 bit STATUS IDs over D00 D15 D32 A MASTER that sends and receives data 32 bits at a time over D00 D31 or A SLAVE that sends and receives data 32 bits at a time over DOO D31 or an INTERRUPT HANDLER that receives 32 bit STATUS IDs over D00 D31 or an INTERRUPTER that sends 32 bit STATUS IDs over DOO D31 H 3 special type of 1014 signal line that is used to propagate signal level from board to board starting with the first slot and ending with the last slot There are four bus grant daisy chains and one interrupt acknowledge daisy chain on the 1014 DATA TRANSFER BUS One of the four buses provided by the 1014 backplane The DATA TRANSFER BUS allows MASTERS to direct the transfer of binary data between themselves SLAVES DATA TRANSFER B
4. DTR NOT CLEAR SEND DTR CHECK PIN 20 CTS CAN WE OUTPUT A CHAR OUTPUT IT RETURN EQ PUT CHARACTER FOR GOOD U1DP BTST BDTR D1 BEQ S 010 2 RN BTST 3 STS_1 A0 5 NE U1DP2 5 1 STS_1 A0 BEQ S NE RN MOVE B DO0O DAT 1 AO0 Y BRA S
5. Jumper 26 12 11 10 9 8 7 2132 1 2 3 4 5 6 12 11 10 9 8 7 2764 1 2 3 4 5 6 12 11 10 9 8 7 27128 1 2 3 4 5 6 12 11 10 9 8 7 27256 1 2 3 4 5 6 12 11 10 9 8 7 27512 1 2 3 4 5 6 P Default condition during manufacturing Location Diagram of the Jumperfield B26 Figure 4 1 3 Las 4 5 4 1 3 Access Timer Selection of EPROM Area 1 To nabl th the EPROM areas have use of fast and slow devices a selectable access time This jun Table 4 nperfield provides different jumper settings as listed in 2 25 Figure 4 2 2 shows the location diagram of th Speed selectors 4 1 4 The SYS68K CPU 6 contains is shown in Appendix 4 1 5 Ihe start address of the EPROM Area 1 decoding PAL capacity of th Table 4 Insertion of Devices into EPROM Area 1 D IP sockets Register 4 two 28 pin this manual The assignment D of Address Map of EPROM Area 1 is fixed mapped via a The size of the memory area depends on the memory used devices 1 2 types Table 4 lists the address map for the different usable device 1 2 Address Map of EPROM Area 1
6. VMEbus Board Setup This appendix summarizes the changes which have to be made to the default setup of additional VMEbus boards so that they are VMEPROM compatible Sections A 2 through A 5 are available EPROM but are not installed All drivers may be installed with the INSTALL command When INSTALL is entered followed by a question mark the information shown below will appear INSTALL cr THE FOLLOWING UARTS AND DISK DRIVERS ARE ALREADY IN EPROM UART TYPE 1 ONBOARD 6 ADR 85000 UART TYPE 2 FORCE SIO 1 2 ADR 85400 UART TYPE 3 FORCE ISIO 1 2 ADR 85800 DISK DRIVER FORCE 5 51 1 ADR 585 00 DISK DRIVER FORCE WFC 1 ADR 86400 By typing in INSTALL lt file gt lt address gt lt cr gt a specific driver may be loaded in the system The addressed file should be located in EPROM A 1 VMEbus Memory In general every FORCE memory board can be used together with VMEPROM The base address has to be set correctly in order to use the board within the tasking memory of VMEPROM The board base address of any additional memory must be set to be contiguous to the on board memory The start address is 100000 It is strongly recommended that only 16 bit memory boards are used because of speed considerations 2 SYS68K SIO 1 SIO 2 These two serial I O boards are
7. B24 1 2 B24 56 4 5 21 19 21 10 11 13 14 8 6 8 16 17 19 20 5 3 5 2 0 2 9 9 6 4 6 3 2 1 24 1 6 B24A 2 5 3 4 4 3 4 5 2 5 6 1 The Location Diagram of the PI T and the Jumperfields Figure 4 4 2 r3 t3 a Mg y a Jie L 4 54 4 4 3 PI T is able to force an interrupt to the CPU included timer allows the use Interrupt Handling of the multitasking software The general purpose 24 bit Figure 4 4 2 outlines the interrupt request timer with i as ts 5 bi This function a time base for location diagram of the PI T and the jumper field t prescaler can be used as an output for programmable frequencies with internal or external clocks as a watchdog and as a normal time base The interrupt request level of both interrupt signal lines is level 5 The interrupt autovectoring is used on the board Therefore th fixed interrupt vector number for the PI T is 429 The address 5000074 contains the start address of the interrupt handling routine Please refer to the PI T 68230 data sheet it includes all the programming de
8. Pin Assignment for EPROM Area 1 Upper Byte 27512 27256 27128 2764 2732 2732 2764 27128 27256 27512 16 VCC NC 28 Vcc NC X X X X X X X X NC 4113 21 NC VCC VCC A15 15 X X X X X A8 26 VCC A14 A14 A14 X X X X X A7 25 X X X X X X X X X X A6 24 A10 X X X X X X X X X X 5 23 A12 X X X X X X X X X X A4 22 OE X X X X X X X X X X A3 21 All X X X X X X X X X X A2 20 CE X X X X X X X X X X A 19 015 X X X X X X X X X X D8 18 D14 X X X X X X X X X X D9 17 013 X X X X X X X X X X 16 D12 X X X X X X X X X X GND 15 10111 X X X X X Pin Assignment for EPROM Area 2 SRAM Lower Byte 21 62256 6264 512 256 128 64 64 128 256 512 6264 62256 Batt Batt 15 16 28 X X X X X X X X X X X X 113 21 15 15 WE WE X X X X X X A8 26 1 14 14 14 52 14 X X X X X X 7 25 X X X X X X X X X X X X A6 24 10 X X X X X X X X X X X X 5 23 A12 X X X X X X X X X X X X A4 22 X X X X X X X X X X X X A3 21 11 X X X X X X X X X X X X A2 20 CE X X X X X X X X X X X X A 19 D7 X X X X X X X X X X X X DO 18 06 X X X X X X X X X X X X D1 1705 X X X X X X X X X X X X D2 16 D4 X X X X X X X X X X X X GND 15 D3 X X X X X X
9. CD CO I O boards 5 O 1 2 board or mixture of both every type must be set to the first base 9 and BP commands O 1 2 board which must be These can be either Please 0 1 board the base to be set to B00000 9600000 SYS68K WFC 1 Disk Controller drives together with the WFC 1 disk controller The floppy drives must be jumpered to drive select 3 and 4 an be accessed as disk number 0 and 1 out of VMEPROM talled automatically when a WFC 1 controller RESET when the simu to detect the hardware support 80 tracks side rate used is 3 ms The f is del front configuration The Winchester drives are not installed automatically loppy drives are insi tected by the CONFI G command or after panel switch of the CPU 6 Usable floppy drives must double sided and double density is set The step A 4 ester d can lated Ihe FRMT command must be used for VMEPROM for defining the following factors The physical drive structure i e number of heads number of cylinders drive select number etc The bad block of the Winchester drive partitions to used If this setup procedure is performed once for a particular drive the data is stored in the very first sector of the Winchester a
10. DEVICE 68230 Parallel Interface Timer Affected Affected by Address Mode by Reset Read Cycle Using 0 0001 R W bd N Port General Control Register PGCR 0 0003 R W Y N Port Service Request Register PSRR 0 0005 R W Y N Port A Data Direction Register PADDR 0 0007 R W Y N Port B Data Direction Register PBDDR 0 0009 R W Y N Port C Data Direction Register PCDDR 0 000 R W N Port Interrupt Vector Register PIVR 0 000 R W Y N Port A Control Register PACR OEOO00F R W Y N Port B Control Register PBCR 0 0011 R W N Port A Data Register PADR 0E0013 R W N Port B Data Register PBDR 0 0015 Port A Alternate Register PAAR 0 0017 Port Alternate Register PBAR 0 0019 R W N N Port C Data Register PCDR 0 001 R W N Port Status Register PSR 0 0021 R W Y N Timer Control Register TCR 0 0023 R W Y N Timer Interrupt Vector Register TVIR 68230 PI T Parallel Interface Timer cont Affected Affected by Address Mode by Reset Read Cycle Using 0 0027 R W Y N Counter Preload Register High CPRH 0E0029 R W N N Counter Preload Register Middle CPRM 0 002 R W N N Counter Preload Register Low CPRL 0 002 Count Register High CNTRH 0 0031 Count Register Middle
11. Cart D Yo Ili s Ip m sI m 5 dares 5 4 Single Level Bus Arbiter The SYS68K CPU 6 board contains a Single Level Bus Arbiter for multimaster environments The timing diagram of the on board single level bus arbiter is shown in Figure 5 4 1 Table 5 4 1 lists the time values In the default condition during manufacturing the board is configured to use the on board single level Bus Arbiter Table 5 4 1 Time Values of the Single Level Bus Arbiter a O O I eem sss 7 No Description Min Max ee 1 BR3 active to AS inactive 10 sex 2al AS high to BGOUTARBITER 25 557 EE SERRE INN NE Figure 5 4 1 Timing Diagram of the One Level Bus Arbiter BGOUT ARBITER AS LOCAL BBSY 5 5 VMEbus Release Functions If the SYS68K CPU 6 board has become bus master on the VMEbus then it must be able to release Bus Mastership under different conditions There are three conditions for releasing bus mastership A Timeout Counter Condition RAT B BCLR Signal of the VMEbus RBCLR C Release On Request ROR The influence of the conditions can be switched on and off via jumpers 5 5 1 Release On Request ROR The ROR mode limits the effect of the RAT function With t
12. Figure 5 3 5 Arbiter and Bus Request Level Jumper Selection on B13 with External Arbiter 5 1 Figure 5 3 6 Location Diagram of the Slave Bus ew dee WS Ga 5 1 Figure 5 5 1 Location Diagram of the RAT Jumperfield 5 23 Figure 5 6 2 Location Diagram of the Special Function Jumpers SR DS ap NAR WR USUS Figure 5 7 1 The Interrupt Acknowledge Daisy Chain 5 27 Figure 5 7 2 Functional Diagram of the Interrupt Acknowledge xL MEDIE Figure 5 7 3 The Interrupt Vector Acquisition Timing Diagram CA ce EV WS QE NL e Dow 1 Figure 5 7 4 The VMEbus Interrupt Hardware Diagram 5 Figure 5 7 5 Location Diagram of the VMEbus Interrupt Parts Figure 6 4 1 The Location Diagram of the Reset Signal 6 Figure 6 4 2 The Front Panel of the CPU 6 s 6 Tab Tabl Tab Tab Tab Tab Tab Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tab Tab Tab Tabl Tabl Tabl Tabl Tabl WW CPU Clock Freq 5 568 000000000000000000000 00000000 HE AAA D gt 444 444 494 bD p O1 CO CO CO CO CO O CO CO CO
13. This page was intentionally left blank Literature References Pleas refer to the following books for further detailed information 1 68000 Assembly Language Programming ISBN 0 931988 62 4 Osborne McGraw Hill 2 M68000 Familie Teil 1 Grundlagen und Architektur ISBN 3 921803 16 0 te wi Verlag 3 User s Manual of the 68881 including description of the instructions MC68881 UM AD 4 VMEbus Specifications 2618 5 Shannon Tempe Arizona 85282 602 966 5936 This page was intentionally left blank DEAR CUSTOMER APPENDIX J Product Error Report WHILE FORCE COMPUTERS HAS ACHIEVED A VERY HIGH STANDARD OF QUALITY IN OUR DUCTS AND DOCUMENTATION WE CONTINUALLY SEEK SUGGESTIONS FOR IMPROVEMENTS WE WOULD APPRECIATE ANY FEEDBACK YOU CARE TO OFFER PLEASE USE ATTACHE D DUCT ERROR REPORT FORM FOR YOUR COMMENTS PROJ AND RETURN IT TO ONE OF OUR FORCE COMPUTERS OFFICES SINCERELY FORCE COMPUTERS INTRODUCTION TO VMEPROM FOR USE WITH SYS68K CPU 6 1 Tab Tab Tab Tab Tabl Tabl GENERAL OVERVIEW gt El 2 4 General Info Features of TABLE OF CONTENTS rmation VMEPROM Power Up Sequence Front Panel Switches Switch The SYS68K CPU 6 25 gt 2 2 2
14. ud m M y Z D APPENDIX D Task Control Block Definitions The following are Task Control Block TCB definitions define define define define MAXARG MAXBP MAXNAM TMAX special sys defin define defin defin defin defin the 68020 regs are si defin defin defin defin defin defin defin defin defin defin defin defin 000000000000 defin define define define struct 000 100 Z Z 50 Z ZU 1AC 1 4 4 3B8 3BC 3BD gt gt 6 SOMEREG 0x0001 T DISP 0x0002 T SUB 0x0004 T ASUB 0x0008 T RANG 0x0010 REG IN 0x0020 VB SF DF CA CA PC SR US 55 5 DO REGS WO LW EG ch ch ch ch ch ch ch ch lo ch cha ar _ubuf 256 R AR CR TACK TACK TACK 25 TE RD ORD B ar ar mwb ar _mpb ar ar ar tsp ar kil ng sfp ar _svf 801 321 60 81 5081 max max max Max tem flags for VMEPROM display only 7 6 5 no regist trace gt 1 trace over subroutine set er display trace over subroutine active trace over range set
15. READ MODIFY WRITE CYCLE A DTB cycle that is used to both read from and write to a SLAVE location without permitting any other MASTER to access that location This cycle is most useful in multiprocessing systems where certain memory locations are used to control access to certain systems resources For example semaphore locations REQUESTER A functional module that resides on the same board as a MASTER or 6 INTERRUPT HANDLER requests use of the whenever its MASTER or INTERRUPT HANDLER needs it SERIAL CLOCK DRIVER A functional module that provides a periodic timing signal that synchronizes operation of the VMSbus Although the 1014 specification defines a SERIAL CLOCK DRIVER for use with the VMSbus and although it reserves two backplane signal lines for use by that bus the VMSbus protocol is completely independent of the 1014 SLAVE A functional module that detects DTB cycles initiated by a MASTER and when those cycles specify its participation transfers data between itself and the MASTER SLOT A position where a board can be inserted into a 1014 backplane If the 1014 system has both a 91 and J2 backplane or a combination 21 22 backplane each slot provides a pair of 96 pin connectors If the system has only a 91 backplane then each slot provides a single 96 pin connector SUBRACK A rigid framework that provide
16. This page was intentionally left blank INSTALLATION This page was intentionally left blank PLEASE READ THE COMPLETE INSTALLATION PROCEDURE BEFORE THE BOARI 5 INSTALLED IN A VMEBUS ENVIRONMENT TO AVOID MALFUNCTIONS AND COMPONENT DAMAGES This page was intentionally left blank 5 1 0 GENERAL OVERVIEW 1 Function Switch Positions 2 Connection of the Terminal 2 0 THE DEFAULT HARDWARE SETUP 2 1 The VMEbus Setup 2 2 The Local Setup 3 0 INSTALLATION IN THE RACK Co 1 Power On 3 2 Correct Operation 4 0 JUMPERS SETTINGS ON THE SYS68K CPU 6 4 1 System and User I O Jumpers 4 2 Jumper Location Diagram of the System and User Configuration Jumpers 4 3 VMEbus Configuration Jumpers 4 4 Jumper Location Diagram of the VMEbus Configuration Jumpers 4 5 Local Configuration Jumpers 4 6 Jumper Location Diagram of the Local Configuration Jumpers 5 0 WARNINGS LIST OF FIGURES Figure 1 1 The Front Panel of SYS68K CPU 6 4 3 4 4 4 5 4 6 This page was intentionally left blank 1 0 GENERAL OVERVIEW Easy installation of the SYS68K CPU 6 products is provided because the memory map the I O devices and their interfaces are configured to communicate to a standard terminal with RS232 interface The monitor VMEPROM boots up
17. of the FPCP The FPCP can be RESET by executing the following small program FPCP MOVE W 100 D0 MOVE W 50 5060380 LOOP SUBQ W 51 00 5 LOOP MOVE W 50 5060300 TURN RESET OFF END The RESET instruction of the 68000 68010 does not reset the FPCP in a proper way so that the software RESET has to be used has to be activated for at least 100us 4 7 7 Summary of the 68881 Coprocessor address 0E0200 Usable Data Bits DO 15 Supported Transfer Types Byte Word Reset Function Reset on write word to 0E0380 min 100us Reset off write word to 0E0300 4 8 Local Interrupt Handling The on board CPU is able to handle seven different priorit interrupt request levels The allows an unlimi CPU Interrupt priority levels are seven being the highest priori three bit mask which indica ted number of peripheral devices to interrupt ty tes tized interrupt daisy chain on the VMEbus t the numbered from one to seven leve The status register contains a the current priority of the processor Interrupts for al Interrupt requests arriving at the processor do not forc priority levels less than or equal to the current processor priority are ignored immediat exception processing Pending interrupts are detected between instruction executions If the
18. peuyepur sse2oy HOUS peuyepur s825y uous peuyepuf 4 5 ssa2oy piepue S Buipusosy pjepuels ssa2oy Auosiedns 1 Buipueosy Auosiedns 5 NOLLON 3 IA2I 2I2rIr2xrIA20rI2IJ0IJ0xxrI20rI30r23r23x KX 4 8 XZ k Z L 2 CIXI223xrIIIIJ2AJ12xXxIrIrIrz z 32xX rI ZIIIIIIIAJIIIIIIIIAJXIIIIIILIIcr TZTZTETIEXIIE I Js sd hd heh 0 L S SS3HQQOV 20 00 TIWWIO3QVX3H 5 2 1 Short I O Address Modifier Code To select a 64 Kbyte range out of the on board 68000 CPUs 16 Mbyte address space an address comparator 166 is used on the board This 64 Kbyte range is jumper selectable in the range from 100 000 to SFFFFFF The jumper field B23 is used to define the address range Figure 5 2 1 outlines the 4 decoder in detail For valid decoding OUT Table 5 2 2 lists address signals as the following jumper settings are possible means that the corresponding addr
19. 6 TEST 128 PROGRAM IS EXECUTED 1000 TIMES CAUTION THIS BENCHMARK NEEDS 128 KBYTE MEMORY BEN6BEG LEA L 8010 MOVE L 203A0000 D1 OPCODE FOR MOVE L 0 PC DO MOVE L 20000 4 D2 LENGTH IS 128 KBYTE 8004 MOVE L D1 A2 LOAD OPCODE TO MEMORY SUBQ L 1 D2 BNE S 004 MOVE W 54 75 A2 APPEND RTS PROGRAM IS NOW LOADED START 1000 TIMES MOVE L 1000 D3 8008 BSR S 8010 SUBQ L 1 D3 5 8008 RTS 8010 DG 0 PROGRAM WILL START BEN6END PAGE BENCH 7 FLOATING POINT 1 000 000 ADDITIONS not used on 68000 010 based systems BEN7BEG rts BEN7END BENCH 8 FLOATING POINT 1 000 000 SINUS BEN8BEG rts BEN8END PAGE BENCH 9 FLOATING POINT 1 000 000 MULTIPLICATIONS BEN9BEG RTS BEN9END page DOS BENCHMARK 1 CONTEXT SWITCHES BEN10BEG MOVE L 100000 6 8000 XSWP CONTEXT SWITCH SUBQ L 1 D6 DONE BGT S 000 SN RTS PAGE BENLOEND DOS BENCHMARK 42 EVENT SET 11 MOVEQ L 32 D1 SELECT EVENT 32 M
20. of the Jumperfield B26 of the EPROM Area 2 of the Speed Selectors Drawing of the Baud Rate Selection arts d Location Diagram best case Diagram worst case Diagram of the Terminal Por Diagram of the Terminal Por Diagram of the Remote Port Diagram of the Remote Port tion with a Host Computer Interfacing to Host Computer in the ct ct ming Diagram Cycle Timing Diagram Hardware Location The Hardware The Location RTC Write Cycle Ti RTC Read The Location The Global Refresh Data Format S Register Model of Th Ti e G nterru ming AHA AHA AHA AH SA Location Read Cycle Foll Write Cycle Fol The Short Location The Bus Grand G 1 Diagram of the Access Cycle without Refresh Request Timing Diagram ummary of the 68881 the 68881 pt Vector on Diagram of BERR Cycle Diagram of the BERR Jumperfield owed by Write Cycle lowed by Read Comparator 2 23 cats Diagram of the Short Parts Daisy Chain 01 O1 Arbitration Timing Bus Arbitration Timing Diagram The Jumperfield for the Bus Arbitration OY 4 CO UW List of Fiqures cont d
21. 3 9 2 20 1 Location Diagram of the Terminal Port Figure 4 3 7 quw E AIC n Ce TRO LE 1 BE AS 0 1 g L PED A RJ 4 3 3 2 Register Layout Device 6850 Terminal Address Mode Description 0C0080 R Status Register 0C0080 W Control Register 0C0082 R Receive Data Register 0C0082 W Transmit Data Register 4 3 3 3 Baud Rate Selection Please see chapter 4 3 1 The Baud Rate Selection 4 3 3 4 Terminal Port Summary Start Address End Address Access Mode Usable Data Bits Access Time Interrupt Interrupt Request Level Handling 50 0080 0C0082 Byte Only Read and Write D8 100 200 4 D15 Ons min Ons max fixed IRQ vector 28 5000070 4 3 4 Remote Port second RS232 compatibl interface is the Remo The hardware drawing is shown in Figure 4 3 8 a diagram of the interface parts is outlined in Fig te Interfac nd the location ure 4 3 9 The Remote Interface can interrupt the 68000 CPU on level 3 forced interrupt vector is the autovector 27 50 4 3 4 1 The I O Signal Assignment 00006C Further details of control function
22. E MASTER incoming signal is guarani that teed this timing transitions the SLAVE will the SLAVE changes its the level of its outgoing signal not change outgoing tween two of edge from the the signal its Figure 5 1 1 Cycle Followed by Write Cycle READ ware hil AD1 A221 AMD AM M V sA AS 20 wan We WI DS A 2 0 20V 20 OUTPUTS FROM MASTER Table 5 1 2 Write Cycle followed by Read Cycle E The MASTER incomingsignal transit is guaranteed this timing bel ions tween two of NOTE NUMBER PARAMETER MIN MAX NOTES 1 Axx and AMx valid and IACK high 35 B to AS low 2 DTACK low to invalid address or 0 IACK low 3 AS high 40 B 4 DTACK low to AS high 0 5 AS to DS A skew 0 6 WRITE valid to DS A low 35 B 7 DS B high to invalid WRITE 10 B 8 Data release to DS A low 0 B 9 DS A to DS B skew 10 B 10 DTACK low to DS A high 0 b 11 DS A high 40 B 12 DS B high to DS A low 40 B 13 DTACK BERR high to DS A low 0 C 14 DTACK low to DS B high 0 1 5 DS A high to invalid data 0 D 16 DS B high 40 B
23. no register initialization if set unsigned char unsigned int unsigned long tored in the following order DO D7 0 6 256 byte user buffer argument count of the cmd line 10 breakpoints 5 names in name buffer number of tasks d id s ud during id i 57 ud 80 byte monitor command line buffer 32 byte monitor parameter buffer monitor parameter buffer character out buffer system work buffer task pdos stack task stack pointer kill self pointer RESERVED FOR INTERNAL PDOS USE save flag 68881 support 881 RESERVED FOR INTERNAL PDOS USE D Task Control Block Definitions cont d 3BE long trp 16 user TRAP vectors piri 3FE long _zdv zero divide trap 402 long chk CHCK instruction trap TUS 406 long trv TRAPV Instruction trap m A0A long trc trace vector 4A0E long fpa 2 floating point accumulator 416 long fpe fp error processor address 41A char clp command line pointer 41E char _bum beginning of user memory 422 char eum end user memory 426 char ead entry address 42A char imp internal memory po
24. Default Jumper Interrupt Jumper 15 Request Level Setting 8 7 7 IRQ6 IN 5 IRQ4 IN IRQ3 IN IRQ2 IN IRQ1 IN 14 1 Note In the default conditions all IRQ signals from the VMEbus will be acknowledged by the on board CPU By default all jumpers are installed Figure 5 7 5 Location Diagram of the VMEbus Interrupt Parts ERE sie Ema TH ae Cape 19 VE B x B ER 5 7 3 The ABORT Function Switch The second switch on the front panel of the SYS68K CPU 6 is used to generate a nonmaskable int This interrupt forces the au terrupt at level 7 to the 680x0 CPU tointerrupt vector 31 The switch can be used for debugging purposes please refer to the or for selftests if special routines are Software User s Manual built in 5 8 Summary of the VMEbus Interface Data Transfer Modes A24 D16 D8 VMEbus A24 A16 Start Address 100 000 FFO 000 End Address FEF FFF FFF FEF Interrupt Handler Arbitration Specials Any 1 to 7 stat Single level bus arbiter SYSCLK driver Bus Requester level 0 to 3 stat Power Monitor 6 0 THE RESET STRUCTURE There is a SYSRESET driver installed on t
25. Start End Used Total Address Address Device Capacity 080 008 083 FFF 2764 16K Byte 080 008 087 FFF 27128 32K Byte 080 008 O8F FFF 27256 64K Byte 080 008 09F FFF 27512 128K Byte 4 1 6 Summary of EPROM Area 1 Start Address 080008 End Address S09FFFF Boundary 020000 Boot Address 000000 to 000007 Access Modes Byte or Word Read Only accesses supported Default Access Time 250ns max 4 2 The EPROM Area 2 For user application programs or as a static RAM area two 28 pin Sockets are provided on the board 4 2 1 Memory Organization of EPROM Area 2 The chip selection for the upper D8 D15 and the lower socket 00 07 on the board is organized by byte This allows byte manipulation if SRAM chips are installed Figure 4 2 1 shows the location diagram of the user area and the jumper configuration area This jumper configuration area defines which address control signals are connected to the socket pairs 4 2 2 Usable Device Types The following device types are usable in User Area 2 Device Organization Capacity EPROM 2764 8K 8 16 Kbytes total EPROM 27128 16K 8 32 Kbytes total EPROM 27256 32K 8 64 Kbytes total EPROM 27512 64K 8 128 Kbytes total SRAM 6264 8K 8 16 Kbytes total SRAM 62256 32K 8 64 Kbytes total Table 4 2 1 describes the jumper settings required for the different devices This page was
26. 15 60 03C SD Uninitialized Interrupt Vector 16 23 64 04C SD Unassigned reserved 95 24 96 060 SD Spurious Interrupt 25 100 064 SD Level 1 Interrupt Autovector 26 104 068 SD Level 2 Interrupt Autovector 21 108 06C SD Level 3 Interrupt Autovector cont d Vector Address 5 Dec Hex Space Assignment 28 112 070 SD Level 4 Interrupt Autovector 29 116 074 SD Level 5 Interrupt Autovector 30 120 078 SD Level 6 Interrupt Autovector 31 124 07C SD Level 7 Interrupt Autovector 32 47 128 080 SD TRAP Instruction Vectors 191 OBF 48 63 192 0CO SD Unassigned reserved 255 OFF 64 255 256 100 SD User Interrupt Vectors 1023 3FF Vector numbers 12 13 14 16 through 23 and 48 through 63 are reserved for future enhancements should be assigned these numbers 3 5 The memory map of SYS68K CPU 6 is outlined in Tab All memory anq Processor 6VA if an access to the not insta areas are The Address Map of SYS68K CPU 6 35 1 No user peripheral devices identical for all SYS68K CPU 6 products except for the memory map of the Floating Point Co To detect the end of the onboard addresses 80000 to 80007 are not occur decoded bus error will be generated on SYS68K CPU 6A Lled FPCP is initiated DRAM area via software 6V and the and a bus error will Table 3 5
27. BB BC BD BE CO C1 C2 C3 4 C8 DO D6 E6 F2 F6 FB FC 100 11C 158 198 ODD int long tics unsigned char unsigned char unsigned char unsigned char unsigned char char char char char char char char char char char _ long char char LNE int char char char char char char char char char char char int long _ long E unsigned char patb 1 _brkf 1 _f8bt _utyp 1l urat 1 evtb 1 _evtil evts lt N 000000 evtm ct _ char 6 char iler 6 char 16 char char char char char char char long int char char long wind wadr chin chot iord begn 1 14 Opip i uart 1 OY Ne lt 5 6 cont d smon _syrs 2 Shrs smin lt Ne gt gt gt LS 1 2 lt
28. Memory Layoul On board I O On board Int Off board In 4 1 4 2 54 9 Contr 4 4 Defaul 4 5 Defaul Switch ol Switches t EPROM Usage of VMEPROM Devices errupt Sources terrupt Sources THE CONCEPT OF VMEPROM 342 Getting Star Command Line VMEPROM Comm ted Syntax ands SPECIAL VMEPROM COMMANDS FOR CPU 6 4 1 4 2 4 3 CONFIG Sea FUNCTIONAL SELFTEST P rch VMEbus for Hardware Perform Functional Tes erform On board Selftes ct ct RESTRICTIONS ON STANDARD COMMANDS Diwali Baud Port RAM Disk U Program Af Default Co On board On board Off board List of Tables sage ter Reset ntrol Switch Setting I O Devices Interrupt Sources Interrupt Sources t Memory Usage of VMEPROM 2 2 2 2 2 2 1 GENERAL OVERVIEW 1 1 General Information The SYS68K CPU 6 operates under the control of VMEPROM an EPROM resident real time multiuser multitasking monitor program VMEPROM provides the user with a powerful debugging tool for single and multitasking real time applications for the high performance SYS68K CPU 6 board The 68881 Floating Point Coprocessor is not supported by VMEPROM This manual describes those parts of VMEPROM which are specific for the hardware of the CPU 6 All general commands and system calls a
29. User Alterable Memory Locations 88000 88016 8802E 88036 DS DS DS DS DS DS DS DS DS B 22 Name and disk of the startup file There must be a zero terminated string Ihe default value SYSSTRT 2 These are three entries for default RAM disk defaults to address 5800000 second to 700000 and the third to is the The first entry the A0000 Th ntries ar DC W Disk number DC W Number of 256 byte sectors DC L Start address This is the default of a RAM disk if it is initialized by the system string These four entries contain address which is jumpered to initialization of the kernel first long word holds 8000 default the second holds af 00 address of the 005 booter EPROM the third is A0000 an d It must be a zero terminated th te Th b th i th 05 0 40on0 last one is the start address of VMEPROM Generation of Applications EPROM H1 General Information In general there are four ways to bind an application program in EPROMs to the VMEPROM kernel In all cases the application program is executed in user mode Ihe XSUP system call can be used to switch to supervisor mode The first two ways keep the original EPROMs of VMEPROM The application can be put into the User EPROM Area of the CPU 6 board or the applicatio
30. XO XO CO CO CO CO CO DP BW O1 O1 O OO O1 CO NN I AC List of Tables A Timing A Timing EPROM Area 1 J Address Map of EPROM Area 2 J EPROM Area 2 J EPROM Speed Selection Address Map of EPROM Area 2 The Baud Rate Selection Jumper B7 ACI 95 es 0 6 mper Settings EPROM Area 1 mper Set mper Set best case worst case Terminal Connector Signal Assignments De Re De Ho De Th De RT RT Ti fault Jum mote Conn fault Jum st fault J e PI T fault Ju C Write C Read me Val ue per Set ector Sign per Set Signal Assignments umper Set Address Map mper Set Register Model of Time Val Time Val S Refresh Request 5 Acknowledge Terei Code Th Th The On Board Th BE BE BE BE Re Th Th Ju Ti Ac Th e In e In terru toint umper umper umper umper e Au RR RR RR RR G agg ad Cycle foll Write Cycle fol f ting at B3 al Assignments tings at Bl at B5 tings tings the ues ues an or Access Vector Conversion Devices upt Vector Table Interrupt Scheme tings A tings B tings
31. y b 1 mu 11 89 vem d Hi 1 PBo a F38 1 iOi CC 24 L 2 3 war Ec 2 4 DER AUR REC MM b gt ISS P2e 134 2254 7 e te HHHH P ot gt es a HH 4 4 1 PI T Register Layout and Addressing All of the PI T registers directly addressable read writeable as shown in Table 4 4 1 The base address is 0E0000 Only single byte transfers to from the PI T on the data bits D0 D7 are allowed odd addresses The absolute access address of the first register under the default conditions during manufacturing is 50 0001 Caution Interrupt Vector Number Registers PIVR address 0E000B and TVIR address 0E0023 are programmable but no interrupt vector can be forced because of the auto interrupt vectoring The PI T is used as an internal control device for steering and controlling of the local functions 4 4 2 Timer Ihe TIMER INTERRUPT function is performed by the timer module of the PI T device This independent part of the PI T contains a 24 bit wide counter and a 5 bit prescaler The timer may generate periodic interrupts or a single int
32. 17 Dxx valid to DTACK low 25 E 18 Data released to DTACK BERR 0 E high 19 DS B high to DTACK BERR high 30 B NOTES A 11 times given in nanoseconds B The MASTER must guarantee this timing between two of its outgoing signal transitions C The MASTER must wait for the incoming signal edge from the SLAVE before changing the level of its outgoing signal D This is a guarantee that the SLAVE will not change the incoming signal until the MASTER changes its outgoing signal its Figure 5 1 2 Write Cycle Followed by Read Cycle WRITE READ AEAD NU JU WE 20 Ay OUTPUTS FROM MASTER 5 5 E 000 031 Ww E 9 id T T ig A 2 10 e adi z 20 20 19 4 DTACK BERR 20 08V This page was intentionally left blank 5 2 Address Modifier Implementation The 68000 CPU contains three function code signals which indicate the state of the processor USER or SUPERVISOR mode and the cycle type currently being executed PROGRAM or DATA access The next table lists all the states and types of the 680 0 CPU The CPU Function Codes FC2 ECI CYCLE TYPE LOW LOW LOW Reserved LOW LOW HIGH User Data LOW HIGH LOW User Program LOW HIGH HIGH Reserved HIGH LOW LOW Reserved HIGH LOW HIGH Supervisor Data HIGH HIGH LOW Supervisor Program HIGH
33. 68B50 ACIA 5 28 000070 Terminal 68B50 ACIA 3 21 00006C Remote 68B50 ACIA 2 26 000068 Host 4 9 The BERR Generator To provide an error function if a device or memory on the bus has not responded within a maximum time a time out counter is used on the board This time out counter generates a Bus Error Signal BERR after a user supplied time limit up to 15ms The CPU aborts the current cycle if the BERR signal has been recognized and forces the exception routine Figure 4 8 1 shows the detailed diagram of an access cycle aborted via BERR with the default set values Table 4 9 1 lists the usable time out values and the equivalent jumper settings Figure 4 9 2 outlines the location diagram of the jumperfields If the board is the current VMEbus master and an external VMEbus card generates a BERR then the cycle will be aborted in the same way For example an external BERR signal can be generated by a dynamic memory card by using an Error Detection and Correction Logic EDC and detection of a non correctable data pattern Figure AS BERR 4 9 1 Timing Diagram of a BERR Cycle Table 4 9 1 BERR Jumper Settings B33 3 25 13 2 0 1 7 4 1 B34 3 2 1 Time Out Min 24ms Default setting during manufacturin
34. B13 Bus Request 2 S cup 5721 Bus Grant 4 27 5 5 6 25 BCLR Poo 24 8 9 10 21 11 20 13 18 14 17 15 Bus IRQ enable 1 14 4 D1 5 32 2 13 eA 4 11 5 e 10 6 9 7 8 B23 Short I O Address 5 9 Modifier G oo Es OE Jumper Location Diagram of the VMEbus Configuration Jumpers E 5 Local Confiquration Jumpers Jumper Description Default Schematics See field Page B25 Error Timer 7 10 qom 4 83 11 14 B33 Error Timer 2 7 D3 B34 Error Timer 25 Bus Mastership Timer 5 8 dt em 5 21 B31 2 3 7 D2 B32 B8 Clock Selectors 2 2 Al 9 2 2 E B10 8MHz 2 3 2 A2 Su 4 5 B10 12 5MHz 1 2 5 6 11 EPROM Access Time 1 8 2 4 4 14 Selection 4 5 B26 EPROM Size Selection 12 8 CS 4 2 10 11 4 9 7 8 27 1 12 8 4 8 10 11 4 9 6 7 21 DTACK Generated 8MHz 1 5 6 C2 3 1 for RAM 12 5MHz 4 5 16 Battery STDBY 4 4 56 B35 Read Modify Write 3 A2 Jumper Location Diagram of the Local Configuration Jumpers e Pea Bc This page was intentionally left blank Circuit Schematics of the SYS68K CPU 6 This page was intentionally left blank Connector PIN Assignment of the SYS68K CPU 6 P1 Connector Pin Assi
35. DFOOOC4E750E 444452C2 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XX 0200XX 14 52 S9030000FC RC 0000 03 S9 Check sum 24 bit Address Count Record Type Check sum Dat Count System RAM Definitions SYRAM H DEFINIT ON OF SYRAM BLOCK OF MEMORY 05 Jan 88 Revised to correspond to PDOS 3 3 BRIAN C COOPER EYRING RESEARCH INSTITUTE INC Copyright 1985 1988 last update 23 Feb 88 identical to MSYRAM SR i define NT 64 number of tasks TI define NM NT 3 amp 0 number of task messages define NP 16 number of task message pointers m define ND NT 3 amp 0 number of delay events define NC 8 number of active channel buffers define NF 64 number of file slots 522 define NU 1 5 number of I O UART ports define IZ 6 input buffer size 2 P2P define MZ 0x1000000 maximum memory size 16M maximum define TZ 64 task message siz define NT define define NTP define NCB NC define NFS NF define NEV ND define NIE ND 2 define 5 NU 1 define P2P IZ define MMZ 7 define TMZ TZ define OxFF gt gt 8 P2P input b
36. INTERRUPT HANDLER A functional module that detects interrupt requests generated by INTERRUPTERS and responds to those requests by asking for STATUS ID information LOCATION MONITOR A functional module that monitors data transfers over the DTB in order to detect accesses to the locations it has been assigned to watch When an access occurs to one of these assigned locations the LOCATION MONITOR generates an on board signal MASTER A functional module that initiates DTB cycles in order to transfer data between itself and a SLAVE module OBO A SLAVE that sends and receives data eight bits at a time over D00 D07 POWER MONITOR MODULE A functional module that monitors the status of the primary power source to the 1014 system and signals when that power has strayed outside the limits required for reliable system operation Since most systems are powered by an AC source the power monitor is typically designed to detect drop out or brown out conditions on AC lines READ CYCLE A DTB cycle used to transfer 1 2 or 4 bytes from a SLAVE to a MASTER The cycle begins when the MASTER broadcasts and address and an address modifier Each SLAVE captures this address and address modifier and checks to see of it is to respond to the cycle If So it retrieves the data from its internal storage places it on the data bus and acknowledges the transfer Then the MASTER terminates the cycle
37. call when th e RESET button was pressed th be destroyed t panel causes all programs to I O devices t overwrites the first word in T system If breakpoints were defined and a user program was running e user program could possibly Pressing reset while a program is running should only be used as a last re failed sort when all other actions s uch as pressing C twice have 1 4 2 ABORT Switch ABORT switch is defined by VMEPROM to cause level 7 interrupt This interrupt cannot be disabled and is therefore th appropriate way to terminate a user program and return to the command level of VMEPROM If ABORT is pressed while a user program is under execution all user registers are saved at the current location of the program counter and the message Aborted Task is displayed along with the contents of the processor register If ABORT is pressed while a built in command is executed or the command interpreter is waiting for input only the message is displayed and control is transferred to the command interpreter The processor registers are not modified and are not displayed in this case 1 4 3 Control Switches There are no control switches on the front panel of the CPU 6 however at address location 8 in EPROM one byte is reserved to simulate the control switches These switches as simulated in the byte in EPROM define the default behavior and actions o
38. is driven of the IRQs is wired to slot one of the VME daisy chain ZZ Mid NI32 LZ Z Nid 5 27 Figure 5 7 1 Interrupt Acknowledge Daisy Chain Figure 5 7 2 Functional Diagram of the Interrupt Acknowledge Daisy Chain Scheme SLOT 1 SLOT X SLOT X 1 SLOT X42 INTERRUPT INTERRUPT INTERRUPT CONTROL CONTROL CONTROL LOGIC LOGIC LOGIC ACK This page was intentionally left blank Table 5 7 1 Time Values of the Interrupt Vector Acquisition NOTE NUMBER PARAMETER MIN MAX NOTES 1 Axx valid and IACK low to 35 B AS low 2 DTACK low to invalid address or 0 C IACK high 3 AS high 40 B 4 DTACK low to AS high 0 G 5 AS to DSO skew 0 6 WRITE valid to 50 low 35 B 7 DS0 high to invalid WRITE 10 B 8 Data release to DTACK high 0 E 9 Dxx valid to DTACK low 25 E 10 DTACK low to DSO high 0 1 DS0 high 40 B 12 DSO high to invalid data 0 D 13 DTACK high to DSO low 0 14 DS0 high to AS low 30 B NOTES A All times given in nanoseconds B Ihe INTERRUPT HANDLER must guarantee this timing between two of its outgoing signal transitions 55 INTERRUPT HANDLER must wait for the incoming signal edge from the INTERRUPTER before changing the level of its outgo
39. 1 2 B23 7 1 4 B3 1 4 2 24 7 4 E 2 B5 1 D1 E 2 B24A 7 3 2 B7 3 2 B25 7 C3 E 6 B8 2 1 6 B26 8 C3 E 6 B9 2 E 6 B27 8 D3 E 6 B10 2 2 6 B31 7 D2 E 6 B11 2 4 6 32 7 D2 E 6 B13 3 D1 4 B33 7 03 6 14 4 B3 4 B34 7 03 6 B15 4 1 4 B35 3 A2 E 6 B16 4 A4 E 6 B36 4 2 4 21 6 2 6 B37 4 1 4 System and User Jumpers Jumper Description Default Schematics See field Page B1 Serial I O Interface 2 19 1 4 31 configuration for remote 3 18 4 17 5 16 7 8 10 11 6 13 B3 Serial I O Interface 2 19 1 4 24 configuration for 3 18 terminal 4 17 5 16 7 8 10 11 6 13 5 Serial I O Interface 2 15 1 D1 4 38 configuration for host 3 14 4 13 c2 7 10 8 9 B7 Baud Rate Control 1 20 L gt DS 4 17 3 18 5 16 eT 24 Parallel Interface I 52 7 4 4 47 3 6 Am 7 8 10 11 13 e 16 17 19 20 24 Parallel Interface 1 6 ha 4 47 m5 dod Jumper Location Diagram of the System and User I O Configuration Jumpers VMEbus Configuration Jumpers Jumper Description Default Schematics See field Page 14 Reset Generator mE 4 B3 6 1 B36 4 A2 B37 4 2 B300 je 52 4 B2
40. 800000 SW ON Execute file SYSSTRT on disk 2 after RESET OFF No startup file is executed OFF Switch 7 has no effect if SW5 and SW6 are not set to OFF SW8 ON Hardware configuration on VMEbus is checked controllers are installed as they are found OFF The VMEbus is not checked for additional OFF hardware 1 4 4 Default Memory Usage of VMEPROM By default VMEPROM uses the following memory assignment on CPU 6 Memory Layout of the On board RAM 00000 Vector Storage of the 68000 68010 00400 System Configuration Data 00800 General Purpose RAM Reserved for System Commands 01000 Kernel System 07000 Task Control Block for First Task 08000 User Memory 7 800 Mail Array 80000 Note that VMEPROM only clears the memory from 0 to 8000 after reset Additionally after a reset has been made the location at 8000 is overwritten with an XEXT system call to avoid a System crash because no program was loaded The CONFIG command can be used to install additional memory It searches from address 100000 until a bus error occurs Please note that the size of the first task can not be extended beyond the address 580000 this would overwrite the Mail Array However the additional memory which can be installed may be used for data arrays or for creating new tasks The maximum memory which may be used for tasking is 16 Mbytes If more m
41. BLOCK WRITE CYCLE A DTB cycle used to transfer a block of 1 to 256 bytes from a MASTER to a SLAVE The block write cycle is very similar to the block read cycle It uses a string of 1 2 or 4 byte data transfers and the MASTER does not release the DTB until all of the bytes have been transferred differs from a string of write cycles in that the MASTER broadcasts only one address and address modifier at the beginning of the cycle Then the SLAVE increments this address on each transfer so that the next transfer is stored on the next higher location BOARD A printed circuit PC board its collection or electronic components and either one or two 96 pin connectors that can be plugged into 1014 backplane connectors BUS TIMER A functional module that measures how long each data transfer takes on the DTB and terminates the DTB cycle if a transfer takes too long If the MASTER tries to transfer data to or from a nonexistent SLAVE location it might wait forever The BUS TIMER prevents this by terminating the cycle 008 0 A SLAVE that sends and receives data eight bits at a time over D00 D07 Or INTERRUPT HANDLER that receives eight bit STATUS IDs over DOO DO7 or an INTERRUPTER that sends eight bit STATUS IDs over 00 07
42. BUILD A 6850 COMMAND REG D1 B 8D S OUT CMD B Ih08 P001 SAVE IN PSLEDB X 7654 3210 U1CMD MOVEM L 1 2 A7 8D S MOVEQ L 510 2 D2 0 0001 0000 LSR B 4 D1 D1 8 0000 FHPI ROXL B 1 D2 D2 0 0010 0008 LSL B 7 D1 D1 P I000 0000 ROXL B 4 D2 D2 0008 POOL TOT B D1 ENABLE INTS BMI S 8010 N LEAVE DISABLED TAS B D2 Y SET UPPER BIT OF CMD B 8010 MOVE B D2 PSLEDB SAVE IN LOW MEMORY MOVEM L A7 D1 D2 WORKING RTS Ck k k CK k lt k lt CK k k k k k lt lt lt k k x k lt k k k k k k k k k S k k k lt k k k lt k lt X X X lt CHECK FOR VALID BASE ADDRESS U1DC MOVE L 1 7 SAVE Al LEA L 1 01 00 TST W A1 DONE BEQ S U1DCO4 Y SET POP OUT CMPA L 1 0 VALID BNE S U1DCOO GN MOVE W 20000 7 Y ALLOW LAST CHAR TO CLEAR 0108602 SUBO W 1 A7 LOOP BNE S U1DCO2 MOVE B 503 1 A0 ISSUE RESET TO THE Ul DC03 1DC04 IR MOVE W SUBQ W BNE S ADDQ W MOVEA L RTS MOVEA L ADDQ W CLR W RTR CMP B RTS 2 1 01 2 A7 A7 4 0000 A7 A7 DC03 7 7 SCE DO 50 WAIT FOR AWHI WAIT FOR RESET POP COUNTER RETURN LE POP
43. Baud Rate Selection 4 3 5 4 Host Port Summary Start Address 0C0041 End Address 50 0043 Access Mode Odd Byte Only Read and Write Usable Data Bits DO D7 Access Time 1000ns min 2000ns max Interrupt Request Level 2 Interrupt Handling fixed IRQ vector 26 Address 000068 4 4 Parallel Interface and Timer Chip The Parallel Int erface and Timer module PI T 68230 is used on the board to provide powerful asynchronous parallel I O on the SYS68K CPU 6 board Easy access to the PI T is provided by the asynchronous bus structure and the nonmultiplexed data address bus This allows effective communication to the PI T Features of the PI T 68230 Port Modes include Bit I O Unidirectional 8 Bit and 16 Bit Bidirectional 8 Bit and 16 Bit Selectable Handshaking Options 24 Bit Programmable Timer with 5 Bit Prescaler Software Programmable Timer Modes 2 Selectable Interrupt Sources Registers are readable and writeable 11 registers are directly addressable The detailed hardware connection of the PI T is outlined in Figure 4 4 1 Figure 4 4 1 Hardware Diagram of the a 464 n 68230 9 2 89 k H z 358 5 9 pe I
44. Cache control register long cnt execution count BYTE nokill kill tasks with no input port BYTE mask unit mask for echo WORD sysflg system flags used by VMEPROM Ef bit 0 display registers short form bit 1 trace without reg display bit 2 trace over subroutine bit 3 trace over subroutine active bit 4 trace over range T LWORD t range 2 start stop PC for trace over range LWORD ex regs pointer to area for saved regs BYTE sparend 0x1000 0xFD8 make tcb size 1000 bytes char tbe 0 task beginning Interrupt Vector Table of VMEPROM Vector Vector Number s HEX Assignment 0 000 Reset Initial Supervisor Stack Pointer 1 004 Reset Initial Program Counter 2 008 Bus Error 3 00C Address Error 4 010 Illegal Instruction 5 014 Zero Divide 6 018 CHK CHK2 Instruction 7 01 CpTRAPcc TRAPcc TRAPV Instructions 8 020 Privilege Violation 9 024 Trace 10 028 VMEPROM System Calls 02C Coprocessor Instructions 12 030 Unassigned Reserved 13 034 Coprocessor Protocol Violation 14 038 Format Error 15 03C Uninitialized Interrupt 16 040 r THROUGH P Unassigned Reserved 23 05C 24 060 Spurious Interrupt 25 064 Level 1 Interrupt Auto Vector 26 068 Level 2 Int
45. DTACK signal to the CPU by an access to from the 4 5 3 Battery Backup Mode A lithium battery is included in the shipment This battery is not soldered onto the board because of the use of aluminium foil for packing during shipping The location diagram of the position of the battery is outlined in Figure 4 5 3 Table 4 5 1 Register Model of the Default Board Base Address 0C0401 Default Register Reset Label Description Address Offset Value HEX 0C0401 01 5 Counter ten thousands of secs 0C0403 03 RTCCHTS Counter hundredths tenths of secs 0C0405 05 RTCCSEC Counter seconds 0C0407 07 Counter minutes 0C0409 09 RTCCHRS Counter hours OCO40B OB RTCCDOW Counter day of week OCO40D OD RTCCDOM Counter day of month OCO40F OF RTCCMON Counter month 0C0411 11 5 RAM ten thousandths of secs 0C0413 13 RTCRHTS RAM hundredths tenths of secs 0C0415 15 RTCRSEC RAM seconds 0C0417 17 RTCRMIN RAM minutes 0C0419 19 RTCRHRS RAM hours 0 041 RTCRDOW RAM day of week 0 041 1D RTCRDOM RAM day of month OCO41F 1F RTCRMON RAM month 0C0421 21 RICLSR Interrupt Status Register 0C0423 23 Interrupt Control Register 0C0425 25 RTCCRES Counters
46. G 4 gt g H 5 a m Cy E C T m H 8 5 b u 1015 1015 8 Nid 110298 6 Nid 110198 110099 5 Nid 8 1015 98 l Mid Nid Mil D8 9 Nid zMIODS tf OQ O O O O O O L 10715 9313 LL L um P Figure 5 3 2 Global DTB Arbitration Timing MASTER USING MASTER USING AS BBSY MASTER MASTER B DTB GRANTED TU MASTER B ARBITRATIO MASTER USING MASTER BUSING en 2 AS MASTER BEST MASTER GRANTED MASTER B 5 3 2 The On Board DTB Slave Bus Arbitration A full DTB slave arbitration is provided on the board to allow the usage of the SYS68K CPU 6 in multimaster and multiprocessor environments The board control logic generates a Bus Request BRx on a selectabl level 0 3 if an off board transfer is initiated and the board is not the current DTB master After a received BGXIN signal at the equivalent level the control logic drives the BBSY signal low to inform the Bus Arbiter that the arbitration is completed and releases its Bus Request signal Figures 5 3 4 and 5 3 5 outline the BRx BGxIN and BGxOUT jumper fields and Figure 5 3 6 shows the location diagram Ihe Bus Request level and the Bus Grant level m
47. KOK OK KOK OR KO KOR kk 470 char linebuf 82 command line buffer fs char linebuf 82 7 elternate line buffer a 514 char cmdline 82 alt rnate cmdline for XGNP 5667 int allargs gotargs argc save and count for XGNP Rf 56A int argc argument counter SE ate Pura char argv MAXARG pointer to arguments of the cmd line 594 char redirection args fren line 7 iat lport oport I O port assignments kr 5A0 char Laan holds pointer to line in _mwb ET 5A4 LWORD offset base memory pointer D 5A8 5 5E6 654 668 SCR 680 684 FOSE 769197 7 6592 7 6BA IRTEE 784 4 L TFG 7F8 ERIE CRY BE8 F0A F6A F6EFE LRETZ k76 2 4 6 FCO EC4 WFCA FCC FDA FD8 Task Control Block Definitions cont d int bpcnt num of defined breakpoints LWORD bpadr MAXBP breakpoint address f WORD bpinst MAXBP breakpoint instruction char 11 breakpoint command T int bpocc MAXBP 4 of times t
48. Remote Port Summary Start Address 50 0101 End Address 0C0103 Access Mode Byte Only Read and Write Usable Data Bits DO D7 Access Time 1000ns min 2000ns max Interrupt Request Level 3 Interrupt Handling fixed IRQ vector 27 Address 00006C 4 3 5 Host Port third on board RS232 C with a host computer 4 3 10 A standard communication method to communicate between a terminal host nector sparent a When P4 and Mode con Tran tran host the Figu Transmit Data Line TXD Receive Data Line RXD board polls the terminal AC When the user types in recognizes it stops from the terminal to monitor program The Sequence tha SYS68K CPU 6 board If the a conn connected devic The baud rate of each module interface The baud rate of the host A detailed description of Dump Load DU LO commands The Host Interface can interrupt forced interrupt vector is the au canno interface can be used in conjunction the computer and no correction or m te AC Transparent Mode handling does n The detailed schematic compu In a configuration like the one shown re 4 3 11 both computers are con from the back to the IA regist the valid stop character sequence the transmission of the following characters the host computer ter Transparent Mode smitted charac
49. Sequence locations initial stack pointer 0 and 4 These f the system EPROM area They defined start after reset or LOS modules to perform invoked as the first task the CPU 6 Next the terface of VMEPROM is If a terminal is connected to the terminal port of the CPU 6 the VMEPROM banner along with the VMEPROM prompt will be displayed upon power up or reset The default terminal port setup is as follows Asynchronous communication 9600 Baud 8 data bits 1 stop bit no parity Hardware handshake protocol If the above message does not appear check the following 1 Baud rate and character format setting of the terminal default upon delivery of the SYS68K CPU 6 is 9600 Baud 8 data bits 1 stop bit no parity 2 Cable connection form the SYS68K CPU 6 to the terminal please refer to the Hardware User s Manual for the pinning of the D Sub connector and the required handshake signals 3 Power supply 5V 12V 12V must be present See the Hardware User s Manual for the power consumption of the SYS68K CPU 6 If everything goes well the header and prompt are displayed on the terminal and VMEPROM is now ready to accept commands 1 4 Front Panel Switches 1 4 1 RESET Switch Pressing the RESET switch on the fron terminate immediately and resets the processor and all When the VMEPROM kernel is started i the user memory after the task control block with an
50. Start Address 0A0000 End Address SOBFFFF Boundary 020000 Access Modes Byte or Word transfers Read or Write on SRAM Read only on EPROM Usable Data Bits DO D7 and D8 D15 Default Access Time 250ns max 4 3 Serial I O Interfaces The board contains thr Separate strap selectable baud rate interface serial I O assignment All serial Communication I O indep has a changes to the 25 pin control chips 4 3 1 The Baud Rate Selection Each clock input for the transmit and receive baud rate of the I O channels is strap selectable to one of the nine different baud rate clocks driven by the 14411 B7 defines the baud rate of the terminal host and the remo The connection at B7 between pins 10 and 11 defines the baud ra The receiver and transmit three serial range and works as a prescaler rate of the three rates as listed in B7 20 B7 18 B7 16 Baud Baud Baud Table 4 3 1 selector of selector of selector of ndent serial jumperfield for are 6850 Interface Adapter ACIA the host port the remote port D sub connectors devices I O channels with a 110 to 38400 Ba ud Each easy I O signal female Asynchronous The jumperfield the terminal port te por ter ba ports can be connected to the different ba te ud ud Each of the baud rate selection signals has to be connect
51. VMEPROM COMMANDS FOR CPU 6 The following commands are implemented on the CPU 6 in addition to those listed in Chapter 3 of the VMEPROM User s Manual 4 1 Search VMEbus for Hardware Format This comman useful if switch 8 is set to off 1 4 3 configuration by default to section In addition memory in the system 50 searches the VMEbus for available hardware VMEPROM is started and the simulated front panel for further information that VMEPROM does not this command allows the user to install with this command The following hardware is detected 9 ASCU 1 0 1 SIO 2 SCS 1 1 2 37 4 5 6 1 Contiguous m It is please refer check the emory starting at 100000 additional Additional memory can ONLY be installed The boards must be set to the default address for 16 bit systems the CPU 6 used The CONFIG command al and initializes the disk controller if 5 5 1 example 25 the CONF This set the Appendix of th L is aci from the selftest the command is suspended until the SYSFAI e Additional memory must be contig must start at 1 G command to allow up is summarized for all supported boards in is manual uous to the on board memory of 00000 This memory is cleared 9 no long
52. address at which the code data is to reside 53 A record containing code data and the 4 byte address at which the code data is to reside S5 A record containing the number of S1 S2 and S3 records transmitted in a particular block The count appears in the address field There is no code data field Not supported by VMEPROM 57 termination record for a block of 53 records address field may optionally contain the 4 byte address of the instruction to which control is to be passed There is no code data field S8 A termination record for a block of S2 records The address field may optionally contain the 3 byte address of the instruction to which control is to be passed There is no code data field S9 A termination record for a block of S1 records The address field may optionally contain the 2 byte address of the instruction to which control is to be passed Only one termination record is used for each block of S records 37 and S8 records are usually used only when control is to be passed to a 3 or 4 byte address Normally only one header record is used although it is possible for multiple header records to occur 2 5 Example 5214020000000004440002014660000 241 F8044CB1 214020010203C0000020E428110C1538066FA487AE4 214020020001021DF0008487A001221 521402003021 425553200030600821 41
53. and signal paths that bus the connector pins Some 1014 systems have a single PC board called the J1 backplane It provides the signal paths needed for basic operation Other 1014 systems also have an optional second PC board called J2 backplane provides the additional 96 pin connectors and signal paths needed for wider data and address transfers Still others have a single PC board that provides the signal conductors and connectors of both the J1 and J2 backplanes BACKPLANE INTERFACE LOGIC Special interface logic that takes into account the characteristics of the backplane its signal line impedance propagation time termination values etc The 1014 specification prescribes certain rules for the design of this logic based on the maximum length of the backplane and its maximum number of board slots BLOCK READ CYCLE A DTB is cycle used to transfer a block of 1 to 256 bytes from a SLAVE to a MASTER This transfer is done using a string of 1 2 or 4 byte data transfers Once the block transfer is started the MASTER does not release the DTB until all of the bytes have been transferred It differs from a string of read cycles in that the MASTER broadcasts only one address and address modifier at the beginning of the cycle Then the SLAVE increments this address on each transfer so that the data for the next cycle is retrieved from the next higher location
54. automatically without any modifications to the boards 1 1 Function Switch Positions The SYS68K CPU 6 contains two toggle switches with a default parking position The RESET and the ABORT switches move automatically back into the DOWN position after having been switched into the UP position Please toggle the switch sometime before installing the board into the rack to detect any switches which may have been damaged during transportation For reference Figure 1 1 shows the Front Panel of SYS68K CPU 6 in detail Figure 1 1 Front Panel of SYS68K CPU 6 REMOTE Interface Connector Interface Connector P3 HOST Interface Connector 1 2 Connection of the Terminal The terminal must be connected to the terminal interface connector found in the middle of the front panel The following communication setup is used for interfacing the terminal No Parity 8 Bits per character 1 Stop Bit 9600 Baud Asynchronous Protocol Please configure the terminal to this setup The hardware interface is RS232 compatible and the following signals are supported Signal PIN Input Output Common Protective GND 1 RxD 2 TxD 3 x DTR 5 X GND 3 CTS 20 not drive a signal line which is CAUTION The terminal used must t of SYS68K CPU 6 marked to be an outpu 11 signals marked as Input or Common have to be supp
55. converted by jumper 3 5V for Facit 5165 current loop adapter if strapped internally 3 11 Glossary of VMEbus Terms IEEE 1014 A16 A type of module that provides or decodes an address on address line A01 through A15 A24 A type of module that provides or decodes an address on address lines A01 through A23 A32 A type of module that provides or decodes an address on address lines A01 through A31 ARBITRATION The process of assigning control of the DTB to a REQUESTER ADDRESS ONLY CYCLE A DTB cycle that consists of an address broadcast but no data transfer SLAVES do not acknowledge ADDRESS ONLY cycles and MASTERS terminate the cycle without waiting for an acknowledgment ARBITER A functional module that accepts bus requests from REQUESTER modules and grants control of the DTB to one REQUESTER at a time ARBITRATION BUS One of the four buses provided by the 1014 backplane This bus allows an ARBITER module and several REQUESTER modules to coordinate use of the DTB ARBITRATION CYCLE An ARBITRATION CYCLE begins when the ARBITER senses a bus request Ihe ARBITER grants the bus to a REQUESTER which signals that the DTB is busy The REQUESTER terminates the cycle by taking away the bus busy signal which causes the ARBITER to sample the bus requests again BACKPLANE 1014 printed circuit PC board with 96 pin connectors
56. different configurations The configuration for VMEPROM is defined on top of file to NT 64 NF 64 51000000 16M 120 121 NOTE The offset on top of each line is calculated only for this 7 configuration 019C char _maps NMB system memory bit map 059C char NPS 1 NCP character input buffers 097A char iout NPS 1 NCP character output buffers 0D58 char rdtb 16 redirect table 0D68 int _tque NTBt1 task queue ODEA char tlst NTB TBZ task list 11EA char tsev NTB 32 task schedule event table 19EA long _tmtf NTM to from INDEX W 1 char tmbf TMZ NTM task message buffers 2AEA char _tmsp NTP 6 task message pointers 2B4A char _deig 2 8 NIE 10 delay event insert queue 2C94 char _devt 2 NEV 10 delay events 2F16 int _bsct 32 basic screen command table 2F56 int _xchi NCB channel buffer queue 2F66 char xchb NCB BPS channel buffers 3F66 char xfsl NFS FSS file slots 40E6 char 121 level 2 lock file prims evnt 40E7 char 131 level 3 lock disk prims evnt 40E8 char spare3 8 reserved for PDOS INSTALL 40F0 int rdkl NRD 4 1 RAM disk list ii ui T i ud i
57. follows Only one jumper can be set at B31 and B32 to define the multiplication factor to the times listed Multiplication factor Connection min max Note B3 1 2 1 2 31 3 2 x3 x4 B32 3 2 x5 x6 B32 1 2 7 8 Default setting during manufacturing Calculation example minimum timeout 3205 x 3 96us maximum timeout 32us x 4 128us 5 6 The Slot 1 Functions 5 6 1 The SYSCLK Driver If the SYS68K CPU 6 board is used as the slot 1 controller master board the SYSCLK signal of the VMEbus must be driven This signal is a fully asynchronous 16 MHz clock signal which can be enabled if a jumper on jumperfield B13 is installed between Pin 11 and Pin 20 Default condition during manufacturing If there is no connection no SYSCLK signal is driven from the SYS68K CPU 6 Figure 5 6 2 outlines the jumperfield of the SYSCLK Signal By default the jumper between pin 11 and pin 20 is installed and the SYSCLK signal is driven 5 6 2 ACFAIL The VMEbus signal ACFAIL can be connected to the H4 input of the PI T to initiate an interrupt on level 5 A handling routine has to be written for proper handling of the ACFAIL condition application dependent The connection of the ACFAIL signal to the PI T can be made by inserting a jumper at jumperfield B24 between pin 11 and pin 12 The location di
58. intentionally left blank 4 0 DEVELOPMENT SYSTEMS WITH SYS68K CPU 6 For software development with the SYS68K CPU 6 series of boards FORCE COMPUTERS offers a development target system with SYS68K CPU 6 as a CPU board and the Real Time Operating System PDOS The multiuser Real Time Operating System includes an Assembler for the 68000 68010 as well as the following programming languages as an option C FORTRAN 77 PASCAL All of these compilers generat fficient code to optimize the run time of the programs Further details are listed in the data sheet of the miniFORCE series of development target systems DOS is a trademark of Eyring Research Laboratories This page was intentionally left blank 5 0 HISTORY MANUAL 5 5 REVISION DESCRIPTION DATE OF LAST CHANGE Rev 1 1 VMEPROM description for Version 2 53 included 2 Chapter 6 5 The Program mable Reset Option has been added 3 Default Jumpersetting of B23 has been corrected NOV 28 1989 Rev 2 Appendix F Front Panel Switches has been removed from Section 7 Appendix to the Introduction to VMEPROM JUL 25 1990 Rev 3 Appendix H Generation of Application in EPROM has been removed from Section 7 Appendix to the Introduction to VMEPROM 0171992 4 Corrected chapter 4 2 3 Access Time Selection AUG 06 1996
59. intentionally left blank Table 4 2 1 EPROM Area 2 Jumper Settings for EPROMs Type Jumperfield B27 12 O O O O O 2764 1 i 241 10 9 8 7 O O O O O O 27128 O O O O O O 1 2 3 4 5 6 12 11 10 9 8 7 27256 1 2 3 4 5 6 12 11 10 9 8 7 O O 27512 1 2 3 4 5 6 Default condition during manufacturing Table 4 2 1B Note No battery backup for the SRAMs EPROM Area 2 Jumper Settings for SRAMs Jumperfield B27 12 11 10 9 8 7 6264 1 2 3 4 9 6 12 11 10 9 8 7 O O 62256 1 2 3 4 5 6 With on board battery backup for the SRAMs Jumperfield B27 12 11 10 9 8 y 62LP64 1 2 3 4 5 6 12 11 10 9 8 7 62LP256 2 4 5 If the on board ba devices may be installed be destroyed ttery backup is used Otherwis only full CMOS the battery will Location Diagram of the EPROM Area 2 Figure 4 2 1 SENDERS DN pl a 5 I a i CN TP L3 UN LL r E 8 This p
60. memory The task s memory has a size of approximately 490 Kbyte Only the switches 2 and 8 on the front panel are used All other are undefined Switch 2 defines the databus width and Switch 8 is used to check for the hardware configuration on VMEbus Keep All Setups In order to keep all setups of VMEPROM the user program can be located at address 58800 relative to the begin address of the EPROM real address 88800 In this case the front panel switches are defined as described in the Introduction to VMEPROM Both the user and the supervisor stack are located in the task control block The user stack has a reserved space of 800 bytes and the supervisor stack a space of 5600 bytes The program is started in user mode The following values are available on the stack 4 A7 Long word containing the begin address of the TCB 8 A7 Long word containing the begin address of the system RAM SYRAM A C program at this address could look like this main tcbp syramp struct TCB tcbp struct SYRAM syramp BIOS SOURCE CODE LISTINGS 5 68230 Initialization 58167 Initialization 6850 Initialization Receiver Interrupt Handler ACIA Character Output Driver 1 PI T 68230 Initialization Initialize LEA L PI 0 MOVE B 508 A0 ST B PCDR 0 CL
61. memory to support multiple vector tables and to allow a variable memory map On SYS68K CPU 6 VMEPROM the vector base register is not altered which results in the same address map as used for the 68000 version The Function Code Register allows the supervisor to access user data and program space to emulate CPU space cycles and or modify data During a Bus Error exception processing sequence the following information is placed on the supervisor stack A Status Register B Program Counter 2 to 5 words Frame format vector offset D Internal register information 22 words Storage of this information allows recovery from a bus error and nables the program to be continued from where the bus error occurred 4 Vector Table of the 68010 Vector Address 5 Dec Hex Space Assignment 0 0 000 SP Reset Initial SSP 4 004 SP Reset Initial PC 2 8 008 SD Bus Error 3 12 00C SD Address Error 4 16 010 SD Illegal Instruction 5 20 014 SD Zero Divide 6 24 018 SD CHK Instruction 7 28 01 SD TRAPV Instruction 8 32 020 SD Privilege Violation 9 36 024 SD Trace 10 40 028 SD Line 1010 Emulator 11 44 02C SD Line 1111 Emulator 12 48 030 SD Unassigned reserved 13 5 2 034 SD Unassigned reserved 14 56 038 SD Unassigned reserved
62. must be installed by using the INSTALL command The following must be entered INSTALL U3 85800 In order to install one of the ports of an ISIO board in VMEPROM the BP command can be used The ISIO 1 2 boards are the driver type 3 In order to install the first port of 9 O board with a baud rate of 9600 the following commandline can be used BP 4 9600 3 968000 Ihe port can then be used as port number 4 Please note that the hardware configuration must detected befor a port can installed This can be done with the CONFIG command or by setting a simulated front switch on the CPU 6 and pressing RESET Please refer to the command description in the VMEPROM User s Manual for a detailed description of the CONF Ihe base address of all ports of an 9 Specified with the BP command are as follows VMEPROM supports up to two serial SIO port 4 first ISIO board 2 3 4 5 6 7 8 1 second ISIO board 2 3 4 5 6 7 8 the SIO 1 2 board or the note that the first board of In using one SIO 1 board and one address of the boards have address VMEPROM supports up to two floppy disk drives and three Winch SIO 1 SIO 968 968 968 968 968 968 968 968 988 988 988 988 988 988 988 988 Co
63. priority of the pending interrupt request is lower than or equal to the current processor priority the execution continues with the next instruction and no interrupt exception processing is started If the priority of the pending interrupt is greater than the current processor priority th is started After the start of the interru Status Register SR is saved the processor is set to supe level is set to the level of Ih device classifying th th e processor fetches the vector number from the referen n th xception processing sequence exception sequence a copy of the n the stack the privilege state of visor and the processor priority e interrupt being acknowledged interrupting displaying the level th in Table 4 8 1 Table 4 8 2 shows th address under which the start routine is stored number of the interrupt being acknow e address bus using the address signals 1 e conversion of the interrupt vector into ce as an interrupt acknowledge and ledged on A2 and A3 as listed the address of the interrupt service Table 4 8 1 Interrupt Acknowledge Level Code E A3 A2 Al FCO FC2 Note 1 1 1 6 1 1 0 5 0 1 4 0 0 3 0 1 2 0 0 1 0 0 1 0 0 0 Note Not assigned The content of the interrupt vector whose vector number was fetched and translated is loaded into the
64. program counter to start the interrupt handling routine The vector that was moved from the interrupting device onto the data bits DO D7 is translated by the CPU into an address which contains the start address of the interrupt handling routine Table 4 8 2 The Interrupt Vector Conversion D16 D8 D7 DO Peripheral L 1 1 Vector ignored WE sos oe V2 V1 VO Number 16 8 7 Al Translated E we es Address 00000 V7 V6 ME Rue to s VO VO VO from the 8 bit vector number 4 8 1 Interrupt Level Assignment The SYS68K CPU 6 board contains six on board interrupt sources the three serial I O Controllers ACIAs the ABORT function switch the Parallel Interface and the Real Time Clock Table 4 8 1 lists the combinations of the on board devices and the corresponding interrupt level as well as the default set auto interrupt vectors Table 4 8 3 The On Board Devices Interrupt Scheme Interrupt Autointerrupt Default On Board Devic Level Vectoring Vector Address ABORT Switch a YES Sih 500007 58167 6 5 30 5000078 68230 5 5 29 5000074 Terminal 4 5 28 5000070 Remote 3 YES 21 00006C ACIA Host 2 YES 26 000068 ACFAIL SYSFAIL 5 a YES 29 0
65. set to the base address 5800000 by default VMEPROM expects the first SIO 1 SIO 2 boards at 5 00000 This is in the standard address range A24 D16 D8 of address 5 00000 So the address modifier decoder AM Decoder of the SIO 1 2 boards must be set to Standard Privileged Data Access Standard Nonpriviledged Data Access Please refer to the User s Manual of your SIO boards to perform the necessary setup If a second SIO 1 2 board shall be used the base address must be set 1 to SFCBOOZOO0 Th used address setup of the second 51 O b Before using the driver for the 51 INSTALL installed by using the entered INSTALL The 51 BP command can be used Please refer to the User s Manual of your 51 In order to install one of the ports of the S o same AM decoder setup as described above must be board for the oard O 1 2 board the driver must be command The following must be U2 85400 IO boards in VMEPROM the 1 2 boards use the driver type 2 Therefore to install the first port of an SIO board with a baud rate of 9600 the following command line can be used BP 4 9600 2 B00000 Ihe port can then be used as pori number 4 Please note that the hardware configuration must b installed This can be done with a simulated front panel switch on detected befor a port can be the CONFIG command
66. the system monitor called SYS68K CPU 6 and for the user program data The dynamic RAM area consists of 512 Kbytes on the SYS68K CPU 6 The DRAM has an access time of 150ns typical if no refresh cycle is under execution 4 6 1 Address Map and Capacity Address 000 000 ROM Initialization Vectors from System EPROM 000 007 000 008 SYSTEM DRAM Area Reserved 007 FFF 008 000 I USER DRAM Area 512 Kbytes 07 FFF 4 6 2 Access Timing of the DRAM This paragraph describes all of the timings to from the DRAMs In general the DRAMs 120ns devices which operate at an ffective access time of 150ns A fully asynchronous control logic drives the access cycles as well as the refresh cycles The refresh circuitry generates one refresh cycle every 15 microseconds Therefore the board can be used to operate in high end real time applications The detailed timing diagram is shown in Table 4 6 1 and Figure 4 6 1 Table 4 6 1 Time Values for an Access Cycle without Refresh Request ns ns SIGNAL DESCRIPTION Min Max 1 AS active to Access Request 10 33 active 2 AS active to Access Cycle 33 66 start 3 AS active to DTACKOUT 285 328 asserted 4 AS active to AS 285 14000 inactive 5 AS inactive to DTACKOUT 30 45 inactive 6 AS inactive to Access Cycle 15 25
67. tings D owed by Write Cycl lowed by Read Cycl e Address Modifier Codes e Short me Valu quisition e VMEbus es I O Jumper Settings Time Values of the Single Level mper Settings of B25 of the Interrupt Interrupt Jumper Settings tings for EPROMs tings for SRAMs for B24 and 24 without Bus Arbiter B31 and B32 for RAT Vector This page was intentionally left blank 1 0 GENERAL INFORMATION The SYS68K CPU 6 series of processor boards combines the powerful 16 32 bit microprocessor the 68000 68010 with 512 Kbytes of dynamic RAM and a VMEbus interface The on board Real Time Clock the three serial I O interfaces and the parallel I O and timer offer a powerful combination to accomplish a wide variety of applications Easy access to the installed devices is provided through the ROM resident monitor called VMEPROM This powerful software package is based on a realtime kernel and file manager and can be used for program development and debugging of application programs The usage of the SYS68K CPU 6 series of boards in critical real time applications is provided through the high CPU clock rate up to 12 5 MHz and the fast on board DRAM only 1 wait state at 12 5 MHz Photo of SYS68K CPU 6 Figure 1 1 Figure 1 2 VMEbus Block Diagram of the SYS68K CPU 6 P Connector 65807 PPEP nly a
68. 00074 Note On request this signal from the VMEbus can be used to generate an Interrupt Please refer to Chapter 5 7 2 4 8 2 Usage of the Auto Vectors Table 4 8 4 lists the vector numbers for the autointerrupt scheme and the spurious interrupt Table 4 8 4 The Autointerrupt Vector Table Absolute Vector Corresponding Address Number Interrupt Level 000060 24 Spurious Interrupt 000064 25 Level 1 Interrupt Autovector 000068 26 2 r 00006C 27 2 5000070 28 4 5000074 29 5 000078 30 6 00007C 31 7 A global timing diagram of the interrupt vector acquisition is shown in Figure 4 8 1 The priority level seven is a special case Level seven in cannot be disabled by the interrupt priority mask a non maskable interrupt terrupts IRO 7 is Figure 4 8 1 The Global Interrupt Vector Acquisition z A01 A31 J YX LWORD M AS SR Ei MASTER OUTPUTS WRITE ed a E 051 DATA TRANSFER BUS 000 007 SLAVE DTACK r OUTPUTS BERR NOTE The interrupt vector aquisition is only used during IRQ s from the VMEbus 4 82 8 3 Summary of the Local Interrupts Device Type Level IRQ Vector Address ABORT Switch 2117 7 31 500007 58167 6 30 000078 68230 5 29 5000074
69. 1 Memory Map of SYS68K CPU 6 000 000 ROM Initialization Vectors from SYSTEM EPROM 000 007 000 008 E On Board DRAM 512 Kbytes 07 FFF 080 008 SYSTEM EPROM Area 128 Kbytes 09 FFF 0 0 000 USER EPROM Area 128 Kbytes or SRAM 64 Kbytes OBF FFF 041 RS 232 Interface Host P3 connector 043 oco 080 RS 232 Interfac Terminal 4 connector 082 101 RS 232 Interfac Remote P5 connector 103 401 RTC Real Time Clock 42F OEO 001 E PI T Parallel Interface Timer 0 0 035 0 0 200 I FPCP Floating Point Coprocessor 0 0 300 Reset off 0 0 380 Reset on 100 000 VMEbus A24 D16 D8 FEF FFF FFO 000 VMEbus A16 D16 D8 FFF 4 0 THE LOCAL BUS Each of the SYS68K CPU 6 products contains a local bus driven and controlled only by the 68000 68010 CPU All of the memory the I O devices and the FPCP communicate to the CPU via this bus The VMEbus interface described in Chapter 5 of this manual is also connected to this local bus and fully controlled by the CPU Detailed information about the functional groups is given in the subsequent chapters For reference a block diagram of the SYS68K CPU 6 is provided at Figure 4 0 1 The SYS68K CPU 6 consists of four sockets for JEDEC compatible devices Two different memeory
70. 5 5 Summary of the 4 6 Dynamic RAM 4 6 1 Address Map Capacity 4 6 2 Access Timing of the DRAM 4 6 3 Refreshing of the DRAMs 4 6 4 Summary of the DRAM I 4 7 The Floating Point Coprocessor 68881 FPCP 4 7 1 Interfacing to the 68881 4 7 2 Data Format of the 68881 4 7 3 68881 Instruction Set 4 7 4 Addressing of the 68881 4 7 5 Detection of the 68881 4 7 6 RESET of the FPCP gt 4 7 7 Summary of the 68881 4 8 Local interrupt Handling 4 8 1 Interrupt Level Assignment 4 8 2 Usage of the Auto Vectors 4 8 3 Summary of the Local Interrupts 4 9 The BERR Generator THE VMEbus INTERFACE 5 1 Data Transfer Size 5 2 The Address Modifier Implementation 5224 The Short Address Modifier Code 5 3 VMEbus Arbitration 5 3 1 Arbiter Options 5 3 2 On Board Slave Bus Arbitration 5 4 The Single Level Bus Arbiter 5 5 VMEbus Rel lease Functions IND Ds Release On Request ROR 5 5 2 Release on Bus Clear RBCLR 5 5 3 Release After Time Out RAT 5 6 Slot 1 Functions 552 gt 5 6 1 SYSCLK Driver 5 6 2 ACFAIL Srp a Sw 5 7 The VMEbus Interrupt Handler 5 7 1 The On Board IACK Daisy Chain 5 7 2 The VMEbus Interrupt Handling 5 7 3 The ABORT Function Switch 5 8 Summary of the VMEbus Interface THE RESET STRUCTURE 6 1 The Voltage Sensor iS ee 6 3 The Reset Instruction of the CPU 6 4 The Reset Funct
71. 6 B9 2 6 27 8 D3 E 6 B10 2 2 6 7 2 E 6 B11 2 4 6 32 7 02 6 B13 3 1 4 B33 7 D3 6 14 4 3 4 B34 7 03 6 B15 4 01 4 B35 3 A2 E 6 B16 4 4 6 B36 4 2 4 21 6 2 6 B37 4 1 4 1 System and User Jumpers Jumper Description Default Schematics See field Page B1 Serial I O Interface 2 19 1 4 31 configuration for remote 3 18 16 10 11 B3 Serial O Interface 2 19 1 4 24 configuration for 18 terminal 4 17 5 16 P 8 eL 6 13 B5 Serial I O Interface 2 15 1 D1 4 38 configuration for host 3 14 4 13 5 X2 7 10 8 9 B7 Baud Rate Control 1 20 1 D3 4 17 3 18 5 16 10 11 24 Parallel Interface 1 2 7 4 4 47 3 6 4 7 8 10 11 13 14 16 17 19 20 24 Parallel Interface 1 6 1 4 47 2 S04 Jumpers 4 2 Jumper Location Diagram of the System and User I O Configuration EDD mah _ En E nn lE B BE ug 4 3 VMEbus Configuration Jumpers Jumper Description Default Schematics See field Page B14 Reset Generator zc 4 B3 6 1 B36 4 2 B37 4 2 B300 1 2 4 B2 B13 Bus Re
72. 68000 program co The first byte 8 bi Ihe seven stack poin All of the word addre 68010 contains seventeen 32 bit registers two 32 bit unters and a 16 bit status register eight registers are used as data registers 00 07 for t word 16 bit and long word 32 bit operations address registers A0 A6 the supervisor and the user ter may be used as base address registers or as software Stack pointers where word and long word operations are supported 17 registers described may be used for word and for long SS operations or as index registers Table 3 1 lists the clock frequencies for each of the SYS68K CPU 6 versions the processor type and the corresponding jumper settings Table 3 1 CPU Clock Frequency Version CPU Type Clock Frequency Jumper Settings at 10 CPU 6A 68000 12 5 MHz Mode A CPU 6V 68010 8 0 MHz Mode B CPU 6VA 68010 12 5 MHz Mode A CPU 6VB 68010 12 5 MHz Mode A Figure 3 1 CPU Clock Speed Jumper Settings Mode A CPU 6A CPU 6VA CPU 6VB B21 B10 1 1 o Mode B CPU 6V B21 B10 A 1 1 Caution No other jumper settings are allowed Any other jumper setting than those shown can cause component damage and or other malfunctions Figure 3 2 Location Diagram of the CPU Cloc
73. 81 FPCP is designed to operate coprocessor with the 68020 microprocessor or as a peripheral device with the 68000 68010 microprocessors There is a software handshake defined for intercommunication between the CPU and the FPCP This procedure is performed by the 68020 on its own while 680x0 microprocessors need a software package to run the handshake The procedure is described in the 68020 User s Manual the 68020 coprocessor interface handshake protocol The specific application of the protocol is described in the 68881 User s Manual The offset of the FPCP to the I O Area Base Address is 200 so the base address of the FPCP is 0 0200 The 68881 data sheet is included in Appendix H The 68881 Floating Point Coprocessor operating at 12 5 MHz clock frequency is a full implementation of the IEEE Standard P754 for Floating Point Arithmetic Draft 10 0 A set of eight general Floating Point Data Registers supporting full 80 bit extended precision are available for arithmetic operations such as Add Subtract Multiply Divide Compare Scale Exponent Modulo Conditional Branches Absolute Value Sin cosine hyperbolic sin and cosine Tangent cotangent hyperbolic tangent and cotangent e EXP x e EXP x 1 E EXP xtract 4 ln x ln x 1 log 10 log 2 x 2 EXP x 10 EXP x Square root Conditional Trap 32 The FPCP supports the following
74. CNTRM 0E0033 R N N Count Register Low CNTRL 0 0035 R W Y N Timer Status Register TSR A write to this register may perform a special status resetting operation Mode Dependent DEVICE 58167 Real Time Clock Address Mode Description 0C0401 R W Counter Ten Thousands of Seconds 0C0403 R W Counter Hundredths and Tenths of Sec 0C0405 R W Counter Seconds 0C0407 R W Counter Minutes 0C0409 R W Counter Hours OCO40B R W Counter Days of the Week OCO40D R W Counter Days of the Month 0 040 R W Counter Month 0C0411 R W RAM Ten Thousands of Sec 0C0413 R W RAM Hundredths and Tenths of Sec 0C0415 R W RAM Seconds 0C0417 R W RAM Minutes 0C0419 R W RAM Hours 0 041 R W RAM Days of the Week 0 041 R W RAM Days of the Month 0 041 R W RAM Month 0C0421 Interrupt Status Register 0C0423 R W Interrupt Control Register 0C0425 W Counters Reset 0C0427 W RAM Reset 0C0429 R W Status Bit 0C042B W GO Command 0C042D W Standby Interrupt 0C042F W Test Mode APPENDIX D Component Part List SYS68K CPU 6 For Internal Use Only Jumper Settings on the SYS68K CPU 6 Jumper Page Jumper Page field Coordinate Description field Coordinate Description B1 1
75. DECIMAL CONVERSION OVERFLOW OCCURS Figure 4 7 2 Register Model of the 68881 79 63 0 FPO FP1 2 FP3 Floating Point 4 Data Registers 5 6 7 23 1 5 7 0 0 Exception Mode FPCR Control Register E sun ka ru P Enable Control Condition Quotient Exception Accrued FPSR Status Register Code Status Exception FPIAR Instruction Address Register 4 7 3 The 68881 Instruction Set The 68881 instruction set is organized into six major classes 1 Moves between the 68 2 Move multiple registers 3 Monadic operations 4 Dyadic operations 881 in and out in and out 5 Branch set or trap conditionally and 6 Miscellaneous 4 7 4 Addressing of the 68881 The 68881 is addressed via a part of the address signals The coprocessor address is 50 02 The Coprocessor Interface Register Map 31 00 RESPONSE CONTROL 04 SAVE RESTORE 08 COMMAND OC RESERVED CONDITION 10 OPERAND 14 REGISTER SELECT RESERVED 18 INSTRUCTION ADDRESS 1C OPERAND ADDRESS 4 7 5 Detection of the 68881 The sense pin of the FPCP is not connected Should an address of a nonpresent FPCP be addressed 0E02XX then a bus error will occur 4 7 6
76. HIGH HIGH Interrupt Acknowledge The Function Code Assignment to the AM Codes The function code signal and FC2 from the CPU and the DMAC are connected to the VMEbus via a transceiver The assignment to the AM codes is listed below FCO gt gt AM1 FC2 gt 2 5V gt Short I O Range gt AMA 5V gt 5 Therefore all AM codes which are defined the specifications are supported The Address Modifier Codes Table 5 2 1 dads snq3WA snq3iNA 9 dS snq3WA snq3WA snq3WA snq3WA oeds snq3WA oeds snq3WA gad snq3WA snq3WA oadg snq3WA 9945 snq3WA A8 ssa2oy pepueix3 sse2oy Duipueosy 5 85900 p pu lx3 559000
77. ICE SYS68K CPU 6 User s Manual Edition No 4 March 1997 P N 200119 FORCE COMPUTERS Inc GmbH All Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted Copyright by FORCE COMPUTERS INTRODUCTION This page was intentionally left blank 5 GENERAL INFORMATION ON THE SYS68K CPU 6 THE FLOATING POINT COPROCESSOR THE MONITOR OF SYS68K CPU 6 DEVELOPMENT SYSTEMS WITH SYS68K CPU 6 HISTORY OF MANUAL REVISIONS This page was intentionally left blank 1 0 GENERAL INFORMATION ON THE SYS68K CPU 6 The SYS68K CPU 6 series of processor boards uses a 68000 or a 68010 CPU and the 68881 Floating Point Coprocessor only on CPU 6VB To provide fast CPU operation in a local RAM area at CPU frequency of 8 or 12 5 MHz a 512 Kbyte dynamic RAM is instal lock on every CPU board Zero or wait state is required for each DRAM access 8 or 12 5 MHz operation Three serial I O interfaces are provided on the board to communicate to a terminal printer host computer or any other equipment which is RS232 compatible Up to 512 Kbytes of EPROM can be used on the four 28 pin sockets to allow effective usage of the SYS68K CPU 6 boards performance applications in high A Real Time Clock with on board battery backup and a parallel interface completes the SY
78. Instruction 7 28 01 SD TRAPV Instruction 8 32 020 SD Privilege Violation 9 36 024 SD Trace 10 40 028 SD Line 1010 Emulator 11 44 02C SD Line 1111 Emulator 12 48 030 SD Unassigned reserved 13 5 2 034 SD Unassigned reserved 14 56 038 SD Unassigned reserved 15 60 03C SD Uninitialized Interrupt Vector 16 23 64 04C SD Unassigned reserved 95 24 96 060 SD Spurious Interrupt 25 100 064 SD Level 1 Interrupt Autovector 26 104 068 SD Level 2 Interrupt Autovector 21 108 06C SD Level 3 Interrupt Autovector The Vector Table of the 68000 cont Vector Address 5 Dec Hex Space Assignment 28 112 070 SD Level 4 Interrupt Autovector 29 116 074 SD Level 5 Interrupt Autovector 30 120 078 SD Level 6 Interrupt Autovector 31 124 07C SD Level 7 Interrupt Autovector 32 47 128 080 SD TRAP Instruction Vectors 191 OBF 48 63 192 0CO SD Unassigned reserved 255 OFF 64 255 256 100 SD User Interrupt Vectors 1023 3FF Vector numbers 12 13 14 16 through 23 and 48 through 63 are reserved for future enhancements No user peripheral devices should be assigned these numbers 3 3 The 68010 Hardware Description The 68010 contains the same features as those the 68000 description in paragraph except for the following enhancements A vector base register is used to determine the location of the exception vector table in
79. NAL Protective GND 2 X Receive Data RXD 3 X Transmit Data TXD 4 5 X Request to Send RTS 6 7 X X Signal GND 8 X Data Carrier Detect DCD 9 X X Signal GND 19 20 X Clear to Send CTS Remote Connector Signal Assignments INPUT OUTPUT SIGNAL Protective GND 2 X Receive Data RXD 3 X Transmit Data TXD 4 5 X Request to Send RTS 6 7 X X Signal GND 8 X Data Carrier Detect DCD 9 X X Signal GND 19 20 X Clear to Send CTS Host Connector Signal Assignments En INPUT OUTPUT SIGNAL Protective GND 2 X Transmit Data TXD 3 X Receive Data RXD 5 X Clear to Send CTS 7 X X Signal GND 9 X X Signal GND 18 20 X Clear to Send CTS Pin Assignment for EPROM Area 1 Lower Byte 27512 27256 27128 2764 2732 2732 2764 27128 27256 27512 A16 VCC VEC NC 28 Vcc NC X X X X X X X X NC A13 21 NC VCC VCC 15 15 X X X X X 8 26 A14 A14 A14 X X X X X A7 25 X X X X X X X X X X A6 24 A10 X X X X X X X X X X 5 23 A12 X X X X X X X X X X 4 22 OE X X X X X X X X X X A3 21 All X X X X X X X X X X A2 20 CE X X X X X X X X X X A 19 D7 X X X X X X X X X X DO 18 D6 X X X X X X X X X X D1 I DS X X X X X X X X X X D2 16 D4 X X X X X X X X X X GND LS X X X X X
80. OVE L 100000 D6 8000 XSEV SET EVENT SUBQ L 1 D6 DONE BGT S 8000 PN RTS BENIIEND PAGE PDOS BENCHMARK 3 CHANGE TASK PRIORITY BEN12BEG MOVEQ L 1 D0 SELECT CURRENT TASK MOVEQ L 64 D1 SET PRIORITY TO 64 MOVE L 100000 D6 8000 XSTP SET PRIORITY SUBQ L 1 D6 DONE BGT S 000 PN RTS BEN12END PDOS BENCHMARK 44 SEND TASK MESSAGE BEN13BEG CLR L DO SELECT TASK 0 LEA L 1 1 MOVE L 100000 D6 8000 XSTM SEND MESSAGE XKTM READ MESSAGE BACK SUBQ L 1 D6 DONE BGT S 8000 PN RTS 501 DC B BENCH 13 0 EVEN PAGE BEN13END PDOS BENCHMARK 45 READ TIME OF DAY BEN1 4BEG MOVE L 100000 D6 8000 EQU XRTP SUBQ L 1 6 DONE BGT S 8000 PN RTS Special Locations The following table describes some special locations in the EPROM These locations define the default setup of the name of the startup file user program location and RAM disk addresses These options can be selected by front panel switches The locations shown in the table can be changed by the user to adapt VMEPROM to every environment To make the necessary changes please conduct the following steps Read the EPROMs with an EPROM programmer 23 Modify the code 35 Burn new EPROMs and keep the old ones in a safe location 4 Insert the new EPROMs in the CPU board and test the changes
81. R B TMCR 0 CLR B PSRR AO MOVE L 0 MOVEP L DO CPR AO MOVEP L CNTR 0 MOVE B 5 1 0 POINT TO CHIP GET PC3 AS OUTPUT LEAVE PC5 INPUT SET PC3 HIGH NO T timer as if System Clock INT ENABLE PC3 ON TOUT PC3 PIN FOR NO INTS FOR PIRQ GET TIMER CONSTANT LOAD PRELOAD LOAD COUNTER ENABLE T 58167 Initialization Initialize LEA L MOVE B 500 5 2 MOVE B 00 ICR 2 INTS OFF POINT TO CHIP RESET amp DISABLE STANDBY Turn OFF compare int INTERRUPT 3 6850 Initialization Ck CK CK CK Ck CK CC CC CC CC CK sk se se e CK de sc fe se S S Sk UK Se ese she A X se ko o BAUD PORT D1 B FHPI 8D S CMD B Ih08 POOL BAUD BSR S U1DC CHECK FOR VALID BASE BSR S U1CMD BUILD A COMMAND REG FROM D1 MOVE B PSLEDB CMD 1 A0 SET CONTROL CODE BRA S GOOD RETURN SR EQ DC L U 1ADR DC L U 2ADR DC L U 3ADR DC W 0
82. RETURN ADDRESS SET STATUS RETURN EQ 4 Receiver Interrupt Handler BINT4 ACIA SPI2 SPI3 ACIA02 4 6 DLER TERMINAL PORT ADDR DISABLE INTS PORT ADDR AFTER INTS DISABLED PLEASE SAVE REGS GET UART ADR lt PY EXI T TO 25 DATA AVAILABLE GET CHARACTER PUSH HOST PORT ADDR PUSH REMOTE PORT ADDR LOAD UP SYSRAM PTR ENTRY POINI XDEF XDEF SPIl SPI2 SPI3 MOVE L U 1ADR A7 MOVE W B PTMSK SR MOVE L A7 PSUADR MOVEM L D0 A6 A7 MOVEA L PSUADR AO BIST 0 STS_1 A0 BEQ S 04 MOVE B DAT_1 A0 DO BRA S 02 MOVE L U 2ADR 7 BRA S MOVE L U 3ADR A7 BRA S MOVEA L BSSRAM A5 MOVEA L 5 JMP K2CHRI A1 MOVEM L A7 D0 A6 RTE KERNEL TO ROUTINE K2SCHRI RESTORE REGS RETURN amp HOPE Character Output Driver
83. S TO SOURCE AND DESTINATION MOVE L 1 1 DBRA D3 002 SUBQ L 1 D2 5 8001 RTS NOP NOP PAGE 3 SUBSTRING CHARACTER SEARCH 100 000 TIMES IAKEN FROM El DN 08 08 85 MOVE L 100000 D4 MOVE L 15 D0 MOVE L 120 D1 LEA L 1 LEA L BSR S SUBQ L 1 D4 BNE S 8002 RTS BEGIN EDN BENCH 1 MOVEM L D3 D4 A2 A3 AT SUB W D0 D1 MOVE W D1 D2 SUBQ W 2 D0 MOVE B 0 3 010 1 012 DBEQ D1 010 BNE S 090 MOVE L 0 2 MOVE L A1 A3 MOVE W D0 D4 BMI S 8030 8020 A2 DBNE D4 020 BNE S 012 030 SUB W D1 D2 032 MOVEM L A7 D3 D4 A2 A3 RTS 090 MOVEQ L 1 D2 BRA S 032 END EDN BENCH 1 EDNIDAT DC B 000000000000000000000000000000 DC B 000000000000000000000000000000 DC B HEREO0000000000000000000000000 EDNIDAT1 DC B HERE IS A 000000000000000 BEN3END PAGE BENCH 44 BIT TEST SET RESET 100 000 TIMES TAKEN FROM EDN 08 08 85 BENABEG RTS BEN4END PAGE BENCH 5 MATRIX TRANSPOSITION 100 000 TIMES TAKEN FROM EDN 08 08 85 BEN5BEG RTS BEN5END PAGE
84. S68K CPU 6 Features of the 68000 68010 8 Data Registers 32 bits wide 7 Address Registers 32 bits wide 1 User Stack Pointer 32 bits wide 1 Supervisor Stack Pointer 32 bits wide 14 Addressing Modes 56 Powerful Instruction Types 16 Mbyte Direct Addressing Range using asynchronous Bus Interface 16 Bit Data Bus fully This page was intentionally left blank 2 0 THE FLOATING POINT COPROCESSOR The 68881 Floating Point Coprocessor FPCP is a full implementa Arithmetic The FPCP i tion of the IEEE Standard for Binary Floating Point IEEE 754 nstruction set supports all the addressing modes of the 68000 family The FPCP is installed on the SYS68K CPU 6VB as a COprocesso with access from the 68010 via the local bus Features of the 68881 16 7 MHz clock frequency 8 general purpose floating point data registers supporting 80 bit extended precision of real data 64 bit mantissa 15 bit exponent and one sign bit 3 registers for control status and instruction address 67 bit arithmetic unit 67 bit barrel shifter 46 instructions with 35 arithmetic operations IEEE 754 compatible including all requirements and suggestions Full set of trigonometric and transcended functions 7 data types Byte Integer Word Integer Long Word Integer Single Precision Real Double Precision Real Ext
85. Table of the 68000 The 68010 Hardware Description The Vector Table of the 68010 The Address Map of SYS68K CPU 6 LOCAL BUS EPROM Arga sep AL Ge dlc nU 4 1 1 Memory Organization of EPROM Area 4 1 2 Usable Device Types of EPROM Area 4 1 3 Access Timer Selection of EPROM Area 1 4 1 4 Insertion of Devices into EPROM Area 1 4 1 5 Address Map of EPROM Area 1 4 1 6 Summary of EPROM Area 1 The EPROM Area 2 4 2 1 Memory Organization of EPROM Area 2 4 2 2 Usable Device Types 4 2 3 Access Time Selection 4 2 4 Address Map of EPROM Area 2 4 2 5 The USER Area Summary The Serial O Interfaces EC 4 3 1 Baud Rate Selection 4 3 2 Timing of the ACIAs 4 3 3 The Terminal Port be UR Wu 4 3 3 1 Signal Assignment 4 3 3 2 Register Layout 4 3 3 3 Baud Rate Selection 4 3 3 4 Terminal Port Summary 4 3 4 Remote Port A 4 3 4 1 The I O Signal Assignment 4 3 4 2 Register Layout 4 3 4 3 Baud Rate Selection 4 3 4 4 Remote Port Summary 4 3 5 The Host Port 4 3 5 1 The I O Signal Assignment 4 3 5 2 Register Layout 4 3 5 3 Baud Rate Selection 4 3 5 4 Host Port Summary The Parallel Interface and Timer Chip 4 4 The PI T Register Layout and Addressing 4 4 2 Timer 4 4 3 Interrupt Handling 4 4 4 Summary of the PI T The Real Time Clock a 4 5 1 Register Layout 4 5 2 Access Timing 4 5 3 Battery Backup 4 5 4 Interrupt Assignment 4
86. U 6 to the terminal refer to the Hardware User s Manual for the pinning of the D Sub connector and the required handshake signals 3 Power supply 5V 12V 12V must be present See the Hardware User s Manual for the power consumption of the SYS68K CPU 6 If everything goes well the header and prompt are displayed on the terminal and VMEPROM is now ready to accept commands 3 2 Command Line Syntax All valid VMEPROM commands consist of command lt cr gt or command parameters lt cr gt where the underlined parts must be entered by the user T more than one parameter has to be entered they must Separated by a space or a comma For a detailed description of all functions of the command interpreter please refer to chapter 3 of the VMEPROM User s Manual 3 3 VMEPROM Commands VMEPROM supports more than 75 commands All of these commands are EPROM resident and are available at any time Most of these commands are common for all versions of VMEPROM 11 of the common commands of VMEPROM are described in detail in chapter 3 of the VMEPROM User s Manual Those commands which are CPU 6 hardware specific are described in the following paragraphs of this manual For a short description of one or all VMEPROM commands the HELP command can be used Enter HELP cr for a description of all commands or enter HELP command lt cr gt for a description of a particular command 4 SPECIAL
87. US is often abbreviated to DTB DATA TRANSFER BUS CYCLE A sequence of level transitions on the signal lines of the DTB that result in the transfer of an address or an address and data between a MASTER and a SLAVE There are seven types of data transfer bus cycles DTB An acronym for DATA TRANSFER BUS FUNCTIONAL MODULE A collection of electronic circuitry that resides on one 1014 board and works together to accomplish a task IACK DAISY CHAIN DRIVER A functional module which activates the interrupt acknowledge daisy chain whenever an INTERRUPT HANDLER acknowledges an interrupt request This daisy chain ensures that only one INTERRUPTER will respond with its STATUS ID when more than one has generated an interrupt request INTERRUPT ACKNOWLEDGE CYCLE A DTB cycle initiated by an INTERRUPT HANDLER that reads a STATUS ID from an INTERRUPTER An INTERRUPT HANDLER generates this cycle when it detects an interrupt request from an INTERRUPTER and it has control of the DTB INTERRUPT BUS One of the four buses provided by the 1014 backplane The INTERRUPT BUS allows INTERRUPTER modules to send interrupt requests to INTERRUPT HANDLER modules INTERRUPTER A functional module that generates an interrupt request on the INTERRUPT BUS and then provides STATUS ID information when the H 5 INTERRUPT HANDLER requests it
88. age was intentionally left blank 4 2 3 Access Time Selection To enable the us have a selectable access tim of fast and slow devices the PROM EPROM areas Speed selector This jumperfield provides different jumper settings as listed in Table 4 2 2 Figure 4 2 2 shows the location diagram of the speed selectors Table 4 2 2 EPROM Speed Selection Jumper Jumper Access Times Device Closed Closed ns Access on 11 on B11 Min Max Times ns 7 8 2 3 62 125 60 J 18 15 125 188 125 8 3 6 188 250 180 8 2 33 125 250 125 8 25 250 375 250 8 3 6 375 500 375 Default connection at Jumper 11 Location Diagram of the Speed Selectors Figure 4 2 2 4 15 4 2 4 Address of EPROM Area 2 The start address of the EPROM Area 2 is fixed mapped via a decoding PAL The size of this memory area depends on the memory capacity of the used devices Table 4 2 3 lists the address map for the different usable device types Table 4 2 3 Address Map of EPROM Area 2 Start End Used Total Address Address Device Capacity 0 0 000 0A3 FFF 2764 16 Kbytes 0 0 000 0A7 FFF 27128 32 Kbytes 0 0 000 OAF FFF 27256 64 Kbytes 0 0 000 FFF 27512 128 Kbytes 0 0 000 FFF 6264 16 Kbytes 0 0 000 OAF FFF 62256 64 Kbytes 4 2 5 The USER Area Summary
89. agram of the jumperfield is outlined in Figure 556 2 5 6 3 SYSFAIL The SYSFAIL signal can be connected to the H2 input of the PI T to force an interrupt on level 5 to the CPU The connection of the SYSFAIL signal to the H2 input is provided if a jumper is installed at jumperfield B24 between pin 8 and pin 9 location diagram of the SYSFAIL is shown in Figure 5 6 2 Figure 5 6 2 Location Diagram of the Special Function Jumpers p CL CO co wz ET n c Led 5 7 Th 1 unlimited Each of th in is in DO used terrupt D7 An active in signal e VMEbus specificat IRQ7 terrupter modules to ensure that modules places i and e seven VMEbus The VMEbus Interrupt Handler three special control number of interrupt sources in the system VMEbus cards in the system that interrupt vector acquisition is connected at signal IACK N passes th active IACK rough each N decoded level signal signal through its the in onto it is vector A function diagram of the own terrupt given in Figure 5 7 2 Acknowledge Cycle with an The related time values ar Figure 5 7 3 5 7 1 The Interrupt Ackn
90. al of the system monitor used The detailed hardware diagram of the interface is shown in Figure 4 3 12 The signal assignments are outlined in Table 4 3 8 default signal assignments during manufacturing are listed in Table 4 3 9 Table 4 3 8 Host Signal Assignments P3 P OUTPUT SIGNAL 1 Protective GND 2 X Transmit Data TXD 3 X Receive Data RXD 5 X Clear to Send CTS 7 X X Signal GND 9 X X Signal GND 18 20 X Clear to Send CTS Figure 4 3 12 Hardware Diagram of the Host Port TA LH s TR 4 GAD 0 J7 1488 Table 4 3 9 Default Jumper Settings at B5 PIN 2 15 3 14 4 13 5 127 7 10 8 9 9 8 0 7 1 6 2 5 3 4 4 3 5 2 6 1 Figure 4 3 13 Location Diagram of the Host Port my ay 2 arep Y s E a pcs 1 ikan ZR 4 3 5 2 Register Layout Device 6850 Host Address Mode Description 0 004 Status Register 0C004 W Control Register 0C0043 R Receive Data Register 0C0043 W Transmit Data Register 4 3 5 3 Baud Rate Selection Please see Chapter 4 3 1 The
91. als connected 1 Timer Real Time Clock Interrupts VMEbus Interface Firmware Power Requirements Operating Temp Storage Temp Relative Humidity Board Dimensions P2 conn 24 bit timer included in the PI ZE 58167 RTC with on board battery backup All on board devices are capable of generating interrupts to Local i request the CPU on a fixed level IRO nterrupts do not cause a VMEbus Jumper selectable VMEbus request level 0 3 Transfer Modes Al6 D8 D16 A24 D8 D16 Interrupt Handler 1 7 stat Single Level Arbiter SYSCLK Driver Power Monitor RESET Generator Bus Release Options ROBCLR RAT REC VMEPROM installed on each CPU 6 product 5 3 12 12V to 50 to 019 95 4 0 2 0 2 60 85 Double Eurocard Degrees C Degrees C non condensing 234x160mm 9 2 x 6 3 Memory Map of the SYS68K CPU 6 Products 000 000 ROM Initialization Vectors from SYSTEM EPROM 000 007 000 008 On Board DRAM 512 Kbytes 07 FFF 080 008 SYSTEM EPROM Area 128 Kbytes 09 FFF 000 USER EPROM Area 128 Kbytes or SRAM 64 Kbytes OBF FFF 041 2 RS 232 Interface Host P3 connector
92. banks with two sockets each are used one for boot up and one for user application programs 4 1 Area 1 During the power up phase the 68000 CPU reads two vectors from this EPROM area one is the Initial Stack Pointer Address 000000 5000003 and one is the Initial Program Counter Address 000004 000007 The data signals D0 D7 are used on the socket J75 Lower byte and the data signals D8 D15 are connected to the socket J76 Upper byte 4 1 1 Memory Organization of EPROM Area 1 For proper initialization the first eight addresses of EPROM Area 1 are downmapped to address 0 to 8 Figure 4 1 2 shows the location diagram of the EPROM Area 1 4 1 2 Usable Device Types of EPROM Area 1 EPROM Area 1 can be configured for the listed device types if the connections described in Table 4 1 1 are mad Device Organization Capacity EPROM 2164 8K x 8 16 Kbytes total EPROM 27128 16K x 8 32 Kbytes total EPROM 27256 32K x 8 64 Kbytes total EPROM 27512 64K x 8 128 Kbytes total Figure 4 0 1 Block Diagram of SYS68K CPU 6 Elus interface Connector 5 MAE i d 22 a s Power a Davaclinn P Gamato o DTAKK Generator BREAST E 1217 r TERMINAL P 95131 AREA Table 4 1 1 EPROM Area 1 Jumper Settings
93. cess the LED is lit to dark green when the bus is busy When waiting for the bus the LED can become dark HARDWARE USER S MANUAL This page was intentionally left blank APPENDICES Specification of the SYS68K CPU 6 Products Memory Map of the SYS68K CPU 6 Products Address Assignment and Register Layout of the I O Devices Componen For In t Part List of the SYS68K CPU 6 ternal Use Only Jumper Settings on the SYS68K CPU 6 Circuit Schematics Connector PIN Assignment of the SYS68K CPU 6 Glossary of VMEbus Terms P1014 Literature References Product Error Report This page was intentionally left blank Specification of the SYS68K CPU 6 Microprocessor Floating Point DRAM EPROM J Os Serial 68000 8 0 6 68000 12 5 CPU 6A 68010 12 5 MHz CPU 6VA 68010 12 5 MHz CPU 6VB 68881 FPCP 12 5 MHz only on CPU 6VB 512 Kbyte dynamic RAM Wait State at 8 MHz 1 Wait State at 12 5 MHz Distributed Hardware Refresh 128 Kbytes for the SYSTEM Area 128 Kbytes for the USER Area 3 RS232 interfaces built with 68B50 devices Strap selectable baud rate from 110 19200 baud Strap selectable I O signal assignment to the Parallel I O 3 25 pin 68230 PI T with 24 D Sub Connectors I O sign
94. data types Word and Long Integers Single Double and Extended Precision Real Numbers Packed BCD String Real Numbers 4 7 1 Interfacing to the 68881 62881 A20 A23 A16 A19 13 15 5 12 4 AD Main Processor Coprocessor 4 7 2 Data Format of the 68881 The 68881 contains seven data types supported by all arithmetic and transcendal operations Example FADD B 0 Byte Integer FADD W D2 FP3 Word Integer W FADD L BIGINT FP7 Long Word Integer L FADD S 3 14159 FP5 Single Precision Real S FADD D SP Double Precision Real D FADD X TEMP PTR A7 FP3 Extended Precision Real X FADD P 1 23 25 Packed Decimal Real P Figure 4 7 1 outlines the data format summary of the 68881 and Figure 4 7 2 shows the register layout of the internal register of the 68881 Please refer to the 68881 User s Manual for further details Figure 4 7 1 Format Summary of the 68881 8BITS BYTE INTEGER 0 16 BITS WORD INTEGER 0 32 BITS LONG INTEGER 30 22 0 SINGLE REAL SIGN OF FRACTION 62 51 0 EXP FRACTION SIGN OF FRACTION 94 80 63 0 SIGN OF MANTISSA IMPLICIT BINARY POINT 91 80 57 0 woer ii iii PACKED MANTISSA DECIMAL REAL IMPLICIT DECIMAL POINT 2 BITS USED ONLY FOR INFINITY OR NANS ZERO OTHERWISE SIGN OF EXPONENT SIGN OF MANTISSA UNLESS A BINARY TO
95. defining the following factors physical structure of the drive i e number of heads number of cylinders drive select number etc The bad block of the winchester drive The partitions to be used If this setup procedure is performed once for a particular drive the data is stored in the very first sector of the Winchester and is loaded automatically when the disk controller is installed in VMEPROM The driver for the ISCSI 1 may be installed by using the INSTALL command The following must be entered INSTALL 585 00 The default base address of the ISCSI 1 controller is A00000 in the standard VME address range Ihe SCSI 1 driver uses interrupts by default This cannot be disabled Please make sure that the interrupt daisy chain is closed so that the controller can work properly 5 Formats 5 Eight types of S records have been defined to accommodate the several needs of the encoding transportation decoding functions VMEPROM supports 0 S1 S2 S3 S7 S8 and S9 records 57 and S8 on load only An S record format module may contain S records of the following types 50 header record for each block of S records S1 A record containing code data and the 2 byte address at which the code data is to reside 52 record containing code data and the 3 byte
96. ed to one of the listed baud rates Table 4 3 1 The Baud Rate Selection Jumper B7 Connection No Connection PIN between between 10 and 11 10 and 11 143 5 9600 Baud 38400 Baud 2 4 6 4800 Baud 19200 Baud 2400 Baud 9600 Baud 7 1200 Baud 4800 Baud 14 600 Baud 2400 Baud 8 300 1200 Baud 13 150 Baud 600 Baud 9 110 Baud 440 Baud 12 60 Baud 240 Baud The baud rates of the terminal default during manufacturing host and remot interfac 4 17 connected to 9600 Baud ar in Figures 4 3 1 and 4 3 3 show the detailed hardware drawing the jumper location diagram Figure 4 3 1 Hardware Drawing of the Baud Rate Selection Parts 5 c90 Figure 4 3 2 Default Jumper Settings of B7 TO Se 1 20 3 8 5 16 1 0 10 2 9 3 8 4 7 5 6 6 5 7 4 8 6 6 3 9 2 20 o 0 1 Location Diagram of the Baud Rate Selection Parts Figure 4 3 3 gi J 88 ga 4 3 2 Timing of the ACIAs The ACIA is a controller device of the synchronous 6800 family Therefore the access cycle is controlled by the processor signals VMA VPA and the E signal To initiate the transfer the processor must receiv the VPA signal from the decoding log
97. emory is available it can only be used for data storage but not for tasking memory 1 4 5 Default EPROM Usage of VMEPROM System EPROM Memory Layout 80000 85000 88000 100000 BIOS Modules Kernel and File Manager EPROM Resident Installable Devices and Tables User Interface Debugging Tools Line Assembler Disassembler System Tools 2 5 568 6 2 1 Layout Address Device 000 000 E System EPROM Boot Vectors 000 007 000 008 512 Kbyte Local DRAM 507 FFF 080 000 System EPROM Area 509 FFF 0 0 000 5 User EPROM Area SOBF FFF 50 0 000 E Local I O Devices SOFF FFF 100 000 Address Range SFFF FFF 2 2 I O Devices The following table shows the on board I O devices and addresses Table 2 1 On board I O Devices Device Addres Terminal ACIA 0C008 Host ACIA 0C004 Remote ACIA 0C010 RTC 58167A 0C040 PI T 68230 50 000 68881 50 020 their 2 3 On board Interrupt Sources The following table shows the on board interrupt sources and levels which are defined by VMEPROM Table 2 2 On board Interrupt Sources DEVICE NTERRUPT LEVEL NTERRUPT VECTOR Abort Switch 7 6 AV6 PI T 5 AV5 Terminal ACIA 4 AV4 Remote ACIA 3 AV3 Ho
98. ended Precision Real Packed Decimal Strings 22 constants available in the on chip ROM including Pi e and powers of 10 Virtual memory machine operations Efficient mechanism for procedure calls context switches and interrupt handling This page was intentionally left blank 3 0 5 568 6 Every CPU 6 board contains VMEPROM a realtime multitasking monitor debugger It consists of a powerful realtime kernel a file manager and a monitor debugger with 68000 68010 line assembler disassembler The monitor debugger includes all functions to control the realtime kernel and file manager as well as all tools required for program debugging such as breakpoints tracing memory display memory modify and host communication VMEPROM supports several memory and I O boards on the VMEbus to take full advantage out of the file manager and the kernel functions A built in selftest checks all on board devices together with the on board memory This allows the detection of all failures on the board Memory initialization and test commands offers easy installation of global memory in the environment on the VMEbus The one line assembler disassembler is 68000 68010 compatible and supports all commands in the original mnemonic For reference to the I O devices of VMEPROM please s register 8 entitled BIOS Source Code Listing This page was
99. er Size signal 100 000 cycle If this board is the current VMEbus master low driven BBSY and the current access address is higher or equal to then a VMEbus transfer is initiated Figures 5 1 1 and 5 1 2 show the detailed timing diagrams of a read cycle and a write Tables 5 1 1 and 5 1 2 list all of the time values Table 5 1 1 Read Cycle followed by Write Cycle NOTE NUMBER PARAMETER IN NOTES 1 Axx and AMx valid and IACK high 35 B to AS low 2 DTACK low to invalid address or 0 C IACK low 3 AS high 40 B 4 DTACK low to AS high 0 5 AS to DS A skew 0 6 WRITE valid to DS A low 35 B 7 DS B high to invalid WRITE 10 B 8 DTACK high to active data bus 0 C 9 Dxx valid to DS A low 35 B 10 DTACK low to invalid data 0 C DS A to DS B skew 0 10 12 DTACK BERR low to DS A high 0 C 13 DS A high 40 B 14 DS B high to DS A low 40 B 1 5 DS B high 40 B 16 DS B high to DTACK high 0 D 17 DTACK BERR low to DS B high 0 C 18 DS A low to DTACK or BERR asserted 0 11 times given in nanoseconds By The MASTER must guarantee this timing between two of its outgoing signal C Ihe MASTER mus SLAVE before changing D This transitions is a guarantee incoming signal wait for the incoming signal until
100. er active Example CONFIG cr tive on the VMEbus 1 2 Or DISK DRIVER FORCE SCSI NSTALLE UART FORCE SIO1 2 U3 INSTALLED ASCU 1 2 boards available SCSI 1 boards available SIO 1 2 boards available DRAM boards with p if available which SCS troller arity to be So installs Winchester disks in the system Therefore come for during L signal is 4 2 FUNCTIONAL Perform Functional Test Format FUNCTIONAL This command performs a functional test on the local memory and on the bus interface of the CPU board NOTE This command is not designed for the user but used instead for internal purposes by FORCE COMPUTERS 4 3 SELFTEST Perform On board Selftest Format SELFTEST This command performs a test of the on board functions of the CPU 6 It may only be run if no other tasks are created If there are any other tasks no selftest will be made and an error will be reported The selftest tests the memory of the CPU 6 board and all devices on the board The following tests are performed in this order 1 I O test This function tests the access to and the interrupts from the MPCC If the MPCC cannot generate interrupts an error will be reported 2 Memory test on the memory of the current task The following procedures are pe
101. errupt after a programmable time period It may be used as a watchdog timer or for elapsed time measurements The timer is clocked by the 8 MHz frequency of the PI T clock input Table 4 4 1 The PI T Address Base Address 50 0000 Offset Reset Label Description Value 01 00 PITPGCR Port General Control Register 03 00 PITPSRR Port Service Request Register 05 00 PITPADDR Port A Data Direction Register 07 00 PITPBDDR Port B Data Direction Register 09 00 PITPCDDR Port C Data Direction Register OB OF PITPIVR Port Interrupt Vector Register OD 00 PITPACR Port A Control Register OF 00 PITPBCR Port B Control Register 14 PITPADR Port A Data Register 13 PITPBDR Port B Data Register 19 PITPAAR Port A Alternate Register 17 Port Alternate Register 19 PITPCDR Port C Data Register 1B PITPSR Port Status Register 21 00 PITTCR Timer Control Register 23 OF PITTIVR Iimer Interrupt Vector Reg 25 PITCPR Counter Preload Register 27 m 29 2B 2D PITCNTR m Count Register 2F 31 33 p 35 00 PITTSR Timer Status Register This page was intentionally left blank Table 4 4 2 Default Jumper Settings for 24 B24A
102. errupt Auto Vector 21 06C Level 3 Interrupt Auto Vector 28 070 Level 4 Interrupt Auto Vector 29 074 PI T Timer 30 078 Level 6 Interrupt Auto Vector 31 07 Abort Switch 32 080 qm THROUGH gt TRAP 40 15 Instruction Vectors 47 OBC 48 49 0C4 50 0C8 51 OCC 52 ODO 53 004 gt Unassigned Reserved 54 008 55 ODC 56 0 0 5 7 0E 4 58 0 8 59 OEC THROUGH 63 OFC Interrupt Vector Table of VMEPROM cont Vector Vector Number s HEX Assignment 64 100 THROUGH gt SIO 1 2 Interrupt Vectors 75 12 r 76 130 THROUGH gt ISIO 1 2 Interrupt Vectors 83 14 84 150 THROUGH gt User Defined 118 ID8 19 IDC Disk Interrupt Vector 120 1E0 4 THROUGH gt User Defined 255 BENCH BEN1BEG 802 V 01 BENLEN BENCH BEN2BEG D 8001 8002 8010 BEN2END BENCH BEN3BEG 8002 Benchmark Source Code APPENDIX F 1 DECREMENT LONG WORD IN MEMORY 10 000 000 TIMES LEA L 8010 MOVE L 10000000 AO SUBQ L 1 0 BNE S 020 RTS DS L 1 2 PSEUDO DMA 1K BYTES 50 000 TIMES MOVE L 50000 D2 DO 50000 TRANSFERS MOVE W SFF D3 EACH IS BYTES LEA L 8010 Al POINT
103. ess signal must be high 1 means that the corresponding address signal must be low 0 the jumper positions and the corresponding well as the jumper settings in the default conditions during manufacturing Figure 5 2 2 outlines the location diagram of the short I O parts Figure 5 2 1 The Short I O Comparator B23 8 9 ADRESS BUS D EMI HOHER x 14 415 8 i TIN 20 4 t GNO 2 Table 5 2 2 The Short I O Jumper Settings Jumper Positions Corresponding Default Jumper B23 Address Signal Setting 9 8 23 OUT 22 OUT 21 OUT 20 OUT A19 OUT 18 OUT 17 OUT A16 OUT 16 1 Start Address Short I O 5 FF0000 End Address Short I O FFFFFF Figure 5 2 2 Location Diagram of the Short Parts acm E971 3 CE on BH v e p D ov E he pu 5 3 The VMEbus Arbitration The VMEbus is designed to allow multimaster and multiprocessor application Only the current VMEbus master is able to force read or write transfers to and from other VME modules This requires a special handshake scheme to control which VME module receives bus mastership This controller module is the VMEbus arbiter arbiter res
104. f VMEPROM after power up Within this reserved byte there is one bit for each control switch For example bit 7 simulates SW1 bit 6 simulates SW2 bit 5 simulates SW3 and so on The bit is equal to one if the switch is off and equal to zero if the switch is on The switch settings are read in by VMEPROM after reset and control various options The following summary describes the software definition for each switch SW 1 If this switch is set to ON the RAM disk is initialized as defined by switch 3 and 4 after reset When the disk is initialized all data on the disk is lost SW 2 Not used SW 3 and SW 4 These two switches define the RAM disk which is used by default See Table 1 1 for a detailed description of these switches The default definition of these switches can be patched in the EPROMs for the user s convenience Please refer to the Appendix of this manual for a description of the memory locations to be patched SW 5 and SW 6 These switches define which program is to be invoked after reset Please refer to Table 1 2 for a detailed description The default definition of these switches can be patched in the EPROMs for the user s convenience Please refer to the Appendix of this manual for a description of the memory locations to be patched SW 7 If this switch i
105. g Max 32ms Table 4 9 2 BERR Jumper Settings B33 3 25 13 2 0 1 4 4 1 34 3 2 1 Time Out Min 8ms Max 16ms Table 4 9 3 BERR Jumper Settings B33 3 B25 2 1 B34 3 2 1 Time Out Min 2 5ms Max 3 0ms Table 4 9 4 BERR Jumper Settings D B33 3 B25 2 1 B34 3 2 1 Time Out Min 224ms Max 256ms Figure 4 9 2 Location Diagram of the BERR Jumperfield Mu En 8 U tu T gt a lt ML T alL 3 This page was intentionally left blank 5 0 THE VMEbus INTERFACE The SYS68K CPU 6 board contains a VMEbus interface which allows the following transfer modes A24 A16 The standard D D 16 16 D8 D8 addressing A24 and the short I O A16 are controlled via hardware because the A16 mode is only a subset of the A23 mode The address range of the short I O is the upper end of the address range of the 68000 68010 Sho rt I O address range SFF0000 to SFFFFFF All address modifier signals as well as the interrupt request lines are supported by the SYS68K CPU 6 5 1 Data Transf
106. gnments PIN ROW A ROW B ROW C NUMBER SIGNAL SIGNAL SIGNAL MNEMONIC MNEMONIC MNEMONIC 1 200 BBSY D08 2 201 BCLR D09 3 202 ACFAIL D10 4 D03 BGOIN D11 5 D04 BGOOUT D12 6 D05 BGlIN D13 7 D06 BG OUT e 214 8 207 BG2IN 015 9 GND BG20UT GND 10 SYSCLK BG3IN SYSFAIL 11 GND BG3OUT BERR 12 DS1 BRO SYSRESET 13 DSO BRIS LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTACK AMO A22 17 GND 21 18 5 2 20 19 GND AM3 A19 20 IACK GND A18 21 ACKIN A17 22 IACKOUT A16 23 GND 15 24 07 IRQ7 A14 25 A06 IRQ6 A13 26 A05 TRQ5 Al2 27 04 IRQ4 A11 28 A03 IRQ3 A10 29 A02 IRQ2 A09 30 01 1 08 3 12V 5V STDBY 12V 32 5V 5V 5V P2 Connector PIN Assignments PIN ROW A ROW B ROW C NUMBER SIGNAL SIGNAL SIGNAL MNEMONIC MNEMONIC MNEMONIC 1 5V PC4 2 GND PCS 3 PC2 6 4 PCT 5 GND 6 PB7 7 PB6 8 5 9 PB4 10 PB3 11 PB2 12 GND 13 5V 14 GND 15 16 17 H2 18 H1 19 GND 20 24 22 GND 23 4 24 25 2 26 1 24 28 GND 29 30 3d 5V GND 5V 32 5V 5V Terminal Connector Signal Assignments INPUT OUTPUT SIG
107. he ROR mode disabled the Release After Timeout function terminates bus mastership as soon as the timeout condition is entered If the ROR mode is enabled then bus mastership will be released if the timeout condition is entered and a Bus Request is pending With ROR enabled very short timeout can be selected without losing bus access efficiency Jumper B13 Pin 13 18 IN ROR is enabled OUT ROR is disabled Default condition is ROR is enabled 5 5 2 Release on Bus Clear RBCLR The RBCLR function allows the release of the bus mastership if an external arbiter drives the BCLR signal active 5 5 3 Release After Time Out RAT A timer chip with a changeable clock rate is installed on the SYS68K CPU 6 to provide a release of bus mastership at latest after timeout The maximum contiguous time available for the bus master state is defined by jumper settings at the jumperfields B25 B31 or 32 For the RAT times see Table 5 5 1 The location diagram of the RAT jumperfields are outlined in Figure 5 5 1 Table 5 5 1 Jumper Settings of B25 B31 and B32 for Connection at Time Jumperfield B25 5 o 13 0 2515 15 0 5 us 2 5 25 12 10 1 0 us 3 5 2 0 us 6 5 9 o Qe 1 4 0 us 4 5 32 0 us 8 5 4 o 1 default setup during manufacturing The minimum and maximum timings must be calculated as
108. he SYS68K CPU 6 board The RESET generator circuitry is operable if the power supply VCC is at least three volts The SYSRESET signal can be asserted low on any one of the following conditions a Front panel RESET switch toggled b Voltage sensor detects VCC below limit Programmable signal asserted d Execution of the RESET instruction by the microprocessor on the board The asserted SYSRESET signal will be held low for at least 200 milliseconds after removing the trigger condition in cases a and Cases keep SYSRESET active only during the time the trigger signal is active 6 1 The Voltage Sensor The RESET generator has a voltage sensor included Power up reset is provided by this sensor as soon as the supply voltage VCC has reached three volts SYSRESET will be asserted if VCC is less than 4 8 volts on the board when the jumper B36 is removed This jumper is inserted at delivery When the jumper at B36 is inserted SYSRESET will be asserted if VCC is less than 4 5 volts SYSRESET will stay asserted at least 200 milliseconds after the supply voltage reaches 4 8 volts with jumper B36 inserted B36 should be inserted for normal operation it can be removed for test purposes 6 2 The SYSRESET Condition The on board RESET generator drives the IEEE 1014 bus SYSRESET signal if the jumper connection at B300 pin 1 and 2 is inserted The SYS68K CPU 6 board moni
109. he breakpoint should be skipped E int bpcocc MAXBP 4 of times the breakpoint is already skipped LWORD bptadr temp breakpoint address WORD bptinst temp breakpoint instruction int bptocc of times the temp breakpoint should skipped int bptcocc of times the temp breakpoint is already skipped ud char bptcmd 11 temp breakpoint command char outflag output messages yes 1 no 0 char 8 Name buffer name char namebd MAXNAME 40 Name buffer data WORD errcnt error counter for test LWORD times timee start end time LWORD pregs N REGS storage area of processor regs WORD tflag trace active flag WORD tcount trace count WORD tacount active trace count WORD bpact break point active flag LWORD savesp save VMEprom stack during GO T etc char VMEMSP 202 Master stack handle w care char VMESSP 802 supervisor stack handle w care char VMEPUSP 802 vmeprom internal user stack LWORD f fpreg 3 8 floating point data regs LWORD f fpcr FPCR reg LWORD f fpsr FPSR reg LWORD f fpiar FPIAR reg lt BYTE save 0x3c FPSAVE for null and idle BYTE cleos 2 clear to end of screen parameter BYTE cleol 2 clear to end of line parameters y char u_prompt 10 user defined prompt sign long save save
110. ic When the CPU is synchronized to the E clock signal the VMA signal is asserted to signal the I O devices that the transfer is beginning The synchronization requires additional time 1000ns maximum The timing diagrams illustrating the best and worst cases are shown in Figures 4 3 4 and 4 3 5 Tables 4 3 2 and 4 3 3 list the related values Table 4 3 2 ACIA Timing best case No Description Min Max Unit 1 AS low 800 ns 2 AS asserted to VPA 30 80 ns asserted 3 AS inactive to VPA 30 80 ns inactive 4a VMA asserted 8MHz Processor 850 1000 ns clock frequency 4b VMA asserted 12 5MHz 600 750 ns Processor clock frequency to VMA delay 150 Table 4 3 3 Timing worst case No Description Min Max Unit 1 AS low 2000 ns 2 AS asserted to VPA 30 80 ns asserted 3 AS inactive to VPA 30 80 ns inactive VMA asserted 8MHz Processor 850 1000 ns clock frequency 4b VMA asserted 12 5MHz 600 750 ns Processor clock frequency 5 VPA to VMA delay 1000 ns Figure 4 3 4 Timing Diagram best case AS F VPA VMA Figure 4 3 5 Timing Diagram worst case 4 3 3 Terminal Port The RS232 interface is used to communicate via Port 1 connector P4 with a standard terminal transmission format i
111. ides only in slot number one of each VMEbus environment because the bus arbitration is daisy chained from slot 1 to 2 to 3 so on Each system has only one arbiter The arbiter may be on a special card or it may be located a CPU board To provide a minimal system overhead there are thr different arbiters defined in the VMEbus specification a The Four Level Bus Arbiter with a Priority Scheme b The Four Level Bus Arbiter with a Round Robin Scheme c The One Level Bus Arbiter A global description of an arbitration scheme is given in the next chapter 5 3 1 Arbiter Options The arbiter is used to control the DTB arbitration system There are three options a An option PRI Priority Arbiter always assigns the bus on a fixed priority basis where each of the four different Bus Request BRX signals are assigned fixed priorities from the highest BR3 to the lowest BRO b An option RRS Round Robin Select Arbiter assigns the bus on a rotating priority basis If the current DTB Master is level n then the highest priority will be given to level n 1 and proceed sequentially from there Single Level Arbiter only honors requests BR3 and relies on the daisy chain structure for priority determination The bus grant daisy chain structure is outlined in Figure 5 3 1 while Figure 5 3 2 shows the global DTB timing d
112. inactive 7 Data valid before DTACK 10 asserted Figure 4 6 1 Access Cycle without Refresh Request AS ACCESS REQUEST 55 CYCLE DTACK OuT DATA vau 4 67 4 6 3 Refreshing of the DRAMs The Dynamic RAM refresh is accomplished by performing a memory cycle at each of the 128 row addresses at an interval of 2ms RAS Only Refresh results in a substantial reduction of operating power For real time operations the refresh is fully asynchronous to the LOCAL and VMEbus accesses A maximum delay of 300ns for an access is required when a refresh request is pending at the same time as an access request because the refresh has the highest priority The refresh is organized in 128 steps every 2ms This requires a minimum time delay if access requests are pending and refresh is in process The repetition rate for a refresh cycle is 15 microseconds The detailed timing diagram of the refresh is shown in Figure 4 6 2 Figure 4 6 2 The Global Refresh Timing Diagram REFREQ ACCESREQ ACCESS REFCYCLE 4 6 4 Summary of the DRAM Start Address End Address Boundary Access Modes Usable Data Bits Access Time 000008 507 512 bytes 5080000 Byte or Word Read or Write DO D7 and D8 D15 150ns min 165ns typ 520ns max with Refresh 4 7 Floating Point Coprocessor 68881 The 688
113. ing signal D This is a guarantee that the INTERRUPTER will not change the incoming signal until the INTERRUPT HANDLER changes its outgoing signal Ihe INTERRUPT HANDLER is guaranteed this timing between two of its incoming signal transitions Figure 5 7 3 The Interrupt Vector Acquisition Timing Diagram ACKNOWLEDGE CYCLE y t i ten AS 20 WRITE He iw Vt OUTPUTS FROM IN TERRUPT HANDLER 050 ruv nr t Y 2 000 007 n FE amp z 255 DTACK m 5 7 2 The VMEbus Interrupt Handling All of the on board interrupts have a higher priority in the internal interrupt acknowledge daisy chain than the VMEbus interrupts at the same interrupt level The VMEbus interrupt signals IRQl IRQ7 from the VMEbus are received continuously A special jumperfield B15 as shown in Figure 5 8 4 Figure 5 8 5 outlines the location diagram is used to enable disable each IRQ signal separately Table 5 8 2 shows the combinations of the jumper settings An inserted jumper means that the incoming IRQ signal from the VMEbus will be acknowledged by the on board CPU Therefore a noninserted jumper is equivalent to a disabled IRQ signal Figure 5 7 4 VMEbus Interrupt Hardware Diagram Table 5 7 2 VMEbus Interrupt Jumper Settings
114. inter 42 int _aci assigned input file ID 430 int _aci2 assigned input file ID s 432 int len last error number 434 int _sfi spool file id 436 BYTE flg task flags bit 8 command line echo 437 BYTE _slv directory level 438 char fec file expansion count 439 char _sparel reserved for future use 43A char _csc 2 clear screen characters 43C char psc 2 position cursor characters 4 char sds 3 alternate system disks 441 BYTE _sdk system disk 442 char ext XEXT address 7 446 _ XERR address 44A char emd command line delimiter 44B BYTE _tid task id 44 char ecf echo flag 44D char output column counter 44E char mmf memory modified flag 44F char prt input port 4 450 char spu spooling unit mask 451 BYTE unt output unit mask char unit 1 port T 453 char _u2p unit 2 port 4 454 char _u4p unit 4 port Efi 455 char u8p unit 8 port 4 456 char spare2 26 reserved for system use T KOK KK KK RK RK K K KO KOK KR KK KK KK KK KK KK KK KK KK IK He Hk He ck kx VMEPROM variable area KK KK RK RR k K K K KOK KOK KOK OK K KOK KOK OK K Ck KK Ck OK KOK K KOK KOK KOK OK KOK K KOK K KOK K KOK K
115. ion Switch The upper switch on the front panel of the SYS68K CPU 6 board see Figure 6 4 2 is the RESET switch Toggling it provides a reset of all on board devices independent from the jumper options A reset of the board must be performed by toggling the RESET switch or by asserting the SYSRESET backplane signal The red HALT LED turned on signals the HALT state of the processor This state will b ntered e g if a double bus fault occurs The HALT LED is also on while the RESET generator drives the RESET and HALT inpul signals of the processor to low After reset the red light must turn off and the green LED will turn on The RESET jumperfields are shown in Figure 6 4 1 and Figure 6 4 2 outlines the front panel of CPU 6 6 5 The Programmable Reset Option With the jumper B37 inserted the SYSRESET signal will be driven low without effecting the local devices as long as the signal PRGRES connected to B24 pin 15 will be held low Figure 6 4 2 Front Panel of the CPU 6 L HN RESET Button ABORT Button HALT Indicator P5 REMOTE Interface Connector P4 TERMINAL Interface Connector P3 HOST Interface Connector Run Halt Indication LED In Halt condition or during RESET the LED will be illuminated in red During run condition on the board without VMEbus accesses the LED is green During run condition on the board with VMEbus ac
116. ion Switch 6 5 The Programmable Reset Option 6 6 The Run Halt Indication LED TABLE OF CONTENTS cont d re re re re re re re re re re re re re re re re re re re re re re re re re re re re re re re O List of Figures Photo of SYS68K CPU 6 1 OCK Diagram of the SYS68K CPU 6 CPU Clock Speed Jumper Settings Lo cati on Bl Lo ock cati J on Diagram of QN P Lo cati on Diagram Diagram Lo cati on Diagram Lo cati on AA N N ES wN w l l l d O ONDA Hardware De P faul Diagram mper Settings of B7 Diagram of the Baud Rate Selection ACI ACT P arts A Timing A Timing Hardware Lo cati on Hardware Lo cati on Configura gt qa au 99 CO CO CO CO CO CO CO Transparent Mode Diagram of the Host Port Diagram of the Host Port Diagram of the PI T Diagram of the PI T Diagram of the CPU Clock Speed umperfields B10 and B21 SYS68K CPU 6 S of the EPROM Area 1
117. ive to Data invalid 10 60 Figure 4 5 2 Read Cycle Timing Diagram S s SZ 0 VALID 4 5 4 Interrupt Assignment The RTC can be used to force an interrupt to the on board CPU This is provided if a jumper is inserted in the jumperfield B200 Otherw ise no interrupt can be forced and line is always disabled The RTC interrupt request level the interrupt request is fixed at level 6 the highest maskable interrupt level The jumper location diagram of the RTC circuit is shown in Figure 4 5 3 The interrupt control logic on the board decodes the RTC Interrupt Request level IRQ6 and forces the autointerrupt vector after the interrupt has been acknowledged on that level This vector is fixed and reserved on the board specially for the RTC The long word stored at address 000078 vector no 30 represents the RTC interrupt handling routine start address 4 5 5 Summary of the Access Address 0C0401 50 042 Access Mode Odd Byte Only Read and Write cycles Usable Data Bits D7 Interrupt Level 6 auto interrupt vectoring Interrupt Vector Fixed 430 Address 000078 Figure 4 5 3 Location Diagram of the 4 6 The Dynamic RAM The on board RAM area is used for the CPU s exception vector table as scratch pad for
118. k Speed Jumperfields ling Lad a gl Ut 3 1 68000 Hardware Description The 68000 provides 23 address signals 16 data signals and 10 control signals which build the fully asynchronous bus interface A Data Transfer Acknowledge DTACK and a Bus Error BERR input signals error ha Seven inl the CPU if a bus cycle can be aborted correctly or if an S been detected 8 data 7 addr 32 bit 32 bit 16 bit terrupt request signals are encoded and driven to the CPU to provide fast and effective interrupt acknowledgment for real time applications Features of the 68000 registers 32 bit ss registers 32 bit supervisor stack pointer user stack pointer status register 16 Mbyte direct addressing space Hardware signals provide detection of program and data fetches as well as of supervisor and user mode 56 powerful instruction types with 14 addressing modes 5 main data types Memory mapped I O Asynchronous bus interface 3 2 The Vector Table of the 68000 Vector Address 5 Dec Hex Space Assignment 0 0 000 SP Reset Initial SSP 4 004 SP Reset Initial PC 2 8 008 SD Bus Error 3 12 00C SD Address Error 4 16 010 SD Illegal Instruction 5 20 014 SD Zero Divide 6 24 018 SD CHK
119. ll local devices the serial I O interfaces the Real Time Clock and the PI T are initialized after boot up The VMEPROM is configured to work independent of hardware connections to the REMOTE and HOST ports as well as to the Parallel Interface All jumpers of the different SYS68K CPU 6 board versions are set during manufacturing so that no jumper setting change is required in order to boot the board 3 0 INSTALLATION IN THE RACK All SYS68K CPU 6 boards are preset to the default condition and can be mounted immediately into a VME rack only at slot 1 CAUTION A Switch off power before installing the board to avoid electrical damages of the components B The board contains a special ejector on the front panel To ensure proper installation the board must plugged in and the screws of the front panel must be turned Unplug every other VMEbus or VMXbus board to avoid conflicts D Remove all connections on the P2 backplane to avoid conflicts 3 1 Power On If the board is correctly installed the switches are in the correct positions the terminal is correctly configured and under power the power for the VMEbus rack can be switched on First the HALT LED must show a red light then after one to three seconds At the it must change to a green light same time the following message is displayed on the terminal lt k k k k k k k lt k k l
120. n EFRONUSR A NI AREA 2 0 HARDWARE OVERVIEW The SYS68K CPU 6 boards contain the powerful 68000 68010 CPU with 512 Kbytes of dynamic RAM a maximum of 256 Kbytes of EPROM and powerful I O devices One RS232 interface Port 2 connector P4 is used in conjunction with a standard terminal to enter and debug user programs under the control of VMEPROM A second RS232 interface may be used for up download of user programs and data RS232 interface Port 3 connector P5 is a universal port printer or other device support an additional terminal A Parallel Interface and Timer Chip PI T 68230 is used interface various hardware on the P2 connector and to work as the time base for VMEPROM The SYS68K CPU 6VB contains 68881 with 12 5 MHz clock applications In addition the Real Time Clock time base because of its on board battery backup a All of the I O devices the DRAM on the local bus Memory and I O extension is provided using VMEbus interface The block diagram of SYS68K CPU 6 shows functional areas in detail and the EPROM areas are local Port 1 connector P3 The third 58167A provides constant Floating Point Coprocessor te to support floating point ted the the This page was intentionally left blank 3 0 6 8000 68010 MICROPROCESSOR DESCRIPTION The
121. n can reside on an external RR 2 or RR 3 board on the VMEbus In both cases the simulated front panel switches of the CPU 6 board have to be set so that the application program is stalled after VMEPROM is booted If you want to put your application on the CPU 6 the jumper settings and access times have to be changed to reflect the size and access times of the EPROMs used Please refer to the Hardware User s Manual for a detailed description In both cases the user stack is located at the top of the tasking memory and the supervisor stack is located within the task control block The user stack has a size of 50 bytes No register ar predefined 1 1 Replacing the User Interface The following section describes how an application program can be put into EPROMs replacing the user interface of VMEPROM This method gives nearly 96 Kbytes of EPROM space to the application Two general ways are possible a Removing 11 Setups If no setups are required the application can be put into EPROMs at address 8000 relative to the begin address of the EPROM The entry address is 8046 which is the first byte after the tables described in Appendix H cache of address 58046 is started in user mode directly after th kernel has been initialized The supervisor stack is located in the tack control block size is 500 bytes and the user stack is located at the top of the task s
122. nd is loaded automatically when the disk controller is installed in VMEPROM The driver for the WFC 1 may be installed by using the INSTALL command The following must be entered INSTALL W 86400 The default base address of the WFC 1 controller has to be set to B01000 To do so the address comparison for 24 bit address has to be enabled VMEPROM supports the termination interrupt of the WFC 1 controller If you want to use the WFC 1 with interrupts the corresponding jumper has to be set to enable the interrupt Please refer to the User s Manual of the WFC 1 controller for a detailed description of the address setup and the termination interrupt A5 SYS68K ISCSI 1 Disk Controller VMEPROM supports up to two floppy disk drives and three Winchester disk drives together with the ISCSI 1 disk controller The floppy drives have to be jumpered to drive select 3 and 4 and can be accessed as disk number 0 and 1 out of VMEPROM The floppy drives are installed automatically when a ISCSI 1 controller is detected by the CONFIG command or after RESET when the simulated front panel switch of the CPU 6 is set to detect the hardware configuration Usable floppy drives must support 80 tracks side and must be double sided double density The step rate used is 3 ms The Winchester drives are not installed automatically The FRMT command must be used for VMEPROM and for
123. oco 043 oco 080 RS 232 Interfac Terminal 4 connector 082 101 RS 232 Interfac Remote P5 connector 103 401 2 Real Time Clock 42F OEO 001 PI T Parallel Interface Timer OEO 035 OEO 200 FPCP Floating Point Coprocessor OEO 300 Reset off OEO 380 Reset on 100 000 VMEbus A24 D16 D8 FFO 000 VMEbus A16 D16 D8 FFF Address Assignment and Register Layout of the I O Devices Address I O Device 50 0 041 ACIA 1 68B50 50 0 080 ACIA 2 68B50 50 0 101 ACIA 3 68B50 50 0 401 58167 50 0 001 PI T 68230 50 0 200 68881 DEVICE 6850 ACIA Terminal Address Mode Description 0C0080 R Status Register 0C0080 W Control Register 0C0082 R Receive Data Register 0C0082 W Transmit Data Register DEVICE 6850 ACIA Host Address Mode Description 0C0041 R Status Register 0C0041 W Control Register 0C0043 R Receive Data Register 0C0043 W Transmit Data Register DEVICE 6850 ACIA REMOTE Address Mode Description 0 0101 Status Register 0 0101 W Control Register 0C0103 R Receive Data Register 0C0103 W Transmit Data Register
124. or by setting the CPU 6 and RESET Please refer to the command description in detailed description of the CONF the VMEPROM User s Manual for a and BP commands The base addresses of all ports of an SIO 1 2 board which must be Specified with the BP command are as follows SIO port 4 1 first SIO 5 00000 2 5 00040 3 5 00080 4 5 000 0 5 5 00100 6 5 00140 1 second SIO board B00200 2 B00240 3 5 00280 4 5 002 0 5 5 00300 6 5 00340 VMEPROM supports up to two serial I O boards These can be either the SIO 1 2 board or the ISIO 1 2 board or a mixture of both Please note that the first board of every type must be set to the first base address using one 510 1 board and one ISIO 1 board the base address of the boards have to be set to SIO B00000 5 4 5960000 SYS68K ISIO 1 2 These serial I O boards are set to the address 5960000 in the standard VME address range by default VMEPROM anticipates this board at this address This is to say that no changes need to be made to the default setup An optional second board may be used Ihe address must be set to 980000 when using the second board Please refer to the SYS68K ISIO 1 2 User s Manual for a description of the base address setup Before using the driver for the ISIO 1 2 board the driver
125. orted from the terminal to enable the transmission If the terminal is configured to the setup listed above please connect the 25 pin D sub connector to the terminal with a cable which supports all of the listed signals This page was intentionally left blank 2 0 THE DEFAULT HARDWARE SETUP All VMEbus and local interfaces are configured to be used immediately without any changes This results in a default hardware setup which may conflict with other boards also installed in the rack 2 1 The VMEbus Setup The following signals are driven received from the SYS68K CPU 6 Driven Received From SYSCLK X Clock Module BR3 Requester Logic to Single Level Arbiter BG3OUT x DTB Arbitration ACFAIL Local PI T and Jumperfield SYSFAIL Local PI T and Jumperfield SYSRESET X X Power Monitor and RESET Generator CAUTION The on board single level arbiter is enabled and reacts on every BR3 SYS68K CPU 6 is configured as a slot 1 board 2 2 The Local Setup local DRAM is initialized from location 8 to 4000 This area is under the control of and reserved for the VMEPROM firmware which is installed on each SYS68K CPU 6 board All other RAM cells on the local DRAM and on the VMEbus will not be accessed and will remain unmodified The initialization and test of memory areas can be carried out via VMEPROM commands A
126. ot display the described text the terminal setup may be wrong Please check this setup If the board does not boot up correctly please do not place the board back into the plastic box without replacing the metal foil on the back or putting the board into an antistatic bag or components may be destroyed Please do not install other VMEbus boards into a rack which includes the following functions before the jumper settings have been changed SYSCLK Driver Arbiter Please do not solder the battery included in the shipment into the PCB prior to reading the installation paragraph and prior to testing the board functions with the SELFTEST command Please do not connect I O signals at P2 connector prior to cross checking the SYS68K CPU 6 P2 I O signal assignment to avoid component damages The RESET instruction of the local CPU does not reset the local I O devices only the VMEbus SYSRESET will be forced if the jumper setting is in the default condition 5 568 6 HARDWARE USER S MANUAL This page was intentionally left blank 5 GENERAL INFORMATION HARDWARE OVERVIEW H CO CO CO H E 1 2 3 4 4 1 4 2 4 3 4 4 4 5 68000 68010 MICROPROCESSOR DESCRIPTION The 68000 Hardware Description The Vector
127. owledge signal the of as shown i board on the board IACKOU re slot 1 to T signal quester the data bus and a global the cu the n Figure 5 8 1 the VMEbus and has not produ control logic m signal tion defines seven interrupt request signals signals which allow an IACK rren In signals may be shared by two or more Interrupt Acknowledge only one of the unlimited number ts interrupt vector onto the data bits Daisy Chain of informs all of the urrent read cycle t VMEbus master terrupt Acknowledge is an This In Ihe that it can plac Interrupt Acknowledge timing of an N ACK signal If a board receives an ced an interrupt on the ust bypass the to inform the next board N if ACK th interrupt Daisy Chain is Interrupt Interrupt Vector Acquisition is given in The On Board IACK Daisy Chain To provide full VMEbus compatibility as an output signal if the SYS and if no on board interrupt high performance master multiprocess ing transparent interrupt handling of the on board and off board The low driven motherboards and runs down the signal the is pending systems IACK signal 68K CPU 6 board is the current VMEbus This allows full because given in Table 5 7 1
128. quest 2 S cup 5721 Bus Grant 4 27 SYSCLK 6 25 BCLR 7 24 8 9 10 21 11 20 123 2218 14 17 15 Bus IRQ enable 1 14 4 5 32 2 13 12 4 11 gt 59 7 08 B23 Short I O Address 5 9 Modifier ation Jumpers TTS 7 jH Y 5 Local Configuration Jumpers Jumper Description Default Schematics See field Page B25 Error Timer 7 10 qom 4 83 11 14 B33 Error Timer 2 7 D3 B34 Error Timer B25 Bus Mastership Timer 5 8 dt em 5 21 B31 2 3 7 D2 B32 B8 Clock Selectors 2 2 Al 9 2 2 E B10 8MHz 2 3 2 A2 Su 4 5 B10 12 5MHz 1 2 5 6 11 EPROM Access Time 1 8 2 4 4 14 Selection 4 5 B26 EPROM Size Selection 12 8 CS 4 2 10 11 4 9 7 8 27 1 12 8 4 8 3 10 4 9 6 7 21 DTACK Generated 8MHz 1 5 6 C2 3 1 for RAM 12 5MHz 4 5 16 Battery STDBY 4 4 56 B35 Read Modify Write 3 A2 4 6 Jumper Location Diagram of the Local Configuration Jumpers This page was intentionally left blank WARNINGS A B C D E F G H the board does not boot up correctly please do not remove any jumpers If an error has been found by VMEPROM please refer to the VMEPROM User s Manual for a detailed error description If the terminal does n
129. re described in the VMEPROM User s Manual 1 2 Features of VMEPROM Line assembler disassembler with full support of all 68000 68010 instructions Over 20 commands for program debugging including breakpoints tracing processor register display and modify S record up downloading from any port defined the system Time stamping of user programs Built Benchmarks Disk support for RAM disk floppy and Winchester disks Either SYS68K WFC 1 or SYS68K ISCSI 1 may be used VMEPROM also allows disk formatting and initialization Serial I O support for up to two SIO 1 2 or ISIO 1 2 boards in the system _ EPROM programming utility using the SYS68K RR 2 3 Doards Full Screen Editor More than 30 commands to control the PDOS kernel file manager x Complete task management redirection to files or ports from the command line Over 100 system calls to the kernel are supported Data conversion functions Task management system calls Terminal I O functions File management functions 1 23 After power up the 68000 68010 retrieves th and program counter from address tions are the first eight bytes o are mapped down to address 0 for a Control is so transferred to the B he necessary hardware initialization of time kernel is started and the user inl loca power up all real Power Up
130. reset 0C0427 21 RTCRRES RAM reset 0C0429 29 RTCSTAT Status bit 0C042B 2B CRTCGO GO command 0C042D 2D RTCSINT Standby interrupt 0C042F 2 RTCTEST Test mode Table 4 5 2 Write Time Values Note A Number Parameter Min 1 Axx valid and IACK high to AS low 10 3 AS high 30 4 AS low to CSRTC active 0 5 AS active 0 6 AS invalid to UDS high 0 40 7 AS inactive to CSRTC inactive 0 40 8 AS low to LDS low WRITE 10 130 9 AS low to DTACK low 1000 2000 11 AS inactive to DTACK inactive 5 45 12 AS active to WRITE low 10 150 13 AS inactive to WRITE inactive 10 70 14 Data valid to Data Strobes active 0 15 As inactive to Data invalid 10 45 Figure 4 5 1 Write Cycle Timing Diagram S e 1 4 5 0 8 DTACK DATA Table 4 5 3 Read Time Values Note A Number Parameter Min 1 Axx valid and IACK high to AS low 10 3 AS high 30 4 AS active to CSRTC low 30 60 5 AS low 1800 2500 6 AS inactive to UDS inactive 10 60 7 AS inactive to CSRTC inactive 0 40 8 AS active to LDS valid 10 130 9 AS low to DTACK low 1800 2500 11 AS inactive to DTACK inactive 5 45 12 WRITE high to AS active 10 14 Data valid to DTACK active 10 15 DTACK inact
131. rformed 1 Byte Test 2 Word Test 3 Long Word Test All passes of the memory test perform pattern reading and writing as well as bit shift tests If an error occurs while writing to or reading from memory it will be reported This ensures that VMEPROM could initialize the PI T 68230 properly and the interrupts from the PI T are working 3 Clock Test If the CPU does not receive timer interrupts from the PI T 68230 an error will be displayed CAUTION During this process all memory is cleared Example SELFTEST VMEPROM Hardware Selftest T O CES Luces passed Memory test passed CLOCK test passed 2 5 RESTRICTIONS ON STANDARD COMMANDS 5 1 Baud Port The BP command is not able to alter the baud rate of any on board ports because the hardware does not allow it INTRODUCTION TO VMEPROM 5 VMEbus Board Setup VMEbus Memory SYS68K SIO 1 SIO 2 SYSOSR od ane SYS68K WFC 1 Disk Controller SYS68K ISCSI 1 Disk Controller oP QO N 5 Formats Bl 5 Types B2 S Record Example System RAM Definitions Task Control Block Definitions Interrupt Vector Table of VMEPROM Benchmark Source Code Special Locations Generation of Applications in EPROM H1 General Information edes
132. s and port format changes are shown in the software manual of the system monitor used The detailed hardware diagram of the interface is outlined in Figure 4 3 8 The signal assignments are listed in Table 4 3 6 and the default signal assignments during manufacturing are listed in Table 4 3 7 Figure 4 3 8 Hardware Diagram of the Remote Port J5 4 1488 471 12 96 70 4 1489 a LL 55580 51 mE S2 Figure 4 3 9 Location Diagram of the Remote Port Table 4 3 6 Remote Connector Signal Assignments P5 PIN NPUT OUTPUT SIGNAL 1 2 X Receive Data RXD 3 X Transmit Data TXD 4 5 X Request to Send RTS 6 7 Signal GND 8 X Data Carrier Detect DCD 9 Signal GND 19 20 X Clear to Send CTS Table 4 3 7 Default Jumper Settings at 1 PIN 2 19 3 18 4 17 5 16 7 8 6 13 1 10 2 9 3 O 8 4 2 5 Ot 6 6 5 0 5 7 O 4 8 3 9 2 20 1 4 3 4 2 Register Layout Device 6850 Remote Address Mode Description 0C0101 R Status Register 0C010 W Control Register 0C0103 R Receive Data Register 0C0103 W Transmit Data Register 4 3 4 3 Baud Rate Selection Please see Chapter 4 3 1 The Baud Rate Selection 4 3 4 4
133. s initially preset as follows 8 data bits 1 stop bit No parity Asynchronous protocol The terminal must be set to these conditions The terminal interface can interrupt the 68000 CPU on level 4 The forced interrupt vector is the auto interrupt vector 28 5000070 4 3 3 1 The I O Signal Assignment Further details of control functions and port format changes are shown in the software manual of the used system monitor The detailed hardware diagram of the interface is given in Figure 4 3 6 default signal assignments during manufacturing are listed in Table 4 3 4 Figure 4 3 6 Hardware Diagram of the Terminal Port J5 TAXDI 1489 J7 ATST 42V 1488 J6 z 12V Lnd 1489 4 5 1488 5 GND Table 4 3 4 Terminal Connector Signal Assignments OUTPUT SIGNAL 1 2 X Receive Data RXD 3 X Transmit Data TXD 4 5 X Request to Send RTS 6 d Signal GND 8 X Data Carrier Detect DCD 9 Signal GND 1 9 20 X Clear to Send CTS The location diagram of the terminal interface parts Figure 4 3 7 is shown in This page was intentionally left blank Table 4 3 5 Default Jumper Setting at B3 2 19 3 18 4 17 5 16 7 8 TOS 13 6213 1 10 2 9 3 8 4 7 5 5 7 0 4 8
134. s mechanical support for boards inserted into the backplane ensuring that the connectors mate properly and that adjacent boards do not contact each other It also guides the cooling airflow through the system and ensures that inserted boards do not disengage themselves from the backplane due to vibration or shock SYSTEM CLOCK DRIVER A functional module that provides a 16 MHz timing signal on the UTILITY BUS SYSTEM CONTROLLER BOARD A board which resides in slot 1 of a 1014 backplane and has a SYSTEM CLOCK DRIVER a DTB ARBITER an IACK DAISY CHAIN DRIVER and a BUS TIMER Some also have a SERIAL CLOCK DRIVER a POWER MONITOR or both UAT A MASTER that sends or receives data in an unaligned fashion SLAVE that sends and receives data unaligned fashion UTILITY BUS One of the four buses provided by the 1014 backplane This bus includes signals that provide periodic timing and coordinate the power up and power down of 1014 systems WRITE CYCLE A DTB cycle used to transfer 1 2 or 4 bytes from a MASTER to a SLAVE The cycle begins when the MASTER broadcasts an address and address modifier and places data on the DTB Each SLAVE captures this address and address modifier and checks to see if it is to respond to the cycle If so it stores the data and then acknowledges the transfer The MASTER then terminates the cycle
135. s set to on VMEPROM tries to execute a startup file after reset The default filename is SYSSTRT and the file must reside on disk 2 SW 8 If this switch is set to on VMEPROM checks the VMEbus for available hardware after reset In addition VMEPROM waits for SYSFAIL to disappear from the VMEbus The following hardware can be detected Contiguous memory starting at 80000 ASCU 1 2 SIO 1 2 SIO 1 2 5 51 1 WFC 1 Please refer to Section 4 2 of this manual for details Table 1 1 RAM Disk Usage SW 4 SW 3 OFF OFF RAM DISK AT TOP OF MEMORY 32 Kbyte OFF ON RAM DISK AT 700000 512 Kbyte ON OFF RAM DISK AT A0000 32 Kbyte ON ON RAM DISK AT 800000 512 Kbyte Table 1 2 Program After Reset SW 6 SW 5 OFF OFF VMEPROM OR USER PROGRAM at same location OFF ON AUTOBOOT PDOS ON OFF USER PROGRAM AT A0000 ON ON USER PROGRAM AT 800000 Table 1 3 Default Control Switch Setting Switch Position Function Default SW1 ON Initialize RAM disk on RESET OFF OFF Use old RAM disk initialization SW2 Not used SW3 RAM disk address OFF SWA OFF 544 SW3 OFF OFF RAM ISK AT TOP OF MEMORY 32KB OFF ON RAM ISK AT 700000 512KB ON OFF RAM 5 5 0000 32 ON ON RAM DISK AT 800000 512KB SW5 Startup program to be executed after RESET OFF SW6 OFF SW6 SW5 OFF OFF VMEPROM OFF ON AUTOBOOT PDOS ON OFF USER PROGRAM AT A0000 ON ON USER PROGRAM AT
136. st ACIA 2 AV2 2 4 Off board Interrupt Sources VMEPROM supports several VMEbus boards Since these boards are interrupt driven the level and vectors must be defined for VMEPROM to work properly Table 2 3 shows the default setup of the interrupt levels and vectors of the supported hardware of the hardware setup of the boards Appendix of this manual The supported with the base addresses and the interrupt In order for summarized in this table For a detailed description please refer to the I O boards together level and vector are these boards to work properly with VMEPROM the interrupt vectors listed may not be used Table 2 3 Off board Interrupt Sources Board Interrupt Level Interrupt Vector Board Base Address 510 1 4 64 75 5 00000 SIO 1 2 4 76 83 960000 WFC 1 3 19 B01000 SCSI 4 19 A00000 ASCU 1 2 7 5802000 3 THE CONCEPT OF VMEPROM 3 1 Getting Started After power up or after RESET has been pressed VMEPROM prints a banner showing the version and revision being used and prints the prompt If the above message does not appear check the following 1 Baud rate and character format setting of the terminal default upon delivery of the SYS68K CPU 6 is 9600 Baud 8 data bits 1 stop bit no parity 2 Cable connection from the SYS68K CP
137. t k lt k lt k lt lt x lt x lt x k k k k k k k k k k k k k amp amp k amp k amp k amp k amp k X k X k k k k k lt lt X x lt x lt VMEP ROM BYS68K CPU 6 Version 2 1 24 88 c FORCE COMPUTERS and Eyring Research k k k CK C CC CC lt k lt lt x lt x lt x lt x lt x k lt k lt k lt k k k k k k k k k k C amp k amp k amp k lt k lt X lt X X X X x lt The next entry the terminal keyboard may be some carriage returns which will result in a display of an equivalent number of question marks 3 2 Correct Operation To test the correct operation of the CPU 6 the following command has to be typed in SELFTEST After a matter of a few seconds the following messages will appear on the screen Memory test passed I O test passed Clock test passed Any errors will be reported as they are designated If an error message is displayed please refer to register 6 Introduction to VMEPROM and the command description SELFTEST The next steps are under User s direction 4 0 JUMPERS SETTINGS ON THE SYS68K CPU 6 Jumper Page Jumper Page field Coordinate Description field Coordinate Description B1 1 1 2 B23 4 B3 1 4 2 24 7 4 E 2 B5 1 D1 E 2 B24A 7 3 2 B7 3 E 2 B25 7 C3 E 6 B8 2 1 6 26 8 3
138. tails that are important for the PI T handling 4 4 4 Summary of the PI T Access Address 0E0001 0E0035 Access Mode Odd Byte Only Read and Write transfer Usable Data Bits DO D7 Interrupt Level 5 auto interrupt vectoring Interrupt Vector Fixed 29 Address 000074 4 5 The Real Time Clock The on board Real Time Clock 58167A can be used as a calendar a real time counter and for time measurements Features of the Real Time Clock 1 10000 of second through month counter 56 bits of RAM with comparator to compare the real time counter to the RAM data Interrupt Output with 8 possible interrupt signals Power Down mechanism disables all input and output signals E Status register to indicate rollover during a read cycle 32 768 Hz crystal oscillator Four year calendar no leap year 24 hour clock Battery backup during main power down 4 5 1 Register Layout The access address of the RTC register is 0C0401 to 0C042F Only single byte transfers to and from the on the data bits DO D7 are allowed All of the RTC registers are directly addressable and read writeable as shown in Table 4 4 1 4 5 2 Access Timing The read write timing diagram and the time values are given in Figures 4 5 1 and 4 5 2 and in Tables 4 5 2 and 4 5 3 The RTC is a metal gate CMOS circuit which has an access time of approximately 1100ns This requires a special delay of the
139. ters are sent directly from the terminal to odification is given in Figure the all b P3 is is used connector is carried out figured terminal terminal ters in 1 to receive data on th and echo it via th The SYS68K CPU 6 the Transparent Mode the CPU o0 5 lt and returns to the system stop character sequenc the SYS68K CPU 6 board sends to the host compute rminal ot use the for is given the tointerrupt vector is the last character Ix t drive the CTS signal to high state ection from P3 pin 5 to pin 20 has to be hardwired SYS68K CPU 6 board terminal and host computer interface must be jumpered equally IA remains unaltered becaus this ACIA for the transfer th mat and the system monitor the Software User s Manual 68000 CPU on level 2 The 26 000068 Figure 4 3 10 Configuration with a Host Computer TERMINAL Figure 4 3 11 Interfacing to a Host Computer in the Transparent Mode x e 8 a sin m m ow d x F wu n m m OF ux x x F 4 E tn m s 4 3 5 1 I O Signal Assignment Further details of control functions and port format changes are shown in the VMEPROM user s manu
140. tors the SYSRESET backplane signal if B37 is not inserted default condition The following reactions will be performed if SYSRESET is sensed asserted low The board stops driving bus signals except for SYSRESET The arbiter will be reset The processor and peripherals installed the board will be reset special case with the RESET instruction When SYSRESET is cleared high normal operation will begin The jumper at B300 connecting pins 1 and 2 is inserted on delivery The local reset option obtained by removing this jumper is for test purposes local reset asserted during a bus access can lead to a bus error or other malfunctions The local reset does not reset the on board arbiter In further explanations the jumper is presumed inserted and the RESET generator drives the SYSRESET signal according to the default configuration If the jumper 14 is inserted then the RESET signal is suppressed This option is for test purposes only 6 3 Reset Instruction of the The RESET instruction of the 68000 and 68010 microprocessors is designed to reset peripherals under program control without resetting the processor itself This instruction is fully supported by the SYS68K CPU 6 board and the SYSRESET signal will be driven active for 512 CPU clock cycles when B37 is inserted RESET jumperfields are outlined in Figure 6 4 1 6 4 The Reset Funct
141. uffer wrap around mask define 1 lt lt 2 2 characters port 2 define MPZ 2048 memory pagesize define MBZ MMZ MPZ memory bit map size define MBZ 8 number of map bytes 27 define FSS 38 file slot size Z define 2 TCB index define 4 index define 2 event 41 event 2 define TQS TQE 2 scheduled event define TBZ TQS 2 4 TASK entry size define BPS 256 bytes per sector 74 define NRD 4 number of RAM disks struct SYRAM 000 char bios address of bios rom 004 char mail mail array address m 008 unsigned int rdkn ram disk 00A unsigned int rdks ram disk size 00C char rdka ram disk disk address 010 char _bflg basic present flag 011 char directory flag 012 int _f681 68000 68010 flag 014 char sram run module BSSRAM 018 1 reserved for expansion x7 System RAM Definitions 1A 1C 20 21 22 24 25 26 28 38 48 58 68 78 82 84 86 88 98 A8 AC BO B4 B6 B8 B9
142. ust be equal for proper operation The default Bus Request level during manufacturing is 3 Therefore the connections to be made are as listed in Figure 5 3 5 The detailed timing diagram if an arbitration cycle is outlined in Figure 5 3 3 Table 5 3 1 lists the time values Table 5 3 1 Time Values of the Slave Bus Arbitration No Description Min Max T BGXIN low to BBSY active 25 65 2 BBSY low to BRX active 10 65 3 BBSY low to BGOUT inactive 10 45 4 BGXIN low to BGXOUT low 35 50 NOTE All times given in nanoseconds Figure 5 3 3 Bus Arbitration Timing Diagram BBSY ON BOARD BGX OUT BBSY FROM VME BUS Figure 5 3 4 Jumperfield for the Bus Arbitration BEA Sy SG 10 GAD E BLEBS BLOKBEl Im 16 L 285 1 iih Figure 5 3 5 Arbiter and Bus Request Level Jumper Selection on B13 with External Arbiter BR3 BR2 BR1 BRO Or Q 1 1

Force Computers SYS68K / CPU-6 Manual

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