SH67P54 - SinoWealth！
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1. Supply Control Circuit LCD SEG1 E segment driver OSC Duby Le amp scan SEG34 Control output 50 _ DUTYO LPS1 DUTY1 Built in special LCD power control for LCD power modulation Address 0D O S2 Set LCD SEG9 SEG30 to be LCD segment output or scan output ports 0 LCD segment output 1 scan output ports O S1 Set PORTD as LCD segment or I O PORT 0 1 0 PORT 1 LCD segments 50 Set PORTC as LCD segment or I O PORT 0 PORT 1 LCD segments When LVD is set to 1 and the divider resistors is 270kO the LCD voltage power will be degraded to about 90 of VDD It is designed to reduce extra LCD contrast control output pins Then the LCD can be fitted automatically for different voltage levels by the software 10 3 LCD on off Control and Divider Resistors Setting Address 07 LCDON LCD on off switch 0 LCD off 1 LCD on LCDON When LCD is off COM amp SEG output GND in LCD application LVD If LCD is off and LCD is shared to LED application COM output Vpp and SEG output GND LCD RLCD1 RLCD0 LCD divider resistors setting Power 0 0 R1 R2 R4 270kQ Default Supply 0 1 R1 R2 RA 90kQ Control 1 0 R1 R2 R4 30kQ Circuit 1 1 R1 R2 R3 RA 10kQ When large LCD panel is used user can set the v2. Functional Description 1 CPU The CPU contains the following functional blocks Program Counter PC Arithmetic Logic Unit ALU Carry Flag CY Accumulator Table Branch Register Data Pointer INX DPH DPM and DPL and Stacks 1 1 PC The PC is used for ROM addressing consisting of 12 bits Page Register PC11 and Ripple Carry Counter PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO The program counter is loaded with data corresponding to each instruction The unconditional jump instruction JMP can be set at 1 bit page register for higher than 2K The program counter cans only 4K program ROM address Refer to the ROM description 1 2 ALU and CY The ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI Decimal adjustments for addition subtraction DAA DAS Logic operations AND EOR OR ANDIM EORIM ORIM Decisions BAO BA1 BA2 BAZ BNZ BC BNC Logic Shift SHR The Carry Flag CY holds the ALU overflow that the arithmetic operation generates During an interrupt service or CALL instruction the carry flag is pushed into the stack and recovered from the stack by the RTNI instruction It is unaffected by the RTNW instruction 1 3 Accumulator AC The accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with the ALU data is transferr
3. 2A 1 69 47 3950 98 2 4017 86 1 69 SH67P54 Music Table 2 Following is the music scale reference table for channel 1 or channel 2 under OSC 32 768kHz Up to 4 octaves are possible Music scale data for 32 768kHz OSC and SELO SEL1 0 LSFR LSFR C1 6 C1 0 Ideal C1 67 C1 0 Real freq C2 14 C2 8 C2 14 2 8 freq 0D 261 63 12 260 06 0 60 34 277 18 26 277 70 0 19 52 293 66 36 292 57 0 37 4B 311 12 35 309 13 0 64 17 329 63 2D 327 68 0 59 5D 349 23 6F 348 60 0 18 77 369 99 7B 372 36 0 64 6E 392 00 6C 390 10 0 49 39 415 30 63 420 10 1 16 73 440 00 0D 442 81 0 64 66 466 15 34 468 11 0 42 4C 493 88 52 496 49 0 53 19 523 25 4B 528 52 1 01 32 554 35 17 546 13 1 48 65 587 33 5D 585 14 0 37 4 622 24 TT 630 15 1 27 0C 659 26 6E 655 36 0 59 0A 698 46 39 712 35 1 99 1E 739 97 73 744 73 0 64 11 783 99 66 780 19 0 49 2C 830 59 4C 819 20 1 37 1D 880 00 19 862 32 2 01 29 932 31 32 910 22 2 37 3E 987 77 65 963 77 2 43 50 1046 48 4A 1024 00 2 15 1108 71 15 1092 27 1 48 62 1174 63 2A 1170 29 0 37 Ce
4. RESET Schmitt trigger input PORTA 0 PORTA 3 PORTB D loH 2mA PORTA 0 PORTA 3 PORTB D loL 2mA PORTA 1 2 or Alarm output loH 5mA PORTA 1 2 or Alarm output loL 5mA SEGx to be output port or LED SEGx IOH 1mA SEGx to be output port or LED SEGx loL 1mA LED 100 LED COMx loL 2 5mA LCD COMx LCD SEGx the voltage variation of V1 V2 V3 V4 is less than 0 2V Pull high Resistor PORTA D Pull low Resistor PORTA D WDT Current LCD Lighting lt lt lt lt lt lt lt lt lt lt lt lt LCD Driving on resistor RLCD1 RLCDO 0 0 LCD voltage divider RLCD1 RLCDO 0 1 resistor RLCD1 RLCDO 1 0 RLCD1 RLCDO 1 1 39 DC Electrical Characteristics SH67P54 5 0V GND OV TA 25 fosc 32 768kHz foscx is not used LCD voltage divider resistor 270kQ 1 4 LCD bias unless otherwise specified Parameter Conditions Operating Voltage Operating Current All output pins unload execute NOP instruction LCD off WDT off Operating Current All output pins unloaded OSCX as system oscillator foscx 8MHz Execute instruction Standby Current All output pins unload HALT mode WDT off LVR off Standby Current All output pins unload HALT mode OSCX as system oscillator foscx 8MHz WDT off Standby Current 1 A
5. used as output ports data must be written to bit O of the same addresses 358 36D LCD RAM could be used as data memory if necessary When the STOP instruction is executed the LCD will be turned off but the data of LCD RAMs keep the same value before executing the STOP instruction 10 1 LCD Control Register Address 15 DUTY1 0 LCD duty control 0 0 1 8 duty 1 4 bias 0 1 1 6 duty 1 3 bias 1 0 1 5 duty 1 3 bias 1 1 1 4 duty 1 3 bias LPS1 LPSO LCD frame frequency control LCD clock is divided from OSC so LCD frame frequency will change in proportion to the variation of OSC frequency LPS1 LPSO 0 1 1 0 IN 1 8 DUTY MODE 16Hz 8Hz IN 1 6 DUTY MODE 17 0Hz 8 5Hz IN 1 5 DUTY MODE 17 0Hz 8 5Hz IN 1 4 DUTY MODE 16Hz 8Hz FRAME Frequency OSC 32 768kHz FRAME Frequency OSC 262kHz IN 1 8 DUTY MODE IN 1 6 DUTY MODE IN 1 5 DUTY MODE IN 1 4 DUTY MODE 1 1 ONE FRAME When the CPU is in STOP mode the COMx and SEGx are pulled low It can easily be woken up by a keyboard scan Port interrupt When the CPU is in HALT mode the COMx and SEGx are normal It can easily be woken up by base timer timer0 or port interrupt 18 SH67P54 10 2 LCD Power VoD Power Switch LCDON Power Degrade LVD 9 LCD COM1 LCD common Power driver COM8
6. Vpp SEG SEG x q A LL GND UNSELECT GND UNSELECT UNSELECT Example 1 4 Duty 4X10 Dots COM1 GND COM2 COM3 COM4 3 SEG1 GND SEG2 SEG3 SEA SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG5 COMx amp SEGx refer to the driving amplified output of COMx 8 SEGx SEG6 GND SEG7 SEG8 SEG9 SEG10 71 GND 11 Read ROM DATA Address 1A 1B 1C 1D Remarks ROM Data table address data register ROM Data table address data register ROM Data table address data register ROM Data table address data register The register consists of a 12 bit write only PC address load register RDT 11 RDT 0 and a 16 bit read only ROM table data read out register RDT 15 RDT 0 To read out the ROM table data users should write the ROM table address to RDT register first high nibble first then low nibble then after one instruction the right data will put into RDT register automatically write lowest nibble of address into 1A will start the data read out action 26 SH67P54 12 Programmable Sound Generator PSG PSG has channel1 and channel2 The function block diagram is shown as follows
7. OTP Writer SDA The recommended steps are as following 1 The jumpers are open to separate the programming pins from the application circuit before programming the chip 2 Connect the programming interface with OTP writer and begin programming 3 Disconnect OTP writer and short these jumpers when programming is complete For more detail information please refer to the OTP writer user manual 44 Application Circuit for reference only AP1 VDD 3 0V OSC Crystal oscillator 32 768kHz Code Option OSCX Ceramic oscillator 455kHz PORTB I O PORTA 1 PORTA 2 ALARM output LCD Internal LCD 1 8 duty 1 4 bias 8x30 1 8 duty 1 4 bias SH67P54 100p 455kHz BUZZER PORTA 2 OSCXI 10kQ RESET 104 OSCXO o lt PORTB 5 2 t osco 32 768 2 OSCI 12p TEST GND AP2 VDD 5 0V OSC RC oscillator 262kHz Code Option LCD Internal LCD 1 4 duty 1 3 bias PORTA PORTB 0 External interrupt 4X34 1 4 duty 1 3 bias OSCXI 10kQ V V RESET 104 OSGXO rs PORTA PORTAO 10 lt PORTE 3 930kQ 9560 NN OSCI 102 GND i TEST 45 Ext int SH67P54 AP3 VDD 5 0V OSC Crystal oscillator 32 768kHz Code Option OSCX RC osci
8. The timer can be programmed in several different system clock sources by setting the Timer Mode register TMO Timer 0 reads and writes operations follow these rules Write Operation Read Operation Low nibble first High nibble first High nibble to update the counter Low nibble follows 7 2 Timer0 Mode Register TMO The 8 bit counter counts prescaler overflow output pulses TMO are 4 bit registers used for timer control as shown in Table 1 The register selects the input clock sources in the timer Table 1 Timer0 Mode Registers 02 Prescaler Clock Source 12048 System clock 1512 System clock 128 System clock 32 System clock 18 System clock 14 System clock 12 System clock 1 PORTA O Falling Edge 0 oOoO o o o TMO 3 control function 0 without Auto Reload function 1 Auto Reload function 15 SH67P54 8 Base Timer MCU has base timer which the clock source is OSC Low frequency oscillation Crystal 32 768kHz or RC 262kHz After MCU is reset it counts at every clock input signal When it counts to FF right after next clock input counter counts to 00 and generates an overflow This causes the interrupt of base timer interrupt request flag to 1 Therefore the base timer can function as an interval timer periodically generating overflow output as every 256th clock signal output The tim
9. amp PORTD COM 4 1 COM 8 5 shared DRIVER with SEG 31 34 Vi V2 V3 V4 SH67P54 Pad Description Designation Description 3 4 5 6 PORTD 3 0 Bit programmable I O shared with Segment 8 5 7 8 9 10 PORTC 3 0 Bit programmable I O shared with Segment 4 1 11 12 13 14 PORTB 3 0 Bit programmable I O Vector interrupt 15 16 17 18 PORTA 3 0 Bit programmable I O PORTA 1 PORTA 2 shared with PSG output 20 GND Ground BDO Bonding option 0 21 VDD Power supply BD1 Bonding option 1 22 OSCXI Oscillator X input 23 OSCXO Oscillator X output 24 OSCI Oscillator input 25 OSCO Oscillator output 26 TEST Test pin must be connected to GND 27 RESET Reset input No internal pull high 29 30 31 32 V 4 1 Connected with external LCD divided resistor 38 37 36 35 COM 4 1 Common signal output for LCD display COM5 SEG34 COM6 SEG33 39 40 41 42 Com7 SEG32 COM8 SEG31 Common segment signal output for LCD display 43 64 SEG 30 9 Segment signal output for LCD display Shared with scan output Total 58 Pads 2 bonding Pads OTP Programming Pin Description OTP program mode Designation Shared by Description VDD VDD Programming Power supply 5 5V VPP RESET Programming high voltage Power supply 11 0V GND GND Ground SCK OSCI Programming Clock input pin SDA 0 Programming Data pin
10. CHANNEL1 osc CH1 CLK T MIXER MPX PSG OSCX CH2 CLK CHANNEL2 The PSG function provides four sub functions for wide applications Programmable Sound Two channels create programmable sound Every channel can be programmed as follows Enable Disable every channel sounds Select every channel sound frequency Two channel sounds are mixed into one PSG output The PSG output can be controlled at 4 volume levels Fine Noise PSG can provide wide band noise The wide band noise volume can be controlled at 4 volume levels Alarm PSG can provide many alarm functions by the software The alarm carrier frequency can be programmed individually The alarm volume can be controlled at 4 volume levels Remote Control The remote control is the only expandable application for PSG sound Since the remote control frequency is 56 13kHz or 37 92kHz the software can select the sound frequency 12 1 PSG Sub Block Diagram MPX block diagram SELO SEL1 p OSC 12 PSG CLOCK SLECTOR CLocK OSCX 16 gt Clock Source OSC clock PSG clock OSC OSC 32 768kHz 32 768kHz OSC 262kHz 262kHz OSC 2 OSC 32 768kHz 16 384kHz OSC 262kHz 131kHz OSCX OSCX 1 8MHz 1 8MHz OSCX 455kHz 455kHz OSCX 16 OSCX 1 8MHz 112 5kHz OSCX 455kHz 28 4kHz The MPX block selects 4 clock so
11. AC lt Mx 8 Ac ANDM 00110 1bbb xxx xxxx 8 SHR 11110 0000 000 0000 Instruction Code 3 AC 0 CY AC shift right one bit Function Flag Change ADI 01000 1111 xxx lt ADIM 01001 iiii XXX XXXX lt 58 3 01010 1111 xxx xxxx lt 1 SBIM 01011 iiii Xxx lt Mx 1 01100 1111 Xxx Xxxx lt Mx ORIM 01101 iiii xxx xxxx lt Decimal Adjust Mnemonic 01110 1111 Xxx xxxx Instruction Code Mx 4 Function Flag Change DAA X 11001 0110 xxx xxxx AC Mx lt Decimal adjust for add CY DAS X 11001 1010 xxx xxxx CY AC Mx lt Decimal adjust for sub 37 Transfer Instruction Mnemonic Instruction Code Function SH67P54 Flag Change LDA X B 00111 Obbb xxx xxxx AC lt Mx STA X B 00111 1bbb xxx xxxx Mx LDI Xl 01111 iiii xxx AC Mx lt Control Instruction Mnemonic Instruction Code Function Flag Change BAZ X 10010 Xxx PC 0 BNZ 10000 xxxx Xxx XXXX PC 0 BC 10011 XXXX PC if CY 1 BNC 10001 XXX
12. When switching from OSCX to OSC the user should switch clock first then turn off OSCX If switching from OSCX to OSC and turning off OSCX in one instruction the OSCX turn off control will be delayed for one instruction cycle automatically to prevent CPU operation error Following is the timing of system clock switching OSCX turn off OSCX turn on osexo QUA BU Sys High Low frequency operation High frequency operation frequency operation Warm up time Switch from OSCX to OSC Switch from OSCX to OSC Figure 1 Timing of System Clock Switching 11 SH67P54 4 6 System Clock The system clock varies as the clock source changes The following table shows the instruction execution time according to each frequency of the system clock source OSCFREQ 32 768kHz OSC 262kHz OSC 455kHz OSCX 2MHz OSCX 8MHz OSCX Cycle time 122 07 us 15 27 us 8 79 us 2 us 0 5 us 5 Low Voltage Reset LVR The LVR function is to monitor the supply voltage and generate an internal reset in the device It is typically used in AC line applications or large battery where large loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum 5 1 Functions of the LVR Circuit The LVR function is selected by Code Option The LVR circuit has the following functions It generates an internal reset signal when VDD lt VLVR I
13. nibble TimerO load counter register high nibble Reserved BitO 1 Select LCD divider resistors Bit2 LCD on off PORTA PORTB PORTC PORTD BitO 1 Bonding option BDO is weakly pulled high BD1 is weakly pulled low Bit2 3 PORTA 1 amp PORTA 2 as PSG output or 1 0 PORT Bit0 Set PORTC as LCD segment Bit1 Set PORTD as LCD segment Bit2 Set segment as output port Bit3 LCD Voltage degrade Table Branch Register Pseudo index register Data pointer for INX low nibble Data pointer for INX middle nibble Data pointer for INX high nibble External interrupt PORTA O rising falling edge set Bit1 PORTB PORTC interrupt rising falling edge set Bit2 Port pull high low set Bit3 Port pull high low enable control Turn on OSCX oscillator Bit1 CPU clocks select 1 OSCX 0 OSC Bit3 OSCX type selection BitO 1 Select LCD DUTY 1 8 1 6 1 5 or 1 4 Bit2 3 LCD frequency control PULLEN The Configuration of System Register continue SH67P54 Remarks PORTA input output control PORTB input output control PORTC input output control PORTD input output control ROM Data table address data register ROM Data table address data register ROM Data table address data register ROM Data table address data register Bito 2 Watchdog timer control Bit3 Watchdog timer overflow flag Res
14. reading this alarm control register the user can read the corresponding output envelope frequency the 1Hz 4Hz 8Hz and 32Hz Alarm Control Register OSC 32 768kHz or 262kHz Alarm output control DC envelop 1Hz output 4Hz output 8Hz output 32Hz output Figure Alarm modulation output for OSC 32 768kHz or OSC 262kHz DUUM UD E coro H H H I TT PSG as Remote Control The remote control is only an expandable application for PSG sound The user can select the CH1 as tone output and the CH2 will create alarm frequency envelope signal When PSG channel is programmed in the ALARM mode the programmer can set ALARM mode register to 0000
15. shifted out that program execution may enter an abnormal state The ROM can address 4096 X 16 bits of program area from 000 to FFF 2 1 Vector Address Area 000 to 004 The program is sequentially executed There is an area address 000 through 004 that is reserved for a special interrupt service routine such as starting vector address Address Instruction Remarks 000 JMP Jump to RESET service routine 001 JMP Jump to External interrupt service routine 002 JMP Jump to TimerO service routine 003 JMP Jump to Base Timer service routine 004 JMP JMP instruction can be replaced by any instruction Jump to PORT interrupt service routine SH67P54 3 RAM Built in RAM contains of general purpose data memory and system register Because of its static nature the RAM can keep data after the CPU enters STOP or HALT 3 1 RAM Addressing Data memory and system register can be accessed in one instruction by direct addressing The following is the memory allocation map System register and I O 000 01F 370 377 Data memory 020 16F LCD RAM space 300 348 Segment scan output RAM 358 36D 3 2 Configuration of System Register System Register 00 1F 370 377 RAM Map Remarks Interrupt enable flags Interrupt request flags Mode register Prescaler Base timer mode register TimerO load counter register low
16. 1 1 1 48 5 67 54 Ordering Information SH67P54H CHIP FORM SH67P54P LQFP 64 49 SH67P54 Package Information LQFP64 Outline Dimensions BODY SIZE 10 10 unit inches mm J SHHHHHHHHHHHHHI See Detail F al Seating Plane 1 1 0 063 MAX 1 60 MAX 0 002 MIN 0 006 MAX 0 05 MIN 0 15 MAX 0 055 0 002 1 40 0 05 0 009 0 002 0 22 0 05 0 004 MIN 0 008 MAX 0 09 MIN 0 20 MAX 0 394 BASIC 10 00 BASIC Symbol Dimensions in inch Dimensions in mm 0 394 BASIC 10 00 BASIC 0 020 BASIC 0 50 BASIC 50 SH67P54 Data Sheet Revision History Von G pe Package information update Feb 2009 Change Ordering Information Dec 2008 1 Change Ordering Information 2 Change QFP64 package information Jan 2005 51
17. 1A 78 11 71 34 70 22 62 69 60 45 44 52 40 0B 09 25 z wo o N N N N N O O O 30 SH67P54 12 2 Function Description PSG as sound generator The programmable sound is one of the 4 working modes The software designer can select up to 16 clock sources as PSG clock And then select the CH1 and CH2 frequency divided value that is controlled by the value of REG C1 6 C1 0 or C2 14 C2 8 The user can select the 4 volume level controlled by VOLO VOL1 The music tone can output both PSG and PSG The user also can control the OCT1 OCT2 bit that shifts the music tone octaves Example 1 CH1EN CH2EN 1 Example 2 CH1EN 0 CH2EN 1 OSCX 1 8MHz SELO SEL 1 1 OSCX 1 8MHz SELO SEL1 1 So PSG clock 112kHz Switch clock 28kHz So PSG clock 112kHz Switch clock 28kHz Vol Clock 112kHz Vol Clock 112kHz TIME SLOT TIME SLOT III cmien o 1 _ 111111111111111 vOL Control VOL level 4 VOL lewel 4 VOL level 3 VOL level 3 VOL level 2 VOL level 2 ll III VOL level 1 Example 3 1 C
18. 20 19 OSCXI 30 29 40 39 38 137 136 35 34 33 32 131 SH67P54 VDD BD1 BDO SEG24 43 142 41 SEG23 SEG22 SEG21 SEG20 47 SEG19 48 SEG18 49 SEG17 150 SEG16 51 SEG15 52 SEG14 53 SEG13 54 SEG12 SEG11 SEG10 57 SEG9 VVIHOd c W1YOd 0 gq13Od V 8lHOd c 81HOd 193S 0 9LYOd 29851 93S c O1HOd v93S 91Y0d S93S 0 01YOd 993S L Q LHOd 193S c Q LHOd 893S Q LHOd Block Diagram RESET 4 GND OSCS SH67P54 OSCI OSCO OSCXI OSCXO gt ROM 4096 X 16 gt RAM 384 X 4 SH6610D gt 8 BIT TIMER0 CPUCORE 4 0 INTO PORTA 8 EXTERNAL INT PORTA 1 PSG PORTA 2 PSG PORTA 3 PORTB 3 0 PORTC 3 0 EF 353 PORTD 3 0 SEG 30 9 SEG 8 1 shared H PORT LCD SEGMENT gt RAM SCAN REGISTER PSG COMMON DRIVER CPU OPERATING VOLTAGE LCD VOLTAGE GENERATOR with PORTC
19. 302 32A 303 32B 304 32C 305 32D 306 32E 307 32F 308 330 309 331 30A 332 30B 333 30C 334 30D 335 30E 336 30F 337 310 338 311 339 312 33A 313 33B 314 33C 315 33D 316 33E 317 33F 318 340 319 341 31A 342 31B 343 31C 344 31D 345 31E 346 31F 347 22 SH67P54 LCD 1 8 Duty 1 4 Bias COM1 8 SEG1 30 Address Address 300 328 301 329 302 32A 303 32B 304 32C 305 32D 306 32E 307 32F 308 330 309 331 30A 332 30B 333 30C 334 30D 335 30E 336 30F 337 310 338 311 339 312 33A 313 33B 314 33C 315 33D 316 33E 317 33F 318 340 319 341 31A 342 31B 343 31C 344 31D 345 SEGS 30 is used as scan output port Address Address Address Address 358 35E 364 36A 359 35F 365 36B 35A 360 366 36C 35B 361 367 36D 35C 362 368 35D 363 369 23 10 5 LCD Waveform 1 8 DUTY 1 4 BIAS SELECT UNSELECT 1 V2 V3 COM v4 GND SELECT UNSELECT vi 2 V4 GND SEG Example the output waveform of 1 8 duty and 1 4 bias MT v2 COM1 GN
20. 40 C to 85 C in the operational sections of this specification is not implied or intended Exposure to the absolute maximum rating Storage Temperature 55 Cto 125 conditions for extended periods may affect device reliability DC Electrical Characteristics VDD 3 0V GND OV TA 25 C fosc 32 768kHz foscx is not used LCD voltage divider resistor 270kQ 1 4 LCD bias unless otherwise specified Parameter in i Conditions Operating Voltage All output pins unload execute instruction LCD off WDT off All output pins unloaded OSCX as system oscillator foscx 4MHz Execute NOP instruction All output pins unload HALT mode WDT off LVR off LCD off All output pins unload HALT mode OSCX as system oscillator foscx 4MHz WDT off All output pins unload STOP mode LCD off WDT off PORTA PORTD RESET Schmitt trigger input PORTA PORTD Operating Current Operating Current Standby Current gt Standby Current gt Standby Current 1 gt Input High Voltage 0 7 X VDD VDD 0 3 Input High Voltage 0 8 X VDD VDD 0 3 Input Low Voltage 0 3 0 3 X VDD Input Low Voltage 0 3 0 2 X VDD Output High Voltage 0 7 X VDD Output Low Voltage 0 2 X VDD Output High Voltage 0 7 X Output Low Voltage 0 2 X VDD Output High Voltage VDD 0 6 Output Low Voltage 0 6 Output High Voltage VDD 0 6 Output Low Voltage GND 0 6
21. 80 00 9 878 91 0 12 13 0 56 932 31 13 937 50 0 56 1B 0 09 987 77 1B 986 84 0 09 5A 0 46 1046 48 5A 1041 67 0 46 56 0 52 1108 71 56 1102 94 0 52 37 0 24 1174 63 37 1171 88 0 24 3D 0 44 1244 48 3D 1250 00 0 44 76 0 79 1318 48 76 1308 14 0 78 31 0 67 1396 88 31 1406 25 0 67 46 0 02 1479 95 46 1480 26 0 02 1A 0 35 1567 95 1A 1562 50 0 35 69 0 41 1661 18 69 1654 41 0 41 25 0 12 1759 96 25 1757 81 0 12 17 0 56 1864 62 17 1875 00 0 56 5D 1 69 1975 49 5D 2008 93 1 69 3B 0 46 2092 96 3B 2083 33 0 46 6E 1 47 2217 41 6E 2250 00 1 47 5C 0 24 2349 27 5C 2343 75 0 24 39 1 74 2488 96 39 2445 65 1 74 66 1 58 2636 96 66 2678 57 1 58 4c 0 67 2793 77 4c 2812 50 0 67 19 0 02 2959 89 19 2960 53 0 02 32 0 35 3135 90 32 3125 00 0 35 65 0 41 3322 37 65 3308 82 0 41 4A 0 12 3519 93 4A 3515 63 0 12 15 0 56 3729 23 15 3750 00 0 56 s 1 1 aa aa 1 3
22. B Program the adequate frequency output to PSG output Then use PAM1 or PAM2 control the envelope of code In this way remote control function can be implemented easily The Remote Frequency 56 73kHz or 37 92kHz The software should select OSCX 455kHz SEL 1 1 and SELO 0 so that the PSG Clock 455kHz Then select channel 1 alarm mode C1M 1 and OCT1 0 C2 0 C23 are set to OOH VOL1 VOL2 1 1 Then select C1 6 C1 0 so that N 6 and the PSG output frequency 455kHz 1 2 X 6 37 92kHz Or select C1 6 C1 0 78 so that N 4 and the PSG output frequency 455kHz 1 2 X 4 56 87kHz 32 SH67P54 13 Interrupt Four interrupt sources are available in SH67P54 External interrupt INTO TimerO interrupt Base timer interrupt Port s falling rising edge detection interrupt INT 1 13 1 Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on 00 and 01 of the system register They can be accessed or tested by the program Those flags are cleared to 0 at initialization by the chip reset The Configuration of System Register 0 Address Function 00 Interrupt enable flags 01 Interrupt request flags When IEx is set to 1 and the interrupt request is generated IRQx is 1 the interrupt will be activated and the vector address will be generated from the priority PLA corresponding to the interrupt sources When an interrupt occurs t
23. D COM2 GND vi 2 COM3 GND 2 4 1 4 DUTY 1 3 BIAS SELECT UNSELECT COM din SELECT UNSELECT SEG TT GND 24 SH67P54 V1 2 V3 GND V1 V2 V3 GND SH67P54 Example 1 4 Duty 1 3 Bias COM4 v3 COM1 v2 COM3 vi v3 COM2 v2 vi COM1 0 v3 v2 COM3 V1 v3 v2 COM4 SEGn 1 SEGn v2 SEGn vi v2 SEGn 1 V1 v3 vi COM4 SEGn 0 Vi V2 Lor 2330741 10 6 Shared to LED Application User can use SEG amp COM in the application of LED matrix by Code Option and configuration of LED RAM is the same as LCD RAM Application Note The SEG amp COM can not driver the LED matrix directly for the cause of weak driving ability So in the LED Matrix application the driving circuit will be used such as following Example 1 8 Duty LED Matrix Application Circuit VDD VDD VDD VDD COM1 COM2 COM3 COM8 1 2 5 2 LED Matrix 8X30 dots GND WV SEG2 K K SEG30 SEG29 vvv GND SEG30 GND GND 25 SH67P54 10 7 LED Waveform 1 8 DUTY 1 4 DUTY UNSELECT UNSELECT RED u r N Vpp COM x SELECT SELECT SELECT SELECT SELECT SELECT SELECT az
24. H2EN 1 OSC 32 768kHz SELO SEL1 0 So PSG clock 32 768kHz Switch clock 32 768kHz No vol control the VOL level is set to 4 by hardware so software should set VOLO VOL1 1 TIME SLOT m EE EE HII ER E E E leve voL 4 Note For 32 768kHz operations the volume control cannot be used since the PWM multiplexing frequency is not high enough to Switch sound If a user wants to turn off the PSG completely the software must disable both channels The user should not turn off the PSG by zero waves from output Both the CH1EN and CH2EN should be set to for the low power operation mode Example 4 If software designer wants to create C2 Channel 1 mixed with F5 Channel 2 sound For the C2 F5 sound frequency please refer to Music Table 1 and Music Table 2 VOL level 3 Then the user can select the suggestion as follows 1 The user first selects CH1EN CH2EN 1 C1M C2M 0 2 The user can select OSCX 1 8MHz and SELO SEL 1 1 so the P
25. HIP OSCO 41 10P 15P OSC RC Oscillator Type CHIP 10 SH67P54 4 3 OSCX Oscillation OSCX has two clock oscillators The software options select the Ceramic Crystal or RC as the CPU s sub clock If the OSCX is not used it must be selected as a ceramic resonator and the OSCXI must be connected to GND OSCX Ceramic Crystal Oscillator Type 47P 100 P OSCXI 455kHz Ceramic OSCXO e e CHIP 47 100 OSCX RC Oscillator Type Roscx QSCXI 102 F CHIP OSCXO e 4 4 Control of Oscillator The oscillator control register configuration is shown as follows Address Bit3 Bit2 Bit1 Bit0 14 OXS OXM OXON OXON OSCX oscillation on off 0 Turn off OSCX oscillation 1 Turn on OSCX oscillation OXM switching system oscillator 0 select OSC as system oscillator 1 select OSCX as system oscillator OXS OSCX oscillator type selection 0 OSCX set as Ceramic Resonator Crystal Oscillator 1 OSCX set as RC oscillator 4 5 Programming Notes It takes at least 5 ms for the OSCX oscillation circuit to turn on until the oscillation stabilizes When switching the CPU system clock from OSC to OSCX the user must wait a minimum of 5ms since the OSCX oscillation is running However the start time varies with respect to oscillator characteristics and the condition of use Thus the wait time depends on the application
26. SG CLK 112 5kHz 3 Then the user can select OCT1 1 and the value of channel 1 LSFR C1 6 C1 0 23 so the N 108 Please see the Music Table 1 So the channel 1 sound frequency 112 5kHz 8 2 X 108 64 10Hz the C2 sound frequency 4 Then the user can select OCT2 0 and the value of channel 2 LSFR C2 8 C2 14 4F so the N 81 Please refer to the Music Table 1 So the channel 2 sound frequency 112 5kHz 1 2 X 81 694 4Hz the F5 sound frequency 5 Lastly the user should select the VOL1 1 and VOLO 0 so the VOL level 3 31 SH67P54 Note The designer provides two crossing tables as an appendix since the designer prefers PSG clock 32 768kHz or PSG clock 112 5kHz PSG as a Noise Generator Fine noise is created by CH2 If the user wants to create the single noise then make the CH1 music tone output Otherwise the user can mix the wide band noise and the CH1 music tone into one output through the MIXER Lastly the user can select 4 volume levels controlled by VOLO VOL 1 PSG as an Alarm Generator When PSG is in the alarm mode the CH1 provides the alarm carrier frequency and the CH2 provides the alarm envelope signal Lastly the user can select 4 volume levels controlled by VOLO VOL 1 The channel 2 low nibble C2 0 C2 3 will be the alarm control register Channel 1 output would modulate with an ALARM envelope control for 32 768kHz or 262kHz The carrier frequency can be programmed by PSG channel 1 In
27. Watchdog timer out period 4096ms Watchdog timer out period 1024ms Watchdog timer out period 256ms Watchdog timer out period 128ms Watchdog timer out period 64ms Watchdog timer out period 16ms Watchdog timer out period 4ms Watchdog timer out period 1ms No watchdog timer overflow reset S x gt X Xx gt x gt x gt x x 1 1 1 1 1 10 Watchdog timer overflow WDT reset happens Note Watchdog timer out period valid for VDD 5V WDF will be cleared after Power on Reset Pin Reset or Low Power Reset 17 SH67P54 10 LCD Driver The LCD driver contains a controller a voltage generator 8 common signal pins and 30 segment driver pins when LCD dots are maximum There are four different programmable driving modes 1 8 duty amp 1 4 bias 1 6 duty amp 1 3 bias 1 5 duty amp 1 3 bias and 1 4 bias amp 1 3bias The driving modes are controlled by the system register 15 and the power on initialization status is 1 8 duty 1 4 bias When 1 6 duty and 1 3 bias mode are used 8 are used as SEG32 31 When 1 5 duty and 1 3 bias mode are used COM6 8 are used as SEG33 31 When 1 4 duty and 1 3 bias mode are used COM5 8 are used as SEG34 31 The LCD SEGS 30 can also be used as output port controlled by the bit 2 of the system register 0D When SEGS 30
28. X PC if CY z 1 BAO 10100 xxxx Xxx PC if AC 0 1 BA1 10101 Xxx PC ifAC 1 BA2 10110 XXXX PC BA3 10111 XXX XXXX 1 2 1 P 1 X ifAC 3 CALL 11000 xxxx XXX ST P CY PC 1 X Not include p I X X X r RTNW 11010 000h hhh 1111 lt ST TBR lt hhhh lt 1111 RTNI 11010 1000 000 0000 CY lt ST HALT 11011 0000 000 0000 STOP 11011 1000 000 0000 JMP 1110p xxxx Xxx XXXX lt X Include p TJMP 11110 1111 111 1111 P lt PC11 C8 TBR AC NOP Where Program counter 11111 1111 111 1111 No Operation Immediate data ROM page 0 Accumulator Logical exclusive OR Stack Complement of accumulator Logical OR Table Branch Register Carry flag Logical AND Data memory RAM bank 000 38 SH67P54 Electrical Characteristics Absolute Maximum Ratings Comments DC Supply Voltage 0 3V to 7 0V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device Input Voltage 0 3V to Vpp 0 3V These are stress ratings only Functional operation of this device atthese or any other conditions above those indicated Operating Ambient Temperature
29. alue of 07 to increase the bias current for better LCD performance But SH67P54 it will cost more power when smaller divider resistors are used User can also use external parallel connection resistors for complex bias current 19 SH67P54 10 4 Configuration of LCD RAM LCD 1 4 Duty 1 3 Bias COM1 4 SEG1 34 Address Address 300 311 301 312 302 313 303 314 304 315 305 316 306 317 307 318 308 319 309 31A 30A 31B 30B 31C 30C 31D 30D 31E 30E 31F 30F 320 310 321 20 LCD 1 5 Duty 1 3 Bias COM1 5 SEG1 33 Address Address SH67P54 300 328 301 329 302 32A 303 32B 304 32C 305 32D 306 32E 307 32F 308 330 309 331 30A 332 30B 333 30C 334 30D 335 30E 336 30F 337 310 338 311 339 312 33A 313 33B 314 33C 315 33D 316 33E 317 33F 318 340 319 341 31A 342 31B 343 31C 344 31D 345 31E 346 31F 347 320 21 348 SH67P54 LCD 1 6 Duty 1 3 Bias COM1 6 SEG1 32 Address Address 300 328 301 329
30. e SINO WEALTH SH67P54 OTP 4 Bit Micro controller with LCD Driver Features m SH6610D Based Single Chip 4 Bit Micro controller B OTPROM 4K X 16 bits RAM 384 X 4bits System Register 48 X 4 bits Data RAM 336 X 4 bits B Operation Voltage System Oscillator 300kHz 4MHz VDD 2 4V 6 0V System Oscillator 30kHz 8MHz Vpp 4 5V 6 0V 16 CMOS Bi directional I O Pins PORT C D can switch to segment m Built in Pull high and Pull low Resistor for I O W 8 Level Subroutine Nesting include interrupts W One 8 Bit Auto Re load Timer Counter m Warm Up Timer for Power on Reset m Powerful Interrupt Sources External Rising Falling Interrupt TimerO Interrupt Base Timer Interrupt Port s Rising Falling Edge Interrupt PORTB C 8 bit Base Timer m LCD Driver 8 X 30 1 8 duty 1 4 bias 6 X 32 1 6 duty 1 3 bias 5 X 33 1 5 duty 1 3 bias 4 X 34 dots 1 4 duty 1 3 bias W CD used as Scan Output General Description W LCD shared as LED Matrix m Built in Dual Tone PSG with One Noise Generator W Built in Watchdog Timer Two LVR Level Code Option 1 4 0V Level2 2 5V W 2 Clock Sources OSC Code Option selects the type of OSC Crystal Oscillator 32 768kHz RC Oscillator 262kHz OSCX system register selects the type of OSCX Ceramic Resonator Crystal Oscillator 400kHz 8MHz RC oscillator 2MHz 8MHz E Instruction cycle time 4 fosc User program can read ROM data T
31. ed between the accumulator and system register or data memory can be performed 2 OTPROM SH67P54 1 4 Table Branch Register TBR Table Data can be stored in program memory and can be referenced by using Table Branch TJMP and Return Constant RTNW instructions The TBR and AC are placed by an offset address in program ROM TJMP instruction branch into address PC11 PC8 X 2 TBR AC The address is determined by RTNW to return look up value into TBR AC ROM code bit7 bit4 is placed into TBR and bit3 bitO into AC 1 5 Data Pointer The Data Pointer can indirectly address data memory Pointer address is located in register DPH 3 bits DPM 3 bits and DPL 4 bits The addressing range can have 3FFH locations Pseudo index address INX is used to read or write Data memory then RAM address bit9 comes from DPH DPM and DPL 1 6 Stack The stack is a group of registers used to save the contents of CY amp PC 11 0 sequentially with each subroutine call or interrupt The MSB is saved for CY and it is organized into 13 bits X 8 levels The stack is operated on a first in last out basis and returned sequentially to the PC with the return instructions RTNI RTNW Note The stack nesting includes both subroutine calls and interrupts requests The maximum allowed for subroutine calls and interrupts are 8 levels If the number of calls and interrupt requests exceeds 8 then the bottom of stack will be
32. er accepts 4096Hz or 32 75kHz clock and base timer generates an accurate timing interrupt This clock input source is selected by BTM register Arms mu me s o3 o x gt x Else states X X Disable the base timer clear base timer counters and keep them as 00 Prescaler Ratio Clock Source 1 4096Hz or 32 75kHz 14 4096Hz or 32 75kHz 18 40962 32 75kHz 40962 32 75kHz 8 Bit base timer counter 11 74 18 16 N e 32 768kHz 4096Hz or 18 er 4Bit Scaler a 262kHz 32 75kHz 16 SH67P54 9 Watchdog Timer WDT Watchdog timer is a down count counter and its clock source is an independent built in RC oscillator so that the WDT will always run even in the STOP mode if it is enabled The watchdog timer automatically generates a device reset when it overflows Code Option can enable or disable this function The watchdog timer control register WDT bit2 0 selects different overflow frequency WDT bit3 is watchdog timer overflow flag If the Watchdog timer is enabled the CPU will be reset when watchdog timer overflows Repeat reads or writes WDT register 1E the watchdog timer should re count before the overflow happens System Register 1E WDT Address Remarks Bit2 0 Watchdog timer control VIE Bit3 Watchdog timer overflow flag Read only
33. erence only Typical RC Oscillator Resistor vs Frequency 1 fosc vs Rosc 500 400 300 fosc 2 200 100 Vpp 5 0V 0 1000 2000 3000 4000 5000 6000 7000 8000 Rosc Resistor vs fosc Vpp 5 0V 500 400 300 fosc kHz 200 100 3 0V 2000 4000 6000 8000 Rosc c Resistor vs fosc Vpp 3 0V 42 SH67P54 SH67P54 2 foscx vs Roscx Vpp 5V 8000 6000 R 4000 5 8 2000 0 0 50 100 150 200 Roscx Resistor vs foscx VDD 5 0V 3 0V 8000 6000 4000 5 2 2000 0 0 50 100 150 200 Roscx Resistor vs foscx VDD 3 0V 43 SH67P54 In System Programming Notice for OTP The In System Programming technology is valid for OTP chip The Programming Interface of the OTP chip must be set on the user s application PCB and users can assemble all components including the OTP chip in the application PCB before programming the OTP chip Of course it s accessible bonding OTP chip only first and then programming code and finally assembling other components Since the programming timing of Programming Interface is very sensitive therefore four jumpers are needed VDD VPP SDA SCK to separate the programming pins from the application circuit as shown in the following diagram Application PCB OTP Chip VPP VDD SCK
34. erved BitO 1 PSG1 PSG2 mode control Bit2 3 PSG1 PSG2 clock source selection PSG channel 1 low nibble PSG channel 1high nibble Bit3 channel 1 octave shift control PSG channel 2 nibble 1 or alarm output PSG channel 2 nibble 2 PSG channel 2 nibble 3 PSG channel 2 nibble 4 Bit3 channel 2 octave shift control Bit1 Channel 1 2 enable Bit2 Bit3 volume control System Register 00 12 Please refer to SH6610D User s manual 3 3 System Register Initial State Power On Reset Pin Reset Voltage Reset WDT Reset 0000 0000 mox mor Rar ae ce nox oo ico mco w c SH67P54 System Register Initial State continue Power On Reset Pin Reset WDT Reset Address ILow Voltage Reset s u s m X 0A 0B 0C 00 0 INX 3 INX 2 INX 1 INX 0 uuuu 12 14 16 18 1A uuuu 11 s10 13 u 0u oo s 0000 15 19 0000 s mm sie mm sic sip m ow esr wes F Ea E AOS 537 973 s374 5375 5376 5377 Legend x unknown unchanged unimplemented read as 0 3 4 Others Initial State lt ala m m Others After any Reset Program Counter PC 000 CY Undefined Accumulator AC Undefined Data Memory Undefined SH67P54 4 System Clock and Oscil
35. he PC and CY flag will be saved into the stack memory and jump to the interrupt service vector address After the interrupt occurs all interrupt enable flags IEx are reset to 0 automatically so when IRQx is 1 and IEx is set to 1 again the interrupt will be activated and the vector address will be generated from the priority PLA corresponding to the interrupt sources 1 2 3 4 5 ny AY Instruction Instruction Instruction Execution Execution Execution 1 12 N Interrupt Nesting During the SH6610D CPU interrupt service the user can enable any interrupt enable flag before returning from the interrupt The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences If the interrupt request is ready and the instruction of execution N is IE enable then the interrupt will start immediately after the next two instruction executions However if instruction I1 or instruction I2 disables the interrupt request or enable flag then the interrupt service will be terminated 13 2 External Interrupt External interrupt is shared with the PORTA O falling rising edge active When the bit 3 of the register 0 IEX is set to 1 the external interrupt is enabled The External interrupt can be used to wake the CPU from the HALT mode 13 3 TimerO Interrupt Base Timer Interrupt The input clock of TimerO and Base Timer are based on system clocks or OSC clock INTO input as TimerO and Base Timer source The timer overflow fro
36. lator 4 1 Circuit Configuration SH67P54 has two on chip oscillation circuits OSC and OSCX OSC is a low frequency crystal Typ 32 768kHz or RC Typ 262kHz determined by the Code Option This is designed for low frequency operation OSCX also has two types ceramic crystal Typ 455kHz or RC 2MHz to 8MHz to be determined by the software option It is designed for high frequency operation It is possible to select the high speed CPU processing by a high frequency clock and select low power operation by low operation clock At the start of Power on reset Pin reset and low power reset initialization the OSC starts oscillation and OSCX is turned off But at the start of WDT reset initialization the OSC starts oscillation and OSCX remains the original state Immediately after reset initialization the OSC clock is automatically selected as the system clock input source Oscillator Block Diagram Base Timer OSCI Low Frequency Osco Clock Oscillator System clock Source Selector gt A OSCXI amp Switching control mE System clock CPU Clock High Frequency OSCXO Clock Oscillator 4 2 OSC Oscillation The OSC generates the basic clock pulses that provide the CPU and peripherals Base Timer LCD with an operating clock OSC Crystal Oscillator Type 5 OSCI 32 768kHz Crystal C
37. ll output pins unload STOP mode LCD off WDT off Input High Voltage 0 7 X VDD VDD 0 3 PORTA PORTD Input High Voltage 0 8 X VDD VDD 0 3 RESET Schmitt trigger input Input Low Voltage 0 3 0 3 X VDD PORTA PORTD Input Low Voltage 0 3 0 2 X VDD RESET Schmitt trigger input Pull high Resistor PORTA D Pull low Resistor PORTA D WDT Current 20 LCD Lighting 15 40 SH67P54 AC Characteristics VDD 3 0 GND OV TA 25 fosc 32 768kHz crystal unless otherwise specified Parameter Conditions Oscillation Start Time Instruction Time AC Characteristics GND OV TA Parameter Symbol 25 fosc 262kHz RC foscx stop unless otherwise specified Conditions Frequency Variation Parameter Symbol Include supply voltage and chip to chip variation Conditions Frequency Variation Low Voltage Reset Electrical Characteristics 2 4 6V Parameter Include supply voltage and chip to chip variation Condition LVR Voltage 1 LVR Enable LVR Voltage 2 LVR Enable 41 Timing Waveform System Clock Timing Waveform System Oscillator System Clock A RC Oscillator Characteristics Graphs for ref
38. llator 1 8MHz PORTB PORTC PORTD I O PORTA 1 PSG output PORTA 2 PSG output 4X26 1 4 duty 1 3 bias SPEAKER OSCXO PORTA 1 8099 vSdZ9HS PORTA 2 AP4 Large LCD panel If internal different bias resistor 10 30kO 90 270 don t meet request user can use External LCD bias 1 4 Bias or 1 3 Bias 1 4 Bias 1 3 Bias Normal LCD pannel Large LCD pannel Large LCD pannel V1 V1 V1 Ext R Ext R V2 V2 V2 SH67P54 SH67P54 SH67P54 Ext R Ext R V3 V3 V3 Ext R Ext R V4 V4 VA Use internal bias resistors 46 Music Table 1 SH67P54 Following is the music scale reference table for channel 1 or channel 2 under OSCX 1 8MHz Up to 6 octaves are possible Music scale data for 1 8MHz OSCX and SELO SEL1 1 LSFR C1 6 C1 0 C2 14 C2 8 Error Ideal freq LSFR C1 6 C1 0 C2 14 C2 8 Real freq Error 42 0 08 493 88 42 493 42 0 09 23 0 01 523 25 23 520 83 0 46 64 0 47 554 35 64 556 93 0 47 0B 0 24 587 33 0B 585 94 0 24 4E 0 44 622 24 4E 625 00 0 44 54 0 38 659 26 54 661 77 0 38 4F 0 58 698 46 4F 694 44 0 58 74 0 02 739 97 74 740 13 0 02 43 0 35 783 99 43 781 25 0 35 38 0 40 830 59 38 827 21 0 41 9 0 13 8
39. m FF to 00 will generate an internal interrupt request IRQTO or IRQBT 1 If the interrupt enable flag is enabled IETO or IEBT 1 a timer interrupt service routine will start Timer interrupt can also be used to wake the CPU from the HALT mode 13 4 Port Interrupt The PORTB and PORTC are used as port interrupt sources Since PORTB and PORTC bit programmable I Os so only the voltage transition from VDD to GND applying to the digital input port can generate a port interrupt The condition is that the other port must be input high level Interrupt Servicing Sequence Diagram 33 SH67P54 14 HALT and STOP Mode After the execution of HALT instruction the device will enter halt mode In the halt mode CPU will stop operating But peripheral circuit Base Timer and Watchdog Timer will keep operating After the execution of STOP instruction the device will enter stop mode In the stop mode the whole chip including oscillator will stop operating without watchdog timer if it is enabled In HALT mode SH67P54 can be waked up if any interrupt occurs In STOP mode SH67P54 can be waked up if port interrupt occurs or Watchdog timer overflow when WDT is enabled When SH67P54 is waked up by interrupt from HALT or STOP mode it will save current PC into the stack and jump to the corresponding interrupt vector address 15 Warm up Timer The device has oscillator warm up timer to eliminate unstable state of initial
40. nd CH2 OUT into one tone output to PORTA 1 PORTA 2 when PAM1 1 PAM2 1 Then the tone output is controlled by the volume control bit into 4 volume levels and in the end outputted by PSG PORTA 1 amp PORTA are controlled by PAM1 4 PAM2 Remarks PORTA 1 I O PORT PORTA 2 I O PORT PORTA 1 PSG output PORTA 2 I O PORT PORTA 1 I O PORT PORTA 2 PSG output PORTA 1 PSG output PORTA 2 PSG output Vol control Vol Level NO YES YES YES Note The user should not enable two PSG channels together to produce one tone otherwise it will produce some unpredictable errors If it is necessary to use 2 channels together i e to play two channel melody do not allow score always is the same tones then the unpredicted errors will not occur or user will ignore it 29 SH67P54 The Value N of Divider1 is Corresponding to the REG C1 6 C1 0 or REG C2 14 C2 8 as shown in the following Table LSFR LSFR LSFR C1 6 C1 0 1 6 C1 0 01 6 1 0 C1 6 C1 0 C2 14 C2 8 C2 14 C2 8 C2 14 C2 8 C2 14 C2 8 01 16 12 4B 02 2C 24 17 04 59 49 2E 08 33 13 5D 10 67 26 3B 20 4E 4D 77 41 1D 1B 6E 03 3A 36 5C 06 75 6D 39 0C 6A 5A 73 18 54 35 66 30 29 6B 4C 61 53 56 19 42 27 2D 32 05 4F 5B 65 0A 1F 37 4A 14 3E 6F 15 28 7D 5E 2A 51 7A 3D 55 23 74 7B 2B 47 68 76 57 OF 50 6 2 1 21 58 5 3C 43 31 3F 19 07 63 72 46 64 1C 0D 7C 48 38
41. nding Option 35 16 2 Code Option a Oscillate type 0 32 768kHz Crystal oscillator 1 262kHz RC oscillator b OSCX range select 0 400kHz 2MHz 1 2MHz 8MHz c Watchdog timer 0 Enable 1 7 Disable d LVR Reset 0 Disable 1 Enable LVR level 0 Level1 4 0V 1 Level2 2 5V f LCD LED matrix 0 LCD application 1 LED matrix application e 36 SH67P54 SH67P54 17 Instruction Set All instructions are one cycle and one word instructions The characteristic is memory oriented operation Arithmetic and Logical Instruction Accumulator Type Mnemonic Instruction Code Function Flag Change ADC 00000 Obbb xxx xxxx AC Mx Ac CY CY ADCM 00000 1bbb xxx xxxx AC MX Mx Ac CY CY ADD 00001 Obbb xxx xxxx AC lt Mx Ac CY ADDM 00001 1bbb xxx xxxx lt CY SBC 00010 Obbb xxx xxxx AC lt CY SBCM 00010 1bbb xxx xxxx lt SUB 00011 Obbb xxx xxxx AC lt Mx Ac 1 CY SUBM 00011 1bbb xxx xxxx lt 1 00100 Obbb xxxx AC lt Mx Ac EORM 00100 1bbb xxx xxxx lt Mx Ac 00101 Obbb xxxx AC lt Mx ORM 00101 1bbb xxx xxxx lt Mx Ac AND 00110 Obbb xxx xxxx
42. nts to generate an interrupt when a falling edge from VDD to GND emerges on the port the following must be executed 1 Set the port as input port fill port data register and avoid port floating 2 Pull high the port Use external pull high resistor or set PULLEN to 1and set PH PL to 1 3 Set Falling Edge register Set PBCFR to 0 in PORTB PORTC INT application Set EINFR to 0 in EXINT application And further falling edge transition would not be able to make interrupt request until all of the pins return to in PBC INT application When PORTO is shared to segment user can only generate interrupt on PORTB 14 SH67P54 7 Timer 0 SH67P54 has one 8 bit timer The timer consists of an 8 bit up counter and an 8 bit preload register The timers provide the following functions Programmable internal timer function Read the counter values 7 1 Timer 0 Configuration and Operation The timer 0 consists of an 8 bit write only timer load register TLOL TLOH and an 8 bit read only timer counter TCOL TCOH Each has low order digits and high order digits The timer counter can be initialized by writing data into the timer load register TLOL TLOH Write the low order digit first and then the high order digit The timer counter is loaded with the content of the load register automatically when the high order digit is written or counts overflow happens The timer overflow will generate an interrupt if the interrupt enable flag is set
43. oscillation when oscillator starts oscillating in the following conditions Hardware reset Power on reset Low voltage reset Wake up from stop mode Warm up time interval 1 If RC oscillator is selected as system clock the warm up counter prescaler is divided by 27 128 Example 262kHz RC is system clock warm up time interval is 2 X 1 262kHz 0 489ms 2 If Ceramic Resonator Crystal Oscillator is selected as system clock the warm up counter prescaler is divided by 2 4096 Example 8MHz Ceramic is system clock warm up time interval is 2 1 8 2 0 5128 34 SH67P54 16 Options 16 1 Bonding Options Up to 4 different bonding options are possible for the user s needs The chip s program has 4 different program flows that will vary depending on which bonding option is used The readable contents of BD1 and BDO will be different depending on bonding Remarks 1 Bonding option BDO is weakly pulled high BD1 is weakly pulled low Bit2 3 PORTA 1 amp PORTA 2 as PSG output or I O PORT BD1 bond to BDO bond to GND BDO bond to GND and BD1 bond to ND GND BD O BD 1 VDD BDO BD 1 BD0 1 BD1 0 1 BD1 1 GND GND BDO BD 1 VRD 0 1 BDO 0 BD1 0 BDO 0 BD1 1 SH67P54 Bo
44. t cancels the internal reset signal when VDD gt VLVR Here VDD power supply voltage VLvR LVR detect voltage there are two level selected by Code Option Level1 2 4 2 6V typical 2 5V Level2 3 8 4 2V typical 4 0V 12 SH67P54 6 Ports The MCU provides 16 bi directional I O pins Each I O pin contains pull high low MOS controllable through programming When every I O is used as input the PORT control register PACR PBCR PCCR PDCR controls the ON OFF of the output buffer Every I O pin has an internal pull high low resistor which is controlled by PULLEN PH PL of 13 and data of the port Port I O mapping address is shown as follows Address Remarks 08 PORTA 09 PORTB 0A PORTC 0B PORTD 16 PORTA input output control 17 PORTB input output control 18 PORTO input output control 19 PORTD input output control Equivalent Circuit for a Single I O Pin PULLEN RIPE 1 d Weak Pull high 1 0 Control Register Dx 1 0 Pad DATA Regiser V Weak ps 4 Pull Low V GND DATA READ DATA IN READ System Register 13 Remarks BitO External interrupt PORTA O rising falling edge set Bit1 PORTB PORTC interrupt rising failing edge set Bit2 Port pull high low set Bit3 Port pull high low enable control PULLEN PH PL PBCFR EINFR RW EINFR 1 E
45. urces as PSG clock that provides the two channel clock sources 27 SH67P54 Channel 1 Li REGISTER C1 6 C1 0 PSG CLOCK 8 gt SELECTOR DIVIDER 1 gt 2 CH1 OUT Scaling ratio 1 Channel 1 is constructed by a 7 bit pseudo random counter Channel 1 is enabled disabled by CH1EN It creates either a sound frequency or an alarm carrier frequency or a remote carrier frequency Channel 2 C2M NOISE 1 2 2 GENERATOR SELECTOR OUT ES SELECTOR REGISTER C2 14 C2 0 1Hz 4Hz 8Hz 32Hz Scaling ratio 1 2 2 14 C2 8 DIVIDER C23 C20 C1M ENEVLOP ENEVLOP A 15 bit pseudo random counter construct channel 2 Channel 2 is enabled disabled by CH2EN It can be a 15 bit wide band noise generator or a 7 bit sound generator It can also create an alarm envelope signal Remarks 1 is a Sound generator CH2 is a Sound generator CH1 is a Sound generator CH2 is a Noise generator CH1 is a Sound generator 2 is an Alarm mode register 28 SH67P54 Mixer TIME SLOT VOLO 1 0 PSG SELECTOR1 PORTA 1 CH1 OUT TIMESLOT gt CONTROL CH2 OUT PSG gt SELECTOR2 PORTA 2 PA 2 I O f PAM2 The MIXER mixes CH1 OUT a
46. wo low power operation modes HALT and STOP E Low power consumption OTP type amp Code protection E Chip and LQFP64 SH67P54 is a single chip micro controller integrated with SRAM 4K OTPROM timer watchdog timer and dual tone PSG LCD driver LED Matrix driver and port V2 2 SH67P54 LQFP64 PIN Configuration RESET TEST Osco OSCXO OSCX 0 17 OSCI 20 GND vi 2 v3 V4 NC 28 NC ON 8 e 2 V1HOd LWOO E E 081908 zWO2 g 8 L 81HOd enoo 5 281908 E z 81HOd v O3S SWOO 8 LO E 1938 0 0180d E 9IS 9NOI n 5 2938 01904 zeo3s Woo s 93s zo1uoa 15935805 E r as oruod 093 E o e 6293 E e 8293 E E ze3srzarsoa 12935 E 5 93s e amp a1soa 9293 s on 9293 E SEG24 SEG23 SEG22 SEG21 SEG19 SEG14 SEG13 SEG12 SEG11 SH67P54 Pad Configuration LWOO WOO EWOO VINOD vEDAS SWOO 93S 9WOO c 93S 4WOO 1e93S 8NO9 02945 66945 86945 12945 90935 9695 V1 OSCI 27 V2 26 v3 25 V4 24 RESET 23 TEST 22 OSCO
47. xternal Rising Edge interrupt 0 External Falling Edge interrupt PBCFR 1 PORTB PORTC Rising Edge interrupt 0 PORTB PORTC Falling Edge interrupt PH PL 1 Port Pull high resistor ON 0 Port Pull low resistor ON PULLEN 1 Port Pull high low enable 0 Port Pull high low disable To turn on the pull high resistor user must set PULLEN to 1 set PH PL to 1 and write 1 to the port data register To turn on the pull low resistor user must set PULLEN to 1 set PH PL to 0 and write O to the port data register 13 SH67P54 6 1 PORTB amp PORTC Interrupt The PORTB and PORTC are used as port interrupt sources Following is the port interrupt function block diagram IEP PORTB n Rising Falling PORTC n Edge Detector Port Interrupt Note 0 1 2 3 6 2 External INTO PORTA 0 is shared by external interrupts External INTO PORTA 0 AND PORTB PORTC interrupt PROGRAMMING NOTES E f user wants to generate an interrupt when a rising edge from GND to VDD emerges in the port the following must be executed 1 Set the port as input port fill port data register and avoid port floating 2 Pull low the port Use external pull low resistor or set PULLEN to 1and set PH PL to 0 3 Set Rising Edge register Set PBCFR to 1 in PBC INT application Set EINFR to 1 in EXINT application And further rising edge transition would not be able to make interrupt request until all of the pins return to GND in PBC INT application E f user wa
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