HDL Synthesis Design with LeonardoSpectrum: CPLD Flow
Contents
1. m Constraints Clock Frequency Mhz r Optimize Effort Fastest High Runtime _ _ _ Effort r Output Output File m Place And Route F Run Integrated Place and Route Run Flaw AA AP active Review 2004 Lattice Semiconductor Help 101 x ix xd Info Attempting to checkout a license to run as LeonardoSpectrum fos Session history will be logged to file C ispTOOLSS_0 examples Tuto Info Working Directory is now C ispTOOLSS_0 examples Tutorial tut Info Loading Exemplar Blocks file C ISPTOOLSS_0 SPECTRUM data xmp Messages will be logged to file C ispTOOLSS_0 examples Tutorial tu LeonardoSpectrum for Lattice 2004b 39_OEM Lattice Release OEM Lat Working Directory TutorialitutorS Ln 17 Col 1 10 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Task 4 Use Quick Setup to Synthesize the Design Quick Setup is a push button flow that you can use to achieve good first pass synthesis results You specify the target technology open your input design files optionally set the target clock frequency and verify the name of the output netlist When you click Run Flow the entire synthesis flow is executed from start to finish including synthesis applying global constraints optimization and writing the netlist The output is an EDIF netlist that can be rea2. static timing analysis Static timing analysis is the process of verifying circuit timing by totaling the propagation delays along paths between clocked or combinational elements in a circuit The analysis can determine and report timing data such as the critical path setup and hold time requirements and the maximum frequency synthesis Synthesis is the process of translating a high level design RTL description consisting of state machines truth tables and or Boolean equations into a process specific gate level logic implementation VHDL VHDL or VHSIC Very High Speed Integrated Circuits Hardware Description Language is a language for describing the structure and function of integrated circuits Verilog Verilog is a language for describing the structure and function of integrated circuits 2004 Lattice Semiconductor 23 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Recommended Reference Materials You can find additional information on the subjects covered by this tutorial from the following recommended sources e LeonardoSpectrum for Lattice User s Manual e LeonardoSpectrum for Lattice HDL Synthesis Manual e Lattice ispLEVER online help e How To guides e Process Flows gt ispXPGA Flows e Data sheets technical notes and other information on ispXPGAs on the Lattice Web site at http www latticesemi com search literature cfm Click on FPGA gt ispXPGA 2004 Lattice Semiconductor
3. 0 0 00 0 00 up LSI5000 r sp io_select 0 70 IBUF 1 00 1 00 up ispLSISOO0VE ix115 0 INV 1 00 2 00 up ispLSI5000VE_old ix113 0 NAN2 1 00 3 00 up i 1x43 0 NAN2 1 00 4 00 up sane ix10770 NAN2 1 00 5 00 up Bema ix47 0 NAN2 1 00 6 00 up ispmach4000C io_z 0 OBUF 1 00 7 00 up ispmach4000V z 0 00 7 00 up ispmach50008 a data arrival time 7 00 rf Device LC4032V 25744C x Open files Package z Working Directory m Constraints Clock Frequency Mhz r Optimize Effort Fastest 4 1 High Runtime _ _ Effort r Output Output File multiple_0 edf m Place And Route F Run Integrated Place and Route we 4 4 AP active Review data required time not specified data required time not specified data arrival time unconstrained path Design summary in file multiple_0 sun AutoWrite args are multiple_0 edf Writing file multiple_0 edf CPU time taken for this run was 0 41 sec 0 Info Finished Synthesis run Run Successfully Ended On Thu Mar 10 14 58 30 Pacific Daylight T working Directory Tutorialitutor3 Ln 163 Col 1 8 Choose File gt Exit to exit LeonardoSpectrum Click Yes in the confirmation box 2004 Lattice Semiconductor 14 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Task 5 Import the EDIF File into Your Project You can import EDIF
4. Number of bidir ports O Number of instances 24 Number of nets 31 No design errors found in circuit multiplexerdtol WriteBLIF ended normally Done completed successfully KE ofa Ready fm 2 Note After you import an EDIF file into the ispLEVER project it is always linked to the Project Navigator Therefore if you make changes and recompile your HDL file to create a new EDIF file your project is automatically updated as well 2004 Lattice Semiconductor 16 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Task 6 Fit the Design and View the Report The ispLEVER software has a single user interface with all options preset to deliver the highest possible push button performance for most devices When you double click a process all the processes prior to that process run automatically Therefore all you have to do is double click the final process However here you will run one process at a time and view the results as you go At the end of a successful fitter run the ispLEVER software generates a JEDEC file as well as a fitter report so that you can see how the ispLEVER software has utilized and routed the part To run the Fitter and view the report 1 With the target device selected in the Sources window double click Fit Design in the Processes for Current Source window to run the Fitter The ispLEVER software successfully fits the design in the specified device and generate
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6. a COMP_GT 6T_O gt COMP sl EQO This tutorial first directs you to create an EDIF project in the Project Navigator then select the target device in which the design will be implemented The tutorial assumes that functional simulation has already been performed Next you start LeonardoSpectrum and open a new LeonardoSpectrum project After you import the VHDL source files and set the implementation options the tool synthesizes the design into the target device and generates an EDIF netlist You then import the EDIF netlist into the Project Navigator project and perform mapping placing and routing Finally you perform a static timing analysis and examine the results About the Tutorial Data Flow The following figure illustrates the design flow that the tutorial takes You may find it helpful to refer to this diagram as you move through the tutorial tasks 2004 Lattice Semiconductor 3 isoLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Synthesize with multiple edf Leonardo Spectrum Fit design with Fitter Analyze timing with Performance Analyst 2004 Lattice Semiconductor 4 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Task 1 Create a New Project To begin a new project you must create a project directory Then you must give the project file a name syn and declare the project type EDIP The ispLEVER software saves an initial design file with the syn file
7. extension in the directory that you specify All project files are copied to or created in this directory The project type specifies that all design sources will be of this type To create a new project 1 Start the ispLEVER system if it is not already running 2 In the Project Navigator choose File gt New Project to open the Create New Project dialog box 3 In the dialog box do the following e Inthe Project Name box type mux e In the Location box change to the following directory lt install_path gt examples tutorial tutor3 Note If you want to preserve the original tutorial design files save the tutor3 directory to another location on your computer before proceeding e In the Design Entry Type box choose EDIF e Inthe Synthesis Tools box choose LeonardoSpectrum e Click Next to open the Project Wizard Select Device dialog box 2004 Lattice Semiconductor 5 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Project Wizard xi C ISPTOOLS5_O EXAMPLESSTUTORIALSTUTORS Schematic ABEL Synplify O Schematic HDL LeonardoSpectrum Schematic erilog HDL Verilog HDL 2004 Lattice Semiconductor 6 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Task 2 Target a Device In the Project Navigator Sources in Project window the device icon appears next to the target device for the project The Project Navigator enables you tar
8. gt Fit Design Pre Fit Equations Signal Cross Reference Fitter Report E HTML Fitter Report KR Post Fit Pinouts A Post Fit Re Compile f JEDEC File f ISC 1532 File K Timing Analysis 2 Timing Report gt Generate Timing Simulation Files 2 Report File gt Generate Board level Stamp Model E Stamp Model File fe Stamp Model Data File E ispLEVER Auto Make Log File Starting C ispTOOLSS_O ispepldNbin checkini exe err automake err C ispTOOLSS_O ispepld cor Done completed successfully 2004 Lattice Semiconductor 8 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Task 3 Start LeonardoSpectrum from ispLEVER For HDL designs the ispLEVER software provides two synthesis tools that are integrated into the Project Navigator environment LeonardoSpectrum and Synplify You can synthesize your Verilog or VHDL design as a standalone process by choosing the synthesis tool from the Lattice Semiconductor program group in your Start menu or you can synthesize automatically and seamlessly within the Project Navigator LeonardoSpectrum for Lattice is a logic synthesis tool that starts with a high level design written in the Verilog or VHDL hardware description language HDL Then it converts the HDL description into small high performance design netlists that are optimized for Lattice devices When you start LeonardoSpectrum for the first time the main window is maximized a
9. 2 0 0 netlists from third party synthesis tools such as Synplify or LeonardoSpectrum into ispLEVER To import an EDIF netlist into your project 9 In the ispLEVER Project Navigator choose Source gt Import to open the Import File dialog box 10 Select multiple_0 edf and then click Open 2 x Look in autos O ex FE File name mutiple_0 edf Files of type Sources txt ed abv 7 Cancel W The software adds the selected EDIF file muitiple_0 edf to the project sources 2004 Lattice Semiconductor 15 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow ispLEYER Project Navigator C ISPTOOLS5_0 EXAMPLES TUTORIAL TUTORS mux syn File view Source Process Options Tools Window Help D0 S E noma TJERT EEE eE BPECCOLELCIEET I Sources in Project Processes for current source B MUX Documents K Optimization Constraint K Constraint Editor EJ Lc4256v 10T1001 Fit Design B multiplexer4to1 multiple _0 edf E Pre Fit Equations Signal Cross Reference Fitter Report E HTML Fitter Report Post Fit Pinouts A Post Fit Re Compile fe JEDEC File f 15C 1532 File K Timing Analysis Timing Report D gt Generate Timing Simulation Files a Report File gt Generate Board level Stamp Model a Stamp Model File fe Stamp Model Data File x Inspect circuit multiplexer4tol 4 Number of input ports Number of output ports 1
10. HDL Synthesis Design with LeonardoSpectrum CPLD Flow Table of Contents HDL Synthesis Design with LeonardoSpectrum CPLD Flow cccccceeeeeees 2 Task 1 Create a New Project snccccccecscseseetecocinssetessensensccttocaenedsneasinucdeecoaeatinauentines 5 Task 2 Target a Device ri iiiisicsdicaimasdinnanadinninadincinindaneseidanisardanesanndancsaarsanesanadnazs 7 Task 3 Start LeonardoSpectrum from isoOLEVER ceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 9 Task 4 Use Quick Setup to Synthesize the DeSIQN ccccceeeeeeeeeeeeeeeeeeeeeees 11 Task 5 Import the EDIF File into Your Project cccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeees 15 Task 6 Fit the Design and View the Repott cccccceeessseeeceeeeeeeeeeeeesseeees 17 Task 7 Perform Static Timing Analysis cccececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenaaees 19 SUMMAY sparades kra nE aAA EEA EREA du ncdamed arena ui AEA 22 COS SAY E EE E pda ed A peed acta a 23 Recommended Reference Materials ccccccccceceeeeceeeeeeeeeeeeeeeeeneneeeeeeeeeeeeeee 24 2004 Lattice Semiconductor Tutor3 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow HDL Synthesis Design with LeonardoSpectrum CPLD Flow This tutorial shows you how to use LeonardoSpectrum from within ispLEVER to synthesize a Verilog design and generate an EDIF file for a Lattice CPLD device Note If you want to learn how to use LeonardoSpectrum in standalo
11. SOURCE LI DESTINATI DELAY ns DELAY MH Delay Cons r Analysis Max CC ICO C tSUAH tOE C IPD C tCOeE C RCY C tP2P an r Path Control of P Paths St r Display paths longer than za Number of p paths For Help press F1 Num 14 59 09 4 The Performance Analyst performs seven distinct analysis types fMAX tSU tH tPD tCO tOE tCOE and tP2P The first type fMAX is an internal register to register delay analysis MAX measures the maximum clock operating frequency limited by worst case register to register delay The tP2P type is the path between any two user specified pins The remaining five types are external pin to pin delay 2004 Lattice Semiconductor 19 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow analysis Timing threshold filters source and destination filters and path filters can be used to independently fine tune each analysis 3 Under Analysis select tCO and then click Run The tCO path trace analysis reports clock to out delay starting from the primary input going through the clock of flip flops or gate of latches and ending at the primary output In this case it is 12 95 ns Note Your timing results may differ slightly ial Performance Analyst Untitled mux File View Preferences Window Help Untitled mux LC4256 10T1001 DELAY TABLE Operating conditions Industrial ba reg_data reg_data reg_data r
12. ces all generated output files These files include the output files from the synthesis process For ispLEVER projects you should make the working directory the same as your project directory 6 Make sure the path is pointing to lt install_path gt examples tutorial tutor3 then click Set to close the dialog box 2004 Lattice Semiconductor 12 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Set Working Directory xj C MspTOOLS5 O examples T utoraltutora be AS a e CS A ispTOOLS5_O 4J examples B Tutorial 4 tutor3 Cancel H D DA SS JA H PA SS SA A E TA Note Only a few files will be generated in this tutorial Because many generated files can be created in a real project it is a good practice to separate your design source files and batch scripts into a separate subdirectory For example the input source files could be kept in a subdirectory named src Then if your first synthesis run generates the fastest possible circuit you may want to do one or more optional runs to evaluate the tradeoffs between speed and area You can simply copy the src subdirectory into a new working directory named smallest for example and the new generated files for the next run will be placed there 7 At the bottom of the Quick Setup tab click Run Flow LeonardoSpectrum reads the opened input files and creates an in memory EDIF style database called the RTL database The desi
13. d by ispLEVER Attributes that are placed on design objects by the HDL source code and LeonardoSpectrum are converted to properties in the EDIF netlist To synthesize the design 1 On the Quick Setup tab under Technology click the plus sign in front of Lattice to expand the tree view and then select the ispmach4000V device family ispGDX ispGDX2 ispLSI 1 moo ispLSI5000 ispLSIS000VE ispLSI5000VE_old ispLS18000 ispmach4000B ispmach4000C 2 In the Input field click the Open files icon to open the Set Input File s dialog box LeonardoSpectrum does not read pre compiled HDL designs from disk Instead the source files are read directly into memory where LeonardoSpectrum builds an EDIF like in memory database 3 Make sure that you are in the tutorial tutor3 directory 4 Select multiple v and click Open 2004 Lattice Semiconductor 11 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Look in a tutor3 gt ae Es File name muttiple v Files of type Input Files V VERI H VER VHD HC Cancel LeonardoSpectrum automatically points the output file to the project directory and places the file name in the Input box Input multiple v Open files R 3 n Working Directory Le 5 Directly below the Open Files icon click the Working Directory icon to open the Set Working Directory dialog box The working directory is where LeonardoSpectrum pla
14. eq_data C UAH C OE C PD C COE p2P MEN Double click to expand path r Display tco longer than Apply joo r Longest delay Gane Delay path reg_data_3_ C 2z 12 95 NUM 13 39 11 7 Remember from Task 4 that the data arrival time was 7 0 This number was the simulated estimate Now using the Performance Analyst you can see the actual delay of 9 64 ns 4 Click the highlighted cell 12 95 in the spreadsheet window to open the Expanded Path dialog box This dialog box enables you to analyze the individual timing components used to calculate the timing path It shows a source pin From and a destination pin To It also shows the delay type the delay of that path value ns and the cumulative delay of all the signals 2004 Lattice Semiconductor 20 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Expanded Path 1 Source reg_data_3_ C Destination z Help reg_data_3 Export z Equations E 5 Click Equations to open the Equations dialog box which shows the functional relationship between the selected source and the destination Equations lel Es Source req_data_3_ C Destination z reg_data_3_ C Id 1 pterm 1 signal z select_l_ amp select_0_ amp reg_data_2_ Q lselect_1_ amp select_0_ amp reg_data_1_ Q Iselect_1_ amp lselect_O_ amp reg_data_0_ Q select_1_ amp select_0_ amp reg_data_3_ Q 4 pterms 6 signals 6 Close the Perf
15. get a design to a specific Lattice device at any time during the design process The default device is ispLSI5256VE 165LF256 For this project you will target a different device To view the list of available devices and to change the target device 1 In the Project Wizard Select Device dialog box do the following e Inthe Family box select ispMACH4000 e Inthe Device box choose LC4256V e Accept the default settings for the rest of the boxes e Click Next to open the Project Wizard Add Source dialog box Project Wizard Select Device j x Select Device Device Information Family Device Status Production JispMACH 4000 LC4256 ispLS 5000VE LO4256C 160 Pass 10000 ispLSI 8K Device LC4256C Logic cells 256 LC4256v 128 ispMACH 443 LC4256 160 140 cells 64 ispMACH 445 ispMACH 50008 gt LC42562C y 120 pins 64 Dedicated input 6 Speed grade ns Package type 10 horae l Output enable Operating conditions Icc 12 m Part Name LC4256v 1 0T1001 cmo eo 2 In the Project Wizard Add Source dialog box click Next then click Finish Your Project Navigator should look like this 2004 Lattice Semiconductor 7 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow ispLEYER Project Navigator C ISPTOOLS5_0 EXAMPLES TUTORIAL TUTORS mux syn Optimization Constraint X Constraint Editor
16. gn is composed of generic gates and non mapped black box modules such as operators counters and inferred RAMs Next the in memory design is mapped to the specified technology globally optimized and the results for each module are saved If a timing constraint is not met at this point additional critical path optimizations are run to try to meet the constraints The results are kept in a second in memory technology mapped design database The output EDIF netlist and support files are then automatically generated and written to the working directory The Critical Path Report appears in the right pane Note The Run Flow button is not active until you have selected your Input File s and target technology When the synthesis process is complete the Information window on the right says that the run successfully ended 2004 Lattice Semiconductor 13 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Mentor Graphics LeonardoSpectrum for Lattice Information Read Only J Ioj x LS Eile Edit view Tools Window Help js emamna mem see ix Quick Setup 1000 0 MHz Run the entire flow from this one condensed page Specify your source file s technology and desired frequency then press Run Flow Critical Path Report Technology min ispGDX a multiple v Critical path 1 unconstrained path ispGDX2 NAME GATE ARRIVAL ispLSI 1000 2000 31 select
17. iconductor 18 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Task 7 Perform Static Timing Analysis Static timing analysis is the process of verifying circuit timing by totaling the propagation delays along paths between clocked or combinational elements in a circuit The analysis can determine and report timing data such as the critical path setup and hold time requirements and the maximum frequency The Performance Analyst traces each logical path in the design and calculates the path delays using the device s timing model and worst case AC specifications supplied in the device data sheet The timing analysis results are displayed in a graphical spreadsheet with source signals displayed on the vertical axis and destination signals displayed on the horizontal axis The worst case delay value is displayed in a spreadsheet cell if there is at least one delay path between the source and destination To more easily identify performance bottlenecks you can double click a cell to view the path delay details To perform timing analysis 1 In the Project Navigator Sources in Project window select the target device 2 In the Processes for Current Source window double click the Timing Analysis process to open the Performance Analyst ial Performance Analyst Untitled compare File view Net Control Preferences Window Help Data Sheet Operating conditions Version 2 1 DELAY TABLE Commercial z silat
18. nd displays the Tip of the Day and an information screen To start LeonardoSpectrum 1 In the Project Navigator choose Tools gt LeonardoSpectrum Synthesis to open the LeonardoSpectrum synthesis tool It may take a few moments to activate the tool 2 Click OK to close the Tip of the Day There are three ways to synthesize your design Quick Setup Advanced Flow Tabs and Synthesis Wizard In this tutorial you will use the Quick Setup method 3 Make sure the Quick Setup tab is selected on the toolbar Your screen should look similar to the following If not choose Tools gt Quick Setup 2004 Lattice Semiconductor 9 ispLEVER Tutorials Mentor Graphics LeonardoSpectrum for Lattice Information Read Only LS Eile Edit view Tools Window Help HDL Synthesis Design with LeonardoSpectrum CPLD Flow js fee tae as pm ee eet eet a m o emas rejse Quick Setup Run the entire flow from this one condensed page Specify your source file s technology and desired frequency then press Run Flow Info License passed Info system variable EXEMPLAR set to C ISPTOOLSS_0 SPECTRUM r Technology min Lattice Copyright 1990 2004 Mentor Graphics All rights reserved Portions copyright 1991 2004 Compuware Corporation Welcome to LeonardoSpectrum for Lattice Run By xyz Run Started On Thu Mar 10 14 53 48 Pacific Daylight Time 2005
19. ne mode or understand more about its advanced features please see the third party manuals online by choosing Help gt ispLEVER Documentation Library from the ispLEVER Project Navigator Learning Objectives When you have completed this tutorial you should be able to do the following e Create a new EDIF project in the ispLEVER system and target a device e Start LeonardoSpectrum from within the Project Navigator synthesize your Verilog design and generate an EDIF netlist file e Import the EDIF file into the ispLEVER system fit the design generate a JEDEC file and view the Fitter report e Perform static timing analysis using the Performance Analyst and view the results Time to Complete This Tutorial The time to complete this tutorial is about 20 minutes System Requirements One of the following software configurations is required to complete the tutorial e IspLEVER Starter e ispLEVER Base e ispLEVER Advanced e ispLEVER Advanced System with active Mentor Graphics LeonardoSpectrum license Accessing Online Help You can find online help information on any tool included in the tutorial at any time by pressing the F1 key About the Tutorial Design The tutorial design consists of a simple set of equal to greater than and less than data comparators as shown in the following figure 2004 Lattice Semiconductor 2 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow COMPDAT SEL CLK RST
20. ormance Analyst without saving 7 Close LeonardoSpectrum then close ispLEVER without saving 2004 Lattice Semiconductor 21 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Summary You have completed the HDL Synthesis Design with LeonardoSpectrum tutorial In this tutorial you have learned how to do the following e Create anew EDIF project in the ispLEVER system and target a device e Launch LeonardoSpectrum from within ispLEVER and generate an EDIF netlist file using the Quick Setup tab flow e Import the EDIF file into the ispLEVER system fit the design generate a JEDEC file and view the Fitter report e Run static timing analysis using the Performance Analyst and view the results 2004 Lattice Semiconductor 22 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum CPLD Flow Glossary Following are the the terms and concepts that you should understand to use this tutorial effectively EDIF EDIF Electronic Design Interchange Format is a format used to exchange design data between different electronic computer aided design systems It is designed to be written and read by computer programs that are constituent parts of EDA systems or tools Its syntax has been designed for easy machine parsing and is similar to LISP The ispLEVER software supports EDIF Version 2 0 0 HDL An HDL is a hardware description language which describes the structure and function of integrated circuits
21. rum CPLD Flow 2 Double click the HTML Fitter Report process to open the report in your browser 3 View the contents and then close the report mux html Netscape 18 x File Edit View Go Bookmarks Tools Window Help M Q X File C ISPTOOLSS_O EXAMPLES TUTORIAL TUTOR3 mux html iy SS A hl J EA S Home My Netscape Q Search S Instant Message WebMail Radio People amp Yellow Pages S Download Calendar Fichannels a Q Netscape Enter Search Terms E Aseh Hohi PO SSS PFormFill Clear Browser History News Email Weather gt Table of Contents ispLEVER 5 0 00 32 10 05_CP_ALL Fitter Report File Top Project Summary Compilation Times Design Summary Device Resource Summary GLB Resource Summary GLB Control Summary Optimizer and Fitter Options All Rights Reserved Pinout Listing Input Signal List Output Signal List Bidir Signal List Buried Signal List The Basic Detailed Report Format can be selected in the dialog box PostFit Equations Tools gt Fitter Report File Format Copyright C 1992 2005 Lattice Semiconductor Corporation Project Summary Project Name i mux Project Path C ISPTOOLSS_0O EXAMPLES TUTORIAL TUTOR3 Project Fitted on Thu Mar 10 15 00 47 2005 Device M4256 _64 Package 100 GLB Input Mux Size 33 Available Blocks 16 Speed 10 Part Number LC4256V 10T1001I Source Format EDIF Project mux Fit Successfully OA SF BD ore 2004 Lattice Sem
22. s a JEDEC file Optional If you like you can right click on the JEDEC File process and select View to create and look at the contents of the JEDEC file Close the file when you are through E ispLEYER Project Navigator C ISPTOOLS5_0 EXAMPLES TUTORIAL TUTOR3 mux syn File View Source Process Options Tools Window Help 0 tae Gad normal S LE v co a a em v PEETS Mie wf OO Sources in Project Processes for current source mux Gj Documents f m LC4256V 10T1001 B multiplexer4to1 multiple _0 edf Timing Driven Analyze 2 0 Done completed successfully Starting Done completed successfully supported by Lattice Semiconductor ispLEVER 5 00 Copyright 1992 2005 Lattice Semiconductor U K Optimization Constraint K Constraint Editor W O Fit Design E Pre Fit Equations A Signal Cross Reference ef E Fitter Report A E HTML Fitter Report Post Fit Pinouts A Post Fit Re Compile Aw JEDEC File f 15C 1532 File K Timing Analysis B Timing Report 8 Generate Timing Simulation Files B Report File gt Generate Board level Stamp Model B Stamp Model File fei Stamp Model Data File All Rights Reserved C N ispTOOLSS_O ispepld bin synsvf exe exe C ispTOOLSS_O ispvmsystem ispufw prj 1 Need not generate svf file according to the constraints exit 2004 Lattice Semiconductor 17 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpect
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