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AT-MIO-16X User Manual - Artisan Technology Group

1. ete 4 28 Table 4 10 Analog Output Voltage Versus Digital Code Unipolar Mode 4 30 Table 4 11 Analog Output Voltage Versus Digital Code Bipolar Mode 4 31 Table 5 1 Am9513A Counter Timer Allocations 5 1 Table 5 2 RTSI Switch Signal Conte tlOpis sn nant eee teat enda as eee ia Sera Mec 5 27 Table 6 1 EEPROM Factory Area Information eese nennen 6 2 Table 6 27 Calibration DAC Srini edet a tie Du atas m 6 5 Table 1 Equivalent Offset Errors in 16 Bit Systems A 2 Table 2 Equivalent Gain Errors in 16 Bit Systems A 3 Table 3 Typical Multiple Channel Scanning Settling Times 4 National Instruments Corporation AT MIO 16X User Manual Chapter 1 Introduction This chapter describes the AT MIO 16X lists the contents of your AT MIO 16X kit the optional software and optional equipment and explains how to unpack the AT MIO 16X About the AT MIO 16X Congratulations on your purchase of the National Instruments AT MIO 16X The AT MIO 16X is a high performance software configurable 16 bit DAQ board for laboratory test and measurement and data acquisition and control applications The board performs high accuracy measurements with self calibration high speed settling to 16 bits noise as low as 0 8 LSBrms and a maximum DNL of 0 5 LSB Because of its large FIFOs and dual channel DMA the AT MIO 16X ca
2. nette en a cd nine 2 26 EXTSTROBE Signal tenaient 2 27 Signal 2 28 EXTITRIG Signal Timing inerte 2 29 EXITMRTRIGr Signal Urine oss evite vs dy eaa dead 2 30 Event Counting Application with External Switch Gating 2 31 Frequency Measurement Application 2 32 General Purpose Timing Signals sess 2 33 AT MIO 16X Block Diagramme 3 1 PC I O Channel Interface Circuitry Block Diagram eese 3 3 Analog Input and Data Acquisition Circuitry Block Diagram 3 5 ADC Conversion THE cose quedes eva qoe 3 8 Single Channel Posttrigger Data Acquisition Timing eese 3 0 Single Channel Pretrigger Data Acquisition Timing eee 3 10 Scanning Posttrigger Data Acquisition Timing eee 3 11 Interval Scanning Posttrigger Data Acquisition Timing ess 3 12 Analog Output Circuitry Block 3 13 Analog Output Waveform 3 15 Posted DAC Update 3 16 Analog Output Waveform 3 17 FIFO Cyclic Waveform Generation with Disable
3. m Voltage I O Connector AT MIO 16X Board in the NRSE Input Configuration Figure 2 10 Single Ended Input Connections for Ground Referenced Signals Common Mode Signal Rejection Considerations Figures 2 7 and 2 8 located earlier in this chapter show connections for signal sources that are already referenced to some ground point with respect to the AT MIO 16X In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the AT MIO 16X In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the AT MIO 16X The common mode input range of the AT MIO 16X PGIA is defined as the magnitude of the greatest common mode signal that can be rejected The PGIA can reject common mode signals as long as V in and jn are both in the range 11 V Thus the common mode input range for the AT MIO 16X depends on the size of the differential input signal V aiff Vtin The exact formula for the allowed common mode input range is as follows Voem max 11 V Vaiff 2 National Instruments Corporation 2 23 AT MIO 16X User Manual Configuration and Installation Chapter 2 With a differential voltage of 10 V the maximum possible common mode voltage is 6 V The common mode voltage is measured with respect to the AT MIO 16X ground and can be calculated by the following formula V
4. A 2 lura EO A 2 Nonlinear Mens nt n ne A 3 NOIE uis 4 Analog Data Acquisition ore stesso donnant ne en A 4 Single Channel Acquisition Rates 4 Multiple Channel Scanning Acquisition 4 Analog Output Eaa 5 Explanation of Analog Output Specifications A 6 AT MIO 16X User Manual viii National Instruments Corporation Contents ilio rH M A 6 Haine TOV retinas nan ee Quo de que Ait brute 7 Power Requirement from PC I O Channel ss 7 PHVSICal 7 Operating Environment otc eee at Ie hes Is Ui lateri bee 7 Storage Environment ete found Re S en A 7 Appendix B HO CORRECTION ea dt ea EET B 1 Signal Connection Descriptions s B 3 Appendix C AMD Am9513A Data Sheet C 1 Appendix D Customer Communication D 1 lllo P Index 1 abeunte c terti dat Me rd Glossary 1 National Instruments Corporation ix AT MIO 16X User Manual Contents Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9
5. This pin is from the Am9513A Counter 1 signal OUTPUT This pin is from the Am9513A Counter 1 signal External Timer Trigger If selected a high to low edge on EXTTMRTRIG results in the output DACs being updated with the value written to them in the posted update mode EXTTMRTRIG will also generate a timed interrupt if enabled GATE2 This pin is from the Am9513A Counter 2 signal OUTPUT This pin is from the Am9513A Counter 2 signal SOURCES This pin is from the Am9513A Counter 5 signal GATES This pin is from the Am9513A Counter 5 signal OUTS This pin is from the Am9513A Counter 5 signal Frequency Output This pin is from the Am9513A FOUT signal AT MIO 16X User Manual Configuration and Installation Chapter 2 The signals on the connector can be classified as analog input signals analog output signals digital I O signals digital power connections or timing I O signals Signal connection guidelines for each of these groups are given in the following section Analog Input Signal Connections AI GND is an analog input common signal that is routed directly to the ground tie point on the AT MIO 16X These pins can be used for a general analog power ground tie point to the AT MIO 16X if necessary In NRSE mode AI SENSE is connected internally to the negative input of the AT MIO 16X PGIA In the DIFF and RSE modes this signal is driven by AI GND or left unconnected Signal pins
6. cm actual 2 V where V is the signal at the positive input of the and V is the signal at the negative input of the Both V and are measured with respect to AI GND Analog Output Signal Connections OUT is the voltage output signal for analog output Channel 0 DAC1 OUT is the voltage output signal for analog output Channel 1 EXTREF is the external reference input for both analog output channels Each analog output channel must be configured individually for external reference selection in order for the signal applied at the external reference input to be used by that channel Analog output configuration instructions are in the Analog Output Configuration section earlier in this chapter The following ranges and ratings apply to the EXTREF input Normal input voltage range 10 V peak with respect to AO GND Usable input voltage range 18 V peak with respect to AO GND Absolute maximum ratings 30 V peak with respect to AO GND AO GND is the ground reference point for both analog output channels and for the external reference signal Figure 2 11 shows how to make analog output connections and the external reference input connection to the AT MIO 16X board AT MIO 16X User Manual 2 24 National Instruments Corporation Chapter 2 Configuration and Installation EXTREF External Reference Signal Optional Channel 1 Analog Output Channels 16 Board Figure
7. 5 AI GND ACHS8 9 10 ACHII ACHI2 ACH13 14 15 DACO OUT EXTREF DIG GND BDIOO BDIOI BDIO2 BDIO3 5 V SCANCLK EXTTRIG EXTCONV GATEI EXTTMRTRIG OUT2 GATES FOUT Figure B 1 AT MIO 16X 50 Pin I O Connector National Instruments Corporation B 1 AT MIO 16X User Manual I O Connector Appendix B Figure B 2 shows the pin assignments for the AT MIO 16X 68 pin I O connector ACH8 ACHI AIGND ACHIO ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND 15 DACO DACI EXTREF BDIOO DGND ADIOI BDIO2 DGND 5 V DGND DGND EXTTRIG EXTGATE DGND 5 DGND EXTTMRTRIG GATE2 DGND GATES OUTS FOUT 95 N N N N UJ UJ Hll e S 8 2 o ww we TR ER RTE RP elles ul ululululululululu IS 2 mIDISIRIU ACHO AIGND ACH9 ACH2 AIGND ACHII AISENSE ACHI2 5 AIGND 14 ACH7 AIGND AOGND AOGND DGND ADIOO BDIOI DGND ADIO2 BDIO3 ADIO3 SCANCLK EXTSTROBE DGND EXTCONV SOURCEI GATEI OUTI DGND OUT2 SOURCES DGND DGND Figure B 2 AT MIO 16X 68 Pin I O Connector AT MIO 16X User Manual B 2 National Instruments Corporation Appendix B Signal Connection Descriptions 68 Pin Pins 24 27 29 32 56
8. 32768 24576 16384 8192 0 8192 16384 24576 327768 ADC Code Figure A 1 Typical Relative Accuracy of Analog Input Circuitry Nonlinear Errors Relative accuracy is a measure of the non linearity of an analog system It indicates the maximum deviation of the averaged analog input to digital output transfer curve from an endpoint fit straight line If the analog circuitry has been calibrated perfectly then the endpoint fit straight line is the ideal transfer function and the relative accuracy specification indicates the farthest deviation from the ideal that the system permits Figure A 1 shows the typical relative accuracy of the AT MIO 16X input National Instruments Corporation A 3 AT MIO 16X User Manual Specifications Appendix A Differential nonlinearity DNL is a measure of deviation of code widths from their theoretical value of 1 LSB The width of a given code is the size of the range of analog values that can be input to produce that code ideally 1 LSB A specification of 1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs that is no missing codes and that no code width exceeds 2 LSBs DNL is measured using histograms Noise System noise is the amount of noise in LSB rms in the ADC data when there is no signal present at the input of the board This figure includes the quantization noise of the ADC Analog Data Acquisition Rates Single Channel Acquisition Rates The maximum single ch
9. Connector S SOURCE4 SOURCE3 OUTI CONVERT OUT2 Data OUT3 Acquisition SCANCLK OUT4 Timing OUTS CONFIGCLK GATE3 EXTTRIG Figure 3 17 Timing I O Circuitry Block Diagram AT MIO 16X User Manual 3 20 National Instruments Corporation Chapter 3 Theory of Operation Am9513A contains five independent 16 bit counter timers a 4 bit frequency output channel and five internally generated timebases The five counter timers can be programmed to operate in several useful timing modes The programming and operation of the Am9513A are presented in detail in Appendix C AMD Am9513A Data Sheet Am9513A clock input is one tenth the BRDCLK frequency BRDCLK is selected through a register in the AT MIO 16X register set The factory default for BRDCLK is 10 MHz which generates a 1 MHz clock input to the Am9513A The Am9513A uses this clock input plus BRDCLK divided by two input at Source 2 to generate six internal timebases These timebases can be used as clocks by the counter timers and by the frequency output channel When BRDCLK is 10 MHz the six internal timebases normally used for AT MIO 16X timing functions are 5 MHz 1 MHz 100 KHz 10 kHz 1 kHz and 100 Hz The 16 bit counters in the Am9513A can be diagrammed as shown in Figure 3 18 SOURCE COUNTER Figure 3 18 Counter Block Diagram Each counter has a SOURCE input pin a GATE input pin and an output pin label
10. DRVAIS 4 14 EEPROMCD 4 21 EEPROMCS 4 5 EEPROMDATA 4 21 EISA DMA 4 9 EXTREFDACO 4 9 EXTREFDACI 4 9 DIS 4 18 FIFO DAC 4 18 GATE2SEL 4 18 5 23 INTCHB lt 2 0 gt 4 14 INTGATE 4 6 I O INT 4 12 OUT lt 5 1 gt 4 55 OUTEN 5 29 OVERFLOW 4 20 5 5 5 16 OVERRUN 4 20 5 5 5 1 RETRIG_DIS 4 6 RSI 4 60 RTSITRIG 4 7 52 through SO bits 5 29 SCANDIV 4 5 5 11 SCANEN 4 6 5 8 5 9 SCLK 4 5 SCN2 4 6 5 10 SDATA 4 5 SRC3SEL 4 18 5 21 5 23 TMRREQ 4 20 5 23 5 25 5 26 5 31 board and RTSI clock selection See RTSI clock configuration board configuration See configuration BYTEPTR bit 4 55 C C lt 7 0 gt bit 4 54 cables and cabling cabling considerations 50 pin connector 2 35 68 pin connector 2 36 field wiring considerations 2 34 to 2 35 Calibration DAC 0 Load Register 4 50 Calibration DAC 1 Load Register 4 51 calibration procedures calibration DACs 1 2 6 5 EEPROM ADC and DAC FIFO Depth field table 6 4 Area Information field table 6 4 Configuration Memory Depth Field table 6 3 EEPROM map 6 1 factory area information table 6 2 National Instruments Corporation Revision and Subrevision field table 6 3 storage area 1 2 6 3 equipment requirements 6 5 input calibration 3 7 6 6 output calibration 3 14 6 7 reference calibration 6 6 CFGMEMEF bit 4 21 CHAN AIS bit 4 26 CHAN BIP bit 4 26 CHAN CAL bit 4 26 CHAN DSP bit 4 28 GHOST b
11. 2112 1 AT MIO 16X User Manual 4 10 National Instruments Corporation Chapter 4 Register Map and Descriptions Command Register 3 Command Register 3 contains 16 bits that control the ADC link to the AT DSP2200 digital I O port interrupt and DMA modes and interrupt channel selection The contents of this register are defined to be cleared upon power up and after a reset condition Address Base address 04 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 ADCREQ DACIREQ DACOREQ DRVAIS INTCHB2 INTCHB1 INTCHBO LSB Bit Name Description 15 ADCDSP ADC DSP Link Enable This bit controls the serial link from the A D converter to the AT DSP2200 If ADCDSP is set then the serial link is enabled Data from channels that have been marked in the channel configuration memory will be transmitted over the RTSI bus If ADCDSP is cleared the serial RTSI link is disabled irrespective of the marking of channels in the channel configuration memory 14 DIOPBEN Digital I O Port B Enable This bit controls the 4 bit digital output port B If DIOPBEN is set the Digital Output Register drives the DIOK lt 8 5 gt digital lines at the I O connector If DIOPBEN is cleared the Digital Output Register drivers are set to a high impedance state therefore an external device can drive the DIO 8 5 digital lines 13 DIOPAEN Digital I O Port A Enable This bit
12. AT MIO 16X User Manual 3 10 National Instruments Corporation Chapter 3 Theory of Operation Continuous Scanning Data Acquisition Timing Continuous scanning data acquisition uses the configuration memory register to automatically sequence from one analog input channel setting to another during the data acquisition sequence Continuous scanning cycles through the configuration memory without any delays between cycles Scanning is similar to the single channel acquisition in the programming of both the sample interval counter and the sample counter Scanning data acquisition is enabled through a register in the AT MIO 16X register set Figure 3 7 shows the timing for a continuous scanning data acquisition sequence Trigger DAQPROG CONVERT Channel SCANCLK DAQCMPLT Interrupt DAQCLEAR VMLFE Figure 3 7 Scanning Posttrigger Data Acquisition Timing In this sequence the timing is the same as the single channel acquisition except for the addition of the channel sequencing and the generation of the SCANCLK signal The first sampled channel is Channel 0 followed in time by Channel 1 and finally Channel 2 After this the sequence is repeated For this example the sequence consists of Channels 0 1 and 2 which are cycled through twice to generate six values of conversion data After the six samples have been acquired the sample counter terminates the data acquisition sequence The SCANCLK signal is generated to indicate when
13. Address Base address 18 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used Strobe Effect Updates latched DAC values to the DAC Register in posted update mode sets the TMRREQ signal in Status Register 1 and generates an interrupt or DMA request if enabled National Instruments Corporation 4 43 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 DAC Clear Register Accessing the DAC Clear Register clears parts of the DAC circuitry including emptying the DAC FIFO Address Base address 1E hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Empties the DAC FIFO clears the TMRREQ bit in Status Register 1 and its associated interrupts and clears the DACCOMP bit in Status Register 1 and its associated interrupts AT MIO 16X User Manual 4 44 National Instruments Corporation Chapter 4 Register Map and Descriptions General Event Strobe Register Group The General Event Strobe Register Group consists of six registers that when written to cause the occurrence of certain events on the AT MIO 16X board such as clearing flags and starting A D conversions Bit descriptions of the six registers making up the General Event Strobe Register Group are given on the following pages National Instruments Corporation 4 45 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 DMA Channel Clear Register Accessing the DMA Chan
14. EISA Extended Industry Standard Architecture F farads FIFO first in first out FSR full scale range ft feet HCT high speed CMOS TTL hex hexadecimal Hz hertz ksamples 1 000 samples LED light emitting diode LS low power schottsky LSB least significant bit MB megabytes m meters MSB most significant bit NRSE nonreferenced single ended PGIA programmable gain instrumentation amplifier ppm parts per million rms root mean square RSE referenced single ended RTSI Real Time System Integration National Instruments Corporation Glossary 1 AT MIO 16X User Manual Glossary SCXI Signal Conditioning eXtensions for Instrumentation S seconds TC terminal count TTL transistor transistor logic V volts VDC volts direct current Vref voltage reference Vrms volts root mean square AT MIO 16X User Manual Glossary 2 National Instruments Corporation Index Numbers Symbols 5 V power pins warning against connecting 2 27 5 V signal 2 14 B 3 A A2DRvV bit 4 8 5 28 A2RCV bit 4 8 5 28 A4DRV bit 4 8 5 28 A4RCYV bit 4 8 5 26 5 28 A6 through 0 bits 5 29 ACH O 15 signals 2 14 2 16 B 3 A D conversion results in ADC FIFO 4 24 reading single conversion result 5 5 straight binary mode A D conversion values table 4 25 two s complement mode A D conversion values table 4 25 A D converter 3 7 Calibration Register 4 40 ADC conversion timing 3 8 ADC Event Strobe Register Group 4 34
15. aono nue reas eg 6 4 Figure A 1 Typical Relative Accuracy of Analog Input Circuitry eese A 3 Figure B 1 AT MIO 16X 50 Pin I O Connector ss B 1 Figure B 2 16 68 Pin I O Connector seen B 2 Tables Table 2 1 Default Settings of National Instruments Products for the PC 2 5 Table 2 2 Switch Settings with Corresponding Base I O Address and Base I O Address MMOL D ET 2 5 Table 2 3 Available Input Configurations for the 16 2 7 Table 2 4 Actual Range and Measurement Precision Versus Input Range Selection and RE CPR EN RENTE EU 2 9 Table 2 5 Recommended Input Configurations for Ground Referenced 2 18 Table 4 1 16 Register poda ees 4 1 Table 42 DMA Channel Selection 2o roi fae ede din 4 10 Table 4 3 DMA and Interrupt MOSS eaae edge pps 4 13 Table 4 4 Interrupt Level Sele ctn P REA 4 15 Table 4 5 Board and RTSI Clock SelecttOn soi ones 4 16 Table 4 6 Analog Output Waveform Modes 4 17 Table 4 7 Straight Binary Mode A D Conversion Values eere 4 25 Table 4 8 Two s Complement Mode A D Conversion Values 022121 4 25 Table 4 9 Input C Oni guration
16. lt 0 15 gt are tied to the 16 analog input channels of the AT MIO 16X In single ended mode signals connected to lt 0 15 gt are routed to the positive input of the AT MIO 16X PGIA In differential mode signals connected to lt 0 7 gt are routed to the positive input of the AT MIO 16X and signals connected to lt 8 15 gt are routed to the negative input of the AT MIO 16X PGIA Warning Exceeding the differential and common mode input ranges results in distorted input signals Exceeding the maximum input voltage rating can result in damage to the AT MIO 16X board and to the PC National Instruments is not liable for any damages resulting from such signal connections Connection of analog input signals to the AT MIO 16X depends on the configuration of the AT MIO 16X analog input circuitry and the type of input signal source With the different AT MIO 16X configurations you can use the AT MIO 16X in different ways Figure 2 6 shows a diagram of the AT MIO 16X PGIA Programmable Gain V Measured Voltage Gain 1 2 5 10 20 50 100 Figure 2 6 AT MIO 16X PGIA AT MIO 16X User Manual 2 16 National Instruments Corporation Chapter 2 Configuration and Installation The AT MIO 16X PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to the AT MIO 16X board Signals are routed to the positive a
17. sees 3 17 FIFO Programmed Cyclic Waveform Timing eee 3 18 FIFO Pulsed Waveform Generation Timing seen 3 18 Digital Circuitry Block 3 19 Timing I O Circuitry Block Diagram ss 3 20 Counter Block DISSEatibs sanie Cseterum QU ee Pie they ante EHI 3 2 Bus Interface Circuitry Block Diagram eere 3 23 Initializing the Am9513A 5 3 Single Conversion Programming ri qose Duo Fog 5 4 Single Channel Data Acquisition Programming 5 6 Scanning Data Acquisition Programming 5 8 Interval Scanning Data Acquisition 5 0 Resetting an Am9513A Counter Timer us 5 17 Cyclic Waveform Programming a esset tenian eo ae e HAY nenne e a area 5 19 Programmed Cycle Waveform Programming 5 20 Pulsed Cyclic Waveform Programming ss 5 22 RESLS Witch Control Pallet edente 5 29 AT MIO 16X User Manual x National Instruments Corporation Contents Figure 6 1 AT MIO 16X EEPROM Map sisi 6 1 Figure 6 2 Revision and Subrevision Field 6 3 Figure 6 3 Configuration Memory Depth Field eee 6 3 Figure 6 4 ADC and DAC Depth str Pee eot ance cae 6 4 Figure 6 5 Area Information Field
18. 2 9 posted update mode 3 14 to 3 16 postgain offset error analog input circuitry A 2 posttrigger data acquisition timing Index 10 National Instruments Corporation multiple channel scanned data acquisition 3 11 single channel data acquisition 3 9 power connections I O connector 2 27 power requirements A 7 pregain offset error A 2 pretrigger data acquisition timing 3 9 to 3 10 programmed cycle waveform generation 5 19 to 5 21 programming See also registers Am9513A Counter Timer 5 26 to 5 27 analog input circuitry 5 4 data acquisition functions 5 10 to 5 26 analog output circuitry 5 18 applying a trigger 5 15 to 5 16 clearing analog input circuitry 5 10 cyclic waveform generation 5 18 to 5 19 multiple analog input channel configurations 5 11 programmed cycle waveform generation 5 19 to 5 21 pulsed cyclic waveform generation 5 21 to 5 23 resetting hardware 5 16 to 5 17 sample counter s 5 12 to 5 14 sample interval counter 5 11 to 5 12 scan interval counter 5 14 to 5 15 servicing data acquisition operations 5 16 single analog input channel configurations 5 10 waveform cycle counter 5 24 to 5 25 waveform cycle interval counter 5 25 to 5 26 waveform generation functions 5 23 to 5 24 data acquisition sequences with channel scanning 5 7 to 5 10 continuous channel scanning 5 7 to 5 8 interval channel scanning 5 8 to 5 10 digital I O circuitry 5 26 initialization Am9513A 5 2 to 5 3 AT
19. A 16 bit count mode can be used if the number of A D sample conversions to be performed is less than 65 537 A 32 bit count mode should be used if the number of A D sample conversions to be performed is greater than or equal to 65 537 4 6 National Instruments Corporation Chapter 4 Register Map and Descriptions Bit Name Description continued 4 RTSITRIG RTSI Trigger This bit controls multiple board synchronization through RTSI Bus triggering If RTSITRIG is set then triggering of the data acquisition sequence by another National Instruments board over the RTSI bus is enabled Otherwise if RTSITRIG is cleared the data acquisition sequence is triggered by the onboard Start DAQ Register or a high to low transition on the EXTTRIG signal at the I O Connector When this bit is set the local DAQ Start Register and the EXTTRIG signal have no effect 3 0 0 Reserved These bits must always be set to zero National Instruments Corporation 4 7 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Command Register 2 Command Register 2 contains 15 bits that control AT MIO 16X RTSI bus transceivers analog output configuration and DMA Channels A and B selection Bits 8 15 of this register are cleared upon power up and after a reset condition Bits 0 7 of this register are undefined upon power up and are not cleared after a reset condition These bits should be initialized through software Address Base address 02
20. Bits 8 15 of this register are cleared upon power up or following a reset condition Bits 0 7 of this register are undefined upon power up and are not cleared after a reset condition These bits should be initialized through software Address Base address 4 06 hex Type Write only World Size 16 bit Bit Map 15 14 13 12 11 10 9 8 CLKMODEBI CLMODEBO DACIDSP DACODSP DACMB3 DACMB2 DACMBI DACMBO MSB 7 6 5 4 2 2 1 0 DACGATE DB DIS CYCLICSTOP ADCFIFOREQ SRC3SEL GATE2SEL FIFO DAC EXTTRIG DIS LSB Bit Name Description 15 14 CLKMODEB lt 1 0 gt Clock Mode Select These bits control the selection of the board clock and RTSI bus clock Upon power up CLKMODEB1 and CLKMODEBO are cleared In this condition the board is configured for internal 10 MHz operation For other available modes see Table 4 5 for bit patterns Table 4 5 Board and RTSI Clock Selection Effect RTSI Clock Board Clock Internal 10 MHz Internal 10 MHz 1 Driven onto board clock Received from RTSI clock AT MIO 16X User Manual 4 16 National Instruments Corporation Chapter 4 Bit Name 13 DACIDSP 12 DACODSP 11 8 DACMB lt 3 0 gt 7 DACGATE Register Map and Descriptions Description continued DAC 1 DSP Link Enable This bit controls the serial link from the AT DSP2200 to DAC 1 of the analog output section If DACIDSP is set then the serial link is enabled Data is sent from the AT DSP2200 over the RTSI bus and is a
21. National Instruments Corporation Appendix A Timing I O Number of channels Resolution Base clock available Base clock accuracy Compatibility Counter input frequency Specifications 3 counter timers 1 frequency output 16 bit for 3 counter timers 4 bit for frequency output channel 5 MHz 1 MHz 100 kHz 10 kHz 1 kHz 100 Hz 0 01 TTL compatible inputs and outputs Counter gate and source inputs are pulled up with 4 7 KQ resistors onboard 6 9 MHz maximum 145 nsec period with a minimum pulse width of 70 nsec Power Requirement from PC I O Channel Power consumption Physical Board dimensions T O connector Operating Environment Component temperature Relative humidity Storage Environment Temperature Relative humidity National Instruments Corporation 2 0 A typical at 5 VDC 13 3 by 4 5 in 50 pin male ribbon cable connector or 68 pin male shielded cable connector 0 to 70 C 596 to 9096 noncondensing 55 to 150 596 to 9096 noncondensing 7 AT MIO 16X User Manual Appendix B I O Connector This appendix describes the pinout and signal names for the AT MIO 16X 50 pin I O connector and the 68 pin I O connector Figure B 1 shows the 16 50 pin I O connector AI GND ACHO ACHI ACH2 ACH3 4 5 ACH6 ACH7 AI SENSE DACI OUT AO GND ADIOO ADIOI ADIO2 ADIO3 DIG GND 5 EXTSTROBE EXTGATE SOURCE OUTI GATE2 SOURCES
22. Pregain offset error is the amount of possible voltage offset error in the circuitry before the gain stage Its contribution to total offset error is multiplied by the gain Postgain offset error is the amount of possible voltage offset error in the circuitry following the gain stage Its contribution to total offset error is not multiplied by the gain The total offset error is the postgain offset error plus the gain times the pregain offset error Gain error is the amount of possible deviation from ideal gain expressed as a proportion of the gain The total linear measurement error for a given input voltage takes into account all gain and offset errors but does not include any nonlinear errors such as relative accuracy It is the sum of the gain error times the input voltage the gain times the pregain offset error and the postgain offset Tables 1 2 list equivalent offset and gain errors for 16 bit ADC systems and may be useful for comparing systems They also apply to 16 bit DAC systems Table A 1 Equivalent Offset Errors in 16 Bit Systems Voltage of FSR Range 0to 10 V 152 6 0 001526 1 10 to 10 V 305 2 uV 0 001526 AT MIO 16X User Manual A 2 National Instruments Corporation Appendix A Specifications Table A 2 Equivalent Gain Errors in 16 Bit Systems 0 to 10 V 1 0 001526 0 001526 15 26 ppm 10 to 10 V 1 0 001526 0 003052 30 52 ppm Error LSB
23. Scan Clock This pin pulses once for each A D conversion in the scanning modes The low to high edge indicates when the input signal can be removed from the input or switched to another signal National Instruments Corporation Chapter 2 68 Pin Pins 45 11 10 43 42 41 40 38 37 50 Pin Pins 37 38 39 40 41 42 43 44 45 46 47 48 49 50 National Instruments Corporation Signal Names EXTSTROBE EXTTRIG EXTGATE EXTCONV SOURCEI GATEI OUTI EXTTMRTRIG GATE2 OUT2 SOURCES GATES OUTS FOUT 2 15 Configuration and Installation Descriptions continued External Strobe Writing to the EXTSTROBE Register results in a minimum 500 nsec low pulse on this pin External Trigger In posttrigger data acquisition sequences a high to low edge on EXTTRIG initiates the sequence In pretrigger applications the first high to low edge of EXTTRIG initiates pretrigger conversions while the second high to low edge initiates the posttrigger sequence External Gate When EXTGATE is low A D conversions are inhibited When EXTGATE is high A D conversions are enabled External Convert A high to low edge on EXTCONV causes A D conversion to occur Conversions initiated by the EXTCONV signal are inhibited outside of a data acquisition sequence and when gated off SOURCE This pin is from the Am9513A Counter 1 signal
24. assuming that differential inputs are used Tie the shield for each signal pair to the ground reference at the source e If you use a non shielded cable such as a ribbon cable Route the analog lines separately from the digital lines When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise from switching digital signals coupling into the analog signals AT MIO 16X User Manual 2 36 National Instruments Corporation Chapter 3 Theory of Operation This chapter contains a functional overview of the AT MIO 16X and explains the operation of each functional unit making up the AT MIO 16X Functional Overview The block diagram in Figure 3 1 is a functional overview of the AT MIO 16X board ADC Interrupt Mux Mode 16 Bit Selection Sampling A D Switches Interface TA Channel Data ee Control amp I O Connector Data Control Input dex AC p RTSI Bus DACO Control Interface Serial ADC Data pact AG Serial DAC Data 4 Calibration C ESTs DACs Figure 3 1 AT MIO 16X Block Diagram National Instruments Corporation 3 1 AT MIO 16X User Manual Theory of Operation Chapter 3 The following major components make up the AT MIO 16X board PC I O channel interface circuitry Analog input circuitry Data acquisition circuitry Analog output circuitry DAC waveform generati
25. configuration list is reached or the memory becomes full After the final write to the channel AT MIO 16X User Manual 4 26 National Instruments Corporation Chapter 4 Register Map and Descriptions configuration memory the CONFIGMEMLD Register should be strobed to load the first channel configuration value At this point the channel configuration memory is primed and does not need to be accessed again until a new channel configuration sequence is desired Conversions either by EXTCONV or by Counter 3 of the Am9513A Counter Timer automatically sequence through the channel configuration memory as programmed When the end of the channel configuration memory is detected it is automatically reset to the first value in the list Strobing the DAQ Clear Register also resets the channel configuration memory to the first value in the list without destroying existing channel configuration values A strobe of the CONFIGMEMLD Register is still necessary to load the first value in the memory Continual strobing of the CONFIGMEMLD Register with only one value in the list serves only to reload this one value Continual strobing with more than one value in the memory sequences through the channel configuration list In the single channel data acquisition mode only one value should be written and loaded into the channel configuration register National Instruments Corporation 4 29 AT MIO 16X User Manual Register Map and Descriptions Chapter 4
26. line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and so the PGIA does not reject it In this case instead of directly connecting the negative line to AI GND connect it to AI GND through a resistor that is about 100 times the equivalent source impedance This puts the signal path nearly in balance so about the same noise couples onto both and connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the 100 GQ input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AI GND This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for instance the source impedance is 2 and the AT MIO 16X User Manual 2 20 National Instruments Corporation Chapter 2 Configuration and Installation two resistors are each 100 the resistors load down the source with 200 and produce a 196 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled then the PGIA needs a resistor between the positive input and AI GND If the sou
27. the DAC FIFO is at least half full of data If DACFIFOHF is set the DAC FIFO is not half full of data If the appropriate DAC and I O modes are enabled interrupts or DMA requests are generated when the DAC FIFO is less than half full DAC FIFO Empty Flag This bit reflects the state of the DAC FIFO If DACFIFOEF is clear the DAC FIFO is empty If DACFIFOEF is clear before the last point has been transferred to the DACs and DACCOMP is set this is an error condition and should be handled appropriately If DACFIFOEF is set then the DAC FIFO has at least one remaining point to be transferred EEPROM Data This bit reflects the value of the data shifted out of the EEPROM using SCLK with EEPROMCS enabled EEPROM Chip Deselect This bit reflects the status of the EEPROM chip select pin Because protection circuitry surrounds the EEPROM having EEPROMCS enabled in Command Register 1 does not necessarily result in the EEPROM being enabled If EEPROMCD is low after a mode has been shifted into the EEPROM an error occurred in shifting in an unsupported mode To initialize EEPROMCD EEPROMCS must be brought low while SCLK is pulsed high Configuration Memory Empty Flag This bit indicates the status of the channel configuration memory If this bit is clear the channel configuration memory is empty and can be written to If CFGMEMEF is set the channel configuration memory is not empty National Instruments Corporation 4 21
28. value for pretrigger acquisition modes 3 Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register 4 Write the sample count value to the Am9513A Data Register to store the Counter 4 load value Ifthe sample count is between 2 FFFF 65 535 decimal write the sample count to the Am9513A Data Register e Ifthe sample count is 10000 65 536 decimal write 0 to the Am9513A Data Register Write 48 to the Am9513A Command Register to load Counter 4 Write FFF4 to the Am9513A Command Register to decrement Counter 4 Write FF28 to the Am9513A Command Register to arm Counter 4 9o SO OU Clear the CNT32 16 bit in Command Register 1 to notify the hardware that only Counter 4 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and turns off the data acquisition operation when Counter 4 decrements to zero Sample Counts Greater than 65 536 To program the sample counter for sample counts greater than 65 536 use the following programming sequence to concatenate Counter 4 to Counter 5 The lower 16 bits of the sample count are stored in Counter 4 and the upper 16 bits of the sample count are stored in Counter 5 writes are 16 bit operations values given are hexadecimal 1 Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register 2 Write 1025 to the Am951
29. 1 is configured for unipolar operation When DAC Channel 1 is configured for bipolar operation the data is interpreted in two s complement form National Instruments Corporation 4 33 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 ADC Event Strobe Register Group The ADC Event Strobe Register Group consists of six registers that when written to cause the occurrence of certain events on the AT MIO 16X board such as clearing flags and starting A D conversions Bit descriptions of the six registers making up the ADC Event Strobe Register Group are given on the following pages AT MIO 16X User Manual 4 54 National Instruments Corporation Chapter 4 Register Map and Descriptions CONFIGMEMCLR Register Accessing the CONFIGMEMCLR Register clears all information in the channel configuration memory and resets the write pointer to the first location in the memory Address Base address 1B hex Type Read only Word Size 8 bit Bit map Not applicable no bits used Strobe Effect Clears the channel configuration memory Before the channel configuration memory is written to it must be cleared of its existing information and reset to an initialized state This process is accomplished by accessing the CONFIGMEMCLR Register Once the existing channel configuration values are cleared they are not recoverable At this point the channel configuration memory is ready to be filled with valid information Natio
30. 11 10 National Instruments Corporation Name BIPDACI BIPDACO EXTREFDACI EXTREFDACO 0 DMACHBB 2 0 DMACHAB lt 2 0 gt Register Map and Descriptions Description continued Bipolar DAC 1 This bit configures the range of DAC 1 in the analog output section If this bit is set DAC 1 is configured for bipolar operation of Vref to 4 Vrer In this mode data written to this DAC is interpreted in two s complement format If this bit is cleared DAC 1 is configured for unipolar operation of 0 V to Vref In this mode data written to DAC 1 is interpreted in straight binary format Bipolar DAC 0 This bit configures the range of DAC 0 in the analog output section If this bit is set then DAC 0 is configured for bipolar operation of Vref to Vref In this mode data written to this DAC is interpreted in two s complement format If this bit is cleared then DAC 0 is configured for unipolar operation of 0 V to Vref In this mode data written to DAC 0 is interpreted in straight binary format External Reference for DAC 1 This bit controls the reference selection for DAC 1 in the analog output section If this bit is set the reference used for DAC 1 is the external reference voltage from the I O connector If this bit is cleared the internal 10 is used for the DAC 1 reference External Reference for DAC 0 This bit controls the reference selection for DAC 0 in the analog output se
31. 2 1 Board Conn uration s era E 2 3 AT Bus Interface s eve iH else eee eA dit d ei dee 2 3 Base O Address Selection sinsir Sedan ce ie Ege cede ese dp Qe a ede 2 3 Interrupt and DMA Channel Selection eene 2 6 Analog Input Configuration dotis 2 6 Input MOde s e LES aoe aa Eee 2 7 DIFF Input Eight Channels cete odis de 2 7 RSE Input 16 Chelsea di ce 2 8 NRSE Input 16 Channels mens Mt dades 2 8 Input Polarity and Input Range 55 oia de eerie die 2 0 Considerations for Selecting Input 4444220222 2 9 Analog Output Configuration s eco edocti manne nass 2 10 Analog Output Reference Selection aiia e eret tin ib dias 2 10 Analog Output Polarity Selection cuero efe eles 2 10 Digita l UO Con aide ee redeo Ce Beda Rew dae te dades 2 10 Board and RTSI Clock Configuration sus 2 10 Hardware Installati n SRE en Untere opio be ufo oto it E 2 11 signal CONI CHONS 555 T osse tut e a adu 2 11 Signal Connec ton Descriptions teneo ore nd DE 2 14 Analog Input Signal Connections us 2 16 Types Ol EA aste t Air 2 17 Floating Signal Sources 2 17 Ground Referenced Signal Sources 2 17
32. 2 11 Analog Output Connections The external reference signal can be either a DC or an AC signal This reference signal is multiplied by the DAC code to generate the output voltage Digital I O Signal Connections The digital lines ADIO lt 0 3 gt are connected to digital I O port A The digital lines BDIO lt 0 3 gt are connected to digital I O port B DIG GND is the digital ground pin for both digital I O ports Ports A and B can be programmed individually to be inputs or outputs The following specifications and ratings apply to the digital I O lines Absolute maximum voltage input rating 5 5 V with respect to DIG GND Digital input specifications referenced to DIG GND Vin input logic high voltage 2 V minimum Vir input logic low voltage 0 8 V maximum input current load logic high input voltage 40 LA maximum IL input current load logic low input voltage 120 LA maximum National Instruments Corporation 2 25 AT MIO 16X User Manual Configuration and Installation Chapter 2 Digital output specifications referenced to DIG GND output logic high voltage 2 4 V minimum output logic low voltage 0 5 V maximum output source current logic high 2 6 mA maximum Io output sink current logic low24 mA maximum With these specifications each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads Figure 2 12 depicts signal connections for three typical digital I O applications
33. 2 18 ground referenced signal sources 2 18 to 2 19 recommended configurations for ground referenced and floating signal sources table 2 18 single ended connections floating signal RSE sources 2 22 general considerations 2 21 to 2 22 grounded signal NRSE sources 2 22 to 2 23 pin assignments I O connector 50 pin connector 2 12 B 1 68 pin connector 2 13 B 2 power connections I O connector 2 27 RTSI switch 5 27 to 5 28 signal descriptions 2 14 to 2 16 timing connections 2 27 to 2 34 data acquisition timing connections 2 27 to 2 30 general purpose connections 2 30 to 2 34 signals for 2 27 to 2 30 types of signal sources floating signal sources 2 17 ground referenced signal sources 2 17 warning against exceeding ratings 2 11 single analog input channel programming 5 10 single channel data acquisition sequence programming 5 5 to 5 6 single channel data acquisition timing 3 8 to 3 10 See also DAQ programming posttrigger data acquisition timing 3 9 pretrigger data acquisition timing 3 9 to 3 10 sample interval timer 3 8 to 3 9 specifications A 4 Single Conversion Register 4 39 single conversions programming flow chart 5 4 generating single conversions 5 5 reading single conversion result 5 5 using SCONVERT or EXTCONV signal 5 4 single ended connections floating signal RSE sources 2 22 general considerations 2 21 to 2 22 National Instruments Corporation Index grounded signal
34. 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to each cycle through the scan sequence programmed in the channel configuration register This mode is called interval channel scanning See the Multiple Channel Data Acquisition section earlier in this chapter AT MIO 16X User Manual 3 22 National Instruments Corporation Chapter 3 Theory of Operation The Am9513A 4 bit programmable frequency output channel is located at the I O connector FOUT pin Any of the five internal timebases and any of the counter SOURCE or GATE inputs can be selected as the frequency output source The frequency output channel divides the selected source by its 4 bit programmed value and makes the divided down signal available at the FOUT pin RTSI Bus Interface Circuitry The AT MIO 16X is interfaced to the National Instruments RTSI bus The RTSI bus has seven trigger lines and a system clock line National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC and share these signals A block diagram of the RTSI bus interface circuitry is shown in Figure 3 19 A2 A2 DRV RCV 10 MHz EN dE Oscillator RTSICLK Trigger Drivers Drivers TMRTRIG OUT5 RTSI Bus Connector RTSI SEL Internal DATA A4 A4 Data Bus RTSI DRV RCV Switch Figure 3 19 RTSI Bus Interface Circuitry Block Diagram The RTSICLK line can be used to source a 10 MHz signal across the RTSI bus or to rec
35. 3 Theory of Operation needed Counter 4 is concatenated with Counter 5 of the Am9513A to form a 32 bit counter The sample counter decrements its count each time the sample interval counter generates an A D conversion pulse and the sample counter stops the data acquisition process when it counts down to zero The sample counter can also be used to count conversions generated by external conversion signals The configuration memory register is set up to select the analog input channel and configuration before data acquisition is initiated for a single channel data acquisition sequence These settings remain constant during the entire data acquisition process therefore all A D conversions are performed on a single channel Single channel acquisition is enabled through a register in the AT MIO 16X register set The data acquisition process be initiated via software or by applying an active low pulse to the EXTTRIG input on the AT MIO 16X I O connector Figure 3 5 shows the timing of a typical single channel data acquisition sequence Trigger DAQPROG CONVERT i ee ee ee Sample CTR 9 X8X7TX6XSX4X3X2KLXWX_I DAQCMPLT LO S Loc cu us uw Bx Interrupt Te RAT REN DAQCLEAR ae Figure 3 5 Single Channel Posttrigger Data Acquisition Timing In this sequence the sample interval counter Counter 3 is programmed to generate conversion signals only under a certain gating signal such as the DAQPROG signal In addition t
36. 50 pin connector 16X board with 50 AT MIO 16X board with 50 pin connector connector 181610 01 01 AT MIO 16X 776578 11 AT MIO 16X board with 68 pin connector EY The board part number is printed on your board along the top edge on the component side You can identify which version of the AT MIO 16X board you have by looking up the part number in the preceding table In addition to the board each version of the AT MIO 16X kit contains the following components Kit Component Part Number AT MIO 16X User Manual 320640 01 NI DAQ software for DOS Windows LabWindows with manuals 776250 01 NI DAQ Software Reference Manual for DOS Windows Lab Windows 320498 01 NI DAQ Function Reference Manual for DOS Windows LabWindows 320499 01 If your kit is missing any of the components contact National Instruments Your AT MIO 16X is shipped with the NI DAQ software for DOS Windows LabWindows NI DAQ has a library of functions that can be called from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation digital I O counter timer SCXI RTSI and self calibration NI DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code NI DAQ comes with language interfaces for Professional BASIC Turbo
37. A D conversion result every time one becomes available Another method is to monitor the ADCFIFOHF flag and read in values only when the ADC FIFO is at least half full If the FIFO is half full a block of 256 values can be consecutively read in The advantage of this second method is that Status Register 1 needs to be read only once for every 256 values while the first method requires one status register to be read per ADC FIFO read To service the data acquisition operation perform the following sequence until the data acquisition has completed 1 Read Status Register 1 16 bit read 2 If the OVERRUN or OVERFLOW bits are set the data acquisition sequence has been halted because one of these error conditions has occurred Clear the A D circuitry by writing to DAQ Clear Register and determine the cause of the error OVERRUN and OVERFLOW are explained in step 3 of the Programming the Analog Input Circuitry section earlier in this chapter 3 If the ADCFIFOEF bit is set or the ADCFIFOHF bit read the ADC FIFO Register to obtain the result s Interrupts or DMA can also be used to service the data acquisition operation These topics are discussed later in this chapter Resetting the Hardware after a Data Acquisition Operation After a data acquisition operation terminates if no errors occurred and the sample count was less than or equal to 10000 hex the AT MIO 16X is left in the same state as it was at the beginning of the data acq
38. AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Status Register 2 Status Register 2 contains 1 bit of AT MIO 16X hardware status information for monitoring the status of the A D conversion Address Base address 1A hex Type Read only Word Size 1 bit Bit Map 15 14 13 12 11 10 9 amp MSB 7 6 3 4 3 2 1 0 LSB Bit Name Description 15 1 X Don t care bits 0 ADC BUSY ADC BUSY This bit indicates the status of the A D converter on the AT MIO 16X during a conversion or calibration process The A D converter on the AT MIO 16X can calibrate its internal circuitry on command by strobing the ADC Calibration Register If ADC BUSY is clear an ADC conversion or calibration operation is currently in progress If ADC_BUSY is set ADC conversion or calibration operation is in progress An ADC calibration cycle takes approximately 1 25 sec During this time the ADC is busy as reflected by ADC_BUSY status and cannot be used AT MIO 16X User Manual 4 22 National Instruments Corporation Chapter 4 Register Map and Descriptions Analog Input Register Group The two registers making up the Analog Input Register Group control the analog input circuitry and can be used to read the ADC FIFO Reading from the ADC FIFO Register location transfers data from the AT MIO 16X ADC FIFO buffer to the PC Writing to the CONFIGMEM Register location sets up channel configuration information for the analog input
39. Am9513A Counters 1 2 and 5 SOURCE signals for Counters 1 and 5 and the FOUT signal generated by the Am9513A Counters 1 2 and 5 of the Am9513A Counter Timer be used for general purpose applications such as pulse and square wave generation event counting pulse width time lapse and frequency measurements For these applications SOURCE and GATE signals can be directly applied to the counters from the I O connector The counters are programmed for various operations The Am9513A Counter Timer is described briefly in Chapter 3 Theory of Operation For detailed programming information consult Appendix C AMD Am9513A Data Sheet For detailed applications information consult the Am95 1 3A Am9513 System Timing Controller technical manual published by Advanced Micro Devices Inc Pulses and square waves can be produced by programming Counter 1 2 or 5 to generate a pulse signal at its OUT output pin or to toggle the OUT signal each time the counter reaches the terminal count For event counting one of the counters is programmed to count rising or falling edges applied to any of the Am9513A SOURCE inputs The counter value can then be read to determine the number of edges that have occurred Counter operation can be gated on and off during event counting Figure 2 17 shows connections for a typical event counting operation in which a switch is used to gate the counter on and off AT MIO 16X User Manual 2 30 National Instruments
40. Analog Output Register Group The two registers making up the Analog Output Register Group access the two analog output channels Data can be transferred to the DACS in one of three ways depending on the mode configuration in Command Register 4 according to Table 4 6 Data can be directly sent to the DACs from the local data bus buffered from the local bus by the DAC FIFOs or received serially from the AT DSP2200 across the RTSI bus There are two methods of updating the DACS immediate and posted In the immediate update mode data transferred to the DACS is not buffered and is immediately converted to the appropriate voltage at the output In the posted update mode data is converted to an output voltage only after a falling edge is detected on the TMRTRIG signal or the DAC Update Register is strobed In the immediate update mode and the serial mode the DAC FIFOs are not utilized In all other output modes the DAC FIFOs are used The output voltage generated from the digital code depends on the configuration unipolar or bipolar of the associated analog output channel This configuration is determined by control bits in the Command Register 2 Configuration bits in Command Register 2 determine if the digital code written to the DACS is in straight binary form or in a two s complement form Table 4 10 shows the output voltage versus digital code for a unipolar analog output configuration Table 4 11 shows the voltage versus digital code for a bip
41. COBTIBUEDUOFS stantis eret detail ii tud 2 18 Differential Connection Considerations DIFF Input Configuration 2 18 Differential Connections for Ground Referenced Signal Sources 2 18 Differential Connections for Nonreferenced or Floating Signal SOURCES UNS ME 2 19 National Instruments Corporation v AT MIO 16X User Manual Contents Single Ended Connection Considerations 2 21 Single Ended Connections for Floating Signal Sources RSE 2 22 Single Ended Connections for Grounded Signal Sources NRSE Configuration uisi etse tad es e ee 2 22 Common Mode Signal Rejection Considerations 2 23 Analog Output Signal Connections ss 2 24 Digital I O Signal Connections 2 25 Power 2 27 Timing Connections for Data Acquisition and Analog Output 2 27 Counter Signal Connections 2 30 Field Wiring COofstIUeratioris 4s eoa 2 34 Cabling Considerations for the AT MIO 16X with 50 Pin I O Connector 2 35 Cabling Considerations for the AT MIO 16X with 68 Pin I O Connector 2 36 Chapter 3 Theory of uns 3 1 Functional OVervie Woo bete obi te e
42. Command Register 1 4 5 to 4 7 Command Register 2 4 8 to 4 10 5 26 5 31 Command Register 3 4 11 to 4 15 Command Register 4 4 16 to 4 18 overview 4 4 register map 4 1 Status Register 1 4 19 to 4 21 Status Register 2 4 22 5 26 continuous channel scanning definition 5 7 programming 5 7 to 5 8 continuous scanning data acquisition timing 3 11 counter block diagram 3 21 counter signal connections See general purpose timing connections counter timer See Am9513A Counter Timer Register Group Am9513A System Timing Controller customer communication xiv D 1 cyclic waveform generation See DAC waveform circuitry and timing waveform generation programming CYCLICSTOP bit cyclic waveform generation 3 17 to 3 18 5 18 description 4 18 D D 15 0 bit ADC FIFO Register 4 24 Am9513A Data Register 4 53 DACO Register 4 32 DACI Register 4 33 DAC Clear Register clearing analog output circuitry 5 23 description 4 44 DMA operations 5 30 servicing update requests 5 26 DAC Event Strobe Register Group 4 41 to 4 44 AT MIO 16X User Manual Index DAC Clear Register 4 44 5 23 5 26 5 30 DAC Update Register 4 43 register map 4 2 TMRREQ Clear Register 4 42 5 23 5 26 5 30 5 31 DAC FIFO cyclic waveform generation 5 18 to 5 19 DAC waveform and circuitry timing 3 15 to 3 17 DMA operations 5 30 interrupt programming 5 8 programmed cycle waveform generation 5 19 to 5 21 programming analog output c
43. Connections This section describes input and output signal connections to the AT MIO 16X board via the AT MIO 16X I O connector This section also includes specifications and connection instructions for the signals given on the AT MIO 16X I O connector Warning Connections that exceed any of the maximum ratings of input or output signals on the AT MIO 16X can result in damage to AT MIO 16X board and to the PC Maximum input ratings for each signal are given in this chapter under the discussion of that signal National Instruments is not liable for any damages resulting from such signal connections National Instruments Corporation 2 11 AT MIO 16X User Manual Configuration and Installation Chapter 2 Figure 2 4 shows the pin assignments for the AT MIO 16X 50 pin I O connector AI GND ACHO ACHI ACH2 ACH3 ACH4 ACHS ACH6 ACH7 AI SENSE DACI OUT AO GND ADIOO ADIOI ADIO2 ADIO3 DIG GND 5 EXTSTROBE EXTGATE SOURCEI OUTI GATE2 SOURCES OUTS A o o o o mme jaja 5 le a a a jo 2 je u 2 a a Elo v ou to to r2 t ls j2j amp s s 5 js 2 e s e 8 E 9 S B 0 8 S S AI GND ACH8 ACH9 ACH10 ACHII ACHI2 14 15 DACO OUT EXTREF DIG GND BDIOO BDIOI BDIO2 BDIO3 5 SCANCLK EXTTRIG EXTCONV GATEI EXTTMRTRIG OUT2 GATES FOUT Figure 2 4 AT MIO 16X 50 Pin I O
44. FIFO Programmed Cyclic Waveform Generation One step beyond the continuous waveform generation is the programmed cyclic waveform generation This mode is also available only when the entire buffer fits within the DAC FIFO Figure 3 14 shows the operation of this mode DACFIFORT t 5 _ X 3 X 2 X 1 A 0 5 COUNTER 1 2 or 5 Figure 3 14 FIFO Programmed Cyclic Waveform Timing In this case one of the counters in the Am9513A Counter Timer is programmed to count the number of DAC FIFO Retransmit signals When the counter counts the appropriate number of occurrences it terminates the waveform sequence A bit is available in Status Register 1 to indicate termination of a waveform sequence FIFO Pulsed Waveform Generation Another step beyond cycle counting is pulsed waveform generation Again this mode is applicable only if the entire buffer fits within the DAC FIFO Figure 3 15 shows the operation of this mode and the resulting waveform DACFIFORT CRI JA TX 22 X A 2 CTR 1 Output L I CTR 2 Terminal Count Figure 3 15 FIFO Pulsed Waveform Generation Timing AT MIO 16X User Manual 3 18 National Instruments Corporation Chapter 3 Theory of Operation In the pulsed waveform application Counter 1 of the Am9513A is programmed to count the number of retransmit signals before terminating the sequence At this point Counter 2 serves as an interval timer waiting a programmed amount of
45. Sequences with Channel Scanning 5 7 Continuous Channel Scanning Data Acquisition 5 7 Interval Channel Scanning Data Acquisition eee 5 8 Data Acquisition Programming 5 10 Clearing the Analog Input Circuitry 5 10 Programming Single Analog Input Channel Configurations 5 10 Programming Multiple Analog Input Channel Configurations 5 10 Programming the Sample Interval Counter 5 11 Programming the Sample Counter s ss 5 12 Programming the Scan Interval Counter 5 14 Applymg TEIgget uote teen e e Pede Don va que ie ed de eR Uo gs 5 15 Servicing the Data Acquisition 5 15 Resetting the Hardware after a Data Acquisition 5 16 Resetting a Single Am9513A Counter Timer eese 5 16 Programming the Analog Output Circuitry eee 5 18 Cyclic Waveform Generation seu pues Sgen 5 18 Programmed Cycle Waveform Generation 5 19 Pulsed Cyclic Waveform Generation 5 21 Waveform Generation Programming Functions eeeeseseeeeeseeeseereeseesreseresressese 5 23 Clearing the Analog Output Circuitry ss 5 23 Selecting the I
46. Timer Register Group 4 52 to 4 55 Am9513A Command Register 4 54 Am9513A Data Register 4 53 Am9513A Status Register 4 55 programming 5 26 to 5 27 general considerations 5 26 to 5 27 resource allocation considerations 5 1 sample counters 5 12 to 5 14 sample interval counter 5 11 to 5 12 scan interval counter 5 14 to 5 15 update interval counter 5 23 to 5 24 waveform cycle counter 5 24 to 5 25 AT MIO 16X User Manual Index waveform cycle interval counter 5 25 to 5 26 register map 4 2 resetting after data acquisition operation 5 16 to 5 17 Am9513A System Timing Controller alarm registers and comparators C 11 block diagram C 2 bus transfer switching waveforms C 38 characteristics C 2 command descriptions C 29 to C 32 command summary C 30 connection diagram C 3 count control C 28 count source selection C 29 counter logic groups C 8 counter mode control options C 26 to C 29 counter mode descriptions C 14 to C 26 counter mode operating summary C 14 counter mode register C 11 counter mode register bit assignments C 27 counter output waveforms C 28 counter switching waveforms C 38 crystal input configuration C 40 data bus assignments C 7 data pointer register C 9 data pointer sequencing C 10 data port registers C 11 design hints C 39 detailed description C 8 to C 11 frequency scaler ratios C 13 GATE SRC configuration suggestion C 40 gating control C 13 gen
47. accomplished through writing to a register in the AT MIO 16X register set Single Read Timing The simplest method of acquiring data from the A D converter is to initiate a single conversion and then read the resulting value from the ADC FIFO buffer after the conversion is complete A single conversion can be generated three different ways applying an active low pulse to the pin of the I O connector generating a falling edge on the sample interval counter output pin Counter 3 of the Am9513A Counter Timer or strobing the appropriate register in the AT MIO 16X register set Any one of these operations will generate the timing shown in Figure 3 4 The ADC_BUSY signal status can be monitored through a status register on the AT MIO 16X National Instruments Corporation 3 7 AT MIO 16X User Manual Theory of Operation Chapter 3 CONVERT ADC BUSY FIFO LD Figure 3 4 ADC Conversion Timing When the ADC value is shifted into the ADC FIFO buffer by FIFO LD a signal is generated that indicates valid data is available to be read Single conversion timing of this type is appropriate for reading channel data on an ad hoc basis However if a sequence of conversions is needed this method is not very reliable because it relies on the software to generate the conversions in the case of the strobe register If finely timed conversions are desired that require triggering and gating then it is necessary to program the board to a
48. are low level less than 1 V e Leads connecting the signals to the AT MIO 16X are greater than 10 ft e Any of the input signals require a separate ground reference point or return signal signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also permit input signals to float within the common mode limits of the PGIA Differential Connections for Ground Referenced Signal Sources Figure 2 7 shows how to connect a ground referenced signal source to an AT MIO 16X board configured in the DIFF input mode The AT MIO 16X analog input circuitry must be AT MIO 16X User Manual 2 18 National Instruments Corporation Chapter 2 Configuration and Installation configured for DIFF input to make these types of connections Configuration instructions are included in Chapter 4 Register Map and Descriptions Ground Referenced Signal Source Measured Common Voltage Mode Noise Ground Potential and so on Input Multiplexers Connector AT MIO 16X Board in the DIFF Input Configuration Figure 2 7 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT MIO 16X ground shown as Vom in Figure 2 7 Differential Connections fo
49. be I O mapped accesses within the I O space of the computer Locations are either written to or read from as bytes or words Each register in the register set is mapped to a certain offset from the base address selection of the board as read or write and as a word or byte location as defined by the decode circuitry Base I O Address Selection The AT MIO 16X is configured at the factory to a base I O address of 220 hex This base address setting is suitable for most systems However if your system has other hardware at this base I O address you must change either the AT MIO 16X base address DIP switch or the other hardware base address to avoid a conflict Figure 2 3 shows a graphical representation of the base address selection DIP switch and also shows how to reconfigure the selected base address National Instruments Corporation 2 3 AT MIO 16X User Manual Configuration and Installation Chapter 2 l1 X 03 5 Switch up for 1 Switch down for 0 o o wv lt lt Tl A Switches Set to Base I O Address of Hex 000 T 2 3 M 5 Switch up for 1 N 7 Switch down for 0 F F o t lt lt lt lt Switches Set to Base I O Address of Hex 220 Factory Setting Figure 2 3 Example Base I O Address Switch Settings The base address DIP switch is arranged so that a logical 1 or true state for the associated address selection bit is selected by pushing the toggle switch up or toward the top of the b
50. can be used to count buffer cycles in this mode If Counter 5 is being used for the update signal then only Counters 1 and 2 are available for cycle counting Once the cycle counter reaches the end of its count DAC updating is halted irrespective of the update signal Pulsed Cyclic Waveform Generation An extension of the programmed cycle mode is the pulsed cyclic waveform generation mode in which a programmed number of cycles is generated between a programmed cycle interval The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter National Instruments Corporation 5 21 AT MIO 16X User Manual Programming Clear the analog output circuitry including the DAC FIFO Internal update Set the A4RCV bit in Clear the A4RCV Command Register 2 bit in Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter Program the cycle interval counter Set the waveform generation mode Enable updating Service update requests Figure 5 9 Pulsed Cyclic Waveform Programming Chapter 5 AT MIO 16X User Manual 5 22 National Instruments Corporation Chapter 5 Programming In this mode Counter 1 counts the programmed number of cycles before terminating the sequence Counter 2 then begins counting the time between cycles the cycle interval then restarts the s
51. can be used to measure the input signal Table 2 4 shows the overall input range and precision according to the input range configuration and gain used Table 2 4 Actual Range and Measurement Precision Versus Input Range Selection and Gain Range Configuration Actual Input Range 0 to 10 V 0 to 10 0 V 152 59 uV 0 to 45 0 V 76 29 UV 0 to 2 0 V 30 52 u V 0to 1 0 V 15 26 uV 0 to 40 5 V 7 63 UV 0 to 0 2 V 3 05 uV 0 to 100 0 mV 1 53 10 to 10 V 10 0 to 10 0 V 305 18 LV 5 0 to 45 0 V 152 59 uV 2 0 to 42 0 V 61 04 1 0 to 1 0 V 30 52 uV 0 5 to 40 5 V 15 26 0 2 to 40 2 V 6 10 UV 100 0 to 100 0 mV 3 05 UV The value of 1 LSB of the 16 bit ADC that is the voltage increment corresponding to a change of 1 count in the ADC 16 bit count Note See Appendix A Specifications for absolute maximum ratings National Instruments Corporation 2 9 AT MIO 16X User Manual Configuration and Installation Chapter 2 Analog Output Configuration The AT MIO 16X supplies two channels of analog output voltage at the I O connector The analog output circuitry is configurable through programming of a register in the board register set The reference and range for the analog output circuitry can be selected through software The reference can be either internal or external whereas the range can be either bipolar or unipolar Analog Output Reference Selection Each DAC can be connected to the AT MIO 16X internal referen
52. channel SPDT relay module SCXI 1161 8 channel Power relay module SCXI 1162 32 channel isolated digital input module SCXI 1163 32 channel isolated digital output module SCXI 1180 feedthrough panel SCXI 1181 breadboard SCXI signal conditioning chassis SCXI 1000 4 slot chassis SCXI 1001 12 slot chassis 50 pin AMUX 64T analog multiplexer board with 0 2 m ribbon cable for cascading 50 pin AMUX 64Ts with 0 5 m ribbon cable for cascading 50 pin AMUX 64Ts with 1 0 m ribbon cable for cascading 50 pin AMUX 64Ts with 2 0 m 50 pin ribbon cable for cascading 50 pin AMUX 64Ts without cable National Instruments Corporation 1 7 776784 01 776784 02 776784 05 776784 10 776164 90 776249 02 776249 03 776249 04 776249 05 776574 471 776574 472 776574 475 776574 470 776572 00 776572 20 776572 21 776572 40 776572 60 776572 61 776572 62 776572 63 776572 80 776572 81 776570 0 776571 0 776366 02 776366 05 776336 10 776366 20 776366 90 continues AT MIO 16X User Manual Introduction Equipment Part Number SC 2050 cable adapter board for signal conditioning without cable use with SH6850 cable assembly SC 2060 optically isolated digital input board with 26 conductor cable 0 2 0 4m SC 2061 optically isolated digital output board with 26 conductor cable 0 2m 0 4m SC 2062 electromechanical relay digital control board with 26 conductor cable 0 2m 0 4m SC 2070 general purpose termination breadbo
53. configures the DACS to buffer values written to them and update the output voltage only after a trigger signal This trigger signal can come in the form of an internal counter pulse from Counters 1 2 3 or 5 of the Am9513A Counter Timer it can be supplied from the EXTTMRTRIG signal at the I O connector or it can be obtained by accessing a register in the AT MIO 16X register set In the posted update mode requests for writes to the DAC are generated from the TMRREQ signal and can be acknowledged in one of three ways either polled I O through monitoring the signal in Status Register 1 interrupts or All three response mechanisms will have a delay associated with them in how fast they can respond to the requesting signal DMA will have the fastest response followed by polled I O and finally interrupts The advantage of using interrupts is that the CPU is not solely dedicated to monitoring Status Register 1 and can simultaneously perform other tasks If writes generated from these requests updated the DAC immediately there could be significant jitter in the resulting output waveform so values are written to a buffer where they are updated later with a precisely timed update signal Figure 3 11 depicts the timing for the posted DAC update mode Update Trigger LI L L TMRREQ DAC Write LXI LYT LZ DAC Output Y Figure 3 11 Posted DAC Update Timing In Figure 3 11 the update trigger signal serves to updat
54. down and rolls over In many counter applications the counter reloads from an internal register when it reaches TC In TC pulse output mode the counter generates a pulse during the cycle that it reaches TC and reloads In TC toggle output mode the counter output changes state after it reaches TC and reloads In addition the counters can be configured for positive logic output or negative inverted logic output for a total of four possible output signals generated for one timing mode The GATE and OUT pins for Counters 1 2 and 5 and SOURCE pins for Counters 1 and 5 of the onboard Am9513A are located on the AT MIO 16X I O connector A falling edge signal on the EXTTRIG pin of the I O connector or writing to the STARTDAQ register during a data acquisition sequence sets the flip flop output signal connected to the GATEA input of the Am9513A and can be used as an additional gate input This mode is also used in the pretrigger data acquisition mode The flip flop output connected to GATEA is cleared when the sample counter reaches TC when an overflow or overrun occurs or when the DAQ Clear Register is written to An overrun is defined as an error generated when the ADC cannot keep up with its programmed conversion speed The Am9513A SOURCES pin is connected to the AT MIO 16X RTSI switch which means that a signal from RTSI trigger bus be used as a counting source for the Am95134A counters The Am9513A OUTI OUT2 OUT3 EXTCONV and O
55. for selecting the analog input channel routed to the ADC In single ended mode only one analog input channel is selected In differential mode two analog input channels are selected The following table shows the mapping of analog input channels in the different input configurations Selected Analog Input Channels CHANSEL lt 3 0 gt Single Ended Differential 0 and 8 1 and 9 2 and 10 3 and 11 4 and 12 5 and 13 6 and 14 7 and 15 0 and 8 1 and 9 2 and 10 3 and 11 4 and 12 5 and 13 6 and 14 7 and 15 0 1 2 3 4 5 6 7 8 9 5 3 CH GAIN 2 0 Channel Gain Select These three bits control the gain setting of National Instruments Corporation 4 27 the input PGIA for the selected channel The following gains can be selected on the AT MIO 16X AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Bit Name Description continued 2 CHAN LAST Channel Last This bit should be set in the last entry of the scan sequence loaded into the channel configuration memory More than one occurrence of the CHAN LAST bit is possible in the configuration memory list for the interval scanning mode For example there can be multiple scan sequences in one memory list 1 CHAN GHOST Channel Ghost This bit is used to synchronize conversions for multiple rate channel scanning When this bit is set in any channel configuration value the conversion occurs on the selected channel but the value 1s not saved
56. hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 EISA DMACHBB2 DMACHBBI DMACHBBO DMACHAB2 DMACHABI DMACHABO LSB Bit Name Description 15 AARCV RTSI A4 Receive This bit controls the signal source for the TMRTRIG Timer Trigger signal The TMRTRIG signal updates the DACs in delayed update mode If A4RCV is set pin A4 of the RTSI switch drives the TMRTRIG signal If A4RCV is cleared the TMRTRIG signal is driven by the EXTTMRTRG signal from the I O connector 14 A4DRV RTSI 4 Drive This bit controls the driver that allows the OUTS signal to drive pin A4 of the RTSI switch If A4DRV is set pin A4 of the RTSI switch is driven by OUTS If A4DRV is cleared pin A4 is not driven by OUTS and it can be driven by a signal on the RTSI bus 13 A2RCV RTSI A2 Receive This bit controls the driver that allows the signal to be driven from pin A2 of the RTSI switch If A2RCYV is set pin A2 of the RTSI switch drives the GATEI signal In this case GATEI may not be driven by a signal at the I O connector 12 A2DRV RTSI A2 Drive This bit controls the driver that allows the OUT2 signal to drive pin A2 of the RTSI switch If A2DRV is set pin A2 of the switch is driven by OUT2 If A2DRV is cleared pin A2 is not driven by OUT2 and it can be driven by a signal on the RTSI bus AT MIO 16X User Manual 4 8 National Instruments Corporation Chapter 4 Bit
57. in the ADC FIFO In addition if the sample counter is programmed to count samples from Source 4 conversions with the CHAN GHOST bit set are not counted When the CHAN GHOST bit is clear conversions occur normally and are saved in the ADC FIFO 0 CHAN DSP Channel DSP This bit is used to flag channel data that is to be serially sent over the RTSI bus to the AT DSP2200 If the CHAN DSP bit is set the associated channel conversion data is sent over the RTSI bus If CHAN DSP is clear channel conversion data is not sent The CHAN_DSP bit has no bearing on whether or not the channel conversion data is stored in the ADC FIFO That is controlled by the GHOST bit Table 4 9 Input Configuration Input Mode BitMap BitMap o Effet PGIA PGIA DIFF 0 0 Channels 0 to 7 Channels 8 to 15 CHAN 7 CHAN_SE CHAN AIS xx fo 1 o oos ET ES 1 1 oos arse __ Offset Calibration 0 AI GND AI GND Gain Calibration Internal 5 Vref AI GND Note X indicates a don t care bit Writing to the channel configuration memory must be preceded with a strobe to the CONFIGMEMCLR Register After the channel configuration memory is set up the first value must be preloaded by accessing the CONFIGMEMLD Register Writing to the CONFIGMEM Register following a CONFIGMEMCLR automatically sequences into the memory list for multiple channel configuration values Writing can continue until the end of the channel
58. more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax ___ Phone ___ Computer brand Model Processor Operating system Speed Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps will reproduce the problem AT MIO 16X Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products e AT MIO 16X Revision Level e Base I O Address of AT MIO 16X Factory Setting hex 0220 e DMA Channels of AT MIO 16X Factory Setting 6 and 7 e Interrupt Level of AT MIO 16X Factory Setting 10 e Input Configuration DIFF RSE or NRSE e NI DAQ or La
59. of A D channels and configuration settings called the scan sequence is programmed into the channel configuration memory There are two types of multiple A D conversions with channel scanning continuous channel scanning and interval channel scanning Continuous channel scanning cycles through the scan sequence in the channel configuration memory and repeats the scan sequence until the sample counter terminates the data acquisition There is no delay between the cycles of the scan sequence Continuous channel scanning can be thought of as a round robin approach to scanning multiple channels Interval channel scanning gives each scan sequence a programmed time interval called a scan interval Each cycle of the scan sequence begins at the time interval determined by the scan interval If the sample interval counter is programmed for the minimum time required to complete an A D conversion interval channel scanning can be thought of as a pseudo simultaneous scanning of multiple channels that is all channels in the scan sequence are read as quickly as possible at the beginning of each scan interval Continuous Channel Scanning Data Acquisition Use the programming steps listed in Figure 5 4 to program continuous scanning of multiple A D conversions for posttrigger and pretrigger modes as well as internal and external timing The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions sectio
60. of the analog output circuitry AT MIO 16X User Manual 3 12 National Instruments Corporation Chapter 3 Theory of Operation REF Selection 5 VINT REF From Gain DACI DACIWR DACI OUT e amp I O Connector DACO OUT DACOWR EXTREF Internal 5 V INT REF From Gain DACO REF Selection Figure 3 9 Analog Output Circuitry Block Diagram Analog Output Circuitry Each analog output channel contains a 16 bit DAC reference selection switches unipolar bipolar output selection switches and output data coding circuitry The DAC in each analog output channel generates a voltage proportional to the input voltage reference Vref multiplied by the digital code loaded into the DAC Each DAC can be loaded with a 16 bit digital code by writing to registers on the AT MIO 16X board The output voltage is available on the AT MIO 16X I O connector DACO OUT and DACI OUT pins The analog output of the DACs is updated to reflect the loaded 16 bit digital code in one of the following three ways e Immediately when the 16 bit code is written to the DACs in immediate update mode e When an active low pulse is detected on the TMRTRIG signal in posted update mode e When the Update Register is strobed in posted update mode National Instruments Corporation 3 13 AT MIO 16X User Manual Theory of Operation Chapter 3 Analog Output Configuration The DAC output op amps can be configured through one
61. of the AT MIO 16X registers to generate either a unipolar voltage output or a bipolar voltage output range A unipolar output has an output voltage range of 0 to Vref 1 LSB V and accepts straight binary input values bipolar output has an output voltage range of Vref to Vref 1 LSB V and accepts two s complement input values One LSB is the voltage increment corresponding to an LSB change in the digital code word For unipolar output 1 LSB Vref 65 536 For bipolar output 1 LSB Vref 32 768 The voltage reference source for each DAC is selectable through one of the AT MIO 16X registers and can be supplied either externally at the EXTREF input or internally The external reference can be either a DC or an AC signal If an AC reference is applied the analog output channel acts as a signal attenuator and the AC signal appears at the output attenuated by the digital code divided by 65 536 for unipolar output or 32 768 for bipolar output The internal reference is a 5 V reference multiplied by 2 Using the internal reference supplies an output voltage range of 0 to 9 999847 V in steps of 152 6 for unipolar output and an output voltage range of 10 to 49 999695 V in steps of 305 2 for bipolar output Gain calibration for the DACs applies only to the internal reference not the external reference Offset calibration can be applied to both references Analog Output Calibration Output voltage accuracy is assured through the use of
62. on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources Signals generated at the OUT output are referenced to the signal at the SOURCE input or to one of the Am9513A internally generated clock signals Figure 2 19 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 300 nsec after the source signal rising or falling edge Field Wiring Considerations Accuracy of measurements made with the AT MIO 16X can be seriously affected by environmental noise if proper considerations are not taken into account when running signal wires between signal sources and the AT MIO 16X board The following recommendations apply mainly to analog input signal routing to AT MIO 16X board although they are applicable for signal routing in general You can minimize noise pickup and maximize measurement accuracy by doing the following e Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect analog input signals to the AT MIO 16X With this type of wire the signals attached to the and CH inputs are twisted together and then covered with a shield This shield is then connected only at one point to the signal source ground This kind of connection 15 required for signals traveling through areas with large magnetic fields or high electromagnetic interf
63. own offsets To calibrate this offset the routine grounds the inputs of the PGIA and adjusts CALDAC2 and CALDAC3 until the offset is within a small fraction of an LSB The postgain offset is always calibrated immediately after the pregain offset is calibrated If the three offset DACs are adjusted in this way there is no significant residual offset error and reading a grounded channel returns on average less than 0 5 LSB regardless of gain setting AT MIO 16X User Manual 6 6 National Instruments Corporation Chapter 6 Calibration Procedures the stages up to and including the input of the ADC contribute to the gain error of the analog input circuitry With the set to a gain of 1 the gain of the analog input circuitry is ideally 1 The gain error is the deviation of the gain from 1 and appears as a multiplication of the input voltage being measured To eliminate this error source the routine measures the internal voltage reference and adjusts CALDACO and CALDACI until the measured voltage is equal to the value of the reference as stored in the onboard EEPROM Once the board is calibrated at a gain of 1 there is only a small residual gain error 40 0226 maximum at the other gains The gain error is always calibrated immediately after the offsets are calibrated Analog Output Calibration To null out error sources that affect the accuracy of the output voltages generated the output calibration routine calibrates the analo
64. posttrigger sequences the sample counter starts counting after receipt of the first trigger while in the pretrigger acquisition mode the sample counter does not start counting until a second trigger condition occurs The data acquisition operation is initiated by writing to the DAQ Start Register or by a falling edge on the EXTTRIG signal Programming multiple A D conversions on a single channel requires the following programming steps for posttrigger and pretrigger modes as well as internal and external timing The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter Clear the A D circuitry Program a single analog input channel gain mode and range Program the sample interval counter Program the sample counter Enable a single channel data acquisition operation Apply a trigger Service the data acquisition operation Figure 5 3 Single Channel Data Acquisition Programming AT MIO 16X User Manual 5 6 National Instruments Corporation Chapter 5 Programming Programming Data Acquisition Sequences with Channel Scanning The preceding data acquisition programming sequence programs the AT MIO 16X for multiple A D conversions on a single input channel The AT MIO 16X can also be programmed for scanning multiple analog input channels with different gain mode and range settings during the data acquisition operation The sequence
65. recommended configurations for ground referenced and floating signal sources table 2 18 single ended connections 2 22 FOUT signal Am9513A programmable frequency output channel 3 23 clock source 2 34 definition 2 15 B 5 RTSI switch connections 3 24 timing signal source 5 26 frequency measurement 2 31 to 2 32 functional overview See theory of operation G gain error analog input circuitry A 2 analog output circuitry 6 GATE OUT and SOURCE timing signals counter signal connections 2 30 to 2 34 RTSI bus interface circuitry 3 24 timing I O circuitry 3 21 to 3 22 National Instruments Corporation signal 2 15 5 28 4 GATE2 signal 2 15 4 GATE2SEL bit 4 18 5 23 GATES signal 2 15 B 5 General Event Strobe Register Group 4 45 to 4 51 Calibration DAC 0 Load Register 4 50 Calibration DAC 1 Load Register 4 51 DMA Channel Clear Register 4 46 DMATCA Clear Register 4 47 5 23 5 30 5 31 DMATCB Clear Register 4 48 5 23 5 30 5 31 External Strobe Register 4 49 register map 4 2 general purpose timing connections 2 30 to 2 34 event counting application with external switch gating illustration 2 31 frequency measurement 2 31 to 2 32 GATE SOURCE and OUT signals 2 30 to 2 34 input and output ratings 2 32 to 2 33 time lapse measurement 2 31 ground referenced signal sources definition and requirements 2 17 differential connections 2 18 to 2 19 recommended configurations fo
66. sec 1 LSB maximum over temperature 0 75 LSB typical 1 LSB maximum no missing codes over temperature 0 5 LSB typical 10 V or 0 to 10 V software selectable Each input to the instrumentation amplifier should remain within 11 V of AIGND at any gain or range 15 V power off 25 V power on 105 dB all gains DC to 60 Hz DC to 255 kHz all gains 1 nA 100 in parallel with 100 pF 1 2 5 10 20 50 and 100 software selectable 3 uV maximum 2 2 mV maximum 5 uV C 76 uV maximum 102 mV maximum 120 uV C 1 AT MIO 16X User Manual Specifications Appendix A Gain error relative to reference After calibration 0 00305 30 5 ppm maximum Before calibration any gain 0 215 2 150 ppm maximum Gain 1 0 02 200 ppm maximum with gain error adjusted to 0 at gain 1 Temperature coefficient any gain 8 ppm C System noise including quantization noise Bipolar 10 V range 0 6 LSB rms for gains 1 to 10 0 7 LSB rms for gain 20 1 1 LSB rms for gain 50 2 0 LSB rms for gain 100 Unipolar 0 to 10 V range 0 8 LSB rms for gains 1 to 10 1 1 LSB rms for gain 20 2 0 LSB rms for gain 50 3 8 LSB rms for gain 100 Crosstalk other than from settling 70 dB DC to 100 kHz Onboard reference 5 000 V 2 mV Temperature coefficient 2 ppm C maximum 10 uV C maximum Long term stability 15 ppm 4 1000 hours 75 uV 41000 hours Explanation of Analog Input Specifications Linear Errors
67. section This information is necessary for single conversions as well as single and multiple channel data acquisition sequences Bit descriptions of the two registers making up the Analog Input Register Group are given on the following pages National Instruments Corporation 4 23 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 ADC FIFO Register Reading the ADC FIFO Register returns the oldest ADC conversion value stored in the ADC FIFO Whenever the ADC FIFO is read the value read is removed from the ADC FIFO thereby leaving space for another ADC conversion value to be stored Values are shifted into the ADC FIFO whenever an ADC conversion is complete The ADC FIFO is emptied when all values it contains are read Status Register 1 should be read to determine the FIFO state before the ADC FIFO Register is read If the ADC FIFO contains one or more ADC conversion values ADCFIFOEF bit is set in Status Register 1 and the ADC FIFO Register can be read to retrieve a value If the ADCFIFOEF bit is cleared the ADC FIFO is empty in which case reading the ADC FIFO Register returns meaningless information If the ADCFIFOHF flag is clear in Status Register 1 the ADC FIFO is at least half full with conversion data and 256 FIFO values can be read without checking the ADCFIFOEF in Status Register 1 The values returned by reading the ADC FIFO Register are available in two different binary formats straight binary which
68. signal TMRTRIG from pin A4 of the RTSI switch set the A4RCV bit in Command Register 2 Otherwise clear the A4RCV bit Note If both the A4DRV and 4 bits are set the TMRTRIG signal is driven by the signal OUTS Programming the RTSI Switch The RTSI switch is a 7x7 crossbar switch which can be programmed to connect any of the signals on the A side to any of the signals on the B side and vice versa To do this a 56 bit pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register and then writing to the RTSI Switch Strobe Register to load the pattern into the RTSI switch The 56 bit pattern is made up of two 28 bit patterns one for side A and one for side B of the RTSI switch The low order 28 bits select the signal sources for the B side pins The high order 28 bits select the signal sources for the A side pins Each of the 28 bit patterns are made up of seven 4 bit fields one for each pin The 4 bit field selects the signal source and the output enable for the pin Figure 5 10 shows the bit map of the RTSI switch 56 bit pattern AT MIO 16X User Manual 5 28 National Instruments Corporation Chapter 5 Programming Bit Number 55 51 47 43 39 35 31 27 23 19 15 11 7 3 0 BOSS SNC Oooo SB LS M B AO Control 30 29 28 Bit Number 31 Figure 5 10 RTSI Switch Control Pattern In Figure 5 10 the fields labeled A6 through 0 and B6 through BO are the 4 bit control fields for eac
69. that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WIL
70. the input signal can be removed from the conversion channel This signal is available at the I O connector and can be used to control external multiplexers for higher channel count applications The rising edge of SCANCLK signals when the ADC has acquired the input signal and no longer needs to have it held available In the scanning acquisition modes this signal pulses for every conversion Interval Scanning Data Acquisition Timing Interval scanning assigns a time between the beginning of consecutive scan sequences If only one scan sequence is in the configuration memory list the circuitry stops at the end of the list and waits the necessary interval time before starting the scan sequence again If multiple scan sequences are in the configuration memory list the circuitry stops at the end of each scan sequence and waits the necessary time interval before starting the next scan sequence When the end of the scan list is reached the circuitry stops and waits the necessary time interval before sequencing through the channel information list again Figure 3 8 shows an example of the interval scanning sequence timing National Instruments Corporation 3 11 AT MIO 16X User Manual Theory of Operation Chapter 3 Trigger DAQPROG CONVERT Channel COUNTER2 SCANCLK DAQCMPIT Interrupt DAQCLEAR Figure 3 8 Interval Scanning Posttrigger Data Acquisition Timing In interval scanning applications the first sample does not occur u
71. the next There is no maximum pulse width limitation EXTCONV should be high for at least one conversion period before going low The EXTCONV signal is one HCT load and is pulled up to 5 V through a 10 kQ resistor EXTCONV is also driven by the output of Counter 3 of the Am9513A Counter Timer This counter is also referred to as the sample interval counter The output of Counter 3 and the RTSI connection to EXTCONV must be disabled to a high impedance state if A D conversions are to be controlled by pulses applied to the EXTCONV pin If Counter 3 is used to control A D conversions its output signal can be monitored at the EXTCONV pin A D conversions generated by either the EXTCONV signal or the sample interval counter are inhibited outside of a data acquisition sequence and when gated by either the hardware EXTGATE signal or software command register gate Note EXTCONV and the output of Counter 3 of the Am9513A are physically connected together on the AT MIO 16X If Counter 3 is used in an application the EXTCONV signal must be left undriven Conversely if EXTCONV is used in an application Counter 3 must be disabled EXTTRIG Signal Any data acquisition sequence can be initiated by an external trigger applied to the EXTTRIG pin Applying a falling edge to the EXTTRIG pin starts the sample and sample interval counters thereby initiating a data acquisition sequence Figure 2 15 shows the timing requirements for the EXTTRIG s
72. transfers and you can use them The AT MIO 16X does not use and cannot be configured to use the 8 bit DMA Channels 0 through 3 on the PC I O channel for 16 bit transfers Analog Input Configuration The analog input section of the AT MIO 16X is software configurable You can select different analog input configurations by programming the appropriate register in the AT MIO 16X register set The following paragraphs describe in detail each of the analog input categories AT MIO 16X User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation Input Mode The AT MIO 16X offers three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations use up to 16 channels The DIFF input configuration uses up to eight channels Input modes are programmed on a per channel basis for multimode scanning For example the circuitry can be configured to effectively scan 12 channels four differentially configured channels and eight single ended channels The input configurations are described in Table 2 3 Table 2 3 Available Input Configurations for the AT MIO 16X DIFF Differential configuration has eight differential inputs with the negative input of the PGIA tied to the multiplexer output of Channels 8 through 15 RSE Referenced single ended configuration has 16 single ended inputs with the negative input
73. update interval Requests can be programmed to be generated whenever the DAC FIFO is not full or only when the FIFO is less than half full If the half full method is used 1 024 values can be written at once without reading the DAC FIFO flags after each subsequent transfer to keep from overfilling the FIFO This mode results in a significant performance increase in polled I O or interrupt servicing of the DACs The waveform circuitry is configured through mode bits in Command Register 4 to perform one or two DAC writes per update pulse If two DAC channels are being used and single update mode DACMODEB3 is clear is enabled only one value is read from the DAC FIFO and written to the appropriate DAC channel per update pulse The result is that the channel updates are out of phase with respect to each other If the dual update mode is used DACMODEB3 is set the circuitry will read up to two values from the DAC FIFO and write them to the appropriate DAC channels If the dual update mode is enabled and only one DAC is used then the circuitry will perform only one FIFO read and DAC write per update pulse Notice that if two channels are used the DACO value must be written to the DAC FIFO before the DACI value Cyclic Waveform Generation The simplest mode of waveform generation is the cyclic mode in which an internal or external timing signal is used to update the DACs In this case DAC updating begins when the timing signal starts and ends when
74. use the internal timebase without driving the RTSI bus timebase signal Hardware Installation You can install the AT MIO 16X in any available 16 bit expansion slot in your AT Series computer However to achieve best noise performance you should leave as much room as possible between the AT MIO 16X and other boards and hardware The AT MIO 16X does not work if installed in an 8 bit expansion slot PC Series After you have made any necessary changes verified and recorded the switches and jumper settings a form is included for this purpose in Appendix D Customer Communication you are ready to install the AT MIO 16X The following are general installation instructions but consult your PC user manual or technical reference manual for specific instructions and warnings 1 Turn off your computer Remove the top cover or access port to the I O channel Remove the expansion slot cover on the back panel of the computer Tec o e Insert the AT MIO 16X into a 16 bit slot Do not force the board into place Verify that there are no extended components on the circuit board of the computer that may touch or be in the way of any part of the AT MIO 16X 5 Attach a RTSI cable to the RTSI connectors to connect AT Series boards to each other 6 Screw the AT MIO 16X mounting bracket to the back panel rail of the computer 7 Check the installation 8 Replace the cover The AT MIO 16X board is installed and ready for operation Signal
75. 0 33F 340 35F 360 37F 380 39F 3A0 3BF 3DF 3E0 3FF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 oOooooco rr OOCOrRR Rr OOrFFCOF OF CF OF OF CFO Interrupt and DMA Channel Selection The base I O address selection is the only resource on the AT MIO 16X board that must be set manually before the board is placed into the PC The interrupt level and DMA channels used by the AT MIO 16X are selected via registers in the AT MIO 16X register set The AT MIO 16X powers up with all interrupt and DMA requests disabled To use the interrupt capability of the AT MIO 16X an interrupt level must first be selected via register programming then the specific interrupt mode must be enabled The same method holds for DMA channel selection To use the DMA capability of the board one or two DMA channels must be selected through the appropriate register then the specific DMA mode must be enabled It is possible to have interrupt and DMA resources concurrently enabled The interrupt lines supported by the AT MIO 16X hardware are IRQ3 IRQ4 5 IRQ7 10 IRQ11 IRQ12 and IRQ15 The DMA channels supported are Channels 0 through 3 and Channels 5 through 7 If you use the AT MIO 16X in an AT type computer you should only use DMA Channels 5 through 7 because these are the only 16 bit channels available If you use the board in an EISA computer all channels are capable of 16 bit
76. 0 Load Register Accessing the Calibration DAC 0 Load Register loads the serial data previously shifted into one of the eight selected 8 bit calibration DACs Address Base address hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Updates a selected calibration DAC AT MIO 16X User Manual 4 50 National Instruments Corporation Chapter 4 Calibration DAC 1 Load Register Register Map and Descriptions Accessing the Calibration DAC 1 Load Register loads the serial data shifted into the 12 bit ADC pregain offset calibration DACs Address Type Word Size Bit Map Strobe Effect Base address 1A hex Write only 8 bit Not applicable no bits used Updates the ADC pregain offset calibration DAC National Instruments Corporation 4 51 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Am9513A Counter Timer Register Group The three registers making up the Am9513A Counter Timer Register Group access the onboard counter timer Am9513A controls onboard data acquisition timing as well as general purpose timing for the user The Am9513A registers described here are the Am9513A Data Register the Am9513A Command Register and the Am95134A Status Register The Am9513A contains 18 additional internal registers These internal registers are accessed through the Am9513A Data Register A detailed register description of all Am9513A registers is includ
77. 2 14 B 3 digital I O circuitry 3 19 to 3 20 BDIO lt 3 0 gt bit 4 57 4 58 5 26 BIPDACO bit 4 9 BIPDACI bit 4 9 bits A2DRV 4 8 5 28 A2RCV 4 8 5 28 AADRV 4 8 5 28 AARCV 4 8 5 26 5 28 AT MIO 16X User Manual Index A6 through 5 29 ADC_BUSY 4 22 ADCDSP 4 11 ADCFIFOEF 4 20 5 5 5 16 5 30 5 31 ADCFIFOHF 4 19 5 16 5 30 5 31 ADCFIFOREQ 4 18 ADCREQ 4 13 ADIO lt 3 0 gt 4 57 4 58 5 26 B6 through BO bits 5 29 BDIO lt 3 0 gt 4 57 4 58 5 26 BIPDACO 4 9 BIPDACI 4 9 BYTEPTR 4 55 lt 7 0 gt 4 54 CFGMEMEF 4 21 CHAN AIS 4 26 CHAN BIP 4 26 CHAN CAL 4 26 CHAN DSP 4 28 CHAN GHOST 4 28 CHAN LAST 4 28 5 11 CHAN SE 4 26 CHANSEL 3 0 4 27 CH_GAIN lt 2 0 gt 4 27 CLKMODEB lt 1 0 gt 4 16 CNT32 16 4 6 5 13 5 14 CYCLICSTOP 3 17 to 3 18 4 18 5 18 D lt 15 0 gt 4 24 4 32 4 33 4 53 DACODSP 4 17 DACOREQ 4 14 DACIDSP 4 17 DACIREQ 4 14 DACCMPLINT 4 12 DACCOMP 4 21 5 23 5 26 DACFIFOEF 4 21 5 26 DACFIFOFF 4 21 5 30 DACFIFOHF 4 21 5 30 DACGATE 4 17 DACMB lt 3 0 gt 4 17 DAQCMPLINT 4 12 DAQCOMP 4 19 5 31 DAQEN 4 6 5 8 5 9 DAQPROG 4 19 DB DIS 4 18 DIOPAEN 4 11 5 26 DIOPBEN 4 11 5 26 DMACHA 4 12 DMACHAB lt 2 0 gt 4 9 DMACHB 4 12 DMACHBB lt 2 0 gt 4 9 DMATCA 4 20 5 23 DMATCB 4 20 5 23 DMATCINT 4 12 5 30 5 31 5 30 5 31 2 AT MIO 16X User Manual Index 4
78. 29 31 26 28 30 32 34 35 36 AT MIO 16X User Manual Signal Names AI GND lt 0 15 gt AI SENSE DACO OUT DACI OUT EXTREF AO GND DIG GND ADIO lt 0 3 gt BDIO lt 0 3 gt 5 V SCANCLK 2 14 Chapter 2 Descriptions Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements Analog Input Channels 0 through 15 In differential mode the input is configured for up to eight channels In single ended mode the input is configured for up to 16 channels Analog Input Sense This pin serves as the reference node when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes Analog Channel 0 Output This pin supplies the voltage output of analog output Channel 0 Analog Channel 1 Output This pin supplies the voltage output of analog output Channel 1 External Reference This is the external reference input for the analog output circuitry Analog Output Ground The analog output voltages are referenced to this node Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 supply Digital I O port A signals Digital I O port B signals 5 VDC Source These pins are fused for up to 1 A of 5 V supply
79. 3 Setthe CNT32 16 bit in Command Register 1 to notify the hardware that both Counters 4 and 5 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and Counter 5 decrements every time Counter 4 reaches zero The data acquisition operation is terminated when Counter 4 and Counter 5 reach Zero Programming the Scan Interval Counter Counter 2 of the Am9513A Counter Timer is used as the scan interval counter Counter 2 can be programmed to generate a pulse once every counts is referred to as the scan interval which is the time between successive scan sequences programmed into the mux channel gain memory N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following clocks are available internal to the Am9513A 5 MHz 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the scan interval timer can use signals connected to any of the Am9513A SOURCE input pins To program the scan interval counter use the following programming sequence All writes are 16 bit operations values given are hexadecimal 1 Write FF02 to the Am9513A Command Register to select the Counter 2 Mode Register AT MIO 16X User Manual 5 14 National Instruments Corporation Chapter 5 Programming 2 Write the mode value to the Am9513A Data Register to store the Counter 2 mode value Use one o
80. 3A Data Register to store the Counter 4 mode value for posttrigger acquisition modes Write 9025 to the Am95134A Data Register to store the Counter 4 mode value for pretrigger acquisition modes 3 Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register National Instruments Corporation 5 13 AT MIO 16X User Manual Programming Chapter 5 4 Write the 16 LSBs of the sample count value minus 1 to the Am9513A Data Register to store the Counter 4 load value Ifthe 16 LSBs are all 0 write FFFF 5 Write FF48 to the Am9513A Command Register to load Counter 4 6 Write 0 to the Am9513A Data Register to store 0 into the Load Register for Counter 4 reloading 7 Write FF28 to the Am9513A Command Register to arm Counter 4 8 Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register 9 Write 25 to the Am9513A Data Register to store the Counter 5 mode value 10 Write FFOD to the Am9513A Command Register to select the Counter 5 Load Register 11 Take the 16 MSBs of the sample count and complete the following steps Ifthe 16 LSBs of the sample count are all 0 or all 0 except for a 1 in the LSB write the 16 MSBs to the Am9513A Data Register to store the Counter 5 load value Otherwise add 1 to the 16 MSBs of the sample count and write that value to the Am9513A Data Register to store the Counter 5 load value 12 Write FF70 to the Am9513A Command Register to load and arm Counter 5 1
81. 5 PC I O channel interface 3 4 DMA Channel Clear Register 4 46 DMA operations programming 5 30 to 5 31 dual channel interleaved mode 5 31 procedure 5 30 to 5 31 servicing update requests 5 26 single channel interleaved mode 5 30 DMA request generation bits for controlling 4 13 to 4 14 programming 5 30 DMACHA bit 4 12 DMACHAB lt 2 0 gt bit 4 9 DMACHB bit 4 12 DMACHBB lt 2 0 gt bit 4 9 DMATCA bit clearing analog output circuitry 5 23 description 4 20 interrupt programming 5 31 programming DMA operations 5 30 DMATCA Clear Register clearing analog output circuitry 5 23 description 4 47 interrupt programming 5 31 programming DMA operations 5 30 DMATCB bit clearing analog output circuitry 5 23 description 4 20 interrupt programming 5 31 programming DMA operations 5 30 DMATCB Clear Register clearing analog output circuitry 5 23 description 4 48 interrupt programming 5 31 programming DMA operations 5 30 DMATCINT bit 4 12 AT MIO 16X User Manual Index documentation conventions used in the manual xiv organization of manual xiii related documentation xiv DRVAIS bit 4 14 E EEPROM ADC and DAC FIFO Depth field table 6 4 Area Information field table 6 4 Configuration Memory Depth Field table 6 3 EEPROM map 6 1 factory area information table 6 2 Revision and Subrevision field table 6 3 storage area 6 3 EEPROMCD bit 4 21 EEPROMCS bit 4 5 EEPROMDATA bit 4 21 EISA DMA
82. 5 23 definition 4 20 TMRREQ Clear Register clearing analog output circuitry 5 23 description 4 42 interrupt programming 5 31 programming DMA operations 5 30 servicing update requests 5 26 TMRREQ signal DAC waveform timing circuitry 3 16 interrupt programming 5 31 servicing update requests 5 25 5 26 TMRTRIG signal controlled by A4RCV bit 4 8 programming analog output circuitry 5 18 RTSI switch 3 24 servicing update requests 5 25 to 5 26 trigger applying 5 15 to 5 16 two s complement mode A D conversion values table 4 25 U unpacking the AT MIO 16X 1 7 update counter selecting 5 23 update interval counter programming 5 23 to 5 24 V voltage reference calibration 6 6 W waveform generation programming See also DAC waveform circuitry clearing analog output circuitry 5 23 cyclic waveform generation 5 18 to 5 19 programmed cycle waveform generation 5 19 to 5 21 pulsed cyclic waveform generation 5 21 to 5 23 selecting internal update counter 5 23 update interval counter 5 23 to 5 24 waveform cycle counter 5 24 to 5 25 waveform cycle interval counter 5 25 to 5 26 servicing update requests 5 25 to 5 26 National Instruments Corporation
83. 5 31 DAQ Start Register 4 38 DAQCMPLINT bit 4 12 DAQCOMP bit 4 19 5 31 DAQEN bit 4 6 5 8 5 9 DAQPROG bit 4 19 data acquisition and analog output timing connections 2 27 to 2 30 EXTCONV signal 2 28 EXTGATE signal 2 29 EXTSTROBE signal 2 27 EXTTMRTRIG signal 2 29 to 2 30 EXTTRIG signal 2 28 to 2 29 SCANCLK signal 2 27 data acquisition programming 5 10 to 5 26 analog input circuitry 5 4 analog output circuitry 5 18 applying a trigger 5 15 to 5 16 channel scanning 5 7 to 5 10 continuous channel scanning 5 7 to 5 8 interval channel scanning 5 8 to 5 10 clearing analog input circuitry 5 10 cyclic waveform generation 5 18 to 5 19 multiple analog input channel configurations 5 11 programmed cycle waveform generation 5 19 to 5 21 pulsed cyclic waveform generation 5 21 to 5 23 resetting hardware 5 16 to 5 17 sample counter s 5 12 to 5 14 sample interval counter 5 11 to 5 12 scan interval counter 5 14 to 5 15 National Instruments Corporation servicing data acquisition operations 5 16 single analog input channel configurations 5 10 single channel data acquisition sequence 5 5 to 5 6 single conversions 5 4 to 5 5 flow chart 5 4 generating single conversions 5 4 reading single conversion result 5 5 waveform cycle counter 5 24 to 5 25 waveform cycle interval counter 5 25 to 5 26 waveform generation functions 5 23 to 5 24 data acquisition rates multiple channel scanning rates A 4 to
84. 513A Command Register to decrement Counter n AT MIO 16X User Manual 5 24 National Instruments Corporation Chapter 5 Programming 7 Write the following value to the Am9513A Command Register to arm Counter n FF21 Arm Counter 1 FF22 Arm Counter 2 FF30 Arm Counter 5 After you complete this programming sequence Counter n is configured to count the DAC buffer retransmit signal from SOURCE3 as soon as the load arm counter command is written Programming the Waveform Cycle Interval Counter To program the cycle interval Counter for a pulsed cyclic waveform generation mode use the following programming sequence All writes are 16 bit operations values given are hexadecimal 1 Write FF02 to the Am9513A Command Register to select the Counter 2 Mode Register 2 Write the mode value to the Am9513A Data Register to store the Counter 2 mode value Am9513A counter mode information can be found in Appendix AMD Am9513A Data Sheet C225 Selects 5 MHz clock from SOURCE2 pin CB25 Selects 1 MHz clock 25 Selects 100 kHz clock CD25 Selects 10 kHz clock CE25 Selects 1 kHz clock CF25 Selects 100 Hz clock C525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum 3 Write FFOA to the Am9513A Command Register to select the Counter 2 Load Register 4 Write the desired cycle interval plus one to the Am9513A Data Register to store the Counter 2 load value 5 W
85. 513A Counter Timer is in the following state 16 bit mode is enabled The BCD scaler division is selected FOUT signal is turned off e counter OUT output pins are set to the high impedance output state All counters are loaded with a nonterminal count value For additional details concerning the Am9513A Counter Timer see Appendix C AMD Am9513 Data Sheet AT MIO 16X User Manual 5 2 National Instruments Corporation Chapter 5 Programming Write to the Am9513A Issue a master reset operation Command Register Write OxFFEF to the Am9513A Enable 16 bit access mode Command Register Write OxFF17 to the Am9513A Point to the master mode register Command Register Write OxF000 to the Am9513A Load the master mode value Data Register Write OXFFOO ctr to the Point to the counter mode register Am9513A Command Register Write 0x0004 to the Am9513A Store the counter mode value Data Register Write 0 08 ctr to the Point to the counter load register Am9513A Command Register Write 0x0003 to the Am9513A Store an inactive count value Data Register Increment Ctr Write OxFFSF to the Am9513A Load all counters Command Register Figure 5 1 Initializing the Am9513A Counter Timer National Instruments Corporation 5 3 AT MIO 16X User Manual Programming Chapter 5 Programming the Analog Input Circuitry The analog input circuitry can be programmed for a number of different modes depen
86. 59 64 67 68 33 65 30 28 60 25 57 34 66 31 63 61 26 58 23 62 22 21 20 54 55 4 7 9 12 13 15 18 35 36 39 44 50 53 52 17 49 47 19 51 16 48 8 14 46 45 50 Pin Pins Signal Names 1 2 3 18 19 20 21 22 23 24 33 25 27 29 31 26 28 30 32 34 35 36 37 National Instruments Corporation AI GND lt 0 15 gt AI SENSE DACO OUT DACI OUT EXTREF AO GND DIG GND 5 SCANCLK EXTSTROBE B 3 I O Connector Descriptions Analog Input Ground These pins the reference point for single ended measurements and the bias current return point for differential measurements Analog Input Channels 0 through 15 In differential mode the input is configured for up to eight channels In single ended mode the input is configured for up to 16 channels Analog Input Sense This pin serves as the reference node when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes Analog Channel 0 Output This pin supplies the voltage output of analog output Channel 0 Analog Channel 1 Output This pin supplies the voltage output of analog output Channel 1 External Reference This is the external reference input for the analog output circuitry Analog Output Ground The analog output vo
87. 8 shows the connections for a frequency measurement application A second counter can also be used to generate the gate signal in this application National Instruments Corporation 2 31 AT MIO 16X User Manual Configuration and Installation Chapter 2 Signal Source DIG GND Connector 16 Board Figure 2 18 Frequency Measurement Application Two or more counters can be concatenated by tying the OUT signal from one counter to the SOURCE signal of another counter The counters can then be treated as one 32 bit or 48 bit counter for most counting applications The signals for Counters 1 2 and 5 and the FOUT output signal are directly tied from the Am9513A input and output pins to the I O connector In addition the GATE SOURCE and pins are pulled up to 5 V through a 4 7 kQ resistor The input and output ratings and timing specifications for the Am9513A signals are given as follows Absolute maximum voltage input rating 0 5 V to 7 0 V with respect to DIG GND Am9513A digital input specifications referenced to DIG GND Vin input logic high voltage 2 2 V minimum Vir input logic low voltage 0 8 V maximum Input load current 10 pA maximum AT MIO 16X User Manual 2 32 National Instruments Corporation Chapter 2 Am9513A digital output specifications referenced to DIG GND output logic high voltage 2 4 V minimum output logic low voltage 0 4 V maximum output source curre
88. A 5 single channel rates A 4 data acquisition timing circuitry block diagram 3 5 definition 3 7 multiple channel scanned data acquisition 3 10 to 3 12 rates of data acquisition 3 8 single channel data acquisition 3 8 to 3 10 single read timing 3 7 to 3 8 theory of operation 3 7 to 3 10 data buffers PC I O channel interface circuitry 3 3 DB DIS bit 4 18 default settings for National Instrument products table 2 5 differential connections general considerations 2 18 ground referenced signal sources 2 18 to 2 19 nonreferenced floating signal sources 2 19 to 2 21 differential DIFF input configuration 2 7 definition table 2 7 differential nonlinearity errors analog input A 4 analog output A 6 DIG GND signal definition 2 14 B 3 digital I O signal connections 2 25 to 2 26 Digital Input Register 4 57 5 26 digital I O configuration 2 10 signal connections 2 25 to 2 26 National Instruments Corporation Index specifications A 6 digital I O circuitry block diagram 3 19 programming 5 26 theory of operation 3 19 to 3 20 Digital I O Register Group 4 56 to 4 58 Digital Input Register 4 57 5 26 Digital Output Register 4 58 5 26 register map 4 2 Digital Output Register 4 58 5 26 DIOPAEN bit 4 11 5 26 DIOPBEN bit 4 11 5 26 DMA channel bits for selecting 4 9 to 4 10 configuration 2 6 controlled by ADCREQ bit 4 13 to 4 14 default settings for National Instrument products table 2
89. AC output voltage To correct the gain error the output calibration routine sets each analog output to 5 V and adjusts CALDACA and CALDACS until it measures 5 V between each analog output and AO GND The gain error is always calibrated immediately after the offset is calibrated Notice that CALDACA and CALDACS adjust the gain by varying the values of the internal DAC references Hence the gain of an analog output channel cannot be adjusted under software control if the channel is using an external reference but the offset can still be adjusted National Instruments Corporation 6 7 AT MIO 16X User Manual Appendix A Specifications This appendix lists the specifications of the AT MIO 16X These are typical at 25 C unless otherwise stated The operating temperature range is 0 to 70 C A warmup time of at least 15 minutes is required Analog Input Number of input channels Analog resolution Maximum sampling rate Relative accuracy Differential nonlinearity DNL Differential analog input ranges Common mode input range Overvoltage protection ACHO to ACH15 and AISENSE Common mode rejection ratio Bandwidth 3 dB Input bias current Input impedance Gains Pregain offset error After calibration Before calibration Temperature coefficient Postgain offset error After calibration Before calibration Temperature coefficient National Instruments Corporation 16 single ended 8 differential 16 bit 1 in 65 536 100 ksamples
90. AC sequence ends by running its course or when an error condition occurs such as UNDERFLOW DAQ Complete Interrupt Enable This bit controls the generation of an interrupt when a data acquisition sequence completes If DAQCMPLINT is set an interrupt request is generated when the data acquisition operation completes The interrupt request is serviced by strobing the DAQ Clear Register When DAQCMPLINT is cleared completion of a data acquisition sequence does not generate an interrupt A data acquisition sequence ends by running its course or when an error condition occurs such as OVERRUN or OVERFLOW Input Output Interrupt Enable This bit along with the appropriate mode bits enables and disables I O interrupts generated from the AT MIO 16X To select a specific mode refer to Table 4 3 for available modes and associated bit patterns DMA Channel A Enable This bit controls the generation of DMA requests on DMA Channel A as selected in Command Register 2 DMA requests are generated from A D conversions as well as from timer updates If DMACHA is set then requesting is enabled for DMA Channel A If DMACHA is cleared no DMA requests are generated on DMA Channel A To select a specific mode refer to Table 4 3 for available modes and associated bit patterns DMA Channel B Enable This bit controls the generation of DMA requests on DMA Channel B as selected in Command Register 2 DMA requests are generated from A D conversions as we
91. AN LAST GHOST CHAN DSP LSB Bit Name Description 15 CHAN SE Channel Single Ended This bit configures the analog input section for single ended or differential mode See Table 4 9 14 CHAN AIS Channel Analog Input Sense This bit sets the analog input section for RSE or NRSE mode when CHAN CAL is cleared When CHAN CAL is set this bit controls the reference signal connected to the positive 4 side of the PGIA for calibration purposes See Table 4 9 13 CHAN CAL Channel Calibration Enable This bit controls the analog input configuration switches CHAN CAL is used to disconnect the input multiplexers from the PGIA during a calibration procedure so that known internal reference signals can be routed to the amplifier See Table 4 9 12 CHAN BIP Channel Bipolar This bit configures the ADC for unipolar or bipolar mode When CHAN_BIP is clear the ADC is configured for unipolar operation and values read from the ADC FIFO are in straight binary format When CHAN BIP is set the ADC is configured for bipolar operation and values The FIFO values are two s complement and automatically sign extended 11 10 0 Reserved These bits must always be set to zero AT MIO 16X User Manual 4 26 National Instruments Corporation Chapter 4 Bit Name 9 6 CHANSEL lt 3 0 gt Register Map and Descriptions Description continued Input Channel Select These four bits control the input multiplexer address setting
92. AT MIO 16X User Manual Multifunction I O Board for the PC AT EISA April 1994 Edition Part Number 320640 01 Copyright 1992 1994 National Instruments Corporation All Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support fax 800 328 2203 512 794 5678 Branch Offices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Netherlands 03480 33466 Norway 32 848400 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 U K 0635 523545 Limited Warranty The AT MIO 16X is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media
93. Am9513A are reserved for this purpose This leaves Counters 1 and 5 available for general purpose or waveform generation use National Instruments Corporation 5 1 AT MIO 16X User Manual Programming Chapter 5 Initializing the AT MIO 16X The AT MIO 16X hardware must be initialized for the AT MIO 16X circuitry to operate properly To initialize the AT MIO 16X hardware complete the following steps 1 Write 0 to Command Registers lt 1 4 gt 2 Access the following strobe registers CONFIGMEMCLR Register DAQ Clear Register DMATC A and B Clear Registers DMA Channel Clear Register DAC Clear Register Clear Register ADC Calibration Register 3 Initialize the Am9513A see Initializing the Am9513A section later in this chapter 4 Disable all RTSI switch connections see Programming the RTSI Switch section later in this chapter This sequence leaves the AT MIO 16X circuitry in the following state e DMA and interrupts are disabled The DMA circuitry is cleared e The outputs of counter timers are in the high impedance state The analog input circuitry is initialized The analog output is in immediate update mode The ADC and DAC FIFOs are cleared The DIO ports A and B are set for input mode Initializing the Am9513A Use the following sequence to initialize the Am9513A Counter Timer writes are 16 bit operations values are given in hexadecimal After this sequence of writes the Am9
94. Channel Configurations During a scanning data acquisition operation a selected number of locations in the channel configuration memory are sequenced through by the acquisition circuitry A new channel configuration value is selected after each A D conversion The first conversion is performed on the first channel setting in the memory second conversion is performed on the second channel and gain setting and so on The last entry written to the channel configuration memory must have the LAST bit set This bit marks the end of the scan sequence After the last conversion is performed the scan sequence starts over If there are N entries in the channel configuration memory every Nth conversion in the data collected is performed on the same channel gain mode and range setting Multiple conversions can be performed on each entry in the channel configuration memory before incrementing to the next entry in the scan sequence If the SCANDIV bit in Command Register 1 is set the channel configuration memory increments to the next entry when an active low pulse is detected the Am9513A Counter Timer OUTI signal If the SCANDIV bit is cleared the channel configuration memory is incremented to the next entry after every conversion The channel configuration memory must be loaded with the desired scan sequence before data acquisition begins To load the channel configuration memory perform the following write operations where N is the
95. Connector AT MIO 16X User Manual National Instruments Corporation Chapter 2 Configuration and Installation Figure 2 5 shows the pin assignments for the AT MIO 16X 68 pin I O connector ACHO AIGND ACH9 ACH2 AIGND ACHII AISENSE ACHI2 5 AIGND 14 ACH7 AIGND AOGND AOGND DGND ADIOO BDIOI DGND ADIO2 BDIO3 ADIO3 SCANCLK EXTSTROBE DGND EXTCONV SOURCEI GATEI OUTI DGND OUT2 SOURCES DGND DGND ACH8 ACHI AIGND ACHIO ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND 15 DACO DACI EXTREF BDIOO DGND ADIOI BDIO2 DGND 5 V DGND DGND EXTTRIG EXTGATE DGND 5 DGND EXTTMRTRIG GATE2 DGND GATES OUTS FOUT nt nt nt o nN rn o R tA wlols RTS TR RTA TR IAT 1 15 14 s 6 EX 2 B Figure 2 5 AT MIO 16X 68 Pin I O Connector National Instruments Corporation 2 13 AT MIO 16X User Manual Configuration and Installation Signal Connection Descriptions 68 Pin Pins 24 27 29 32 56 59 64 67 68 33 65 30 28 60 25 57 34 66 31 63 61 26 58 23 62 22 21 20 54 55 4 7 9 12 13 15 18 35 36 39 44 50 53 52 17 49 47 19 51 16 48 8 14 46 50 Pin Pins 1 2 3 18 19 20 21 22 23 24 33 25 27
96. Corporation Chapter 2 Configuration and Installation SOURCE GATE Signal Source DIG GND Connector 16 Board Figure 2 17 Event Counting Application with External Switch Gating To perform pulse width measurement a counter is programmed to be level gated The pulse to be measured is applied to the counter GATE input The counter is programmed to count while the signal at the GATE input is either high or low If the counter is programmed to count an internal timebase then the pulse width is equal to the counter value multiplied by the timebase period For time lapse measurement a counter is programmed to be edge gated An edge is applied to the counter GATE input to start the counter The counter can be programmed to start counting after receiving either a high to low edge or a low to high edge If the counter is programmed to count an internal timebase then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period To measure frequency a counter is programmed to be level gated and the rising or falling edges are counted in a signal applied to a SOURCE input The gate signal applied to the counter input is of some known duration In this case the counter is programmed to count either rising or falling edges at the SOURCE input while the gate is applied The frequency of the input signal is then the count value divided by the known gate period Figure 2 1
97. EAR UL Figure 3 6 Single Channel Pretrigger Data Acquisition Timing The pretrigger sequence is programmed in much the same way as a posttrigger sequence The sample interval timer is programmed to generate conversion pulses under a gate signal and the sample counter is programmed to count the number of conversions The only difference between pretrigger and posttrigger sequences for all data acquisition modes is that the sample counter waits for a gating signal in the pretrigger mode before beginning the count For posttrigger sequences the sample timer is independent of the gating signal and for pretrigger sequences the sample timer is dependent on the gating signal Multiple Channel Data Acquisition Multiple channel data acquisition is performed by enabling scanning during data acquisition Multiple channel scanning is controlled by the configuration memory register The configuration memory register consists of 512 words of memory Each word of memory contains a multiplexer address for input analog channel selection a gain setting a mode setting single ended or differential and a range setting unipolar or bipolar Each word of memory also contains a bit for synchronizing scanning sequences of different rates a bit enabling serial data transmission of channel conversion data over the RTSI bus to the AT DSP2200 digital signal processing board and a bit indicating if the entry is the last in the scan sequence In interval scanni
98. ES gt continues National Instruments Corporation 4 13 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Bit Name Description continued Table 4 3 DMA and Interrupt Modes Continued Interface Mode fi fo Li 1 ff channer to DACO and DACI with 5 ff canner from ADC with 1 1 1 0 0 Channels and to DACs 0 and 1 double buffered with ADC interrupt ee 1 1 1 1 0 0 Channels and B from ADC double buffered with timer interrupt Channel A DACO and Channel from ADC Fa fifi 1 1 0 Channel A to DACI and Channel B from ADC Mode Description ADCREQ DACIREQ le DACOREQ 5 DACIREQ DAC 1 Request Enable This bit controls requesting and interrupt generation from D A updates If this bit is set an interrupt or DMA request is generated when the DAC is ready to receive data If this bit is cleared no DMA request or interrupt is generated To select a specific mode refer to Table 4 3 for available modes and associated bit patterns 4 DACOREQ DAC 0 Request Enable This bit controls DMA requesting interrupt generation from D A updates If this bit is set an interrupt or DMA request is generated when the DAC is ready to recei
99. ES 5 TMRTRIG OUTI EXTTRIG TRIGGERO 2 TRIGGER4 TRIGGERS TRIGGER6 Input Bidirectional Output Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional AT MIO 16X User Manual Programming Chapter 5 Figure 3 19 in Chapter 3 Theory of Operation diagrams the AT MIO 16X RTSI switch connections RTSI Switch Signal Connection Considerations The AT MIO 16X board has a total of nine signals connected to the seven A side pins of the RTSI crossbar switch These same signals also appear at the AT MIO 16X I O connector As shown in Table 5 2 two AT MIO 16X signals are connected to pin A2 and two signals are connected to pin A4 The routing of these signals is further controlled by the bits A4DRV A2DRV and A2RCV in Command Register 2 e To drive the RTSI switch pin A2 with the signal OUT2 set the A2DRV bit in Command Register 2 Otherwise clear the A2DRV bit e drive the signal GATEI from pin A2 of the switch set the A2RCV bit in Command Register 2 Otherwise clear the A2RCV bit Note If both the AZDRV and A2RCV bits are set the GATEI signal is driven by the signal OUT2 This arrangement is probably not desirable e To drive the RTSI switch pin A4 with the signal OUTS set the AA4DRV bit in Command Register 2 Otherwise clear the A4DRV bit e drive the
100. FIFO Register returns meaningless data Once an A D conversion is initiated the ADCFIFOEF bit is set approximately 10 usec after initiating the conversion indicating that the data conversion result can be read from the FIFO An ADC FIFO overflow condition occurs if more than 512 conversions are initiated and stored in the ADC FIFO before the ADC FIFO Register is read If this condition occurs the OVERFLOW bit is set in the Status Register to alert you that one or more A D conversion results have been lost because of FIFO overflow Strobing the DAQ Clear Register resets this error flag An ADC overrun condition occurs if an attempt is made to start a new conversion while the previous conversion is being completed If this condition occurs the OVERRUN bit is set in Status Register to indicate an error condition or that an invalid operation occurred Strobing the DAQ Clear Register resets this error flag Programming Single Channel Data Acquisition Sequence The following programming sequence for sample counts less than 65 537 leaves the data acquisition circuitry in a retriggerable state The sample interval and sample counters are reloaded at the end of the data acquisition to prepare for another data acquisition operation The counters do not need reprogramming and the next data acquisition operation starts when another trigger condition is received National Instruments Corporation 5 5 AT MIO 16X User Manual Programming Chapter 5 In
101. Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 2 16 Figure 2 17 Figure 2 18 Figure 2 19 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figures AT MIO 16X with 50 Pin I O Connector Parts Locator Diagram 2 1 AT MIO 16X with 68 Pin I O Connector Parts Locator Diagram 2 2 Example Base I O Address Switch Settings see 2 4 16 50 Pin Connector eese 2 12 16 68 Pin Connector 2 13 anteire dos cud sense 2 16 Differential Input Connections for Ground Referenced Signals 2 19 Differential Input Connections for Nonreferenced Signals 2 20 Single Ended Input Connections for Nonreferenced or Floating Signals 2 22 Single Ended Input Connections for Ground Referenced Signals 2 23 Analog Output Connections 2 entes ster tine nene a NER En ease Ee ae pU ge GR 2 25 VO Connect Ons a
102. GATE inputs the Am9513A generates six internal timebase clocks from the clock signal supplied by the AT MIO 16X The base clock signal is selected by a register in the AT MIO 16X register set and then divided by 10 The default value is 1 MHz into Am9513A 10 MHz clock signal on the AT MIO 16X The six internal timebase clocks can be used as counting sources and these clocks have a maximum skew of 75 nsec between them The SOURCE signal shown in Figure 2 19 represents any of the signals applied at the SOURCE inputs GATE inputs or internal timebase clocks See Appendix C AMD Am9513A Data Sheet for further details Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals Figure 2 19 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low at least 100 nsec before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tgsy and tgh in Figure 2 19 Similarly the gate signal must be held for at least 10 nsec after the rising or falling edge of a source signal for the gate to take effect at that source edge The gate high or low period must be at least 145 nsec in duration If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or
103. IO 16X I O connector The CB 50 is useful for prototyping an application or in situations where AT MIO 16X interconnections are frequently changed When you develop a final field wiring scheme however you may want to develop your own cable This section contains information and guidelines for designing custom cables In making your own cabling you may decide to shield your cables The following guidelines may help e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that differential inputs are used Tie the shield for each signal pair to the ground reference at the source analog lines pins 1 through 23 should be routed separately from the digital lines pins 24 through 50 e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise from switching digital signals coupling into the analog signals National Instruments Corporation 2 35 AT MIO 16X User Manual Configuration and Installation Chapter 2 Cabling Considerations for the AT MIO 16X with 68 Pin I O Connector National Instruments has a 68 pin mating connector and shell kit you can use with the AT MIO 16X board In making your own cabling you may decide to shield your cables following guidelines may help e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results
104. L NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEW NI DAQ and RTSI are trademarks of National Instruments Corporation Product and company names listed are trademarks or trade names of their respective companies Warning Regardi
105. MIO 16X 5 2 register programming considerations 5 1 resource allocation considerations 5 1 RTSI bus trigger line 5 27 to 5 28 RTSI switch 5 28 to 5 31 National Instruments Corporation Index 11 Index DMA operations 5 30 to 5 31 interrupt programming 5 31 RTSI switch signal connections 5 28 single channel data acquisition sequence 5 5 to 5 6 single conversions generating 5 5 reading results 5 5 pseudo simultaneous scanning 5 7 pulse width measurement 2 31 pulsed cyclic waveform generation 5 21 to 5 23 pulses producing 2 30 R reference calibration 6 6 referenced single ended RSE input configuration 2 8 definition table 2 7 single ended connections for floating signal sources 2 22 registers ADC Event Strobe Register Group 4 34 to 4 40 Calibration Register 4 40 CONFIGMEMCLR Register 4 35 5 10 5 11 CONFIGMEMLD Register 4 36 5 10 5 11 DAQ Clear Register 4 37 5 10 5 30 5 31 DAQ Start Register 4 38 Single Conversion Register 4 39 Am9513A Counter Timer Register Group 4 52 to 4 55 Am9513A Command Register 4 54 Am9513A Data Register 4 53 Am9513A Status Register 4 55 resource allocation programming considerations 5 1 Analog Input Register Group 4 23 to 4 29 ADC FIFO Register 4 24 to 4 25 5 5 5 16 5 31 CONFIGMEM Register 4 26 to 4 29 5 10 5 11 Analog Output Register Group 4 30 to 4 33 DACO Register 4 32 5 18 DACI Register 4 33 5 18 Configuration and St
106. NRSE sources 2 22 to 2 23 single ended input configuration NRSE input 16 channels 2 8 definition table 2 7 RSE input 16 channels 2 8 definition table 2 7 single read timing 3 7 to 3 8 software optional 1 4 SOURCE OUT and GATE timing signals counter signal connections 2 30 to 2 34 RTSI bus interface circuitry 3 24 timing I O circuitry 3 21 to 3 22 SOURCE signal 2 15 B 4 SOURCES signal 2 15 B 5 specifications Am9513A System Timing Controller C 33 to C 37 analog data acquisition rates A 4 to A 5 analog input A 1 to A 4 analog output A 5 to A 6 digital I O 6 operating environment A 7 physical characteristics A 7 power requirements A 7 storage environment A 7 timing I O A 7 square waves producing 2 30 SRC3SEL bit 4 18 5 21 5 23 Status Register 1 4 19 to 4 21 Status Register 2 4 22 5 26 storage environment specifications A 7 straight binary mode A D conversion values 4 24 to 4 25 switch settings See jumpers and switches system noise A 4 T technical support D 1 theory of operation analog input circuitry 3 6 to 3 7 A D converter 3 7 ADC FIFO buffer 3 7 AT MIO 16X PGIA 3 6 block diagram 3 5 input multiplexers 3 6 analog output circuitry 3 12 to 3 14 block diagram 3 13 calibration 3 14 circuitry 3 13 configuration 3 14 AT MIO 16X block diagram 3 1 Index 13 AT MIO 16X User Manual Index DAC waveform circuitry and timing 3 14 to 3 19 FIFO continuous cyclic wa
107. O 16X analog input and analog output circuitry The calibration process involves reading offset and gain errors from the analog input and analog output sections and writing values to the appropriate calibration DACS to null out the errors There are five calibration DACs associated with the analog input section and four calibration DACS with the analog output section two for each output channel After the calibration process is complete each calibration DAC is at a known value Because these values are lost when the board is powered down they are also stored in the onboard EEPROM for future referencing Figure 6 1 shows where information is stored in the EEPROM Factory Information Factory Reference Factory Bipolar Area Fasten ADC Pregain Offset MSB User References 07 User Reference 4 MSB 05 User Reference 3 MSB 5 03 User Reference 2 MSB 01 User Reference 1 MSB Figure 6 1 AT MIO 16X EEPROM Map National Instruments Corporation 6 1 AT MIO 16X User Manual Calibration Procedures Chapter 6 The AT MIO 16X is factory calibrated before shipment and the associated calibration constants are stored in the factory area of the EEPROM Table 6 1 lists what is stored in the EEPROM factory area Table 6 1 EEPROM Factory Area Information Location Description 127 Year of reference calibration for example 92 1992 126 Month of reference calibration for example 2 February 125 Day of reference calib
108. Pascal Turbo C Turbo C Borland C and Microsoft C for DOS and Visual Basic Turbo Pascal Microsoft C with SDK and Borland for Windows NI DAQ software is on high density 5 25 in and 3 5 in diskettes National Instruments Corporation 1 3 AT MIO 16X User Manual Introduction Chapter 1 Optional Software This manual contains complete instructions for directly programming the AT MIO 16X Normally however you should not need to read the low level programming details in the user manual because the NI DAQ software package for controlling the AT MIO 16X is included with the board Using NI DAQ is quicker and easier than and as flexible as using the low level programming described in Chapter 5 Programming The AT MIO 16X can also be used with LabWindows an innovative program development software package for test and measurement applications LabWindows enhances Microsoft QuickBASIC and C with an interactive development environment a graphical user interface function panels to generate source code and libraries for data acquisition instrument control data analysis and graphical presentation You can use the AT MIO 16X with LabVIEW for Windows or LabWindows for DOS LabVIEW and LabWindows are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows enhances Microsoft C and QuickBASIC Both packages include extensive libraries for data
109. Port A ADIO lt 3 0 gt Port B BDIO lt 3 0 gt Switch Connector AT MIO 16X Board Figure 2 12 Digital I O Connections In Figure 2 12 port A is configured for digital output and port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2 12 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2 12 AT MIO 16X User Manual 2 26 National Instruments Corporation Chapter 2 Configuration and Installation Power Connections The I O connector provides 5 V from the PC power supply This 5 V is referenced to DIG GND and can be used to power external digital circuitry Power rating 1 0 A at 5 V 10 fused Warning Under no circumstances should these 5 V power pins be directly connected to analog or digital ground or to any other voltage source on the AT MIO 16X or any other device Doing so can damage the AT MIO 16X and the PC National Instruments is not liable for damages resulting from such a connection Timing Connections for Data Acquisition and Analog Output The data acquisition and analog output timing signals are SCANCLK EXTSTROBE EXTCONV EXTTRIG EXTGATE and EXTTMRTRIG SCANCLK Signal SCANCLK is an output signal that generates a low to high edge whenever an A D conversion begins SCANCLK pulses only when scannin
110. Read only Status Register 2 Read only Analog Input Register Group ADC FIFO Register Read only CONFIGMEM Register Write only Analog Output Register Group DACO Register Write only DACI Register Write only continues National Instruments Corporation 4 1 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Table 4 1 AT MIO 16X Register Map Continued Register Name Offset Address Type Size Hex ADC Event Strobe Register Group CONFIGMEMCLR Register 1B Read only CONFIGMEMLD Register 1B Write only DAQ Clear Register Read only DAQ Start Register Read only Single Conversion Register Write only ADC Calibration Register Write only DAC Event Strobe Register Group TMRREQ Clear Register Read only DAC Update Register Write only DAC Clear Register Read only General Event Strobe Register Group DMA Channel Clear Register Read only DMATCA Clear Register Write only DMATCB Clear Register Read only External Strobe Register Write only Calibration DAC 0 Load Register Write only Calibration DAC 1 Load Register Write only Am9513A Counter Timer Register Group Am9513A Data Register Read and write Am9513A Command Register Write only Am9513A Status Register Read only Digital I O Register Group Digital Input Register Read only Digital Output Register Write only RTSI Switch Register Group RTSI Switch Shift Register Write only RTSI Switch Strobe Register Write only Register Sizes Two different transfer sizes for
111. TRIG pulse is detected Clearing TMRREQ when interrupt or DMA mode is enabled clears the respective interrupt or DMA request Address Base address 1F hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Clears the TMRREQ signal in Status Register 1 and its associated interrupts and clears the DAC COMP signal in Status Register 1 and its associated interrupt The analog output DACS can be updated internally and externally in the waveform generation mode through the control of A4RCV If A4RCV is enabled internal updating is selected and any signal from the RTSI switch can control the updating interval If OUT2 is to be used for updating the DACs A2DRV must also be enabled If OUTS is to be used A4DRV must be enabled as well If A4RCV is disabled external updating is selected and the EXTTMRTRIG signal from the I O connector is used for updating In all cases a falling edge on the selected signal triggers the updating mechanism in posted update mode This trigger also sets the TMRREQ bit in Status Register 1 and generates an interrupt or DMA request if so enabled AT MIO 16X User Manual 4 42 National Instruments Corporation Chapter 4 Register Map and Descriptions DAC Update Register Accessing the DAC Update Register with posted update mode enabled updates both DACO and DACI simultaneously with the previously written values and removes DAC FIFO data for DACO DAC1 or both as programmed
112. UTS pins can be used in several different ways If waveform generation is enabled an active low pulse on the output of the counter selected through the RTSI switch updates the analog output on the two DACs The counter outputs can also be used to trigger interrupt and DMA requests If the proper mode is selected in Command Register 2 an interrupt or DMA request occurs when a falling edge signal is detected on the selected DAC update signal Counters 3 and 4 of the Am9513A are dedicated to data acquisition timing and therefore are not available for general purpose timing applications Signals generated at OUT3 and OUTA are sent to the data acquisition timing circuitry GATE3 is controlled by the data acquisition timing circuitry OUTS3 is internally connected to EXTCONV so that when internal data acquisition sequences OUT3 are used EXTCONV should be disconnected or tristated For the same reason if external data acquisition sequences EXTCONV are used OUT3 should be programmed to the high impedance state Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with Counter 4 to form a 32 bit sample counter The SCANCLK signal is connected to the SOURCE input of the Am9513A and OUT is sent to the data acquisition timing circuitry This allows Counter 1 to be used to divide the SCANCLK signal for generating the CONFIGCLK signal See the Data Acquisition Timing Circuitry section earlier in this chapter Counter
113. Video and Mass Storage National Instruments Corporation C 1 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 2 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 3 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 4 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 5 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 6 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 7 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 8 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 9 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 10 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 11 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 12 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 13 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 14 National Instruments Corporation Appendix C AMD Am9513A Data Sheet Nat
114. Voltage 5 0 to 10 0 V Accuracy 0 00015 21 5 ppm standard 0 000375 3 75 ppm sufficient It is important to realize that inaccuracy of the internal voltage reference results only in gain error Offset error is unaffected If an application can tolerate slight gain inaccuracy there should not be a need to redetermine the value of the onboard reference Calibration DACs There are eight 8 bit DACs CALDAC O 7 and 12 bit DAC CALDACS3 on the AT MIO 16X that are used for calibration These DACs are described in Table 6 2 National Instruments Corporation 6 5 AT MIO 16X User Manual Calibration Procedures Chapter 6 Table 6 2 Calibration DACs Analog DAC Function Adjustment Incremental Range Effect CALDACO Coarse gain trim 1169 ppm 9 13 ppm CALDACI Fine gain trim 65 1 ppm 0 509 ppm CALDAC2 Coarse postgain offset trim 51 8 mV 404 uV CALDAC3 Fine postgain offset trim 512 uV 4 00 uV CALDACS Pregain offset trim 12 mV 0 586 uV CALDAC4 DACO gain trim 976 ppm CALDACS DAC gain trim 976 ppm CALDAC6 DACO offset trim 4 86 mV CALDAC7 DACI offset trim 4 86 mV Reference Calibration The AT MIO 16X has a stable voltage reference to which gain can be calibrated The value of this voltage reference is determined through the reference calibration routine which requires a known external voltage between 5 and 9 99 V to be connected differentially on any desired input channel The routine calibra
115. a register in the AT MIO 16X register set The DAC FIFO and RTSI latch are used for posted updating of the DACs Data written to the DACS is buffered by the DAC FIFO to be updated at a later time The DAC FIFO can buffer up to 2 048 values before updating the DAC The RTSI latch is a special case of the posted update mode because data is not directly written to the AT MIO 16X board from the PC but it is received serially from the AT DSP2200 In this case only one value can be buffered before updating the DAC In the posted update mode you can use one of the three paths to transfer data to the DACs Data can be sent through the FIFO and local latch concurrently or separately In this instance the value written to the DAC through the local latch is not updated until the update pulse trigger occurs If the RTSI latch is used to transfer serial data from the AT DSP2200 over the RTSI bus no other transferring path is allowed In other words data cannot be transmitted serially over the RTSI bus to DAC Channel 0 and transferred through the FIFO to DAC Channel 1 at the same time These modes are mutually exclusive National Instruments Corporation 3 15 AT MIO 16X User Manual Theory of Operation Chapter 3 DAC Waveform Timing Circuitry Waveform timing implies precise updating of the analog output DACs to create a pure waveform without any jitter or uncertainty This timing is accomplished by posting updates to the DACs Posted update mode
116. acquisition instrument control data analysis and graphical data presentation Part numbers for these software packages are listed in the following table LabVIEW for Windows 776670 01 LabWindows Standard package 776473 01 Advanced Analysis Library 776474 01 Standard package with the Advanced Analysis Library 776475 01 AT MIO 16X User Manual 1 4 National Instruments Corporation Chapter 1 Introduction Optional Equipment for AT MIO 16X with 50 Pin Ribbon Cable I O Connector Equipment Part Number CB 50 I O connector block 50 screw terminals National Instruments Corporation 1 5 with 0 5 m type NBI cable with 1 0 m type NBI cable AT Series RTSI bus cables for 2 boards 3 boards 4 boards 5 boards SCXI signal conditioning modules SCXI 1100 32 channel differential multiplexer amplifier SCXI 1120 8 channel isolated analog input SCXI 1121 4 channel isolated transducer amplifier with excitation SCXI 1160 16 channel SPDT relay module SCXI 1161 8 channel Power relay module SCXI 1162 32 channel isolated digital input module SCXI 1163 32 channel isolated digital output module SCXI 1140 8 channel simultaneously sampling differential amplifier SCXI 1180 feedthrough panel SCXI 1181 breadboard SCXI signal conditioning chassis SCXI 1000 4 slot chassis SCXI 1001 12 slot chassis AMUX 64T analog multiplexer board with 0 2 m ribbon cable with 0 5 m ribbon cable with 1 0 m ribbon cable with 2 0 m ribbon cabl
117. airs eet tone 4 32 DACI Registern icis etes te prts quii e 4 33 ADC Event Strobe Register Group acsi eerte ci inet e Ort Lea ar eoe Reha 4 34 CONFIGMEMCLR 2 4 4212124 14 220200 21 404 1 6666 86 8 8 4 35 CONFIGMENIED R6GBSISIGE iios terti etae ea pesto atr 4 36 DAQ Clear RESiSter E 4 37 DAQ Start RegISEIet iois eie us 4 38 Single Conversion Register teoria eran ee Pete eh oo sata e Po a e Enea 4 30 ADC Calibration po esos pU 4 40 DAC Event Strobe Register Group 4 41 into Dee ob ae eS 4 42 DAC Update 4 43 DAG Clear erre tope 4 44 General Event Strobe Register Group ss 4 45 DMA Channel Clear nettes 4 46 DMATCA Clear Register ener rete e Nossa sg e e ede te este et vog 4 47 DMATCB Cleat REGIS UGE te re Period EU 4 48 External Strobe Register ueteres o Ree th ee o ve e 4 49 Calibration DAC 0 Load Register 4 50 Calibration DAC 1 Load Register 4 51 Am9513A Counter Timer Register Group ss 4 52 Am9513A Data R Bist r ese ki netos REA Ee IURE 4 53 A
118. al Convert A high to low edge on EXTCONV causes an A D conversion to occur Conversions initiated by the EXTCONV signal are inhibited outside of a data acquisition sequence and when gated off SOURCE This pin is from the Am9513A Counter 1 signal GATE This is from the Am9513A Counter 1 signal OUTPUT This pin is from the Am9513A Counter 1 signal External Timer Trigger If selected a high to low edge on EXTTMRTRIG results in the output DACS being updated with the value written to them in the posted update mode EXTTMRTRIG will also generate a timed interrupt if enabled GATE2 This pin is from the Am9513A Counter 2 signal OUTPUT This pin is from the Am9513A Counter 2 signal SOURCES This pin is from the Am9513A Counter 5 signal GATES This pin is from the Am9513A Counter 5 signal OUTS This pin is from the Am9513A Counter 5 signal Frequency Output This pin is from the Am9513A FOUT signal National Instruments Corporation Appendix C AMD Am9513A Data Sheet This appendix contains the manufacturer data sheet for the AMD Am9513A System Timing Controller integrated circuit Advanced Micro Devices Inc data sheet This controller is used on the AT MIO 16X Copyright O Advanced Micro Devices Inc 1989 Reprinted with permission of copyright owner rights reserved Advanced Micro Devices Inc 1990 Data Book Personal Computer Products Processors Coprocessors
119. al Instruments Corporation 3 3 AT MIO 16X User Manual Theory of Operation Chapter 3 The interrupt control circuitry routes any enabled board level interrupt requests to the selected interrupt request line The interrupt requests are tristate output signals which allow the AT MIO 16X board to share the interrupt line with other devices Eight interrupt request lines are available for use by the AT MIO 16X IRQ3 IRQ4 IRQ5 IRQ7 IRQ10 IRQ11 12 and IRQ15 These interrupt levels are selectable from one of the registers in the AT MIO 16X register set Six different interrupts can be generated by the AT MIO 16X Each of the following cases is individually enabled and cleared When the ADC FIFO buffer is ready to be serviced e When data acquisition operation completes including an OVERFLOW or OVERRUN error e When a DMA terminal count pulse is received on DMA Channel A or DMA Channel B When the DAC FIFO buffer is ready to be serviced e When a DAC sequence completes including an UNDERFLOW error e When a falling edge signal is detected on the DAC update signal internal or external The DMA control circuitry generates DMA requests whenever an A D measurement is available from the ADC FIFO and when the DAC FIFO is ready to receive more data The DMA circuitry supports full PC I O channel 16 bit DMA transfers DMA Channels 5 6 and 7 of the PC I O channel are available for such transfers Channels 1 2 and 3 are availabl
120. annel data acquisition rate of the AT MIO 16X is 100 ksamples sec 10 usec sample period The AT MIO 16X may run as fast as 111 ksamples sec 9 usec sample period but with unspecified accuracy Multiple Channel Scanning Acquisition Rates When scanning among channels with different voltages the analog circuitry on the AT MIO 16X needs time to settle from one voltage to the next Because of its complex transient response the AT MIO 16X is not always able to settle to full 16 bit accuracy within 10 usec which is the shortest guaranteed sampling interval Table A 3 lists the typical worst case voltage settling times to within three different percentages of full scale range Table A 3 Typical Multiple Channel Scanning Settling Times Accuracy 0 0061 FSR 0 0015 FSR 0 00076 FSR 4 LSB 1 LSB 0 5 LSB Maximum per channel 100 ksamples sec 50 ksamples sec 25 ksamples sec acquisition rate When scanning among channels at various gains the settling times may further increase The settling times given in Table A 3 are for signals changing from and to voltages within in the same full scale range When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V signal is connected to Channel 0 and a 1 mV signal is connected to Channel 1 and suppose the PGIA is programmed to apply a gain of 1 to Channel 0 and a gain of 100 to Channel 1 When the multiple
121. ard without cable use with SH6850 cable assembly BNC 2080 BNC adapter board without cable use with SH6850 cable assembly Digital signal conditioning modules SSR Series 8 channel backplane mounting rack and 0 4 m SC 205X cable 5B Series signal conditioning backplane with 1 m cable for MIO 16 with 0 4 m cable for SC 205X Series 68 pin mating connector and shell Unpacking Chapter 1 776335 90 776336 00 776336 10 776336 01 776336 11 776336 02 776336 12 776358 90 776579 90 776290 18 776291 01 776291 11 776832 01 Your AT MIO 16X board is shipped in an antistatic package to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board take the following precautions e Touch the package to a metal part of your PC chassis before removing the board from the package e Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer AT MIO 16X User Manual 1 8 National Instruments Corporation Chapter 2 Configuration and Installation This chapter explains board configuration installation of the AT MIO 16X into the PC signal connections to the AT MIO 16X and cable considerations Figure 2 1 AT MIO 16X with 50 Pin I O Connector Parts Locato
122. ata transfers Maximum update rate Relative accuracy nonlinearity Differential nonlinearity Offset error After calibration Before calibration Temperature coefficient Gain error Using internal reference After calibration Before calibration Temperature coefficient Using external reference Temperature coefficient Onboard reference Temperature coefficient Long term stability Output voltage ranges software selectable National Instruments Corporation 2 16 bit multiplying DMA programmed I O or interrupts 100 ksamples sec 4 LSB maximum 2 LSB typical bipolar 8 LSB maximum 4 LSB typical unipolar 0 5 LSB maximum monotonic over temperature 305 uV maximum 8 15 mV maximum 50 uV C 0 0061 61 ppm maximum 0 182 1 820 ppm maximum 7 3 ppm C 0 15 1 500 ppm not adjustable 7 3 ppm C 2 ppm C maximum 15 ppm 4 1 000 hours 0 to 10 V unipolar mode 10 V bipolar mode A 5 AT MIO 16X User Manual Specifications Appendix A Current drive capability 5 mA short circuit protected 2 minimum load 1 000 pF maximum capacitive load Output settling time to 0 00396 FSR 10 usec for a 20 V step Output slew rate 5 V usec Output noise 50 uV rms DC to 1 MHz Output impedance 0 3 Q External reference input impedance 10 External reference input range 18 V protected to 30 V power on or off External reference bandwidth 3 dB DC to 300 kHz Explanation of Analo
123. ation A 3 nonreferenced single ended NRSE input configuration 2 8 definition table 2 7 differential connections 2 19 to 2 21 single ended connections for grounded signal sources 2 22 to 2 23 NRSE See nonreferenced single ended NRSE input AT MIO 16X User Manual offset error analog output circuitry 6 operating environment specifications A 7 operation of AT MIO 16X See theory of operation optional equipment 50 pin connector 1 5 to 1 6 68 pin connector 1 7 to 1 8 optional software 1 4 OUT GATE and SOURCE timing signals counter signal connections 2 30 to 2 34 RTSI bus interface circuitry 3 24 timing I O circuitry 3 21 to 3 22 lt 5 1 gt bit 4 55 signal definition 2 15 B 4 selecting internal update counter 5 23 OUT 2 signal definition 2 15 B 4 RTSI switch signal connections 5 28 selecting internal update counter 5 23 OUT3 signal 5 23 OUTS signal definition 2 15 B 5 RTSI switch signal connections 5 28 selecting internal update counter 5 23 OUTEN bit 5 29 OVERFLOW bit 4 20 5 5 5 16 OVERRUN bit 4 20 5 5 5 16 P PC I O channel interface circuitry block diagram 3 3 theory of operation 3 2 to 3 4 PGIA See AT MIO 16X PGIA physical specifications A 7 pin assignments Am9513A System Timing Controller C 6 I O connector 50 pin connector 2 12 B 1 68 pin connector 2 13 B 2 polarity analog output polarity selection 2 10 configuring input polarity and range
124. ation and 0 to 10 V for unipolar operation Bipolar or unipolar mode configuration is programmed on a per channel basis and is controlled through one of the registers in the AT MIO 16X register set Analog Input Configuration Inputs can be configured for differential or single ended signals on a per channel basis through a register in the AT MIO 16X register set In addition single ended inputs can be configured for referenced or nonreferenced signals In the differential configuration one of input Channels 0 through 7 is routed to the positive input of the PGIA and one of Channels 8 through 15 is routed to the negative input of the PGIA In the single ended configuration one of input Channels 0 through 15 is routed to the positive input of the PGIA The negative input of the PGIA in single ended mode is connected to either the input ground or the AI SENSE signal at the I O connector depending on the nature of the input signals PGIA The PGIA fulfills two purposes on the AT MIO 16X board It converts a differential input signal into a single ended signal with respect to the AT MIO 16X ground for input common mode signal rejection This conversion allows the input analog signal to be extracted from any common mode voltage or noise before being sampled and converted The PGIA also applies gain to the input signal amplifying an input analog signal before sampling and conversion to increase measurement resolution and accuracy Software selectabl
125. ational Instruments Corporation 5 17 AT MIO 16X User Manual Programming Chapter 5 Programming the Analog Output Circuitry The voltages at the analog output circuitry output pins pins DACO OUT and DACI OUT on the 16 I O connector are controlled by loading the DAC in the analog output channel with a 16 bit digital code The DAC is loaded by writing the digital code to the DACO and DACI Registers and then the converted output is available at the I O connector Writing to the DACO Register controls the voltage at the DACO OUT pin while writing to the DACI Register controls the voltage at the DAC1 OUT pin The analog output on pins DACO OUT and DACI OUT can be updated in one of three ways immediately when or DAC1 is written to when an active low pulse is detected on the TMRTRIG signal or when the DAC Update Register is strobed The TMRTRIG signal is either the EXTTMRTRIG signal from the I O connector or an internal signal from the output of Counters 1 2 3 or 5 depending on the state of the A4RCV bit in Command Register 2 The update method is selected through mode bits in the Command Register 4 In the waveform mode where a timer trigger generates an update for the DACs and a request for new data the DAC FIFO is used to buffer the incoming data to both of the DAC channels Because this FIFO is 2 048 values deep the last value buffered by the DAC FIFO could lag the output of the DAC channel by up to 2 048 times the
126. atus Register Group 4 4 to 4 22 AT MIO 16X User Manual Index Command Register 1 4 5 to 4 7 Command Register 2 4 8 to 4 10 5 26 5 31 Command Register 3 4 11 to 4 15 Command Register 4 4 16 to 4 18 Status Register 1 4 19 to 4 21 Status Register 2 4 22 5 26 DAC Event Strobe Register Group 4 41 to 4 44 DAC Clear Register 4 44 5 23 5 26 5 30 DAC Update Register 4 43 TMRREQ Clear Register 4 42 5 23 5 26 5 30 5 31 description format 4 3 Digital I O Register Group 4 56 to 4 58 Digital Input Register 4 57 5 26 Digital Output Register 4 58 5 26 General Event Strobe Register Group 4 45 to 4 51 Calibration DAC 0 Load Register 4 50 Calibration DAC 1 Load Register 4 51 DMA Channel Clear Register 4 46 DMATCA Clear Register 4 47 5 23 5 30 5 31 DMATCB Clear Register 4 48 5 23 5 30 5 31 External Strobe Register 4 49 programming considerations 5 1 register map 4 1 to 4 2 register sizes 4 2 RTSI Switch Register Group 4 59 to 4 61 RTSI Switch Shift Register 4 60 RTSI Switch Strobe Register 4 61 relative accuracy specification analog input A 3 analog output A 6 DIS bit 4 6 RSE See referenced single ended input RSI bit 4 60 RTSI bus interface circuitry illustration 3 23 to 3 24 RTSI bus trigger line programming 5 27 to 5 28 RTSI clock configuration CLKMODEB lt 1 0 gt bit for selecting 4 16 timebase selection 2 10 to 2 11 RTSI latch 3 15 RTSI switch control patter
127. bWindows Version Other Products e Computer Make and Model e Microprocessor e Clock Frequency e of Video Board Installed e DOS Version Programming Language Programming Language Version e Other Boards in System e Base I O Address of Other Boards DMA Channels of Other Boards e Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title AT MIO 16X Manual Edition Date April 1994 Part Number 320640 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone ___ Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53 02 MS 53 02 Austin TX 78730 5039 512 794 5678 Glossary i degrees Q ohms percent A amperes ADC analog to digital converter AWG American Wire Gauge BCD binary coded decimal C Celsius CMOS complementary metal oxide semiconductor DAC digital to analog converter dB decibels DIFF differential DIP dual inline package DMA direct memory access DNL differential nonlinearity
128. before contacting National Instruments helps us help you better and faster National Instruments provides comprehensive technical assistance around the world In the U S and Canada applications engineers are available Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 328 2203 512 794 5678 Branch Offices Phone Number Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 00 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Netherlands 03480 33466 Norway 32 848400 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 U K 0635 523545 National Instruments Corporation D 1 Fax Number 03 879 9179 0662 437010 19 02 757 03 11 45767111 90 502 2930 1 48142414 089 714 60 35 02 48301915 03 3788 1923 03480 30673 32 848600 91 640 0533 08 730 43 70 056 27 00 25 0635 523154 AT MIO 16X User Manual Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions
129. bit 4 9 environmental noise minimizing 2 34 to 2 35 equipment optional 50 pin connector 1 5 to 1 6 68 pin connector 1 7 to 1 8 event counting event counting application with external switch gating illustration 2 31 programming 2 30 to 2 31 EXTCONV signal definition 2 15 B 4 generating single conversions 5 5 programming sample counter s 5 12 programming sample interval counter 5 11 RTSI switch 3 24 timing connections 2 28 updating DACs 5 23 External Strobe Register 4 49 EXTGATE signal data acquisition timing connections 2 29 definition 2 15 B 4 EXTREF signal analog output signal connections 2 24 definition 2 14 B 3 EXTREFDACO bit 4 9 EXTREFDACI bit 4 9 EXTSTROBE signal definition 2 15 B 4 digital I O circuitry 3 20 AT MIO 16X User Manual timing connections 2 27 EXTTMRTRIG signal DAC waveform timing circuitry 3 16 definition 2 15 B 4 servicing update requests 5 26 timing connections 2 29 to 2 30 EXTTRIG signal applying a trigger 5 15 definition 2 15 B 4 programming sample interval counter 5 11 RTSI switch 3 24 timing connections 2 28 to 2 29 EXTTRIG DIS bit 4 18 F field wiring considerations 2 34 to 2 35 FIFO continuous cyclic waveform generation 3 17 to 3 18 FIFO DAC bit 4 18 FIFO programmed cyclic waveform generation 3 18 FIFO pulsed waveform generation 3 18 to 3 19 floating signal sources description of 2 17 differential connections 2 19 to 2 21
130. c Waveform Generation In addition to allowing better performance the cyclic mode provides greater flexibility Because the hardware is in full control of the buffer it can start stop and restart the generation of the waveform as programmed An example of this added functionality is shown in Figure 3 13 DACFIFORT CYCLICSTOP m Figure 3 13 FIFO Cyclic Waveform Generation with Disable In this example the entire buffer fits within the DAC FIFO After the waveform is initiated it cycles and recycles through the buffer The end of the buffer is indicated by the DACFIFORT signal or DAC FIFO Retransmit This is a signal generated by the hardware in cyclic mode to trigger the DAC FIFO to retransmit its buffer The CYCLICSTOP signal is programmable through a register in the AT MIO 16X register set If this bit is cleared the DAC FIFO hardware National Instruments Corporation 3 17 AT MIO 16X User Manual Theory of Operation Chapter 3 runs ad infinitum or until the timer update pulse triggering is disabled If necessary the waveform can be stopped by disabling the timer trigger The result of this action is to leave the DAC at some unknown value for example the last updated value The advantage of the CYCLICSTOP control signal is that DAC updating ends gracefully When this signal is set the waveform ends after it encounters the next retransmit signal Thus it will always end in a known state at the end of the buffer
131. cal coupling is a function of how much the electric field differs between the two conductors If AI GND is used as the signal National Instruments Corporation 2 21 AT MIO 16X User Manual Configuration and Installation Chapter 2 reference Channels 0 and 8 are the quietest and Channels 7 and 15 are the noisiest AI GND is on pins 1 and 2 which are very close to pins 3 and 4 which are Channels 0 and 1 On the other hand Channels 7 and 15 are on pins 17 and 18 which are the farthest analog inputs from AI GND The sensitivities to noise of the other channels in the middle are between those of Channels 0 and 15 and vary according to their distance from AI GND If AI SENSE is used as a reference instead of AI GND the sensitivity to noise still varies among the channels but in this case according to their distance from AI SENSE pin 19 so Channel 15 is the least sensitive and Channel 0 is the most sensitive Single Ended Connections for Floating Signal Sources RSE Configuration Figure 2 9 shows how to connect a floating signal source to an AT MIO 16X board configured for single ended input The AT MIO 16X analog input circuitry must be configured for RSE input to make these types of connections Configuration instructions are included in Chapter 4 Register Map and Descriptions Nonreferenced or Floating Signal Source Input Multiplexer Measured AISENSE M Voltage AI GND 16 Board in the RSE Input Configuratio
132. cal isolator outputs and isolation amplifiers An instrument or device that provides an isolated output falls into the floating signal source category The ground reference of a floating signal must be tied to the AT MIO 16X analog input ground in order to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the AT MIO 16X board assuming that the PC AT is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but can be much higher if power distribution circuits are not properly connected If grounded signal source is improperly measured this difference may show up as an error in the measurement The following connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal National Instruments Corporation 2 17 AT MIO 16X User Manual Configuration and Installation Chapter 2 Input Configurations The AT MIO 16X can be configured f
133. ccepted by DAC 1 If DACIDSP is cleared the serial RTSI link is disabled DAC 0 DSP Link Enable This bit controls the serial link from the AT DSP2200 to DAC 0 of the analog output section If DACIDSP is set then the serial link is enabled Data is sent from the AT DSP2200 over the RTSI bus and is accepted by DAC 0 If DACIDSP is cleared the serial RTSI link is disabled DAC Mode Select These bits control the mode used for writing to and updating the DACs DACMB3 is used to select the number of reads from the DAC FIFO per update signal If DACMB3 is clear there will be only one read of the DAC FIFO per update If DACMB3 is set the circuitry will determine whether to perform one read or two reads from the DAC FIFO depending on the data in the FIFO See Table 4 6 for available modes and bit patterns Table 4 6 Analog Output Waveform Modes Waveform Mode Mode Description Single update with no timed interrupts Single update with timed interrupts DMA access through DAC FIFO with single requesting 1 access through DAC FIFO with half flag requesting 1 1 FIFO continuous waveform generation buffer in DAC FIFO X 1 Programmed cycle waveform generation Counter 1 stops after N cycles en ea lt EA DAC Update Gate This bit controls the update circuitry for the DACS in the delayed update mode If DACGATE is set updating of the DACS is inhibited Values can be directly written to the DAC b
134. ce of 10 V or to the external reference signal connected to the EXTREF pin on the I O connector This signal applied to EXTREF must be between 18 and 18 V Both channels need not be configured for the same mode Analog Output Polarity Selection Each analog output channel can be configured for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vref at the analog output A bipolar configuration has a range of Vref to Vref at the analog output Vref is the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an externally supplied reference between 18 and 18 V Both channels need not be configured for the same range Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two s complement format In two s complement mode data values written to the analog output channel range from 32 768 to 432 767 decimal 8000 to 7FFF hex If unipolar range is selected data is interpreted in straight binary format In straight binary mode data values written to the analog output channel range from 0 to 65 535 decimal 0 to FFFF hex Digital I O Configuration The AT MIO 16X contains eight lines of digital I O for general purpose use The eight digital I O lines supplied are configured as two 4 bit ports Each port can be individually configured through programming of a register in the board register set as either i
135. controls the 4 bit digital output port A If DIOPAEN is set the Digital Output Register drives the DIO lt 4 1 gt digital lines at the I O connector If DIOPAEN is cleared the Digital Output Register drivers are set to a high impedance state therefore an external device can drive the DIO lt 4 1 gt digital lines National Instruments Corporation 4 11 AT MIO 16X User Manual Register Map and Descriptions Bit 12 11 10 Name DMATCINT DACCMPLINT DAQCMPLINT I O INT DMACHA DMACHB AT MIO 16X User Manual Chapter 4 Description continued DMA Terminal Count Interrupt Enable This bit controls the generation of an interrupt when a DMA terminal count pulse is received from the DMA controller in the PC AT If DMATCINT is set an interrupt request is generated when the DMA controller transfers the final value on the primary DMA channel Channel A or the secondary DMA channel Channel B The interrupt request is serviced by strobing the appropriate DMATC Clear Register When DMATCINT is cleared no DMA terminal count interrupts are generated DAC Complete Interrupt Enable This bit controls the generation of an interrupt when a DAC sequence completes If DACCMPLINT is set an interrupt request is generated when the sequence completes The interrupt request is serviced by strobing the TMRREQ Clear or DAC Clear Register When DACCMPLINT is cleared completion of a sequence does not generate an interrupt A D
136. ction If this bit is set the reference used for DAC 0 is the external reference voltage from the I O connector If this bit is cleared the internal 10 Vref is used for the DAC 0 reference EISA Computer DMA This bit controls the type of DMA transfer from the ADC FIFO on an EISA computer If EISA DMA is clear single transfer DMA mode is used If EISA DMA is set demand mode DMA is used This bit should only be set if the AT MIO 16X is installed in an EISA type computer Reserved This bit must always be set to zero DMA Channel B Select These bits select the secondary DMA channel for use by the AT MIO 16X See Table 4 2 DMA Channel A Select These bits select the primary DMA channel for use by the AT MIO 16X See Table 4 2 4 9 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Table 4 2 DMA Channel Selection Bit Pattern Effect Bit Pattern Effect Primary DMA Channel Selected A Secondary DMA Channel Selected B DMA Channel 0 1 DMA Channel 1 DMA Channel 2 1 DMA Channel 3 No effect DMA Channel 5 DMA Channel 6 DMA Channel 7 UCI L BMA Came Po Channel 9 3 Gamers 9 3 1 L o 1 9 1 LLL LE Cramers 1 PP N 2 5 lt gt EX ES EX macnas
137. d as follows e Chapter 1 Introduction describes the AT MIO 16X lists the contents of your AT MIO 16X kit the optional software and optional equipment and explains how to unpack the AT MIO 16X e Chapter 2 Configuration and Installation explains board configuration installation of the AT MIO 16X into the PC signal connections to the AT MIO 16X and cable considerations Chapter 3 Theory of Operation contains a functional overview of the AT MIO 16X and explains the operation of each functional unit making up the AT MIO 16X e Chapter 4 Register Map and Descriptions describes in detail the address and function of each of the AT MIO 16X control and status registers Chapter 5 Programming contains programming instructions for operating the circuitry on the AT MIO 16X e Chapter 6 Calibration Procedures discusses the calibration resources and procedures for the AT MIO 16X analog input and analog output circuitry e Appendix A Specifications lists the specifications of the AT MIO 16X e Appendix B O Connector describes the pinout and signal names for AT MIO 16X 50 pin I O connector and the 68 pin I O connector Appendix C AMD Am9513A Data Sheet contains the manufacturer data sheet for the AMD Am9513A System Timing Controller integrated circuit Advanced Micro Devices Inc This controller is used on the AT MIO 16X Appendix D Customer Communication contains forms you can use to request help from Na
138. data acquisition timing to be controlled over the RTSI bus as well as externally and allow the AT MIO 16X and the I O connector to send timing signals to other AT boards connected to the RTSI bus AT MIO 16X User Manual 3 24 National Instruments Corporation Chapter 4 Register Map and Descriptions This chapter describes in detail the address and function of each of the AT MIO 16X control and status registers Note If you plan to use a programming software package such as NI DAQ or LabWindows with your AT MIO 16X board you need not read this chapter However you will gain added insight into your AT MIO 16X board by reading this chapter Register Map The register map for the AT MIO 16X is shown in Table 4 1 This table gives the register name the register offset address the type of the register read only write only or read and write and the size of the register in bits The actual register address is obtained by adding the appropriate register offset to the I O base address of the AT MIO 16X Registers are grouped in the table by function Each register group is introduced in the order shown in Table 4 1 then described in detail including a bit by bit description Table 4 1 AT MIO 16X Register Map Register Name Offset Address Type Size Hex Configuration and Status Register Group Command Register 1 Write only Command Register 2 Write only Command Register 3 Write only Command Register 4 Write only Status Register 1
139. ddress Base address 19 hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Cancels any data acquisition operation in progress empties ADC FIFO clears the OVERRUN bit in Status Register 1 clears the OVERFLOW bit in Status Register 1 clears the DAQCOMP bit in Status Register 1 clears any pending ADC interrupt and resets the configuration memory to the initial value no values are lost Note the channel configuration memory contains valid information and no new values are to be added before restarting the data acquisition sequence the CONFIGMEMLD Register should be strobed following a DAQ Clear strobe National Instruments Corporation 4 37 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 DAQ Start Register Accessing the DAQ Start Register location initiates a multiple A D conversion data acquisition operation Note Several other pieces of AT MIO 16X circuitry must be set up before a data acquisition run can occur See Chapter 5 Programming Address Base address 1D hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Initiates a programmed data acquisition sequence Note Multiple A D conversion data acquisition operations can be initiated in one of three ways by accessing the Start DAQ Register or by detecting an active low signal on either the EXTTRIG or the RTSITRIG signal To trigger the board with th
140. ding on the application If single channels are to be monitored on an ad hoc basis then the single conversion mode can be used If a number of consecutive conversions on any one given channel are required the single channel data acquisition mode should be used If more than one channel needs to be monitored with multiple conversions per channel the scanning data acquisition mode should be used This mode scans through a programmed number of channels each having its own gain mode and range setting The channels are scanned in a round robin fashion separated in time by the programmed sample interval The final mode is the interval scanning mode This mode should be used if more than one channel needs to be monitored but not scanned at full speed Interval scanning sequences through the scan list with each channel conversion separated in time by the programmed sample interval then waits a scan interval before rescanning the list of channels The programming of each of these acquisition modes is described in the following sections Single Conversions Using the SCON VERT or EXTCONV Signal Programming the analog input circuitry to obtain a single A D conversion involves the following sequence of steps listed in Figure 5 2 Clear the A D circuitry Select a single analog input channel gain mode and range Initiate a single A D conversion Read the A D conversion result Figure 5 2 Single Conversion Programming AT MIO 16X Use
141. e without cable SC 2050 cable adapter board for signal conditioning with 50 conductor cable 0 5 m 1 0m SC 2060 optically isolated digital input board with 26 conductor cable 0 2m 0 4 m 776164 01 716164 02 716249 02 776249 03 776249 04 776249 05 776572 00 776572 20 776572 21 776572 40 776572 80 776572 81 776572 60 776572 61 776572 62 776572 63 776570 0x 776571 0 776366 02 776366 05 776366 10 776366 20 776366 90 776335 00 776335 10 776336 00 776336 10 continues AT MIO 16X User Manual Introduction Chapter 1 Equipment Part Number SC 2061 optically isolated digital output board with 26 conductor cable 0 2m 776336 01 04 776336 11 5 2062 electromechanical relay digital control board with 26 conductor cable 0 2m 776336 02 0 4 776336 12 SC 2070 general purpose termination breadboard with 50 conductor cable 0 5 m 776358 00 1 0m 776358 10 BNC 2080 BNC adapter board with 50 conductor cable 0 5 m 776579 05 1 0m 776579 10 Digital signal conditioning modules SSR Series mounting rack and 8 channel backplanewith 0 4 m SC 205X 776290 18 cable 5B Series signal conditioning backplane with 1 m cable for MIO 16 716291 01 with 0 4 m cable for SC 205X Series 716291 11 The AT MIO 16X I O connector is a 50 pin male ribbon cable header The manufacturer part numbers for this header are as follows Electronic Products Division 3M part number 3596 5002 e T amp B Ansley Corporat
142. e Start DAQ Register the RTSITRIG signal in Command Register 1 must be cleared In addition either the EXTTRIG signal should be unasserted or the DIS signal in Command Register 4 must be set Otherwise strobing the Start DAQ Register has no effect AT MIO 16X User Manual 4 56 National Instruments Corporation Chapter 4 Register Map and Descriptions Single Conversion Register Accessing the Single Conversion Register location initiates a single A D conversion Address Base address 1D hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Initiates a single ADC conversion Note A D conversions can be initiated in one of two ways by accessing the Single Conversion Register or by applying an active low signal on the EXTCONV signal The EXTCONV signal is connected to the I O connector to OUT3 of Am9513A and to the AO pin of the RTSI bus switch If the Single Conversion Register is to initiate A D conversions all other sources of conversion should be inhibited to avoid an OVERRUN condition National Instruments Corporation 4 59 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 ADC Calibration Register Accessing the ADC Calibration Register location initiates an ADC calibration procedure This register should be strobed after power up to assure the ADC is in a calibrated state Address Base address 1F hex Type Write only Word Size 8 bi
143. e for 16 bit transfers on EISA computers only and not on PC AT and compatible computers With the DMA circuitry either single channel transfer mode or dual channel transfer mode can be selected for DMA transfer These DMA channels are selectable from one of the registers in the AT MIO 16X register set Analog Input and Data Acquisition Circuitry The AT MIO 16X handles 16 channels of analog input with software programmable configuration and 16 bit A D conversion In addition the AT MIO 16X contains data acquisition configuration for automatic timing of multiple A D conversions and includes advanced options such as external triggering gating and clocking Figure 3 3 shows a block diagram of the analog input and data acquisition circuitry AT MIO 16X User Manual 3 4 National Instruments Corporation Theory of Operation Chapter 3 seuss Joul I91uno Sum uonismboy X ID Bed x 319AUO7 IVA ANOO uonoo eg au a v perdi 9I 570035000 INO3dHH SOYOUIMS uong 9poJA soyd 19881 JOULE euro xqq 319AUO LNOOXNN 2 DIV SIV AsIG as 103290100 xDISILLXH ANOOLX N IONVOS TIHOV TIHOV ITHOV 6HOV 8HOV ASNAS IV LHOV 9HOV SHOV VHOV CHOV THOV OHOV Figure 3 3 Analog Input and Data Acquisition Circuitry Block Diagram AT MIO 16X User Manual 3 5 National In
144. e gains of 1 2 5 10 20 50 and 100 are available through the AT MIO 16X PGIA on a per channel basis AT MIO 16X User Manual 3 6 National Instruments Corporation Chapter 3 Theory of Operation ADC FIFO Buffer When an A D conversion is complete the ADC circuitry shifts the result into the ADC FIFO buffer The FIFO buffer is 16 bits wide and 512 words deep This FIFO serves as a buffer to the ADC and is beneficial for two reasons Any time an A D conversion is complete the value is saved in the FIFO buffer for later reading and the ADC is free to start a new conversion Secondly the FIFO can collect up to 512 A D conversion values before any information is lost thus software or DMA has extra time 512 times the sample interval to catch up with the hardware If more than 512 values are stored in the FIFO without the FIFO being read from an error condition called FIFO overflow occurs and A D conversion information is lost When the ADC FIFO contains a single A D conversion value or more it can generate a DMA or interrupt request to be serviced Analog Input Calibration Measurement reliability 18 assured through the use of the onboard calibration circuitry of the AT MIO 16X This circuitry uses a stable internal 5 VDC reference that is measured at the factory against a higher accuracy reference then its value is permanently stored in the EEPROM on the AT MIO 16X With this stored reference value the AT MIO 16X board can be recalib
145. e on the AT MIO 16X National Instruments Corporation 4 55 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Digital I O Register Group The two registers making up the Digital I O Register Group monitor and control the AT MIO 16X digital I O lines The Digital Input Register returns the digital state of the eight digital I O lines A pattern written to the Digital Output Register is driven onto the digital I O lines when the digital output drivers are enabled see the description for Command Register 2 Bit descriptions of the two registers making up the Digital I O Register Group are given on the following pages AT MIO 16X User Manual 4 56 National Instruments Corporation Chapter 4 Register Map and Descriptions Digital Input Register The Digital Input Register when read returns the logic state of the eight AT MIO 16X digital I O lines Address Base address 1C hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp MSB 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIOI BDIOO ADIO3 ADIO2 ADIO ADIOO LSB Bit Name Description 15 8 X Don t care bits 7 4 BDIO lt 3 0 gt These four bits represent the logic state of the digital lines BDIO lt 3 0 gt 3 0 ADIO lt 3 0 gt These four bits represent the logic state of the digital lines ADIO lt 3 0 gt National Instruments Corporation 4 57 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Digital Output Register Wri
146. e the previously written value to the DAC In the posted update mode the DAC FIFO is used to buffer the data Requests are generated either when the FIFO is not full or when the FIFO is less than half full One of these two signals generates the TMRREQ signal In the example above requesting is generated when the FIFO is not full Because each update removes a value from the DAC FIFO each update also results in the TMRREQ signal being asserted This sequence of events continues until the output buffer data is exhausted There are effectively two different modes in which to operate the DAC FIFOs in posted update mode Data flows in and out at equal rates or data as initialized in the FIFO and once updating begins the data is cycled through when the end of the FIFO buffer is encountered If waveform cycles involving more than 2 048 values are required data must continuously flow into and out of the FIFO buffer to be replenished If waveform cycles of less than 2 048 points are required the data can be transferred to the DAC FIFO only once where it can be cycled through to generate a continuous waveform This mode removes the burden on the PC to continuously transfer new data to the DAC FIFO buffer allowing it to perform other operations In both cases waveforms like the one shown in Figure 3 12 can be realized AT MIO 16X User Manual 3 16 National Instruments Corporation Chapter 3 Theory of Operation Figure 3 12 Analog Output Waveform C
147. ecessary to control and monitor the operation of the AT MIO 16X multiple function circuitry The PC I O channel has 24 address lines the AT MIO 16X uses 10 of these lines to decode the board address Therefore the board address range is 000 to 3FF hex SA5 through SA9 are used to generate the board enable signal SAO through SA4 are used to select individual onboard registers The address decoding circuitry generates the register select signals that identify which AT MIO 16X register is being accessed The AT MIO 16X is factory configured for a base address of 220 hex With this base address all of the registers on the board will fall into the address range of 220 hex to 23F hex If this address range conflicts with any other equipment in your PC you must change the base address of the AT MIO 16X or of the other device See Chapter 2 Configuration and Installation for more information The PC I O channel interface timing signals are used to generate read and write signals and to define the transfer cycle size A transfer cycle can be either an 8 bit or a 16 bit data I O operation The AT MIO 16X returns signals to the PC I O channel to indicate when the board has been accessed when the board is ready for another transfer and the data bit size of the current I O transfer Particular attention must be paid to the AT MIO 16X register sizes An 8 bit access to a 16 bit location and vice versa is invalid and will cause sporadic operation Nation
148. ed OUT The Am9513A counters are numbered 1 through 5 and their GATE SOURCE and OUT pins are labeled GATE N SOURCE N and OUT N where N is the counter number For counting operations the counters can be programmed to use any of the five internal timebases any of the five GATE and five SOURCE inputs to the Am9513A and the output of the previous counter Counter 4 uses Counter 3 output and so on A counter can be configured to count either falling or rising edges of the selected input The counter GATE input allows counter operation to be gated Once a counter is configured for an operation through software a signal at the GATE input can be used to start and stop counter operation The five gating modes available with the Am9513A are as follows No gating Level gating active high Level gating active low e Low to high edge gating e High to low edge gating National Instruments Corporation 3 21 AT MIO 16X User Manual Theory of Operation Chapter 3 A counter can also be active high level gated by a signal at GATE N 1 and GATE N 1 where N is the counter number The counter generates timing signals at its OUT output pin The OUT output pin can also be set to a high impedance state or a grounded output state The counters generate two types of output signals during counter operation terminal count pulse output and terminal count toggle output Terminal count is often referred to as TC A counter reaches TC when it counts up or
149. ed in Appendix C AMD Am9513A Data Sheet Bit descriptions for the Am9513A Counter Timer Register Group registers are given in the following pages AT MIO 16X User Manual 4 52 National Instruments Corporation Chapter 4 Register Map and Descriptions Am9513A Data Register With the Am9513A Data Register any of the 18 internal registers of the Am9513A can be written to or read from The Am9513A Command Register must be written to in order to select the register to be accessed by the Am9513A Data Register The internal registers accessed by the Am9513A Data Register are as follows e Counter Mode Registers for Counters 1 2 3 4 and 5 Counter Load Registers for Counters 1 2 3 4 and 5 e Counter Hold Registers for Counters 1 2 3 4 and 5 The Master Mode Register The Compare Registers for Counters 1 and 2 these registers are 16 bit registers Bit descriptions for each of these registers are included in Appendix C AMD Am9513A Data Sheet Address Base address 14 hex Type Read and write Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 0 D lt 15 0 gt These 16 bits are loaded into the Am9513A Internal Register currently selected See Appendix C AMD Am9513A Data Sheet for the detailed bit descriptions of the 18 registers accessed through the Am9513A Data Register National Instruments Corporation 4 53 AT MIO 16X User Manual Register Map and Descriptio
150. eive another clock signal from another AT board connected to the RTSI bus BRDCLK is the system clock used by the AT MIO 16X Bits in a command register in the AT MIO 16X register set control how these clock signals are routed National Instruments Corporation 3 23 AT MIO 16X User Manual Theory of Operation Chapter 3 The RTSI switch is a National Instruments custom integrated circuit that acts as a 7x7 crossbar switch Pins B 6 0 are connected to the seven RTSI bus trigger lines Pins A 6 0 are connected to seven signals on the board The RTSI switch can drive any of the signals at pins A 6 0 onto any one or more of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto one or more of the pins lt 6 0 gt This capability provides a completely flexible signal interconnection scheme for any AT Series board sharing the RTSI bus The RTSI switch is programmed via its chip select and data inputs On the AT MIO 16X board nine signals are connected to pins A 6 0 of the RTSI switch with the aid of additional drivers The signals OUTI OUT2 SOURCES OUTS and FOUT are shared with the AT MIO 16X I O connector and Am9513A Counter Timer The EXTCONV and EXTTRIG signals are shared with the I O connector and the data acquisition timing circuitry The TMRTRIG signal is used to update the two DACS on the AT MIO 16X These onboard interconnections allow AT MIO 16X general purpose and
151. els 2 8 definition table 2 7 RSE input 16 channels 2 8 definition table 2 7 theory of operation 3 6 Analog Input Register Group 4 23 to 4 29 ADC FIFO Register 4 24 to 4 25 5 5 5 16 5 31 CONFIGMEM Register 4 26 to 4 29 5 10 5 11 register map 4 1 analog input signal connections AT MIO 16X PGIA 2 16 to 2 17 pin descriptions 2 16 to 2 17 warning against exceeding input ranges 2 16 Index 2 National Instruments Corporation analog input specifications linear errors 2 to 3 equivalent gain errors in 16 bit systems table A 3 equivalent offset errors in 16 bit systems table A 2 gain error A 2 postgain offset error A 2 pregain offset error A 2 list of specifications A 1 to A 2 noise 4 nonlinear errors 3 to 4 differential nonlinearity A 4 relative accuracy A 3 typical relative accuracy of analog input circuitry illustration A 3 system noise A 4 analog output circuitry 3 12 to 3 14 block diagram 3 13 calibration 3 14 6 7 clearing 5 23 configuration 3 14 description 3 13 programming 5 18 analog output configuration 2 10 output polarity selection 2 10 output reference selection 2 10 theory of operation 3 14 Analog Output Register Group 4 30 to 4 33 analog output voltage versus digital code bipolar mode table 4 31 unipolar mode table 4 30 DACO Register 4 32 5 18 DACI Register 4 33 5 18 formula for voltage output versus digital code 4 30 to 4 31 overvie
152. equence This sequence of events continues ad infinitum and does not stop until the update signal is removed or the DAC circuitry is cleared This sequence requires that the GATE2SEL signal in addition to the SRC3SEL signal be set in Command Register 4 This allows Counter 1 to count the buffer retransmit signals from the source line of Counter 3 while Counter 2 is gated by the signal at its own gate pin Waveform Generation Programming Functions This section provides a detailed explanation of the programming functions necessary to generate synchronously timed analog output waveforms Clearing the Analog Output Circuitry This involves clearing the TMRREQ DACCOMP and DMATCA or DMATCB bits in the Status Register To do this access the TMRREQ Clear DAC Clear and if necessary the DMATCA or DMATCB Clear registers Selecting the Internal Update Counter Select the desired signal at the RTSI switch to be used for updating the DACs OUTI OUT2 OUTS available as EXTCONV and OUTS are available for updating To route these update signals the A side pin of the RTSI switch must be internally routed to the B side or trigger side Select a trigger line that is not being used The signal must be routed from the selected B side trigger line to the A4 pin on the RTSI switch of this is done in one programming sequence by shifting a 56 bit value to the RTSI switch See the RTSI Bus Trigger Line Programming Considerations section later in this c
153. er is read Table 4 7 shows input voltage versus A D conversion value for straight binary format and 0 to 10 V input range Table 4 8 shows input voltage versus A D conversion value for two s complement format for 10 to 10 V input range AT MIO 16X User Manual 4 24 National Instruments Corporation Chapter 4 Register Map and Descriptions Table 4 7 Straight Binary Mode A D Conversion Values Input Voltage A D Conversion Result Gain 1 Range 0 to 10 V OV 152 6 2 5 V 5 0 V 75 9 999847 V To convert from the ADC FIFO value to the input voltage measured use the following formula V ADC reading 10 V 65 536 Gain Table 4 8 Two s Complement Mode A D Conversion Values A D Conversion Result Range 10 to 10 V Gain 1 Input Voltage 10 0 V 9 999695 V 9 999605 V To convert from the ADC FIFO value to the input voltage measured use the following formula V ADC reading 10 V 32 768 Gain National Instruments Corporation 4 25 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 CONFIGMEM Register The CONFIGMEM Register controls the input channel selection multiplexers gain range and mode settings and can contain up to 512 channel configuration settings for use in scanning sequences Address Base address 08 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 CHANSELI CHANSELO CH GAIN2 CH GAIN CH GAINO CH
154. er set EXTGATE Signal EXTGATE is an input signal used for hardware gating EXTGATE controls A D conversion pulses If EXTGATE is low no A D conversion pulses occur from EXTCONV or the sample interval counter If EXTGATE is high conversions take place if programmed and otherwise enabled EXTTMRTRIG Signal The analog output DACs on the AT MIO 16X can be updated using either internal or external signals in posted update mode The DACS can be updated externally by using the EXTTMRTRIG signal from the I O connector This signal updates the DACs when A4RCV is disabled and the appropriate DAC waveform mode is programmed through one of the registers in the AT MIO 16X register set The analog output DACS are updated by the high to low edge of the applied pulse Figure 2 16 shows the timing requirements for the EXTTMRTRIG signal National Instruments Corporation 2 29 AT MIO 16X User Manual Configuration and Installation Chapter 2 tw 50 ns minimum DACs update 100 ns from this point Figure 2 16 EXTTMRTRIG Signal Timing The minimum pulse width allowed is 50 ns The DACs are updated within 100 ns of the high to low edge There is no maximum pulse width limitation EXTTMRTRIG should be high for at least 50 ns before going low The EXTTMRTRIG signal is one load and is pulled up to 5 V through a 10 kQ resistor Counter Signal Connections The general purpose timing signals include the GATE and OUT signals for the
155. eral description C 2 hardware retriggering C 29 hold register C 11 initializing 5 2 to 5 3 input circuitry C 7 interface considerations C 7 interface signal summary C 7 load data pointer commands C 10 load register C 11 master mode control options C 11 to C 13 master mode register bit assignments C 12 mode waveforms C 15 to C 26 ordering information C 3 to C 5 output control C 26 to C 28 output control logic C 27 pin description C 6 AT MIO 16X User Manual prefetch circuit C 10 programming 5 26 to 5 27 register access C 9 specifications C 33 to C 37 status register C 10 to C 11 switching test circuit C 37 switching waveforms C 38 TC terminal count C 28 TEHWH TGVWH timing diagram C 40 timing I O circuitry 3 20 to 3 23 troubleshooting C 39 analog data acquisition rates multiple channel scanning rates A 4 to A 5 single channel rates A 4 analog input calibration 6 6 analog input circuitry A D converter 3 7 ADC FIFO buffer 3 7 AT MIO 16X PGIA 3 6 block diagram 3 5 calibration 3 7 clearing 5 10 input configuration 3 6 input multiplexers 3 6 programming 5 4 single conversions using SCONVERT or EXTCONV signal 5 4 theory of operation 3 6 to 3 7 analog input configuration 2 6 to 2 9 available input configurations for AT MIO 16X table 2 7 DIFF input eight channels 2 7 definition table 2 7 input mode 2 6 to 2 9 input polarity and range 2 9 NRSE input 16 chann
156. erence AT MIO 16X User Manual 2 34 National Instruments Corporation Chapter 2 Configuration and Installation e Route signals to the AT MIO 16X carefully Keep cabling away from noise sources most common noise source in a PC data acquisition system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to the AT MIO 16X Separate AT MIO 16X signal lines from high current or high voltage lines These lines are capable of inducing currents in or voltages on the AT MIO 16X signal lines if they run in parallel paths at a close distance Reduce the magnetic coupling between lines by separating them by a reasonable distance if they run in parallel or by running the lines at right angles to each other e Do not run AT MIO 16X signal lines through conduits that also contain power lines e Protect AT MIO 16X signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running the AT MIO 16X signal lines through special metal conduits Cabling Considerations for the AT MIO 16X with 50 Pin I O Connector National Instruments has a cable termination accessory the CB 50 for use with the AT MIO 16X board This kit includes a terminated 50 conductor flat ribbon cable and a connector block Signal I O leads can be attached to screw terminals on the connector block and thereby connected to the AT M
157. erning board operation Board operation sometimes varies depending on the revision or subrevision of the board 0110 16 384 0101 8 192 Reserved 0100 4 096 CONFIGMEM Length 0010 1 024 0001 512 0000 256 Figure 6 3 Configuration Memory Depth Field National Instruments Corporation 6 3 AT MIO 16X User Manual Calibration Procedures Chapter 6 If the Configuration Memory Depth Field contains the binary value XXXX0001 where X indicates don t care bits this signifies that the accessed AT MIO 16X board contains a configuration memory with a depth of 512 Thus the configuration memory can hold up to 512 configuration values for channel gain mode and range settings 0110 2 16 384 0101 8 192 0100 4 096 0110 2 16 384 0101 8 192 0100 4 096 0011 2 048 FIFO Length DAC FIFO Length Sx 0011 2 2 048 0010 1 024 0010 1 024 0001 512 0001 512 0000 256 DT 0000 256 7 6 5 4 312 1 MSB LSB Figure 6 4 ADC and DAC FIFO Depth Field If the ADC and DAC FIFO Depth Field contains the binary value 00010011 then the AT MIO 16X board that was accessed contains an ADC FIFO buffer of depth 512 and a DAC FIFO buffer of depth 2 048 This information is extremely useful in determining how many values to read from the ADC FIFO or write to the DAC FIFO when a half full interrupt is generated For example if it is known that the ADC FIFO is 512 values deep and a half full i
158. ersions are automatically halted irrespective of the EXTCONV signal when the sample counter reaches zero National Instruments Corporation 5 11 AT MIO 16X User Manual Programming Chapter 5 To program the sample interval counter for internal conversion signals use the following programming sequence All writes are 16 bit operations values given are hexadecimal 1 Write FF03 to the Am9513A Command Register to select the Counter 3 Mode Register 2 Write the mode value to the Am9513A Data Register to store the Counter 3 mode value Am9513A counter mode information can be found in Appendix C AMD Am9513A Data Sheet Use one of the following mode values 8225 Selects 5 MHz clock from SOURCE pin 8B25 Selects 1 MHz clock 8 25 Selects 100 kHz clock 8D25 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum Write FFOB to the Am9513A Command Register to select the Counter 3 Load Register Write 2 to the Am9513A Data Register to store the Counter 3 load value Write FF44 to the Am9513A Command Register to load Counter 3 gv we m d Write FFF3 to the Am9513A Command Register to step Counter 3 down to 1 7 Write the desired sample interval to the Am9513A Data Register to store the Counter 3 load value e If the sample interval is between 2 and FFFF 65 535 decimal write the sample i
159. eu eid ie 3 1 PC I O Channel Interface Circuitry lu Ace eee 3 2 Analog Input and Data Acquisition Circuitry ss 3 4 Analog Input COLE eec ne rag a DORMI NIC AN IPC DR ER esp 3 6 AJD COBVetlet icone ne 3 6 Analog Input Multplexets eee as 3 6 Analog Input Configuration eee BA ede eat ence aes 3 6 1262 TEC PH 3 6 ADC EIEO juste A 3 7 Analog Input Calibration ester ett e e OS edendum 3 7 Data Acquisition Timing Circuitry gs cede eee 3 7 RAT Mindi ode eoo Me ree ees 3 7 Single Channel Data Acquisition 3 8 Multiple Channel Data Acquisition 3 10 Continuous Scanning Data Acquisition Timing 3 11 Interval Scanning Data Acquisition Timing eene 3 11 Data Acquisition Rates vs iut i a oda ceu edv dat uere 3 12 Analog Output and Timing ea 3 12 Analog Output Circuitry 3 13 Analog Output Configuration ss 3 14 Analog Output CallBralloHn ss 3 14 DAC Waveform Circuitry and Timing eese 3 14 DAG Waveform medals eines a T ua d ead 3 15 DAC Waveform Timing Circuitry eese 3 16 FIFO Continuous Cyclic Waveform Generation 3 17 FIFO Progra
160. f the following mode values 8225 Selects 5 MHz clock Counter 2 Source signal 8B25 Selects 1 MHz clock 8C25 Selects 100 kHz clock 8D25 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum Write FFOA to the Am9513A Command Register to select the Counter 2 Load Register Write 2 to the Am9513A Data Register to store the Counter 2 load value Write FF42 to the Am9513A Command Register to load Counter 2 Write FFF2 to the Am9513A Command Register to step Counter 2 down to 1 SU gy 290 5 Entries stored in the mux channel gain memory should be scanned once during a scan interval The following condition must be satisfied scan interval 2 sample interval x where x is the number of entries in the scan sequence Write the desired scan interval to the Am9513A Data Register to store the Counter 2 load value e If the scan interval is between 2 and FFFF 65 535 decimal write the scan interval to the Am9513A Data Register e If the scan interval is 10000 65 536 decimal write 0 to the Am9513A Data Register 8 Write FF22 to the Am9513A Command Register to arm Counter 2 After you complete this programming sequence Counter 2 is configured to assign a time interval to scan sequences once the trigger to enable A D conversions is detected Applying a Trigger Once a data acquisit
161. formation DAC Waveform Circuitry and Timing There are primarily two modes under which the DACS in the analog output section operate immediate update and posted update Immediate update mode is self evident You write a value to the DAC and its voltage is immediately available at the output In posted update mode the voltage is not available at the output until a timer trigger signal initiates an update This mode has advantages in waveform generation applications which need precisely timed updates that are not software dependent AT MIO 16X User Manual 3 14 National Instruments Corporation Chapter 3 Theory of Operation DAC Waveform Circuitry Figure 3 10 depicts the three different data paths to the analog output DACs Update Serial RTSI Data RTSI Latch R Latch LATCHEN Local Latch Local Data Bus DAC Data Bus LATCHEN Control Circuitry Control Circuitry DACFIFOHF DACFIFORS DACFIFORD RENE To Figure 3 10 Analog Output Waveform Circuitry The local latch is used for immediate updating of the DACs When data is written to the DACs in immediate updating mode the data is directly routed to the DACs to be converted to a voltage at the output In this mode the Update signal is held low or true The only path available for data transfer to the DACS in the immediate update mode is the local latch The path that the data takes to the DACs is determined by the DAC mode enabled through
162. g Output Specifications Offset error 18 the amount of possible voltage offset error in the analog output circuitry expressed in mV Gain error is the amount of possible deviation from ideal gain of the analog output circuitry expressed as a proportion of the gain The total linear error for a DAC at a given output voltage is the output voltage times the gain error plus the offset error Relative accuracy in a DAC is the same as integral nonlinearity because no uncertainty is added by quantization Unlike an ADC every digital code in a DAC represents a specific analog value rather than a range of values The relative accuracy of the system is therefore limited to the worst case deviation from the ideal correspondence a straight line excepting noise If a DAC has been perfectly calibrated then the relative accuracy specification reflects its worst case absolute error Differential nonlinearity in a DAC is a measure of deviation of code width from 1 LSB Fora DAC code width is the difference between the analog values produced by consecutive digital codes A specification of 0 5 LSB differential nonlinearity ensures that the code width is always greater than 0 5 LSB guaranteeing monotonicity and less than 1 5 LSB Digital Compatibility TTL compatible Output current source capability Can source 2 6 mA and maintain Voy at 2 4 V Output current sink capability Can sink 24 mA and maintain at 0 5 V AT MIO 16X User Manual A 6
163. g is enabled on AT MIO 16X SCANCLK is normally low and pulses high for approximately 8 us after the A D conversion begins The low to high edge can be used to clock external analog input multiplexers The SCANCLK signal is driven by one CMOS TTL gate EXTSTROBE Signal A low pulse of no less than 500 ns is generated the EXTSTROBE pin when the External Strobe Register is accessed See the External Strobe Register section in Chapter 4 Register Map and Descriptions for more information Figure 2 13 shows the timing for the EXTSTROBE signal tw 500 ns Figure 2 13 EXTSTROBE Signal Timing The pulse width is defined as 500 ns minimum The EXTSTROBE signal can be used by an external device to latch signals or trigger events The EXTSTROBE signal is an signal National Instruments Corporation 2 27 AT MIO 16X User Manual Configuration and Installation Chapter 2 EXTCONV Signal A D conversions be externally triggered with the EXTCONV pin Applying an active low pulse to the EXTCONV signal initiates an A D conversion Figure 2 14 shows the timing requirements for the EXTCONV signal tw 50 ns minimum ADC switches to hold mode within 100 ns from this point Figure 2 14 EXTCONV Signal Timing The minimum allowed pulse width is 50 ns The ADC switches to hold mode within 100 ns of the high to low edge This hold mode delay time is a function of temperature and does not vary from one conversion to
164. g output circuitry by adjusting the following potential sources of error Analog output offset error e Analog output gain error In order to read the analog output voltages the output calibration routine requires that the AT MIO 16X analog outputs be wrapped back to the analog inputs as follows 1 Connect DACO to a channel lt 0 7 gt 2 Connect DACI to another channel in lt 0 7 gt 3 Connect AO GND to the negative sides of the channels selected in steps 1 and 2 Do not tie AO GND to AI GND as this will complete a ground loop potentially introducing offset calibration errors of several LSBs The output calibration routines require that the input is already calibrated because it uses the input circuitry as the source of calibration Offset error in the analog output circuitry is the total of the voltage offsets contributed by the components in the output circuitry This error which is independent of the DAC output voltage is the amount of voltage generated by the DAC when it is set to produce 0 V To correct this offset error the routine writes a value of 0 to each DAC and adjusts CALDAC6 and CALDAC7 until it measures 0 V between each analog output and AO GND Gain error in the analog output circuitry is the sum of the gain errors contributed by the components in the output circuitry This error is a voltage difference between the desired voltage and the actual output voltage generated that is proportional to the D
165. ge can float with respect to the analog ground of the AT MIO 16X board This common mode voltage is subsequently subtracted from the signals by the input PGIA This configuration is useful when measuring ground referenced signal sources See the Types of Signal Sources section later in this chapter for more information With this input configuration the AT MIO 16X can measure up to 16 different analog input signals This configuration is selected via software See the configuration memory register and Table 4 9 in Chapter 4 Register Map and Descriptions for additional information The results of this configuration are as follows AI SENSE is tied into the negative input of the PGIA e Multiplexer outputs are tied together into the positive input of e Multiplexer control is configured to control up to 16 input channels Note The NRSE input mode is the only mode in which the AI SENSE signal from the I O connector is used as an input In all other modes AI SENSE is either programmed to be unused or driven with the board analog input ground Considerations for using the NRSE input configuration are discussed in the Signal Connections section later in this chapter Figure 2 8 shows a schematic diagram of this configuration AT MIO 16X User Manual 2 8 National Instruments Corporation Chapter 2 Configuration and Installation Input Polarity and Input Range The AT MIO 16X has two polarities unipolar input and bipola
166. generated when a single conversion is available in the FIFO In this case the request is removed when the ADC FIFO is empty Source 3 Select This bit is used to configure the signal connected to Source 3 of the Am9513 Counter Timer If SRC3SEL is set Source 3 is connected to the DAC FIFO retransmit signal In the FIFO programmed cycle waveform modes this bit should be set so the counter can access to the DAC FIFO retransmit signal If SRC3SEL is cleared Source 3 is connected to the SCANCLK signal Gate 2 Select This bit is used to configure the signal connected to Gate 2 of the Am9513 Counter Timer If GATE2SEL is set Gate 2 is connected to Out 1 of the Am9513 This bit should be set when using the FIFO pulsed waveform generation mode If GATE2SEL is cleared Gate 2 is connected to the internal Gate 2 circuitry on the AT MIO 16X FIFO or DAC Write Select This bit controls the destination of writes to the analog output DACs DMA transfers to the DACs are always buffered by the DAC FIFO Programmed I O writes are routed either to the DACs or through the DAC FIFO by using the FIFO DAC bit If FIFO DAC is set programmed I O writes to the DACs are buffered by the DAC FIFO If FIFO DAC is cleared programmed I O writes to the DACs bypass the DAC FIFO and are transmitted directly to the DACs External Trigger Disable This bit gates the EXTTRIG signal from the I O connector If EXTTRIG DIS is set triggers from EXTTRIG are ign
167. generates only positive numbers or two s complement binary which generates both positive and negative numbers The binary format used is determined by the mode in which the ADC is configured The bit pattern returned for either format is given as follows Address Base address 00 hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D10 D9 D7 D6 DS D4 D3 D2 DI DO MSB LSB Bit Name Description 15 0 D lt 15 0 gt Local data bus bits When the ADC FIFO is addressed these bits are the result of a 16 bit ADC conversion Values read range from 0 to 65 535 decimal 0x0000 to OxFFFF when the ADC is in unipolar mode and 32 768 to 32 767 decimal 0x8000 to Ox 7FFF when the ADC is in bipolar mode The A D conversion result can be returned from the ADC FIFO as a two s complement or straight binary value depending on the input mode set by the CHAN bit in the configuration memory location for the converted channel If the analog input circuitry is configured for the input range 0 to 10 V straight binary format is implemented Straight binary format returns numbers between 0 and 65 535 decimal when the ADC FIFO Register is read If the analog input circuitry is configured for the input ranges 10 to 10 V two s complement format is used Two s complement format returns numbers between 32 768 and 432 767 decimal when the ADC FIFO Regist
168. gital I O lines BDIO lt 3 0 gt are connected to bits lt 7 4 gt of the Digital Input Register When a port is enabled the Digital Input Register serves as a read back register returning the digital output value of the port When a port is not enabled reading the Digital Input Register returns the state of the digital I O lines driven by an external device Both the digital input and output registers are TTL compatible The digital output ports when enabled are capable of sinking 24 mA of current and sourcing 2 6 mA of current on each digital I O line When the ports are not enabled the digital I O lines act as high impedance inputs The external strobe signal EXTSTROBE shown in Figure 3 16 is a general purpose strobe signal Writing to an address location on the AT MIO 16X board generates an active low 500 nsec pulse on this output pin EXTSTROBE is not necessarily part of the digital I O circuitry but is shown here because it can be used to latch digital output from the AT MIO 16X into an external device Timing I O Circuitry The AT MIO 16X uses an Am9513A Counter Timer for data acquisition timing and for general purpose timing I O functions An onboard oscillator is used to generate the 10 MHz clock Figure 3 17 shows a block diagram of the timing I O circuitry 1 MHz 5 MHz BRDCLK Am9513A SOURCE2 Five Channel Counter Timer DATA lt 15 0 gt 16 GATEI Am9513A RD WR SOURCEI OUTI 5 SOURCES OUTS
169. h RTSI switch pin of the same name The 4 bit control field for pin AO is shown in Figure 5 10 The bits labeled S2 through 50 are the signal source selection bits for the pin One of seven source signals be selected Pins A6 through 0 can select any of the pins B6 through BO as signal sources Pins B6 through BO select any of the pins A6 through as signal sources For example the pattern 011 for S2 through SO in the control field selects the signal connected to pin B3 as the signal source for pin The bit labeled OUTEN is the output enable bit for that pin If the OUTEN bit is set the pin is driven by the selected source signal the pin acts as an output pin If the OUTEN bit is cleared the pin is not driven regardless of the source signal selected instead the pin can be used as an input pin If the preceding control field contains the pattern 0111 the signal connected to pin B3 Trigger Line 3 appears at pin On the AT MIO 16X board this arrangement allows the EXTCONV signal to be driven by Trigger Line 3 Conversely if the B4 control field contains the pattern 1011 the signal connected to pin A5 appears at pin B4 This arrangement allows Trigger Line 4 to be driven by the AT MIO 16X signal In this way boards connected via the RTSI bus can send signals to each other over the RTSI bus trigger lines To program the RTSI switch complete these steps Calculate the 56 bit pattern based on the de
170. hapter Notice that if 5 is to be used for updating it does not need to be routed across the RTSI switch In this case only is it sufficient to enable A4DRV to drive pin A4 of the RTSI switch with OUTS Programming the Update Interval Counter Select the appropriate counter 1 2 3 or 5 from the Am9513A Counter Timer to be used for updating the DACs Active low pulsing and no gating should be part of the mode programmed To program the update interval counter complete the following programming sequence writes are 16 bit operations All values given are hexadecimal 1 Write FF00 n to the Am9513A Command Register to select the Counter n Mode Register 2 Write the mode value to the Am9513A Data Register to store the Counter n mode value Am9513A counter mode information can be found in Appendix AMD Am9513A Data Sheet Use one of the following mode values 0225 Selects 5 MHz clock from SOURCE2 pin 0B25 Selects 1 MHz clock 0C25 Selects 100 kHz clock 0025 Selects 10 kHz clock National Instruments Corporation 5 23 AT MIO 16X User Manual Programming Chapter 5 0 25 Selects 1 clock 0 25 Selects 100 Hz clock 0525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum 3 Write FFO8 n to the Am9513A Command Register to select the Counter n Load Register 4 Write the desired update interval to the Am9513A Data Register to store the counter n
171. he contents of the RTSI Switch Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSI Switch Strobe Register is written to after shifting the 56 bit routing pattern into the RTSI Switch Shift Register Address Base address OE hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used National Instruments Corporation 4 61 AT MIO 16X User Manual Chapter 5 Programming This chapter contains programming instructions for operating the circuitry on the AT MIO 16X Programming the AT MIO 16X involves writing to and reading from the various registers on the board The programming instructions list the sequence of steps to take The instructions are language independent that is they instruct you to write a value to a given register to set or clear a bit in a given register or to detect whether a given bit is set or cleared without presenting the actual code Note If you plan to use a programming software package such as NI DAQ or LabWindows with your AT MIO 16X board you need not read this chapter Register Programming Considerations Several write only registers on the AT MIO 16X contain bits that control a number of independent pieces of the onboard circuitry In the instructions for setting or clearing bits specific register bits should be set or cleared without changing the current state of the remaining bits in the register However writing to the
172. he sample counter Counter 4 is programmed to count the number of conversions generated In this case the sample counter is programmed to count 10 samples then stop the acquisition sequence A signal is generated at the end of the sequence to indicate its completion An interrupt request can be generated from this signal if desired Because the sample counter begins counting immediately after the application of the trigger this is a posttrigger sequence If samples are necessary before and after the trigger then a pretrigger sequence is needed This sequence is described in the following paragraphs Figure 3 6 depicts a pretrigger data acquisition sequence It is called a pretrigger sequence because the first trigger initiates the sample interval timer without enabling the sample counter Conversions occur after this initial trigger and are stored in the ADC FIFO for later retrieval in the same way they are for a posttrigger sequence After a second trigger is received the sample counter begins counting conversions In this example there are three pretrigger samples and seven posttrigger samples Only the number of posttrigger samples is programmable National Instruments Corporation 3 9 AT MIO 16X User Manual Theory of Operation Chapter 3 Trigger DAQPROG CONVERT 2 Ro o qub up A Samp CTR Gate 222211 Sample CTR 6 AS5XAX3AX2AXIXTX 6 DAQCMPLT Interrupt JHJHJJJJJ J JS S S SPS SH HSS DAQCL
173. hrough the 16 single ended or 8 differential channels expandable with National Instruments multiplexing products at a programmable gain of 1 2 5 10 20 50 or 100 for unipolar or bipolar input ranges A 512 word ADC FIFO buffer can perform seamless data acquisition at the maximum rate without data loss Internal or external triggering and sampling are supported If signal conditioning or additional analog inputs are required you can use the SCXI signal conditioning modules SCXI multiplexer products or the AMUX 64T multiplexer board National Instruments Corporation 1 1 AT MIO 16X User Manual Introduction Chapter 1 You can use the NI DAQ software included with the AT MIO 16X to calibrate the analog input circuitry This software adjusts the offset and gain errors to zero by means of board level calibration DACs You can store calibration DAC constants resulting from the calibration procedure in the onboard EEPROM for later use See Chapter 6 Calibration Procedures for additional information on calibration procedures for the AT MIO 16X Analog Output The AT MIO 16X also has two deglitched double buffered multiplying 16 bit DACs that may be configured for a unipolar or bipolar voltage output range onboard 10 reference is the internal reference to the circuitry of the DAC A 2 048 word DAC FIFO buffer allows seamless waveform generation at the maximum rate without data loss The DAC FIFO can perform cyclic waveform generat
174. ice to drive the digital I O lines the input ports must be enabled Clear the DIOPAEN bit in Command Register 2 if an external device is driving digital I O lines ADIO lt 3 0 gt Clear the DIOPBEN bit in Command Register 2 if an external device is driving digital I O lines BDIO lt 3 0 gt The Digital Input Register can then be read to monitor the state of the digital I O lines as driven by the external device The logic state of all eight digital I O lines can be read from the Digital Input Register If the digital output ports are enabled the Digital Input Register serves as a read back register that is you can determine how the AT MIO 16X is driving the digital I O lines by reading the Digital Input Register If any digital I O line is not driven it floats to an indeterminate value If more than one device is driving any digital I O line the voltage at that line may also be indeterminate In these cases the digital line has no meaningful logic value and reading the Digital Input Register may return either 1 or for the state of the digital line Programming the Am9513A Counter Timer Counters 1 2 and 5 of the Am9513A Counter Timer are available for general purpose timing applications The programmable frequency output pin FOUT is also available as a timing signal source These applications and a general description of the Am9513A Counter Timer are AT MIO 16X User Manual 5 26 National Instruments Corporation Chapter 5 Programmi
175. ignal AT MIO 16X User Manual 2 28 National Instruments Corporation Chapter 2 Configuration and Installation tw 50 ns minimum First A D conversion starts within 1 sample interval from this point Figure 2 15 EXTTRIG Signal Timing The EXTTRIG pin is also used to initiate AT MIO 16X pretriggered data acquisition operations In pretriggered mode data is acquired after the first falling edge trigger is received but no sample counting occurs until after a second falling edge trigger is applied to the EXTTRIG pin The acquisition then completes when the sample counter decrements to zero This mode acquires data both before and after a hardware trigger is received The minimum pulse width allowed is 50 ns The first A D conversion starts within one sample interval from the high to low edge The sample interval is controlled by Counter 3 or EXTCONV There is no maximum pulse width limitation however EXTTRIG should be high for at least 50 ns before going low The EXTTRIG signal is one HCT load and is pulled up to 5 V through a 10 kQ resistor The EXTTRIG signal is logically ANDed with the internal DAQSTART signal If a data acquisition sequence is to be initiated with an internal trigger EXTTRIG must be high at both the I O connector and the RTSI switch If EXTTRIG is low the sequence will not be triggered In addition triggers from the EXTTRIG signal can be inhibited through programming of a register in the AT MIO 16X regist
176. il cleared by strobing the DMATCA Clear Register DMA Terminal Count Channel B DMATCB reflects the status of the DMA process on the selected DMA Channel B When the DMA operation is completed DMATCB goes high and remains high until cleared by strobing the DMATCB Clear Register Overflow This bit indicates whether the ADC FIFO has overflowed during a sample run OVERFLOW is an error condition that occurs if the FIFO fills up with A D conversion data and A D conversions continue If OVERFLOW is set A D conversion data has been lost because of FIFO overflow If OVERFLOW is clear no overflow has occurred If OVERFLOW occurs during a data acquisition operation the data acquisition is terminated immediately This bit is reset by strobing the DAQ Clear Register Overrun This bit indicates whether an A D conversion was initiated before the previous A D conversion was complete OVERRUN is an error condition that can occur if the data acquisition sample interval is too small sample rate is too high If OVERRUN is set one or more conversions were skipped If OVERRUN is clear no overrun condition has occurred If OVERRUN occurs during a data acquisition operation the data acquisition is immediately terminated This bit is reset by strobing the DAQ Clear Register Timer Request This bit reflects the status of the timer update TMRREQ is set whenever the DAC FIFO is ready to receive data or a pulse has occurred on TMRTRIG signal
177. in the interrupt mode TMRREQ generates an interrupt or DMA request only if the proper mode is selected according to Table 4 3 In DMA transfer mode TMRREQ is automatically cleared when the DAC is written to In interrupt and programmed I O modes TMRREQ must be cleared by strobing the TMRREQ Clear Register 4 20 National Instruments Corporation Chapter 4 Bit Name 6 DACCOMP 5 DACFIFOFF 4 DACFIFOHF 3 DACFIFOEF 2 EEPROMDATA 1 EEPROMCD 0 CFGMEMEF Register Map and Descriptions Description continued DAC Sequence Complete This bit reflects the status of the DAC sequence termination circuitry When the DAC sequence has normally completed or ended on an error condition the DACCOMP bit is set If DACCOMP is set prematurely this indicates an error condition If interrupts are enabled an interrupt will be generated on this condition The interrupt is serviced by strobing the TMRREQ Clear or DAC Clear Register While the sequence is in progress the DACCOMP bit is cleared DAC FIFO Full Flag This bit reflects the state of the DAC FIFO If DACFIFOFF is clear the DAC FIFO is full and is not ready to receive data If DACFIFOFF is set the DAC FIFO is not full and is able to continue receiving data If the appropriate DAC and I O modes are enabled interrupts or DMA requests are generated until the DAC FIFO is full DAC FIFO Half Full Flag This bit reflects the state of the DAC FIFO If DACFIFOHF is clear
178. ing data in the DAC FIFO Also due to the smaller buffer size the hardware has more National Instruments Corporation 5 19 AT MIO 16X User Manual Programming Chapter 5 control over the updating and cycling through of the buffer This enables the waveform circuitry to perform cycle counting programmed cycle generation and pulsed cyclic waveform generation To update the analog output DACs in programmed cycle waveform generation mode complete the sequence of programming steps in Figure 5 8 The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter Clear the analog output circuitry including the DAC FIFO Yes Set the A4RCV bit in Clear the A4RCV bit in Command Register 2 Command Register 2 Select the update counter via RTSI programming Program the update interval counter Program the cycle counter Set the waveform generation mode Enable updating Service update requests Figure 5 8 Programmed Cycle Waveform Programming AT MIO 16X User Manual 5 20 National Instruments Corporation Chapter 5 Programming One disadvantage of the programmed cycle waveform generation is that it uses yet another counter to perform the cycle counting For this mode the SRC3SEL bit in Command Register 4 must be set so that the programmed counter can count the buffer retransmit signals from the source line of Counter 3 Counter 1 2 or 5
179. ion part number 609 5007 The mating connector for the AT MIO 16X is a 50 position polarized ribbon socket connector with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent upside down connection to the AT MIO 16X The recommended manufacturer part numbers for this mating connector are as follows e Electronic Products Division 3M part number 3425 7650 e T amp B Ansley Corporation part number 609 5041 Recommended manufacturer part numbers for the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors are as follows e Electronic Products Division 3M part number 3365 50 e T amp B Ansley Corporation part number 171 50 AT MIO 16X User Manual 1 6 National Instruments Corporation Chapter 1 Introduction Optional Equipment for AT MIO 16X with 68 Pin Shielded Cable I O Connector Equipment Part Number SH6850 shielded cable assembly lm 2m 5m 10 m CB 50 I O connector block 50 screw terminals without cable use with SH6850 cable assembly AT Series RTSI bus cables for 2 boards 3 boards 4 boards 5 boards SCXI 1347 shielded cable assembly lm 2m 5m 10m SCXI signal conditioning modules SCXI 1100 32 channel differential multiplexer amplifier SCXI 1120 8 channel isolated analog input SCXI 1121 4 channel isolated transducer amplifier with excitation SCXI 1140 8 channel simultaneously sampling differential amplifier SCXI 1160 16
180. ion directly from the FIFO independent of the PC interface You can use the analog output circuitry for internal timer and external signal update capability for waveform generation You calibrate the analog output circuitry through the NI DAQ software provided with the board This software adjusts the DAC offset and gain errors of each channel to zero by means of board level calibration DACs Calibration DAC constants resulting from the calibration procedure may be stored in the onboard EEPROM for later use See Chapter 6 Calibration Procedures for additional information on calibration procedures for the AT MIO 16X Digital and Timing I O In addition to the analog input and analog output capabilities of the AT MIO 16X the AT MIO 16X also has eight digital I O lines that can sink up to 24 mA of current and three independent 16 bit counter timers for frequency counting event counting and pulse output applications The AT MIO 16X has timer generated interrupts a high performance RTSI bus interface and four triggers for system level timing You can use the AT MIO 16X with its multifunction analog digital and timing I O in many applications including machine and process control automation level monitoring and control instrumentation electronic testing and many others You can use the multichannel analog input for signal and transient analysis data logging and chromatography The two analog output channels are useful for machine and pr
181. ion operation has been configured and programmed the acquisition sequence is initiated when a trigger is received A trigger can be initiated through software or hardware To initiate the data acquisition operation through software strobe the Start DAQ Register Make sure EXTTRIG is not pulled low at the I O connector or RTSI switch To initiate the data acquisition operation through hardware apply an active low pulse to the EXTTRIG pin on the AT MIO 16X I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for EXTTRIG signal specifications National Instruments Corporation 5 15 AT MIO 16X User Manual Programming Chapter 5 Once the trigger is applied Counter 3 generates pulses initiating A D conversions once every sample interval until the sample counter reaches zero In the pretrigger mode these conversions are not counted by the sample counter Counting begins only after the application of a second hardware or software trigger condition and continues until the sample counter reaches zero A D conversion data stored before receipt of the EXTTRIG or DAQ Start signal are pretrigger samples Servicing the Data Acquisition Operation Once the data acquisition operation is initiated with the application of a trigger the operation must be serviced by reading the ADC FIFO The ADC FIFO can be serviced in two different ways One method is to monitor the ADCFIFOEF to read the
182. ional Instruments Corporation C 15 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 16 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 17 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 18 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 19 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 20 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 21 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 22 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 23 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 24 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 25 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 26 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 27 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 28 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Co
183. ircuitry Whether the waveform size is greater than or less than 2 048 points a waveform can be generated that is seamless that is there will be no gaps or missed points in the output waveform If a point is missed for any reason the waveform circuitry will automatically stop updating the DAC and a waveform error signal will be generated that can be monitored in Status Register 1 An error condition or underflow occurs when data is extracted from the DAC FIFO faster than it enters such that at one point the DAC FIFO becomes empty Underflow errors occur because of software or hardware latencies in acknowledging the signal requesting more data for the DAC FIFOs This condition can be prevented in the cyclic mode where the buffer resides wholly in the DAC FIFO and is cycled through to generate a continuous waveform The advantage of having the data in the DAC FIFO is that the FIFO never needs to have the data refreshed therefore it is never empty Rather than requesting new data the FIFO simply reuses existing data removing a large demand on the PC bus bandwidth Maximum updating performance is achieved in this mode because it does not rely on the speed of the computer All described waveform modes involving cycling within the DAC FIFO can also be accomplished without the entire buffer fitting inside the FIFO However this requires more software intervention and therefore results in a slower rate and decreased reliability FIFO Continuous Cycli
184. ircuitry 5 18 DAC Update Register 4 43 DAC waveform circuitry and timing 3 14 to 3 19 See also waveform generation programming analog output waveform circuitry illustration 3 17 block diagram 3 15 DACMB lt 3 0 gt bit for selecting waveform modes 4 17 FIFO continuous cyclic waveform generation 3 17 to 3 18 FIFO programmed cyclic waveform generation 3 18 FIFO pulsed waveform generation 3 18 to 3 19 immediate updating of DACs 3 14 to 3 15 posted DAC update timing illustration 3 16 posted update mode 3 14 to 3 15 waveform circuitry illustration 3 15 waveform timing circuitry 3 16 to 3 17 DACO OUT signal analog output signal connections 2 24 definition 2 14 B 3 programming analog output circuitry 5 18 DACO Register 4 32 5 18 DACODSP bit 4 17 DACOREQ bit 4 14 DACI OUT signal analog output signal connections 2 24 definition 2 14 B 3 programming analog output circuitry 5 18 DACI Register 4 33 5 18 DACIDSP bit 4 17 AT MIO 16X User Manual DACIREQ bit 4 14 DACCMPLINT bit 4 12 DACCOMP bit 4 21 5 23 5 26 DACFIFOEF bit 4 21 5 26 DACFIFOFF bit 4 21 5 30 DACFIFOHF bit 4 21 5 30 DACFIFORT signal 3 17 DACGATE bit 4 17 DACMB lt 3 0 gt bit 4 17 DACs analog output circuitry 3 13 immediate updating 3 14 to 3 15 output configuration 3 14 posted updating 3 15 DAQ Clear Register clearing analog input circuitry 5 10 description 4 37 DMA operations 5 30 interrupt programming
185. is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register The RTSI Switch Control Register is then loaded by writing to the RTSI Switch Strobe Register Bit descriptions of the two registers making up the RTSI Switch Register Group are given on the following pages National Instruments Corporation 4 59 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 RTSI Switch Shift Register The RTSI Switch Shift Register is written to in order to load the RTSI switch internal 56 bit Control Register with routing information for switching signals to and from the RTSI bus trigger lines The RTSI Switch Shift Register is a 1 bit register and must be written to 56 times to shift the 56 bits into the internal register Address Base address hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CO e e 9 LSB MSB Bit Name Description 7 1 0 Reserved These bits must always be set to zero 0 RSI RTSI Switch Serial Input This bit is the serial input to RTSI switch Each time the RTSI Switch Shift Register is written to the value of this bit is shifted into the RTSI switch See the Programming the RTSI Switch section later in this chapter for more information AT MIO 16X User Manual 4 60 National Instruments Corporation Chapter 4 Register Map and Descriptions RTSI Switch Strobe Register The RTSI Switch Strobe Register is written to in order to load t
186. it 4 28 CHAN LAST bit 4 28 5 11 channel scanning See under data acquisition programming CHAN SE bit 4 26 CHANSEL lt 3 0 gt bit 4 27 CH GAIN 2 0 bit 4 27 CLKMODEB lt 1 0 gt bit 4 16 CNT32 16 bit 4 6 5 13 5 14 Command Register 1 4 5 to 4 7 Command Register 2 4 8 to 4 10 5 26 5 31 Command Register 3 4 11 to 4 15 Command Register 4 4 16 to 4 18 common mode signal rejection considerations 2 23 to 2 24 CONFIGMEM Register 4 26 to 4 29 5 10 5 11 CONFIGMEMCLR Register 4 35 5 10 5 11 CONFIGMEMLD Register 4 36 5 10 5 11 configuration See also installation signal connections analog input configuration 2 6 to 2 9 DIFF input eight channels 2 7 input mode 2 7 to 2 8 input polarity and range 2 9 NRSE input 16 channels 2 7 2 8 RSE input 16 channels 2 7 2 8 analog output configuration 2 10 output polarity selection 2 10 output reference selection 2 10 AT bus interface 2 3 base I O address selection 2 3 to 2 6 board configuration 2 3 to 2 6 cabling considerations 50 pin connector 2 35 68 pin connector 2 36 default settings for National Instrument products table 2 5 digital I O configuration 2 10 DMA channel selection 2 6 National Instruments Corporation Index field wiring 2 34 to 2 35 interrupt selection 2 6 parts locator diagram 50 pin connector 2 1 68 pin connector 2 2 RTSI bus clock configuration 2 10 to 2 11 Configuration and Status Register Group 4 4 to 4 22
187. ition operation If DAQEN is cleared software and hardware triggers have no effect Scan Enable This bit controls multiple channel scanning during data acquisition If SCANEN is set and DAQEN is also set alternate analog input channels are sampled during data acquisition under control of the channel configuration memory If SCANEN is cleared and DAQEN is set a single analog input channel is sampled during the entire data acquisition operation When SCANEN is set the SCANCLK signal at the I O connector is enabled Otherwise it is disabled Scan Mode 2 This bit selects the data acquisition scanning mode used when scanning multiple A D channels If SCN2 is set and SCANEN and DAQEN are set interval channel scanning is used In this mode scan sequences occur during a programmed time interval called a scan interval One cycle of the scan sequence occurs during each scan interval If SCN2 is cleared and SCANEN and DAQEN are set continuous channel scanning is used In this mode scan sequences are repeated with no delays between cycles 32 or 16 Bit Sample Count This bit selects the count resolution for the number of A D conversions to be performed in a data acquisition operation If CNT32 16 is cleared a 16 bit count mode is selected and Counter 4 of the Am9513A Counter Timer controls conversion counting If CNT32 16 is set a 32 bit count mode is selected and Counter 4 is concatenated with Counter 5 to control conversion counting
188. le interval counts down at the rate given by the internal timebase or external clock Each time the sample interval timer reaches zero it generates an active low pulse and reloads with the programmed sample interval count initiating a conversion This operation continues until data acquisition halts External control of the sample interval is possible by applying a stream of pulses at the EXTCONV input In this case you have complete external control over the sample interval and the number of A D conversions performed data acquisition operations are functional with external signals to control conversions This means that in a data acquisition sequence that employs external conversion timing conversions are inhibited by the hardware until a trigger condition is received then the programmed number of conversions occurs and conversions are inhibited after the sequence completes When using internal timing the EXTCONV signal at the I O connector must be left unconnected or in the high impedance state Data acquisition can be controlled by the onboard sample counter This counter is loaded with the number of posttrigger samples to be taken during a data acquisition operation The sample counter can be 16 bit for counts up to 65 535 or 32 bit for counts up to 232 1 If a 16 bit counter is needed Counter 4 of the Am9513A Counter Timer is used If more than 16 bits are AT MIO 16X User Manual 3 6 National Instruments Corporation Chapter
189. ll as from timer updates If DMACHB is set requesting is enabled for DMA Channel B If DMACHB is cleared no DMA requests are generated on DMA Channel B To select a specific mode refer to Table 4 3 for available modes and associated bit patterns 4 12 National Instruments Corporation Chapter 4 Register Map and Descriptions Bit Name Description continued 6 ADCREQ ADC Request Enable This bit controls DMA requesting and interrupt generation from an A D conversion If this bit is set an interrupt or DMA request is generated when an A D conversion is available in the FIFO If this bit is cleared no DMA request or interrupt is generated following an A D conversion To select a specific mode refer to Table 4 3 for available modes and associated bit patterns Table 4 3 DMA and Interrupt Modes Interface Mode Mode Description IO INT Channel to DACO hannel A to DACI hannel A to DACO and DACI interleaved hannel A from ADC hannel B to DACO hannel B to DACI hannel to and DACI interleaved hannel B from ADC Lio a 1 Channel A from ADC Channel to DACO and DACI interleaved EPHRAIM ERREUR SERRE EN RE EE ENBEZEXENERNES fifo 1 E 04 er HT TS TS T9 5 oi e pa p 1 1 0 1 0 0 Channel A from ADC with timer interrupt TEE 0 1 ES
190. load value 5 Write the following value to the Am9513A Command Register to load counter n FF41 Load Counter 1 FF42 Load Counter 2 FF50 Load Counter 5 6 Write FFFO n to the Am9513A Command Register to decrement Counter n 7 Write the following value to the Am9513A Command Register to arm Counter n FF21 Arm Counter 1 FF22 Arm Counter 2 FF30 Arm Counter 5 After you complete this programming sequence Counter n is configured to generate active low pulses as soon as the load arm counter command is written Programming the Waveform Cycle Counter Select the appropriate counter 1 2 or 5 from the Am9513A Counter Timer to be used for counting DAC buffer cycles To program the cycle counter complete the following programming sequence All writes are 16 bit operations values given are hexadecimal 1 Write FF00 n to the Am9513A Command Register to select the Counter n Mode Register 2 Write 0325 to the Am9513A Data Register to store the Counter n mode value Am9513A counter mode information can be found in Appendix C AMD Am9513A Data Sheet 3 Write FF08 n to the Am9513A Command Register to select the Counter n Load Register 4 Write the desired cycle count to the Am9513A Data Register to store the Counter load value 5 Write the following value to the Am9513A Command Register to load Counter n FF41 Load Counter 1 FF42 Load Counter 2 FF50 Load Counter 5 6 Write FFFO n to the Am9
191. ltages are referenced to this node Digital Ground This pin supplies the reference for the digital signals at the connector as well as the 5 VDC supply ADIO lt 0 3 gt Digital I O port A signals BDIO lt 0 3 gt Digital I O port B signals 5 Source These pins are fused for up to 1 A of 5 V supply Scan Clock This pin pulses once for each A D conversion in the scanning modes The low to high edge indicates when the input signal can be removed from the input or switched to another signal External Strobe Writing to the EXTSTROBE Register results in a minimum 500 nsec low pulse on this pin AT MIO 16X User Manual I O Connector 68 Pin Pins 11 10 43 42 41 40 38 37 AT MIO 16X User Manual 50 Pin Pins Signal Names 38 39 40 41 42 43 44 45 46 47 48 49 50 EXTTRIG EXTGATE EXTCONV SOURCEI GATEI OUTI EXTTMRTRIG GATE2 OUT2 SOURCES GATES OUTS FOUT B 4 Appendix B Descriptions continued External Trigger In posttrigger data acquisition sequences a high to low edge on EXTTRIG initiates the sequence In pretrigger applications the first high to low edge of EXTTRIG initiates pretrigger conversions while the second high to low edge initiates the posttrigger sequence External Gate When EXTGATE is low A D conversions are inhibited When EXTGATE is high A D conversions are enabled Extern
192. m9513A Command Re e Ce ern 4 54 Am9513A Status Register aset e Fede e tensa en 4 55 Digital I O Register CIrOUD nee seit eoa nee 4 56 Digital Input Reglstet ioter ee teer tat e sr rede e 4 57 Digital Output Re sister de EH tnt tion 4 58 RTSI Switch Register Group et 4 50 RISI Switch Shit Register onset qoe terii Ve sve batum eniin 4 60 Switch Strobe Register eie e itte cose 4 61 Chapter 5 22 5 1 Register Programming Considerations eene 5 1 Resource Allocation 1 5 1 Initializing 5 2 Initializing the AMISTA ae est 5 2 Programming the Analog Input Circuitry eee 5 4 Single Conversions Using the SCONVERT or EXTCONV Signal 5 4 Generating a Single Conversion 5 feet tote pta 5 5 Reading a Single Conversion Result 2 5 5 Programming Single Channel Data Acquisition 5 5 National Instruments Corporation vii AT MIO 16X User Manual Contents Programming Data Acquisition
193. mediate update mode If posted update mode is used the value written to the DACO Register is buffered and updated to the analog output DAC Channel 0 only after an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 10 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 0 D lt 15 0 gt Data bus to the analog output DACs The data written to the DACs is interpreted in straight binary form when DAC Channel 0 is configured for unipolar operation When DAC Channel 0 is configured for bipolar operation the data is interpreted in two s complement form AT MIO 16X User Manual 4 32 National Instruments Corporation Chapter 4 Register Map and Descriptions DACI1 Register Writing to the DACI Register loads the value written to the analog output DAC Channel 1 in immediate update mode If posted update mode is used the value written to the DACI Register is buffered and updated to the analog output DAC Channel 1 only after an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 12 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 0 D lt 15 0 gt Data bus to the analog output DACs The data written to the DACs is interpreted in straight binary form when DAC Channel
194. mmed Cyclic Waveform 3 18 FIFO Pulsed Waveform Generation serene 3 18 Digital TVO vetus ta vate tee On EB Buenas 3 19 Timing VO C 3 20 RESI Bus Meri ace dis ie a SE e a t p S ra tendis 3 23 Chapter 4 Register Map and Descriptions 4 1 Register ee e ete mettent a Nine die annule sn 4 1 Register SIZES E 4 2 Register D scription Format sine nn entente duke es 4 3 AT MIO 16X User Manual vi National Instruments Corporation Contents Configuration and Status Register Group 4 4 Command Resister ss Wome TR Ren ded 4 5 Command Register 2 iere tese ete tee bres e ENTRIES enia agn o esae eva qu Voas 4 8 Command Register en dotes Veg ter Does so ak i poles ote bei quse 4 11 Command Register 4 iei e edere ee co pns 4 16 Stat s R sister Lois cip 4 19 Status m 4 22 Analog Input Register se toe pel 4 23 ADC FIFO RE ed e NUS Fin 4 24 CONPIGMEM REG ister ac ne mr na tn Yen KOH tiene nee ERR UE 4 26 Analog Output Register GrOUp seekers e eda re oes de eR vos 4 30 Ip SIN
195. n Connector Figure 2 9 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration If a grounded signal source is to be measured with a single ended configuration then the AT MIO 16X must be configured in the NRSE input configuration The signal is connected to the positive input of the AT MIO 16X PGIA and the signal local ground reference is connected to the negative input of the AT MIO 16X PGIA ground point of the signal should therefore be connected to the AI SENSE pin Any potential difference between the AT MIO 16X ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the and this difference is rejected by the amplifier AT MIO 16X User Manual 2 22 National Instruments Corporation Chapter 2 Configuration and Installation On the other hand if the input circuitry of the AT MIO 16X is referenced to ground such as in the RSE input configuration this difference in ground potentials appears as an error in the measured voltage Figure 2 10 shows how to connect a grounded signal source to an AT MIO 16X board configured for nonreferenced single ended input The AT MIO 16X analog input circuitry must be configured for NRSE input configuration to make these types of signals Configuration instructions are included in Chapter 4 Register Map and Descriptions
196. n illustration 5 29 AT MIO 16X User Manual definition 3 24 programming 5 28 to 5 31 selecting internal update counter 5 23 signal connections 5 27 to 5 28 RTSI Switch Register Group 4 59 to 4 61 register map 4 2 RTSI Switch Shift Register 4 60 RTSI Switch Strobe Register 4 61 RTSITRIG bit 4 7 5 52 through 50 bits 5 29 sample counters programming 5 12 to 5 14 sample counts 2 through 65 536 5 13 sample counts greater than 65 536 5 13 to 5 14 sample interval counter programming 5 11 to 5 12 sample interval timer 3 8 to 3 9 scan interval 5 7 scan interval counter programming 5 14 to 5 15 scan sequence 5 7 SCANCLK signal definition 2 14 B 4 multiple channel data acquisition 3 10 to 3 11 timing connections 2 27 SCANDIV bit 4 5 5 11 SCANEN bit 4 6 5 8 5 9 SCLK bit 4 5 SCN2 bit 4 6 5 10 SDATA bit 4 5 signal connections 2 11 to 2 34 analog input signal connections 2 16 to 2 17 AT MIO 16X 2 16 to 2 17 pin descriptions 2 16 to 2 17 B 3 to B 5 warning against exceeding input ranges 2 16 analog output signal connections 2 24 to 2 25 cabling considerations 50 pin connector 2 35 68 pin connector 2 35 digital I O signal connections 2 25 to 2 26 field wiring considerations 2 34 to 2 35 input configurations common mode signal rejection 2 23 to 2 24 National Instruments Corporation differential connections floating signal sources 2 19 to 2 21 general considerations
197. n achieve high performance even when used in environments that may have long interrupt latencies such as Windows Because off the shelf instrumentation amplifiers require 500 usec and more to settle to 16 bit accuracy at high gains when sampling multiple channels National Instruments developed the NI PGIA The NI PGIA which is used on the AT MIO 16X is an instrumentation amplifier that settles to 16 bits in 40 us even when the board is used at its highest gain of 100 A common problem with DAQ boards is that you cannot easily synchronize several measurement functions to a common trigger or timing event The AT MIO 16X has the Real Time System Integration RTSD bus to solve this problem The RTS bus consists of our custom RTSI bus interface chip and a ribbon cable to route timing and trigger signals between several functions on one or more DAQ boards in your PC The AT MIO 16X can interface to the Signal Conditioning eXtensions for Instrumentation SCXI system so that you can acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control SCXI is the instrumentation front end for plug in boards Analog Input The AT MIO 16X is a high performance multifunction analog digital and timing I O board for the PC The AT MIO 16X has a 10 usec 16 bit sampling ADC that can monitor a single input channel or scan t
198. n later in this chapter National Instruments Corporation 5 7 AT MIO 16X User Manual Programming Chapter 5 Clear the A D circuitry Program multiple analog input channels gains modes and ranges Program the sample interval counter Program the sample counter Enable a scanning data acquisition operation Apply a trigger Service the data acquisition operation Figure 5 4 Scanning Data Acquisition Programming Setting the SCANEN bit in conjunction with the DAQEN bit in Command Register 1 enables scanning during multiple A D conversions The SCANEN bit must be set regardless of the type of scanning used continuous or interval otherwise only a single channel is scanned Interval Channel Scanning Data Acquisition Follow the programming steps listed in Figure 5 5 to program scanned multiple A D conversions with a scan interval pseudo simultaneous for posttrigger and pretrigger modes as well as internal and external timing The instructions in the blocks of the following flow chart are enumerated in the Data Acquisition Programming Functions section later in this chapter AT MIO 16X User Manual 5 6 National Instruments Corporation Chapter 5 Programming Clear the A D circuitry Program multiple analog input channels gains modes and ranges Program the sample interval counter Program the sample counter Program the scan interval counter Enable an interval scanning data acquisition opera
199. nal Instruments Corporation 4 55 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 CONFIGMEMLD Register Accessing the CONFIGMEMLD Register loads and sequences through the channel configuration memory Address Base address 1B hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Read and apply a channel configuration value to the analog input section Accessing the CONFIGMEMLD Register loads the channel configuration memory values and applies the first channel configuration value to the analog input circuitry After the final write to the channel configuration memory accessing the CONFIGMEMLD Register loads the first channel configuration value Writing to the CONFIGMEMLD Register again loads the second channel configuration value and so on Strobing the DAQ Clear Register resets the channel configuration memory to the first value but does not load the value This does not clear the memory of any values written to it prior to the DAQ Clear strobe After strobing the DAQ Clear Register the CONFIGMEMLD Register should be strobed to load the first value A scanned data acquisition can be initiated from any location in the channel configuration memory by using this method AT MIO 16X User Manual 4 36 National Instruments Corporation Chapter 4 Register Map and Descriptions DAQ Clear Register Accessing the DAQ Clear Register location clears the data acquisition circuitry A
200. name inside its square An asterisk after the bit name indicates that the bit is inverted negative logic In many of the registers several bits are labeled with an X indicating don t care bits When a register is read these bits may appear set or cleared but should be ignored because they have no significance The bit map field for some registers states not applicable no bits used Accessing these registers generates a strobe in the AT MIO 16X These strobes are used to initiate some onboard event to occur For example they can be used to clear the analog input circuitry or to start a data acquisition operation The data is ignored when writing to these registers therefore any bit pattern suffices Likewise data returned from a strobe register read access is meaningless National Instruments Corporation 4 3 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Configuration and Status Register Group The six registers making up the Configuration and Status Register Group allow general control and monitoring of the AT MIO 16X hardware Command Registers 1 2 3 and 4 contain bits that control operation of several different pieces of the AT MIO 16X hardware Status Registers 1 and 2 can be used to read the state of different pieces of the AT MIO 16X hardware Bit descriptions of the six registers making up the Configuration and Status Group are given on the following pages AT MIO 16X User Manual 4 4 National Ins
201. nd negative inputs of the PGIA through input multiplexers on the AT MIO 16X The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the AT MIO 16X ground The AT MIO 16X ADC measures this output voltage when it performs A D conversions signals must be referenced to ground either at the source device or at the AT MIO 16X If you have a floating source the AT MIO 16X should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter If you have a grounded source the AT MIO 16X should not reference the signal to AI GND The AT MIO 16X board avoids this reference by using the DIFF or NRSE input configurations Types of Signal Sources When configuring the input mode of the AT MIO 16X and making signal connections you must first determine whether the signal source is floating or ground referenced These two types of signals are described in the following sections Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices opti
202. nel Clear Register clears the circuitry associated with dual channel DMA operation Two DMA channels are programmed for dual channel DMA When the first DMA channel terminal count is reached the circuitry automatically sequences the second DMA channel When the second DMA channel terminal count is reached the circuitry returns to the first DMA channel for servicing The effect of the DMA channel Clear Register is to initialize this circuitry Address Type Word Size Bit Map Strobe Effect Base address OB hex Read only 8 bit Not applicable no bits used Clears the dual DMA channel circuitry dual DMA mode only AT MIO 16X User Manual 4 46 National Instruments Corporation Chapter 4 Register Map and Descriptions DMATCA Clear Register Accessing the DMATCA Clear Register will clear the DMATCA signal in Status Register 1 and it will acknowledge the interrupt generated from the Channel A terminal counter interrupt When the selected DMA Channel A reaches its terminal count the DMATCA signal in the Status Register is asserted If DMATC interrupts are enabled an interrupt will also be generated Address Base address 19 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Clears the DMATCA signal in Status Register 1 and acknowledges an interrupt from a DMA Channel A terminal count National Instruments Corporation 4 47 AT MIO 16X User Manual Register Map and Descrip
203. ng included in the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation Timing I O Circuitry section in Chapter 3 Theory of Operation explains how the Am9513A is used on the AT MIO 16X board Initialization of the Am9513A as required by the AT MIO 16X and specific programming requirements for the sample interval and sample counters are given earlier in this chapter For general programming details for Counters 1 2 and 5 and the programmable frequency output refer to Appendix C AMD Am9513A Data Sheet In programming the Master Mode Register keep the following considerations in mind Am9513A must be used in 16 bit bus mode scaler control should be set to BCD division for correct operation of the clocks as described in the Programming Multiple A D Programming Conversions on a Single Input Channel section earlier in this chapter RTSI Bus Trigger Line Programming Considerations The RTSI switch connects signals on the AT MIO 16X to the seven RTSI bus trigger lines The RTSI switch has seven pins labeled A lt 6 0 gt connected to AT MIO 16X signals and seven pins labeled B lt 6 0 gt connected to the seven RTSI bus trigger lines Table 5 2 shows the signals connected to each pin Table 5 2 RTSI Switch Signal Connections RTSI Switch Pin Signal Name EXTCONV Bidirectional FOUT Output OUT2 Output Signal Direction National Instruments Corporation GATEI SOURC
204. ng a scan list can consist of any number of scan sequences Whenever a configuration memory location is selected the information bits contained in that memory location are applied to the analog input circuitry For scanning operations a counter steps through successive locations in the configuration memory at a rate determined by the scan clock With the configuration memory therefore an arbitrary sequence of channels with separate gain mode and range settings for each channel can be clocked through during a scanning operation A SCANCLK signal is generated from the sample interval counter This signal pulses once at the beginning of each A D conversion and is supplied at the I O connector During multiple channel scanning the configuration memory location pointer is incremented repeatedly thereby sequencing through the memory and automatically selecting new channel settings during data acquisition The signal used to increment the configuration memory location pointer is generated from the SCANCLK signal Incrementing can be identical to SCANCLK sequencing the configuration memory location pointer once after every A D conversion or it can also be generated by dividing SCANCLK by Counter 1 of the Am9513A Counter Timer With this method the location pointer can be incremented once every N A D conversions so that N conversions can be performed on a single channel configuration selection before switching to the next configuration memory selection
205. ng Medical and Clinical Use of National Instruments Products National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment About This Manual This manual describes the mechanical and electrical aspects of the AT MIO 16X board and contains information concerning its operation and programming AT MIO 16X is a high performance multifunction analog digital and timing I O board for the IBM PC AT and compatibles and EISA personal computers PCs Organization of This Manual The AT MIO 16X User Manual is organize
206. nput or output At system startup and reset the digital I O ports are both configured for input Board and RTSI Clock Configuration When multiple AT Series boards are connected via the RTSI bus you may want all of the boards to use the same 10 clock This arrangement is useful for applications that require counter timer synchronization between boards Each AT Series board with a RTSI bus interface has an onboard 10 MHz oscillator Thus one board can drive the RTSI bus clock signal and the other boards can receive this signal or disconnect from it Many functions performed by the AT MIO 16X board require a frequency timebase to generate the necessary timing signals for controlling ADC conversions DAC updates or general purpose signals at the I O connector You select this timebase through programming one of the registers in the AT MIO 16X register set AT MIO 16X User Manual 2 10 National Instruments Corporation Chapter 2 Configuration and Installation The AT MIO 16X can use either its internal 10 MHz timebase or it can use a timebase received over the RTSI bus In addition if the board is configured to use the internal timebase it can also be programmed to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is then divided by 10 and used as the Am9513A frequency source The default configuration at startup is to
207. ns Chapter 4 Am9513A Command Register The Am9513A Command Register controls the overall operation of the Am9513A Counter Timer and controls selection of the internal registers accessed through the Am9513A Data Register Address Base address 16 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 8 1 These bits must always be set when writing to the Am9513A Command Register 7 0 lt 7 0 gt These eight bits are loaded into the Am9513A Command Register See Appendix C AMD Am9513A Data Sheet for the detailed bit description of the Am9513A Command Register AT MIO 16X User Manual 4 54 National Instruments Corporation Chapter 4 Register Map and Descriptions Am9513A Status Register The Am9513A Status Register contains information about the output pin status of each counter in the Am9513A Address Base address 16 hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp MSB 7 6 3 4 3 2 1 0 LSB Bit Name Description 15 6 X Don t care bits 5 1 OUT 5 1 Each of these five bits returns the logic state of the associated counter output pin For example if OUTA is set then the output of Counter 4 is at a logic high state 0 BYTEPTR This bit represents the state of the Am9513A Byte Pointer Flip Flop This bit has no significance for AT MIO 16X operation because the Am9513A should always be used in 16 bit mod
208. nt at Voy 200 HA maximum output sink current at VoL 3 2 mA maximum Output current high impedance state 25 LA maximum Configuration and Installation Figure 2 19 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the Am9513A V SOURCE d 145 nsec 70 nsec 100 nsec 10 nsec 145 nsec 300 nsec Figure 2 19 General Purpose Timing Signals minimum minimum minimum minimum minimum maximum The GATE and OUT signal transitions in Figure 2 17 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram with the source signal inverted and referenced to the falling edge of the source signal applies to the case in which the counter is programmed to count falling edges National Instruments Corporation 2 33 AT MIO 16X User Manual Configuration and Installation Chapter 2 The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A counter timers and by the Am9513A frequency division output FOUT The signal applied to a SOURCE input must not exceed a frequency of 6 MHz for proper operation of the Am9513A The Am9513A counters can be individually programmed to count rising or falling edges of signals applied at any of the Am9513A SOURCE or GATE input pins In addition to the signals applied to the SOURCE and
209. nterested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix D Customer Communication at the end of this manual AT MIO 16X User Manual xiv National Instruments Corporation Contents About This Manual cron aam bo xiii Organization of Se nn tunes xiii Conventions Used in This Manual oasis dial esie de cod etre aei due duque xiv Related Documentation sisii i eg ad drole d c SE ae XIV Customer COMMUNICA ON 2 2 XIV Chapter 1 Introduction uote ete aD E atu uM ae 1 1 16 CR 1 1 Analog Input bene eh tale 1 1 Analog CULDUE s 1 2 Digital and Timing fantaisie 1 2 What Y our Kit Should 1 3 Optional SoftWare P 1 4 Optional Equipment for AT MIO 16X with 50 Pin Ribbon Cable I O Connector 1 5 Optional Equipment for AT MIO 16X with 68 Pin Shielded Cable I O Connector 1 7 Unpacking sos socii gii o dp tubi E ns ace 1 8 Chapter 2 Configuration and Installation 1 sse
210. nternal Update Counter 5 23 Programming the Update Interval Counter 5 23 Programming the Waveform Cycle Counter 5 24 Programming the Waveform Cycle Interval Counter 5 25 servicing Update Requests esee eet eae torii oai siet eds 5 25 Programming the Digital WO Circuitty eerte ig dades 5 26 Programming the Am9513A Counter Timer enn 5 26 RTSI Bus Trigger Line Programming Considerations eene 5 27 RTSI Switch Signal Connection 5 28 Programming the nt net ne edis d co 5 28 Programming DMA Operations 5 30 Interrupt Prog BIIIBE 5 31 Calibration Proced res cene eoi e SEG 6 1 Calibration Equipment Requirements ie eerie dee toe tere nare dace oce 6 5 Calibration DACS Me M Pac As quine rede 6 5 Reference Cali bration Ond Sethe Salsa alate 6 6 Analog Input CalIDPAUOD oo oett a en cadens 6 6 Analog Output Calibration cedar idee eg tede Sr de tees edet d ie t Sa 6 7 Appendix A Specificati nS seated DP fes 1 Analog Inp t sesen A 1 Explanation of Analog Input
211. nterrupt is generated then 256 values can be read in at once without checking the Status Register to see if the FIFO contains values Alternately if the DAC FIFO is 2 048 values deep and a half full interrupt is generated then 1 024 values can be read This can have a significant performance impact on software speed Reserved Reserved Reserved Reserved Reserved DAC 1 Range DAC 0 Range ADC Range 7 6 5 4 5 211 0 5 LSB Figure 6 5 Area Information Field If the Area Information Field contains the binary value XXXXX101 where X indicates don t care bits then the area described by this area information value contains bipolar DAC 1 calibration constants unipolar DAC 0 calibration constants and bipolar calibration constants The area information value for the factory bipolar area will always be and for the factory unipolar area it will always be 000 If the analog input section is calibrated using the utility library functions and the constants are saved to User Area 7 then the ADC AT MIO 16X User Manual 6 4 National Instruments Corporation Chapter 6 Calibration Procedures Range bit in the area information field for User Area 7 is set or cleared according to the mode in which the analog input section was calibrated bipolar or unipolar The same holds true for the analog output section Calibration Equipment Requirements Normal self calibration requires no external calibrati
212. nterval to the Am9513A Data Register e If the sample interval is 10000 65 536 decimal write 0 to the Am9513A Data Register 8 Write FF24 to the Am9513A Command Register to arm Counter 3 After you complete this programming sequence Counter 3 is configured to generate A D conversion pulses as soon as application of a trigger causes it to be enabled Programming the Sample Counter s Counters 4 and 5 of the Am9513A Counter Timer are used as the sample counter The sample counter tallies the number of A D conversions initiated by Counter 3 or EXTCONV inhibits conversions when the desired sample count is reached If the desired sample count is 65 536 or less only Counter 4 needs to be used making Counter 5 available for general purpose timing applications If the desired sample count is greater than 65 536 both Counters 4 and 5 must be used AT MIO 16X User Manual 5 12 National Instruments Corporation Chapter 5 Programming Sample Counts 2 through 65 536 Use the following programming sequence to program the sample counter for sample counts up to 65 536 The minimum permitted sample count is 2 writes are 16 bit operations values given are hexadecimal 1 Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register 2 Write 1025 to the Am9513A Data Register to store the Counter 4 mode value for posttrigger acquisition modes Write 9025 to the Am9513A Data Register to store the Counter 4 mode
213. ntil after the first falling edge of the Counter 2 output or one scan interval after the trigger Scanning stops at the end of the first scan sequence or at the end of the entire scan list The sequence restarts after a rising edge on Counter 2 is detected The interval scanning mode is useful for applications where a number of channels need to be monitored over a long period of time Interval scanning monitors the N channels every scan interval so the effective channel conversion interval is equal to the interval between scans Data Acquisition Rates The acquisition and channel selection hardware function so that in the channel scanning mode the next channel in the channel configuration register is selected immediately after the conversion process has begun on the previous channel With this method the input multiplexers and the PGIA begin to settle to the new value while the conversion of the last value is still taking place However the circuitry does not always settle to full 16 bit accuracy within the smallest allowed sample period of 10 usec See Appendix A Specifications for specification of settling times for the AT MIO 16X in scanning modes Analog Output and Timing Circuitry The AT MIO 16X has two channels of 16 bit D A output Unipolar or bipolar output and internal or external reference voltage selection are available with each analog output channel through a register in the AT MIO 16X register set Figure 3 9 shows a block diagram
214. ntrolled by Counter 1 of the Am9513A Counter Timer If SCANDIV is cleared the configuration memory is sequenced after each conversion during scanning 11 0 Reserved This bit must always be set to zero National Instruments Corporation 4 5 AT MIO 16X User Manual Register Map and Descriptions Bit Name 10 INTGATE 9 RETRIG DIS 8 DAQEN 7 SCANEN 6 SCN2 5 CNT32 16 AT MIO 16X User Manual Chapter 4 Description continued Internal Gate This bit controls internal and external A D conversions When INTGATE is set no A D conversions take place When INTGATE is cleared A D conversions take place normally INTGATE can be used as a software gating tool or to inhibit random conversions during setup operations Retrigger Disable This bit controls retriggering of the AT MIO 16X data acquisition circuitry When RETRIG DIS is set retriggering of the data acquisition circuitry is inhibited until the end of the previous operation is acknowledged by clearing the DAQPROG bit in Status Register 0 When RETRIG DIS is cleared the data acquisition circuitry may be retriggered any time following the end of the previous acquisition sequence Data Acquisition Enable This bit enables and disables a data acquisition operation that is controlled by the onboard sample interval and sample counters If DAQEN is set a software DAQ Start or hardware EXTTRIG trigger starts the programmed counters thereby initiating a data acquis
215. number of entries in the scan sequence e Strobe the CONFIGMEMCLR Register e ForizO0to N 1 use the following steps a Write the desired analog channel selection and gain setting to the CONFIGMEM Register this loads the configuration memory at location i b Ifi N 1 also set the LASTONE bit when writing to the CONFIGMEM Register e Strobe the CONFIGMEMLD Register Programming the Sample Interval Counter Counter 3 of the Am9513A Counter Timer is used as the sample interval counter Counter 3 can be programmed to generate an active low pulse once every N counts N is referred to as the sample interval that is the time between successive A D conversions N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following internal clocks are available to the Am9513A 5 MHz 1 MHz 100 KHz 10 kHz 1 kHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins Using the EXTCONV signal from the I O connector to control multiple A D conversions involves disabling the sample interval counter This counter should be left in the high impedance state see the Resetting a Single Am9513A Counter Timer section later in this chapter Conversions are generated by the falling edge of the EXTCONV signal Although EXTCONV may be pulsing conversions do not begin until after an active low pulse on Start or the EXTTRIG signal Conv
216. oard Alternately a logical 0 or false state is selected by pushing the toggle switch down or toward the bottom of the board In Figure 2 2B A9 is up true A8 through A6 are low false and A5 is up true This represents a binary value of 10001 XXXXX or hex 220 The Xs indicate don t care bits and are the five least significant bits LSBs of the address A4 through 0 used by the AT MIO 16X circuitry to decode the individual register selections The don t care bits indicate the size of the register space In this case the AT MIO 16X uses I O address hex 220 through hex 23F in the factory default setting Note If you change the AT MIO 16X base I O address you must make a corresponding change to any software packages you use with the AT MIO 16X Table 2 1 lists the default settings of other National Instruments products for the PC Table 2 2 lists the possible switch settings the corresponding base I O address and the base I O address space used for that setting For more information about the I O address of your PC refer to the technical reference manual for your computer AT MIO 16X User Manual 2 4 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 1 Default Settings of National Instruments Products for the PC DMA Channel Interrupt Level Base I O Address AT A2150 None None 120 hex 6 10 Channel 5 Lines 11 12 1C0 hex AT DIO 32F Channels 5 6 Lines 11 12 240 hex AT DSP2200 None N
217. ocess control analog function generation 16 bit resolution voltage source and programmable signal attenuation You can use the eight TTL compatible digital I O lines for machine and process control intermachine communication and relay switching control The three 16 bit counter timers are useful for such functions as pulse and clock generation timed control of laboratory equipment and frequency event and pulse width measurement With all these functions on one board you can automatically monitor and control laboratory processes AT MIO 16X is interfaced to the National Instruments RTSI bus With this bus National Instruments AT Series boards can send timing signals to each other The AT MIO 16X can send signals from the onboard counter timer to another board or another board can control single and multiple A D conversions on the AT MIO 16X Detailed specifications for the AT MIO 16X are listed in Appendix A Specifications AT MIO 16X User Manual 1 2 National Instruments Corporation Chapter 1 Introduction What Your Kit Should Contain There are two versions of the AT MIO 16X One has a 50 pin male ribbon cable I O connector and the other is functionally equivalent but has a 68 pin male shielded cable I O connector Each version of the AT MIO 16X board has a different part number and kit part number as follows Kit Name Kit Part Number Kit Component Board Part Number AT MIO 16X 776578 01 AT MIO 16X board with
218. ocess is not difficult or lengthy and requires no external equipment other than wires to connect the analog output to the analog input Calibration is performed by calling the MIO Calibrate function in NI DAQ The function calibrates the board and performs the necessary EEPROM reads and writes and calibration DAC writes The EEPROM is a 128 bit by 8 bit storage area which contains a permanent storage area and a modifiable storage area The permanent storage area consists of locations 96 through 127 While at the factory these locations can be accessed for a read or a write operation but in the field these locations can only be read from These locations cannot and should not be written to This allows for a permanent set of calibration values that cannot be erased The modifiable area consists of locations 0 through 95 These locations can always be read from and written to Included in this area are the load area user areas and user reference areas Notice that the load area contains constants that are loaded at initialization by the software to place the board in a known and calibrated state Revision T mE Subrevision 0001 B 0000 2 A Figure 6 2 Revision and Subrevision Field If the Revision and Subrevision Field contain the binary value 00100010 this signifies that the accessed AT MIO 16X board is at Revision C and Subrevision 2 This number can be very useful in tracking boards in the field and in answering questions conc
219. of the PGIA referenced to analog ground NRSE Nonreferenced single ended configuration has 16 single ended inputs with the negative input of the PGIA tied to AI SENSE and not connected to ground While reading the following paragraphs you may find it helpful to refer to the Analog Input Signal Connections section later in this chapter which contains diagrams showing the signal paths for the three configurations DIFF Input Eight Channels DIFF input means that each input signal has its own reference and the difference between each signal and its reference is measured The signal and its reference are assigned an input channel This is the recommended configuration With this input configuration the AT MIO 16X can monitor up to eight different analog input signals This configuration is selected via software See the configuration memory register and Table 4 9 in Chapter 4 Register Map and Descriptions The results of this configuration are as follows One of Channels 0 through 7 is tied to the positive input of PGIA e One of Channels 8 through 15 is tied to the negative input of the e Multiplexer control is configured to control up to eight input channels AI SENSE may be driven by the board analog input ground or left unconnected Considerations for using the DIFF input configuration are discussed in the Signal Connections section later in this chapter Figure 2 8 shows a schematic diagram of this c
220. olar analog output configuration The formula for the voltage output versus digital code for a unipolar analog output configuration 15 as follows Vout Vref digital code 65 536 where Vf is the reference voltage applied to the analog output channel The digital code in the above formula is a decimal value ranging from 0 to 65 535 Table 4 10 Analog Output Voltage Versus Digital Code Unipolar Mode Digital Code Voltage Output Decimal Vier 10 V OV 152 6 UV 2 5 V 5V 75N 9 999847 V The formula for the voltage output versus digital code for a bipolar analog output configuration in two s complement form is as follows Vout Vref digital code 32 768 AT MIO 16X User Manual 4 30 National Instruments Corporation Chapter 4 Register Map and Descriptions where V efis the positive reference voltage applied to the analog output channel The digital code in the preceding formula is a decimal value ranging from 32 768 to 432 767 Table 4 11 Analog Output Voltage Versus Digital Code Bipolar Mode Digital Code Voltage Output Hex Reference 10 V 10 V 9 999695 V 9 999695 V Bit descriptions for the registers making up the Analog Output Register Group are given on the following pages National Instruments Corporation 4 31 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 DACO Register Writing to the DACO Register loads the value written to the analog output DAC Channel 0 in im
221. on circuitry Digital I O circuitry Timing I O circuitry RTSI bus interface circuitry The internal data and control buses interconnect the components The theory of operation of each of these components is explained in the remainder of this chapter PC I O Channel Interface Circuitry The AT MIO 16X board is a full size 16 bit PC I O channel adapter The PC I O channel consists of a 24 bit address bus a 16 bit data bus a DMA arbitration bus interrupt lines and several control and support signals The components making up the AT MIO 16X PC I O channel interface circuitry are shown in Figure 3 2 AT MIO 16X User Manual 3 2 National Instruments Corporation Chapter 3 Theory of Operation Address Address Address Register Bus Latches Decoder Selects PCI O Channel Read and Write I O Channel Timing Signals Control Lines Interface Data Buffers Internal Data Bus 5 S S Q e 16 DMA Request DMA Request Control DMA Circuitry AT MIO 16X Acknowledge DMA Acknowledge and Terminal Count IRQ Interrupt AT MIO 16X Control Interrupt Circuitry Request Figure 3 2 PC I O Channel Interface Circuitry Block Diagram The PC I O channel interface circuitry consists of address latches address decoder circuitry data buffers PC I O channel interface timing signals interrupt circuitry and DMA arbitration circuitry The PC I O channel interface circuitry generates the signals n
222. on equipment However because the internal voltage reference drifts slightly with time and temperature it may be necessary to redetermine its value every year or whenever operating the board at an ambient temperature that is more than 10 C from the temperature at which the reference value was last determined The value of the reference is initially determined at the factory at a room temperature of 25 C After the value of the reference is determined the value should be stored in the EEPROM so that it can be used by the input and output calibration routines The calibration procedure which determines the reference value is explained in the Reference Calibration section later in this chapter Locations have been provided in the EEPROM to accommodate user calibration constants see Figure 6 1 For best measurement results the AT MIO 16X onboard reference needs to be measured to 10 001596 15 ppm accuracy According to standard practice the equipment used to calibrate the AT MIO 16X should be 10 times as accurate that is the equipment should have 0 00015 1 5 ppm rated accuracy Practically speaking calibration equipment with four times the accuracy of the item under calibration is generally considered acceptable Four times the accuracy of the AT MIO 16X is 0 000375 3 75 ppm To redetermine the value of the reference on the AT MIO 16X board you will need the following equipment A precision DC voltage source usually a calibrator
223. one 120 hex AT GPIB Channel 5 Line 11 2 hex AT MIO 16 Channels 6 7 Line 10 220 hex AT MIO 16D Channels 6 7 Lines 5 10 220 hex AT MIO 16F 5 Channels 6 7 Line 10 220 hex AT MIO 16X None None 220 hex AT MIO 64F 5 None None 220 hex GPIB PCII Channel 1 Line 7 2B8 hex GPIB PCIIA Channel 1 Line 7 02 1 hex GPIB PCIII Channel 1 Line 7 280 hex Lab PC Channel 3 Line 5 260 hex PC DIO 24 None Line 5 210 hex PC DIO 96 None Line 5 180 hex PC LPM 16 None Line 5 260 hex PC TIO 10 None Line 5 1A0 hex These settings are software configurable and are disabled at startup time Table 2 2 Switch Settings with Corresponding Base I O Address and Base I O Address Space Switch Setting Base I O Address Base I O Address Space A9 A8 A7 A6 AS hex Used hex 000 E00 Reserved 100 100 11F 120 120 13F 140 140 15F 160 160 17F 180 180 19F 1A0 1A0 1BF 1 0 1C0 1DF 1 0 1E0 200 200 21F 220 23F continues x x m cococococcccocooco OHH ha HOOO O OH OGOH SS T OF OH OF OY 1 1 1 1 1 1 1 1 0 0 National Instruments Corporation 2 5 AT MIO 16X User Manual Configuration and Installation Chapter 2 Table 2 2 Switch Settings with Corresponding Base I O Address and Base I O Address Space Continued Switch Setting Base I O Address Base I O Address Space A9 8 7 A6 AS hex Used hex 240 25F 260 27F 280 29F 2A0 2BF 2C0 2DF 2E0 2FF 300 3IF 32
224. onfiguration National Instruments Corporation 2 7 AT MIO 16X User Manual Configuration and Installation Chapter 2 RSE Input 16 Channels RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the AT MIO 16X board The negative input of the differential input amplifier is tied to the analog ground This configuration is useful when measuring floating signal sources See the Types of Signal Sources section later in this chapter for more information With this input configuration the AT MIO 16X can monitor up to 16 different analog input signals This configuration is selected via software See the configuration memory register and Table 4 9 in Chapter 4 Register and Descriptions results of this configuration are as follows e The negative input of the is tied to the signal ground e Multiplexer outputs are tied together into the positive input of PGIA e Multiplexer control is configured to control up to 16 input channels e AI SENSE may be driven by the board analog input ground or left unconnected Considerations for using the RSE configuration are discussed in the Signal Connections section later in this chapter Figure 2 18 shows a schematic diagram of this configuration NRSE Input 16 Channels NRSE input means that all input signals are referenced to the same common mode voltage but this common mode volta
225. or one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Table 2 5 summarizes the recommended input configuration for both types of signal sources Table 2 5 Recommended Input Configurations for Ground Referenced and Floating Signal Sources Type of Signal Recommended Input Configuration Ground referenced nonisolated outputs plug in instruments NRSE Floating batteries thermocouples isolated outputs DIFF with bias resistors RSE Differential Connection Considerations DIFF Input Configuration Differential connections are those in which each AT MIO 16X analog input signal has its own reference signal or signal return path These connections are available when the AT MIO 16X is configured in the DIFF input mode Each input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When the AT MIO 16X is configured for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration up to eight analog input channels are available Differential input connections should be used when any of the following conditions are present e You are connecting eight or fewer signals to the AT MIO 16X Input signals
226. ored by the AT MIO 16X circuitry If this bit is cleared triggers from the EXTTRIG signal are able to initiate data acquisition sequences 4 18 National Instruments Corporation Chapter 4 Register Map and Descriptions Status Register 1 Status Register 1 contains 16 bits of AT MIO 16X hardware status information including interrupt analog input status analog output status and data acquisition progress Address Base address 18 hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp DAQCOMP DAQPROG ADCFIFOHF ADCFIFOEF DMATCA DMATCB OVERFLOW OVERRUN MSB 7 6 5 4 3 2 1 0 TMRREQ DACCOMP DACFIFOFF DACFIFOHF DACFIFOEF EEPROMDATA EEPROMCD CFGMEMEF LSB Bit Name Description 15 DAQCOMP Data Acquisition Complete This bit reflects the status of the data acquisition termination signal If DAQCOMP is set and either OVERFLOW or OVERRUN is also set the current acquisition sequence ended on an error condition If DAQCOMP is set and neither OVERFLOW nor OVERRUN is set the data acquisition operation has completed without error When DAQCOMP is set and ADCREQ in Command Register 3 is also set enabled interrupt or DMA requests are generated until the ADC FIFO is empty DAQCOMP is cleared by strobing the DAQ Clear Register 14 DAQPROG Data Acquisition Progress This bit indicates whether a data acquisition operation is in progress If DAQPROG is set a data acquisition operation i
227. owing state Analog input error flags OVERFLOW and OVERRUN are cleared Pending data acquisition interrupt requests are cleared e ADC FIFO is emptied e DAQCOMP flag in the Status Register is cleared Empty the ADC FIFO before starting any A D conversions This action guarantees that the A D conversion results read from the FIFO are the results from the initiated conversions and are not left over results from previous conversions Programming Single Analog Input Channel Configurations The analog input channel gain mode and range for single conversion and single channel acquisition are selected by writing a single configuration value to the CONFIGMEM Register This register offers a window into the channel configuration memory The CONFIGMEMLD Register must then be strobed to load this channel configuration information See the CONFIGMEM Register bit description earlier in this chapter for analog input channel and configuration bit patterns Set up the bits as given in the CONFIGMEM Register bit description and write to the CONFIGMEM Register Remember that the channel configuration memory must be first initialized with an access to the CONFIGMEMCLR Register Once the channel configuration memory is configured it needs to be written to only when the analog input channel or configuration settings need to be changed AT MIO 16X User Manual 5 10 National Instruments Corporation Chapter 5 Programming Programming Multiple Analog Input
228. pending on which channel requested a DMA transfer If single channel interleaved DMA is selected for writing data to the DACs then one buffer services both DAC 0 and DAC 1 This is accomplished by interleaving the data in the buffer first location in the buffer should hold the first value to be transferred to DAC 0 the second should hold the first value to be transferred to DAC 1 the third should hold the second value to be transferred to DAC and so on AT MIO 16X User Manual 5 30 National Instruments Corporation Chapter 5 Programming If dual channel DMA operation has been selected for DMA requesting service DMA Channel A and memory buffer A DMA A are served first When a DMA terminal count is received the board automatically switches the DMA operation to DMA Channel B and memory buffer B DMA B Therefore the board can collect data to or from one buffer and simultaneously service data in another buffer If the DMA controller is programmed for auto reinitialize mode DMA A and DMA B are continuously served in turn If dual channel DMA operation has been selected to service both analog outputs memory buffer A DMA Channel A and memory buffer B DMA Channel B are concurrently serviced with buffer A serving DAC 0 and buffer B serving DAC 1 Interrupt Programming Seven different interrupts are generated by the AT MIO 16X board e Whenever a conversion is available to be read from the ADC FIFO Whenever the ADC FIFO i
229. r Diagram National Instruments Corporation 2 1 AT MIO 16X User Manual Configuration and Installation Chapter 2 Figure 2 2 AT MIO 16X with 68 Pin I O Connector Parts Locator Diagram AT MIO 16X User Manual 2 2 National Instruments Corporation Chapter 2 Configuration and Installation Board Configuration The AT MIO 16X contains one DIP switch to configure the base address selection for the AT bus interface The remaining resource selections such as DMA and interrupt channel selections are determined by programming the individual registers in the AT MIO 16X register set The general location of the registers in the I O space of the PC is determined by the base address selection whereas the specific location of the registers within the register set is determined by the AT MIO 16X decode circuitry AT Bus Interface Operation of the AT MIO 16X multifunction I O board is controlled through accesses to registers within the board register set Some of the registers in the register set retain data written to them to determine board operation Other registers in the register set contain important status information necessary for proper sequencing of events Still other registers perform functions by accessing them either by reading from or writing to their location However these registers do not retain pertinent data when written to nor do they provide pertinent status information when read The PC defines accesses to plug in boards to
230. r Manual 5 4 National Instruments Corporation Chapter 5 Programming Generating a Single Conversion An A D conversion can be initiated in one of two ways a software generated pulse or a hardware pulse To initiate a single A D conversion through software access the Single Conversion Register To initiate a single A D conversion through hardware apply an active low pulse to the EXTCONV pin on the AT MIO 16X I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for EXTCONV signal specifications Once an A D conversion is initiated the ADC automatically stores the result in the ADC FIFO at the end of its conversion cycle Reading a Single Conversion Result A D conversion results are available when ADCFIFOEF is set in the Status Register and be obtained by reading the ADC FIFO Register To read the A D conversion result use the following steps 1 Read the Status Register 16 bit read 2 If the OVERRUN or OVERFLOW bits are set an error occurred and data was lost 3 If the ADCFIFOEF bit is set read the ADC FIFO Register to obtain the result Reading the ADC FIFO Register removes the A D conversion result from the ADC FIFO and clears the ADCFIFOEF bit if no more values remain in the FIFO The ADCFIFOEF bit indicates whether one or more A D conversion results are stored in the ADC FIFO If the ADCFIFOEF bit is not set the ADC FIFO is empty and reading the ADC
231. r Nonreferenced or Floating Signal Sources Figure 2 8 shows how to connect a floating signal source to an AT MIO 16X board configured in the DIFF input mode The AT MIO 16X analog input circuitry must be configured for DIFF input to make these types of connections Configuration instructions are included in Chapter 4 Register Map and Descriptions National Instruments Corporation 2 19 AT MIO 16X User Manual Configuration and Installation Chapter 2 Floating Signal Source V Measured m Voltage Input Multiplexers AISENSE I O Connector AT MIO 16X Board in the DIFF Input Configuration Figure 2 8 Differential Input Connections for Nonreferenced Signals Figure 2 8 shows two bias resistors connected in parallel with the signal leads of a floating signal source If the source is truly floating it is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to AI GND The best way is simply to connect the positive side of the signal to the positive input of the and connect the negative side of the signal to AI GND as well as to the negative input of the PGIA This works well for DC coupled sources with low source impedance less than 100 2 However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive
232. r ground referenced and floating signal sources table 2 18 single ended connections 2 22 to 2 23 H hardware installation 2 11 resetting after data acquisition operation 5 16 to 5 17 I immediate update mode 3 14 input configurations See also CONFIGMEM Register common mode signal rejection 2 23 to 2 24 differential input floating signal sources 2 19 to 2 21 general considerations 2 18 ground referenced signal sources 2 18 to 2 19 National Instruments Corporation Index nonreferenced or floating signal sources 2 19 to 2 21 recommended configurations for ground referenced and floating signal sources table 2 18 single ended connections floating signal RSE sources 2 22 general considerations 2 21 to 2 22 grounded signal NRSE sources 2 22 to 2 23 input mode See analog input configuration input multiplexer address selection bits CHANSEL lt 3 0 gt 4 27 description 3 6 input polarity and range configuring 2 9 actual range and measurement precision versus input range selection and ain table 2 9 considerations for selecting ranges 2 9 installation See also configuration hardware installation 2 11 unpacking the AT MIO 16X 1 8 INTCHB lt 2 0 gt bit 4 14 internal update counter selecting 5 23 interrupts bit settings generation of interrupts 4 13 to 4 14 interrupt level selection 4 15 configuration 2 6 controlled by ADCREQ bit 4 13 to 4 14 default settings for National In
233. r input Unipolar input means that the input voltage range is between 0 and Vref where Vref is a positive reference voltage Bipolar input means that the input voltage range is between Vref and Vye AT MIO 16X has a maximum unipolar input range of 10 V and a maximum bipolar input range of 20 V 10 V Polarity and range settings are programmed on a per channel basis through the configuration memory register Considerations for Selecting Input Ranges Input polarity and range selection depend on the expected input range of the incoming signal A large input range can accommodate a large signal variation but lowers the voltage resolution Choosing a smaller input range increases the voltage resolution but may result in the input signal going out of range For best results the input range should be matched as closely as possible to the expected range of the input signal For example if the input signal is certain not to be negative below 0 V a unipolar input is best However if the signal is ever negative inaccurate readings will occur if unipolar input polarity is used The software programmable gain on the AT MIO 16X increases its overall flexibility by matching the input signal ranges to those that the AT MIO 16X analog to digital converter ADC can accommodate The AT MIO 16X board has gains of 1 2 5 10 20 50 and 100 and is suited for a wide variety of signal levels With the proper gain setting the full resolution of the ADC
234. rated without additional external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time The 16 is calibrated at the factory in both unipolar and bipolar modes and these values are also permanently stored in the EEPROM Calibration constants can be read from the EEPROM then written to the calibration DACS that adjust pregain offset postgain offset and gain errors associated with the analog input section There is a 12 bit pregain offset calibration DAC an 8 bit coarse postgain offset calibration DAC an 8 bit fine postgain offset calibration DAC an 8 bit coarse gain calibration DAC and an 8 bit fine gain calibration DAC Functions are provided with the board to calibrate the analog input section access the EEPROM on the board and write to the calibration DACs When the AT MIO 16X leaves the factory locations 96 through 127 of the EEPROM are protected and cannot be modified Locations 0 through 95 are unprotected and can be used to store alternate calibration constants for the differing conditions under which the board is used Refer to Chapter 6 Calibration Procedures for additional calibration information Data Acquisition Timing Circuitry This section details the different methods of acquiring A D data from a single channel or multiple channels Prior to any of these operations the channel gain mode and range settings must be configured This is
235. ration for example 29 29th 124 Reserved 123 Board Code AT MIO 16X 2 122 Revision and Sub Revision Field 121 Configuration Memory Depth 120 ADC and DAC FIFO Depths 119 Factory Reference Value MSB 118 Factory Reference Value LSB 117 Area Information 116 Factory ADC Bipolar Pregain Offset MSB 115 Factory ADC Bipolar Pregain Offset LSB 114 Factory DAC Channel Bipolar Offset 113 Factory DAC Channel 0 Bipolar Offset 112 Factory DAC Channel Bipolar Gain 111 Factory DAC Channel 0 Bipolar Gain 110 Factory ADC Bipolar Postgain Offset Fine 109 Factory ADC Bipolar Postgain Offset Coarse 108 Factory ADC Bipolar Gain Fine 107 Factory ADC Bipolar Gain Coarse 106 Area Information 105 Factory ADC Unipolar Pregain Offset MSB 104 Factory ADC Unipolar Pregain Offset LSB 103 Factory DAC Channel Unipolar Offset 102 Factory DAC Channel 0 Unipolar Offset 101 Factory DAC Channel 1 Unipolar Gain 100 Factory DAC Channel 0 Unipolar Gain Factory ADC Unipolar Postgain Offset Fine Factory ADC Unipolar Postgain Offset Coarse 97 Factory ADC Unipolar Gain Fine 96 Factory ADC Unipolar Gain Coarse AT MIO 16X User Manual 6 2 National Instruments Corporation Chapter 6 Calibration Procedures When the AT MIO 16X board is powered on or the conditions under which it is operating change the calibration DACS should be loaded with values from the EEPROM or if desired the board can be recalibrated The AT MIO 16X calibration pr
236. rce has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 KO to 1 If the source has high output impedance you should balance the signal path as described above using the same value resistor on both the positive and negative inputs and you should be aware that there is some gain error from loading down the source The PGIA obtains its input DC bias currents from the DC paths to ground These currents are typically less than 1 nA but they contribute significantly to error whenever the source has more than 1 impedance or is AC coupled If the source is DC coupled the resulting DC offset is less than 1 nA times the DC source resistance For instance a 1 kQ source will produce no more than 1 uV of input offset 0 33 LSB at a gain of 100 bipolar range If the source is AC coupled then the resulting DC offset is less than 1 nA times the sum of the two bias resistors For example if two 100 kQ bias resistors used there could be as much as 200 uV of input offset voltage 0 66 LSB at a gain of 1 bipolar range Single Ended Connection Considerations Single ended connections are those in which all AT MIO 16X analog input signals are referenced to one common ground The input signals are tied to the positive input of the PGIA and their common ground point is tied to
237. read and write operations are available on the PC byte 8 bit and word 16 bit Table 4 1 shows the size of each AT MIO 16X register For example reading the ADC FIFO Register requires a 16 bit word read operation at the selected address whereas writing to the RTSI Strobe Register requires an 8 bit byte write operation at the selected address These register size accesses must be adhered to for proper board operation Performing a byte access on a word location is an invalid operation and should be avoided The converse is also true Performing a word access on a byte location is also an invalid operation and should be avoided You should pay particular attention to the register sizes they are very important AT MIO 16X User Manual 4 2 National Instruments Corporation Chapter 4 Register Map and Descriptions Register Description Format The remainder of this register description chapter discusses each of the AT MIO 16X registers in the order shown in Table 4 1 Each register group is introduced followed by a detailed bit description of each register The individual register description gives the address type word size and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB shown on the left bit 15 for a 16 bit register bit 7 for an 8 bit register and the LSB shown on the right bit 0 A square is used to represent each bit Each bit is labeled with a
238. rite FF42 to the Am9513A Command Register to load Counter 2 6 Write FFF2 to the Am9513A Command Register to decrement Counter 2 7 Write FF22 to the Am9513A Command Register to arm Counter 2 After you complete this programming sequence Counter 2 is configured to count the desired interval after each rising edge on GATE2 is encountered The terminal count active low edge will restart the waveform generation process Servicing Update Requests Updating the DACS using a timer signal can be handled using either polled I O interrupts or DMA requests Upon the application of a falling edge signal to the TMRTRIG signal both DACs are updated and TMRREQ in Status Register 1 is set and if DMA or interrupts enabled a request is generated TMRTRIG can be connected to selected internal signals on the National Instruments Corporation 5 25 AT MIO 16X User Manual Programming Chapter 5 RTSI bus with set or the external signal EXTTMRTRIG with A4RCV cleared In the polled I O mode the TMRREQ signal must be monitored in the Status Register to determine when the previous value has been updated to the DAC and a new value is required The most desirable solution involves the use of interrupts because the PC is not dedicated to monitoring the Status Register If interrupts are enabled an interrupt occurs when TMRREQ is set In interrupt mode must be cleared using the TMRREQ Clear Register before exiting the interrupt ro
239. rporation C 29 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 30 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 31 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 32 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 33 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 34 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 35 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 36 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 37 16 User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 38 National Instruments Corporation Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 39 AT MIO 16X User Manual AMD Am9513A Data Sheet Appendix C AT MIO 16X User Manual C 40 National Instruments Corporation Appendix D Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation Filling out a copy of the Technical Support Form
240. s in progress If DAQPROG is cleared the data acquisition operation has completed 13 ADCFIFOHF ADC FIFO Half Full Flag This bit reflects the state of ADC FIFO If the appropriate conversion interrupts are enabled see Table 4 3 and ADCFIFOHF is clear the current interrupt indicates at least 256 A D conversions are available in the ADC FIFO To clear the interrupt read the ADC FIFO until it is empty ADCFIFOEF is clear If ADCFIFOHF is set less than 256 ADC conversions are available in the ADC FIFO National Instruments Corporation 4 19 AT MIO 16X User Manual Register Map and Descriptions Bit 12 11 10 Name ADCFIFOEF DMATCA DMATCB OVERFLOW OVERRUN TMRREQ AT MIO 16X User Manual Chapter 4 Description continued FIFO Empty Flag This bit reflects the state of the FIFO If ADCFIFOEF is set one or more A D conversion results can be read from the ADC FIFO If the appropriate conversion interrupts are enabled see Table 4 3 and ADCFIFOEF is set the current interrupt indicates that A D conversion data is available in the ADC FIFO To clear the interrupt the FIFO must be read until it is empty If ADCFIFOEF is cleared ADC FIFO is empty and no conversion interrupt request is asserted DMA Terminal Count Channel A DMATCA reflects the status of the DMA process on the selected DMA Channel A When the DMA operation is completed DMATCA goes high and remains high unt
241. s more than half full e Whenever a data acquisition sequence completes Whenever a DMA terminal count is received e Whenever a falling edge on TMRTRIG of the Am9513A is detected Whenever the DAC FIFO is less than full Whenever the DAC FIFO is half full These interrupts can be enabled either individually or in any combination In any of the interrupt modes it is a good practice to confirm the source of the interrupt through reading Status Register 1 If ADC FIFOEF or ADC FIFOHF is true a conversion interrupt has occurred Reading from the ADC FIFO Register clears these interrupt conditions Writing to the DAQ Clear Register also clears these conversion interrupts If DAQCOMP is set the interrupt results from the completion of a data acquisition operation This interrupt is cleared by writing to the DAQ Clear Register If TMRREQ is set a DAC update interrupt has occurred Writing to the TMRREQ Clear Register clears this interrupt condition In the case that waveform generation is disabled in Command Register 2 the DACs are not updated and the TMRREQ signal can be used as a timer interrupt If DMATCA or DMATCB is set a DMATC INT has occurred on either DMA Channel A or B Writing to the DMATCA or DMATCB Clear Register clears this interrupt condition National Instruments Corporation 5 31 AT MIO 16X User Manual Chapter 6 Calibration Procedures This chapter discusses the calibration resources and procedures for the AT MI
242. se registers simultaneously affects all register bits You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers This software copy can then be read to determine the status of the write only registers To change the state of a single bit without disturbing the remaining bits set or clear the bit in the software copy and write the software copy to the register Resource Allocation Considerations Counters 1 2 and 5 of the Am9513A Counter Timer are available at the I O connector for general purpose use These counters can only be used so long as this does not conflict with an internal operation in progress on the board that is already using the desired counter Table 5 1 lists the five counters in the Am9513A Counter Timer and enumerates what they are used for in each operation Table 5 1 Am9513A Counter Timer Allocations DAQ Operation Waveform Operation Scan division Updating cycle counting pulsed waveform Scan division Updating cycle counting pulsed waveform Sample interval Updating Sample count N A Sample count gt 65 536 Updating cycle counting Table 5 1 provides a general overview of the AT MIO 16X resources to ensure there are no conflicts when using the counters timers As an example if an interval scanning data acquisition sequence that requires less than 65 537 samples is in operation Counters 2 3 and 4 of the
243. sired signal routing a Clear the OUTEN bit for all input pins and for all unused pins b Select the signal source pin for all output pins by setting bits S2 through SO to the source pin number c Setthe OUTEN bit for all output pins National Instruments Corporation 5 29 AT MIO 16X User Manual Programming Chapter 5 2 Fori 0 to 55 follow these steps a Copy bit i of the 56 bit pattern to bit 0 of an 8 bit temporary variable b Write the temporary variable to the RTSI Switch Shift Register 8 bit write 3 Write 0 to the RTSI Switch Strobe Register 8 bit write This operation loads the 56 bit pattern into the RTSI switch At this point the new signal routing goes into effect Step 2 can be completed by simply writing the low order 8 bits of the 56 bit pattern to the RTSI Switch Shift Register then shifting the 56 bit pattern right once and repeating this two step operation a total of 56 times Only bit 0 of the word written to the RTSI Switch Shift Register is used The higher order bits are ignored Programming DMA Operations The AT MIO 16X can be programmed so that the ADCFIFOEF generates DMA requests every time one or more A D conversion values are stored in the ADC FIFO when the ADCFIFOHF is low and the FIFO is half full and when the DACFIFO requires at least one data value DACFIFOFF is set and when the DACFIFO is less than half full DACFIFOHF is set There are two DMA modes single channel transfer and d
244. strument products table 2 5 PC I O channel interface 3 4 programming 5 31 interval channel scanning definition 5 7 programming 5 8 to 5 10 interval scanning data acquisition timing 3 11 to 3 12 INTGATE bit 4 6 I O connector pin assignments 50 pin connector 2 12 B 1 68 pin connector 2 13 B 2 I O INT bit 4 12 J jumpers and switches base I O address factory settings 2 3 example base I O address switch settings illustration 2 4 AT MIO 16X User Manual Index switch settings with base I O address and address space table 2 5 to 2 6 L LabWindows software 1 4 LASTONE bit 5 11 linear errors equivalent gain errors in 16 bit systems table A 3 equivalent offset errors in 16 bit systems table A 2 gain error A 2 postgain offset error A 2 pregain offset error A 2 M multiple analog input channel programming 5 11 multiple channel scanned data acquisition timing 3 10 to 3 12 continuous scanning 3 11 data acquisition rates 3 12 interval scanning 3 11 to 3 12 posttrigger data acquisition timing 3 11 multiple channel scanning acquisition rates specifications A 4 to A 5 typical settling times table A 4 multiplexer input See input multiplexer N NI DAQ software 1 3 noise minimizing environmental noise 2 34 to 2 35 system noise A 4 nonlinear errors 3 to 4 differential nonlinearity A 4 relative accuracy A 3 typical relative accuracy of analog input circuitry illustr
245. struments Corporation Theory of Operation Chapter 3 Analog Input Circuitry The analog input circuitry consists of an input multiplexer multiplexer mode selection circuitry a PGIA calibration circuitry a 16 bit sampling ADC and a 16 bit 512 word deep FIFO A D Converter The ADC is a 16 bit sampling successive approximation ADC With 16 bit resolution the converter can resolve its input range into 65 536 different steps This resolution generates a 16 bit digital word that represents the value of the input voltage level with respect to the converter input range The ADC has two input modes that are software selectable on the AT MIO 16X board on per channel basis 10 to 10 V or 0 to 10 V The ADC on the AT MIO 16X is guaranteed to convert at a rate of at least 100 ksamples sec The data format circuitry is software programmable to generate either straight binary numbers or two s complement numbers In unipolar mode values returned from the ADC are straight binary and result in a range of 0 to 65 535 In bipolar mode the ADC returns two s complement values resulting in a range of 32 768 to 32 767 Analog Input Multiplexers The input multiplexer consists of a dual eight to one CMOS analog input multiplexer preceded by input protection resistors and has 16 analog input channels Analog input overvoltage protection is 25 V powered on and 15 V powered off Input signals should be in the range of 10 to 10 V for bipolar oper
246. t Bit Map Not applicable no bits used Strobe Effect Initiates an ADC level calibration not a system level calibration Note The BUSY signal in Status Register 2 should be monitored to determine when the AT MIO 16X ADC calibration cycle is finished The calibration cycle takes approximately 1 25 sec to complete All other conversions must be inhibited until the ADC calibration cycle is completed After the calibration cycle the ADC must be initialized by generating a conversion The Single Conversion Register should be accessed to start an A D conversion After the conversion is completed the result will be stored in the ADC FIFO Because this data is meaningless it must be cleared by reading the value from the FIFO or accessing the DAQ Clear Register AT MIO 16X User Manual 4 40 National Instruments Corporation Chapter 4 Register Map and Descriptions DAC Event Strobe Register Group The DAC Event Strobe Register Group consists of three registers that when written to cause the occurrence of certain events on the AT MIO 16X board such as clearing flags and updating the analog output DACSs Bit descriptions of the three registers making up the DAC Event Strobe Register Group are given on the following pages National Instruments Corporation 4 41 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 TMRREQ Clear Register Accessing the TMRREQ Clear Register clears the TMRREQ and DACCOMP bits after a TMR
247. tes the circuitry to the external reference and then reads the internal reference This value is stored as a two s complement binary number in the onboard EEPROM for subsequent use by the analog input calibration routines Because the onboard reference is very stable with respect to time and temperature it is seldom necessary to use the reference calibration routine Every year should be sufficient or whenever operating the board at an ambient temperature that is more than 10 C from the temperature at which the reference value was last determined Factory calibration is performed at approximately 25 C Analog Input Calibration To null out error sources that compromise the quality of measurements the input calibration routine calibrates the analog input circuitry by adjusting the following potential sources of error e Pregain offset offset error at the input of the PGIA Postgain offset offset error at the input of the ADC e Gain error of the analog input circuitry Pregain offset contributes gain dependent error to the analog input system This offset is multiplied by the gain of the PGIA To calibrate this offset the routine grounds the inputs of the PGIA measures the input at two different gains and adjusts CALDACS until the measured offset in LSBs is independent of the gain setting Postgain offset 1s the total of the voltage offsets contributed by the circuitry from the output of the PGIA to the ADC input including the ADC s
248. the negative input of the PGIA When the AT MIO 16X is configured for single ended input up to 16 analog input channels are available Single ended input connections can be used when all input signals meet the following criteria e Input signals are high level greater than 1 V Leads connecting the signals to the AT MIO 16X are less than 15 ft e All input signals share a common reference signal at the source or are floating DIFF input connections are recommended for greater signal integrity if any of the preceding criteria are not met The AT MIO 16X can be software configured for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the AT MIO 16X provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the AT MIO 16X should not supply one If using the AT MIO 16X with a 50 pin I O connector in single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations Moreover the amount of coupling varies among channels especially if a ribbon cable is used The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electri
249. the onboard calibration circuitry of the AT MIO 16X This circuitry uses a stable internal 5 VDC reference that is measured at the factory against a higher accuracy reference then its value is permanently stored in the EEPROM on the AT MIO 16X With this stored reference value the AT MIO 16X board can be recalibrated without external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time The AT MIO 16X is factory calibrated in both unipolar and bipolar modes and these values are also permanently stored in the EEPROM Calibration constants can be read from the EEPROM then written to the calibration DACs that adjust offset and gain errors associated with each analog output channel For each DAC channel there is an 8 bit offset calibration DAC and an 8 bit gain calibration DAC Functions are provided with the board to calibrate the analog output section access the EEPROM on the board and write to the calibration DACs To calibrate an analog output channel the appropriate DAC signal must be wrapped back to the analog input circuitry When the AT MIO 16X leaves the factory locations 96 through 127 of the EEPROM are protected and cannot be modified Locations 0 through 95 are unprotected and can be used to store alternate calibration constants for the differing conditions under which the board is used Refer to Chapter 6 Calibration Procedures for additional calibration in
250. the timing signal is removed A special case of this mode occurs when the buffer fits entirely within the DAC FIFO where it is cycled through If this is true and the CYCLICSTOP bit in Command Register 4 is set DAC updating stops at the next end of buffer This provides a known final value for the DACs To update the analog output DACs in cyclic waveform generation mode the following sequence of programming steps in Figure 5 7 must be followed The instructions in the blocks of the following flow chart are enumerated in the Waveform Generation Programming Functions section later in this chapter AT MIO 16X User Manual 5 18 National Instruments Corporation Chapter 5 Programming Clear the analog output circuitry including the DAC FIFO Yes Set the A4RCV bit in Clear the A4RCV bit in Command Register 2 Command Register 2 Select the update counter via RTSI programming Program the update interval counter Set the waveform generation mode Enable updating Service update requests Figure 5 7 Cyclic Waveform Programming Programmed Cycle Waveform Generation A superset of the waveform functionality exists if DAC data buffer is less than or equal to 2 048 for one channel or less than or equal 1 024 per DAC for two channels In these cases the entire buffer resides wholly within the DAC FIFO where the waveform circuitry cycles through the buffer when the end is reached This removes a large burden on the PC bus for continually updat
251. time and then restarting the sequence This process proceeds ad infinitum until the timer trigger is removed or disabled or the CYCLICSTOP bit is set Digital I O Circuitry The AT MIO 16X has eight digital I O lines These eight digital I O lines are divided into two ports of four lines each and are located at pins ADIO lt 3 0 gt and BDIO lt 3 0 gt on the I O connector Figure 3 16 shows a block diagram of the digital I O circuitry Digital 4 Output Register DOUTO ENABLE DO REG WR DOUTI DAIA lt 7 4 gt Digital 4 Output Register BDIO lt 3 0 gt I O Connector PC I O Channel B A 7 4 EXTSTROBE EXT STROBE WR Figure 3 16 Digital I O Circuitry Block Diagram The digital I O lines are controlled by the Digital Output Register and monitored by the Digital Input Register The Digital Output Register is an 8 bit register that contains the digital output values for both ports 0 and 1 When port 0 is enabled bits 3 0 in the Digital Output Register are driven onto digital output lines ADIO lt 3 0 gt When port 1 is enabled bits lt 7 4 gt in the Digital Output Register are driven onto digital output lines BDIO lt 3 0 gt National Instruments Corporation 3 19 AT MIO 16X User Manual Theory of Operation Chapter 3 Reading the Digital Input Register returns the state of the digital I O lines Digital I O lines ADIO lt 3 0 gt are connected to bits lt 3 0 gt of the Digital Input Register Di
252. ting to the Digital Output Register controls the eight AT MIO 16X digital IO lines The Digital Output Register controls both ports A and B When either digital port is enabled the pattern contained in the Digital Output Register is driven onto the lines of the digital port Address Base address 1C hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 MSB 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIOI BDIOO ADIO3 ADIO2 ADIO ADIOO LSB Bit Name Description 15 8 0 Reserved These bits must always be set to zero 7 4 BDIO lt 3 0 gt These four bits control the digital lines BDIO lt 3 0 gt The bit DIOPBEN in Command Register 2 must be set for BDIO lt 3 0 gt to be driven onto the digital lines BDIO lt 3 0 gt 3 0 ADIO lt 3 0 gt These four bits control the digital lines ADIO lt 3 0 gt The bit DIOPAEN in Command Register 2 must be set for ADIO lt 3 0 gt to be driven onto the digital lines ADIO lt 3 0 gt AT MIO 16X User Manual 4 56 National Instruments Corporation Chapter 4 Register Map and Descriptions RTSI Switch Register Group The two registers making up the RTSI Switch Register Group allow the AT MIO 16X RTSI switch to be programmed for routing of signals on the RTSI bus trigger lines to and from several AT MIO 16X signal lines The RTSI switch is programmed by shifting a 56 bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register The routing pattern
253. tion Apply a trigger Service the data acquisition operation Figure 5 5 Interval Scanning Data Acquisition Programming Setting the SCANEN bit in conjunction with the DAQEN bit in Command Register 1 enables scanning during multiple A D conversions The SCANEN bit must be set regardless of the type of scanning used continuous or interval otherwise only a single channel is scanned National Instruments Corporation 5 9 AT MIO 16X User Manual Programming Chapter 5 Setting the SCN2 bit in Command Register 1 enables the use of a scan interval during multiple A D conversions The scan interval counter gives each cycle through the scan sequence a time interval The scan interval counter begins counting at the start of the scan sequence programmed into the channel configuration memory When the scan sequence terminates the next cycle through the scan sequence does not begin until the scan interval counter has reached its terminal count Be sure that the scan interval counter allows enough time for all conversions in a scan sequence to occur so that conversions are not missed Data Acquisition Programming Functions This section provides a detailed explanation of the functions necessary to program the analog input for single and multiple channel A D conversions Clearing the Analog Input Circuitry The analog input circuitry can be cleared by strobing the DAQ Clear Register This operation leaves the analog input circuitry in the foll
254. tional Instruments or to comment on our products The Glossary contains an alphabetical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics and symbols The ndex contains an alphabetical list of key terms and topics used in this manual including the page where you can find each one National Instruments Corporation xiii AT MIO 16X User Manual About This Manual Conventions Used in This Manual The following conventions are used to distinguish elements of text throughout this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept NI DAQ NI DAQ is used throughout this manual to refer to the NI DAQ software for DOS Windows LabWindows unless otherwise noted PC PC refers to the IBM PC AT and compatibles and to EISA personal computers Abbreviations acronyms metric prefixes mnemonics symbols and terms are listed in the Glossary Related Documentation The following document contains information that you may find helpful as you read this manual Personal Computer AT Technical Reference manual You may also want to consult the following Advanced Micro Devices manual if you plan to program the Am9513A Counter Timer used on the AT MIO 16X e Am9513A Am9513 System Timing Controller technical manual Customer Communication National Instruments want to receive your comments on our products and manuals We are i
255. tions Chapter 4 DMATCB Clear Register Accessing the DMATCB Clear Register clears the DMATCB signal in Status Register 1 and acknowledges the interrupt generated from the Channel B terminal counter interrupt When the selected DMA Channel B terminal count is reached the DMATCB signal in Status Register 1 is asserted If DMATC interrupts are enabled an interrupt will also be generated Address Base address 09 hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Clears the DMATCB signal in Status Register 1 and acknowledges an interrupt from a DMA Channel B terminal count AT MIO 16X User Manual 4 48 National Instruments Corporation Chapter 4 Register Map and Descriptions External Strobe Register Accessing the External Strobe Register location generates an active low signal at the EXTSTROBE output of the I O connector This signal has a minimum low time of 500 nsec The EXTSTROBE pulse is useful for several applications including generating external general purpose triggers and latching data into external devices for example from the digital output port Address Base address 1E hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Generates an active low pulse at the I O connector of at least 500 nsec duration National Instruments Corporation 4 49 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Calibration DAC
256. to 4 40 Calibration Register 4 40 CONFIGMEMCLR Register 4 35 4 4 5 10 5 11 CONFIGMEMLD Register 4 36 5 10 5 11 DAQ Clear Register 4 37 5 10 5 30 5 31 DAQ Start Register 4 38 register map 4 2 Single Conversion Register 4 39 ADC FIFO buffer ADC conversion timing illustration 3 8 analog input circuitry 3 7 interrupt programming 5 8 ADC FIFO Register clearing interrupts 5 31 description 4 24 to 4 25 reading single conversion result 5 5 servicing the data acquisition operation 5 16 BUSY bit 4 22 National Instruments Corporation ADCDSP bit 4 11 ADCFIFOEF bit description 4 20 DMA operations 5 30 interrupt programming 5 31 reading single conversion result 5 5 servicing data acquisition operation 5 16 ADCFIFOHF bit description 4 19 DMA operations 5 30 interrupt programming 5 31 servicing data acquisition operation 5 16 ADCFIFOREQ bit 4 18 ADCREQ bit 4 13 address decoder circuitry 3 3 address latches 3 3 address lines 3 3 ADIO lt 0 3 gt signal definition 2 14 B 3 digital I O circuitry 3 19 to 3 20 ADIO lt 3 0 gt bit 4 57 4 58 5 26 AI GND signal analog input signal connections 2 16 definition 2 14 B 3 differential connections 2 20 to 2 21 single ended connections 2 21 to 2 22 AI SENSE signal analog input signal connections 2 16 definition 2 14 B 3 DIFF input 2 7 NRSE input 2 8 RSE input 2 8 single ended connections 2 22 Am9513A Counter
257. truments Corporation Chapter 4 Register Map and Descriptions Command Register 1 Command Register 1 contains 11 bits that control AT MIO 16X serial device access and data acquisition mode selection The contents of this register are not defined upon power up and are not cleared after a reset condition This register should be initialized through software Address Base address 00 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 B MS 7 6 5 4 3 2 1 0 LSB Bit Name Description 15 EEPROMCS EEPROM Chip Select This bit controls the chip select of the onboard EEPROM used to store calibration constants When EEPROMCS is set the chip select signal to the EEPROM is enabled Before EEPROMCS is brought high SCLK should first be pulsed high to initialize the EEPROM circuitry 14 SDATA Serial Data This bit is used to transmit a single bit of data to the EEPROM and both of the calibration DACs 13 SCLK Serial Clock A low to high transition of this bit clocks data from SDATA into the EEPROM when EEPROMCS is set and the calibration DAC If EEPROMCS is cleared toggling SCLK does not affect the EEPROM Serial data is always loaded into the calibration DACS but the information is not updated until after the application of the appropriate load signal 12 SCANDIV Scan Divide This bit controls the configuration memory sequencing during scanned data acquisition If SCANDIV is set then sequencing is co
258. ual channel transfer Single channel DMA uses only channel A DMA signals while dual channel DMA uses signals for both Channel A and Channel B The DMA channels are selected through Command Register 2 To program the operation perform the following steps after the circuitry on the AT MIO 16X 15 set up 1 Set the appropriate mode bits in Command Register 3 to enable DMA request generation 2 Access the DMATCA and DMATCB Clear Registers the TMRREQ Clear Register the DAC Clear Register and the DAQ Clear Register 3 Program the DMA controller to service DMA requests from the AT MIO 16X board Refer to the IBM Personal Computer AT Technical Reference manual for more information on DMA controller programming 4 Ifa DMA terminal count is received after the DMA service write 0 to either the appropriate DMATC Clear Register to clear the DMATCA or DMATCB bits in Status Register 1 Once steps 1 through 3 are completed the DMA controller is programmed to acknowledge requests If analog input DMA is programmed the DMA controller automatically reads the ADC FIFO Register whenever an A D conversion result is available and then stores the result in a buffer in memory If the DMA controller has been programmed for analog output updating values from the buffer in memory are automatically written to the DAC upon receipt of a DMA request If both analog input and output DMA is selected then the DMA controller reads the FIFO or writes to the DACs de
259. uisition operation The counters do not need to be reprogrammed another data acquisition operation begins when a trigger is received If the next data acquisition operation requires the counters to be programmed differently the Am9513A counters that were used must be disarmed and reset Resetting a Single Am9513A Counter Timer To reset a particular counter in the Am9513A use the following programming sequence writes are 16 bit operations values given are hexadecimal The equation 2 ctr 1 means 2 raised to ctr 1 If ctr is equal to 4 then 2 ctr 1 results in 2 3 or 2 2 2 or 8 This result can also be obtained by shifting left three times AT MIO 16X User Manual 5 16 National Instruments Corporation Chapter 5 Write OxFFCO 2 ctr 1 to the Am9513A Command Register Write OxFFOO ctr to the Am9513A Command Register Write 0 0004 to the Am9513A Data Register Write OxFFOS ctr to the Am9513A Command Register Write 0x0003 to the Am9513A Data Register Write OxFF40 2 ctr 1 to the Am9513A Command Register Write OxFF40 2 ctr 1 to the Am9513A Command Register Programming Disarm X mode Point to the Counter X mode register Store the Counter X mode value Point to the Counter X load register Store a nonterminal count value Load Counter X Load Counter X guarantee nonterminal count state Figure 5 6 Resetting an Am9513A Counter Timer N
260. ut not through the DAC FIFO If DACGATE is cleared updating of and writing to the DACs proceeds normally National Instruments Corporation 4 17 AT MIO 16X User Manual Register Map and Descriptions Bit Name 6 DB DIS 5 CYCLICSTOP 4 ADCFIFOREQ 3 SRC3SEL 2 GATE2SEL 1 FIFO DAC 0 EXTTRIG_DIS AT MIO 16X User Manual Chapter 4 Description continued Double Buffering Disable This bit controls the updating of the DACs If DB DIS is set writes to the DACs in immediate and delayed update mode are neither double buffered nor deglitched If DB DIS is cleared the DACs are double buffered and deglitched Cyclic Stop Enable This bit controls when a DAC sequence terminates If this bit is set when operating the DACs through the FIFO in a cyclic mode the DAC circuitry will halt when the next end of buffer is encountered If this bit is clear when the DACS are in a cyclic mode the DAC circuitry will restart transmission of the buffer after reaching the final point in the buffer This bit is functional only when the DAC circuitry is in cyclic mode and data is stored exclusively in the DAC FIFO ADC FIFO Request This bit controls the ADC FIFO Interrupt and DMA Request mode When ADCFIFOREQ is set ADC interrupt DMA requests are generated when the ADC FIFO is half full In this case the request is removed only when the ADC FIFO has been emptied of all its data When ADCFIFOREQ is cleared ADC interrupt DMA requests are
261. utine This clears the interrupt request The best method of servicing update requests is with DMA since this is done in parallel with the PC CPU If DMA is enabled DMA requests are generated when TMRREQ is set When the DMA controller acknowledges the request is automatically cleared An error is indicated in timer waveform generation when the DACCOMP bit in Status Register 1 is set prematurely If DACFIFOEF is clear when another update occurs then an error has occurred This error indicates an underrun condition where rates are above the maximum rate of the DMA controller or interrupt handling capabilities The error condition is cleared by writing to the TMRREQ Clear Register or the DAC Clear Register Programming the Digital I O Circuitry The digital input circuitry is controlled and monitored using the Digital Input Register the Digital Output Register and the two bits DIOPAEN and DIOPBEN in Command Register 2 See the register bit descriptions earlier in this chapter for more information To enable digital output port A set the DIOPAEN bit in Command Register 2 To enable digital output port B set the DIOPBEN bit in Command Register 2 When a digital output port is enabled the contents of the Digital Output Register are driven onto the digital lines corresponding to that port The digital output for both ports A and B are updated by writing the desired pattern to the Digital Output Register In order for an external dev
262. utomatically generate timed signals that initiate and gate conversions This is known as a data acquisition sequence A data acquisition operation refers to the process of taking a sequence of A D conversions with the sample interval the time between successive A D conversions carefully timed The data acquisition timing circuitry consists of various clocks and timing signals Three types of data acquisition are available with the AT MIO 16X board single channel data acquisition multiple channel data acquisition with continuous scanning and multiple channel data acquisition with interval scanning All data acquisition operations work with pretrigger and posttrigger modes with either internal or external timing signals Pretriggering acquires data before a software or hardware trigger is applied Posttriggering acquires data only after a software or hardware trigger is received Single Channel Data Acquisition Timing The sample interval timer is a 16 bit down counter that can be used with the six internal timebases of the Am9513A to generate sample intervals from 0 4 to 6 sec see the Timing Circuitry section later in this chapter Conversion intervals of less than 10 usec will result in an overrun condition Counter 3 of the Am9513A Counter Timer is used to generate conversion interval timing signals The sample interval timer can also use any of the external clock inputs to the Am9513A as a timebase During data acquisition the samp
263. ve data If this bit is cleared no DMA request or interrupt is generated To select a specific mode refer to Table 4 3 for available modes and associated bit patterns 3 DRVAIS Drive Analog Input Sense This signal controls the AI SENSE signal at the I O connector AI SENSE is always used as an input in the NRSE input configuration mode irrespective of DRVAIS If DRVAIS is set then AI SENSE is connected to board ground unless the board is configured in the NRSE mode in which case AI SENSE is used as an input If DRVAIS is cleared AI SENSE is used as an input in the NRSE input configuration and is not driven otherwise 2 0 lt 2 0 gt Interrupt Channel Select These bits select the interrupt channel available for use by the AT MIO 16X See Table 4 4 AT MIO 16X User Manual 4 14 National Instruments Corporation Chapter 4 Register Map and Descriptions Table 4 4 Interrupt Level Selection Bit Pattern Effect Interrupt Level Enabled ees L ledi eves ded ever Cp edi CE HE N ea T oO ES KJE _0 1 RR ER 1 2 National Instruments Corporation 4 15 AT MIO 16X User Manual Register Map and Descriptions Chapter 4 Command Register 4 Command Register 4 contains 16 bits that control the AT MIO 16X board clock selection serial DAC link over the RTSI bus DAC mode selection and miscellaneous configuration bits
264. veform generation 3 17 to 3 18 FIFO programmed cyclic waveform generation 3 18 FIFO pulsed waveform generation 3 18 to 3 19 waveform circuitry 3 15 waveform timing circuitry 3 16 to 3 17 data acquisition timing circuitry 3 7 to 3 10 block diagram 3 5 data acquisition rates 3 12 multiple channel scanned data acquisition 3 10 to 3 12 single channel data acquisition 3 8 to 3 10 single read timing 3 7 to 3 8 digital I O circuitry 3 19 to 3 20 functional overview 3 1 to 3 2 PC I O channel interface circuitry 3 2 to 3 4 RTSI bus interface circuitry 3 23 to 3 24 timing I O circuitry 3 20 to 3 23 time lapse measurements 2 31 timing circuitry See data acquisition timing circuitry timing I O circuitry timing connections 2 27 to 2 34 data acquisition and analog output 2 27 to 2 30 EXTCONV signal 2 28 EXTGATE signal 2 29 EXTSTROBE signal 2 27 EXTTMRTRIG signal 2 29 to 2 30 EXTTRIG signal 2 28 to 2 29 SCANCLK signal 2 27 general purpose connections 2 30 to 2 34 event counting application with external switch gating 2 31 frequency measurement 2 31 to 2 32 GATE SOURCE and OUT signals 2 30 to 2 34 input and output ratings 2 32 to 2 33 time lapse measurement 2 31 timing I O circuitry 3 20 to 3 23 block diagram 3 20 counter block diagram 3 21 timing I O specifications A 7 timing signals PC I O channel interface 3 3 TMRREQ bit AT MIO 16X User Manual Index 14 clearing analog output circuitry
265. w 4 30 to 4 31 register map 4 1 analog output signal connections 2 24 to 2 25 analog output specifications differential nonlinearity A 6 gain error A 6 list of A 5 to A 6 offset error A 6 relative accuracy A 6 analog output timing connections See data acquisition and analog output timing connections AO GND signal 2 14 2 24 B 3 AT bus interface 2 3 AT MIO 16X See also specifications theory of operation National Instruments Corporation Index block diagram 3 1 board description 1 1 to 1 2 analog input 1 1 to 1 2 analog output 1 2 digital and timing I O 1 2 definition xiii initializing 5 2 kit contents 1 4 optional equipment 50 pin connector 1 6 to 1 7 68 pin connector 1 7 to 1 8 optional software 1 4 parts locator diagram 50 pin connector 2 1 68 pin connector 2 2 unpacking 1 8 uses 1 1 to 1 2 AT MIO 16X PGIA analog input circuitry 3 6 Channel Gain Select GAIN 2 0 bit 4 27 common mode signal rejection considerations 2 23 to 2 24 differential connections 2 18 2 20 to 2 21 illustration 2 16 input signal connections 2 16 to 2 17 single ended connections 2 21 to 2 22 2 22 to 2 23 B B6 through BO bits 5 29 base I O address default settings for National Instrument products table 2 5 example switch settings illustration 2 4 factory settings 2 3 switch settings with base I O address and address space table 2 5 to 2 6 BDIO lt 0 3 gt signal 6 definition
266. xer switches to Channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in bipolar mode The approximately 4 V step from 4 V to 1 mV is 2 000 of the new full scale range To settle within 0 001546 15 ppm of the 100 mV AT MIO 16X User Manual A 4 National Instruments Corporation Appendix A Specifications full scale range on Channel 1 the input circuitry has to settle to within 0 000075 0 75 ppm of the 4 V step It may take as long as 4 000 usec for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Because of the problems with settling times multiple channel scanning is not recommended unless sampling rates are low enough or it is necessary to simultaneously sample several signals as close as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from Channel 0 then 100 points from Channel 1 then 100 points from Channel 2 and so on If however all the channels are scanned at the same gain and all the signals are within 10 of the full scale range of each other for example within 2 V of each other with a 10 range the circuitry settles to full 16 bit accuracy 0 5 LSB in 10 usec and the channels can be scanned at the full rate of 100 ksamples sec Analog Output Number of output channels Type of DAC D

AT-MIO-16X User Manual - Artisan Technology Group

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