Memory revisited - Cristinel Ababei
Contents
1. 21 ROM Read Only Memory Nonvolatile Can be read from but not written to by a processor in an microcomputer system Traditionally written to programmed before inserting to microcomputer syste Uses Store software program for general purpose processor Store constant data parameters needed by system External view enable _ 2x n ROM m Implement combinational circuits e g decoders Ay 7 a Aus Example 8 x 4 ROM Horizontal lines words Vertical lines data Internal view Lines connected only at circles Decoder sets word 2 s line to 1if enabie_ address input is 010 Ay 3x8 decoder A Data lines Q3 and Qi are set to 1 A because there is a programmed connection with word 2 s line programmable connection h J h data line Word 2 is not connected with data lines Q2 and Qo Output is 1010 y Y T Q Q Q A 22 Mask programmed ROM Connections programmed at fabrication set of masks Lowest write ability only once Highest storage permanence bits never change unless damaged Typically used for final design of high volume systems spread out NRE non recurrent engineering cost for a low unit cost OTP ROM One time programmable ROM Connections programmed after manufacture by user user provides file of desired conten2. RAM Random Access Memory Typically volatile memory bits are not held without power supply Read and written to easily by microprocessor during execution Internal structure more complex than ROM aword consists of several memory cells each storing 1 bit each input and output data line connects to each cell in its column rd wr connected to every cell when row is enabled by decoder each cell has logic that stores input data bit when rd wr indicates write or outputs stored bit when rd wr indicates read r w enable Ao Ak enable 2x4 Ay A external view 2K x n read and write memory internal view k hh b 4x4 RAM decoder rd wr To every cell yyy Q QQ A Basic types of RAM SRAM Static RAM Memory cell uses flip flop to store bit Requires 6 transistors Holds data as long as power supplied DRAM Dynamic RAM Memory cell uses MOS transistor and capacitor to store bit More compact than SRAM Retains data for only 2 4 ms Refresh required due to capacitor leak e word s cells refreshed when read Slower to access than SRAM m emory cell internals 27 RAM variations PSRAM Pseudo static RAM DRAM with built in memory refresh controller Popular low cost high density alternative to SRAM NVRAM
3. controllers are on a higher speed bus Devices with more than 32 kB SRAM have two additional 16 kB SRAM blocks LPC1768 Flash memory dynamic characteristics Flash characteristics Tamb 40 CT to 85 C unless otherwise specified Symbol Nendu tret tprog Parameter Conditions Min endurance 10000 retention time powered 10 unpowered 20 erase time sector or multiple 95 100 105 ms consecutive sectors programming time B 0 95 1 1 05 ms 1 Number of program erase cycles 2 Programming times are given for writing 256 bytes from RAM to the flash Data must be written to the flash in blocks of 256 bytes Flash accelerator Allows maximization of the performance of the Cortex M3 processor when it is running code from flash memory while also saving power The flash accelerator also provides speed and power improvements for data accesses to the flash memory Bus DCode Matrix me Combined f AHB AHBLite Buffer t jbus E Array i Gai Flash Accelerator mg Master Port Control Controller Memory Predefined fixed memory map that specifies which bus interface is to be used when a memory location is accessed Memory system has the bit band support e Provides atomic operations to bit data in memory or peripherals e Supported only in special memory regions Supports both little endian and big endian memory configuration Cortex M3 Memory Address Space 1 ARM Cortex M3
4. has a single physical address space of 234 bytes 4 GB ARM Cortex M3 Technical Reference Manual defines how this address space is to be used predefined memory map The SRAM and Peripheral areas are accessed through the System bus The Code region is accessed through the ICode instructions and DCode constant data buses OxE00FFO00 OxEOOFEFFF 0xE0042000 ROM Table Extemal Private Penpheral Bus 0xE0041000 ETM 0xE0040000 TPIU OxE003FFFF 0xE000F000 daza 0xE000E000 NVIC OxEQ00DFFF 0xE0003000 0xE0002000 FPB 0xE0001000 DWT Reserved 0xE0000000 ITM 0x43FFFFFF Bit Band Alias 0x42000000 0x41FFFFFF 0x40100000 on Bit Band Region N NINNI Mw NINN YN J Peripheral 0 5GB SRAM 0 5GB Vendor Specific N NINI NNN OxFFFFFFFF 0x60000000 OxSFFFFFFF 0x40000000 Ox3FFFFFFF 0x20000000 Ox1FFFFFFF 0x00000000 OxFFFFFFFF 0xE0100000 Private Peripheral Bus Debug Extemal Private Peripheral Bus intemal OxEQOFFFFF 0xE0040000 OxE003FFFF 0xE0000000 OxDFFFFFFF Extemal Device 0xA0000000 External RAM OxOFFFFFFF 0x60000000 Peripherals OxSFFFFFFF 0x40000000 0x23FFFFFF Bit Band Alias 0x22000000 32 MB OX21FFFFFF 0x20100000 31 MB 0x20000000 Bit Band Region 1MB Ox3FFFFFFF 0x20000000 Ox1 FFFFFFF Memory Map 3 APB1 peripherals LPC1768 memor
5. it if possible MPU can be used in various ways Set up by an operating system allowing data used by privileged code e g the operating system kernel to be protected from untrusted user programs Can be used to make memory regions read only to prevent accidental erasing of data or to isolate memory regions between different tasks in a multitasking system Overall it can help make embedded systems more robust and reliable Outline Registers Memory map Program code Memory protection unit MPU Peripherals Memories basic concepts 11 Peripherals LPC1768 microcontrollers are based on the Cortex M3 processor with a set of peripherals distributed across three buses Advanced High performance Bus AHB and its two Advanced Peripheral Bus APB sub buses APB1 and APB2 These peripherals are controlled by the CM3 core with load and store instructions that access memory mapped registers can interrupt the core to request attention through peripheral specific interrupt requests routed through the NVIC Data transfers between peripherals and memory can be automated using DMA Labs will cover among others basic peripheral configuration e g lab1 illustrates GPIO General Purpose I O peripherals how interrupts can be used to build effective software how to use DMA to improve performance and allow processing to proceed in parallel with data transfer Peripherals Periphera
6. EE 379 Embedded Systems and Applications Memory Revisited Cristinel Ababei Department of Electrical Engineering University at Buffalo Spring 2013 Note This course is offered as EE 459 500 in Spring 2013 Outline Registers Memory map Program code Memory protection unit MPU Peripherals Memories basic concepts Cortex M3 e Cortex M3 as a RISC processor is a load store architecture with three basic types of instructions Register to register operations for processing data Memory operations which move data between memory and registers Control flow operations enabling programming language control flow such as if and while statements and procedure calls Processor Register Set e Cortex M3 core has 16 user visible registers All processing takes place in these registers e Three of these registers have dedicated functions program counter PC holds the address of the next instruction to execute link register LR holds the address from which the current procedure was called the stack pointer SP holds the address of the current stack top CM3 supports multiple execution modes each with their own private stack pointer e Processor Status Register PSR which is implicitly accessed by many instructions Processor Register Set Functions and Banked Registers General Purpose Register D General Purpose Register General Purpose Register General Purpose Register G
7. Nonvolatile RAM Holds data after external power removed Battery backed RAM SRAM with own permanently connected battery e writes as fast as reads no limit on number of writes unlike nonvolatile ROM based memory SRAM with EEPROM or FLASH stores complete RAM contents on EEPROM or FLASH before power turned off Dual port RAM DPRAM e Usually a static RAM circuit with two address and data bus connections Shared RAM for two independent users e Flexible communication link between two processors Master slave 28 DDR1 SDRAM DDR2 Double Data Rate synchronous dynamic random access memory DDR1 SDRAM is a class of memory integrated circuits used in computers The interface uses double pumping transferring data on both the rising and falling edges of the clock signal to lower the clock frequency One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller DDR2 memory is fundamentally similar to DDR SDRAM DDR2 SDRAM can perform four transfers per clock using a multiplexing technique Credits and references Joseph Jiu The Definitive guide to the ARM Cortext M3 2007 Chapters 5 13 LPC17xx microcontroller user manual Cortex M3 Processor Technical Reference Manual Lab manual G Brown Indiana EECS 373 Umich http esd cs ucr edu 29
8. able ROM Programmed and erased electronically typically by using higher than normal voltage can program and erase individual words Better write ability can be in system programmable with built in circuit to provide higher than normal voltage built in memory controller commonly used to hide details from memory user writes very slow due to erasing and programming e busy pin indicates to processor EEPROM still writing can be erased and programmed tens of thousands of times Similar storage permanence to EPROM about 10 years Far more convenient than EPROMs but more expensive 25 FLASH e Extension of EEPROM Same floating gate principle Same write ability and storage permanence e Fast erase Large blocks of memory erased at once rather than one word at a time Blocks typically several thousand bytes large e Writes to single words may be slower Entire block must be read word updated then entire block written back FLASH applications Flash technology has made rapid advances in recent years cell density rivals DRAM better than EPROM much better than EEPROM multiple gate voltages can encode 2 bits per cell many GB devices available ROMs and EPROMS rapidly becoming obsolete Replacing hard disks in some applications smaller lighter faster more reliable no moving parts cost effective PDAs cell phones laptops iPods etc
9. an executing program is divided into three regions RAM End high gt Main Stack ae Heap End Heap Start RAM Start low L Program Memory Model RAM for an executing program is divided into three regions Data in RAM are allocated during the link process and initialized by startup code at reset The optional heap is managed at runtime by library code implementing functions such as the malloc and free which are part of the standard C library The stack is managed at runtime by compiler generated code which generates per procedure call stack frames containing local variables and saved registers Program code Program code can be located in the Code region the SRAM region the External RAM region It is best to put the program code in the Code region because the instruction fetches and data accesses are carried out simultaneously on two separate bus interfaces Outline Registers Memory map Program code Memory protection unit MPU Peripherals Memories basic concepts 10 Memory Protection Unit MPU Cortex M3 has an optional Memory Protection Unit MPU LPC1768 has one that supports 8 regions Allows access rules to be set up for privileged access and user program access When an access rule is violated gt a fault exception is generated gt fault exception handler will be able to analyze the problem and correct
10. atile SRAM LIFO FLASH DRAM Shift Register CAM Volatile need electrical power Nonvolatile magnetic disk retains its stored information after the removal of power Random access memory locations can be read or written in a random order EPROM erasable programmable read only memory EEPROM electrically erasable programmable read only memory FLASH memory stick USB disk Access pattern sequential access video memory streaming first in first out buffer last in first out stack shift register content addressable memory Static vs Dynamic dynamic needs periodic refresh but is simpler higher density Key Design Metrics 1 Memory Density number of bits mm and Size 2 Access Time time to read or write and Throughput 3 Power Dissipation 15 Memories classification Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory CAM Read Write Memory Read Only Memory Shift Registers Queues RAM ROM Volatile Nonvolatile i Serial In Parallel In First In Last In Static RAM Dynamic RAM Parallel Out Serial Out FirstOut First Out SRAM DRAM SIPO PISO FIFO LIFO Mask ROM Programmable Erasable Electrically Flash ROM ROM Programmable Erasable PROM ROM Programmable EPROM ROM EEPROM Write ability and Storage permanence Traditional ROM RAM distinctions ROM e read only bits stored without power RAM e read and write lose stored bi
11. eneral Purpose Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register General Purpose Register J Main Stack Pointer MSP Process Stack Pointer PSP Link Register LR Program Counter PC R7 Name C R OR Special Registers Name Functions Program Status Registers FAULTMASK Interrupt Mask arena Registers Registers BASEPRI CONTROL Control Register Provide ALU flags zero flag carry flag execution status and current executing interrupt number PRIMASK Disable all interrupts except the nonmaskable interrupt NMI and HardFault FAULTMASK Disable all interrupts except the NMI BASEPRI Disable all interrupts of specific priority level or lower priority level CONTROL Define privileged status and stack pointer selection Outline Registers Memory map Program code Memory protection unit MPU Peripherals Memories basic concepts LPC1768 Memory e On chip Flash memory system Table 9 Up to 512 kB of on chip flash memory Flash memory accelerator maximizes performance for use with the two fast advanced high performance bus AHB Lite buses Can be used for both code and data storage On chip Static RAM SRAM Up to 64 kB of on chip static RAM memory Up to 32 kB of SRAM accessible by the CPU and all three DMA direct memory access
12. ing the memory Memories in high end and middle range of write ability 17 Storage permanence e Range of storage permanence High end e essentially never loses bits e e g mask programmed ROM Middle range e holds bits days months or years after memory s power source turned off e g NVRAM Lower range e holds bits as long as power supplied to memory e g SRAM Lowend begins to lose bits almost immediately after written refreshing needed e e g DRAM e Nonvolatile memory Holds bits after power is no longer supplied High end and middle range of storage permanence Memory array M M C C Cell bit lines Different memory types are distinguished by technology for storing bit in memory cell 18 Support circuitry memory array 16 bits 4x4 2 to 4 decoder ae 4 1 mux demux OE 7 AK CS WE D Control signals DO e Control read write of array e Map internal physical array to external configuration 4x4 gt 16x1 Interface 1 2 Physical configurations are typically square Minimize length word bit line P minimize access delays External configurations are tall and narrow The narrower the configuration the higher the pin efficienc
13. ls are memory mapped core interacts with the peripheral hardware by reading and writing peripheral registers using load and store instructions The various peripheral registers are documented in the user and reference manuals documentation include bit level definitions of the various registers and info on how interpret those bits actual physical addresses are also found in the reference manuals Examples of base addresses for several peripherals see page 14 of the LPC17xx user manual 0x40010000 UART1 0x40020000 SPI 0x40028000 GPIO interrupts 0x40034000 ADC No real need for a programmer to look up all these values as they are defined in the library file lpc17xx h as LPC_UART1_BASE LPC_SPI_BASE LPC_GPIOINT_BASE LPC_ADC_BASE 12 Peripherals e Typically each peripheral has e control registers to configure the peripheral e status registers to determine the current peripheral status e data registers to read data from and write data to the peripheral Peripherals e In addition to providing the addresses of the peripherals lpc17xx h also provides C language level structures that can be used to access each peripheral e For example the SPI and GPIO ports are defined by the following register structures typedef struct uint32_t uint32_t uint32_t uint32_t uint32_t uint32_t SPCR SPSR SPDR SPCCR RESERVEDO 3 SPINT LPC_SPI_TypeDef 13 Outline Regis
14. ters Memory map Program code Memory protection unit MPU Peripherals Memories basic concepts Memory basic concepts e Stores large number of bits mxn m words of n bits each mx n memory k Log m address input signals 5 or m 2 words e g 4 096 x 8 memory e 32 768 bits e 12 address input signals 8 input output data signals n bits per word memory external view e Memory access T xn read and r w selects read or write e emor enable read or write only when asserted o multiport multiple accesses to different locations simultaneously 14 Memory basic categories Writable e Read Only Memory ROM Can only be read cannot be modified written by the processor Contents of ROM chip are set before chip is placed into the system Random Access Memory RAM Read write memory Although technically inaccurate term is used for historical reasons ROMs are also random access Permanence Volatile memories Lose their contents when power is turned off Typically used to store program while system is running Non volatile memories do not Required by every system to store instructions that get executed when system powers up boot code Memories classification Non volatile Volatile Memory Memory Random Access Sequential Access Mask Programmed ROM PROM FIFO Li alo nonvol
15. ts of ROM file input to machine called ROM programmer each programmable connection is a fuse ROM programmer blows fuses where connections should not exist Very low write ability typically written only once and requires ROM programmer device Very high storage permanence bits don t change unless reconnected to programmer and more fuses blown Commonly used in final products cheaper harder to inadvertently modify 23 EPROM UV Erasable programmable ROM Programmable component is a MOS transistor Transistor has floating gate surrounded by an insulator a Negative charges form a channel between source and drain storing a logic 1 b Large positive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0 c Erase Shining UV rays on surface of floating gate causes negative charges to return to channel from floating gate restoring the logic 1 d An EPROM package showing quartz window through which UV light can pass Better write ability can be erased and reprogrammed thousands of times Reduced storage permanence program lasts about 10 years but is susceptible to radiation and electric noise Typically used during design development qua oO or na 2s N o gt _ oO 24 Sample EPROM programmers EDP 17003 PORTABLE EPROM PROGRAMMER EEPROM Electrically erasable programm
16. ts without power Traditional distinctions blurred Advanced ROMs can be written to e g EEPROM Advanced RAMs can hold bits without power e e g NVRAM Write ability Manner and speed a memory can be written Storage permanence Ability of memory to hold stored bits after they are written 16 Write ability and Storage permanence Mask programmed ROM Ideal memory permanence OTP ROM e EPROM EEPROM e i e 5 ii Nonvolatile NVRAM Ea EE eag PE ESAE AIPA PEN ER AIRERA LOAA T Aiia years In system programmable SRAM DRAM Write l __ability During External External External External fabrication programmer programmer programmer programmer only one time only 1 000s OR in system OR in system of cycles 1 000s block oriented of cycles writes 1 000s of cycles In system fast writes unlimited cycles Write ability and storage permanence of memories showing relative degrees along each axis not to scale Write ability e Ranges of write ability High end processor writes to memory simply and quickly e g RAM Middle range processor writes to memory but slower e g FLASH EEPROM Lower range special equipment programmer must be used to write to memory e g EPROM OTP ROM Low end e bits stored only during fabrication e g Mask programmed ROM e In system programmable memory Can be written to by a processor in the microcomputer system us
17. y Adding one address pin cuts data pins in half Several external configurations available for a given capacity 64Kbits may be available as 64Kx1 32Kx2 16Kx4 19 Interface 2 2 e Chip Select CS Enables device If not asserted device ignores all other inputs sometimes entering low power mode e Write Enable WE Store DO at specified address e Output Enable OE Drive value at specified address onto DO Memory timing Reads tRC gt tav i it Xx CS OE DATA x X Access time Time required from start of a read access to valid data output Access time specified for each of the three conditions required for valid data output valid address chip select output enable Time to valid data out depends on which of these is on critical path tac Minimum time required from start of one access to start of next For most memories equal to access time 20 Memory timing Writes twc taw tos tDH Write happens on rising edge of WEH Separate access times taw toy twp specified for address valid CS WE Typically t 0 meaning that WE may not be asserted before address is valid Setup and hold times required for data Write cycle time twc is typically in the order of taw Memory Comparison grid Memory Volatility density rewrite type SRAM DRAM EPROM EEPROM
18. y space 0x4010 0000 E 468 OxFFEF FFFF 0x400F C000 system control 2 2 0000 30 16 reserved 2 area 2 T 0xE010 0000 QEL oxsooB cooo S __QE __ wate peripheral bus 0x4008 8000 14 motor control PWM _ Lek 0xE000 0000 Ox400B 4000 73 reserved z reserved Z 0x400B 0000 repetitive interrupt timer Ox400A C000 AHB periherals 0x400A 8000 Z Z reserved 0x400A 4000 St E oxsooa ooo0 8 2C peripheral bit band alias addressing 0x4009 C000 reserved 2 0x4010 0000 0x400 8000 0x4000 4000 0x4009 0000 J650 0x4008 C000 0x2400 0000 0x4008 8000 AHB SRAM bit band alias addressing 0x4008 0000 Z reserved GPIO APBI peripherals 0x2200 0000 Z x200A 0000 0x200 C000 S reserved Z 3x2008 4000 oses AHB SRAM 2 blocksof 16KB 0 2007 co00 4 amet Z oxtFFF 2000 a Z 3x1000 8000 Z elD code 32 kB local static RAM ox1000 memory space a reserved 2 256 words active interrupt vectors Ne 512 kB on chip flash Outline Registers Memory map Program code Memory protection unit MPU Peripherals Memories basic concepts Program Memory Model e Cortex M3 has been designed to be programmed almost entirely in high programming languages e g C e So it has a well developed procedure call standard called an ABI or application binary interface which dictates how registers are used e This model explicitly assumes that the RAM for
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