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Automated synthesis from VHDL models

1. Automated Synthesis from HDL models Leonardo Mentor Graphics Design Compiler Synopsys ASIC Design Flow Behavioral Verify Model Function VHDL Verilog Synthesis DFT BIST Gate Level Verify amp ATPG Netlist Function Test vectors Verify Function Standard Cell IC amp Timing amp FPGA CPLD DRC amp LVS Physical Layout Map Place Route Verification Mask Data FPGA Configuration File Project directory structure MyHomeDirectory CADProjects Projectl Project2 work adk VHDL std cell library library src syn fm 1 5 layout vhd Synthesis scripts do files Physical logs reports simulation layout files Design database results Netlists v vhd Sdf sdc pow files Automated synthesis HDL Behavioral RTL Models Technology Synthesis Libraries B Leonardo Level 1 FPGA Ex Synopsys Level 2 FPGA Timing Desianware VHDL Verilog Level 3 FPGA 5 cor DE 5 Area delay reports Critical Path Trace works compiled technology in memory mapped design HDL design Synthesis design flow Synthesis steps 2 Load technology library into database Analyze design Load HDL models into database check for synthesizable models Elaborate design Technology independent circuit random amp structured logic Specify design constraints timi
2. delay auto optimize area default delay or both hierarchy preserve flatten auto macro chip macro ASIC block chip includes pads single_level optimize top only otherwise all levels target tech default is to use loaded synth library io target tech Timing Optimization optimize timing lt design_name gt through node _lists gt opt through these nodes force use longest paths ignores constraints single level top level only o w all levels If no options try to improve most critical paths within user specified timing constraints gt Improve arrival time at end of each critical path gt Most effective if user specifies constraints Input arrival output required times clock Example optimize all paths ending at signal out optimize timing through out Optimize Set variables for both optimize and optimize timing commands Technology Input Constraints Optimize Repot Output Select design to optimize Target Technology Run type Optimize Remap Optimize Effort Extended Optimization Effort Pasi Pass 2 Pass3 Pass 4 m Optimize For C Auto Delay Area m Hierarchy Auto Preserve Flatten 0 Pads Optimize a single level of hierarchy Run timing optimization Help ize Optimize Timing Advanced Setings Optimize Timi
3. NM attribute required time wam Max rise fall time allowed used in delay loading calculations Pin Location Requred Time directly specifies the timing through logic cloud A ogo Cud adi 22 Delete Constraints Constraints Help gt Te A Global Clock Input Output Signal Module Report Ready required time 7 dl Sequential circuit example 10 4 ns 1 6 ns min min path hold max max path setup Tsetu p 6 4 ns 4 8 ns c l clock_cycle 20 clka clock_cycle 30 clkb Required clock periods arrival time 10 4 clock clka in1 Arrival at input pin from arrival time 6 4 clock clkb inl previous clock edge required time 1 6 clock clka min Setup time of output pin required time 4 8 clock clka max out1 from next clock edge Technology Input Constraints optimize Report Output M O d U n SL 5 Individual modules may be noopted or dont touched treat as black optir Area or Delay and with Quick or Standard Extended Effort Co mman d 5 ri b U te 5 Manis Module Constraints i 1 3 don t_touch noopt Select modules Optimize for Don t touch keep module as is Eo including lower levels Opt keep selected module but lower levels may be optimized Delete Constraints 1 Select area delay optimization and effort level for each
4. Report Output Specify clock frequency clock cycle and global path constraints for the entire The smallest design for a given frequency is then created All paths between registers are constrained to one clock period You can customize delays betw and registers by specifying a Maximum Delay between each The clock refere zero Input Ports to Registers Registers to Registers Sm Registers to Output Ports ns s Inputs to Outputs Individual Clock net attributes Specify the clock characteristics of different clocks in the design Clock specil include the clock cycle or frequency pulse width or duty cycle and clock offs Reference Clock Properties Frequency MHz Clock s Clock name s ner D ns Pulse Width 0 ns Duty Cycle 50 Z Pin Location Pad Type Delete Constraints These override the global clock settings for the selected clock Signals Timing Constraint Variables Four delay variables can be specified Input pin to output pin through combinational logic Input pin to register 1 2 clock period typical Sum J period i i FF in one block to Register to output pin 1 2 clock period typical FF in another block Register from time it is clocked to register to meet setup time Examples set register2register 8 set input2register 5 register2output input2reg
5. 2 nx204 nx208 nx2 12 nx2 4 nx218 nx225 nx228 nx230 std logic begin Q 2 lt Q 2 EXMPLR 1 lt EXMPLR Q 0 lt Q 0 EXMPLR ix 70 mux2l ni port map gt 169 0 gt 14 gt 0 0 EXMPLR 50 gt 225 15 0ai22 port map Y gt nxl4 A0 gt Q_ 0 EXMPLR AI gt nx202 gt 230 Bl gt count ix203 nand02 port map Y gt nx202 A0 gt count Al gt nx204 ix205 nand04 port map Y gt nx204 A0 gt count Al gt Q_ 2 EXMPLR 2 gt gt 228 ix180 32 port map gt 179 0 gt 208 gt 2 gt 0 gt 212 gt 225 2 EXMPLR EXMPLR dffr port map gt 2 EXMPLR gt 208 gt 179 CLK gt clk gt reset Synthesized netlist 3 2 11 invOl port map Y gt NOT_reset A gt reset ix213 aoi22 port map Y gt nx212 A0 gt 1 2 Al gt 2 14 0 gt 22 Bl gt nx4 ix216 invOl port map Y gt nx214 A gt count ix219 nand02 port map gt 2 1 18 0 gt gt 0 EXMPLR EXMPLR EXMPLR dffr port map gt EXMPLR gt gt 189 CLK gt clk R gt NOT_ reset 1190 mux2l ni port map gt 189 0 gt 60 gt 50 gt 225 ix61 ao32 port gt 60 A0 gt nx48 Al gt nx218 A2 gt nx4 BO gt I 1 Bl gt nx214 ix49 02 port map
6. F timing Select Technology Cells for circuit structure of cells from the technology library Technology Input Constraints Optimize Report Output Click gt Filename folder gt Set Output File and to select output netlist file for place and route Use default format for your displayed output netlist file Filename Format Auto VHDL Verilog C EDIF SDF C Preference NCF Write vendor constraints file Pre Process netlist write only the top level of hierarchy to file Write modules Downto Technology Cells Primitives ite Help 4 gt Output Files EDIF Out Options SDF Out Options Verilog Out Options VHDL Out Options Ready Area report area report file gt cell usage cell usage per instance in the design hierarchy report each level of hierarchy separately all leafs report on all leaf cells including black boxes Example report area cell usage hierarchy mult area rpt Generate a report showing all cell instances in each separate block in the design hierarchy The report includes total number of primitive elements std cells and equivalent area of each Delay reports design timing information report_delay lt report_file_name gt num_paths number default 10 longest_path sorted by longest first critical paths paths so
7. S Technology ut Constraints Optimize Report Output Place amp Route C or FPGA to extend device tree and select library Click on the selected technology logo open the vendor website Use all defaults Set advanced technol options under Advanced Click to View pr Load Library to apply settin Vendor s Web Site Ls Part 5200256 c Xilinx Speed 4 gt CoolRunner SPARTAN Wire Load xc 50 4 v SPARTAN XL Map IOB Registers Load Library Help Settings Qivanced Settings Ready Load a design into the database Analyze syntax check and build database Input VHDL and or Verilog models check dependencies amp resolve generics parameters Elaborate synthesize to generic gates and black boxes technology independent gates operators arithmetic relational etc recognized and implemented with black boxes no logic in them yet Memory Read command does analyze elaborate pre optimize Analyze Command analyze fl vhd src f2 vhd top file vhd Read and analyze into default memory database library work List VHDL files in bottom up order top level last Use quotes if embedded spaces file name file vhd Include directory if necessary src f2 vhd Analyze command switches format vhdl or verilog default VHDL if file ext vhd vh
8. Y gt nx48 A0 gt Q_0 EXMPLR Al Q EXMPLR ix226 nor02 2x port map Y gt nx225 A0 gt count Al 2load 0 EXMPLR EXMPLR dffr port map gt 0 EXMPLR gt 228 gt 169 CLK gt clk gt reset 23 1 invOl port map gt 230 gt 1 0 ix5 invOl port map gt 4 gt 202 ix23 xor2 port map gt 22 0 gt 208 gt 218 end Behave Flowlabs Menu Bar Banner ToolBars Information window a Pr sJ fs aa miei i 2 eaa sle uaar Info License passed _ Session history will be logged to file E B M info working Directory now ril Info system variable EXEMPLAR set to B XE Leo n a rd Info Loading Exemplar Blocks file Er xempl Maszagaz will be logged to file Exempler Leonerdo pectrum Level 3 200018 2 72 Relea Copyright 1990 2000 mxenplar Logic Inc Ally Main M s Window 5 amp Did you know Wart ta get great synthesis results fast and easy Use the Setup FlowTsb Leonardo FPGA CPLD Quick Setup Tab Command Technology Window HDL Files Target Clock Freq Optimization Effort Output File a De i Active Review Spectrum commands attributes variables Enter commands at the command prompt More efficient to read commands from a Tcl script file A variable specifies a global const
9. dl or Verilog if file ext v verilog work lib name lib where design to be stored default work Different libraries might be used for comparing designs Examples analyze src fl vhd src f2 vhd analyze src fl vhd src f2 vhd work lib version Elaborate Command gt Elaborate a design currently in the memory database producing tech independent circuit elaborate divider divider VHDL entity Verilog module Switches single level only do top level for bottom up design architecture al if other than most recently analyzed work lib name if name other than work generics size 9 use this TRUE initval 10011 O List format is generic value generic value parameters format same as generics Read command Performs both analyze and elaborate steps read fl vhd src f2 vhd top file vhd Same switches as analyze and elaborate commands plus dont elaborate fl vhd do analysis but not elaborate gt GUI Input Flow Tab can be used to run read analyze elaborate Uncheck Run Elaborate box for analyze only Uncheck Run Pre Optimization to skip that step for now Select other analyze elaborate options via the Power Tabs Input Flow HDL file list List VHDL files from bottom to top levels of hierarchy FSM encoding Share resources adders etc to do multiple op s Run Elaborate step after Analysis Run Pre Optimize step aft
10. er Elaborate Technology Input Constraints Optimize Report Output Flace amp Route Click Working Directory gt Set Yvorking Directory to establish a path Click Open iles gt Se Input File s to open a file Click LMB on file name to open file information Click RMB on file name to open pulldown with more file choices Double click on file name tc open HOLInvenior Use Windows drag and drop attributes to arrange files Use all detaults Working Directory v2000_1a2 63 demo multvhd gt acc vhd pannas filter_top vhd Encoding Style C Binary Onehot Twohot Random Gray Auto Resource Sharing Run Elaborate Run Pre Optimizaton Read Help Power Tabs below here Elaborate amp VHDL Options Power Tabs Technol straints Optimize Repor Output Pla level designs iter tc p Architecture mnm York libran to place designs in Paremztzre p Generics ioo widh 5 F Eloborote the top level design only nts Optimize Place amp Route Top Entity Architecture an Generic data_vadth e 6 VHDL 43 C VHDL 8 N Pre Optimiza VHDL Optons AJ Select top level design name architecture work library generics top level only Select VHDL 87 instead of 93 Other power tabs for other formats Verilog SDL etc Global con
11. ister register2register input2Zoutput Input constraints Arrival time from previous ckt to input pin relative to clock attribute arrival time Drive level of circuit driving the pin amp max rise fall time allowed used in delay loading calculations data 3ns after ri ing edge of clock ck gt delay BdemalVitua n Circuit N Data arrives at Input port data 7 cbck period of 10 ns i attached to input port ck 3ns arrival time 3 data Technology Input Constraints apimize Report Output Specify the input required time and load characteristics for each input port By input ports are unconstrained with no load applied Input Ports Input Constraint NEM Arrival Time Infinite Drive C Input Drive Transition Rise ns Fall ns INN Pin Location Pad Type Delete Constraints Help STATE EUN Global A Clock Input A Output Signal Module Report Ready Technology Input Constraints Optimize Report Output O t D u t C n St r n 5 Specify the output required time and load characteristics for each output port the output ports unconstrained with no load applied Output Ports Output Constraints Time from clock to valid output at Required Tim ns Max Transition aS pin to be used by external ckt ip
12. module Apply TTT Tr Cock hpa Sand Module Ready Write a Constraint File For subsequent synthesis and or for physical place amp route tool Technology Input Constraints Optimize Report Output Constraint Summary Constraint File O Pre optimization step Technology independent logic optimization Always done as part of optimize command gt pre optimize lt design_ name gt common_logic share operators primitives with common inputs used in different clock cycles unused_logic remove logic that doesn t affect outputs extract recognize counters decoders RAMs ROMs xor_comparator_optimize factor common sub expressions from wide XORs comparators single level do top level only default is all levels boundary propagate constants inputs tied high low from boundary unused inputs etc Pre Optimize Power Tab a hvalues m3 mult Ci filter top 5 4 struct H 0 Pons Nets Cells ul taps H u hvalues rm u3 fit fom wD ud muli 89 385 5 44 1 lt q lt l Select specific design to pre optimize Optimization step Control optimization via Timing constraints on I O signals Input drive and capacitance and output load Definition on clocking schemes optimize design default current design effort quick one pass standard multiple passes remap area
13. ng Technology Input Constraints Optimize Report Output Select design to optimize Optimize a single level of hierarchy Advanced Settings Technology Input Constraints Optimize Repo Dutput Advanced Optimization Options Eu ya ara Wis m E Allow converting of internal tri states Allow transforming Set Reset on DFFs and Latches Break combinational loops statically during timing analysis Bubble Tristates Operator Options Use technology specific module generation library Operator Select Auto C Smallest Small C Fast Fastest Extract Clock Enables Extract Counters Extract Decoders Extract RAMs Extract ROMs Optimization CPU Limit minutes Auto Dissolve Limit 50 LN Help Advanced Settings Save design to file s gt write file name format format name VERILOG VHDL vhd SDF sdf EDIF edf downto library name don t write details of cells primitives in library silent no warnings or information messages single level top level only default is all levels design design gt default is current design Examples write format VHDL mydesign vhd write format Verilog mydesign v write format SDF _ mydesign sdf Delay parameters for timing analysis Output Write one or more files VHDL netlist Verilog netlist SD
14. ng area Compile optimize design Optimize for the loaded technology library Repeat as necessary to meet constraints Generate technology specific netlist s Generate simulation timing data SDF file Generate reports cells area timing LeonardoSpectrum Documentation To access documentation Linux gt In bashrc file export EXEMPLAR linux_apps mentor LeonardoSpectrum 20 4a export LEO DOCS S EXEMPLAR doc bk leospec pdf From command line mgcdocs LEO DOCS gt In GUI access documents from the help menu Main Documents gt User s manual Reference Manual Command summaries HDL Synthesis Manual VHDL Verilog for synthesis Synthesis and Technology Manual AS C FPGA specific Invoking LeonardoSpectrum i Invoke command line version Linux spectrum Spectrum is command line version for Linux To execute command file after startup spectrum file mycommands tcl 2 invoke GUI version leonardo Execute most commands interactively Can save transcript to use as basis for command file LeonardoSpectrum synthesis example Load technology library tsmc035 ASIC Load design file modulo7 vhd Specify constraints clock freq delays etc gt Optimization effort performance vs area Write synthesized netlist output s modulo7 O vhd VHDL netlist for ModelSim amp DFT modulo v Verilog netlist for import into DA IC modulo sdf For ModelSim to study timing modulo7 edf EDIF netli
15. nly after place and route Function of cell sizes and fanouts Table of RC values estimated from net lengths previous projects provided by vendor Variables wire load library name lib to which designed mapped or NIL wire table name if named table loaded wire tree best balanced worst or not set wire load mode top segmented Timing Constraints Simple specify target clock frequency Advanced specify globally or on specific blocks Clock period frequency pulse width duty cycle Input arrival time transition times driver strength Output required time transition times required time arrival time slack Clock related constraints clock_cycle lt clock_period gt lt primary_input_port gt pulse_width lt clock_pulse_width gt lt primary_input_port gt clock_offset lt clock_offset gt lt primary_input_port gt offset from time 0 5 The clock constraint w define the required timing for all logic betw een flops Clock constraint examples 0 0 0 20 0 40 0 clock cycle 40 clock cycle 40 clk pulse width 15 clk clock cycle 40 clk pulse width 15 cl clock offset 5 1 45 0 Global Clock constraints Frequency perio Delay constraints Path delay These apply to the entire design except for objects for which attributes have been defined that specify other clock values Technology Input Constraints Optimize
16. raint directive etc Tcl set and unset commands change variables set voltage 3 3 An attribute is information attached to an object in the memory design database Allows user to fine tune the process at the object level Set with Tcl set attribute command also unset attribute An attribute has owner name value Example 1 es set attribute net nl name max fanout load value 10 Technology library ASIC Load synthesis library for target technology into memory Command example load library technology name Default location EXEMPLAR lib technology name syn Command to load ADK TSMC 0 35 350nm library load library EXEMPLAR lib tsmc035 typ Available ADK libraries tsmc035 typ syn use for course projects tsmc025 typ syn 5 018 typ syn amil2 typ syn 05 typ syn gdk syn Technology library ASIC variables gt Technology variables affect delay calculations delay derating factors Use tech library defaults if variables not set set voltage 2 5 volts set temp 40 degrees celsius centigrade set process process variation if available g ASIC E Mentor Graphics AMI 0 5 typ Choose ASIC library FPGA options include device family part speed grade and pin selection Advanced settings Select max fanout p e bi technology settings Technology Tab FPGA Specify part speed grade wire load use of IOB registers A
17. rted by slack time end points report slack arrival required times at end points start points report slack arrival required times at start points clock frequency no io terminals no internal terminals only primary outputs show input pins gate inputs show nets net names gate pin through node list gt paths through given nodes from start gt paths starting at given points to end points paths ending at given points not through node list gt no paths through the given nodes show schematic number Examples next page Delay report examples report delay critical paths num_paths I clock frequency show nets delay rpt Report the most critical path num paths 1 and the max clock frequency and list all nets along the path default is to show gate outputs only report delay longest path num paths show nets to list PRODUCT DONE outdelay rpt Report longest path from primary inputs or flip flops to primary outputs PRODUCT and DONE Asterisk matches any character string so PRODUCT matches PRODUCT 0 PRODUCT 1 report delay longest path num paths show nets from 156 MCAND START indelay rpt Report longest path from primary inputs MCAND and START to flip flop inputs or primary outputs
18. st for 374 party tool Xilinx Behavioral model to be synthesized modulo 7 counter with asynchronous reset and synchronous load count library ieee use ieee std logic l64 all use ieee numeric_std all entity modulo is port count load reset clk in std logic l unsigned 2 downto 0 unsigned form of std logic vector out unsigned 2 downto 0 defined in IEEE numeric std package modulo7 architecture Behave of modulo 7 is signal 5 unsigned 2 downto 0 begin process reset clk begin if reset 0 then Q s lt 000 async reset elsif clk event and clk 1 then if count 1 Q_s 110 then Q_s lt 000 count rolls over elsif count I then Q_s lt Q_s l increment count elsif load I then Q_s lt synchronous load end if end if end process lt 5 drive the outputs end Synthesized netlist 1 Definition of modulo7 Thu Sep 21 10 48 09 2006 LeonardoSpectrum Level 3 2005 82 library IEEE use IEEE STD LOGIC 1164 all entity modulo 7 is port count std logic load IN std logic reset IN std logic clk IN std logic IN std logic vector 2 DOWNTO 0 Q OUT std logic vector 2 DOWNTO 0 end modulo Synthesized netlist 2 architecture Behave of modulo7 is signal 2 EXMPLR EXMPLR 0 EXMPLR reset nx4 14 nx22 nx48 nx60 nx169 nx179 nx189 nx20
19. straint variables Affect design decisions set max fanout load 5 Global limit on max inputs driven by one output Leonardo splits nets or adds buffers as needed but buffers add delay Override with max fanout load attribute on a net set attribute nl name max fanout load value 10 Constrains only net nl set max fanin 5 set max cap load 4 set max transition 2 set max pt8 max product terms in a sum Load and Drive Constraint Attributes gt output load value out signall out signal output fanout value out signall out signal2 unit loads fanout loads driven by the output Use to calculate delays drive capability May need buffers on selected outputs input max load value in signall in signal2 input max fanout value in signall in signal2 Max unit loads fanout load presented to a circuit input May need inserted buffers to reduce loads input drive value in signall in signal2 Additional delay in ns unit load for an input port Balancing Loads Resolve load violations throughout the design Fix loads after changing attributes without rerunning optimize Load balancing always done as part of optimize Pays attention to OUTPUT LOADS OUTPUT FANOUTS Mostly used at boundaries of hierarchical modules Optimize balances loads within modules Command balance loads design name single Wire Load Table not used with ADK GDK Use to estimate routing delays Exact delays known o

Automated synthesis from VHDL models

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