User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. If you generated you FPGA bitstream using Diamond FPGA you do not need any other handling The app file created can be used as is to configure the FPGA If you used Xilinx ISE and created a bit file you need to use the Sundance executable Getrawdata exe provided for free in the SMT6001 package Please read the SMT6001 help file at chapter Saving FPGA configuration data to file The resulting file can be used as is to configure the FPGA Up to 4 Mbytes of ODR2 SRAM per bank The memory is available as 4 independent banks The ODR2 memory runs at 250MHz Fach bank is fully independent with separate address control and data busses and arranged as follows Viernm Vareri2 XCAV QQ 15 0 QD 15 0 NC QSA 19 0 QWn QRn QK QKn output CQ input Vierm Vreri2 Figure 3 FPGA connections to Bankl of ODRII The devices used are Samsung K7R321884M Alternative part numbers fully compatible can be fitted depending on availability at time of order 4 2 9 Sundance High speed Bus 2 x 60 pin connectors provide 80 IO connections between the FPGA and the outside word They allow interfacing to other Sundance modules providing that you implement an SHB interface in the FPGA See 2 1 The SHB interface is available in Sundance SMT6500 support package Either two 16 bit or 1 32 bit interface can be implemented per connector They allow interfacing to the outside world by implementing your o2. Unit Module Description User Manual Unit Module Number SMT348 Document Issue Number 1 0 4 Issue Date 06 11 2006 Original Author E P User Manual Revision History 1 1 0 0 O First First release 06 11 06 1 EZ 1 Minor inconsistency LS comports removed 26 02 07 E P from block Diagram kuid Clarification about the elements in the JTAG 15 11 07 k chain Updated JTAG header information Wrong 29 02 08 marking of position Added chapters about bitstream formatting FPGA configuration Corrected External Clock I O J1 MMBX 07 03 11 Table of Contents 1 KEV T OK VUO O kaanon tavat vaa tavat ta mt bana ea auia ideia cai added icido 6 2 Related D OCUTMOTII E 7 2 1 Referenced Documents ess cana oa oa oa Da DA EDAD DA DADE DD DA DA DADE DA DA DR DR DADE DA DD DA DA DADE nd naa emma Dn n 7 2 2 Applicable Documents E 7 3 Acronyms Abbreviations and Definitions mewnuennnnnnnnnnnnnannnnnnnnnnnnnenanenn 8 3 1 Acronyms and Abbreviations noon eaa aamen ana aa aaaaaan 8 Ge EIERE 8 4 Functional eenegen 9 So Ik DES K Dikkaesattett DEI ALUDE EE 9 4 2 Module Descrtptton e oen ta oa oa DE aa DADE a a a a a aa aa aa a aa aamuna naan an nannaa 10 L E Ta EE 10 422 CPLD RE DA NANNININ NANNININ 10 4 2 3 FLASH MEMORY EE 10 2 24 TLA eae E daamadi eege enee 10 4 2 5 FPGA Configuration SCHEMES anata DA DA DA DA aa anna naamaa nama anaea 11 4
3. 2 0 FPGA Reset S CMS E 12 4 2 7 FPGA Bitstream formatting mimma kaak 13 3 28 IDR SRAM EE 14 4 2 9 Sundance High speed BUS anoo aaa kallal TEKE asa 15 4 2 10Sundance Low voltage BUS sccccsccscecssatarecssscersccsescssetecsaseiteesscstsesnatedtosinaettensenctessacse 15 a LEE 16 EE ed lt 1 a a ce ne ve sa 16 4 2 13Clocking SCOTS laidudele 17 AZ VALE E 17 RM Kee a eee ee eee eee ee AEA DA DADE EE EAA EE JOSKIN en eter 17 43 Interface TCS ee E 17 4 3 1 Power Budget AEN 17 5 EO OTETUN EG 22 SLT OD VIEW e e E E E 22 5 2 EENEG 23 6 PINO E 24 6 1 FPGA Pin allocation by bank memuenvenvanvennanvannannannannannannannannannannennannannanna 24 EAR eer 24 Gis SEB LLL 24 GA JING moinen liiat EEDENI ENN 25 7 Qualification Requirements EE 25 10 11 7 1 Qualification Tests isiimmmissaamamasns s anmskassnavaamanas n dada dada anita na dia dida dinda nano 25 7 1 1 Meet Sundance standard specifications aeon aamen 25 7 1 2 Speed qualification EE eebe ee 26 7 1 3 Integration Qualification tests 26 Support Packages ARREPENDER SE ARENA APNR RAR RR RR 26 Physical Properties ee 27 SAKOT Ylimaallinen aa date daca aave red sta eu oon 28 EMA hei ji e i a i it 29 Table of Figures Figure 1 Block DIAG TAR ccecccasedecaderetacederdoscorececorednne tecedevadesetaoedoraderetecederncererkGeveestenetacedersdereteereets 9 Figu ure 2 CPLD state TAC O O S DR RR IA DDa LAR IDA LITROS DATA AVIA inaani einari kiii 13 Fi
4. 6 6 6 6 6 o o o 6 6 6 6 COCO 00000 07070007 eee L 0 0 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 e j x o o O e lt pa O Wa O o o lt O 00 00 O 00 00 ee ee gt 14 mem 2 W 3 E E I Wal lt J 2 LL B E 6666666 6666 66 66 6 o 6 6 6 o 6 6 6 6 66 6 6 6 66 6 66 se e oe e e e ee E E E E E E e e e e e Figure 5 Bottom view 6 Pinout 6 1 FPGA Pin allocation by bank Clocks amp DLL control Bank C Data Control Bank B Data Control Bank D Data amp Control Bank A Data amp Control 1xSHB 2xCP 1xSHB 2xCP Vr Vrp Vrn Vref Table 13 Pin allocation by Bank 6 2 SHB SUNDANCE SHB specification 6 3 SLB SUNDANCE SLB specification 8xConfig Clocks amp Reset amp Switches PXI TTL SLB LVTTL 13 Control INTs LEDs Misc 32 Data amp 31 Address amp 1 Control 16 Diff Data amp 4 Diff Clocks 16 Diff Data amp 4 Diff Clocks 13 64 64 64 64 64 64 64 64 46 46 6 4 JTAG ee H ee H e H e D ki ee AK AK JK AK eege ege ege ee ee ee 06 e e ee e ee e e e TLU TIILI HTOTUT e e e e e e e e e e see K See A KA IK IK KA IK AO e eee JK WG AK IK A KA AK A KA HIVIN e WW WWW WW EL UEL 0 00 6 00 0 0 0 0 0 0 0 0 0 0 0 0 o o SA 0 0 0 0 6 0 0 0 0 ogc 8 Mitten Figure 6 JTAG Connector top view 7 Qualification Requirements 7 1 Qua
5. DSP where the FPGA provides all Firmware functionality A proprietary FPGA design providing some sort of functionality Sundance Firmware is the firmware running in an FPGA of a DSP module 4 Functional Description This module conforms to the TIM standard Texas Instrument Module See TI TIM specification amp user s guide for single width modules It sits on a carrier board The carrier board provides power 5V 3 3V 12V ground communication links Comport links between all the modules fitted and a pathway to the host for a non stand alone system The SMT348 reguires a 3 3V power supply as present on all Sundance TIM carrier boards which must be provided by the two diagonally opposite mounting holes 4 1 Block Diagram Flash memory 11 VOpins a Figure 1 Block Diagram 4 2 Module Description e Block and AIS Xilinx Virtex 4 XC4VSX55 LX160 and configuration scheme e Block2 ODR2 SRAM memory e Block3 IO connectors for general purpose or dedicated interfaces BBa SOMHz or 200MHz local clocks and external clock input e HIIS LEDs for development and in use monitoring and general purpose use Xilinx Virtex 4 XC4VSX55FF1148 or XC4VLX160FF1148 FPGA This device is packaged in a 1148 pin BGA package Xilinx Coolrunner II device XC2C256 6CP132C This device is packaged in a 132 ball BGA type package with a 6 speed grade It can be used to configure the FGPA via Comport 3 or from
6. 4 XC4VLX160FF1148 V18 1 1 8 829 1 497 Virtex 4 power 11 HSTLII A estimator design implementation of 4 independent gdrii controllers gt co J E _ E i HSTL power plane V18 1 1 8 6000 10 8 TI TPS54611PWP 1 8v capacity Excess power 3 525 Table 7 Power budget on 1 8v Device Nam Ouantit Voltage V Current m Power W Source e y A ODRII Vtt V09 240 0 9 18 0 3 89 Samsung ODRII 25 termination datasheet rev1 1 p 9 resistor 50 ohms See details HSTL Vtt 3000 5 76 Fairchild ML6554CU termination Power obsolete Plane 0 9v capacity 1 87 Excess power Table 8 Power budget on ODRII 0 9v Termination voltage Device Name Ouantity Voltage V Current mA Power W Source ODRII Vref VR09 8 0 9 0 0 Samsung ODRII 25 datasheet rev1 1 p 9 XC4VLX160FF1148 11 VRO9 16 0 9 0 01 0 000144 DS302 v1 17 HSTL Vref table 3 p 3 Total power consumed VRO9 0 000144 HSTL Vref plane 0 9v VRO9 1 0 9 3 0 0027 Fairchild capacity ML6554CU obsolete Excess power 0 002556 Table 9 Power budget on ODRII and FPGA 0 9v reference voltage Device Name Ouantity Voltage V Current mA Power W Source 25 Mhz Clock V33 1 3 3 15 0 05 Jauch VX3 Ouartz oscillator crystal oscillators datasheet 200 Mhz Clock V33 1 3 3 20 0 066 Ja
7. A switch is used to select the Flash as the source for the configuration bitstream e Using the on board JTAG header and Xilinx JTAG programming tools The JTAG header is a Parallel TV Header Note Using JTAG to configure the FPGA bypasses the CPLD which controls configuration The following section describes the CPLD role and the reset scheme used As the CPLD is bypassed when JTAG is used to configure the FPGA it is necessary to adopt one of the three following ways e If your FPGA design does not implement comport3 o do not use the Reset signal generated by the CPLD but use the TIM reset signal as your design s reset You can use JTAG to configure your FPGA with your application and the design will reset and run everytime you issue a new TIM reset e If your design implements comport3 o Setthe switch to configure the FPGA from flash after reset In this way a default bitstream being stored in flash will be loaded in the FPGA by the CPLD In this manner the CPLD has gone trhough the cycle of configuring the FPGA and releases the reset FPGAresetn Then you can reconfigure the FPGA via JTAG with your application o Set the switch to configure from comport 3 After reset configure the FPGA via JTAG and provide an end key word on comport 3 to the CPLD so that it releases the Reset FPGAresetn 4 2 6 FPGA Reset Scheme The CPLD is connected to a TIM global Reset signal provided to the SMT348 via its primary TIM connector pi
8. a configuration stored in flash memory The flash memory is programmed using the CPLD and data via the ComPort3 S29GL256N11TFIO1 is a 256Mbit flash from Spansion It can be used to configure the FPGA at power up Flash accessed using Comport3 via the CPLD Flash programming selection via switch SW1 See Table 3 Software Library Support available from Sundance The code can run on Sundance DSP TIM or a Host All the flash functionalities are available The JTAG header is compatible with Xilinx Parallel IV cable signals It supports code download for the FPGA FPGA configuration Hardware and Software Debugging tools for the Virtex 4 This cable connects the parallel port of an engineer s Workstation PC to the JTAG chain of the SMT348 Module All the Xilinx devices from block1 are chained and accessible via this JTAG header 4 2 5 FPGA Configuration schemes Different schemes are available to provide maximum flexibility in systems where the SMT348 is involved The FPGA configuration bitstream source is e OnComport 3 The CPLD is connected to the Comport 3 link of the SMT348 TIM connector See block1 A switch is used to select Comport 3 as the link that will be used to receive the bitstream The CPLD allows for FPGA configuration in slave SelectMAP mode e Using the on board Flash memory The CPLD monitors the configuration data between the Flash and the FPGA The FPGA configuration is operated in Slave SelectMap mode
9. able to the User D4 D5 D6 D7 1 Green Led DI connects to the DONE pin of the FPGA and is lit to show that the FPGA is configured depending on supply from manufacturer a red led can be fitted instead 4 2 15 Performance The FPGA features like speed grade and density dictate most performances The performances achievable by the other components are given in the chapters above and the components respective data sheets 4 3 Interface Description For the TIM to carrier board or external world interfacing see in Sundance Help file that you can download from the Sundance Wizzard 4 3 1 Power Budget The SMT348 draws its power from the 3 3v rail of the PCI The PCI specification stipulates that the maximum power for one card is 25W Therefore the maximum current that the SMT348 could draw from 3 3V is 7 6A assuming zero current on all the other supply voltages But this limit is system dependent so a given system might not have the full 7 6A available for a slot even if it is the only PCI card in the system A system might balance the power capabilities differently between the 5V and 3 3V and 12V supplies rather than making 25W available from 5V and 25W available from 3 3V User Manual SMT348 Page 17 of 29 Last Edited 07 03 2011 15 41 As aresult check your main power supply ratings If your system is likely to reach 25W per power rail we advice that you provide extra power to the carrier board usin
10. g an external power supply Device Table 4 Total available power Name Ouantity Voltage V Current mA Power W Source PCI specifications Device Nam Ouantit Voltage V Curren Power W Source e y UMA XC4VLX160FF1148 11 Vfpg 1 1 2 1 805 2 166 Virtex 4 Vccint 1 2v a N E ower design implementation of 4 estimator independent qdrii controllers Fpga Vccint power Vfpg 1 1 2 14000 16 8 TI plane capacity a TPS50410 Table 5 Power budget on 1 2v Device Name Ouantity Voltage V Current mA Power W Source XC4VLX160FF1148 V25 40 2 5 10 1 Virtex 4 power 11 Vcco 2 5v LVDS estimator TX pairs on SLB bus XC4VLX160FF1148 V25 27 2 5 12 0 81 Virtex 4 ds302 11 Vcco 2 5v v1 17 p 7 LVCMOS TX on SIB bus Total power V25 1 81 consumed Fpga 2 5v power V25 1 2 5 1 5 3 75 LT1963 1 5A Linear plane capacity Regulator 3 3v to 2 5V 1 5A Excess power 1 94 Table 6 Power budget on 2 5v User Manual SMT348 Page 18 of 29 Last Edited 07 03 2011 15 41 Device Name Ouantity Voltag Current m Power W Source e V A Samsung ODR II V18 4 1 8 800 5 76 Samsung ODRII burst 4 18 bit 25 datasheet interface rev1 1 p 9 ML6554CU DC DC VIS 1 1 8 0 01 0 018 Fairchild converter ML6554CU obsolete Coolrunner V18 1 1 8 0 55 0 00099 Ise 8 2 03i Xpower XC2C256CP132 software version 1 3
11. gure 3 FPGA connections to Bank1 of ODRIL rentes 14 pis han ado S ITE ek lt RD ama E 22 CEET Mee 23 Figure 6 JTAG Connector TOP EIERE 25 Table of Tables Table 1 DIP switch SW1 position for special reset feature 16 Table 2 DIP switch SW1 position for the selection of the configuration bitstream SOUT CO A ca sheceselibdsctes seated cacees vacecacessdledeseceucceleusdueeuuuces E T 16 Table 3 DIP switch SW1 position for the selection of the Flash erase amp program ODETATIOMS wees eeaeee ee E E e a EE Ee AEE EE EEE EEEE 148 16 Table 4 Total available power E 18 Table 5 Power DUAget ON E 18 Table 6 Power BUALCL ON 25V eu metstuet kalastades kadakad asetet EDAD etes ot SE akadi lakates noetak eta nas 18 Table 7 Power budget on E 19 Table 8 Power budget on ODRII 0 9v Termination Voltage mrwrnrnrnrnnn 19 Table 9 Power budget on ODRII and FPGA 0 9v reference voltage saian n an anencnco 20 Tabl 10 P wer budget EE 20 Table 11 Coolrunner II resources summary cooooonomnnmn nomen aa a mea maana aa nannaa 21 Table 12 Coolrunner II pin resources ucuusuusuaena una e meam mama a a a auma a a aamua maa aca Dn Das 21 Table 13 Pin allocation by Bank EE 24 1 Introduction The SMT348 is an FPGA TIM module designed to be integrated in modular systems It is designed to connect to the huge range of other TIM modules and carriers developed by Sundance Sundance modular so
12. lification Tests 7 1 1 Meet Sundance standard specifications e Meetthe TIM standard specifications e Meetthe SLB specifications LVDS standard e Meetthe SHB specifications User Manual SMT348 Last Edited 07 03 2011 15 41 7 1 2 Speed gualification tests e ODR2 memory accesses at 250MHz 7 1 3 Integration gualification tests e Must work on ALL Sundance platforms as a root TIM module or as part of a network of TIMS on carriers e Mustbe able to work stand alone 8 Support Packages 9 Physical Properties Dimensions Weight Supply Voltages Supply Current 12V 5V 3 3V 5V 12V MTBF 10 Safety This module presents no hazard to the user when in normal use 11 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adeguate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot
13. lutions provide flexible and upgradeable systems The SMT348 is a TIM module aimed at completing the range of Sundance Virtex4 modules like SMT368 SMT362 SMT339 It provides a communications platform between an XC4VSX55 or XC4VLX160 FPGA and e 4banksof ODR2 SRAM at a freguency of up to 250Mhz e 232 bit SHBs e TIM Global Bus e LVDS connections for high speed parallel connections e LVTTL connections and connectors This variety of connectors and interfaces provides a wide range of development options for designers to explore the capabilities of the comprehensive Sundance TIM modules family 2 Related Documents 2 1 Referenced Documents SUNDANCE SDB specification SUNDANCE SHB specification SUNDANCE SLB specification Samsung ODRII Datasheet Spansion S29GLXXXN flash 2 2 Applicable Documents TI TIM specification amp user s guide Samtec OSH Catalogue page Virtex 4 Datasheet 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations TIM TI DSP Xilinx FPGA QDR CP SDB SHB Texas Instruments Module Texas Instrument Digital Signal Processor XilinxO Field Programmable Gate Array Ouad Data Rate ComPort Communication interface Sundance Digital Bus Communication interface Sundance High Speed Bus Communication interface 3 2 Definitions DSP Module Typically a TIM module hosting a TI DSP and a Xilinx FPGA FPGA only Module A TIM with no on board
14. n 30 See TI TIM specification amp User s guide This signal goes to the CPLD and the FPGA Nevertheless as a general rule for good practice the FPGA should not use this reset but should use the reset signal generated by the CPLD The CPLD provides another signal called FPGA Resetn that offers a better Reset control over the FPGA At power up or on reception of a low TIM global Reset pulse the CPLD drives the FPGAResetn signal low and keeps it low This is used to keep the FPGA design in reset A new FPGA configuration bitstream can then be downloaded When the ENDKEY has been received the CPLD drives FPGAResetn high Use FPGAResetn for the Global Reset signal of your FPGA designs In this manner you can control your FPGA design Reset activity and you will also avoid possible conflicts on ComPort 3 if your FPGA design implements it Comport3 is a communication resource shared by the CPLD and the FPGA But only 1 entity is allowed to use it at a time If you implement comport 3 in the FPGA you have to use Fpgaresetn generated by the CPLD as the comport is shared between the two The Reset control is operated by the CPLD line FPGAResetn The following diagram shows the CPLD states after Reset TIM Reset Or TIM Config pgaresetn asserted FPGA Configured and STARTKEY Received ENDKEY Received FPGA Configured Fpgaresetn de ag and ENDKEY Received Figure 2 CPLD state machine
15. t and various control signals References and specifications for these connectors are available in TI TIM specification amp user s guide 4 2 12 DIP Switches One four position DIP switch is connected to the CPLD to provide control over the selection of the configuration bitstream source and a special reset feature called TIM Confign SW1 pos 4 TIM Config ENABLED Table 1 DIP switch SW1 position for special reset feature Table 2 DIP switch SW1 position for the selection of the configuration bitstream source SW1 pos 3 2 1 JPC3 JPC2 JPC1 Table 3 DIP switch SW1 position for the selection of the Flash erase amp program operations The Flash erase amp program operations are operated by the CPLD Commands are provided via Comport3 from an application running on a Host or DSP Status information from the Flash is given over Comport3 as well The SMT348 module contains a SOMHz LVTTL clock a 200MHz clock and a connector for an external LVTTL clock input output 50 MHz LVTTL oscillator Main system clock Clocks the CPLD and the FPGA Can be input in a DCM 200MHz LVTTL oscillator ODRII clock Can also be used as a main FPGA clock Can be input in a DCM An external clock input is provided to the Virtex 4 FPGA via an MMBX connector This connector is NOT fitted by default or if a mezzanine is reguired YOU MUST ask Sundance if needed for your application 4 Red LEDs connect to the FPGA and are avail
16. uch VX3 Ouartz oscillator crystal oscillators datasheet Linear Regulator 3 3v V33 1 3 3 1 136 3 75 LT1963 1 5A to 2 5v 1 5A DC DC converter V33 13 75 N A Fairchild ML6554CU 3 3v to 0 9v obsolete DC DC converter V33 14000 N A TI TPS50410 3 3v to 1 2v DC DC converter V33 6000 N A TI TPS54611PWP 3 3v to 1 8v DIP Switch V33 1 3 3 0 7 0 002 Four 4 7 Kohm pullup Flash memory V33 1 3 3 90 0 297 S29GL256N XCAVLX160FF1 148 V33 1 3 3 Depends on Virtex 4 power 11 LVTTL Vcco 3 3v implemented estimator design 3 3v power plane V33 1 3 3 7600 25W TI TPS50410 Table 10 Power budget on 3 3v User Manual SMT348 Page 20 of 29 Last Edited 07 03 2011 15 41 Details Coolrunner XC2C256 6 CP132 power reguirements based on design Function Pins Used Block Inputs Macrocells Registers Used Used Used 218 256 86 531 896 60 190 256 75 69 106 66 445 640 70 Table 11 Coolrunner II resources summary Pterms Used Signal Type Reguired Mapped Pin Type Input I O Output GCK 1IO Bidirectional GTS IO GCK GSR IO GTS CDR IO GSR DGE IO Table 12 Coolrunner II pin resources 5 Footprint 5 1 Top View SHB FAN SWITCH FPGA JTAG ADR2 POWER SUPPLIES EXT CLK Figure 4 Top View HOSNIS dW3L WEE co tae aldd OLINOI TTT op GLOBAL TERMINATION T1 VO SHB v SLB DATA 5 2 Bottom View bP ad of Oe Oe OE OOOO OOO 0
17. wn interface in the FPGA The FPGA IO banks hosting the SHB signals are powered using Vcco 3 3V 4 2 10 Sundance Low voltage Bus This bus is present on the LX160 version of the module only This is an LVDS bus comprising data 2 x 16 bit buses I amp O clock and control signals They allow interfacing to Sundance mezzanine modules providing that you implement an SLB interface in the FPGA See 2 1 They allow interfacing to the outside world by implementing your own LVDS interface in the FPGA All LVDS data pins both I and O are connected to a 2 5 3 3V powered FPGA banks link selectable by jumper JP3 The FPGA LVDS DIFF TERM standard should be used instead of the DCI terminations when LVDS standard is selected DCI terminations are only available when a 2 5v standard is selected The LVDS Clock signals are also in these banks All LVTTL signals are connected to a 3 3V powered FPGA bank 4 2 11 TIM Connectors TIM connectors provide 4 communication links Comports and a Global Bus to the FPGA The comports which are available on the SMT348 are CP0 CP1 CP3 and CP4 They allow interfacing to Sundance TIM modules or to a Host PC providing that you implement a Comport Interface inside the FPGA See 2 1 The Comport interface is available in Sundance SMT6500 support package The FPGA io banks hosting the Comport signals are powered using Vcco 3 3v The TIM connectors also provide power ground rese
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