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ALMA2e PCI/VME 2eSST Bridge User Manual

1. VMEbus ENPIAN CONVERSION PCI bus data 031 24 D23 16 015 8 D7 0 31 24 23 16 15 8 7 0 MODE No Conversion BYTEO BYTE1 BYTE2 BYTE3 BYTEO BYTE1 BYTE2 BYTE3 BYTEO BYTE1 BYTE2 BYTEO BYTE1 BYTE2 BYTE1 BYTE2 BYTE3 BYTE1 2 BYTE1 2 1 2 BYTEO BYTE1 BYTEO BYTE1 BYTE2 2 BYTE1 BYTE1 BYTE2 BYTE2 BYTES BYTES MODE Address Coherency BYTEO BYTE1 BYTE2 BYTE2 BYTE1 BYTEO BYTEO BYTE1 BYTE2 BYTE2 BYTE1 BYTEO BYTE1 BYTE2 BYTES BYTES BYTE2 BYTE1 BYTE1 BYTE2 BYTE2 BYTE1 BYTEO BYTE1 BYTE1 2 2 1 1 2 2 MODE Data Coherency BYTE1 2 BYTES BYTEO BYTE1 2 BYTEO BYTE1 BYTE2 BYTEO BYTE1 BYTE2 BYTE1 2 BYTES BYTE1 2 1 2 BYTE1 2 BYTEO BYTE1 BYTEO BYTE1 BYTE2 BYTE2 BYTEO BYTEO BYTE1 BYTE1 BYTE2 BYTE2 BYTES BYTES MODE Bytes Translation with No Swapping BYTEO BYTE1 BYTE2 BYTE3 BYTEO BY
2. Width 8 Reset Value 0x00 Access type Read Write 25 24 17 16 1 Bit s Description Endian conversion performed when registers are accessed by the VME side 00 mode No Conversion 01 mode Address Coherency 10 mode Data Coherency 11 mode Bytes Translation with No Swapping 1 0 Byte 0 9 8 Byte 1 17 16 Byte 2 25 24 Byte 3 The conversion mode should be the same in the 4 registers If the two bits differs from register to register the functionality is undefined 2 58 12 10 03 ALMA2e User Manual VME SLVO VME Slave Channel 0 Control Register Same definition for address offset 0x80 0x88 0x90 0x98 0 OxA8 OxBO 0 8 Address from PCI interface Configuration space 0x80 space PCIH BA1 SPACE 0x80 Address from VME interface A16 space VME SLVA 0x80 A24 space CR CSR BAR BEG USER 0x80 Width 32 Reset Value 0x00000000 Access type Read Write VME SLVO offset 0 80 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11110 9181716 5 1 Bit s Description VME_SLV0 7_ADD 11 0 12 0 VME Slave Channel 0 7 base address The 12 bits of the incoming VME address A 31 21 are compared
3. Width 32 Reset Value 0x00000000 Access type Read Write ADEM 0 B03 31 30 29 28 27 26 25 24 23 16 15 SEN 0 Bit s Description 23 0 Read Only No effect on Write A read to this register returns 3 times the VME Address Mask bits 31 24 31 24 VME Address Mask bits 31 24 The FUNCTION 0 Address Decoder Mask ADEM register includes the following registers defined hereafter ADEM 0 at address 0x620 ADEM 0 02 at address 0x624 ADEM 0 01 at address 0x628 ADEM 0 00 at address 0x62C The following FUNCTION Address Decoder Mask ADEM registers have the same bit definition They are at offset addresses FUNCTION 1 ADEM at address 0x630 FUNCTION 2 ADEM at address 0x640 FUNCTION 3 ADEM at address 0x650 FUNCTION 4 ADEM at address 0x660 FUNCTION 5 ADEM at address 0x670 FUNCTION 6 ADEM at address 0x680 FUNCTION 7 ADEM at address 0x690 2 112 12 10 03 ALMA2e User Manual ADEM 0 02 ADEM byte 2 Address Decoder Mask Byte 2 Address from PCI interface Address from VME interface Config space not seen space PCIH BA1 SPACE 80000 0x624 A16 space not seen A24 space CSR BAR 0x624 Width 32 Reset Value 0x00000000 Access type Read Write ADEM 0 B02 31 30 29 28 27 26 25 24 23 16 15 8 Bit s Description 23 0 Read Only
4. Bit s Description IT ADD SET 7 0 7 0 Write a 1 to bits 7 0 of this register sets active interrupt sources respectively to Addressed interrupt number 7 to O IT ADD RESET 7 0 15 8 Write a 1 to bits 15 8 of this register desactivates interrupt sources respectively to Addressed interrupt number 7 to O 12 10 03 Version 0 3 ALMA2e REGISTERS 2 75 ALMA2e User Manual IBM IT AVIT ADD AVIT VME cycle Address Register Address from PCI interface Config space not seen space PCIH BA1 SPACE OxFO Address from VME interface A16 space not seen A24 space CSR BAR USER 0 Width 32 Reset Value 0x00000000 Access type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121111019 8 7 6 5 413211 Bit s Description AVIT ADD Address of the VME cycle generated upon PCI AVITb pin assertion IT AVIT CTRL AVIT VME cycle Control Register Address from PCI interface Config space not seen space PCIH BA1 SPACE OxF4 Address from VME interface A16 space not seen A24 space CSR BAR USER OxF4 Width 8 Reset Value 0x00 Access type Read Write 876543210 Bit s Description IT AM 5 0 Address Modifier of the VME cycle gener
5. ALMA2e User Manual IBM PCI BUSNUM PCI Bus Number register Address from PCI interface Config space 0x40 space PCIH BA1 SPACE 0x40 Address from VME interface A16 space VME SLVA 0x40 A24 space CR CSR BAR BEG USER 0x40 Width 8 Reset Value 0x00 Access type Read Write 7 6 5 4 3 2 1 0 Bit s Description 7 0 The PCI Bus Number register is used to identity the number of the PCI bus ALMA2e is connect to PCI SUBNUM PCI Sub Bus Number register Address from PCI interface Config space 0x41 IO space BA1 SPACE 0x41 Address from VME interface A16 space VME SLVA 0x41 A24 space CR CSR BAR BEG USER 0x41 Width 8 Reset Value 0x00 Access type Read Write 7 6 5 4 3 2 1 0 Bit s Description 7 0 The PCI Sub Bus Number register is used to identify the number of the last hierarchical bus behind ALMA2e 2 36 12 10 03 ALMA2e User Manual PCI ARB PCI Bus Arbiter Control register Address from PCI interface Config space 0x42 space BA1 SPACE 0x42 Address from VME interface A16 space VME SLVA 0x42 A24 space CR CSR BAR BEG USER 0x42 Width 16 Reset Value 0x0000 Access type Read Only PCI ARB 15 14 13 12 11 10 9 8171615431210 Bit s Description 0 PCI Arbiter mode ALMA2e has no longer internal PCI arbiter This bit is Read Write and has no effect 15 1 Reserved This bits
6. d Ped d 14 1 9 Addressing through the ALMA2e 15 1 9 1 VME to PCI aCCesS cues bs be RP b be 15 1 9 2 PCI to VME access 1K Entry Mapping 16 NNO TINING uus 18 1 10 1 Glock TIMING sexs ze MUS LIAE 18 1 10 2 PCI lO Specifications bed eek eae 18 140 3 VME26SST TIMINGS 4 Jer ei EI d RUE 19 REGISTER SEE eq c aes ce t Dd A 20 1 11 1 ALMA2e registers access 20 1 11 2 ALMA2e Registers 22 Chapter 2 ALMA2e REGISTERS 23 2 0 1 PCI Configuration 25 2 0 2 PCI OperationitegisterS SA dais 35 2 0 3 ALMA2e Utility 44 2 0 4 ALMA2e VME Registers 2 49 2 0 5 ALMA2E 1 61 2 0 6 ALMA2e Interrupt Operation 71 2 0 7 ALMA2e Extended Registers 81
7. Bit s Description DMA 1 ADDPCI 31 0 PCI starting address for DMA channel 1 Note At the end of each block size the PCI address of the next block size is loaded in this register 12 10 03 Version 0 3 ALMA2e REGISTERS 2 67 ALMA2e User Manual IBM DMA CHN1 XFERSIZE DMA Channel 1 Transfer Size register Address from PCI interface Config space OxD8 space PCIH BA1 SPACE OxD8 Address from VME interface A16 space VME SLVA 0xD8 A24 space CSR BAR USER 0xD8 Width 24 Reset Value 0x000000 Access type Read Write DMA 1 XFERSIZE 20119 18 17 16 15 14 13 121111109 817 6 5 14 13121110 Bit s Description 20 0 Total number of VME cycles to be performed for a DMA channel 1 transfer 23 21 Reserved return zero when read DMA CHN1 BLOCSIZE DMA Channel 1 Block Size register Address from PCI interface Configuration space OXDB space PCIH BA1 SPACE OxDB Address from VME interface A16 space VME SLVA OxDB A24 space CR CSR BAR USER OxDB Width 8 Reset Value 0x00 Access type Read Write DMA CHN1 BLOCSIZE 76543210 Bit s Description DMA CHN1 BLOCSIZE Total number of VME cycles to be performed for each of a DMA channel 1 transfer 2 68 12 10 03 ALMA2e User Manual DMA CHN1 CTRL DMA Channel 1 Control register Address
8. 1 0 1 1 BYTE3 BYTE1 BYTEO BYTE1 BYTEO 0000 0 0 1 10 1 BYTE2 BYTEO BYTES 2 BYTEO 0000 0 0 1001 0000 01 1 01 0 BYTE1 01 00 0101 2 2 1000 MODE Bytes Translation with Swapping 0 0 1 1 1 1 BYTES BYTE BYTEO BYTES 2 BYTE 0 0 0 0 0 0 0 1 1 1 BYTE2 BYTE1 BYTEO BYTE2 BYTE1 BYTEO 0 1 1110 1 2 BYTE1 1000 1 0 1 1 0 BYTE2 BYTE1 2 BYTE1 0 0 1 0 0 0 0 0 1 1 BYTE1 BYTEO BYTE1 BYTEO 0 0 O0 1 1100 BYTE2 BYTES BYTE2 0011 0 0 0 1 BYTEO BYTEO 0 1 O 1 0 1 0010 1 1 1001 2 2 0111 1 1 1000 1 0 1 1 0 0 1011 1 BYTEO 1 0000 1101 2 2 0000 1001 BYTEO 0000 0101 2 2 0 1 1 0 1 0 BYTE3 1 1 1000 PCI Interrupt Acknowledge access No Conversion mode 0001 1001 0010 1 1 1001 2 2 1001 1000 1001 9 154 12 10 03 ALMA2e User Manua
9. OxF6 Width 8 Reset Value 0x00 Access type Read Write 716543210 Bit s Description IT AVIT STATUS 0 PCI AVITb pin function is Disabled 0 1 PCI AVITb pin function is Enabled This bit is reset to 0 when the VME cycle or VME IRQ 7 1 generated by ALMA2e relatively to PCI AVITb asser tion is acknowledged 12 10 03 Version 0 3 ALMA2e REGISTERS 2 77 ALMA2e User Manual IBM IT VME IRQ Vector Register Address from PCI interface Config space not seen IO space PCIH BA1 SPACE OxF7 Address from VME interface A16 space not seen A24 space CSR BAR USER 0 7 Width 8 Reset Value 0x00 Access type Read Write 716543210 Bit s Description IT VEC 7 3 7 3 Five 5 most significant bits of the interrupt vector returned by ALMA2e in response to a interrupt acknowledge IACK cycle The level of interrupt being returned is on the 3 least significant bits of the VME data byte lane IT GEN VME IRQ Generation Register Address from PCI interface Config space not seen space PCIH BA1 SPACE OxF8 Address from VME interface A16 space not seen A24 space CSR BAR BEG USER OxF8 Width 8 Reset Value 0x00 Access type Read Write 716543210 Bit s Description IT IRQ GEN ENABLE 0 1 interrupt generation feature is Enabled 0 interrupt generation feature is Disabled IT IRQ GEN 7 1 1 VME IRQ 7
10. POWER ON signal V SYSRESETib signal 5 134 12 10 03 ALMA2e User Manual IBM The other sources of reset prevent VME accesses with AM 0x2F but the CR CSR BAR setting is maintained It is required to set bit 6 to 1 of the VME Slave Control register 0x7A to permit VME access with AM 0x2F 5 12 3 input signal AUTO_SLOT_ID is at 0 The Geographical Address GAs signals are sampled and stored in the BAR Register if the parity is compliant with the GAPb If the GA Parity is wrong 0x1E is stored in the CSR BAR Register 12 10 03 Version 0 3 INITIALIZATION amp RESET 5 135 ALMA2e User Manual IBM 5 136 12 10 03 ALMA2e User Manual IBM Chapter 6 INTERRUPTS 6 1 Interrupt Management overview ALMA2e implements an interrupt handler which supports the following operations Incoming interrupts connected to pin PCI AVITb Masking of interrupt sources which can produce an interrupt to the PCI Generation of interrupts to the PCI Generation of interrupts to the VME Handling the interrupt acknowledge cycles on VME Interrupt Registers OxEO 4bytes INT MSKSRC Interrupt Source Mask Register P INTAb OxE4 4bytes INT MSKOUT PCI Interrupt Mask Register OxE8 4bytes INT STATUS Interrupt Status Register OxXEC 2 INT CTRL PCI Interrupt Type Register OxEE 2bytes ADD SET Addressed Interrupt Register OxFO 4bytes AVIT ADD AVIT VME cycle Address Register
11. CHNO ADDVME 31 0 0x00 CHN1 ADDVME 31 0 0x00 DO The two following registers are programmed with the PCI starting address for DMA of Channel 0 and 1 12 10 03 Version 0 3 DMA Controller Operations 8 147 ALMA2e User Manual IBM CHNO ADDPCI 31 0 0x00 C4 1 ADDPCI 31 0 0x00 D4 By reading of these registers one can know the current VME PCI addresses these address registers are decremented as data are exchanged between busses The only allowed data sizes allowed by DMAs being D32 or D64 the address two low significant bits of the above four registers are always ignored on register writes and return zeroes on register reads The two following transfer count registers are programed with the total numbers of VME data cycles of 32 bit or 64 bit data beats for DMA of Channel 0 and 1 The loaded value must be equal to the desired num ber of VME data cycles minus one cycle since the zero value is counted CHNO XFRSIZE 21 0 0x00000 6 C8 1 XFRSIZE 21 0 0x00000 D8 The maximum total amount of data a DMA can transfer is then of 4 Million x VME D64 or D32 data cycles i e 512 MBytes if VME MBLT D64 cycles used or 256 Mbytes if VME BLT D32 cycles are used By reading of these registers one can know the remaining VME data cycles before DMA is completed The two following registers indicate the size of the DMA blocks in terms of a number of VME
12. FIFO Oxn lessthan 1 16 bytes left in VME FIFO OxF less than 256 bytes left in VME FIFO 31 29 Reserved This bits are read write and have no functions Note If register DPT CTL 1 is set to 0 register DRV CTL 31 0 must be left to O 12 10 03 Version 0 3 ALMA2e REGISTERS 2 87 ALMA2e User Manual IBM VSW CTL VME Slave Write Control register This register controls VME to PCI write transaction Address from PCI interface Config space not seen IO space PCIH BA1 SPACE 0x118 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x118 Width 32 Reset Value 0x00000000 Access type Read Write Recommended value 0x01030401 VSW CTL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 91817161514132 10 Bit s Description VME Slave Write control 0 set to 0 ALMA2e is unablet o write in VME FIFO while the PCI reads the VME FIFO for VME slave transaction set to 1 ALMA2e is able to write in VME FIFO while the PCI reads the VME FIFO for VME slave transaction 7 1 Reserved These bits are read write and have no functions PCI write burst length if VSW CTLJO is set to 0 0x00 32 Bytes burst size 0x01 64 Bytes burst size 0x02 128 Bytes burst size 14 8 0x04 256 Bytes burst size 0x08 512 Bytes burst size 0x10 1024 Bytes burst size 0x20 2048 Byt
13. IRQib 7 1 Interrupt Request input V_IRQo 7 1 Interrupt Request output V LWORDb 1 5 indicates size of data transaction V RETRYib VMEbus 2eSST RETRY Signal For 2eSST protocol only V_RETRYo VMEbus 2eSST RETRY Signal For 2eSST protocol only V_SYSCLK 1 5 System Clock signal output V SYSFAILib System input V SYSFAILo System Fail output V SYSRESETib System Reset signal input V_SYSRESETo System Reset signal output V WRITEb Us Write signal 12 10 03 Version 0 3 SIGNAL DESCRIPTIONS 3 117 ALMA2e User Manual 3 2 PCI bus interface signals Signal name 1 0 Out put Type External Pull up Pull down Description P_CLK PCI Bus Clock P ADL 31 0 1 5 PCI Address Data Bus ADH 31 0 1 5 PCI Address Data Bus for PCI64 transaction P CBELb S 0 1 5 Command Byte Enable 4 bit multiplexed bidirectional bus that transfers bus command and bytes enables During the address phase of a transaction these signals define the bus command During the data phase they are used as byte enables The byte enables are valid during the entire data phase and determine which byte lanes carry meaningful data P_BEHb 3 0 1 5 Byte Enable During the address phase of a transaction these signals are invalid During the data phase they are used as byte enables The byte enables are valid during the entire data phase and
14. 0x5F Width 8 Reset Value 0x00000000 Access type Read Write PCI RAMINDEX 7 6 5 4 31 21 1 Bit s Description 0 Reserved PCI RAMDFLT VAL 25 1 ALMA2e decodes PCI MEMORY or I O accesses 0 ALMA2e does not respond to PCI MEMORY or I O accesses 31 26 PCI RAMDFLT AM 5 0 2 42 VME cycle Address Modifiers 5 0 12 10 03 ALMA2e User Manual IBM PCI RAMDATA Mapping Table Data Register Virtual Register Address from PCI interface Configuration space 0x60 space BA1 SPACE 0x60 Address from VME interface A16 space VME SLVA 0x60 A24 space CSR BAR USER 0x60 Width 32 Reset Value 0x00000000 Access type Read Write PCI RAMINDATA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Read Write to Mapping Table 20 bit entry at offset PCI RAMINDEX 9 0 performed through Read Write access to register PCI RAMDATA 31 12 Bit s 11 0 12 13 14 16 15 22 17 31 23 12 10 03 Description Reserved PCI RAMDATA RA 1 Enable VME BLT mode for PCI to VME read access 0 Disable PCI RAMDATA WP 1 Enable Write Posted PCI to VME access 0 Disable PCI RAMDATA VAL Validates PCI I O and MEMORY accesses 1 and MEMORY accesses decoded by ALMA2e 0 ALMA2e does not respond to these acc
15. 12 10 03 Designation CHECKSUM LENGTH of ROM Config ROM data access width CSR data access width CR CSR space Specification ID ASCII C ASCII Manufacturer s ID Board ID Revision ID 0x000000 RESERVED Program ID Code Offset BEG USER CR Offset END SN Offset END USER CR Offset BEG CRAM Offset END RAM Offset BEG USER CSR Offset END USER CSR Offset BEG SN Offset END SN Slave Characteristics Parameters USER DEF Slave Characteristics Parameters Master Characteristics Parameter USER DEF Master Characteristics Param Interrupt Handler Capabilities Interrupt Capabilities RESERVED CRAM Access Width FUNCTION 0 Access Width FUNCTION 1 Access Width FUNCTION 2 Access Width FUNCTION 3 Access Width FUNCTION 4 Access Width FUNCTION 5 Access Width FUNCTION 6 Access Width FUNCTION 7 Access Width Version 0 3 Size 1 Byte 3 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 3 Byte 4 Byte 4 Byte 3 Byte 8 Byte 1 Byte 3 Byte 3 Byte 3 Byte 3 Byte 3 Byte 3 Byte 3 Byte 3 Byte 3 Byte 1 Byte 1 Byte 1 Byte 1 Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Address MSB LSB 123 143 163 183 1 1C3 1 203 223 2 323 423 4 523 623 633 643 653 663 673 683 693 6 6 7 6AB 6AF 6B3 603 753 13F 15F 17F 19F 1BF 1DF 1FF 21 29 81F 39F 41
16. This function is enabled when bits 31 16 of the register UTIL RST are written to a non zero value Maximum time interval allowed between 2 register write accesses is programed into the following register Bits UTIL_RST Register address 0x64 31 16 UTIL WDOG VALUE 15 0 00 gt Reset watchdog feature is Disabled X01 to FF hex gt Reset watchdog feature is Enabled Time out is programmable within a range starting from 4ms 01 hex up to 262 14 seconds FF hex by 4ms steps 12 10 03 Version 0 3 INITIALIZATION amp RESET 5 133 ALMA2e User Manual IBM 5 12 AUTO SLOT ID function The AUTO SLOT ID Function is a way to program at reset the CSR BAR registers of each cards that are on the same back plane This permits then to access the registers of ALMA2e It starts with all cards posting an interrupt IRQ2 on the Interrupt daisy chain AUTO SLOT 10 function is active only if input signal AUTO SLOT ID is at 1 This function is described in the VME64x norm 5 12 1 AUTO SLOT ID is at 1 During the POWER ON RESET and the SYSRESET ALMA2e activates signal SYSFAIL Active 0 ALMA2e generates an interrupt IT2 on IRQ2 The Register CR CSR BAR is Reset to 00 All access to ALMA2e registers with AM 0x2F are inhibited ALMA2e respond OxFE at the first IT2 Acknowledgement cycle After RESET desactivation The monarch see following note waits for the SYSFAIL desactivation from all the VME boards before starting I
17. BYTE1 0 1 1 0 0 BYTE2 BYTE2 0 0001 0 0010 1 BYTE1 1 010 0 BYTE2 BYTE2 0 1 0 0 0 BYTES 1 1 0 1 1 BYTE3 1 1 0 1 1 0 1 2 BYTEO BYTE2 BYTE3 0 1 0 1 BYTES BYTEO BYTEO 0 0101 BYTE2 BYTEO BYTEO BYTE2 0 1 0 1 0 BYTES BYTE1 BYTE1 1 Version 0 3 ENDIAN CONVERSIONS O coc000 20 0005 0 2 VME signals ooooo r F 0 OF OO 000 0000 9 153 ALMA2e User Manual IBM PCI bus data PCI bus data converted signals a 31 24 23 16 15 8 7 0 D31 24 023 16 D15 8 07 0 Q address Byte Enables 3 0 tS Q 1 0 complemented MODE Data Coherency a a 22 1111 BYTE2 BYTE1 BYTEO BYTES BYTE2 BYTE1 BYTEO 0000 0 1 1110 2 1 BYTES 2 BYTE1 0111 BYTE2 BYTE1 BYTEO BYTE2 BYTE1 BYTEO 1000 0 1 0 1 1 0 2 BYTE1 2 BYTE1 0010 110 0 BYTE2 BYTE2 0 0 O0 1 0 0 0 0 1 1 BYTE1 BYTEO BYTEO 0 0 1 1 1 1 100 0 0 1 0 1 1 0 2 2 1001 0 1 0010 BYTE1 BYTE1 0 1 1 1 0 0 0 0 0 1 BYTEO BYTEO 1 0 1 1
18. En Dma seq vmefailO Dma seq vmefail1 u A A Reserved ER Pci seq readfail Pci seq writefail Pci_seq_wpostfail Pci seq sizefail or pci seq sizefail64 Pci seq befail or pci seq befail64 it mng avitfail 6 Reserved Vme slv readfail Vme writefail Vme wpostfail Vme_slv_sizefail Vme_mst_xingfail m A ON Reserved 2 102 12 10 03 ALMA2e User Manual IBM GA Geographical Address register Address from PCI interface Config space not seen space BA1 SPACE 0x1F0 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x1F0 Width 8 Reset Value GAb pins Access type Read Only GA Bit s Description GA Geographical Address Read Only register represents the value sample on pins 4 0 Note 1 this register is in positive logic GAb pins are in negative logic If ALMAZe is slot 2 the pins will be set at Ox1D GA register will be set at 0x02 Geographical parity value is not show in this register Note 2 This register value is used by the ALMA2e to check if an VME 2eSST access concerns it 7 5 Reserved Return zero when read CSR USER DEF SUBUNIT NB Sub Unit Number register Address from PCI interface Configuration space Ox1F1 IO space PCIH BA1 SPACE Ox1F1 Address from VME interface A16 space V
19. PCI read burst length if DRP_CTL 0 is set to 1 0x00 32 bytes burst size 0x01 64 bytes burst size 0x02 128 bytes burst size 0x04 256 bytes burst size 15 8 0x08 512 bytes burst size 0x10 1024 bytes burst size 0x20 2048 bytes burst size Others values 32 bytes burst size Note if the PCI burst length is greater than the DMA blocksize ALMA2e generates a PCI burst size equal to the DMA burst size 31 16 Reserved This bits Read Write and have no functions Note If register CTL 0 is set to 0 the register CTL 31 0 must be left to 0 2 84 12 10 03 ALMA2e User Manual IBM PCR CTL PCI Read Control register This register controls PCI read for VME to PCI read access and PCI to VME DMA Address from PCI interface Config space not seen space PCIH BA1 SPACE 0 10 Address from VME interface A16 space not seen A24 space BAR USER 0x10C Width 32 Reset Value 0x00000000 Access type Read Write Recommended value 0x00000303 PCR CTL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description PCI restart Read mode 0 setto 0 ALMA2e waits until the PCI FIFO is empty before restarting a new PCI Read transfer setto 1 ALMA2e restarts new PCI read transfer if the PCI FIFO hit the FIFO lo
20. This component allows VMEbus single board computer and I O board vendors to develop solutions with PCI support taking thus advantage of the growing family of PCI components in the market VME backplanes applications with 2eSST protocol the SN74VMEH22501 universal bus transceivers is recommended ALMA2e is software compatible with the previous PCI to VME bridge called ALMA V64 since it covers all the ALMA 64 functionality at the exception of the internal PCI arbitration that is no longer implemented Also the pinning has been changed to take into account more advanced CMOS technology with a dual 2 5V 3 3V power supply 1 2 Operating Specifications ALMA2e PCI to VME Bridge Specifications Technology 0 25 um IBM CMOS SA 12bE Temperature Range 40 to 85 ambient 105 Junction Performance up to 70 MByte sec on the VME64x Estimate up to 256 MByte sec on VME with 2eSST protocol 840 MByte sec peak up to 528 MByte sec on the PCI 64 66MHz Signal l Os 252 Power Supply 2 5 5 Core 3 3V 5 I Os all I Os are 5V tolerant Power Dissipation est 0 9 W Worst case 66 Mhz Estimated Packaging 25 25 Ceramic BGA 360 ball 1 27mm pitch 12 10 03 Version 0 3 Overview 1 5 ALMA2e User Manual IBM 1 3 Features PCI Bus 64bit 66Mhz External Interrupt ALMA A D64 Interrupts from PCI Bus Request 4 1 Bus Grant PCI Bus PCI Bus PCI Bus Interrupt Requestor
21. the VMEbus 0000 0000 Timer is inactive Others Timer initial setting in microseconds 2 52 12 10 03 ALMA2e User Manual IBM VME Master Control register Address from PCI interface Configuration space 0x73 space PCIH BA1 SPACE 0x73 Address from VME interface A16 space VME SLVA 0x73 A24 space CSR BAR BEG USER 0x73 Width 8 Reset Value 0x00 Access type Read Write 716 3121110 Bit s Description 0 Reserved 1 Reserved Must be left to zero otherwise result is unpredictable VME MST ABORT 2 A BERR Acknowledgment on the VME bus is translated onto the PCI bus as a 1 Normal acknowledgment 0 Target Abort VME MST LECPERF Recommended setting is 1 3 Controls the DTACK handling latency on Master Reads and thus has an effect on the data transfer rate 0 Normal handling of V DTACKib assertion on Reads 1 Fast handling of V DTACKib assertion on reads VME MST VMEPERF 1 0 These 2 bits control latency between data phases on Master Writes MASTER state machine and thus has an 4 5 effect on the data transfer rate 00 01 11 Normal latency between data phases on master Writes 10 Low latency between data phases on master Writes Recommended setting is bits 29 28 10 VME MST PCIPERF 1 0 Recommended setting is bits 31 30 10 These 2 bits control latency between data phases on Master Writes FIFO data routing latency and thus has 6 7 an effect on the data transfer rate 00 01 11
22. 2 0 8 Control Status CSR 105 2 0 9 Configuration ROM CR 109 Chapter 3 SIGNAL DESCRIPTIONS 115 3 1 VME bus interface signals 1 1 117 3 2 PCI bus interface SignalS onze epi eh omar WO PER pinu 118 3 3 General purpose 119 3 4 JTAG sighals 2c Ee Ro T EESTI Li ep 121 3 5 Manufacturing Test signal 2 21 4 121 Chapter4 PACKAGING 123 4 1 Ceramic BGA 25mm 361 Package 124 Chapter 5 INITIALIZATION amp 127 Neu 127 12 10 03 Version 0 3 3 ALMA2e User Manual IBM 5 2 Reset with ON 128 5 3 Reset controlled by the 129 5 4 Reset controlled by the Addressed Reset operation 130 5 5 Reset controlled by the V SYSRESETib input VME SYSRESET 131 5 6 Reset controlled by the Reset 0 131 5 7 Sampling hardware 5 131
23. 26 25 24 23 22 21 20 19118 17 16 15 14 13 12 11 109 8 7 6 5 413211 Bit s Description Function 0 Channel 9 LEBE Data byte ordering conversion mode performed on this channel 00 mode No Conversion 01 mode Address Coherency 10 mode Data Coherency 11 mode Byte translation with no swapping Function 0 Channel 9 WRITE POST 2 setto 0 Write Post for this channel is disable setto 1 Write Post for this channel is enable Function 0 Channel 9 READ AHEAD 3 setto 0 Read Ahead for this channel is disable setto 1 Read Ahead for this channel is enable 6 4 Function 0 Channel 9 BUSCOM PCI Bus Command 3 1 of the PCI cycle generated by ALMA2e Function 0 Channel 9 Enable 7 setto 0 the VME Function 0 VME slave channel 9 is disable setto 1 the VME Function 0 VME slave channel 9 is enable OFFSET Address translation 31 8 Value to add to the VME address to obtain the PCI address PCI address 31 0 VME address 31 0 OFFSET 31 8 The following CSR user function control registers have the same bit definition They are at addresses USER FUNC1 CTL at address 0x188 USER FUNC2 at address 0x190 USER at address 0x198 USER FUNCA at address 0x1A0 USER FUNCS5 at address 0x1A8 USER 6 at address 0 1 0 USER FUNC7 at address 0x1B8 12 10
24. OxF4 1 bytes IT_AVIT_CTRL AVIT VME cycle Control Register OxF5 1 bytes IT_AVIT_DATA AVIT VME cycle Data Register OxF6 1 bytes IT_AVIT_STA AVIT Interrupt Status Register OxF7 1 bytes IT_IRQ_VEC VME IRQ Vector Register OxF8 1 bytes IT_IRQ_GEN VME IRQ Generation Register OxF9 bytes ACK1 7 VME IACK Level 1 Level 7 Registers 0 1 0 4bytes CSR USER DEF INT MSKOUTI1 Interrupt Mask register1 INT1b 0 1 4 4bytes USER DEF INT MSKOUT2Interrupt Mask register2 INT2b Ox1E8 4bytes USER DEF INT MSKOUTSInterrupt Mask register3 INT3b Ox1EC 4bytes USER DEF INT MSKFAIL Interrupt Mask FAIL register PCI Bus VME Bus ALMA2e lt Interrupt lt IRGib 7 1 Controller IRQo 7 1 INT1b lt INT2b lt INT3b lt Figure 6 1 Interrupt Signals controlled ALMA2e 12 10 03 Version 0 3 INTERRUPTS 6 137 ALMA2e User Manual IBM 6 2 Generating Interrupt to the VME from the PCI AVITb pin This feature is useful for a standalone board in order to be able to generate an interrupt to the VME by connecting a PCI interrupt signal INTA for example to pin PCI AVITb According to programmed value of the following configuration bit the generated VME interrupt can be materialized either by VME IRQ7 1 interrupt signals activation or via generation of a specific cycle called AVIT VME cycle IT AVIT IRQSEL bit
25. Reset Value 0x00000000 Access type R W CSR_USER_XRATE 31 30 29 28 27 26 25 24 23 22 21 20 11911817 16 15 14 13121110 9 8 7 6 5 4 38 2 1 0 Bit s Description General Purpose Register Bran Used to store data No other action results from a Read or a Write CSR USER DEF VME TIME CSR user function Address from PCI interface Config space not seen space BA1 SPACE 0x1C8 Address from VME interface A16 space not seen A24 space BAR USER 0x1C8 Width 64 Reset Value 0x00000000 Access type Read Write CSR USER VME TIME 63 32 31 0 Bit s Description 63 0 CSR USER VME TIME Time estimate of VME bus busy 12 10 03 Version 0 3 ALMA2e REGISTERS 2 99 ALMA2e User Manual IBM CSR USER DEF VME USED CSR user function Address from PCI interface Config space not seen space BA1 SPACE 0 1 Address from VME interface A16 space not seen A24 space BAR USER 0x1D0 Width 64 Reset Value 0x00000000 Access type Read Write CSR USER VME USED 63 32 31 0 Bit s Description CSR USE
26. V BBSYib BBSYo V BERRib V BERRo V BCLRb V SYSRESETib V SYSRESETo V SYSCLK V RETRYib V RETRYo VME CLK VME_SYSCONT_INb VME_BASE_ADD6 VME_BASE_ADD7 OEb ADIR AMDIR ASDIR DDIR DSDIR DTACKDIR General POWER_ON_RESETb Purpose RESETINb signals RESETOUTb 31 SYSFAILINb SYSCONDIR OC CTL PWSR CTL AUTO SLOT ID GAb 4 0 GAPb Figure 5 ALMA2e Signal Pins block diagram 3 116 12 10 03 ALMA2e User Manual IBM 3 1 VME bus interface signals All Pull Down resistors must be lower or equal to 3KOhm Output External TA Signal name 1 0 Type Pull Up Description Pull Down A 81 1 1 5 VME Address bus V_ACFAILib Power Fail V AM 5 0 1 5 Address Modifiers V ASb Us Pull Up Address Strobe V BCLRb Us Pull Up Bus Clear V BBSYib Bus Busy input V BBSYo Bus Busy output V BERRib Bus Error input V Bus Error output BGIND 3 0 Bus Grant daisy chain input V BGOUTPb S3 0 Bus Grant daisy chain output V BRib 3 0 Bus Request input V BRo 3 0 Bus Request output V D 31 0 1 5 Data bus V DTACKb Us Pull Up Data Transfer Acknowledge V DSb 1 0 1 5 Pull Up Data Strobes V IACKb 1 5 Interrupt Acknowledge V_IACKINb Interrupt Acknowledge daisy chain input V IACKOUTb Interrupt Acknowledge daisy chain output
27. on page 5 8 Sampling VME System Controller pin During power on reset only ALMA2e samples VME_SYSCONT_INb pin by loading its logical state into register bit SVME ARB SYSCONTb 971 12 10 03 Version 0 3 INITIALIZATION amp RESET 5 131 ALMA2e User Manual IBM 5 9 Suggested usage of RESETINb and RESETOUTb pins In the case of a so called PCI native machine PCI bus reset signal RST may be directly connected to input RESETINb while output RESETOUTb stays unused In the case of a so called VME native machine PCI bus reset signal RST and other board devices reset inputs may be directly connected to output RESETOUTb to allow for resetting of the whole board from the VME Input RESETINb is then connected to the board reset controller to the reset button in the more simple case 5 10 VME SYSFAIL Handling The VME SYSFAIL signal may be controlled by the software through the bit 0 of the UTIL VMECNTL register at address 0x68 Bit s UTIL VMECNTL Register address 0x68 0 SYSFAIL ext bit written to a 1 ALMA2e generates SYSFAIL asserts V_SYSFAILob low bit written to a 0 ALMA2e de activates SYSFAIL asserts V SYSFAlLob high The initial value of that bit depends upon which type of reset is used This bit is initialized to 0 only in the case where reset is controlled by the POWER input and provided input PWSR CTL is wired to logic 1 In all other cases the UTIL SYSFAIL bit will be init
28. operation it asserts RETRY during address phase 3 to request for the transfer to be restarted 1 5 2 PCI bus interface PCI Bus command ALMA2e initiates and responds to a subset of PCI bus commands PCI bus command is defined by the P CBELb 3 0 signals during the address phase of a transaction The Table 1 defines the PCI bus command subset that the ALMA2e supports as a slave and as a master TABLE 0 2 PCI Commands supported by ALMA2e P CBELb 3 0 Command Type Supported as Slave Supported as Master 0000 Interrupt acknowledge No Yes 0001 Special Cycle No Yes 0010 IO read Yes Yes 0011 IO write Yes Yes 0100 Reserved No Yes 0101 Reserved No Yes 0110 Memory Read Yes Yes 0111 Memory Write Yes Yes 1000 Reserved No Yes 1001 Reserved No Yes 1010 Configuration Read ies Ma d ik 1011 Configuration Write DD ed Us Mi 1100 Memory Read multiple Yes Aliased to Memory Read Yes 1101 Dual Address cycle No No 1110 Memory Read Line Yes Aliased to Memory Read Yes 1111 Memory Write amp Invalidate Yes Aliased to Memory Write Yes 12 10 03 Version 0 3 Overview 1 11 ALMA2e User Manual IBM PCI Master Interface The ALMA2e PCI master interface can generate cycle all the MEMORY cycles Interrupt Acknowledge Special cycle and Type 0 and 1 Configuration cycles Interrupt Acknowledge or Special Cycle can be initiated from the VME through a rea
29. 0 Signal SYSFAIL generated by ALMA2e is de activated 7 1 Reserved 8 UTIL SYSRESET State of signal SYSRESET of the VME Bus 0 non active 1 active 15 9 Reserved 23 16 UTIL CONFIG 7 0 The state of VME Address input signals V A 8 1 is loaded in this register during Resets 24 Reserved 31 25 Reserved 2 46 12 10 03 ALMA2e User Manual IBM UTIL ERRSTA Error Status Register Address from PCI interface Configuration space 0x6C space PCIH BA1 SPACE 0x6C Address from VME interface A16 space VME SLVA 0x6C A24 space BAR USER 0x6C Width 32 Reset Value 0x00000000 Access type Read Write UTIL ERRSTA 31 30 29 28 27 26 25 124 23 22 21 20 19 18 17 16 15 14 13 12 11 1019 8171615143210 Bit s Description Error bits definition When at 0 no error reported 10 11 12 13 17 14 12 10 03 VME arb timeoutfail When ALMA2e is VME system Controller If after an arbitrated bus grant no VME agent has asserted a V BBSYb within 8 mS VME mst nodata ALMAGe is the target of a PCI single data access for which all PCI Byte Enables lines are inactive no data to transfer VME_slv_sizefail ALMAGe is the target of a VME BLT or MBLT access for which data beat size is 032 064 VME slv wpostfail ALMAGe is the target of a VME write posted access and PCI e
30. 1 011 128 111 2 GB PCI ARS BA2 PCI Base Address 2 size 000 16 MB 100 256 MB 14 12 001 32MB 101 512 010 64 110 1 011 128 111 2 GB PCI ARS EN 15 0 PCI Base address are fixed and equal to 256MB 1 PCI Base address size are programmable and given by registers PCI ARS BAx above 2 40 12 10 03 ALMA2e User Manual IBM PCI BASPACE PCI Base Address Space register Address from PCI interface Config space 0 5 space PCIH BA1 SPACE 0x5B Address from VME interface A16 space VME SLVA 0x5B A24 space CSR BAR BEG USER 0x5B Width 8 Reset Value 0x03 Access type Read Write PCI BASPACE 71615 4 3121110 Bit s 12 10 03 Description PCI BASPACE 6 0 Base Address 6 is mapped in MEMORY Space 1 Base Address 6 is mapped in Space Note PCI BAR 6 is fixed and mapped to I O Space if PCI BASPACE EN 0 PCI BASPACE BA5 0 Base Address 5 is mapped in MEMORY Space 1 Base Address 5 is mapped in Space Note PCI 5 is fixed and mapped to I O Space if PCI BASPACE EN 0 PCI BASPACE BA4 0 Base Address 4 is mapped in MEMORY Space 1 Base Address 4 is mapped in Space Note PCI BAR 4 is fixed and mapped to MEMORY Space if PCI BASPACE EN 0 PCI BASPACE 0 Base Address 3 is mapped in MEMORY Space 1 Base Address is mapped I O Space Note PCI BAR 3 is fixed and mapped to MEMORY Space if PC
31. 1 interrupt is are generated 0 No interrupt is generated ALMAQ2e asserts the V_IRQo 7 1 pins selected by those bit 7 1 at 1 2 78 12 10 03 ALMA2e User Manual IT 2 3 4 5 6 7 VME IACK Level 1 VME IACK Level 7 Registers When ALMA2e forwards IRQ 7 1 interrupt to a PCI interrupt the PCI Interrupt Handler issues then an interrupt acknowledge cycle as a read access to the one ACK 8 bit register associated with the interrupt level ALMA2e translates that PCI read cycle into a VME IACK cycle and the vector returned by the VME interruptor agent is forwarded to the PCI bus as read data of the addressed ACK register The Seven ACK 1 8 registers have the same definition Address from PCI interface Address from VME interface Width Reset Value Access type 7161514131211 7161514131211 7161514131211 7161514131211 7161514131211 7161514131211 7161514131211 Bit s Description 7 0 IT ACK1 7 0 Address 7 0 217 01 Address 7 0 IT ACK3 7 0 Address 7 0 IT ACK4 7 0 Address 7 0 ACK5 7 0 Address 7 0 IT ACK6 7 0 Address 7 0 ACK7 7 0 Address 12 10 03 Version 0 3 Config space not seen IO space PCIH BA1 SPACE OxF9 A16 space not seen A24 space CSR BAR USER 0 9 8 0x00 Read Only IT ACK1 Address 0 9 IT ACK2 Address OxFA IT ACK3 Addres
32. 12 10 03 Version 0 3 SIGNAL DESCRIPTIONS 3 121 ALMA2e User Manual IBM 3 122 12 10 03 ALMA2e User Manual IBM Chapter 4 PACKAGING 12 10 03 Version 0 3 PACKAGING 4 123 ALMA2e User Manual IBM 4 1 Ceramic BGA 25mm 361 pin Package 25mm BGA Top view through package 360X 070 89 25 0 20 lim 22 86 T gt WV UTRPNML FEDCBA 4 OO0OOcOOOOOOOOOOOOOO 2 Ooeoooeoeceooeeceoceo OGoeoeoceocooceceoeooco 5 O oeocecooeceoececeo O60e oceoceoooeoooceoceo 8 0 2 2 2 4 lO Soeoeoceoeooeoeoceoceo 5 amm y Y N 25 0 20 22 86 19 x 19 Pad array 360 total pads 252 signal I Os 24VDD2 5V 108 power 30VCC3 3V Viewed through top of package C4 Encapsulation fillet N 015 C SEATING PLANE Not to scale all dimensions are in millimeters Figure 6 360 pin Ceramic
33. 49 51F 59F 61F 62F 63F 64F 65F 66F 67F 68F 69F 6CF 74F FFF Designation FUNCTION 0 AM Code Mask FUNCTION 1 AM Code Mask FUNCTION 2 AM Code Mask FUNCTION 3 AM Code Mask FUNCTION 4 AM Code Mask FUNCTION 5 AM Code Mask FUNCTION 6 AM Code Mask FUNCTION 7 AM Code Mask FUNCTION 0 XAM Code Mask FUNCTION 1 XAM Code Mask FUNCTION 2 XAM Code Mask FUNCTION 3 XAM Code Mask FUNCTION 4 XAM Code Mask FUNCTION 5 XAM Code Mask FUNCTION 6 XAM Code Mask FUNCTION 7 XAM Code Mask FUNCTION 0 Address Decoder Mask FUNCTION 1 Add Deco Mask FUNCTION 2 Add Deco Mask FUNCTION 3 Add Deco Mask FUNCTION 4 Add Deco Mask FUNCTION 5 Add Deco Mask FUNCTION 6 Add Deco Mask FUNCTION 7 Add Deco Mask RESERVED RESERVED RESERVED Master Data Access Width Master Data AM Capabilities Master Data XAM Capabilities RESERVED ALMA2e REGISTERS Size 8 Byte 8 Byte 8 Byte 8 Byte 8 Byte 8 Byte 8 Byte 8 Byte 32Byte 32Byte 32Byte 32Byte 32Byte 32Byte 32Byte 32Byte 4 Byte 4 Byte 4 Byte 4 Byte 4 Byte 4 Byte 4 Byte 4 Byte 1 Byte 1 Byte 1 Byte 1 Byte 8 Byte 32Byte 555 bytes 2 109 ALMA2e User Manual Configuration ROM CR Registers details Address 0x03 B3 B7 BB BF C3 C7 0x620 0 623 0 624 0 627 0 628 0 620 0 62 0 62 2 110 Size 1 bytes 3 bytes 3 bytes 3 bytes 1 bytes 3 bytes 1 bytes 3 bytes 1 bytes 3 bytes 1 bytes Name CHECKSUM Offset BEG USER CSR Offset END USER C
34. 5 4 Reset controlled by the Addressed Reset operation This type of reset occurs when a Write to bits 8 and 9 of the register UTIL RST 264 is done from either the VMEbus or PCI bus ALMA2e takes the following actions depending upon the 2 bit value which is loaded into register UTIL RST 9 8 Detailed operations controlled by the UTIL_RST_ADD 1 0 bits setting are described below Bit s UTIL RST Register address 0x64 9 8 UTIL ADD 1 0 00 no action RESETOUTh if active is de asserted 01 ALMA2e generates SYSRESET 10 ALMA2e generates RESTOUTb 11 ALMA2e generates SYSRESET and RESTOUTb 1 Writing 01 to UTIL RST ADDJ1 0 ALMA2e generates V SYSRESETo for 201m even if it is not VMEbus System Controller Sequence of actions is the following ALMA2e processes the write access to register UTIL ADD 1 0 When the access is completed ALMA2e performs a brief Internal reset note that UTIL_RST_ADD is not affected samples hardware configurations see chapter 5 7 Sampling hardware configurations on page 131 generates V SYSRESETo and starts a 201ms timer Upon 201ms timer expiration ALMA2e de activates V_SYSRESETo 2 Writing 10 to UTIL RST ADD 1 0 ALMA2e generates RESETOUTb for 201ms max Sequence of actions is the following ALMA2e processes the write access to register UTIL RST ADD 1 0 When the access is completed ALMA2e performs a brief Internal reset note that UTIL RST ADD is not affected samples hardware
35. 5 8 Sampling VME System Controller 131 5 9 Suggested usage of RESETINb and RESETOUTb pins 132 5 10 VME SYSFAIL Handling arm RR e mnn 132 5 11 Reser Walchd0og irnn ioa tw moneta S NUR RUE BUR onn 133 542 AUTO SLOT ID function aee PEE a ee ES Pa 134 5 121 AUTO SEOT IDS 3t 12 2c t LRL ERR uL Rc RE ERES 134 5 12 2 Normal AUTO SLOT ID operations 134 5 12 3 input signal AUTO SLOT 10 is 0 135 Chapter 6 INTERRUPTS eee Xx 137 6 1 Interrupt Management 137 6 2 Generating Interrupt to the from the PCI 138 6 2 1 AVIT 5 138 6 2 2 VME Interrupt Request Cycle 7 17 138 6 3 Masking and Generating interrupts to the 139 6 34 Routing to Interrupt case eek ey ess ee 140 6 3 2 Routing to INT1b 2b 3b pins with CSR USER DEF INT MSKOUT 141 6 4 Interrupt sources translated to an interrupt to 142 6 4 1 VME Interrupts our epe RE p e
36. 6 5 41 831 21 110 Bit s Description 31 0 User s Data The two following 32 bit registers have the same definition as CSR USER DEF REGO CSR USER DEF 1 Address Offset 0 1 8 CSR USER DEF REG2 Address Offset 0x1FC 2 104 12 10 03 ALMA2e User Manual 2 0 8 Control Status CSR Registers The definition of the following control registers can be found in the VME64 EXTENSIONS ANSI VITA 1 1 1997 Oct 7 1998 specification Reference 2 Address Ox7FFFF Ox7FFFB Ox7FFF7 Ox7FFF3 Ox7FFEF Ox7FFEB Ox7FFE3 Ox7FFE7 Ox7FFDS Ox7FFDF Ox7FFCS Ox7FFCF Ox7FFB3 Ox7FFBF Ox7FFA3 Ox7FFAF Ox7FF93 Ox7FF9F Ox7FF83 Ox7FF8F Ox7FF73 Ox7FF7F Ox7FF63 Ox7FF6F Ox7FCOO Ox7FF5F 12 10 03 Size 1 bytes 1 bytes 1 bytes 1 bytes 1 bytes 1 bytes 2 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 216 bytes Name CR CSR BAR BIT SET BIT CLEAR CRAM OWNER USER DEF BIT SET USER DEF BIT CLEAR RESERVED FUNCTION 7 ADER FUNCTION 6 ADER FUNCTION 5 ADER FUNCTION 4 ADER4 FUNCTION 3 ADER FUNCTION 2 ADER FUNCTION 1 ADER FUNCTION 0 ADER RESERVED Version 0 3 Use Page Notes Base Address Register for CR registers 106 BIT SET Register BIT CLEAR Register Configuration RAM OWNER Register USER DEFINED BIT S
37. 7 of the register IT AVIT CTRL 7 at address OxF4 0 gt PCI AVITb pin assertion is translated into AVIT VME cycle Read or Write 1 PCI AVITb pin assertion is translated into a VME IRQ7 1 interrupt 6 2 1 VME cycle A low level applied on input pin PCI AVITb will make ALMA2e to request a VME access D08 EO to the address programed into the register IT AVIT ADD 31 0 at address OxFO The VME cycle is of type ODD or EVEN depending upon the value of the bit 0 IT AVIT ADD 0 0 gt EVEN data is mapped to 008 015 IT AVIT ADD 0 1 gt ODD data is mapped to 000 007 The VME cycle Address Modifier is programed into the register IT AVIT CTRL 5 0 at address OxF4 No coherency checking is done by ALMA2e on the Address Modifier provided to VME VME cycle Read or Write mode is programed into the register IT AVIT CTRL 6 0 Write cycle 1 Read cycle In the case of a Write cycle the 8 bit data provided is programed into the register IT AVIT DATA 7 0 at address OxF5 AVIT DATA 7 0 data written to the VME In the case of a Read cycle data received from the VME is ignored by ALMA2e When such a AVIT VME cycle is acknowledged by the VME either through DTACK V DTACKb or BERR V BERRib a status bit will be set to zero in order to disable PCI AVITb interrupt handling A new PCI AVITb interrupt request could be serviced when the status bit is reset to one through a write to th
38. 9 8 or XAM 7 6 C 15 10 Toup Compare bits 15 10 C 23 16 Compare bits 23 16 C 31 24 31 The following registers in addition with FUNCTION 7 ADER defines up to 8 VME channels 21 Compare bits 31 24 They have the same definition FUNCTION 6 ADER FUNCTION 5 ADER FUNCTION 4 ADER FUNCTION 3 ADER FUNCTION 2 ADER FUNCTION 1 ADER FUNCTION 0 ADER 12 10 03 Version 0 3 Address Decode Compare 6 Address Decode Compare 5 Address Decode Compare 4 Address Decode Compare 3 Address Decode Compare 2 Address Decode Compare 1 Address Decode Compare 0 address 0x7FFC3 address 0x7FFB3 address Ox7FFA3 address Ox7FF93 address Ox7FF83 address Ox7FF73 address Ox7FF63 ALMA2e REGISTERS 2 107 ALMA2e User Manual IBM 2 108 12 10 03 ALMA2e User Manual 2 0 9 Configuration ROM CR Register Following is the set of registers that are defined in the CR Configuration ROM space These registers are R W implemented in ALMA2e and the user has the flexibility to define it according to the VME64 Extension Norm See reference 2 A read at a Reserved address returns always a Zero Address MSB LSB 03 07 OB OF 13 17 1B 1F 23 27 2B 2F 33 37 3B 3F 43 47 4B 4F 53 57 5B 5F 7B 7F 83 87 8B D7 DB DF 8F 93 97 9B 9 7 7 C3 C7 CB CF D3 D7 DB DF E7 EB EF F3 F7 FB FF 103 107 10B 10F 113 117 11B 11F
39. D 30 E15 V 010 E16 V D 9 E17 V D 5 E18 V D 8 E19 V D 6 F01 REQ64b F02 GND F03 ADH 24 04 F05 P PAR64 F06 GND F07 ADH 14 F08 VDD 09 ADH 10 F10 GND 11 V D 13 F12 VCC F13 V D 29 14 GND 15 V D 1 16 VCC F17 V D 7 F18 GND F19 ASb 001 P STOPb G02 GND 003 P ADH 27 004 VCC 005 P ADH 31 006 PADH 23 907 VCC 008 P ADH 13 G09 CE RI G10 V D 831 Gi V D 26 G12 V D 15 G13 V D 20 014 V AM 2 G15 G16 V 0 4 POWER ON RESETb G17 V D 2 G18 D 0 G19 V LWORDb 01 P DEVSELb VDD P ADH 29 H04 GND 05 P ADL 31 VCC 07 VCC H08 GND 09 P ADH 2 H10 VDD H11 D 25 H12 GND H13 V AM 3 H14 VDD H15 VME BASE 007 H16 GND H17 V 4 H18 VCC H19 AMDIR 401 FRAMEb 102 ADH 21 103 ADH 26 404 P_ADH 28 J05 P ADL 29 06 ADH 25 07 ADL 30 108 ADH 30 Jog VDD J10 GND Ji1 VDD J12 RESERVED_1 J13 PWSR_CTL 414 V_D 3 45 J16 117 0 J18 5 J19 K01 GND ADL 26 K04 VDD K05 GND K06 GND K07 ADL 27 VDD K09 GND K10 GND Ki1 GND K12 VDD K13 V_A 28 4 GND 12 10 03 Version 0 3 PACKAGING 4 125 ALMA2e User Manual Pin Signal name Pin Signal name Pin Signal name Pin Signal name Pin Signal name K15 A 27 K16 VDD K17 OC_CTL 8 GND K19 ADIR 101 P_IRDYb 102 VCC 103 P ADL 22 104 ADL 18 105 GN
40. INDEX counter is loaded with a given starting offset then any subsequent write or read access to the PCI RAM DATA register address will automatically increment the counter Current value of Mapping Table offset can be known at any time by reading PCI RAM INDEX register 12 10 03 Version 0 3 Overview 1 21 ALMA2e User Manual IBM 1 11 2 ALMA2e Registers The following diagram shows the ALMA2e s register addressing organization For compatibility with previous product and because the 512KB CR CSR Configuration ROM Control Status Register space starts at zero from the VME side the ALMA2e Configuration space and ALMA2e Extended Space are accessed with 2 different addresses from the PCI ALMA2e ALMA2e Config Space E CR Config Space 256 Regs Configuration ROM 256 Regs ALMA2e FFF Extended x BEG USER CR END USER CR Config RAM Unused PEG CRAM END CRAM BEG USER CSR User CR Space CR Configuration ROM ALMA2e Config offset 8 0000 Space 256 Regs use CSR CR CSR 512KB ALMA2e User CR Space Extended END USER CSR pollere CSR User CSR Space Reserved ALMA2e Config VME64 defined CSR Space 256 Regs VME64x defined CSR ALMA2e Extend 7 00 Config RAM Unused CSR Reserved VME64 defined CSR VME64x defined CSR From PCI From VME From VME IO Space A24 A16 Figure 4 ALMA2e Addressing Model 1 22 12 10 03 ALMA2e User Ma
41. MB s rate 0x3 OxF Reserved Reserved This bit is reserved and return zero when read 12 10 03 ALMA2e User Manual 2 0 6 ALMA2e Interrupt Operation Registers The following Interrupt Registers are uses for Interrupt control in ALMA2e The seven registers IT ACKi are Virtual A write access from the VME or the PCI bus to these registers has no effect A Read access from the VME bus to one of these register reset it to O A Read access from the PCI bus to one of these register results in an acknowledgment cycle of interrupt on the VME bus Address Size Name OxEO 4 bytes IT INT MSKSRC 0 4 4 IT INT MSKOUT OxE8 4bytes INT STATUS OxEC 2bytes INT CTRL OxEE 2bytes ADD SET RESET OxFO 4bytes ADD OxF4 bytes CTRL OxF5 bytes DATA OxF6 _ bytes STA 0 7 1bytes IRQ OxF8 bytes GEN OxF9 7 bytes IT ACK1 to IT ACK7 12 10 03 Version 0 3 Use Interrupt Source Mask Register PCI Interrupt Mask Register Interrupt Status Register PCI Interrupt Type Register Addressed Interrupt Register AVIT VME cycle Address Register AVIT VME cycle Control Register AVIT VME cycle Data Register AVIT Interrupt Status Register VME IRQ Vector Register VME IRQ Generation Register VME IACK Level 1 VME IACK Level 7 Registers ALMA2e REGISTERS Page 72 73 73 74 75 76 76 77 77 78 78 79 Notes 2 71 ALMA2e User Manua
42. No effect on write A read to this register returns 3 times the VME Address Mask bits 23 16 31 24 VME Address Mask bits 23 16 ADEM 0 01 ADEM byte 1 Address Decoder Mask Byte 1 Address from PCI interface Address from VME interface Width Reset Value Access type Config space not seen space BA1 SPACE 80000 0x628 A16 space not seen A24 space CSR BAR 0x628 32 0x00000000 Read Write ADEM 0 01 31 30 29 28 27 26 25 24 23 16 15 amp 7 Bit s Description 23 0 Read Only No effect on write A read to this register returns 3 times the VME Address Mask bits 15 8 31 24 VME Address Mask bits 15 8 12 10 03 Version 0 3 ALMA2e REGISTERS 2 113 ALMA2e User Manual IBM ADEM 0 BOO ADEM byte 0 Address Decoder Mask Byte 0 Address from PCI interface Config space not seen space BA1 SPACE 80000 0x62C Address from VME interface A16 space not seen A24 space CR CSR BAR 0x62C Width 32 Reset Value 0x00000000 Access type Read Write ADEM 0 B00 31 30 29 28 27 26 25 24 23 16 15 2 Bit s Description 23 0 Read Only No effect on write A read to this register returns 3 times the above Byte 3 of ADEM 0 00 24 EFM E
43. PCI from PCI to VME AVME starting address the VME address from which data are read from or written to anaddress aligned on a 4 byte boundary or a 8 byte boundary for the VME starting address depending upon VME cycles used are BLT 32 bit data beats or MBLT 64 bit data beats respectively A PCI starting address the PCI address from which data are read from or written to an address aligned on a 4 byte boundary for the PCI starting address 32 bit data beats Atransfer count maximum programmable size is 2 Mega VME data cycles data beats A block count maximum programmable size is 256 VME data cycles data beats VME Address Modifiers of the VME cycles to generate PCI Bus Command of the PCI cycles to generate An enable bit for allowing block count transfers of the two channels to be interleaved DMA completes when its transfer count is exhausted DMA completion can be signalled via an interrupt to the PCI bus The event reflected into the control signal seq finishO seq finish1 is recorded into bits 7 and 6 respectively of the Interrupt Status Register INT INT STATUS see chapter 6 4 Interrupt sources translated to an interrupt to PCI on page 142 Abnormal conditions during DMAs are recorded into the Error Status Register 2 6C bits 21 18 8 2 DMA Channels programming The two following registers are programmed with the VME starting address for DMA of Channel 0 and 1 respectively
44. PCI Edge detection ALMA V64 asserts BGLOCb pin 2 the PCI agent which requested the VME bus by asserting the BRLOCb pin is granted Edge detection 10 ALMA_V64 deasserts BGLOCb pin ALMA V64 is asking for the VME bus to be released Edge detection 13 11 Reserved 14 SYSFAIL Level detection 15 ACFAIL Level detection 16 Addressed interrupt no 0 Level detection 17 Addressed interrupt no 1 Level detection 18 Addressed interrupt no 2 Level detection 19 Addressed interrupt no 3 Level detection 20 Addressed interrupt no 4 Level detection 21 Addressed interrupt no 5 Level detection 22 Addressed interrupt no 6 Level detection 23 Addressed interrupt no 7 Level detection 24 Reserved 25 VME IRQ1 Level detection 26 VME IRQ2 Level detection 27 VME IRQ3 Level detection 28 VME IRQ4 Level detection 29 VME IRQ5 Level detection 30 VME IRQ6 Level detection 31 VME IRQ7 Level detection 12 10 03 Version 0 3 INTERRUPTS 6 139 ALMA2e User Manual IBM LEVEL Following Interrupt sources are detected active on the signal level and therefore are not memorized VME IRQ7 to IRQ1 VME interrupt sources on bits 31 25 Addressed Interrupt sources Addressed Interrupt no 7 to no 0 on bits 23 16 ACFAIL and SYSFAIL interrupt sources on bits 15 14 For those Level detected interrupt source the generated PCI interrupt stays active until the source itself is disabled writing a O or a 1 to the
45. SLV A64 VME Slave A64 Address register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0 120 Address from VME interface A16 space not seen A24 space CR CSR BAR USER 0x120 Width 32 Reset Value 0x00000000 Access type Read Write VME SLV A64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 14113 121 11 10 9 8 7 6 51 141 31 21 1 Bit s Description 31 0 VME Slave Upper Address bits for A64 VME access VME MST A64 VME Master A64 Address register Address from PCI interface Config space not seen IO space PCIH BA1 SPACE 0 124 Address from VME interface A16 space not seen A24 space CR CSR BAR USER 0x124 Width 32 Reset Value 0x00000000 Access type Read Write VME MST A64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121111019 87 615 413211 Bit s Description 31 0 VME Master Upper Address bits for A64 VME access 12 10 03 Version 0 3 ALMA2e REGISTERS 2 91 ALMA2e User Manual IBM DMAO VME A64 DMA Channel 0 VME A64 upper bits Address register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x128 Address from VME interface A16 space not
46. a A16 or A24 or A32 VME Address VME A16 VME A24 VME A32 2 60 OFFSET OFFSET Generated PCI Address on 32 bits 12 10 03 ALMA2e User Manual 2 0 5 ALMA2E Registers Address 0xCO 0xC4 0xC8 OxCB O0xCC OxCE OxCF 0 00 0 04 0 08 OxDB OxDC OxDE OxDF 12 10 03 Size 4 bytes 4 bytes 3 bytes 1 byte 2 bytes 1 byte 1 byte 4 bytes 4 bytes 3 bytes 1 byte 2 bytes 1 byte 1 byte Name DMA CHNO ADDVME DMA CHNO ADDPCI DMA CHNO XFRSIZE DMA CHNO BLOCSIZE DMA CHNO CTRL DMA CHNO DMA CHNO RATE DMA 1 ADDVME DMA CHN1 ADDPCI DMA CHN1 XFRSIZE DMA CHN1 BLOCSIZE DMA CHN1 CTRL DMA 1 DMA CHN1 RATE Version 0 3 Use DMA Channel 0 VME Address DMA Channel 0 PCI Address DMA Channel 0 transfer size DMA Channel 0 Block size DMA Channel 0 Control DMA Channel 0 Extended Address Modifier DMA Channel 0 transfer Rate DMA Channel 1 VME Address DMA Channel 1 PCI Address DMA Channel 1 transfer size DMA Channel 1 Block size DMA Channel 1 Control DMA Channel 1 Extended Address Modifier DMA Channel 1 transfer Rate ALMA2e REGISTERS Page 62 62 63 63 64 65 66 67 67 68 68 69 70 70 Notes 2 61 ALMA2e User Manual IBM DMA CHNO ADDVME DMA Channel 0 VME Address register Address from PCI interface Config space 0 0 space PCIH BA1 SPACE 0xCO Address from VME interface A16 space VME SLVA 0xCO A24 spac
47. allows to selectively de activate the Addressed Interrupt sources A given Addressed Interrupt source may be cleared by resetting to zero its associated bit in the register This is done by writing a data equal to one to the selected register bit associated with that source IT ADD RESET 7 0 EF bit N20 gt Addressed Interrupt source number is cleared bit N21 Addressed Interrupt source number N is not cleared Bits to zero in the write data will not modify the corresponding register bits This register is readable from the VME or PCI ports 6 4 3 ALMA2e exceptions end of DMA or timeout Interrupts These interrupts sources refer to the following events listed below All sources are edge sensitive excepted for the ACFAIL and SYSFAIL ones level sensitive All these exceptions are maskable by the bit 8 of the IT INT MSKSCR register at address OxEO VME ACFAIL detected when input V_ACFAILb is asserted low This interrupt after masking is recorded into bit 15 register IT INT STATUS e VME SYSFAIL detected when input V SYSFAILib is asserted low This interrupt after masking is recorded into bit 14 register IT INT STATUS VMEbus Locking feature vme req wsr indicates that the software which currently owns the VMEbus is willing to release the bus through a write to a one of bit REQ LBG This interrupt after masking is recorded into bit 10 register IT INT STATUS VMEbus Locking feature vme req Ibg indica
48. are reserved and return zeros when read PCI SCTRL PCI Specific Control register Address from PCI interface Config space 0x44 space BA1 SPACE 0x44 Address from VME interface A16 space VME SLVA 0x44 A24 space CR CSR BAR BEG USER 0x44 Width 16 Reset Value 0x8000 Access type Read Write 15 14 13 12 111101 91876543210 Bit s 12 10 03 Description PCI bus size Read Only register 0 ALMA2e is connected to a PCI 32 bit bus 1 ALMA2e is connected to a PCI 64 bit bus Reserved Return zeros when read PCI SCTRL LAT16EN for debug purpose Must be left to 0 PCI SCTRL TARGLATEN for debug purpose Must be left to 0 PCI SCTRL NORETRY 0 ALMA2e retries PCI access to internal registers if the VME interface is busy 1 ALMA2e does not retry PCI access to internal registers PCI SCTRL NOMAP 0 Mapping table is used for PCI to VME access 1 Mapping table is not used PCI RAMDFLT is used for PCI to VME access Version 0 3 ALMA2e REGISTERS 2 37 ALMA2e User Manual IBM PCI Configuration Address register Address from PCI interface Config space 0 4 space PCIH BA1 SPACE 0x4C Address from VME interface A16 space VME SLVA 0 4 A24 space CR CSR BAR BEG USER 0 4 Width 32 Reset Value 0x00000000 Access type
49. bits determine where in PCI MEMORY or IO address space this region is located The size of this base address register is programmable as follow If PCI ARS EN 0 BAR size 256Mbytes bits 31 28 are R W bits 27 24 are RO If PCI ARS EN 1 and If POI ARS 2 000 BAR size 16Mbytes bits 31 24 R W If PCI ARS BA2 001 size 32Mbytes bits 31 25 are R W bit 24 is RO 31 24 If PCI ARS BA2 010 BAR size 64Mbytes bits 31 26 are R W bit 25 24 are RO If PCI ARS 2 011 BAR size 128Mbytes bits 31 27 R W bit 26 24 are RO If POI ARS BA2 100 BAR size 256Mbytes bits 31 28 are R W bit 27 24 are RO If POI ARS BA2 101 BAR size 512Mbytes bits 31 29 are R W bit 28 24 are RO If PCI ARS BA2 110 BAR size 1Gbytes bits 31 30 are R W bit 29 24 are RO If PCI ARS BA2 111 BARsize 2Gbytes bits 31 is R W bits 30 24 are RO See register PCI ARS at address 0x58 The definition of the following BA n SPACE registers is the same as the PCIH BA2 SPACE The only change is the BA field number They are at addresses SPACE at address 0x18 PCIH 4 SPACE at address 0x1C PCIH 5 SPACE at address 0x20 BA6 SPACE at address 0x24 2 32 Reset 0x1000 000 Reset 0x2000 000 Reset 0x3000 001 Reset 0x4000 001 12 10 03 ALMA2e User Manual PCIH ITLINE PCI Interrupt Line register Address from PCI interface Address fr
50. determine which byte lanes carry meaningful data P PAR 1 0 t s Parity bit is even parity across P_ADL 31 0 and P_CBELb 3 0 The master drives P_PAR for address and write data phases the target drives P_PAR for read data phases P_PAR64 1 5 Parity bit is even parity across P ADH 31 0 _ 0 The master drives P 64 for address and write data phases the target drives PAR for read data phases P IDSEL Initialization Device Select is used as a chip select during CONFIGURATION read and write transactions P DEVSELb s t s Pull Up Device Select When actively driven indicates the driving device has decoded its address as the target of the current access P ACK64b s t s Pull Up Device Select for 64 bit transaction P FRAMEb s t s Pull Up Cycle Frame is driven by the current master to indicate the beginning and duration of an access P FRAMEb is asserted to indicate a bus transaction is beginning While this signal is asserted data transfers continue When it is deasserted the transaction is in final data phase P REQe64b s t s Pull Up 64 bit transaction request P IRDYb s t s Pull Up Initiator Ready indicates the signal is driven by the initiating agent s bus master s ability to complete the current data phase of the transaction During a write operation P IRDYb indicates
51. eu 142 6 4 2 Addressed 2 1 142 6 4 3 ALMA2e exceptions end of DMA or timeout Interrupts 143 6 5 Interrupters 5 cuna Rex E E EDEN ID La 144 6 5 1 ALMA2e VME interrupt generation through 144 6 6 ALMA2e response to VME interrupt acknowledge 145 Chapter 7 ERROR 146 Chapter 8 DMA Controller Operations 147 8 1 OVerVIG Ws esa beca ede dete Pacers ai ba EUR 147 8 2 DMA Channels 0 147 8 3 DMA Operation Timing 150 Chapter 9 ENDIAN CONVERSIONS 151 9 1 VME data Big Endian conversion to Little Endian 151 9 2 PCI data Little Endian conversion to Big Endian 153 12 10 03 ALMA2e User Manual IBM Chapter 1 Overview 1 1 ALMA2e GENERAL DESCRIPTION provide an highly integrated single chip solution to interface a VME64 bus with 2eSST protocol two edge Source Synchroneous Transfer and a 64 bit 66 Mhz PCI Bus All the bridge features are fully programmable from PCI bus or VME bus
52. for 53 setup is equal to 2 VME period 31 2 ns Note Check the speed you want to run before setting this register Recommended setting 0 Reserved This bit is Read Write and has no function ODDBIT This bit represents the value of the odd bit on VME 2eSST transfer Version 0 3 ALMA2e REGISTERS 2 95 ALMA2e User Manual IBM DISABLE WRITE BACK This feature is used only when ALMA2e generates a VME 2eSST DMA read read VME and write PCI and when the VME slave agent interrupts the VME transfer before the cycle count is reached 17 Setto 0 Write back is enable default value ALMA2e will calculate the new DMA blocksize taking account of the less data on the previous cycle Setto 1 Write back is disable The DMA engine does not check the number of data transfer data will not be transferred 31 18 Reserved This bits are read write and have functions Note If register CTL 0 or CTL 1 is set to 0 register VME2ESST CTL 31 0 must be left to the reset value 2 96 12 10 03 ALMA2e User Manual IBM CSR USER FUNCO CTL user function 0 control register VME slave channel 9 control Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x180 Address from VME interface A16 space not seen A24 space CR CSR BAR USER 0x180 Width 32 Reset Value 0x00000000 Access type Read Write CSR USER FUNCO CTL 31 30 29 28 27
53. hardware configurations on page 131 5 6 Reset controlled by the Reset Watchdog When reset watchdog times out sequence of actions is the following ALMA2e performs internal reset generates RESETOUTb and starts 201ms timer Upon 201ms timer expiration ALMA2e de activates RESETOUTb and Internal reset hardware configurations are sampled see chapter 5 7 Sampling hardware configurations on page 131 The event reflected into control signal UTIL wdg reset is recorded into Error Status bit 1 register UTIL ERRSTA 7 6C set to a 1 and may generate an interrupt to the PCI bus see chapter Interrupt sources translated to an interrupt to PCI on page This bit as for the others register bits could be cleared only upon assertion of POWER ON RESETb or via a write to the register 5 7 Sampling hardware configurations During resets ALMA2e samples a given number of input pins which are used to set hard wired ALMA2e configuration from external switches or pull up down resistors Sampling of these hard wired inputs is done as follows logical states of pins VME BASE ADD 7 6 GAP GAB 4 0 are loaded into register SLVA 7 0 978 Bit 7 VME BASE ADD7 Bit 6 VME BASE ADD6 Bit 5 GAP Bit 4 0 GAB 4 0 logical state of pins A 8 1 are loaded into register UTIL VMECNTL 23 16 96A no function is attached to this register field For explanations about above hard wired pins see Chapter SIGNAL DESCRIPTION
54. register set to 0x00 2 34 Config space 0x3E space not seen access ends with Master Abort termination A16 space VME_SLVA 0x3E A24 space CR_CSR_BAR BEG_USER_CSR 0x3E 8 0x00 Read Only Config space 0x3F space not seen access ends with Master Abort termination A16 space VME_SLVA Ox3F A24 space CR CSR BAR BEG_USER_CSR Ox3F 8 0x00 Read Only 12 10 03 ALMA2e User Manual 2 0 2 Operation registers Address 0x40 0x41 0x42 0x44 0x46 0 4 0 50 0 54 0 58 0x5A 0 5 0 5 5 Ox5F 0x60 12 10 03 Size Name 1 byte PCI BUSNUM 1 byte PCI SUBNUM 2 bytes PCI ARB 2 bytes PCI SCTRL 2 bytes 4 bytes PCI CFGADD 4 bytes PCI CFGDATA 4byios PCI SPECIAL 2 bytes PCI ARS 1 byte 1 byte PCI BASPACE 2 bytes PCI RAMINDEX 1 byte 1 byte PCI RAMDFLT 4 bytes PCI RAMDATA Version 0 3 Use PCI Bus Number register PCI Sub Bus Number register PCI Bus Arbiter Control register PCI Specific Control register Reserved PCI Configuration Address register PCI Configuration Data register PCI Interrupt Acknowledge register Special Cycle register PCI Slave Address Range Size register Reserved PCI Base Address Space register Mapping Table Index register Reserved Mapping Table Default register Mapping Table Data register ALMA2e REGISTERS Page Notes 36 36 37 37 38 39 39 40 41 42 42 42 2 35
55. remain unchanged Address 2 low order bits are modified LEBE 11 Bytes Translation with No Swapping Data bytes are translated Address 2 low order bits remain unchanged Hardware semaphores VME Multiprocessor architectures often need to be able to share common resources between different VME cards The ability for a card to have hardware mechanisms for handling semaphores is therefore necessary The standard VME rev C Read Modify Write cycle is able to support semaphores Unfortunately there are a few drawbacks in using this RMW VME protocol VME rev RMV is a slow mechanism and its support can even slow down RMW standard cycles This is due to the signalling method on the VME indeed indivisible cycles can only be recognized at the end of the read phase RMW cycles are often not used nor generated by modern microprocessor architectures and hardware emulation of such cycles is not easy to design For these reasons the ALMA2e chip includes 4 shared 8 bit Semaphore registers so that the design of VME multiprocessor architectures can be greatly simplified 1 14 12 10 03 ALMA2e User Manual IBM VMEbus DeadLock avoidance Feature BRLOCb amp BGLOCb pins VME REQ LBR amp LBG bits In order to prevent deadlock situations ALMA2e is providing a mechanism allowing a PCI bus master device to obtain the VMEbus ownership before it starts its access to ALMA2e By doing so the device is guaranteed t
56. should be the same Semaphore write A write to address offsets 74 or 75 or 76 or 77 is executed when one of the following conditions are met The register high order bit is at 0 semaphore not busy A write to address offsets 48 or 49 or 4A or 4B is unconditionally executed The register high order bit is at 1 semaphore busy with the high order bit of the Data to be written at O Semaphore Read Semaphore registers read is allowed under no conditions however they can be read only at address offset 74 75 76 and 77 Semaphore Register usage example To get Semaphore ownership Loop on writing Semaphore registers a 7 bits unique task identifier with high order bit set to 1 until reading back the same value 2 54 To release Semaphore ownership Write anything with the high order bit reset to zero 0x00 for example 12 10 03 ALMA2e User Manual IBM VME SLVA VME Slave Channel A Address Register Address from PCI interface Configuration space 0x78 IO space BA1 SPACE 0x78 Address from VME interface A16 space VME SLVA 0x78 A24 space CSR BAR USER CSR 0x78 Width 16 Reset Value 0x0000 Access type Read Write 15 14 13 12 111101 91876543210 12 10 03 Description VME SLVA ADD 7 0 VME Slave Channel A Base address State on external pins VME BASE ADD 7 6 GAP GAB 4 0 is sampled amp loaded in this reg
57. space accesses and the 8MB granularity does not apply anymore The second provides address modifiers value of the VME cycle to generate All others informations are hard coded as follows no address translation PCI address is forwarded as is onto the VMEbus Little Endian Big Endian conversion mode set to the Address Coherency mode read prefetching and write posting set to disabled 12 10 03 Version 0 3 Overview 1 17 ALMA2e User Manual 1 10 Timings 1 10 1 Clock Timing Table 2 Clock timing Parameter Min Typical Max Units VME CLK input frequency 64 MHz VME_CLK duty cycle 40 60 P_CLK 25 66 Mhz P_CLK duty cycle 40 60 1 10 2 PCI IO Specifications Following timing are given for ALMA2e as input or output on a PCI bus at 66 MHz loaded by 10 pF Worst Case conditions Best Case conditions Table 3 PCI timing 105 degrees junction temperature 40 degrees junction temperature and voltage 596 and voltage 5 PCI Signal Input Output Setup min Hold min Min Max P ADL 31 0 3 00 ns Ons 2ns 6 ns P ADH 31 0 3 00 ns Ons 2ns 6 ns P_CBELb 3 0 3 08 ns Ons 2ns 6 ns _ 0 3 00 ns 0 09 ns 2 5 6 ns P FRAMEb 3 34 ns 0 06 ns 2ns 6ns P REQ64b 3 00 ns Ons 2ns 6ns P_IRDYb 3 37 ns 0 12 ns 2ns 6ns P_DEVSELb 3 19 ns 0 19 ns 2ns 6ns P ACK64b 3 21 ns Ons 2ns 6ns P_TRDYb 3 13 ns 0 08 ns 2ns 6ns P_STOPb 3 10 ns 0 22 ns 2
58. status register DMA completion can be signalled via an interrupt to the PCI bus The DMA engine supports all of the 2eSST operations A64 A32 A64 broadcast and A32 broadcast transaction ALMA2e allows five different speed for 2eSST transfer Data reception can be done at the theoretical maximum speed of 320 Mb sec Table 1 DMA performance Transaction Type Performance MB sec DMA PCI to VME Single 8 DMA PCI to VME BLT D32 34 DMA PCI to VME MBLT D64 70 DMA PCI to VME 2eSST mode 240 DMA VME to PCI Single 7 DMA VME to PCI BLT D32 22 DMA VME to PCI MBLT D64 50 DMA VME to PCI 2eSST mode 230 1 7 Interrupt management The ALMA2e interrupt controller can handle different interrupt sources 7 VME interrupts IRQ7 IRQ1 8 addressed interrupts occur when a specific 8 bit register is addressed in write mode from the PCI or the VME ACFAIL and SYSFAIL on VMEbus Internal Exceptions End of DMA error acknowledges on PCI bus or VMEbus VMEbus arbitration time out All these interrupts can be masked and can drive either the PCI bus interrupt pin P_INTAb or 3 additional programmable interrupt pins P_INT1b P INT2b or P INT3b ALMA2e can also generate VME Interrupts IRQ7 IRQ1 when a specific 8 bit register is addressed in write mode from the VMEbus or the PCI bus The release mechanism of this interrupter is ROAK Release on Acknowledge An external interrupt input pin PCI AVITb allows a
59. that a valid data is present on P AD 31 0 During a read operation it indicates the master is prepared to accept data P TRDYb s t s Pull Up Target Ready indicates the target agent s selected device s ability to complete the current data phase of the transaction During a read operation TRDYb indicates that valid data is present on P AD 81 0 During a write operation it indicates the target is prepared to accept data 3 118 12 10 03 ALMA2e User Manual Signal name I O Out External Description put Pull up Type Pull down P STOPb s t s Pull Up Stop signal indicates the current target is requesting the mas ter to stop the current transaction P_PERRb s t s Pull Up Parity error is used by ALMA2e for the reporting of data parity errors during write transactions as a target or during read transactions as a master P_SERRb Pull Up System error is used by ALMA2e for the reporting of address parity errors during read write transactions as a target P RSTb PCI this signal is used to identify if ALMA2e is nected to a PCI32 or a PCI64 bus P REQb 1 5 Bus Request ALMA2e bus request to an external PCI arbi ter P GNTb Us Bus Grant is 2 bus grant from an external PCI bus arbiter P INTAb o d Pull Up Interrupt A is used to request an interrupt 3 3 General purpose signals Si
60. to the 12 bits of this register to validate the access on this channel see also VME SLV0 7 ADDMSK SLVO0 7 LEBE 1 0 Data byte ordering conversion mode performed on a VME access to PCI 13 12 00 mode No Conversion 01 mode Address Coherency 10 mode Data Coherency 11 mode Bytes Translation with No Swapping 14 VME SLV0 7 WPOST 1 Enables Write posting on this channel 15 VME SLV0 7 RAHEAD 1 Enables Read prefetching on this channel SLV0 7 ADDMSK 1 1 0 27 16 0 Address bits decoding is masked on that bit position 1 Address bits decoding is enabled on that bit position see SLVO0 7 ADD 30 28 VME SLV0 7 BUSCON 2 0 PCI Bus Command 3 1 of the PCI cycle generated by ALMA2e 31 VME SLV0 7 ENABLE Slave channel 0 7 enable bit 1 disable bit 0 VME SLVO offset 0x84 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12111109 8171615 1 Bit s Description 7 0 VME_SLV0 7_AM 7 0 Valid if bit 1 VME Slave Channel 0 7 Address Modifier decoding bits 3 8 encoding of the 2 code 15 8 VME_SLV0 7_AM 15 8 Valid if bit 1 VME Slave Channel 0 7 Address Modifier decoding bits 3 8 encoding of the 5 code 31 16 SLVO0 7 OFFSET 15 0 12 10 03 Address Translation to apply on bits 31 16 of the VME address for PCI address generation Version 0 3 ALMA2e REGISTERS 2 59 ALMA2e User Manual Use of Offset for the generation of the PCI address from
61. true asserted when they are at logic low 0 Active high signals are labelled with no suffix they are defined as true asserted when they are at logic high 1 Logic low on a signal corresponds to the low voltage logic high to the high voltage Acronyms and Abbreviations Msb Most significant bit s BGA Ball Grid Array 2eSST two edge Source Synchroneous Transfer VMEbus VersaModule Eurocard bus SBC Single Board computer BLT Block Transfers MBLT Multiplexed Block Transfers 2 12 10 03 ALMA2e User Manual IBM Table of contents Chapter 1 Overview ucc ERN FEES 5 1 1 ALMA2e GENERAL DESCRIPTION 5 1 2 Operating 5 1 3 Y ecu ee etn dt ee bad eure Ea eed 6 1 4 VMEbus signals external buffering example 8 1 5 FUNCTIONAL 1 1 9 1 5 1 VMEbus Interface etes mast rra ee RUE Osea ds 9 1 5 2 POI bus interface cov se ca ERE LEES 11 1 6 ates parks eeu EPHESCILRE EI s 13 1 7 Interrupt Management iudei teet Lite xr te E bated Pit 13 1 8 Special Features ue mecs aet vaa ace de
62. 01 10 11 00 00 00 00 01 12 10 03 PCI bus data ENDIAN CONVERSION VMEbus data ae 31 24 23 16 15 8 7 0 D31 24 023 16 015 8 07 0 Byte Enables 3 0 t complemented MODE No Conversion 2 1111 2 BYTE1 BYTEO 2 BYTE1 BYTEO 0 1 1 1 0 BYTES BYTE2 BYTE1 2 1 0 0111 BYTE2 1 BYTEO BYTE2 BYTE1 BYTEO 1 0 1 1 0 BYTE1 2 BYTE1 0 1 1 0 0 BYTES BYTE2 BYTES BYTE2 0 0 0 1 1 BYTE1 BYTEO BYTE1 BYTEO 0 1000 0 01 0 0 2 2 1 0010 1 1 0 0 0 0 1 BYTEO BYTEO 1 1 0 1 1 BYTE3 BYTE BYTEO BvreE3 BYTEO 1101 2 2 0 1 0 0 1 BYTEO 0 1 0 1 0 BYTES 1 1 0 0101 2 BYTEO BYTE2 BYTEO 1 MODE Address Coherency 031 24 D23 16 D15 8 07 0 31 24 23 16 15 8 7 0 11 1 1 BYTE2 BYTE1 BYTEO BYTEO BYTE1 BYTE2 0 0 1 1 1 BYTE2 BYTE1 BYTEO BYTEO BYTE1 BYTE2 0 1110 2 BYTE1 1 2 1 0110 2 BYTE1 BYTE1 BYTE2 0 0 0 1 1 BYTE1 BYTEO BYTEO
63. 03 Version 0 3 ALMA2e REGISTERS 2 97 ALMA2e User Manual IBM CSR USER FUNCO A64 user function 0 upper bits Address register VME slave channel 9 upper bits Address Address from PCI interface Config space not seen space PCIH BA1 SPACE 0 184 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x184 Width 32 Reset Value 0x00000000 Access type Read Write CSR USER FUNCO A64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description USER FUNCO 64 VME base address Upper bits for 64 VME access The following CSR user function Upper Bits Address registers have the same bit definition They are at addresses USER FUNC1 A684 at address 0x18C USER FUNC2 A64 at address 0x194 CSR USER A64 at address 0x19C USER FUNCA A684 at address 0x1A4 USER 5 A64 at address 0x1AC USER FUNCS6 A684 at address 0x1B4 USER FUNC7 A684 at address 0x1BC 2 98 12 10 03 ALMA2e User Manual IBM CSR USER XRATE Transfer Rate register Address from PCI interface Config space not seen space BA1 SPACE 0 1 0 Address from VME interface A16 space not seen A24 space BAR USER 0x1C0 Width 32
64. 1 0 Three state 48 mA OEb IT m ADIR V A 81 1 p Three state 48 mA A 31 1 V LWORDb LWORD OEb 4 V_AM 5 0 AMDIR Three state 48 5 0 V IACKb Vos OEb x4 emit DSDIR Three state 64 mA psi o V Qo YES gt lt Vcc GND x 1 Three state 64 mA V ASb AS GND OE Vcc X V BCLRb SYSCONDIR Three state 64 mA BCLR V SYSCLK SYSCLK no R pull up GND __ is required x 1 Vcc DTACKDIR MD Three state 64 mA V DTACKb DTACK RETRY RETRYo x1 V BR3 00 V BBSYo V SYSRESETo V IRQ7 10 Open Collector 48 mA ACFAIL T BR3 0 V SYSFAILo V BERRo SYSRESET V RETRYib V ACFAILib ZA BBSY V BR3 0ib V BBSYib IRQ7 1 V SYSRESETib V_IRQ7 1ib OE A OE xm BERR V SYSFAILib V BERRib Figure 2 VME buffering of ALMA2e signals 1 8 12 10 03 ALMA2e User Manual IBM 1 5 FUNCTIONAL DESCRIPTION The ALMA2e VME PCI bridge is an highly flexible component that supports Master and Slave bus operations on both the PCI bus and VMEbus ports 1 5 1 VMEbus interface VME Master interface The ALMA2e VME master module provides D32 D16 D8 and UAT under A32 A24 and A16 addressing modes plus D64 BLT and D32BLT under A64 A32 and A24 addressing modes Any Address Modifier AM is supported The VME block mode D64 or D32 can be automatically started from a PCI burst The use of internal FIFOs allows maximum sp
65. 1 10 9 8 7 6 5 41 931 21 1 Bit s Description PCI INTACK SPECIAL Virtual register When this register is read from the VME bus ALMA2e initiates a PCI Interrupt Acknowledge cycle When this register is written from the VME bus ALMA2e initiates a PCI Special Cycle Note A read from the PCI to this register returns 0 a write from the PCI to this register has no effect 31 0 12 10 03 Version 0 3 ALMA2e REGISTERS 2 39 ALMA2e User Manual IBM PCI ARS PCI Slave Address Range Size register Address from PCI interface Config space 0x58 space PCIH BA1 SPACE 0x58 Address from VME interface A16 space VME SLVA 0x58 A24 space CSR BAR USER 0x58 Width 16 Reset Value 0x4924 Access type Read Write PCI ARS 15 14 131121111109 8 7 65 413121110 Bit s Description PCI ARS BA6 PCI Base Address 6 size 000 16 MB 100 256 MB 2 0 001 32MB 101 512 010 64 110 1 011 128 111 2 GB PCI ARS BA5 PCI Base Address 5 size 000 16 MB 100 256 MB 5 3 001 32 101 512 010 64 110 1 011 128 111 2 GB PCI ARS 4 PCI Base Address 4 size 000 16 MB 100 256 MB 8 6 001 32MB 101 512 010 64 110 1 011 128 111 2 GB PCI ARS PCI Base Address 3 size 000 16 MB 100 256 MB 11 9 001 32MB 101 512 010 64 110
66. 19 18 17 16 15 14113 121111019 7 6 5 413211 Bit s Description DMA read VME control 0 setto 0 ALMA2e is Unable to write in VME FIFO while the PCI reads the VME FIFO for DMA VME to PCI setto 1 ALMA2eis Able to write in VME FIFO while the PCI reads the VME FIFO for DMA VME to PCI 7 1 Reserved This bits are read write and have no functions Burst size for DMA from VME to PCI 0x00 32 Bytes 0x01 64 Bytes 0x02 96 Bytes 14 8 0x04 256 Bytes 0x08 512 Bytes 0x10 1024 Bytes 0x20 2078 Bytes others 32 Bytes 8 word of 32 bits 15 Reserved This bit is reserved and return zero when read High Level of data in FIFO needed to start the PCI write transaction DRV_CTL 0 is set to 1 0 0 48 bytes 0 8 176 bytes 0 1 64 bytes 0 9 192 bytes 0 2 80 bytes OxA 208 bytes 0x3 96 bytes OxB 224 bytes 23 16 0 4 112 bytes OxC 240 bytes 0 5 128 bytes OxD 256 bytes 0 6 144 bytes OxE 272 bytes 0 7 160 bytes OxF 288 bytes Note 1 if DRV_CTL 0 is set to 0 this register as no effect Note 2 The High Level must be greater than the Low Level VME Low level of Data in FIFO under which the PCI write transaction is stopped CTL 0 is set to 1 0 0 less than 16 bytes left in VME FIFO 0 1 less than 32 bytes left in VME FIFO 28 24 0 2 less than 48 bytes left VME FIFO Ox3 less than 64 bytes left
67. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 121 11 10 9 8 7 6 51 141 31 21 1 Bit s Description 0 Reserved This bits is Read Write and has no functions PCI Single read access control setto 0 Even for Single Read transfer ALMA2e reads more than one data on the VME bus 1 setto 1 when ALMA2e detects a PCI Single Read access only one cycle Read is done on the VME bus Warning In MBLT mode this may results in non conform operation 2 7 Reserved This bits are read write and have no functions PCI Low level Value if PCR CTL 0 is set to 1 0x0 PCI FIFO empty 0 1 less than 16 Bytes left in PCI FIFO 14 8 0 2 less than 32 Bytes left in PCI FIFO Ox3 less than 48 Bytes left in PCI FIFO Oxn lessthan 16 x n Bytes left in PCI FIFO OxF less than 256 Bytes left in PCI FIFO 31 15 Reserved These bits are Read Write and have no functions Note If register CTL 0 is set to 0 register PCR CTL 31 0 must be left to 0 2 86 12 10 03 ALMA2e User Manual IBM DRV CTL DMA Read VME Control register Address from PCI interface Config space not seen IO space PCIH BA1 SPACE 0x114 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x114 Width 32 Reset Value 0x00000000 Access type Read Write DRV CTL 31 30 29 28 27 26 25 24 23 22 21 20
68. 3 P ADL 2 004 ADL 4 005 PERRb 006 TMS 007 V IACKOUTb 008 V IRQo 1 909 INTib 010 V SYSRESETib Utt SYSCONT 012 V BGOUTb 3 U13 V IRQo 5 Ui4 V A 3 015 V IRQo 3 016 V A 11 017 V A 6 U18 V A 15 019 V A 16 01 P ADL 8 V02 GND V03 P ADL 5 vo4 VCC V05 GND 06 GND 07 vos VDD V09 INT3b V10 GND Vii BGINb 0 V12 VCC V13 V BGOUTb 2 Vi4 GND V15 V A 5 vie VDD V17 V A 9 V18 GND V19 V A 13 WO P ADL 7 W02 P ADL 6 wo3 VCC Wo4 PAR 05 SERRb W06 BRLOCKb W07 BGLOCKb 08 V IRQo 2 WO09 INT2b W10 TEST W11 V BGOUTb 1 W12 SYSCONDIR 13 RETRYo W14 RETRYib W15 V A 1 W16 V A 4 W17 V A 7 Wi8 V A 10 W19 V A 14 all these pads are internally connected to the GND plane e VDD all these pads are internally connected to the 2 5V Power supply e VCC all these pads are internally connected to the 3 3 V Power supply 4 126 12 10 03 ALMA2e User Manual Chapter 5 INITIALIZATION amp RESET 5 1 Overview ALMA2e reset logic handles five reset sources as listed below 1 Power on reset 2 VME system reset 3 Local board reset when input POWER ON RESETb is asserted low when input V SYSRESETib is asserted low when input RESETINb is asserted low this pin could by example be connected to the card hard reset Reset button or to the PCI bus reset signal RST when register UTIL_RST 9 8 at address 0x65 is written from ei
69. 8 27 26 25 24 23 22 21 20 Bit s Description 0 IO Space is used for PCI BAR 1 Read only register set to 1 1 Reserved Read only register set to 0 2 7 These bits are always 0 since the minimum size of PCI BAR 1 is 256 bytes 31 8 These bits determine where in PCI IO address space this region is located Note PCI BAR 1 of ALMA2e is always 1 Mbytes length even if the size coded in this register indicate 256 bytes 12 10 03 Version 0 3 ALMA2e REGISTERS 2 31 ALMA2e User Manual PCIH BA2 SPACE PCI Base Address 2 register Address from PCI interface Config space 0x14 space not seen access ends with Master Abort termination Address from VME interface A16 space VME SLVA 0x14 A24 space CSR BAR USER 0x14 Width 32 Reset Value 0x00000000 Access type Read Write PCIH BA2 SPACE 31 30 29 28 27 26 25124 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit s Description PCIH BA2 SPACE 0 MEMORY Space 1 IO Space 0 If PCI BASPACE EN 0 BA2 SPACE 0 If PCI BASPACE EN 1 PCIH BA2 SPACE PCI BASPACE BA2 See register PCI BASPACE at address 0 5 23 1 Reserved This bits are reserved and return zeros when read PCIH BA2 OFFSET These
70. A24 space BAR USER CSR 0x06 Width 16 Reset Value 0x0200 Access type Read Only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 Bit s Description 4 0 Reserved Return zeros when read 66 MHz Capability 5 Read only register this bit represents the value programmed in bit 9 of register 0 ALMA2e is not able to run PCI bus at 66 MHz 1 ALMA2e is able to run PCI bus at 66 MHz 6 Reserved This bits are reserved and return zeros when read 7 Fast back to back Capability Read only bit set to 0 Data Parity Error Detected 8 This bit is set when ALMA2e detects the following conditions ALMA2e Master of the PCI transaction and P_PERRb signal active 20 DEVSEL Timing 01 10 9 This bits are Read only ALMA2e always returns 01b when read ALMA2e always decodes as a MEDIUM device Signaled Target Abort 11 Read only bit Reset when write to 1 This bit is set when ALMA2e as a slave generates Target Abort Received Target Abort 12 Read only bit Reset when write to 1 This bit is set when ALMA2e as a master generates a transaction terminated with Target Abort Received Master Abort 13 Read only bit Reset when write to 1 This bit is set when ALMA2e as a master generates a transaction except for Special Cycle termi nated with Master Abort Signaled System Error 14 Read only bit Reset when write to 1 This bit is set when ALMA2e as a Slave asserts SERR Detected Parity Error This bit is set by
71. ALMA2e User Manual IBM ALMA2e PCI VME 2eSST Bridge User Manual Preliminary Version 0 3 Dec 10 2003 4 ALMA2e User Manual IBM About This Book The objective of this user s manual is to describe the functionality of the ALMA2e PCI VME Bridge for use by system designers and software developers Any published errata or updates to this document as well as Application Notes may be found at web site http www chips ibm com Audience This manual is intended for system software and hardware developers of VME products using the industry standard PCI Local Bus as the on board local bus is assumed that the reader has a knowledge of the IEEE std 1014 1987 and VME64 versions of the VMEbus Specification and of the PCI Local Bus Specification Revision 2 0 References Documentation The VMEbus SPECIFICATION conforms to ANSI IEEE STD 1014 1987 VITA 2 VME64 EXTENSIONS ANSI VITA 1 1 1997 Oct 7 1998 3 VME 2eSST VITA 1 5 200X Draft 2 3 Nov 6 2002 4 THE VMEbus SPECIFICATION conforms to ANSI IEEE STD 1014 1987 VITA 5 THE VMEbus HANDBOOK expanded third edition Wade D Paterson VITA 6 PCI LOCAL BUS SPECIFICATION Revision 2 2 December 18 1998 PCI SIG 7 PCI SYSTEM DESIGN GUIDE Revision 1 0 8 September 1993 PCI SIG Conventions PCI Bus Specification in the text refers to the PCI Local Bus Specification Revision 2 0 Active low signals are labelled with a b suffix they are defined as
72. ALMA2e when one of these conditions occurs 15 ALMA2e asserts P SERRb signal ALMA2e asserts P_PERRb signal P SERRb or P PERRb signal asserted when bit 6 of register CMD 6 1 2 28 12 10 03 ALMA2e User Manual IBM PCIH REVID PCI Revision ID register Address from PCI interface Config space 0x08 space not seen access ends with Master Abort termination Address from VME interface A16 space VME SLVA 0x08 A24 space CSR BAR USER 0x08 Width 8 Reset Value 0x30 Access type Read Only PCIH REVID 76543210 Bit s Description ALMA2e Revision ID Read only register set to 0x30 PCIH CLSCD PCI Class Code register Address from PCI interface Config space 0x09 space not seen access ends with Master Abort termination Address from VME interface A16 space VME SLVA 0x09 A24 space CSR BAR USER CSR 0x09 Width 24 Reset Value 0x008006 Access type Read Only PCIH CC BC PCIH CC SC PCIH CC SPI vov 23 22 21 20 19 18 17 16 15 14 13 12111 1019 1817161543210 Bit s Description 7 0 PCIH CC SPI Register level programming interface Read only register set to 0 00 15 8 PCIH SC Sub Class Code register coded as Other Bridge Device Read only register set to 0x80 23 15 PCIH Base Class Code register coded
73. Access type Read Write DMA1 VME A64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description DMA1 A64 9190 Channel 1 VME Upper Address bits for A64 VME access DMA1 VME SLVSEL DMA Channel 1 VME Slave Select register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x134 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x134 Width 32 Reset Value 0x00000000 Access type Read Write DMA1 VME SLVSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description DMA1 SLVSEL SUM DMA Channel 1 VME Slave Select signals for DMA channel 1 VME 2eSST broadcast cycles 12 10 03 Version 0 3 ALMA2e REGISTERS 2 93 ALMA2e User Manual IBM VME64 TCH VME64x Trouble Shoot register This register is for debug purpose must be set to 0x00000000 Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x138 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x138 Width 32 Reset Value 0x00000000 Access type Read Write R
74. BGA Package 4 124 12 10 03 ALMA2e User Manual Pin Signal name Table 5 ALMA2e 360 pin Ceramic BGA pin list Pin Signal name Pin Signal name Pin Signal name Pin Signal name A01 02 BEHb 2 A03 DI2 04 P BEHb 1 A05 BEHb 0 A06 P ADH 06 A07 P ADH 09 A08 P ADH 04 09 VME A10 V D 27 11 D 23 12 BERRib A13 DTACKb A14 DTACKDIR A15 V SYSCLK 16 V BBSYo 17 BBSYib 18 19 DDIR 01 P_BEHb 3 Bo2 GND P_ADH 17 04 VDD BOS GND 06 GND 07 P_ADH 1 B08 VCC 09 RESETINb B10 GND B11 V D 24 Bi2 VDD B13 D 21 14 GND B15 4 B16 VCC B17 IRGib 7 18 B19 V DS1b C01 REQb 02 ADH 18 ADH 22 04 ADH 16 05 ADH 12 06 ADH 11 07 P ADH 8 08 P ADH 3 09 P ADH 0 C10 V D 28 Cii V D 17 C12 V D 19 C13 V D 14 C14 IRQib 3 C15 V IRQib 1 C16 V D 12 C17 V IRQib 5 C18 C19 V DSOb 001 IDSEL 2 VCC 003 ADH 19 D04 GND 005 VCC 006 007 Dos GND 009 P ADH 5 010 VDD 011 V D 22 012 GND 013 V IRQib 2 D14 VCC 015 V IRQib 6 016 GND 017 V 0 11 018 VDD 019 DSDIR E01 ACK64b E02 GNTb E03 GND E04 ADH 20 E05 P ADH 15 E06 ADH 7 E07 GND E08 PCI AVITb E09 E10 TDI Et DH E12 V D 18 E13 V D 16 E14 V
75. CK mechanism Each channel can be configured with selectable parameters An additional channel available under A16 or A24 CR CSR space is provided for ALMA2e internal registers access ALMA2e provides an A24 CR CSR space as define in the VME64x specification 12 10 03 Version 0 3 Overview 1 9 ALMA2e User Manual IBM VME bus requester ALMA2e drives the bus requests on the 4 levels BRO to BR3 optional FAIR policy and the release of the bus can be managed with ROR Release On Request RWD Release When Done ROC Release On Clear or RNE Release NEver policy VME System controller ALMA2e is VME bus system controller if the input pin VME SYSCONT INb is strapped to Ground ALMA2e supports the auto system controller mechanism as defined into the VME64 norm if this pin is connected to the BG3IN signal and if the backplane interface logic on board connects a 3 Kohm resistor between BG3IN and the ground ALMA2e includes a mechanism for VME64x AUTO SLOT ID operation The following modules are activated if ALMA2e is selected as the VME system controller VME arbiter with two arbitration capabilities PRI fixed priority RRS Round Robin depending on the user choice A fixed arbitration time out of 8ms is selectable between BGOUT transmission and BBSY reception DTB Timer A programmable timer 4 us to 256 us measures the elapsed time between the DS assertion and the DTACK or signal SYSCLOCK
76. Cs is a major issue and ALMA2e addressing flexibility allows the VME computer to use the same address mapping convention as the one defined by the chosen microprocessor architecture 1 9 4 VME to PCI access As a VME Slave ALMA2e decodes if its VME slave image address and address modifiers are the target of the VME access through use of 16 decoding channels whose address recognition range depth is programmable 1MB to 4GB Min Max depth These features accommodate well with the big parcelling out of the VME address map sometimes found in VME systems To permit the mixing of VME64 and 2eSST 8 out of 16 Channels can be programmed as 2eSST ALMA2e responds to the VME access under the following conditions VME address 12 Msb match the address field of at least one channel VME address modifiers match the address modifiers field of the channel that has been hit The channel that has been hit is enabled A prioritization is performed between channels when more than one is hit The PCI address is obtained through a translation of the VME address with a granularity of 64KB Thus the offset field of the selected channel is added to the 16 Msb of the VME address While the PCI bus command is obtained from the PCI bus command field of the selected channel These capabilities allows for high mapping flexibility of VME addresses into the 4GB PCI address MEMORY and spaces 12 10 03 Version 0 3 Overview 1 15 ALMA2e User Manual IBM VME addr
77. D 106 ADL 15 107 ADL 25 108 ADL 24 109 VDD 10 GND 11 VDD 12 V A 29 L13 V A 30 114 V BRib 3 115 V A 31 116 V A 21 117 V SYSFAlLib L18 A 26 L19 V WRITEb MO TRDYb Moz VCC P_ADL 19 04 GND 05 P ADL 28 VDD M07 ADL 20 08 GND M09 OEb M10 VDD M11 V BGOUTbO M12 GND M13 V A 23 M14 VCC M15 VME BASE M16 GND M17 V A 22 M18 VDD M19 P RSTb 1 CBELb 3 NO2 P ADL 21 NO3 P ADL 16 NO4 P ADL 23 05 GND 6 VCC NO7 ADL 12 NO8 ADL 0 09 10 RESETOUTb 1 AUTO SLOT ID 2 BGINb 3 N13 IRQo 6 14 V A 24 N15 BRo 3 N16 V A 20 N17 V A 17 N18 A 25 N19 TRSTb P01 P CBELb 2 Po2 GND GND 04 VCC PO5 P_ADL 17 PO6 GND P07 P ADL 1 Pog VCC PO9 GAb 4 P10 GND 11 V_IRQo 4 P12 VDD P13 V_SYSRESETo 14 GND P15 V_BRib 1 P16 VCC 17 V A 19 P18 GND P19 V A 18 01 P CBELb 1 R02 P ADL 13 ADL 14 04 VCC 05 ADL 11 06 V IACKb 07 V IACKINb RO8 GAb 0 09 P INTAb R10 V SYSFAILo R11 V R12 V BGINb 2 R13 IRQo 7 R14 SYSFAILINb R15 V BRo 0 R16 BRo 1 R17 BRib 2 R18 V BRib 0 R19 BRo 2 TO CBELb 0 T02 VDD TO3 P ADL 9 T04 GND TO5 ADL 3 TO6 VCC TO7 GAb 2 08 GND TO9 GAb 3 T10 VDD Ti V_BGINb 1 T12 GND T13 V A 2 T14 VCC T15 V_A 8 T16 GND 117 V A 12 T18 VCC T19 V BCLRb UO1 P ADL 10 002 VCC 00
78. ET Register USER DEFINED BIT CLEAR Register Address Decode Compare Register 7 107 Address Decode Compare Register 6 107 Address Decode Compare Register 5 107 Address Decode Compare Register 4 107 Address Decode Compare Register 3 107 Address Decode Compare Register 2 107 Address Decode Compare Register 1 107 Address Decode Compare Register 0 107 Registers Not implemented Returns always 0 on Read ALMA2e REGISTERS 2 105 ALMA2e User Manual IBM CR CSR BAR Base Address Register for CR registers Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x80000 Ox7FFFF Address from VME interface A16 space not seen A24 space CSR BAR Ox7FFFF Width 8 Reset Value 0x00000000 Access type Read Write CR CSR BAR 7161543210 Bit s Description CR CSR BAR Base Address for the 512KB space 2 106 12 10 03 ALMA2e User Manual Function 7 ADER Address Decode Compare 7 Register Address from PCI interface Address from VME interface Config space not seen IO space A16 space not seen A24 space 0x7FFD3 0x7FFD3 Width 32 Reset Value 0x00000000 Access type Read Write Function 7 ADER 31 30 29 28 27 26 25 24 231 221211 201 19118 17 16 15 14 13 12 11 10 1 Bit s Description 0 XAM 1 DFSR 7 2 5 0 or XAM 5 0 9 8 C
79. I BASPACE EN 0 PCI BASPACE BA2 0 Base Address 2 is mapped in MEMORY Space 1 Base Address 2 is mapped in Space Note PCI BAR 2 is fixed and mapped to MEMORY Space if PCI BASPACE EN 0 PCI BASPACE EN Programmable PCI Space Enable 0 mapping space for all PCI BAR is fixed 1 PCI BAR 2 3 4 5 6 mapping space are programmable PCI BA1 EN Enable access to ALMA2e registers through PCI BAR BA1 0 Only ALMA2e Configuration Space registers is accessible from the PCI Compatibility with previous ALMA 64 product 1 All spaces registers are accessible from the PCI Note BA1 space size is always equal to 1 MB Reserved Return zero when Read Version 0 3 ALMA2e REGISTERS 2 41 ALMA2e User Manual IBM PCI RAMINDEX Mapping Table Index Register Address from PCI interface Configuration space 0 5 space PCIH BA1 SPACE 0x5C Address from VME interface A16 space VME SLVA 0x5C A24 space BAR BEG USER CSR 0x5C Width 16 Reset Value 0x00000000 Access type Read Write PCI RAMINDEX 9876543210 Bit s 15 10 Description PCI RAMINDEX 9 0 1K entry Mapping Table address Reserved PCI RAMDFLT Mapping Table Default Register Address from PCI interface Configuration space 0 5 space PCIH BA1 SPACE 0 5 Address from VME interface A16 space VME SLVA 0x5F A24 space CR CSR BAR BEG USER
80. IBM DMA CHNO CTRL DMA Channel 0 Control register Address from PCI interface Configuration space OXCC space BA1 SPACE 0 Address from VME interface A16 space VME SLVA OxCC A24 space CR CSR BAR BEG_USER_CSR 0xCC Width 16 Reset Value 0x0000 Access type Read Write DMA CHNO CTRL 15 141 13 12 11 1019 8 7 6 5 41 8 21 11 0 Bit s Description DMA CHNO START 0 Setto 0 No DMA channel 0 running setto 1 channel 0 starts DMA CHNO MIXAGE 1 setto 0 channel 0 has to wait the end of DMA channel 1 before to start setto 1 Blocks of both channel 0 and 1 can be interleaved DMA CHNO VME2PCI DMA transfer direction on channel 0 2 setto 0 PCI read to VME write setto 1 VME read to PCI write DMA CHNO BUSCOM Three high order bits of the PCI bus command DMA CHNO NOINCR No Increment This mode works only with AM type Single or BLT 6 It does not work for MBLT or 2eSST 0 normal DMA setto 1 all VME cycles start at the same address 7 Reserved Must be left to 0 DMA CHNO AM VME Address Modifier for DMA channel 0 DMA CHNO LEBE Conversion type to perform on DMA channel 0 00 mode conversion 01 mode Address Coherency 10 mode Data Coherency 11 mode Bytes Translation with No Swapping 13 8 15 14 2 64 12 10 03 ALMA2e User Manual IBM DMA CHNO XAM DMA Channel 0 Extended Address Mo
81. Interface Control 1K entry 4 gt Mapping Table Registers 2 Channel VME Data PCI Data DMA FIFO FIFO Resets Controller up to 2KB up to 2KB lt lt Timers Clocks 6 55 VME Bus VME Bus VME VME Bus System Control Interrupt Data Transfer Controller Interface VE NES V V Utility Data Transfer Priority Interrupt Data Transfer Bus Bus X Arbitration Bus Bus A64 D64 VMEbus 2eSST Figure 1 ALMA2e block diagram High performance Bridge between PCI and VME e Asynchronous transfers between PCI and VME Deep decoupling Transmit and Receive FIFOs VME64 compliant up to 70 MBytes sec External VME buffers TTL ETL buffers supported Register set fully accessible from both the PCI bus and the VMEbus ports Two channel programmable DMA Controller 1 6 12 10 03 ALMA2e User Manual IBM VMEbus interface e VME64 and IEEE std 1014 1987 compliant e VMEbus System Controller Autoslot ID mechanism VMEbus Requestor Level 0 3 e VMEbus Interrupter and Interrupt handler IRQ1 7 e VMEbus master slave A32 A24 A16 D32 016 D8 UAT e VMEbus master slave A32 A24 D32BLT D64MBLT e VMEbus master slave A64 D32 D32BLT DeAMBLT VMEbus master slave 2eSST A64 A32 VMEbus master slave 2eSST Broadcast A64 A32 Programmable VME slave image base address and size 16 VME slave channels a
82. Interrupt Status Register corresponding bit would have no effect EDGE other interrupt sources are detected active on the signal edge and would be memorized by ALMA2e only if not masked For those Edge detected interrupt source the generated PCI interrupt stays active until it is cleared by writing a O into the corresponding bit in the Interrupt Status Register writing a 1 to the Interrupt Status Register corresponding bit would have no effect Following are the ALMA2e Exceptions Interrupts sources Edge detected ALMA2e VMEbus arbiter time out bit 0 VME arb timeoutfail End of DMA operation on bits 7 6 seq finishO 1 channel 0 1 see DMA Operation VME amp PCI transfer errors on bit 8 see Error Handling ALMA2e VMEbus Locking bits 10 9 req Ibg and vme req wsr on see chapter on Preventing of deadlocks using the VMEbus locking feature under pin control and Preventing of deadlocks using VMEbus locking feature software control Interrupt Status After masking status of interrupt sources can be obtained by a read to the Interrupt Status Register only those sources active on edge are latched IT INT STATUS S1 0 at address OxE8 bit 0 gt interrupt of rank n is inactive or invalidated bit n 1 gt interrupt of rank is valid Interrupt Masking Valid interrupt sources are translated or not into a PCI interrupt depending upon the PCI Interrupt Mask Register
83. LMA2e 00 No conversion mode Bytes are passed as is from one bus to another Address is not affected 01 Address Coherency mode Data bytes are swapped VME address is not affected A01 bit and LWORD signal are kept as is 10 Data Coherency mode Data bytes ordering is not changed on writes PCI MSB is aligned on VME MSB and vice versa on reads The VME address obtained after translation is modified A01 bit and LWORD such a way it is consistent with the byte address in the Big Endian convention PCI address 2 are XORed with binary 11 11 Byte translation with no swapping mode Bytes are translated no swapping Done only when data size is 4 bytes 9 1 VME data Big Endian conversion to Little Endian These Endian conversions are done on the VME data upon VME writes to the PCI bus or to ALMA2e registers or upon PCI reads from the VMEbus 12 10 03 Version 0 3 ENDIAN CONVERSIONS 9 151 ALMA2e User Manual Table B 1 VME data Big to Little Endian conversions VME signals DS1 0 0 oem 0 9 152 A01 OO 0 O0O 0 000 se OOF 0 000 se ooo 09 0 LWORD et oe oe OC et et st OO OOOO
84. ME SLVA Ox1F1 A24 space CSR BAR USER CSR Ox1F1 Width 8 Reset Value 0x00 Access type Read Write CSR USER DEF SUBUNIT NB 76543210 Bit s Description SUBUNIT NB Sub Unit Number to be transmitted in the 2eSST Protocol 12 10 03 Version 0 3 ALMA2e REGISTERS 2 103 ALMA2e User Manual IBM CSR USER DEF RST SRC Reset Source register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0 1 2 Address from VME interface A16 space not seen A24 space BAR USER 0x1F2 Width 8 Reset Value 0x00 Access type Read Write CSR USER DEF RST SRC 76543210 Bit s Description A Write to the bit i clears the bit i 0 PWON Reset source is Power On Reset 1 SYSRESET Reset source is SYSRESETb signal 2 RESETIN Reset source is RESETINb signal 3 ADD_RST Reset source is an Addressed Reset 4 WD Reset source is watchdog 7 5 Reserved CSR USER DEF REGO 1 2 General purpose register used for PCI VME communication Address from PCI interface Config space not seen space BA1 SPACE 0 1 4 Address from VME interface A16 space not seen A24 space BAR USER 0x1F4 Width 32 Reset Value 0x00 Access type Read Write CSR USER DEF REGO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13121110 9 8 7
85. ME Slave Channel 1 Control Register VME Slave Channel 2 Control Register VME Slave Channel 3 Control Register VME Slave Channel 4 Control Register VME Slave Channel 5 Control Register VME Slave Channel 6 Control Register VME Slave Channel 7 Control Register ALMA2e REGISTERS Page 54 50 51 52 53 54 55 56 57 58 59 59 59 59 59 59 59 59 Notes 2 49 ALMA2e User Manual VME REQ VME Request Control Register Address from PCI interface Address from VME interface Configuration space 0x70 space PCIH BA1 SPACE 0x70 A16 space VME SLVA 0x70 A24 space CSR BAR USER 0x70 Width 8 Reset Value 0x00 Access type Read Write 716 3121110 Bit s Description 0 1 VME REQ LEVEL 1 0 Reset by POWER ON RESET Request level on the VME bus done by ALMA2e BR3 0 VME REQ FAIRMODE 2 0 No Fair mode 1 Fair mode ALMA2e Doesn t assert a VME request if another request is already pending on the same level VME REQ FAIRTIMEOUT 3 0 No Fair mode Time out 1 Fair mode Time out when the 20 micro seconds time out expires ALMA2e is no longer in fair mode VME REQ 1 0 VME bus release mode 4 5 00 ROR Release on Request 01 RWD Release When Done 10 ROC Release On Clear 11 RNE Release Never 6 VME REQ LBR Software VME bus request same function as pin BRLOCb External VMEbus Requesting feature VME REQ LBG 7 Software VME bus grant same funct
86. ME interface A16 space VME SLVA 0x02 A24 space BAR USER 0x02 Width 16 Reset Value 0x0035 Access type Read Only PCIH DID 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description Device Identification Number Value 0x0035 index 0x02 0x35 index 0x03 0x00 2 26 12 10 03 ALMA2e User Manual IBM PCIH CMD PCI Command register Address from PCI interface Config space 0x04 space not seen access ends with Master Abort termination Address from VME interface A16 space VME SLVA 0x04 A24 space CSR BAR USER 0x04 Width 16 Reset Value 0x0000 Access type Read Write Recommended value 0x0007 15 141 13 12 11 10 19 8 7 6 5 41 8 21 11 0 Bit s Description Enable PCI Slave IO space 0 setto 0 ALMA2e PCI IO access are Disable setto 1 ALMA2e PCI IO access are Enable Enable PCI Slave MEM space 1 setto 0 ALMA2e PCI MEM access are Disable setto1 ALMA2e PCI MEM access are Enable PCI Master Enable 2 setto 0 ALMA2e will never generate PCI access as a Master setto1 ALMA2e may generate PCI access as a Master Enable Special Cycle operation 3 Read only set to 0 ALMA2e never monitor Special Cycle as a slave Although this bit is set to 0 ALMA2e is able to generate PCI Special Cycles Enable Memory Write amp Invalidate operation 4 Read on
87. Modifier register Address from PCI interface Configuration space OxDE space PCIH BA1 SPACE OxDE Address from VME interface A16 space VME SLVA OxDE A24 space CR CSR BAR USER CSR OxDE Width 8 Reset Value 0x00 Access type Read Write 7 6 5 14 3 21110 New register in ALMA2e for 2eSST protocol Was reserved in previous ALMA version Bit s Description DMA CHN1 XAM VME 2eSST extended Address Modifier for DMA channel 1 0x11 A32 D64 2eSST 0x12 A64 D64 2 55 0x21 A32 D64 Broadcast 2eSST 0x22 A64 D64 Broadcast 2eSST Note For A64 addressing XAM 0x12 or XAM 0x22 the 32 upper bits are specified in register DMA1 VME A64 at offset 0x130 For Broadcast transfer 0x21 0x22 the parameter Slave Select is specified in register DMA1 VME SLVSEL at offset 0x134 CHN1 RATE DMA Channel 1 Transfer Rate register Address from PCI interface Configuration space OxDF space PCIH BA1 SPACE OxDF Address from VME interface A16 space VME SLVA OxDF A24 space CR CSR BAR BEG_USER_CSR OxDF Width 8 Reset Value 0x00 Access type Read Write 7 6 5 4 3 21110 New register in ALMA2e 2eSST protocol Was reserved in previous ALMA version Bit s 2 70 Description DMA CHN1 RATE VME 2eSST Transfer Rate parameter for DMA channel 1 0x0 160 MB s rate 0 1 267 Mb s rate 0 2 320
88. Normal latency between data phases on master Writes 10 Low latency between data phases on master Writes 12 10 03 Version 0 3 ALMA2e REGISTERS 2 53 ALMA2e User Manual VME SEM VME Semaphore Register Address from PCI interface Address from VME interface Configuration space 0 48 amp 74 space BA1 SPACE 0 48 amp 74 A16 space VME SLVA 0x48 amp 74 A24 space 0x48 amp 74 Width 32 Reset Value 0x00000000 Access type Read Write VME SEM 0 3 31 30 29 28 27 126 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 211 Bit s Description 7 0 VME SEMQ 7 0 Reset By POWER ON RESET 15 8 VME SEM1 7 0 Reset By POWER ON RESET 23 16 SEM 2 7 0 31 24 VME SEM3 7 0 VME Semaphore Registers Four 8 bit Semaphore Registers are shared between PCI and VME mapped at addresses 48 and 74 These registers are conditionally written when address offsets 74 75 76 and 77 are accessed in write mode They are unconditionally written when address offsets 48 49 4A and 4B are accessed in write mode Data is defined into the 7 low order bits of the register while the high order bit is used as a control bit which enables the register to be written Multiple semaphore Bytes can be read and written simultaneously by using a 32 bit cycles to extend number of bits available in this case bit 7 of each Byte
89. R VME USED 63 0 Cumulative Time used VME bus CSR USER DEF ALMA USED CSR user function Address from PCI interface Config space not seen IO space BA1 SPACE 0 108 Address from VME interface A16 space not seen A24 space BAR USER 0x1D8 Width 64 Reset Value 0x00000000 Access type Read Write CSR USER ALMA USED 63 32 31 0 Bit s Description 63 0 CSR USER ALMA USED Cumulative Time used on VME bus by ALMA2e 2 100 12 10 03 ALMA2e User Manual USER DEF INT MSKOUTH 2 3 Interrupt Mask Register This register allows to Mask the interrupt source that can activate the INT1b output signal Address from PCI interface Address from VME interface Width Reset Value Access type Config space not seen space BA1 SPACE 0 1 A16 space not seen A24 space CSR BAR USER 0x1E0 32 0x00000000 Read Write CSR USER DEF INT MSKOUT1 31 30 29 28 27 26 25 24 23 221211201 19 18 17 16 15 14 13 12 11 10 9 8 7 6 51 41 31 21 110 Bit s Description 31 VME IRG7 Interrupt is masked if 21 30 VME IRQ6 29 VME IRQ5 28 VME IRQ4 27 VME IRQ3 26 VME IRQ2 25 VME IRQ1 24 Reserved 23 Addressed Interrup
90. Read Write PCI CFGADD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 2 1 Bit s Description 1 0 Reserved Returns zeros when read 7 2 PCI CFGADD REGNUM Register Number of the external device to configured 10 8 PCI CFGADD FNUM Function Number of the external device to configured PCI CFGADD DEVNUM Device Number of the external device to configured 0x00 PCI device 0 PCI ADD 11 is active 0 01 PCI device 1 PCI ADD 12 is active 0x02 PCI device 2 PCI ADD 13 is active 0x03 PCI device 3 PCI ADD 14 is active 0 04 PCI device 4 PCI ADD 15 is active 0x05 device 5 PCI ADD 16 is active 0x06 PCI device 6 PCI ADD 17 is active 0x07 PCI device 7 PCI ADD 18 is active 0x08 PCI device 8 PCI ADD 19 is active 15 11 0x09 PCI device 9 PCI ADD 20 is active Ox0A device 10 ADD 21 is active 0 0 PCI device 11 ADD 22 is active OxOC PCI device 12 PCI ADD 23 is active 0 00 PCI device 13 ADD 24 is active OxOE PCI device 14 ADD 25 is active OxOF PCI device 15 PCI ADD 26 is active 0x10 device 16 PCI ADD 27 is active 0x11 device 17 ADD 28 is active 0x12 PCI device 18 ADD 29 is active 0x13 PCI device 19 ADD 30 is active 0x14 PCI device 20 ADD S31 is active 23 16 PCI CFGADD BUSNUM PCI bus number of the external device to configured 30 24 Reserved Returns
91. SER DEF INT MSKOUT 1 0x1E0 OxFFFFFF7F USER DEF INT MSKOUTI 1 0x1E4 OXFFFFFFBF 12 10 03 Version 0 3 INTERRUPTS 6 141 ALMA2e User Manual IBM 6 4 Interrupt sources translated to an interrupt to PCI 6 4 4 VME interrupts When VME interrupt request IRQ7 1 is received by ALMA2e on pins V IRQib 7 1 it is translated by ALMA into a maskable interrupt to the PCI VME interrupts IRQ7 1 after masking are recorded respectively into bits IT INT STATUS S31 25 These interrupt sources are level sensitive Once the PCI interrupt handler device identified that the interrupt is sourced by VME IRQ7 1 it may ask ALMA2e to generate a VME Interrupt Acknowledge cycle VME IACK cycle via a read targeting one of the following virtual ALMA2e byte registers Each one of these registers indexed from 1 to 7 is associated with the interrupt level of same value as the index Note that any write access to these registers is normally acknowledged but will produce no action IT ACK1 7 0 F9 IT ACK2 7 0 FA IT ACK3 7 0 IT ACK4 7 0 IT ACK5 7 0 FD IT ACK6 7 0 FE IT ACK7 7 0 FF Any PCI read access of a Byte size to one of these registers will be forwarded by ALMA2e as a VME IACK 008 0 at the corresponding interrupt level The interrupt vector received by ALMA2e is then passed as a read data to the PCI the interrupt vector value is duplicated on the 4 PCI byte lanes Note No checking is performed by ALMA2e abou
92. SR ADEM 0 ADEM 0 B03 ADEM 0 BO2R ADEM 0 B02 ADEM 0 BO1R ADEM 0 01 ADEM 0 BOOR ADEM 0 00 Use Begin Address of User CSR space Read value of ADEM 0 byte 3 ADEM 0 byte 3 Read value of ADEM 0 byte 2 ADEM 0 byte 2 Read value of ADEM 0 byte 1 ADEM 0 byte 1 Read value of ADEM 0 byte 0 ADEM 0 byte 0 Page Notes 111 112 112 113 113 113 113 114 114 12 10 03 ALMA2e User Manual USER Offset Address for access of the Registers The 24 bits are split in 3 registers Address from PCI interface Address from VME interface Width Reset Value Access type BEG USER CSR Config space not seen IO space PCIH BA1 SPACE 80000 0 A16 space not seen A24 space CSR BAR 0xB3 24 0x00 Read Write 71615 413121 1 0 0xB3 716 5 4 31 2110 0 7 7 6 5 4 3 2 1 0 OxBB Bit s Description 7 0 BEG USER CSR 7 0 Bits 7 0 at address 0xB3 15 8 USER CSR 15 8 Bits 7 0 at address 0 7 23 16 USER 23 16 Bits 7 0 at address OxBB 12 10 03 Version 0 3 ALMA2e REGISTERS 2 111 ALMA2e User Manual IBM ADEM 0 ADEM byte 3 Address Decoder Mask Byte 3 Address from PCI interface Config space not seen space PCIH BA1 SPACE 80000 0x620 Address from VME interface A16 space not seen A24 space CSR BAR 0x620
93. SYb within 8 mS after an arbitrated bus grant by ALMA2e as VME system Controller All PCI Byte Enables lines are inactive no data to transfer when ALMA2e is the target of a PCI single data access Data beat size is not D32 or D64 when ALMA2e is the target of a VME BLT or MBLT access PCI error PCI cycle completes with a Target or a Master Abort when ALMA2e is the target of a VME write posted access PCI error PCI cycle completes with a Target or a Master Abort when ALMA2e is the target of a VME write non posted access PCI error PCI cycle completes with a Target or a Master Abort when ALMA2e is the target of a VME read access in Read Ahead mode PCI data are prefetched Data transfer timeout when ALMA2e is System Controller no VME slave is responding at time out defined by register VME TIM Watchdog timer not been cleared before time out after a reset generated by ALMA2e Watchdog function the Watchdog timer is UTIL_RST 31 16 register VMEbus Error when ALMA2e translates the interrupt from PCI AVITb pin assertion into VME cycle ALMA2e is the target of a PCI access for which the PCI Byte Enables pattern is specifying non adjacent valid bytes for example PCI reading writing only the byte3 and byte1 of the 4 byte data pattern byte2 and byteO being not transferred Data beat size is not equal to 32 bits when ALMA2e is the target of a PCI burst access VMEbus Error when ALMA2e is the target of a PCI write posted acces
94. T2 Acknowledgement cycles The AUTO SLOT ID function can be disabled by software with the following sequence Write in register IT IRQ GEN 9 OxF8 to desactivate interrupt IRQ2 Write in register CR CSR BAR to prevent the ALMA2e respond OxFE at the first IT2 Acknowledgement cycle Write in register SLV 0x7A VME Slave Control Register bit 6 to 1 to authorize access from VME with AM 0x2F Write in register UTIL VMECTL 9 0x68 for SYSFAIL desactivation 5 12 2 Normal AUTO SLOT operations The monarch wait until desactivation of the SYSFAIL If the interrupt IRQ2 is active the IT2 Acknowledgement cycle must be done If on the IT2 Acknowledgement the answer is not OxFE the protocol of AUTO SLOT is stopped If on the IT2 Acknowledgement the answer is OxFE the monarch can set the register CSR BAR address offset OX7FFFF an access with AM 0x2F and Base Address 00 Same operation is repeated until interrupt IRQ2 remains active At the end of the sequence the Slave Canal Register 0 2 is set for all the cards attached to the VME in the back plane Note ALMA2e as Monarch ALMA2e is not able to acknowledge its own interrupt IRQ2 ALMA2e is monarch only if it is also System controller In this case the software must first desactivate its interrupt by programming CR CSR in the first card and then Acknowledge the interrupt IRQ2s Only 2 sources of reset can activate the AUTO SLOT D signal
95. TE1 BYTE2 BYTES BYTEO BYTE1 BYTE2 BYTEO BYTE1 BYTE2 BYTE1 BYTE2 1 2 BYTE1 2 BYTE1 2 BYTEO BYTE1 BYTE1 2 2 BYTEO BYTEO BYTE1 BYTE1 BYTE2 BYTE2 BYTES BYTES PCI PCI Byte Enables 3 Qjddress complemented 1 0 ooo o 7 007 a oer O lt 5 042 oper ooe ons as ooorortoo a 00 0000 0 oooro n oot oor oor O oOororta oooroo0oe 0o gt 2 gt 2 a a a ooortosoo 0O02 00000 12 10 03 ALMA2e User Manual 9 2 PCI data Little Endian conversion to Big Endian These endian conversions are done on the PCI data upon PCI writes to the VMEbus or upon VME reads from the PCI bus Note that no conversion is required when ALMA2e registers are read from the PCI bus since ALMA2e register set is mapped in the bridge already using the Little Endian byte ordering convention Table B 2 PCI data Little to Big Endian conversions PCI address 1 0 00 00 01 01 00 10 00 01 10 11 00 00 00 00 01 00 00 01 01 00 10 00
96. VME 2eSST Transfer Rate parameter for DMA channel 0 0 0 160 MB s rate ere 0 1 267 Mb s rate 0x2 320 MB s rate 0x3 OxF Reserved 7 4 Reserved Return zero when Read 2 66 12 10 03 ALMA2e User Manual IBM DMA CHN1 ADDVME DMA Channel 1VME Address register Address from PCI interface Config space OxDO space PCIH BA1 SPACE OxDO Address from VME interface A16 space VME SLVA 0 00 A24 space CSR BAR USER 0xDO Width 32 Reset Value 0x00000000 Access type Read Write DMA CHN1 ADDVME 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description 1 ADDVME 31 0 VME starting address for DMA channel 1 Note At the end of each block size the VME adaress of the next block size is loaded in this register DMA CHN1 ADDPCI DMA Channel 1 PCI Address register Address from PCI interface Config space 0 04 space PCIH BA1 SPACE 0xD4 Address from VME interface A16 space VME SLVA 0xD4 A24 space CSR BAR USER 0xD4 Width 32 Reset Value 0x00000000 Access type Read Write DMA CHN1 ADDPCI 31 30 29 28 27 26 25 24 23 22 21 20 19118 17 16 15 14 13 12 11 109 7 615 413211
97. Y or I O 1 16 12 10 03 ALMA2e User Manual IBM nit 6 TE Por c Em Ew amp amp 1 to 8 bits can be selected PCI Base Address Registers 4 MSb from 1 MSb up to 8 MSb can be selected er PCI man CI com a d PCI address target hit index 9 0 MEMORY cycle 16 bits 21 10 cycle 1K entry PCI to Mapping Table Address bits VME VME AM Generated VME Address for translation Address Modifiers RA Read Ahead enable WP Write Posting enable LEBE Little Big Endian VAL PCI MEMORY access Valid for indexes 0 51 1 conversion mode PCI access Valid for indexes 512 1023 Thus ALMA2e selects itself as the target of the PCI access when both Base Address Registers and Mapping Table are hit The selected Mapping Table entry tells the ALMA2e PCI slave behavior on writes write posting enable disable and provides all the informations useful to cycle generation onto the VMEbus such as address translation address modifiers Little Endian Big Endian conversion mode and read prefetch enable disable The Mapping Table can be disabled through programming In that mode called transparent mode an ALMA2e register content and some hard coded informations substitutes themselves to the Mapping Table programming The register provides two informations The first indicates whether access can be accepted or rejected no distinction is made between MEMORY or I O
98. a receiver ALMA2e can accept all the possible rates SST160 SST267 SST320 However depending on particular system timing performance behavior it is possible not to accept transfers at SST320 rate by clearing bit 3 of VME2ZESST register a slave error would then be generated during address phase 3 if a rate of SST320 was detected by ALMA2e as a slave As a 2eSST data source ALMA2e generates one of the 3 possible rate codes SST160 SST267 SST320 according to its RATE register setting The actual timings of the 2eSST are based on the setting of register VME2ESST It is the user responsibility to program actual 2eSST timings compatible with the 2eSST rate code selected actual timings should correspond to a rate less than or equal to the rate code with set up and hold times greater than or equal to the 2eSST requirements During address phase 3 DSO0 reassertion if a broadcast 2eSST operation has been selected XAM 0x21 or 0x22 VME addresses A21 to A1 indicate the geographical address of the slaves to be targeted by the broadcast To select a slave with a geographical address i bit Ai should be set to 1 For each DMA channel the slaves participating in the broadcast operation are programmed in register DMA VME SLVSEL During the broadcast operation the master responds with to its own cycles and the participating slaves capture the transmitted data If a slave is not ready to accept the full broadcast
99. ace A16 space VME SLVA 0xC8 A24 space BAR BEG USER 0xC8 Width 24 Reset Value 0x000000 Access type Read Write DMA CHNO XFERSIZE 20 19 18 17 16 15 14 13 12111 101 9181716543210 Bit s 20 0 23 21 Description Total number of VME cycles minus 1 to be performed for a DMA channel 0 transfer Up to 4 Million of cycles can be programmed giving 512MB for D64 or 256 MB for D32 For 2eSST this number must be odd 1 3 5 Reserved return zero when read DMA CHNO BLOCSIZE DMA Channel 0 Block Size register Address from PCI interface Configuration space OxCB space PCIH BA1 SPACE OxCB Address from VME interface A16 space VME SLVA OxCB A24 space CR CSR BAR USER OxCB Width 8 Reset Value 0x00 Access type Read Write DMA CHNO BLOCSIZE 7 6 5 4 3121110 Bit s 12 10 03 Description DMA CHNO BLOCSIZE Total number of VME cycles minus 1 to be performed for each block of a DMA channel 0 transfer In one VME cycle 4 Bytes are transfered in D32 8 Bytes are transfered in D64 MBLT Each VME cycle is defined by a new DTACK active A block size is defined by a VME Tenure AS and the Maximum must comply with the VME Norm For 2eSST this number must be odd 1 3 5 Version 0 3 ALMA2e REGISTERS 2 63 ALMA2e User Manual
100. as Bridge Device Read only register set to 0x06 12 10 03 Version 0 3 ALMA2e REGISTERS 2 29 ALMA2e User Manual PCIH LT PCI Latency Timer register Address from PCI interface Address from VME interface Width Reset Value Access type PCIH LT 76543210 Bit s Description Read only register set to 0x00 PCIH HT PCI Header Type register Address from PCI interface Address from VME interface Width Reset Value Access type PCIH HT 76543210 Bit s Description ALMA2e Header Type Read only register set to 0x30 2 30 Config space 0x0D space not seen access ends with Master Abort termination A16 space VME SLVA 0x0D A24 space BAR USER 0 00 8 0x00 Read Only ALMA2e has no Latency Timer Config space 0 0 space not seen access ends with Master Abort termination A16 space VME SLVA 0 0 A24 space CSR BAR USER 0x0E 8 0x30 Read Only 12 10 03 ALMA2e User Manual PCIH BA1 SPACE PCI Base Address 1 register Address from PCI interface Address from VME interface Width Reset Value Access type Config space 0x10 space not seen access ends with Master Abort termination A16 space VME SLVA 0x10 A24 space CSR BAR USER CSR 0x10 32 OxFFFFFFO1 Read Write PCIH_BA1_SPACE 31 30 29 2
101. ated upon PCI AVITb pin assertion IT AVIT WRITEB 6 R W mode of the VME cycle generated upon PCI AVITb pin assertion 0 Write 1 Read IT AVIT IROSEL 0 cycle is generated when upon assertion of PCI AVITb pin The Address AM R W mode and Data of this cycle are supplied by the IT AVIT ADD IT AVIT AM 7 IT AVIT WRITEB and IT AVIT DATA registers The size of the VME transfer is a byte 1 a VME Interrupt IRQ7 IRQ1 is generated upon assertion of PCI AVITb pin Level of the interrupt is set equal to the rank of the set at 1 into IT AVIT DATA T7 1 register 2 76 12 10 03 ALMA2e User Manual IBM IT AVIT DATA AVIT VME cycle Data Register Address from PCI interface Config space not seen space PCIH BA1 SPACE OxF5 Address from VME interface A16 space not seen A24 space CSR BAR BEG USER OxF5 Width 8 Reset Value 0x00 Access type Read Write 716543210 Bit s Description AVIT DATA 7 0 Write data value of the VME cycle generated upon PCI AVITb pin assertion case of IT AVIT IRQSEL 1 7 0 Interrupt level of the VME 1 7 VME IRQ 1 generated upon PCI AVITb pin assertion case of IT_AVIT_IRQSEL 0 AVIT STA Interrupt Status Register Address from PCI interface Config space not seen space PCIH BA1 SPACE OxF6 Address from VME interface A16 space not seen A24 space CSR BAR BEG USER
102. ation of local reset RESETINb to the VME SYSRESET 0 2 1 yes 7 1 Reserved UTIL RST ADD 1 0 Generation of local reset and or a VME reset 00 De activation of RESETOUb independently of the time out 01 Activation of SYSRESET for 201 ms 10 Activation of RESETOUb for 201 ms maximum 11 Activation of SYSRESET and RESOUTb 15 10 Reserved UTIL VALUE 15 0 Watchdog Timer value ms UTIL WDG VALUE 15 0 multiplied by 4 Writing a value different of zero in this register restart the Timer Writing a zero inhibits the Watchdog function 31 16 12 10 03 Version 0 3 ALMA2e REGISTERS 2 45 ALMA2e User Manual UTIL VMECNTL VME System Control Register Address from PCI interface Address from VME interface Configuration space 0x68 space BA1 SPACE 0x68 A16 space VME SLVA 0x68 A24 space BAR USER 0x68 Width 32 Reset Value 0x00000000 Access type Read Write UTIL VMECNTL 31 30 29 28 27 26 25 24 231 22121 201 19118 17 16 15 14 13 12 11 10 211 Bit s Description UTIL SYSFAIL At the POWER ON RESET the is not activated if the PWSR signal is active 0 In all other cases of RESET the SYSFAIL is activated Read Gives state of signal SYSFAIL of the VME Bus 1 active Write 1 Signal SYSFAIL generated by ALMA2e is activated Write
103. blocks with those of the other Channel DMA CHNO MIXAGE 060 CC 0 gt Channel 0 is not allowed to interleave its blocks with those of Channel 1 Must wait until Channel 1 DMA is finished 1 gt Channel 0 is allowed to interleave its blocks with those of Channel 1 DMA_CHN1_MIXAGE 060 DC 0 gt Channel 1 is not allowed to interleave its blocks with those of Channel 0 Must wait until Channel 0 DMA is finished 1 gt Channel 1 is allowed to interleave its blocks with those of Channel 0 Some applications are requiring that on the VMEbus side all data to be transferred to the same VME fixed address i e all VME cycles must start at the same address initial value of DMA CHNO ADDVME or DMA_CHN1_ADDVME ALMA2e is providing a programmable bit allowing for such type of application DMA_CHNO_ NOINCR Db DMA 1 NOINCR 050 0 Normal is required on Channel 0 Channel 1 1 gt VME address is not augmented by 4 during DMA In the case of a PCI read VME write DMA only ALMA V64 features a mode called Turbo mode allowing each DMA block to be transferred via a single PCI burst whose size is equal to the DMA block byte count Turbo mode enabled instead of performing a suite of 8 data burst transactions Turbo mode disabled This brings some performance improvement but increases the ALMA2e bandwidth consumption Notably this mode prevents other bus masters to utilize the PCI bus when ALMA2e
104. configurations see Sampling hardware configurations gener ates RESETOUTb and starts 201ms timer write to register UTIL RST ADD 1 0 with 00 will makes ALMA2e to immediately de activates RESETOUTDb From that point that signal could be re asserted only after the watchdog timer has expired see chapter 5 6 Reset controlled by the Reset Watchdog on page 131 Upon 201ms timer expiration ALMA2e de activates RESETOUTb 3 Writing 11 to UTIL RST ADD 1 0 ALMA2e generates both V SYSRESETo even if it is not VMEbus System Controller and RESETOUTb for 201ms The two above sequences of actions are performed 4 Writing 00 to UTIL RST ADDT 1 0 ALMA2e de activates RESETOUTb if it were already active from a previous addressed reset operation otherwise no action is performed The current addressed reset operation being performed by ALMA can be known by a read to the UTIL RST ADD 1 0 register 5 130 12 10 03 ALMA2e User Manual IBM 5 5 Reset controlled by the V SYSRESETib input SYSRESET Sequence of actions is the following Upon assertion low of V SYSRESETib ALMA2e performs an Internal reset generates RESETOUTb and starts 201ms timer 201ms is the assumed required time to reset any board local devices Upon either 201ms timer expiration or V SYSRESETib de activation ALMA2e de activates RESETOUTDb and the internal reset and samples hardware configurations see chapter 5 7 Sampling
105. d or write access to a specific ALMA2e internal register Configuration cycles for primary and secondary buses can be initiated from the VME through access to two specific ALMA2e internal registers used as configuration address and configuration data registers according to mechanism 2 of the PCI specification ALMA2e can generate PCI burst up to 2KB without wait state PCI Slave interface ALMA2e PCI slave interface decodes cycles MEMORY cycles and Type 0 CONFIGURATION cycles Note that MEMORY READ MULTIPLE MEMORY READ LINE and MEMORY WRITE amp INVALIDATE are also accepted by ALMA2e but are treated as regular MEMORY READ or MEMORY WRITE accesses ALMA2e slave image base addresses and address spaces are encoded into 6 PCI Base Address Registers defined into its Configuration Header space Five Base Address registers BAR are available for decoding of PCI accesses to the VME and one Base Address register is reserved for decoding of PCI accesses to ALMA2e Configuration space registers PCI to VME address translation through 1K Mapping table In addition a Mapping table of 1K entries is used to enable disable PCI MEMORY space accesses up to 4GB as well as PCI I O space accesses up to 4GB with a granularity of 8MB For a given 8MB addresses block ALMA2e selects the associated Mapping Table entry in which are programed the VAL bit to enable disable the PCI access the WP bit to enable disable PCI Write Posting plu
106. data cycles in which the above total transfer size is broken down for DMA of Channel 0 and 1 loaded value must be equal to the desired number of VME data cycles minus one cycle since the zero value is counted DMA CHNO BLOCSIZE 7 0 0x00 CB DMA_CHN1_BLOCSIZE 7 0 0x00 DB The maximum amount of data which can be transferred per DMA block A DMA block is normally trans ferred on a single VMEbus tenure is of 256 VME 064 or 032 data cycles i e e 16 Kilobytes if DMA block is transferred using a VME MBLT 064 cycle or e 8 Kilobytes if DMA block is transferred using VME BLT 032 cycle In order to comply with VME norm relating to address boundaries crossing during MBLT 2KBytes address boundary BLT 256Bytes address boundary ALMA2e will automatically stop the current DMA block transfer at the boundary and will resume a new VMEbus tenure to transfer the remaining data of the DMA block It is however advisable for performance reasons to program the DMA block count accordingly to these address boundaries i e DMA_CHNx_BLOCSIZE 7 0 hex will give 63 1 VME data cycles the case where VME D32 cycles are used For each Channel the transfer direction is programed into bits 2 of the Channel Control Registers DMA CHNO VME2PCI 060 CC DMA CHN1 VME2PCI 050 DC 0 gt Data are read from PCI and written to the VME on Channel 0 Channel 1 1 gt Data are read from VME and written to the PCI on Channel 0 C
107. difier register Address from PCI interface Configuration space OxCE space PCIH BA1 SPACE OxCE Address from VME interface A16 space VME SLVA OxCE A24 space CSR BAR USER CSR OxCE Width 8 Reset Value 0x00 Access type Read Write DMA CHNO XAM 76543210 New register in ALMA2e for 2eSST protocol Was reserved previous ALMA version Bit s Description DMA CHNO XAM VME 2eSST extended Address Modifier for DMA channel 0 Ox11 A32 D64 2eSST 0x12 A64 D64 2eSST 0x21 A32 D64 Broadcast 2eSST 7 0 0x22 A64 D64 Broadcast 2eSST Note For A64 addressing 0x12 or 0x22 the 32 upper bits are specified in register DMAO VME A64 at offset 0x128 For Broadcast transfer XAM 0x21 or XAM 0x22 the parameter Slave Select is specified in register VME SLVSEL at offset 0x12C 12 10 03 Version 0 3 ALMA2e REGISTERS 2 65 ALMA2e User Manual DMA CHNO RATE DMA Channel 0 Transfer Rate register Address from PCI interface Address from VME interface Width Reset Value Access type DMA CHNO RATE 7 6 5 4 3 2 1 0 Configuration space OxCF space PCIH BA1 SPACE OxCF A16 space VME SLVA OxCF A24 space BAR USER OxCF 8 0x00 Read Write New register in ALMA2e for 2eSST protocol Was reserved in previous ALMA V64 version Bit s Description DMA CHNO RATE
108. e CSR BAR USER 0xCO Width 32 Reset Value 0x00000000 Access type Read Write DMA CHNO ADDVME 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 12111 10 9 8 7 6 51 141 31 21 1 Bit s Description DMA CHNO ADDVME 31 0 VME starting address for DMA channel 0 Note At the end of each block size the VME adaress of the next block size is loaded in this register DMA CHNO ADDPCI DMA Channel 0 PCI Address register Address from PCI interface Config space 0 4 space PCIH BA1 SPACE 0xC4 Address from VME interface A16 space VME SLVA 0xC4 A24 space CSR BAR USER 0xC4 Width 32 Reset Value 0x00000000 Access type Read Write DMA CHNO ADDPCI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121 11 10 9 8 7 6 51 41 31 21 1 Bit s Description DMA CHNO ADDPCI 31 0 PCI starting address for DMA channel 0 Note At the end of each block size the PCI address of the next block size is loaded in this register 2 62 12 10 03 ALMA2e User Manual IBM DMA CHNO XFERSIZE DMA Channel 0 Transfer Size register Address from PCI interface Config space 0xC8 space PCIH BA1 SPACE 0xC8 Address from VME interf
109. e bit of the IT AVIT STA 0 at address OxF6 6 2 2 VME Interrupt Request Cycle IRQ7 1 Bits 7 to 1 of register IT AVIT DATA 7 1 plays as Enable Disable bits for VME interrupts IRQ7 to IRQ1 generated ALMA2e A low level applied to pin PCI AVITb will be translated into one or several VME interrupt requests according to those AVIT DATA 7 1 bits which are set to a one The Status bit 0 IT AVIT STA is immediately set to zero disable state and no other PCI AVITb interrupt request could be serviced until this bit had not been set to enable through a write to this register bit 6 138 12 10 03 ALMA2e User Manual IBM 6 3 Masking and Generating interrupts to the PCI Any interrupt generated to the PCI by ALMA2e is sourced by an interrupt source belonging to one of the following group Group of VME interrupt sources IRQ7 1 Group of Addressed Interrupt sources 0 to 7 Group of exceptions end of DMA or time out interrupt sources All these interrupt sources are individually maskable via the Interrupt Source Mask Register depicted below IT INT 5 1 01 at Address OxEO bit 0 gt the corresponding interrupt source is not masked validated bit 1 gt the corresponding interrupt source is masked invalidated Bit s Interrupt source Masked 0 VME Bus Arbiter time out Edge detection 5 1 Reserved 6 End of DMA Channel 1 Edge detection 7 End of DMA Channel 0 Edge detection 8 Exception VME amp
110. e drives the VMEbus for only 20 microseconds Recommended setting is 0 VME REQ NORELWDMA This bit is operating when the External VMEbus Requesting feature is used Recommended setting is 0 0 internal request going active makes ALMA2e to ask the External VMEbus requester to release 6 the VMEbus by de asserting pin BGLOCb 1 internal request going active does not make ALMA2e to ask the External VMEbus requester to release the VMEbus DMA request will be serviced only after the VMEbus master decided to release the bus REQ FREEMODE This bit is operating when the External VMEbus Requesting feature is used Recommended setting is O 7 1 The External VMEbus Request via pin BRLOC or bit VME REQ LBR has the highest priority over DMA internal request is serviced immediately 0 The External VMEbus Request has a rotating priority with the DMA internal request is serviced after ALMAQ2e has serviced a pending DMA request 12 10 03 Version 0 3 ALMA2e REGISTERS 2 51 ALMA2e User Manual IBM VME TIM VME Data Transfer Timer Register Address from PCI interface Configuration space 0x72 space PCIH BA1 SPACE 0x72 Address from VME interface A16 space VME SLVA 0x72 A24 space CSR BAR USER 0x72 Width 8 Reset Value 0x00 Access type Read Write 76543210 Bit s Description DTBTOUT 7 0 Time out from 0 to 256 us for Data transfers
111. ecommended value 0x00000000 VME64 TCH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13121110 9 8 7 6 5 4 38 2 1 0 Bit s Description ALMA V64 design corrections For debug only 31 0 This register is used to activate corrective actions that prevents problems seen in previous revision of ALMA Recommended setting is 0 0000 0000 2 94 12 10 03 ALMA2e User Manual IBM VME2ESST CTL VME 2eSST Control register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0 140 Address from VME interface A16 space not seen Width Reset Value Access type A24 space CR CSR BAR USER 0x140 32 0x00002218 Read Write VME2ESST CTL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13112 111 10 9181765432110 Bit s 8 12 13 14 15 16 12 10 03 Description V2bESST SLV VME 2eSST Slave mode enable setto 0 ALMA2e is unable to decode VME 2eSST transfer setto 1 ALMA2e is able to decode VME 2eSST transfer V2ESST_MST VME 2eSST Master mode enable setto 0 ALMA2e is unable to generate VME 2eSST transfer setto 1 ALMA2e is able to generate VME 2eSST transfer V2ESST_BRD VME 2eSST Broadcast mode enable s
112. eed in decoupled mode Read ahead or Write posting A set of registers allows users to set the new FIFO behavior with a high flexibility according to different VME applications As a VME master in DMA mode ALMA2e provides A64 A32 broadcast A32 and broadcast A64 2eSST transaction ALMA2e allows five different speed for 2eSST transfer Data reception can be done at the theoretical maximum speed of 320 Mb sec VME Slave interface The ALMA2e VME slave interface supports the same addressing mode and data size as the VME master interface Sixteen decoding channels are available for accessing the PCI bus from the VME bus Each channel can be configured independently in the A64 A32 A24 A16 address space Height out of 16 channels can be configured independently in the A64 2eSST A32 2eSST A64 2eSST broadcast or A32 2eSST broadcast address space These channels allow the user to program the PCI bus access parameters with a minimum granularity of 1 Mbyte A set of registers allows users to set the new FIFO behavior with a high flexibility according to different VME applications As Slave ALMA2e provides A64 A32 broadcast A32 and broadcast A64 2eSST transaction ALMA2e allows five different speed for 2eSST transfer Data reception can be done at the theoretical maximum speed of 320 Mb sec VME RMW cycle is supported by ALMA2e however the targeted PCI resource is not locked during the read and write ALMA2e does not support the PCI LO
113. es burst size Others values 32 Bytes burst size Note if VSW_CTL 0 is set to 1 this register as no effect 15 Reserved This bit is reserved and return zero when read High Level to start the PCI write transaction if VSW CTLJO is set to 1 0x0 48 bytes 0 1 64 bytes 0x2 80 bytes 0 3 96 bytes 0 4 112 bytes 0 5 128 bytes 0x6 144 bytes 0 7 160 bytes 23 16 0 8 176 bytes 0x9 192 bytes OxA 208 bytes OxB 224 bytes OxC 240 bytes OxD 256 bytes OxE 272 bytes OxF 288 bytes Note 1 if VSW CTLJO is set to 0 this register as no effect Note 2 The High Level must be greater than the Low Level 2 88 12 10 03 ALMA2e User Manual 27 24 31 28 Low Level to start the PCI write transaction if VSW is set to 1 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 OxB OxC OxD OxE OxF Note1 if VSW is set to 0 this register as no effect Note 2 The Low Level must be less than the High Level Reserved This bits are read write and have no functions 48 bytes 64 bytes 80 bytes 96 bytes 112 bytes 128 bytes 144 bytes 160 bytes 176 bytes 192 bytes 208 bytes 224 bytes 240 bytes 256 bytes 272 bytes 288 bytes leftin VME FIFO leftin VME FIFO leftin VME FIFO leftin VME FIFO leftin VME FIFO leftin VME FIFO left in VME FIFO left VME FIFO left VME FIFO left in VME FIFO left in VME FIFO left in VME FIFO left VME FIFO left in VME FIFO left i
114. ess 8000555 modifiers ALMA2e VME target hit 16 VME VME address channels WPOST Write Posting enable RAHEAD Read Ahead enable Generated PCI LEBE Little Big Endian command conversion mode BUSCOM PCI bus command r w Figure 3 VME slave decode amp address translation mechanisms for a VME access to PCI 1 9 2 PCI to VME access 1K Entry Mapping Table ALMAQ2e as a PCI slave implements 6 Base Address Registers for PCI bus address and command decode At Reset these registers are initialized such as to define five ranges of 256 MB mapped in the MEMORY space 3 ranges and in the space 2 ranges while one range of 256B mapped in the space has been reserved for decoding of those PCI cycle accessing internal registers After reset the five 256 windows can be changed to any size from 16MB up to 2GB and to any space or MEMORY thru registers programming Besides the regular decode through Base Address Registers an additional validation of the PCI access is performed with a granularity of 8MB in the MEMORY or I O space For that purpose ALMA2e implements a 1K entry programmable Mapping Table whose low order 512 entries are used to validate MEMORY accesses while the high order 512 entries are used to validate accesses through a validation bit VAL programmed in the entry line PCI address 9Msb are used to index one or the other of these blocks according as PCI cycle is MEMOR
115. esses PCI RAMDATA 0 Little Big Endian conversion mode for PCI to VME access data conversion 00 mode No Conversion 01 mode Address Coherency 10 mode Data Coherency 11 mode Bytes Translation without Swapping PCI RAMDATA AM 5 0 Address Modifiers of VME cycle to generate for PCI to VME access PCI RAMDATA ADD 8 0 Address bits for PCI to VME access address translation Version 0 3 ALMA2e REGISTERS 2 43 ALMA2e User Manual IBM 2 0 3 ALMA2e Utility Registers These Utility Registers are used mainly during the initialization phase at the Power On of the card using ALMA2e Address Size Name Use Page Notes 0x64 4 bytes UTIL RST VME Reset Control amp Watchdog Timer Register 45 0x68 4 bytes UTIL VMECNTL VME System Control Register 46 Ox6C 4 bytes UTIL ERRSTA Error Status Register 47 2 44 12 10 03 ALMA2e User Manual IBM UTIL RST VME Reset Control amp Watchdog Timer Register Address from PCI interface Configuration space 0x64 space BA1 SPACE 0x64 Address from VME interface A16 space VME SLVA 0x64 A24 space CSR BAR USER 0x64 Width 32 Reset Value 0x00000000 Access type Read Write UTIL RST 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121111019 87 6 5 413211 Bit s Description UTIL RST LOC2VME 0 Propag
116. etection 19 Addressed interrupt no 3 Level detection 20 Addressed interrupt no 4 Level detection 21 Addressed interrupt no 5 Level detection 22 Addressed interrupt no 6 Level detection 23 Addressed interrupt no 7 Level detection 24 Reserved 25 VME IRQ1 Level detection 26 VME IRQ2 Level detection 27 VME IRQ3 Level detection 28 VME IRQ4 Level detection 29 VME IRQ5 Level detection 30 VME IRQ6 Level detection 31 VME IRQ7 Level detection 2 72 12 10 03 ALMA2e User Manual IBM IT INT MSKOUT PCI Interrupt Mask Register Address from PCI interface Config space not seen space BA1 SPACE 0 4 Address from VME interface A16 space not seen A24 space CSR BAR BEG USER 0 4 Width 32 Reset Value 0x00000000 Access type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121111019 7 16 5 413211 Bit s Description PCI INTERRUPT MASK see above register IT_INT_MSKSRC 31 0 for interrupt source definition bit 0 the corresponding interrupt source generates an interrupt to the PCI bit 1 the corresponding interrupt source does not generates an interrupt to the PCI 31 0 IT INT STATUS Interrupt Status Register Address from PCI interface Config space not seen space PCIH BA1 SPACE OxE8 Address
117. etto 0 ALMA2e is unable to generate VME 2eSST Broadcast transfer setto 1 ALMA2e is able to generate VME 2eSST Broadcast transfer VME320 Enable VME 320 Mbytes mode setto 0 ALMA2e will generate a Slave error during phase 3 of the address transfer of a VME 320 rate transfer to signal to Master that it is unable to support 320 Mbytes transfer rate setto1 ALMA2e accepts all transfer rate as a Slave VME_SUSPEND setto 0 ALMA2e does not generate a Slave Suspend termination if the PCI interface is busy setto 1 ALMA2e generate a Slave Suspend termination if the PCI interface is busy Reserved These bits are read write and have no functions Speed Selection to generate data on the VME bus 0 1 Very Slow maximum transfer rate is 146 MB s 0 2 Slow maximum transfer rate is 170 9 MB s 0 4 Medium maximum transfer rate 205 MB s 0 8 Fast maximum transfer rate 256 MB s 0x10 Ultra Fast maximum transfer rate 341 MB s Hold H1 Timing setto 0 the minimum time for timing H1 is equal to 0 ns the 5ns required by the specification is ensure by the DTACK propagation delay This register bit setting Z0 is not recommended Check your routing path before using this timing setto 1 the minimum time for timing H1 is equal to 1 VME period 15 6 ns the specification requires 5ns minimum S3 2eSST Setup Timing for the first data phase Setto 0 Minimum time for 53 setup is equal to 1 period 15 6 ns Setto 1 Minimum time
118. evice ID register PCI Command register PCI Status register Revision ID register PCI Class code register Register level programming interface 0x9 Sub Class code offset Base class code offset 0xB Reserved PCI Latency timer register PCI Header type register Reserved PCI Base Address register no1 PCI Base Address register no 2 PCI Base Address register no 3 PCI Base Address register no 4 PCI Base Address register no 5 PCI Base Address register no 6 Reserved Reserved Reserved Reserved Reserved PCI Interrupt line register PCI Interrupt pin register PCI Minimum grant register PCI Maximum latency register ALMA2e REGISTERS Page Notes 26 26 27 28 29 29 29 29 30 31 31 31 31 31 31 33 33 34 34 2 25 ALMA2e User Manual IBM PCIH VID PCI Vendor ID register Address from PCI interface Config space 0x00 space not seen access ends with Master Abort termination Address from VME interface A16 space VME SLVA 0x00 A24 space CSR BAR USER CSR 0x00 Width 16 Reset Value 0x1014 Access type Read Only PCIH VID 15 141 13 12 11 1019 8 7 6 5 41 8 21 11 0 Bit s Description Vendor Identification Number Value 0x1014 index 0x00 0x14 index 0x01 0x10 PCIH DID PCI Device ID register Address from PCI interface Config space 0x02 space not seen access ends with Master Abort termination Address from V
119. fig space not seen IO space PCIH BA1 SPACE 0 104 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x104 Width 32 Reset Value 0x00000000 Access type Read Write VSR CTL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121111019 8 6 5 413211 Bit s Description PCI read burst length control 0 set to 0 the PCI burst length on VME to PCI read ahead transaction is fixed and equal to 32 Bytes Set to 1 the PCI burst length on VME to PCI read ahead transaction is programmable and given by VSR_CTL 15 8 read mode in VME 2eSST read transfer 1 set to 0 The burst size of the PCI transaction is defined by other fields of this VSR_CTL register set to 1 the PCI read burst is equal to the cycle count given by the VME 2eSSt Read Read ahead mode option 2 set to 0 ALMA2e always gets a number of data equal to the PCI read burst size set to 1 ALMA2e stops the PCI read burst a soon as ALMA2e detects the end of the read transac tion on the VME bus 3 7 Reserved This bits are read write and have no functions PCI read burst size if VSR_CTL 0 is set to 1 0x00 32 bytes burst size 0x01 64 bytes burst size 0x02 128 bytes burst size 15 8 0x04 256 bytes burst size 0x08 512 bytes burst size 0x10 1024 bytes burst size 0x20 2048 bytes burs
120. from PCI interface Address from VME interface Width Reset Value Access type DMA 1 CTRL Configuration space OXDC space BA1 SPACE 0xDC A16 space VME SLVA OxDC A24 space CR CSR BAR BEG_USER_CSR 0xDC 16 0x0000 Read Write 15 14 13112 11 1101918171615 3121110 Bit s Description DMA CHN1 START 0 Setto 0 No DMA channel 0 running setto 1 channel 0 starts DMA CHN1 MIXAGE 1 setto 0 channel 1 has to wait the end of DMA channel 0 before to start setto 1 Blocks of both channel 1 and 0 can be interleaved DMA CHN1 VME2PCI DMA transfer direction on channel 1 2 setto 0 PCI read to VME write setto 1 VME read to PCI write DMA CHN1 BUSCOM Three high order bits of the PCI bus command DMA 1 NOINCR No Increment This mode works only with AM type Single or BLT 6 It does not work for MBLT or 2eSST setto 0 normal DMA setto 1 all VME cycles start at the same address 7 Reserved Must be left to 0 13 8 DMA CHN1 AM DMA 1 LEBE VME Address Modifier for DMA channel 1 Conversion type to perform on DMA channel 1 15 14 00 mode conversion 01 mode Address Coherency 10 mode Data Coherency 11 mode Bytes Translation with No Swapping 12 10 03 Version 0 3 ALMA2e REGISTERS 2 69 ALMA2e User Manual IBM DMA 1 Channel 1 Extended Address
121. from VME interface A16 space not seen A24 space CSR BAR USER 0 8 Width 32 Reset Value 0x00000000 Access type Read Write 31 30 29 28 27 26 25 24 23 22 21 201 19 181 17 16 1 5 141 13 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description INTERRUPT SOURCE STATUS see above register IT_INT_MSKSRC 31 0 for interrupt source definition bit 0 the corresponding interrupt source is inactive bit 1 the corresponding interrupt source is active 31 0 12 10 03 Version 0 3 ALMA2e REGISTERS 2 73 ALMA2e User Manual IBM IT INT CTRL PCI Interrupt Type Register Controls the assertion of Interrupt on outputs INT1b 2b 3b and INTAb Address from PCI interface Config space not seen space PCIH BA1 SPACE OxEC Address from VME interface A16 space not seen A24 space CSR BAR BEG USER 0 Width 16 Reset Value 0x0000 Access type Read Write 12111 1019 8 51413121110 Bit s Description IT INT INT1 2 0 INT1b Interrupt pin is asserted upon those interrupt sources among the seven VME IRQ 1 IRQ 7 selected by bits 2 0 encodings 001 to 111 respectively encoding 000 is Reserved IT INT INT2 5 3 INT2b Interrupt is asserted upon those interrupt sources among the seven VME IRQ 1 VME IRQ 7 selec
122. generator at 16 MHz SYSRESET can be generated See Special Features SYSFAIL generator from specific pin SYSFAILINb or from a special ALMA2e register access Operation 2eSST mode ALMA2e supports 2eSST transfers as defined in the Vita 1 5 standard As VME slave up to 8 addressing windows be programmed to accept 2eSST transfers ALMA2e will initiate 2eSST transfers over the VME by a dedicated setting of the internal DMA controller No 2eSST transfers will be generate over the VME as a result of a PCI slave operation Only the 6U version of the standard is implemented The slower 2eVME protocol is not supported During address phase 1 the first 050 assertion an address modifier encoding of 0x20 is used for 2eSST transfers The extended AM codes used by ALMA2e as a VME master or slave are shown in table 1 below TABLE 0 1 Extended AM for 2eSST used by ALMA2e Extended Address Modifier codes Address Data Mode Ox11 A32 D64 2eSST 0x12 A64 D64 2eSST 0x21 A32 D64 Broadcast 2eSST 0x22 A64 D64 Broadcast 2eSST Address phase 2 DSO de assertion includes the cycle count and the speed rate For the cycle count ALMA2e uses either the block size programmed in the DMA controller divided by two because of the 2 edges or a smaller value to avoid crossing a 2 KB boundary or to avoid transferring more data than requested at the end of the DMA 1 10 12 10 03 ALMA2e User Manual IBM As a 2eSST dat
123. gnal name Typ Output e Type External Pull up Pull Description down ADIR Address direction for VME Local transceivers At Power On Reset this signal is forced to low level AMDIR Address Modifier direction for VME Local transceivers At Power On Reset this signal is forced to low level ASDIR Address Strobe direction for VME Local transceivers At Power On Reset this signal is forced to low level BGLOCb PCI Local Bus Grant data output Belongs to the External VMEbus Requesting feature pro tocol Used optionally to prevent deadlocks When asserted grants the VMEbus to the PCI bus mas ter which asserted BRLOCb used optionally by a PCI bus master which does not support the PCI Retry proto col PCI sideband signal BRLOCb PCI Local Bus Request Belongs to the External VMEbus Requesting feature protocol Used to prevent deadlocks from concurrent VME and PCI accesses When asserted forces ALMA2e to request VMEbus ownership used optionally by a PCI bus master which does not support the PCI Retry protocol PCI sideband signal DDIR Data direction for VME Local transceivers At Power On Reset this signal is forced to low level 12 10 03 Version 0 3 SIGNAL DESCRIPTIONS 3 119 ALMA2e User Manual configuration T Output External Signal name Pull up Pull Description e Type d
124. gt 1 1 V_SYSRESETo out 40 161mS RESETOUTb V SYSRESETib In A Sampling VME_SYSCONT_INb Figure 5 1 PowerOn Reset with ALMA2e 5 128 12 10 03 ALMA2e User Manual IBM 5 3 Reset controlled by the RESETINb input The sequence of actions is the following Upon assertion low of RESETINb ALMA2e performs an internal reset and generates RESETOUTb Moreover in the case where ALMA2e is configured as VME System Controller register bit ARB SYSCONTb 9971 is set to 1 see chapter 5 8 Sampling VME System Controller pin on page 131 and provided register bit SUTIL LOC2VME 264 is set to 1 then ALMA2e also generates V SYSRESETo for at least 201ms Note ALMA2e propagates normally VME daisy chains when it is not generating V SYSRESEToO Upon de activation of RESETINb ALMA2e de activates RESETOUTb and Internal reset hardware configurations are sampled see chapter 5 7 Sampling hardware configurations on page 131 Note In the case where RESETINb is activated for less than 201ms V_SYSRESETo being timed by ALMA2e generated during 201ms the PCI bus central resource must hold any access targeted to the VMEbus until completion of the current SYSRESET operation For that purpose software can check that no VME SYSRESET is active by reading register bit UTIL SYSRESET 969 12 10 03 Version 0 3 INITIALIZATION amp RESET 5 129 ALMA2e User Manual IBM
125. h and FIFO control register VME Slave Read Control register DMA Read PCI Control register PCI Read Control register PCI Slave Read Control register DMA Read VME Control register VME Slave Write Control register PCI Slave Write Control register VME Slave A64 upper bits Address VME Master A64 upper bits Address DMA Channel 0 A64 upper bits Address register DMA Channel 0 Slave Select register DMA Channel 1 A64 upper bits Address register DMA Channel 1 Slave Select register VME64x Trouble Shoot register Reserved VME 2eSST Control register CSR user function 0 control register CSR user function 0 upper bits address register CSR user function 1 6 control register CSR user function 1 6 upper bits address register CSR user function 7 control register CSR user function 7 upper bits address register Transfer Rate register VME Time register Cumulative VME access Time register Cumulative VME access Time to ALMA2e register Interrupt Mask register Interrupt Mask FAIL register Geographical Address register Sub Unit Number register Reset Source register General purpose register ALMA2e REGISTERS Page Notes 82 83 84 85 86 87 88 90 91 91 92 92 93 93 94 95 97 98 99 99 100 100 101 102 103 103 104 104 2 81 ALMA2e User Manual IBM DPT CTL Data path and FIFO control register Address from PCI interface Config space not seen space BA1 SPACE 0x100 Address fr
126. hannel 1 For each Channel VME Address Modifiers are programed into bits 13 to 8 of the Channel Control Regis ters DMA_CHNO_AM 5 0 0x00 QCD 1 AM 5 0 0x00 QDD For each Channel the PCI Bus Command three high order bits are programed into the bits 5 to 3 of of the Channel Control Registers 8 148 12 10 03 ALMA2e User Manual IBM DMA CHNO BUSCOWM 2 0 DXXX CC DMA CHN1 BUSCOM 2 0 OXXX DC The PCI Bus Command C BE 3 0 P CBEb 3 0 pins will be made up with CHNO BUSCONM 2 0 contents concatenated with CHNO VME2PCI contents For each Channel the Little Big Endian byte ordering conversion mode to be applied to data bytes is pro gramed into the following 2 bit registers DMA_CHNO_LEBE 1 0 0500 DMA_CHN1_LEBE 1 0 0600 0 gt no Little Big Endian conversion 1 gt Little Big Endian conversion mode is Address Coherency 2 gt Little Big Endian conversion mode is Data Coherency 3 gt Little Big Endian conversion mode is bytes translation with no swapping only applies to 1 2 or 3 byte data PCI Data DMAs PCI read VME write VME data DMAs VME read PCI write have their bytes re ordered according the Big Little Endian conversion mode programmed into field VME_SLVx_LEBE 1 0 Refer to ENDIAN CONVERSIONS on page 151 Finally in the case where both Channels are active it is possible for any one channel to interleave its own DMA
127. hat ALMA2e will not retry its transaction This feature can be advantageously used by those PCI bus master devices which are not supporting the PCI Retry protocol and which therefore may be responsible of deadlocks The mechanism has two implementations one is under pin control BRLOCb as bus request pin BGLOCb as bus grant pin the other is under software control through the Request control register at the address 970 The bit VME REQ LBR of this register is used for bus request and the bit VME REQ LBG for bus grant Once granted the PCI master device issues transaction to access VME resources as long as it wishes and must hold the BRLOCb pin active during all the time it is operating However ALMA2e may at any time ask the device to release the VMEbus by de asserting BGLOCb or resetting the VME REQ LBG bit this event may also be signalled via an interrupt In this case the device must stop its current transaction as soon as it can and signal that it has finished its operation by de asserting the BRLOCb pin or by resetting the VME REQ LBR bit 1 9 Addressing through the ALMA2e bridge High Addressing flexibility is a key feature to enable a bridge such as ALMA2e to accommodate a whole range of uses from a simple SBC Single Board Computer VME card to a complex VME multiprocessor architecture in the majority of VME computer designs software compatibility at user and kernel level with existing standard desktop workstations or P
128. ialized to a 1 SYSFAIL set active The SYSFAIL signal may also be generated by ALMA2e when the SYSFAILINb input is active asserted low From that point ALMA2e will not de activate VME SYSFAIL until SYSFAILINb is disabled even if bit SUTIL SYSFAIL 268 is written to a zero The Status of SYSFAIL signal can be obtained by reading UTIL_SYSFAIL bit bit 0 read to a 1 gt VME SYSFAIL is inactive bit 0 read to a 0 gt VME SYSFAIL is active This bit reflects the SYSFAIL signal state on the VMEbus input V SYSFAlLib whatever the source which issued it i e from the software a write to register bit SUTIL SYSFAIL 268 from other VMEbus agents input V SYSFAILib from the device connected to the SYSFAILINb input The SYSFAIL signal when activated by ALMA2e or by any other VME source may potentially generates an interrupt to the PCI see chapter Interrupt sources translated to an interrupt to PCI on page 130 It is thus advisable to first mask this interrupt source before having the software to issue a VME SYSFAIL 5 132 12 10 03 ALMA2e User Manual IBM 5 11 Reset Watchdog A watchdog function is implemented in ALMA2e which when enabled dictates the VMEbus or PCI bus master to periodically perform a write access to a particular register to prevent ALMA2e from starting a reset operation as it is described below see chapter 5 6 Reset controlled by the Reset Watchdog on page 131
129. ion as pin BGLOCb belongs to the External VMEbus Requesting feature protocol 2 50 12 10 03 ALMA2e User Manual VME ARB VME Bus Arbitration Control register Address from PCI interface Address from VME interface Width Reset Value Access type 76543210 Bit s Description VME ARB SYSCONTB Configuration space 0x71 IO space BA1 SPACE 0x71 A16 space VME SLVA 0 71 A24 space CSR BAR BEG USER 0x71 8 0x00 Read Write R O Reset by POWER ON RESET 0 0 sets 2 as VME system controller external pin VME ARB TYPE ALMA2e VMEbus arbiter arbitration type 1 0 Fixed priority Highest priority is Req 3 Lowest Req 0 1 Rotating priority VME ARB BCLR 0 when ALMA2e is VME system controller it never drives the V BCLRb signal 2 1 when ALMA2e is VME system controller it drives the V BCLRb signal if in Fixed priority mode a higher priority request occurs in Rotating priority a new request occurs VME REQ ROUND 0 Fixed Priorities between internal bus requests 3 1 AVITb pin assertion highest priority 2 PCI access 3 start lowest priority 1 Rotating Priority between above internal bus requests 4 Reserved 2 Must be held to zero otherwise result is unpredictable VME REQ RORTIMER This bit is operating when ALMA2e bus requester is set in the ROR mode Release On Request 5 0 ALMA2e drives the VMEbus permanently 1 ALMA2
130. ister on resets Bit 7 BASE ADD7 Bit 6 VME BASE ADD6 Bit 5 GAP Bit 4 0 GAB 4 0 VME_SLVA_AM 7 0 VME Slave Channel A Address Modifier decoding bits 3 8 encoding of the 2 code AM2 AM0 code is decoded as valid if register bit 1 is decoded as invalid if register bit 0 Version 0 3 ALMA2e REGISTERS 2 55 ALMA2e User Manual VME SLV VME Slave Control Register Address from PCI interface Address from VME interface Width Reset Value Access type Configuration space 0 7 space BA1 SPACE 0x7A A16 space VME SLVA 0 7 A24 space CSR BAR BEG USER 0 7 8 0x00 Read Write 312110 Bit s Description VME SLV ABORT 0 On aborted PCI transaction ALMA2e acknowledges the VME bus by signalling BERR 1 On aborted PCI transaction ALMA2e acknowledges the VME bus by signalling DTACK VME SLV D64DBL 0 AVME MBLT read access with Read prefetch mode disabled on PCI is translated into a suite of PCI single 32 bit data accesses 1 into a suite of PCI 2 data burst accesses VME SLV DTACKPERF This bit controls the assertion timing on slave posted writes and thus has an effect on the data trans fer rate 0 normal assertion of V DTACKob on Posted Writes 1 fast assertion of V DTACKob on Posted Writes Recommended setting is 1 VME SLV DTACK120PERF This bit controls the assertion timing on slave reads and
131. l IBM Document Revision Date Revision Description March 07 03 0 0 Original version First version with all registers are included April 103 os Signal assignment and definition frozen June 25 03 0 2 updates of register s definitions Added DMA controller Deere Gs MONS AUTO SLOT ID function defined 12 10 03 Version 0 3 155 ALMA2e User Manual Copyright International Business Machines Corporation 2003 Rights Reserved Printed in the United States of America 12 03 The following are trademarks or registered of International Business Machines Corporation in the United States or other countries or both IBM the IBM Logo IEEE is a registered trademark in the United States of the Institute of Electrical and Electronics Engineers Fur further information see http www ieee org Other company product and service names may be trademarks or service marks of others All information contained in this document is subject to change without notice The products described in this document are NOT intended for use in applications such as implantation life support or other hazardous uses where malfunction could result in death bodily injury or catastrophic property damage The information contained in this document does not affect or change IBM product specifications or warranties Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or thi
132. l IBM IT INT MSKSRC Interrupt Source Mask Register This registers allows the masking of the sources of interrupt that can activate the P INTAb output signal Address from PCI interface Config space not seen space BA1 SPACE OxEO Address from VME interface A16 space not seen A24 space CSR BAR USER OxEO Width 32 Reset Value 0x00000000 Access type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121 11 10 9 8 7 6 5 41 31 21 1 bit 0 the corresponding interrupt source is not masked bit 1 the corresponding interrupt source is masked Bit s Description 0 VME Bus Arbiter timeout Edge detection 5 1 Reserved 6 End of DMA Channel 1 Edge detection 7 End of DMA Channel 0 Edge detection Exception VME amp PCI Edge detection 8 See definition in the CSR USER DEF INT MSKFAIL register at address 1 0 9 ALMAQ2e asserts BGLOCb pin the PCI agent which requested the VME bus by asserting the BRLOCb pin is granted Edge detection 10 ALMA 2e deasserts BGLOCb pin ALMA 2e is asking for the VME bus to be released Edge detection 13 11 Reserved 14 SYSFAIL Level detection 15 ACFAIL Level detection 16 Addressed interrupt no 0 Level detection 17 Addressed interrupt no 1 Level detection 18 Addressed interrupt no 2 Level d
133. le ALMA2e interprets A64 as A32 AM code setto 1 VME A64 MBLT mode is Enable VME 64 BLT SGL control 7 setto 0 VME A64 BLT and SGL mode is Disable ALMA2e interprets A64 as A32 AM code setto 1 VME A64 BLT and SGL mode is Enable VME Master Bloc size setto 0 VME bloc size is fixed and equal to 8 for PCI to VME access 8 setto 1 VME bloc size is programmable PCI to VME transfers for up to 2KBytes burst is controlled by the bit 0 of the PSW 9 11C set to 1 Note this register does not control bloc size for DMA engine transfer PCI Frequency 9 setto 0 Only PCI frequency at 33 MHz is supported compatible with previous ALMA V64 product setto 1 PCI frequency up to 66 MHz is supported PCI Timing Control setto 0 Nominal timing control behavior 10 setto 1 ALMA2e adds an extra PCI clock to detects that a PCI slave has accept PCI 64 transaction In this case PCI slaves must not drive TRDY on the same clock as DEVSEL Note this register was introduce for timing 14 11 Reserved This bits are read write and functions DMA Fair Play mode 15 setto 0 DMA fair play mode is Disable setto 1 DMA fair play mode is Enable DMA Fair play period miento Represents the number of VME clock between two DMA requests when the DMA fair play mode is enable 2 82 12 10 03 ALMA2e User Manual IBM VSR CTL VME Slave Read Control register This register controls VME Slave Read access Address from PCI interface Con
134. lid INT2b is activated asserted low if IRQ4 is valid INT2b is activated asserted low if IRQ5 is valid INT2b is activated asserted low if IRQ6 is valid INT2b is activated asserted low if IRQ7 is valid INT INT3 10 8 6 3 2 INT3b is activated INT3b is activated INT3b is activated INT3b is activated INT3b is activated INT3b is activated INT3b is activated INT3b is activated asserted low if Addressed Interrupt n 0 is valid asserted low if Addressed Interrupt n 1 is valid asserted low if Addressed Interrupt n 2 is valid asserted low if Addressed Interrupt n 3 is valid asserted low if Addressed Interrupt n 4 is valid asserted low if Addressed Interrupt n 5 is valid asserted low if Addressed Interrupt n 6 is valid asserted low if Addressed Interrupt n 7 is valid Routing to INT1b 2b 3b pins with CSR USER DEF INT MSKOUT The controls of INT1b 2b 3b interrupt output signal is possible with a setting of the bits 11 and 12 of the PCI Interrupt Type register IT INT CTRL at address When bit 1120 and bit 12 1 the Interrupts sources are masked by the registers USER DEF INT MSKOUT1 2 3 and CSR USER DEF INT MSKFAIL Example The two interrupt outputs INT1b and INT2b can be configured to generate respectively two separate DMA interrupts DMAO and DMA1 when each DMA operation is done The registers programming is IT INT OxEC 0x00001000 CSR U
135. lso to generate either VME interrupts IRQ7 IRQ1 or a VME bus cycle whose characteristics are fully programmable read or write cycle value of address address modifiers and data 12 10 03 Version 0 3 Overview 1 13 ALMA2e User Manual IBM 1 8 Special Features Reset controller ALMA2e handles the following Reset sources Power on reset when input pin POWER ON RESETb is asserted Low reset SYSRESET when input pin V SYSRESETib is asserted Low Local reset when input pin RESETINb is asserted Low Addressed Reset when a specific 8 bit register is addressed in write mode Reset due to Reset Watchdog function These resets can be propagated to the locations below according to programming ALMA2e internal reset VME reset SYSRESET assertion of the V SYSRESETo pin High Local reset assertion of the RESETOUTb pin Low Data conversion Little Endian and Big Endian byte ordering conventions are fully supported by ALMA2e Little Endian Big Endian conversions are automatically performed on both data directions according to a programmable conversion mode as defined below refer to the LEBE field of the VME slave channels and of the PCI Mapping Table entry LEBE 00 No conversion Data byte ordering and Address 2 low order bits remain unchanged LEBE 01 Address Coherency Data bytes are swapped Address 2 low order bits remain unchanged LEBE 10 Data Coherency Data byte ordering
136. ly register set to 0 Although this bit is set to 0 ALMA2e is able to generate and decode PCI Memory Write amp Invalidate Cycles VGA Palette Snoop Read only register set to 0 ALMA2e is not a device Enable Parity Error Response settoQ ALMA2e masks detection of parity errors and P_PERRb is not asserted although parity is still generated 6 setto1 ALMA2e PCI bus parity errors detection is enable for all types of PCI transaction including the following PCI address bus parity errors PCI data bus parity errors while PCI master PCI data bus parity errors while PCI target Address Stepping Control Read only register set to 0 2 does not support address stepping as a PCI master nor as a PCI target P SERRb Enable 8 setto 0 ALMA2e never drives P SERRb signal setto 1 X Enable the assertion of P SERRb when a PCI parity error is detected The bit 6 above of the PCI command register must also be enable for parity error reporting 9 Fast back to back enable Read Only set to 0 ALMA2e is not able to generate fast back to back transaction 15 10 Reserved These bits are reserved and return zeros when read 12 10 03 Version 0 3 ALMA2e REGISTERS 2 27 ALMA2e User Manual IBM PCI Device Status register Address from PCI interface Config space 0x06 space not seen access ends with Master Abort termination Address from VME interface A16 space VME SLVA 0x06
137. n VME FIFO left in VME FIFO Note 1 If register DPT CTL 1 is set to 0 register DRV CTL 31 0 must be left to 0 Note 2 If the High Level and the Low level to close ALMA2e may miss the High Level value to restart the PCI transaction The PCI transaction will then start at the end of the VME transaction Performance will drop a little bit 12 10 03 Version 0 3 ALMA2e REGISTERS 2 89 ALMA2e User Manual IBM PSW CTL PCI Slave Write Control register This register controls PCI to VME write transaction Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x11C Address from VME interface A16 space not seen A24 space CSR BAR USER CSR 0 11 Width 32 Reset Value 0x00000000 Access type Read Write Recommended value 0x00000001 PSW CTL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 141 13 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description PCI Slave Write control 0 set to 0 ALMA2e generates a PCI Disconnect Without Data transfer on the ninth 9th data set to 1 ALMA2e accepts up to 2K bytes burst 1 Reserved Must be left to 0 31 2 Reserved These bits are read write and have no functions Note 1 If register CTL 1 is set to 0 register DRV CTL 31 0 must be left to 0 2 90 12 10 03 ALMA2e User Manual IBM VME
138. nd VME to PCI access conversion address translation bus cycles parameters Programmable Posted Write Prefetch Read coupled mode BLT MBLT cycle e Semaphore registers 64 bit 66MHz bus interface Fully compliant 64 bit 25 to 66 MHz PCI bus interface Revision 2 2 master slave with burst operation e 1K entry on chip Mapping Table for PCI to VME access conversion address translation bus cycle parameters Little Endian Big Endian byte ordering conversion with programmable conversion modes Programmable Posted Write Prefetch Read coupled mode Clocking e PCI clock 25 to 66MHz e VME Clock 64MHz IEEE 1149 1 JTAG testability support Available in high density 360 Ball BGA packages Interfaces to both 3V and 5V technologies 12 10 03 Version 0 3 Overview 1 7 ALMA2e User Manual 1 4 VMEbus signals external buffering example The following figure shows how external signal buffering can be done with either 74ABT or ETL or SN74VMEH22501 or equivalent technologies ALMA2e control signals xxxDIR are used to set the direction of the corresponding signals For the Open collector type of drivers it is possible to choose between inverting and non inverting signal by placing a 1 0 on the input pin of ALMA2e Buffer Possible Technology DDIR SN74VMEH22501 V D 81 0 D 8
139. ns 6 ns P_PAR 3 00 ns Ons 2ns 6 ns P_PAR64 3 00 ns Ons 2ns 6 ns 12 10 03 ALMA2e User Manual 1 10 3 VME 2eSST Timings Following timings are given for ALMA2e in 2eSST mode For the Set up Hold timings of the ALMA2e DATA as input the reference signal is DS1 in Write and DTACK in Read Note that the 2eSST specifies the timings at the Back plane connector Table 4 VME2eSST timing Effective Speed selection 22 number of VME CLK anh transfer rate VME2ESST CTL 8 12 ALMA2 64 MHz or 60 MHz at source connector 146 MBytes s VERY SLOW 0x01 23 4 ns 3 5 VME CLK 54 6 ns 64 MHz SST 160 18 ns 171 MBytes s SLOW 0x02 15 6 ns CLK 46 8 ns 64 MHz SST 267 10 8 ns 205 MBytes s MEDIUM 0x04 15 6 ns 2 5VME 39 0 ns 64 MHz SST 267 10 8 ns 256 MBytes s FAST 0x08 15 6 ns 2VME 31 2 ns 64 MHz SST 267 10 8 ns 341 MBytes s ULTRA FAST 0x10 7 8 ns 1 5VME 23 4 ns 64 MHz SST 320 320 MBytes s ULTRA FAST 0x10 8 35 ns 1 5VME CLK 25 0ns 60 MHz SST 320 9 ns 12 10 03 Version 0 3 Overview 1 19 ALMA2e User Manual IBM 1 11 REGISTER SET 1 11 1 ALMA2e registers access mechanisms 1 ALMA2e registers Space ALMA2e Configuration Space A space named ALMA2e Configuration Space of 256 entries Bytes is allocated to internal registers All the internal registers are intrinsically in the little endian byte ordering con
140. nterrupt of level N 1 to 7 is issued by ALMA2e when bit of the register is set to a one together with the enable bit bit 0 set to a one IT GEN 7 0 at address OxF8 Upon the interrupt acknowledge cycle VME IACK cycle ALMA2e will automatically clear the bit which initiated the interrupt However one can reset the pending interrupt by writing a one to this bit together with writing at the same time a zero to bit 0 should be used for debug purpose only since this violates the VME norm A read to IT IRQ GEN 7 0 from the VME or PCI will allow to know the current status of the requests bit N to a one indicates that VME IRQ N interrupt is pending According to the VME norm this register can be initialized only via a Power On Reset to prevent a pending interrupt not yet acknowledged to be cleared After any other reset than the Power On Reset and before any setting of this register it is advisable to read this register again in order to determine whether it remains an interrupt pending VME interrupts may also be generated from the local bus PCI bus via the mechanism associated to the pin PCI AVITb see chapter 6 2 Generating Interrupt to the VME from the PCI AVITb pin on page 6 129 6 144 12 10 03 ALMA2e User Manual IBM 6 6 ALMA2e response to a VME interrupt acknowledge cycle ALMA2e samples its own interrupt requests when it detects VME IACK input V IACKb is asserted low It examine then the VME interrupt
141. nual Chapter 2 ALMA2e REGISTERS Register space PCI Configuration registers PCI Operation registers ALMA2e Utility Registers ALMA2e VME Registers ALMA2e DMA Registers ALMA2e Interrupt Registers ALMA2e Extended Registers CSR Control Status Registers CR Configuration ROM Registers 12 10 03 Version 0 3 25 35 44 49 61 71 81 105 109 Address Offset x 00 3C x40 63 x64 6F x48 BF 0 DF xEO FF x100 1 7 7FFFF x03 FFF ALMA2e REGISTERS 2 23 ALMA2e User Manual IBM 2 24 12 10 03 ALMA2e User Manual 2 0 1 PCI Configuration registers These registers are from the PCI interface only accessible in CONFIG mode access Address 0x00 0x02 0x04 0x06 0x08 0x09 0x0C 0 OxOE OxOF 0x10 0x14 0x18 0 1 0 20 0 24 0 28 0 2 0 30 0x34 0x38 Ox3C Ox3D Ox3E Ox3F 12 10 03 Size Name 2 bytes PCIH_VID 2 bytes PCIH_DID 2 bytes PCIH_CMD 2 bytes PCIH_DSTAT 1 byte PCIH_REVID 3 bytes PCIH_CLSCD 1 byte PCIH_CLS 1 byte PCIH_LT 1 byte PCIH_HT 1 byte PCIH_BIST 4 bytes PCIH_BA1_SPACE 4 bytes PCIH_BA2_SPACE 4 bytes PCIH_BA3_SPACE 4 bytes PCIH_BA4 SPACE 4 bytes PCIH_BA5 SPACE 4 bytes PCIH_BA6_SPACE 4 bytes Reserved 4 bytes Reserved 4 bytes Reserved 4 bytes Reserved 4 bytes Reserved 1 byte PCIH_ITLINE 1 byte PCIH_ITPIN 1 byte PCIH_MINGNT 1 byte PCIH_MAXLT Version 0 3 Use Vendor ID register D
142. om VME interface Config space 0x3C space not seen access ends with Master Abort termination A16 space VME SLVA 0x3C A24 space CSR BAR USER CSR 0x3C Width 8 Reset Value 0x00 Access type Read Write PCIH ITLINE 7 6 5 4 3 2 1 0 Bit s Description 7 0 Routing path of the existing PCI Interrupt pin to Interrupt system pin PCIH_ITPIN PCI Interrupt Pin register Address from PCI interface Address from VME interface Width Reset Value Access type PCIH_ITPIN 76543210 Bit s Description 12 10 03 Version 0 3 Config space 0x3D space not seen access ends with Master Abort termination A16 space VME_SLVA 0x3D A24 space CR_CSR_BAR BEG_USER_CSR 0x3D 8 0x01 Read Only the PCI INTA interrupt pin is enable INTA is an output of ALMA2e Read only register set to 0x01 ALMA2e REGISTERS 2 33 ALMA2e User Manual PCIH MINGNT PCI Minimum Grant register Address from PCI interface Address from VME interface Width Reset Value Access type MINGNT 76543210 Bit s Description 7 0 Read only register set to 0x00 PCIH MAXLAT PCI Maximum Latency register Address from PCI interface Address from VME interface Width Reset Value Access type PCIH MAXLAT 7 6 5 4 3 21 11 0 Bit s Description 7 0 Read only
143. om VME interface A16 space not seen A24 space CSR BAR USER 0x100 Width 32 Reset Value 0x00000000 Access type Read Write Recommended value 0x00108103 on a PCI 32 bit 33 MHz bus 0x00108133 on a PCI 64 bit 33 MHz bus 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4113 121 11 10 9 8 7 6 5 41 31 21 1 Bit s Description PCI FIFO select PCI write in PCI FIFO VME Read PCI FIFO set to 0 32 Bytes PCI FIFO selected B setto 1 2 KBytes PCI FIFO selected It is Recommended to set bit 0 amp 1 to the same value such that the VME and the PCI FIFOs are identical in size VME FIFO select VME write in VME FIFO PCI Read VME FIFO set to 0 32 bytes VME FIFO selected set to 1 2 KBytes VME FIFO selected 2 Must be left to 0 3 Reserved This bit is Read Write and has no function PCI 64 bit Master control 4 setto 0 PCI 64 bit Master interface Disable setto 1 X PCI 64 bit Master interface Enable Note PCI 64 bit Master interface is enable only if both PCI FIFO select and VME FIFO select are set to 1 PCI 64 bit Slave control 5 setto 0 PCI 64 bit Slave interface is Disable setto 1 PCI 64 bit Slave interface is Enable Note PCI 64 bit Master interface is enable only if both PCI FIFO select and VME FIFO select are set to 1 VME A64 MBLT control 6 setto 0 VME A64 MBLT mode is Disab
144. on 0 3 INITIALIZATION amp RESET 5 127 ALMA2e User Manual IBM 5 2 Reset with POWER RESETb The typical sequence of Reset actions is the following Upon POWER ON RESETb assertion low ALMA2e performs Internal reset and generates V SYSRESETo and RESETOUTb Upon de activation of POWER ON RESETb 40ms timer is started Upon the 40ms timer expiration the VME System Controller VME SYSCONT IND is sampled see chapter 5 8 Sampling VME System Controller pin on page 131 hardware configurations are sampled see chapter 5 7 Sampling hardware configurations on page 131 a new timer of 161ms is started Upon the 161ms timer expiration all board power supplies are now stabilized V SYSRESETo RESETOUTb and Internal reset are de activated Note The VME norm requires that the minimum active duration of SYSRESET by any board to be at least 200ms PCI Bus P RSTb Sampled VME_SYSCONT_INb 2 2 RESETINb ALMA2e i AEA Jo Signals VME BASE ADD6 7 m me CR CSR BAR 4 AUTO SLOT ID POWER ON RESETb gt UTIL RST gt RESETOUTb UTIL VMECNTL V SYSRESETo V 4 VME Bus Schematic for Reset with ALMA2e TO T1 T2 T4 T5 SYS CLK UUULUUUUUUUUUUUUUUUUUUUL Power Supplies Ex POWER ON RESETb 20165 201mS
145. own RESERVED1 RESERVED No Pull Up or Pull Down required DTACKDIR Acknowledge direction for VME Local transceivers At Power On Reset this signal is forced to low level DSDIR Data Strobes direction for VME Local transceivers At Power On Reset this signal is forced to low level INT1b o d Pull Up ALMA2e Interrupt Request 1 PCI sideband signal INT2b o d Pull Up ALMA2e Interrupt Request 2 PCI sideband signal INT3b o d Pull Up ALMA2e Interrupt Request PCI sideband signal PCI AVITb Interrupt Request from PCI Agent PCI sideband signal A VME cycle or a VME Interrupt is generated according to bit 7 of the IT AVIT CTRL register Address OxF4 AUTO SLOT ID Auto slot ID Active High 1 See paragraph 5 12 GAb 4 0 Geographical Addressing used by VME64x boards to automatically identify into which VME64x backplane slot it is plugged GAPb Geographical Addressing Parity POWER ON RESETb Power On Reset from board active Low 0 PWSR CTL Varies with Power System Reset Control configuration When POWER ON RESETb signal becomes active the V SYSRESETo and V SYSFAILo signals are disabled if that pin 1 are enabled if that pin 0 OC CTL Varies with Open Collector Control configuration must be tied to 0 if inverting external OC buffers are used must be tied 1 with non inverting external OC buffers OEb Pull Up Global Output Enable for VME Local transceivers optional use RESETINb Reset input from boa
146. rd RESETOUTb o d Pull Up Reset output for board reset SYSCONDIR Direction for V BCLRb and V SYSCLK VME Local transceivers At Power On Reset this signal is forced to low level SYSFAILINb System fail hardware input VME BASE ADD7 Varies with Enable external sample of base address in slave mode A16 VME BASE ADD6 Varies with configuration Base address in slave mode A16 VME CLK VME Clock up to 64 Mhz VME SYSCONT INb Varies with configuration VME System Controller input ALMA2e is VME System Controller if sampled Low 0 after Reset 3 120 12 10 03 ALMA2e User Manual IBM 3 4 JTAG signals Output External Signal name 1 0 T z Pull up Description Pull down TCK JTAG Clock TDI Data input TDO 1 5 Data output TMS Mode Select TRSTb JTAG Reset 3 5 Manufacturing Test signal Output External Signal name 1 0 T Pull up Description Pull down LSSD Boundary scan Latches CE1 DI1 Vdd Driver Inhibit1 CE1 DI2 Vdd Driver inhibit2 CEO TEST Gnd Test C Clock IO Gnd CE1 RI Vdd Receiver inhibit Note 1 This test signal is for manufacturing use only It must be pulled up or tied to Vdd for normal ALMA2e operation Note 2 This test signal is for manufacturing use only It must be pulled down or tied to Gnd for normal ALMA2e operation
147. rd parties All information contained in this document was obtained in specific environments and is presented as an illustration The results obtained in other operating environments may vary THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document IBM Microelectronics Division 2070 Route 52 Bldg 330 Hopewell Junction NY 12533 6351 The IBM home page can be found at http www ibm com Keep in touch with the fast pace of developments within IBM Microelectronics through news summaries and technical updates delivered electronically at ibm com chips techemail 156 June 25 03
148. requests it has generated in order to find the one which is to the same level than the one being acknowledged If it effectively finds a pending interrupt at that level it executes the following actions itresets of the pending interrupt it provides the interrupt vector to the VME data bus bits 000 007 D 0 7 it activates the VME DTACK signal V DTACKb That principle of releasing the interrupt upon acknowledgment complies with the interrupter mode of ROACK The interrupt vector provided ALMA2e is stored into the 8 bit register IT IRQ at address OxF7 for which the 3 low order bits encode the level of the VME interrupt the 5 high order bits are coded by the application so that to provide a to specific vector to the VME In the case where ALMA2e plays as the VMEbus arbiter and is the originator of the VME interrupt it is well clear that it does not activate its VME IACKOUT output signal V IACKOUTDb If ALMA2e is not the interrupting device it will propagates the VME IACKIN V IACKIND to IACKOUT V IACKOUTDb Daisy Chain via pins 12 10 03 Version 0 3 INTERRUPTS 6 145 ALMA2e User Manual IBM Chapter 7 ERROR HANDLING The 32 bit Error Status Register UTIL ERRSTA at address Ox6C is dedicated for the recording of the error events that ALMA2e is encountering during its operation The bit definition is following 0 10 11 12 13 18 19 20 21 7 146 No VME agent has asserted a V BB
149. rror occurs PCI cycle completes with a Taget or a Master Abort VME_slv_writefail ALMAQGe is the target of a VME write non posted access and a PCI error occurs PCI cycle completes with a Target or a Master Abort VME_slv_readfail ALMAQGe is the target of a VME read access in Read Ahead mode PCI data are prefetched and a PCI error occurs PCI cycle completes with a Target or a Master Abort VME tim Gtbfail ALMA2e is System Controller A data transfer time out occurs VME slave is responding at time out defined by register VME TIM UTIL reset A reset has been generated ALMA2e Watchdog function the Watchdog timer defined by UTIL_RST 31 16 register has not been cleared before time out IT mng avitfail PCI AVITb pin is asserted ALMA2e translates the interrupt into a VME cycle which completes with a Bus Error PCI seq befail ALMA2e is the target of a PCI access for which the PCI Byte Enables pattern is specifying non adjacent valid bytes for example PCI reading writing only the byte3 and byte1 of the 4 byte data pattern byte2 and byteO being not transferred PCI seq sizefail ALMA2e is the target of a PCI burst access for which data beat size is not equal to 32 bits PCI seq wpostfail ALMAGe is the target of a PCI write posted access and a VMEbus Error occurs PCI seq writefail ALMAQGe is the target of a PCI write non posted access and a VMEbus Error occurs PCI seq read fail ALMAQGe is the targe
150. s VMEbus Error when ALMA2e is the target of a PCI write non posted access VMEbus Error when ALMA2e is the target of a PCI read access Read Ahead mode enabled or not VMEbus Error during DMA Channel 1 VMEbus Error during DMA Channel 0 PCI error Target or Master Abort during DMA Channel 1 PCI error Target or Master Abort during DMA Channel 0 12 10 03 ALMA2e User Manual IBM Chapter 8 DMA Controller Operations 8 1 Overview ALMA2e implements a DMA Controller which is offering two independent channels allowing each to move between VMEbus and PCI bus up to 256 MBytes using VME MBLT cycles or 128 MBytes using VME BLT cycles of data The total amount of data to transfer called transfer count is sliced into blocks of data whose size called block count is also programmable Each block is transferred to the VME through a single bus tenure ALMA2e keeps the VMEbus until all the data of the block are transferred During a block transfer on each data phase beat either 64 bits MBLT or 32 bits BLT of data are exchanged While on the PCI bus side the same block is subject to multiple PCI burst cycles for being transferred PCI burst size is of 8 data of 32 bit at the maximum excepted in the Turbo mode depicted below Each one of the DMA channels 0 and 1 can be programed with the followings Astart bit the DMA starts when this bit is written by the software The transfer direction from VME to
151. s OxFB IT 4 Address OxFC IT ACK5 Address OxFD IT ACK6 Address OxFE IT ACK7 Address OxFF OxF9 OxFA OxFB OxFC OxFD OxFE OxFF ALMA2e REGISTERS 2 79 ALMA2e User Manual IBM 2 80 12 10 03 ALMA2e User Manual 2 0 7 ALMA2e Extended Registers Address 0x100 0x104 0x108 0x10C 0 110 0 114 0 118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x180 0x184 0x1B8 0x1BC 0x1C0 0x1C8 0 100 0 108 0 1 0 1 4 0 1 8 Ox1EC Ox1F0 Ox1F1 0 1 2 0 1 4 Ox1F8 Ox1FC 12 10 03 Size 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 8 bytes 8 bytes 8 bytes 4 bytes 4 bytes 4 bytes 4 bytes 1 bytes 1 bytes 1 bytes 3 bytes Name DPT CTL VSR CTL DRP CTL PCR CTL PSR CTL DRV CTL VSW CTL PSW CTL VME SLV A64 VME MST A64 DMAO VME A64 DMAO VME SLVSEL DMA1 VME A64 DMA1 VME SLVSEL VME64_ TCH VME2ESST_CTL CSR USER FUNCO CTL USER FUNCO 64 CSR USER FUNC7 CTL CSR USER FUNC7 A64 CSR USER XRATE CSR USER DEF VME TIME CSR USER DEF VME USED CSR USER DEF ALMA USED USER DEF INT MSKOUT1 CSR USER DEF INT MSKOUT2 CSR USER DEF INT MSKOUTS3 CSR USER DEF INT MSKFAIL GA CSR USER DEF SUBUNIT NB CSR USER DEF RST SRC USER DEF REG0 1 2 Version 0 3 Use Data pat
152. s all the parameters required to generate a master access onto the VMEbus such as address bits for PCI to VME address translation ADD 9 bits the VME Address Modifiers AM 6 bits Little Big Endian conversion mode LEBE coded 2bits and Read Ahead enable 1bit To accommodate software mapping flexibility requirements ALMA2e allows for some programming of its slave image characteristics via a selectable feature So the so called hard coded recognition address range depth and space as defined by the base address field size and the I O space MEMORY space indicator bit value within the PCI Base Address Register layout can be selectively overridden by programmed values As slave ALMA2e can receive PCI burst up to 2KB without wait states during data phase 1 12 12 10 03 ALMA2e User Manual IBM 1 6 DMA ALMA2e has two DMA channels user accessible with a programmable priority between channels and the option that blocks from the two channels may be interleaved Each channel is initialized with a source address a destination address a transfer count up to 16 MBytes 2M words of 64 bits maximum a block count up to 2KBytes up to 256 words of 64 bits plus all the necessary control data VME Address Modifiers PCI bus command transfer direction etc When DMA ends the information related to the completion of the DMA normal ending or a description of the errors is available in an interrupt status register and an error
153. seen A24 space CSR BAR USER 0x128 Width 32 Reset Value 0x00000000 Access type Read Write DMAO VME A64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121111019 8 7 6 5 413211 Bit s Description DMAO VME A64 2059 DMA Channel 0 VME Upper Address bits for A64 VME access DMAO VME SLVSEL DMA Channel 0 VME Slave Select register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0 12 Address from VME interface A16 space not seen A24 space BAR USER 0x12C Width 32 Reset Value 0x00000000 Access type Read Write DMAO VME SLVSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1411312111109 87 615 413211 Bit s Description SLVSEL 8450 DMA Channel 0 VME Slave Select signals for DMA channel 0 VME 2eSST broadcast cycles 2 92 12 10 03 ALMA2e User Manual IBM DMA1 VME A64 DMA Channel 1 VME A64 upper bits Address register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x130 Address from VME interface A16 space not seen A24 space CSR BAR BEG USER 0x130 Width 32 Reset Value 0x00000000
154. setting IT INT MSKOUT S1 0 at address 0 4 bit 0 translation of valid interrupt of rank into an interrupt to PCI is enabled bit 1 translation of valid interrupt of rank n into an interrupt to PCI is disabled 6 3 1 Routing to Interrupt Pin The interrupt to PCI is signalled through one the following pins P INTAb pin INTA of the PCI bus norm INT1b INT2b or INT3b according to the setting of the bit 11 of the register IT INT CTRLat Address OxEC IT INT MODE bit 11 0 Standard mode P INTAb INTAZ is activated asserted low for any valid interrupt source 1 Real Time mode INTAb INTAZ is activated asserted low for any valid interrupt source unless otherwise specified by registers fields IT INT INT1 IT INT INT2 and IT INT see below 6 140 12 10 03 ALMA2e User Manual INT INT1 bit 2 0 NOOR WDM Reserved INT1b is activated asserted low if IRQ1 is valid INT1b is activated asserted low if IRQ2 is valid INT1b is activated asserted low if IRQ3 is valid INT1b is activated asserted low if IRQ4 is valid INT1b is activated asserted low if IRQ5 is valid INT1b is activated asserted low if IRQ6 is valid INT1b is activated asserted low if IRQ7 is valid INT INT2 5 3 NOOR WDM Reserved INT2b is activated asserted low if IRQ1 is valid INT2b is activated asserted low if IRQ2 is valid INT2b is activated asserted low if IRQ3 is va
155. ss will repeat until DMA_CHNO_XFRSIZE 21 0 count is exhausted At that point the end of DMA event if not masked is recorded into the Interrupt Status Register E8 control signal seq finishO is raised and an interrupt to the PCI may be signalled see chapter 6 4 Interrupt sources translated to an interrupt to PCI on page 142 When a transfer error is detected on either buses control signals seq pcifailo seq pcifail1 are raised for a PCI bus error on Channel 0 1 and seq vmefailo seq vmefail1 are raised for a VMEbus error The abnormal termination events are recorded into the Error Status Register 6 and also if not masked into the Interrupt Status Register E8 and an interrupt to the PCI may be signaled see chapter Chapter 7 ERROR HANDLING on page 146 and chapter 6 4 Interrupt sources translated to an interrupt to PCI on page 142 8 150 12 10 03 ALMA2e User Manual IBM Chapter 9 ENDIAN CONVERSIONS The VMEbus bytes are ordered using the Big Endian convention while the Little Endian s is used for the PCI bus ALMA2e automatically performs endian conversions data exchanged between buses The mode in which the endian conversion is processed can be programmed into the Mapping Table Little Big Endian conversion mode 1 0 field for PCI accesses or into the VME Slave Channel 0 7 Control registers field VME SLVO LEBE 1 0 Below are described the Endian conversion modes used by A
156. states it A pull up is required to sustain the inactive state untilanother agent drives it and must be provided by the central resource o d Open Drain allows multiple devices to share as a wire OR All non mentioned output signal types are Totem Pole standard active driver All inputs are TTL levels 5V Interface All I Os have protection circuitry that permits connection to 5 V busses without damage This does not imply however that the I Os can actively drive CMOS compatible 5V level TTL LVTTL and PCI levels are only supported Pull Down All Pull Down resistors must be lower or equal to 3KOhm 12 10 03 Version 0 3 SIGNAL DESCRIPTIONS 3 115 ALMA2e User Manual P_ADL 31 0 P ADH 31 0 P CBELb 3 0 P BEHb 3 0 P PAR P PAR64 P FRAMEb REQ64b P TRDYb P IRDYb P STOPb P DEVSELb ACK64b P IDSEL P PERRb P SERRb P P INTAb P RSTb PCI64 bus interface 89 P REQb P GNTb TDI TDO TMS TRSTb JTAG interface 5 CEO TEST CE1 DI CE1 DI2 CEO CE1 RI Mfg Test signals 5 tu RESERVED1 BGLOCb BRLOCb PCI_AVITb INT1b INT2b INT3b Total Signal I O s 252 V D 81 0 V DSb 1 0 V DTACKb V WRITEb V A 81 1 V 5 0 V LWORDb V ASb V IRQib 7 1 V IRQo 7 1 V ACFAlLb V SYSFAlLib V_SYSFAILo V_IACKINb VMEBus V_IACKOUTb V IACKb interface V BRib 3 0 121 V BRo 3 0 V BGINb 3 0 V BGOUTDb 3 0
157. stops reading data while it is flushing its FIFO to the VMEbus at the slower speed of that bus This mode is controlled by the following programming bits 12 10 03 Version 0 3 DMA Controller Operations 8 149 ALMA2e User Manual IBM DMA CHNO TURBO 000 CC DMA_CHN1_TURBO 060 DC 0 gt Turbo mode disabled on Channel 0 Channel 1 1 gt Turbo mode enabled on Channel 0 Channel 1 8 3 DMA Operation Timing ALMA2e will attempt to start DMA type of transfer on one or both channels when the software writes a one into the bit 0 of the Channel Control Registers DMA_CHNO_START 0x00 bit written to 1 ALMA2e is required to start a DMA on Channel 0 bit written to 0 no action DMA continues normally DMA_CHN1_START 0x00 DC bit written to 1 ALMA2e is required to start a DMA on Channel 1 bit written to 0 no action DMA continues normally In order to perform its DMA ALMA2e must get the ownership of both VMEbus and PCI bus It starts first to request the VMEbus when granted it then requests the PCI bus and starts as soon it gets the PCI bus transferring its first DMA block CHNO BLOCSIZE 7 0 is decremented as data phases are acknowledged on both VME and PCI buses When DMA_CHNO_BLOCSIZE 7 0 count is exhausted the block is then fully transferred DMA CHNO XFRSIZE 21 0 is decremented by the amount of DMA_CHNO_BLOCSIZE 7 0 reflecting the new amount of VME data cycles remaining to perform The proce
158. t 7 22 Addressed Interrupt 6 21 Addressed Interrupt 5 20 Addressed Interrupt 4 19 Addressed Interrupt 3 18 Addressed Interrupt 2 17 Addressed Interrupt 1 16 Addressed Interrupt 0 15 ACFAIL 14 SYSFAIL 13 11 Reserved 10 ALMA2e deassert BGLOCb 9 ALMA2e assert BGLOCb 8 EXCEPTION VME amp PCI See definition in the CSR USER DEF INT MSKFAIL register at address 1 0 74 End of DMAO 6 End of DMA1 5 21 Reserved 0 VME BUS Arbiter Time out The following registers have the same definition CSR USER DEF INT MSKOUTS at address 1E4 to mask source of interrupt to activate INT2b CSR USER DEF INT MSKOUTS at address 1E8 to mask source of interrupt to activate pin INT3b 12 10 03 Version 0 3 ALMA2e REGISTERS 2 101 ALMA2e User Manual IBM CSR USER DEF INT MSKFAIL Interrupt Mask FAIL Register Used for masking the individual source of VME PCI exception Address from PCI interface Config space not seen space PCIH BA1 SPACE 0 1 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x1E0 Width 32 Reset Value 0x00000000 Access type Read Write CSR USER DEF INT MSKFAIL 24 23 221 211201 19 18 17 16 1 5 141131 121 11 10 9 8 7 6 5 41 31 21 110 Bit s Description 23 22 Reserved Dma seq pcifailO 21 0 Maskis active 1 Maskis not active N Dma_seq_pcifail1
159. t of a PCI read access Read Ahead mode enabled or not and a VMEbus Error occurs Reserved Version 0 3 ALMA2e REGISTERS 2 47 ALMA2e User Manual 18 19 20 21 31 22 2 48 DMA seq vmefail channel 1 A VMEbus Error occurred during DMA Channel 1 DMA seq vmefail channel 0 A VMEbus Error occurred during DMA Channel 0 DMA seq channel 1 A PCI error occurred Target or Master Abort during DMA Channel 1 seq pcifail channel 0 A PCI error occurred Target or Master Abort during DMA Channel 0 Reserved 12 10 03 ALMA2e User Manual 2 0 4 ALMA2e VME Registers Address Size Name 0x48 4 bytes VME 5 0 3 0x70 1 bytes VME_REQ 0x71 1 bytes VME_ARB 0x72 1 bytes VME_TIM 0x73 1 bytes VME_MST 0x74 4 bytes VME SEMO 3 0x78 1 bytes VME SLVA Ox7A 1 bytes VME SLV 0 7 2 bytes VME PERF 0 7 4 bytes VME SLVA LEBE 0x80 8 bytes VME SLVO 0x88 8 bytes VME SLV1 0x90 8 bytes VME SLV2 0x98 8 bytes VME SLV3 0 0 8 bytes VME_SLV4 0 8 8 bytes VME SLV5 0 0 8 bytes VME SLV6 0xB8 8 bytes VME SLV7 12 10 03 Version 0 3 Use VME Semaphore Registers VME Request Control Register VME Bus Arbitration Control Register VME Data Transfer Timer Register VME Master Control Register VME Semaphore Registers VME Slave Channel A Address Register VME Slave Control Register VME Master Performance Control Register VME Slave Channel A Byte Ordering Control Reg VME Slave Channel 0 Control Register V
160. t size Others values 32 bytes burst size Note ALMA2e does not control boundary crossing 31 16 Reserved These bits are Read Write and have no functions Note If register CTL 0 is set to 0 Register CTL 31 0 must be left to 0 ALMA2e does not control boundary address crossing The software must take care to avoid access to forbidden region due to read ahead 12 10 03 Version 0 3 ALMA2e REGISTERS 2 83 ALMA2e User Manual IBM DRP CTL DMA Read PCI Control register Address from PCI interface Config space not seen space PCIH BA1 SPACE 0x108 Address from VME interface A16 space not seen A24 space CSR BAR USER 0x108 Width 32 Reset Value 0x00000000 Access type Read Write Recommended value 0x00002003 DRP CTL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 121111019 87 6 5 413211 Bit s Description PCI read burst length control Setto 0 the PCI burst length on PCI to VME DMA transaction is fixed and equal to 32 bytes setto 1 the PCI burst length on PCI to VME DMA transaction is programmable and given by DRP CTL 15 8 PCI read mode in VME 2eSST read transfer 1 set to 0 set to 1 the PCI read burst length is equal to the cycle count given by the VME 2esst DMA blocksize 2 7 Reserved This bits are read write and have no functions
161. t the effective state of the interrupt source This VME IACK cycle is characterized by the following The IACK signal is activated asserted low to notify al the VMEbus devices that the current cycle is an interrupt acknowledge cycle The level of the interrupt being acknowledged is encoded on address lines V A 3 1 The IACK signal is connected to daisy chain input V IACKINb VME IACKIN of the VMEbus arbiter module and is propagated by ALMA2e to the output V IACKOUTb VME IACKOUT of the daisy chain 30ns after receipt of V DSb 1 0 VME DS1 0 The daisy chain thus initiated by ALMA2e will be propagated by the other bus devices up to the interrupting device 6 4 2 Addressed Interrupts It is possible for the software to generate up to 8 level sensitive interrupts by writing from the VME or PCI ports to the IT_ADD_SET register These so called Addressed Interrupt sources are set active by writing a one to the bit position corresponding to desired the interrupt source number IT ADD SET 7 0 EE bit N20 gt Addressed Interrupt source number is not active bit N21 Addressed Interrupt source number N is active Addressed Interrupts 7 to 0 after masking are recorded into bits IT INT STATUS 23 16 respectively 6 142 12 10 03 ALMA2e User Manual IBM Bits to zero in the write data will not modify the corresponding register bits This register is readable from the VME or PCI ports RESET The second field of the register
162. ted by bits 5 3 encodings 001 to 111 respectively encoding 000 is Reserved 7 6 Reserved IT INT INT3b Interrupt pin is asserted upon activation of one interrupt sources among the 8 Addressed interrupt sources 0 10 8 to 7 The bits 10 8 are encoded from 000 to 111 such that only one Addressed interrupt can drive the INT3b signal The Address interrupts are generated by writing a 1 to bit 7 to 0 of the IT ADD SET 7 0 Reg ister IT INT MODE 0 P INTAb pin PCI INTA is asserted upon all interrupt sources H 1 INT1b INT2b INT3 pins are asserted upon those interrupt sources selected by IT INT INT1 2 3 above register fields INTAb pin PCI INTA is asserted upon interrupt sources not selected by the above register fields IT INT INT123 MODE if IT INT MODE 1 this bit has no effect 12 INT MODE 0 0 No interrupt asserted on pin INT1b 2b 3b 1 interrupt asserted on pin INT1b 2b 3b following the definition in registers CSR USER DEF INT MSKOUT1 2 3 and CSR USER DEF INT MSKFAIL Warning The Read of this bit returns always a 0 15 13 Reserved 2 74 12 10 03 ALMA2e User Manual IBM IT ADD SET Addressed Interrupt Register Address from PCI interface Config space not seen space PCIH BA1 SPACE OxEE Address from VME interface A16 space not seen A24 space CSR BAR USER OxEE Width 32 Reset Value 0x00000000 Access type Read Write 15 14 13 12111109 87 165 4 131210
163. tes that VMEbus is granted to the software which requested via the bit VME REQ LBR This interrupt after masking is recorded into bit 9 register IT INT STATUS VME amp PCI transfers errors this interrupt source is detected active when any one of the transfer errors recorded into the Error Status register bits 21 18 and 13 1 register UTIL ERRSTA 6C becomes true This interrupt after masking is recorded into bit 8 register IT INT STATUS End of DMA on Channel 0 detected internally signal seq finishO This interrupt after masking is recorded into bit 7 register IT INT STATUS End of DMA on Channel 1 detected internally signal seq finish This interrupt after masking is recorded into bit 6 register IT INT STATUS ALMA2e VME arbiter time out detected internally signal VME arb timeoutfail This interrupt source is detected active when the Error Status register bit 0 register UTIL ERRSTA 6 becomes true 12 10 03 Version 0 3 INTERRUPTS 6 143 ALMA2e User Manual IBM 65 VMEbus Interrupter 6 5 1 ALMA2e VME interrupt generation through Register IT IRQ GEN 7 0 A VME interrupt is issued when one of the 7 VMEbus signals IRQ7 IRQ1 is activated level 7 having the highest priority corresponding ALMA2e pins are V IRQo 7 1 asserted high The VME IRQ Generation register IT IRQ GEN which can be accessed by both the PCI and VME ports allows for generating one or several interrupts VME i
164. ther VMEbus or PCI bus 5 Reset Watchdog Time Out when ALMA2e Reset Watchdog timer times out 4 Addressed reset Depending upon which reset source is activated 2 takes one or several of the following reset actions Reset of ALMA2e internal logic Internal reset note that some registers can only be reset through pin POWER_ON_RESETb Generation of the VME system reset output pin V_SYSRESETo is asserted high e Generation of local board reset output pin RESETOUTDb is asserted low The following table describes how reset actions taken by ALMA2e are controlled Reset Source V SYSRESETo RESETOUTb Internal Reset POWER ON RESETb asserted asserted performed V SYSRESETib asserted performed asserted if RESETINb A MAAS IS System asserted performed Controller and UTIL_RST LOC2VME 1 poglesse diese aC Ber One 01 or 11 WEST 10 or 11 PIE Watchdog no action asserted performed The bit 8 of the UTIL VMECNTL Register is a Read only status bit UTIL SYSRESET ext that indicates to what state is the signal SYSRESET on the VMEbus Bit UTIL_VMECNTL Register address 0x68 8 UTIL SYSRESET ext bit 0 SYSRESET is inactive 1 SYSRESET is active ALMA2e is either generating V SYSRESEToO or receiving V SYSRESETib The Software PCI bus devices can check by testing this bit 8 that SYSRESET is active in order to avoid unsuccessfull access to the VMEbus while it is being initialized 12 10 03 Versi
165. thus has an effect on the data transfer rate 0 normal assertion of V DTACKob on Reads 1 fast assertion of V DTACKob on Reads Recommended setting is 1 VME SLV DTACKMSKPERF This bit operates on the DTACK de assertion timing on slave writes and thus has an effect on the data trans fer rate 0 normal De assertion of V DTACKob on Writes 1 fast De assertion of V DTACKob on Writes Recommended setting is 1 Reserved Must be left to zero otherwise ALMA2e behavior is unpredictable CR CSR EN was reserved in ALMA V64 0 only the ALMA V64 Registers can be accessed by the VME with type A16 AM Address Modifiers 1 Allthe ALMA2e s Registers can be accessed in mode CR CSR AM A24 AUTO SLOT ID was reserved in ALMA V64 Reflect signal value of AUTO SLOT ID Note In debug mode it could be interesting to set the VME SLV ABORT bit at 1 to avoid a Bus error generated on the VME bus which would result into an exception signaling on the board and a board reboot 2 56 12 10 03 ALMA2e User Manual IBM VME Master Performance Control Register Address from PCI interface Configuration space Ox7B space PCIH BA1 SPACE 0 7 Address from VME interface A16 space VME SLVA 0x7B A24 space CR CSR BAR USER 0x7B Width 8 Reset Value 0x00 Access type Read Write 716543210 Bit s Description VME ARB PERF This bit controls the number of clocks used to internally re s
166. ual IBM 2 Access to internal ALMA2e s registers ALMA2e Identifying on VME Access to internal registers On a VME A16 cycle ALMA2e identifies its internal registers of the configuration space are accessed when it decodes its VME Slave channel A address VME SLVA register as the target of that access All of the internal register set is accessible from VME bus via A24 CR CSR transaction ALMA2e Identifying on PCI Access to internal registers ALMA2e will respond to a PCI CONFIGURATION cycle ALMA2e is when its P IDSEL input pin is asserted high ALMA2e identifies its internal registers are accessed via a PCI I O cycle when it decodes its PCI Base Address Register no 1 PCIH 1 register as the target of the access Access to Reserved registers When PCI or VME access are performed on an internal Reserved register except otherwise noted ALMA2e returns a value 0 on a Read or takes no action external common behavior on a write 3 Accessing the Mapping Table The 1K entry PCI Mapping Table can be accessed via the 2 following internal registers Mapping Table index PCI RAM INDEX register counter which contains a Mapping Table entry address Mapping Table data PCI RAM DATA register virtual register a write or read access to that register address will make ALMA2e to load the write data or to return content at Mapping Table offset pointed by the PCI RAM INDEX register To access the Mapping table first the PCI RAM
167. vention In the following register description bit 0 is the least significant bit of the register It is composed of the ALMA2e Configuration Space Header for address offsets ranging from 0x00 to Ox3F and of the ALMA2e Configuration Space Specific for address offsets ranging from 0x40 to OxFF A VME master may access both spaces via VME A16 read write cycles A PCI master may access both spaces via PCI CONFIGURATION cycles and access only the ALMA2e Configuration Space Specific via PCI cycles this feature allows some PCI agents with no means to generate PCI CONFIGURATION cycles to access ALMA2e configuration registers too ALMA2e Extended Register Space A second register space called Extended Register Space provides access to all of the new registers CR CSR registers transaction flexibility registers ALMA2e CR CSR Configuration ROM Control Status Register Space This 512 KB register space is defined with a 8 0000 offset for PCI access E x00 Offset PCI Configuration Header Registers x40 ALMA2e PCI Operation Registers Configuration 64 Utility Operation Registers 256 Registers 70 VME Operation Registers Operation Registers x EO Interrupt Operation Registers X ros ul DERE x 100 ALMA2e Extended Register Space x1FC Figure 1 1 ALMA2e Configuration space and Extended Space Register 1 20 12 10 03 ALMA2e User Man
168. w level given in the register PCR CTL 11 8 1 Reserved This bit is Read Write and has no function Read ahead mode option setto 0 ALMA2e always gets a number of data equal to the PCI read burst size 2 setto 1 ALMA2e stops the PCI read burst as soon as ALMA2e detects that the transaction has already read 2 048 bytes Must be left to 0 7 3 Reserved These bits are Read Write and have no function PCI Low level Value if PCR CTL 0 is set to 1 0x0 PCI FIFO empty 0 1 less than 16 Bytes left in PCI FIFO 11 8 0 2 less than 32 Bytes left in PCI FIFO Ox3 less than 48 Bytes left in PCI FIFO Oxn lessthan 16 x n Bytes left in PCI FIFO OxF less than 256 Bytes left in PCI FIFO 31 12 Reserved This bits are read write and have no functions Note If register CTL 0 is set to 0 the register CTL 31 0 must be left to 0 ALMA2e does not control boundary address crossing The software must take care to avoid access to forbidden region due to Read ahead 12 10 03 Version 0 3 ALMA2e REGISTERS 2 85 ALMA2e User Manual IBM PSR CTL PCI Slave Read Control register This register controls PCI to VME read transfers Address from PCI interface Config space not seen IO space PCIH BA1 SPACE 0x110 Address from VME interface A16 space not seen A24 space CSR BAR USER CSR 0x110 Width 32 Reset Value 0x00000000 Access type Read Write Recommended value 0x00000000 PSR CTL 31 30
169. xtra function mask this feature is not used in ALMA2e 25 EFD Extra function decoder 1 the next ADEM provides another decoder for the same function rather than another function 26 DFS Dynamic Function Sizing 1 the mask bits above are not valid because the function s size is dynamic 27 FAF Fixed Address function 1 the function s ADER is not programmable 31 28 Reserved These bits are reserved and return zeros when read 2 114 12 10 03 ALMA2e User Manual IBM Chapter 3 SIGNAL DESCRIPTIONS Signal notational conventions b symbol at the end of a signal name denotes that the active state occurs when the signal is at the low voltage When no b symbol is present the signal is active high i Input signal notation used when a VME standard bidirectional signal defines input and output signals 0 Output signal notation used when a VME standard bidirectional signal defines input and output signals Signal Type Definition The following signal type definitions are taken from Revision 2 2 of the PCI local bus specifica tion 6 Tri State amp is a bidirectional tri state input output pin s t s Sustained Tri State is an active low tri state signal owned and driven by one and only one agent at a time The agent that drives an s t s pin low must drive it high for at least one clock before letting it float A new agent cannot start driving a s t s signal any sooner than one clockafter the previous owner tri
170. ynchronize the BGIN3 0 daisy chains signals 0 0 V BGIND 3 0 input signals are re synchronized with 2 clocks 1 BGIND S3 0 input signals are re synchronized with 1 clock Recommended setting is 0 1 Reserved Must be held to zero otherwise ALMA2e behavior is unpredictable VME MST FIRSTPERF This bit controls AS assertion timing on master writes and thus has an effect on the data transfer rate 2 0 normal assertion of the first V ASb on Writes 1 fast assertion of the first V ASb on Writes Recommended setting is 1 VME MST DS021PERF This bit controls DS1 0 de assertion timing on master reads and thus has an effect on the data transfer rate 3 0 normal de assertion of V DSb 1 0 on Reads 1 fast de assertion of V DSb 1 0 on Reads Recommended setting is 1 VME MST DS120PERF This bit controls DS1 0 assertion timing on master writes and thus has an effect on the data transfer rate 4 0 normal assertion of V DSb 1 0 on Writes 1 fast assertion of V DSb 1 0 on Writes Recommended setting is 1 5 6 Reserved Must be held to zero otherwise ALMA2e behavior is unpredictable Reserved 12 10 03 Version 0 3 ALMA2e REGISTERS 2 57 ALMA2e User Manual VME SLVA LEBE VME Slave Channel A Byte Ordering Control Registers Address from PCI interface Address from VME interface Configuration space 0 7 space PCIH BA1 SPACE 0x7C A16 space VME SLVA 0 7 A24 space CSR BAR USER CSR 0x7C
171. zeros when read 31 PCI CFGADD EN PCI Configuration Enable 2 38 12 10 03 ALMA2e User Manual IBM PCI CFGDATA PCI Configuration Address register Address from PCI interface Config space 0x50 space BA1 SPACE 0x50 Address from VME interface A16 space VME SLVA 0x50 A24 space BAR USER CSR 0x50 Width 32 Reset Value None Virtual register Access type Read Write PCI CFGDATA 31 30 29 28 27 26 25 24 23 22 21 201 19 18 17 16 1 5 141 13 121 11 10 9 8 7 6 51 141 3121 1 Bit s Description PCI CFGDATA Virtual register A Read or Write to this register from the VME bus results in a PCI Configuration cycle read or write initiated by ALMA2e with the address defined in register CFGADD Note A read from the PCI to this register returns 0 a write from the PCI to this register has no effect 31 0 PCI INTACK SPECIAL PCI Interrupt Acknowledge Special Cycle register Address from PCI interface Config space 0x54 space PCIH BA1 SPACE 0x54 Address from VME interface A16 space VME SLVA 0x54 A24 space BAR USER 0x54 Width 32 Reset Value None Virtual register Access type Read Write PCI INTACK SPECIAL 31 30 29 28 27 261 25 241 23 221211 201 19 181 17 16 15 141 13 1211

ALMA2e PCI/VME 2eSST Bridge User Manual

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