CAN – Beschreibung
Contents
1. Infineon inrineon C1 64 Group The On Chip CAN Interface 19 The On Chip CAN Interface The Controller Area Network CAN bus with its associated protocol allows communication between a number of stations which are connected to this bus with high efficiency Efficiency in this context means Transfer speed Data rates of up to 1 Mbit sec can be achieved Data integrity The CAN protocol provides several means for error checking Host processor unloading The controller here handles most of the tasks autonomously Flexible and powerful message passing The extended CAN protocol is supported The integrated CAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active i e the on chip CAN module can receive and transmit Standard frames with 11 bit identifiers as well as Extended frames with 29 bit identifiers Note The CAN module is an XBUS peripheral and therefore requires bit XPEN in register 5 YSCON to be set in order to be operable Core Registers Control Registers Object Registers Interrupt Control ODP4 E ODP8 E SYSCONSystem Configuration Register CSR Control Status Register SYSCON3Peripheral Management Control Register PCIR Port Control Interrupt Register DP4 Port 4 Direction Control Register BTR Bit Timing Register ODP4 Port 4 Open Drain Control Register GMS Global Mask Short DP8 Port 8 Direction C2. User s Manual 19 16 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface 19 3 The Message Object The message object is the primary means of communication between CPU and CAN controller Each of the 15 message objects uses 15 consecutive bytes see map below and starts at an address that is a multiple of 16 Note All message objects must be initialized by the CPU even those which are not going to be used before clearing the INIT bit Offset Message Control MCR 0 Object Start Address EFn0 2 Arbitration UAR amp LAR i 4 Message object 1 EF10 6 Message object 2 EF20y Message object 14 EFEO Message object 15 EFFO The general properties of a message object are defined via the Message Control Register MCR There is a dedicated register MCRn for each message object n Each element of the Message Control Register is made of two complementary bits This special mechanism allows the selective setting or resetting of specific elements leaving others unchanged without requiring read modify write cycles None of these elements will be affected by reset The table below shows how to use and interpret these 2 bit fields User s Manual 19 17 1999 09 pee Infineon technologies C164 Group The On Chip CAN Interface XReg EFn0j Reset value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1d 0 R
3. CPUUPD 1 15 14 13 12 11 10 9 8 7 6 5 4 01 01 10 01 10 01 01 01 RMTPND T XRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND MCR Remote frame was received in the meantime gt RMTPND 1 TXRQ 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10 10 10 01 10 01 01 01 RMTPND TXRHG CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND After updating the message the CPU should clear CPUUPD and set NEWDAT The previously received remote request will then be answered If the CPU wants to transmit the message actively it should also set TXRQ which should otherwise be left alone User s Manual 19 33 1999 09 Infineon technologies Configuration Example of a Reception Object C164 Group The On Chip CAN Interface This object shall be configured for reception A receive interrupt shall be generated each time new data comes in From time to time the CPU sends a remote request to trigger the sending of this data from a remote node MCR Message object is idle i e waiting for a frame to be received 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 01 01 01 01 10 01 10 01 RMTPND TXRQ MSGLST NEWDAT MSGVAL TXE RXIE _ INTPND MCR A data frame was received gt NEWDAT 1 INTPND
4. message is actually being transmitted during the time the message was being updated by the CPU the CAN controller will not reset bit TXRQ In this way bit TXRQ is only reset once the actual data has been transferred 3 When the CPU requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted if bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first This arbitration is done when several objects are requested for transmission by the CPU or when operation is resumed after an error frame or after arbitration has been lost Arbitration Registers The Arbitration Registers UARn amp LARn are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages A received message with a matching identifier is accepted as a data frame matching object has DIR 0 or as a remote frame matching object has DIR 1 For matching the corresponding Global Mask has to be considered in case of message object 15 also the Mask of Last Message Extended frames using Global Mask Long can be stored only in message objects with XTD 1 standard frames using Global Mask Short only in mess
5. 1 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 10 10 01 10 10 RMTPND TXHGQ MSGLST NEWDAT MSGVAL TXIE RXIE INTPND To process the message the CPU should clear INTPND and NEWDAT process the data and check that NEWDAT is still clear after that If not the processing should be repeated To send a remote frame to request the data simply bit TXRQ needs to be set This bit will be cleared by the CAN controller once the remote frame has been sent or if the data is received before the CAN controller could transmit the remote frame User s Manual 19 34 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface 19 6 The CAN Application Interface The on chip CAN module of the C164 is connected to the external physical layer i e the CAN bus via two signals Table 19 2 CAN Interface Signals CAN Signal Port Pin Function CAN RXD Controlled via Receive data from the physical layer of the CAN bus CAN TXD C1PCIR IPC Transmit data to the physical layer of the CAN bus A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level Connection to an External Transceiver The CAN module of the C164 can be connected to an external CAN bus via a CAN transceiver Note Basically it is also possible to connect several CAN modules directly on board without using CAN transceivers CAN RXD CAN Tran
6. Definition The bit time is determined by the XBUS clock period t and the number of time quanta per bit XCLKC the Baud Rate Prescaler bit time ISync Seg t IrSegi ITSega Ioync Seg t b b o TSEG1 1 3 bel TSEG2 1 i 1 ee z ty BRP 1 2 b CLK Note TSEG1 TSEG2 and BRP are the programmed numerical values from the respective fields of the Bit Timing Register User s Manual 19 11 1999 09 Infineon technologies C164 Group The On Chip CAN Interface Bit Timing Register XReg EF04 Reset value UUUU Hard Synchronization and Resynchronization To compensate phase shifts between clock oscillators of different CAN controllers any CAN controller has to synchronize on any edge from recessive to dominant bus level if the edge lies between a Sample Point and the next Synchronization Segment and on any other edge if it itself does not send a dominant level If the Hard Synchronization is enabled at the Start of Frame the bit time is restarted at the Synchronization Segment otherwise the Resynchronization Jump Width SJW defines the maximum number of time quanta by which a bit time may be shortened or lengthened during one Resynchronization The current bit time is adjusted by Note SJW is the programmed numerical value from the respective field of the Bit Timing Register User s Manual 19 12 1999 09 Infineon technologies
7. Global Mask Long UGML amp LGML Bits holding a 0 mean don t care i e do not compare the message s identifier in the respective bit position The last message object 15 has an additional individually programmable acceptance mask Mask of Last Message UMLM amp LMLM for the complete arbitration field This allows classes of messages to be received in this object by masking some bits of the identifier Note The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message Global Mask Short XReg EF06 Reset value UFUU User s Manual 19 15 1999 09 pe Infineon inrineon C1 64 Group The On Chip CAN Interface UGML Upper Global Mask Long XReg EF08 Reset value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 13 ID28 21 AW nw LGML Lower Global Mask Long XReg EF0A Reset value UUUUg 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDA 0 0 0 0 ID12 5 rw r r r rw Bit Function 1D28 0 Identifier 29 bit Mask to filter incoming messages with extended identifier D XReg EFOC Reset value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 ID17 13 ID28 21 rw rw rw SED XReg EFOE Reset value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDA 0 0 0 0 ID12 5 w r r r rw
8. no other interrupt request with a higher priority Example message 1 INTID 03 4 message 14 INTID 10 IPC Interface Port Control reset value 111g i e no port connection The encoding of bitfield IPC is described in section The CAN Application Interface Note Bitfield IPC can be written only while bit CCE is set 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to 00 idle state User s Manual 19 10 1999 09 Infineon technologies Configuration of the Bit Timing C164 Group The On Chip CAN Interface According to the CAN protocol specification a bit time is subdivided into four segments Sync segment propagation time segment phase buffer segment 1 and phase buffer segment 2 o 1 CPS Each segment is a multiple of the time quantum t with tj BRP 1 CLK The Synchronization Segment Sync Seg is always 1 f long The Propagation Time Segment and the Phase Buffer Segment 1 combined to TSeg1 define the time before the sample point while Phase Buffer Segment 2 TSeg2 defines the time after the sample point The length of these segments is programmable except Sync Seg via the Bit Timing Register BTR Note For exact definition of these segments please refer to the CAN Protocol Specification sample point transmit point 1 time quantum Figure 19 4 Bit Timing
9. the BTL depends on the baudrate and on external physical delay times Intelligent Memory The Intelligent Memory CAM RAM Array provides storage for up to 15 message objects of maximum 8 data bytes length Each of these objects has a unique identifier and its own set of control and status bits After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further CPU actions Organization of Registers and Message Objects All registers and message objects of the CAN controller are located in the special CAN address area of 256 bytes which is mapped into segmentO and uses addressesOO EF00 through 00 EFFFy All registers are organized as 16 bit registers located on word addresses However all registers may be accessed bytewise in order to select special actions without effecting other mechanisms Register Naming reflects the specific name of a register as well as a general module indicator This results in unique register names Example module indicator is C1 CAN module 1 specific name is Control Status Register CSR unique register name is C1CSR Note The address map shown below lists the registers which are part of the CAN controller There are also C164 specific registers that are associated with the CAN module User s Manual 19 5 1999 09 Infineon technologies User s Manual C164 Group General Registers Message Object 1 Message Object 2 Message O
10. 5 1999 09 Infineon ies reus The On Chip CAN Interface Power Up all bits undefined TXIE application specific RXIE application specific INTPNDd 0 RMTPND 0 TXRQ 0 MSGLST 0 Identifier application specific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application specific Initialization NEWDAT 0 Process Start process message contents Process End lt tr a Process no request update Process Figure 19 9 CPU Handling of Receive Objects DIR 0 User s Manual 19 26 1999 09 Infineon ies reus The On Chip CAN Interface Power Up all bits undefined RXIE application specific INTPND 0 RMTPND 0 MSGLST 0 Identifier application specific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application specific Initialization Process Start process message contents NEWDAT 0 Process Process End Restart Process Figure 19 10 CPU Handling of the Last Message Object User s Manual 19 27 1999 09 Infineon Inrineon C1 64 Group The On Chip CAN Interface CPU releases Buffer 2 CPU releases Buffer 1 Buffer 1 released Buffer 2 released CPU access to Buffer 2 CPU allocates Buffer 2 Store received Message into Buffer 1 Buffer 1 released Buffer 1 allocated
11. Buffer 2 allocated Buffer 2 released CPU access to Buffer 2 CPU access to Buffer 1 Store received Store received Message Message into Buffer 1 into Buffer 2 Buffer 1 allocated Buffer 1 allocated Buffer 2 allocated Buffer 2 allocated CPU access to Buffer 2 CPU access to Buffer 1 Store received CPU releases CPU releases Store received message into Buffer 2 Buffer 1 message into Buffer 1 Buffer 2 MSGLST is set MSGLST is set Allocated NEWDAT 1 OR RMTPND 1 Released NEWDAT 0 AND RMTPND 0 Figure 19 11 Handling of the Last Message Object s Alternating Buffer User s Manual 19 28 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface 19 4 Controlling the CAN Module The CAN module is controlled by the C164 via hardware signals e g reset and via register accesses executed by software Accessing the On chip CAN Module The CAN module is implemented as an X Peripheral and is therefore accessed like an external memory or peripheral That means that the registers of the CAN module can be read and written using 16 bit or 8 bit direct or indirect MEM addressing modes Also bit handling is not supported via the XBUS Since the XBUS to which the CAN module is connected also represents the external bus CAN accesses follow the same rules and procedures as accesses to the external bus CAN accesses cannot be executed in parallel to external instruction fetches or data read writes but are arbitr
12. C164 Group The On Chip CAN Interface Calculation of the Bit Time The programming of the bit time according to the CAN Specification depends on the desired baudrate the XCLK frequency and on the external physical delay times of the bus driver of the bus line and of the input comparator These delay times are summarized in the Propagation Time Segment tProp Where tProp is two times the maximum of the sum of physical bus delay the input comparator delay and the output driver delay rounded up to the nearest multiple of tg To fulfill the requirements of the CAN specification the following conditions must be met HSeg2 2 2 1 Information Processing Time TSeg2 suw fTseg1 Z 3 q Segi feJw Prop Note In order to achieve correct operation according to the CAN protocol the total bit time should be at least 8 tg i e TSEG1 TSEG2 2 5 So to operate with a baudrate of 1 MBit sec the XCLK frequency has to be at least 8 16 MHz depending on the prescaler control bit CPS in register CSR The maximum tolerance df for XCLK depends on the Phase Buffer Segment 1 PB1 the Phase Buffer Segment 2 PB2 and the Resynchronization Jump Width SJW min PB1 PB2 d m EN A 2 X 13 X bittime PB2 AND tSJW df E m 20 X bit time The examples below show how the bit timing is to be calculated under specific circumstances User s Manual 19 13 1999 09 ineon Infineon ies Gros The On Chip CAN Interfa
13. CAN Module Activation After a reset the CAN module is disabled Before it can be used to receive or transmit messages the application software must activate the CAN module Three actions are required for this purpose General Module Enable globally activates the CAN module This is done by setting bit XPEN in register SYSCON Pin Assignment selects a pair of port pins that connect the CAN module to the external transceiver This is done via bitfield IPC in register PCIR Module Initialization determines the functionality of the CAN module baudrate active objects etc This is the major part of the activation and is described in the following User s Manual 19 30 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface Module Initialization The module initialization is enabled by setting bit INIT in the control register CSR This can be done by the CPU via software or automatically by the CAN controller on a hardware reset or if the EML switches to busoff state While INIT is set all message transfer from and to the CAN bus is stopped the CAN transmit line CAN TXD is 1 recessive the control bits NEWDAT and RMTPND of the last message object are reset e the counters of the EML are left unchanged Setting bit CCE in addition permits changing the configuration in the Bit Timing Register To initialize the CAN Controller the following actions are required configure the Bit
14. MTPND TxRQ MSGUST NEWDAT MSGVAL TXIE RXIE INTPND rw rw rw rw rw rw rw rw Bit Function INTPND Interrupt Pending Indicates if this message object has generated an interrupt request see TXIE and RXIE since this bit was last reset by the CPU or not RXIE Receive Interrupt Enable Defines if bit INTPND is set after successful reception of a frame TXIE Transmit Interrupt Enable Defines if bit INTPND is set after successful transmission of a frame 1 MSGLST Message Lost This bit applies to receive objects only Indicates that the CAN controller has stored a new message into this object while NEWDAT was still set i e the previously stored message is lost User s Manual 19 18 1999 09 technologies C164 Group The On Chip CAN Interface Bit Function In message object 15 last message these bits are hardwired to 0 inactive in order to prevent transmission of message 15 2 When the CAN controller writes new data into the message object unused message bytes will be overwritten by non specified values Usually the CPU will clear this bit before working on the data and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the CPU will set this bit along with clearing bit CPUUPD This will ensure that if the
15. Timing Register CCE required set the Global Mask Registers initialize each message object If a message object is not needed it is sufficient to clear its message valid bit MSGVAL i e to define it as not valid Otherwise the whole message object has to be initialized After the initialization sequence has been completed the CPU clears bit INIT Now the BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits i e Bus Idle before it can take part in bus activities and start message transfers The initialization of the message objects is independent of the state of bit INIT and can be done on the fly The message objects should all be configured to particular identifiers or set to not valid before the BSP starts the message transfer however To change the configuration of a message object during normal operation the CPU first clears bit MSGVAL which defines it as not valid When the configuration is completed MSGVAL is set again User s Manual 19 31 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface Busoff Recovery Sequence If the device goes busoff it will set bit BOFF and also set bit INIT of its own accord stopping all bus activities To have the CAN module take part in the CAN bus activities again the bus off recovery sequence must be started by clearing the bit INIT via software Once INIT has b
16. age objects with XTD 0 Message objects should have unique identifiers i e if some bits are masked out by the Global Mask Registers i e don t care then the identifiers of the valid message objects should differ in the remaining bits which are used for acceptance filtering If a received message data frame or remote frame matches with more than one valid message object it is associated with the object with the lowest message number l e a received data frame is stored in the lowest object or the lowest object is sent in response to a remote frame The Global Mask is used for matching here User s Manual 19 19 1999 09 pee Infineon Inrineon C1 64 Group The On Chip CAN Interface After a transmission data frame or remote frame the transmit request flag of the matching object with the lowest message number is cleared The Global Mask is not used in this case When the CAN controller accepts a data frame the complete message is stored into the corresponding message object including the identifier also masked bits standard identifiers have bits ID17 0 filled with 0 the data length code DLC and the data bytes valid bytes indicated by DLC This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used When the CAN controller accepts a remote frame the corresponding transmit message object 1 14 remains unchanged except for bits TXRQ
17. and RMTPND which are set of course In the last message object 15 which cannot start a transmission the identifier bits corresponding to the don t care bits of the Last Message Mask are copied from the received frame Bits corresponding to the don t care bits of the corresponding global mask are not copied i e bits masked out by the global and the last message mask cannot be retrieved from object 15 Upper Arbitration Register XReg EFn2 Reset value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 ID17 13 ID28 21 l l l i l rw rw Lower Arbitration Register XReg EFn4y Reset value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function User s Manual 19 20 1999 09 pee Infineon inrineon C1 64 Group The On Chip CAN Interface Message Configuration The Message Configuration Register low byte of MCFGn holds a description of the message within this object Note There is no don t care option for bits XTD and DIR So incoming frames can only match with corresponding message objects either standard XTD 0 or extended XTD 1 Data frames only match with receive objects remote frames only match with transmit objects When the CAN controller stores a data frame it will write all the eight data bytes into a message object If the data length code was less than 8 the remaining bytes of the message object will be overwritten by non specifie
18. ated and inserted into the external bus access stream Accesses to the CAN module use demultiplexed addresses a 16 bit data bus byte accesses possible two waitstates and no tristate waitstate The CAN address area starts at 00 EFOO and covers 256 Bytes This area is decoded internally so none of the programmable address windows must be sacrificed in order to access the on chip CAN module The advantage of locating the CAN address area in segment 0 is that the CAN module is accessible via data page 3 which is the system data page accessed usually through the system data page pointer DPP3 In this way the internal addresses such like SFRs internal RAM and the CAN registers are all located within the same data page and form a contiguous address space Power Down Mode If the C164 enters Power Down mode the XCLK signal will be turned off which will stop the operation of the CAN module Any message transfer is interrupted In order to ensure that the CAN controller is not stopped while sending a dominant level 0 on the CAN bus the CPU should set bit INIT in the Control Register prior to entering Power Down mode The CPU can check if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register After returning from Power Down mode via hardware reset the CAN module has to be reconfigured User s Manual 19 29 1999 09 Infineon technologies C164 G
19. bject 3 Message Object 4 Message Object 5 Message Object 6 Message Object 7 Message Object 8 Message Object 9 Message Object 10 Message Object 11 Message Object 12 Message Object 13 Message Object 14 Message Object 15 CAN Address Area The On Chip CAN Interface Control Status Register CSR Port Ctrl Interrupt Reg PCIR Bit Timing Register BTR Global Mask Short GMS Global Mask Long LGML UGML Mask of Last Message LMLM UMLM General Registers 1999 09 Infineon technologies 19 2 The Control Status Register CSR accepts general control settings for the module and provides general status information C164 Group The On Chip CAN Interface General Functional Description CSR Control Status Register XReg EF00 Reset value XX01 15 14 13 12 11 10 9 7 6 4 3 2 1 0 B E RX TX OFF WRN OK OK LEC TM CCE CPS EIE SIE IE INIT rh rh r rwh rwh rwh rw rw rw rw rw rw rwh IE Interrupt Enable Enables or disables interrupt generation from the CAN module via the signal XINTR Does not affect status updates SIE Status Change Interrupt Enable Enables or disables interrupt generation when a message transfer reception or transmission is successfully completed or a CAN bus error is detected and registered in the status partition EIE Error Interrupt Enable Enables or disables interrupt generation on a c
20. bus value was dominant BitOError During the transmission of a message or acknowledge bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicates that the bus is not stuck at dominant or continously disturbed CRCError The received CRC check sum was incorrect Unused code may be written by the CPU to check for updates A C1 M O EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96 BOFF Busoff Status Indicates when the CAN controller is in busoff state see EML Note Reading the upper half of the Control Register status partition will clear the Status Change Interrupt value in the Interrupt Register if it is pending Use byte accesses to the lower half to avoid this User s Manual 19 8 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface CAN Interrupt Handling The on chip CAN module has one interrupt output which is connected through a synchronization stage to a standard interrupt node in the C164 in the same manner as all other interrupts of the standard on chip peripherals With this configuration the user has all contr
21. ce Bit Timing Example for High Baudrate This example makes the following assumptions XCLK frequency 20 MHz BRP 00 CPS 0 Baudrate 1 Mbit sec lq 100 ns 22 txcLK bus driver delay 50 ns receiver circuit delay 30 ns bus line 40 m delay 220 ns tProp 600ns 6 f fSJW 100ns 1 ft4 TSeg1 700nS fprop fsuw tTSeg2 200 ns Information Processing Time Sync 100ns c z1 1q fgit 1000 NS fgync frSegt frSeg2 min PB1 PB2 tolerance for fkci 0 39 2x 13xbittime PB2 O lus 2x 13 x lus 0 2us Bit Timing Example for Low Baudrate This example makes the following assumptions XCLK frequency 4 MHz BRP 01 CPS 20 Baudrate 100 kbit sec tq 1 us 4 fxcLk bus driver delay 200 ns receiver circuit delay 80 ns bus line 40 m delay 220 ns Prop 1us 1 fq IsJw 4us 4 t ITSeg1 5 us Prop fSJW tTSeg2 4 us Information Processing Time 2 tg Sync 1 us 1 Ig fgit 10uS fgync fTSeg1 fTSeg2 min PB1 PB2 tolerance for fci 1 58 2x 13x bit time PB2 4us 2x 13 x 10us 4us User s Manual 19 14 1999 09 Infineon technologies C164 Group The On Chip CAN Interface Mask Registers Messages can use standard or extended identifiers Incoming frames are masked with their appropriate global masks Bit IDE of the incoming message determines if the standard 11 bit mask in Global Mask Short GMS is to be used or the 29 bit extended mask in
22. d values Message Configuration Reg XReg EFn6 Reset value UU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DLC DIR XTD 0 0 rw rw rw r r 2 Function User s Manual 19 21 1999 09 Infineon nrineon C1 64 Group The On Chip CAN Interface Data Area The data area occupies 8 successive byte positions after the Message Configuration Register i e the data area of message object n covers locations 00 EFn7 through O0 EFnE Location OO0 EFnF is reserved Message data for message object 15 last message will be written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the CPU has read the first one Handling of Message Objects The following diagrams summarize the actions that have to be taken in order to transmit and receive messages over the CAN bus The actions taken by the CAN controller are described as well as the actions that have to be taken by the CPU i e the servicing program The diagrams show e CAN controller handling of transmit objects CAN controller handling of receive objects CPU handling of transmit objects CPU handling of receive objects CPU handling of last message object e Handling of the last message s alternating buffer User s Manual 19 22 1999 09 Infineon TES reus The On Chip CAN Interface recei
23. een cleared the module will then wait for 129 occurrences of Bus ldle before resuming normal operation At the end of the busoff recovery sequence the Error Management Counters will be reset This will automatically clear bits BOFF and EWRN During the waiting time after the resetting of INIT each time a sequence of 11 recessive bits has been monitored a BitOError code is written to the Control Register enabling the CPU to check up whether the CAN bus is stuck at dominant or continously disturbed and to monitor the proceeding of the busoff recovery sequence Note An interrupt can be generated when entering the busoff state if bits IE and EIE are set The corresponding interrupt code in bitfield INTID is 01 p The busoff recovery sequence cannot be shortened by setting or resetting INIT User s Manual 19 32 1999 09 Infineon technologies 19 5 The two examples below represent standard applications for using CAN messages Both examples assume that identifier and direction are already set up correctly The respective contents of the Message Control Register MCR are shown C164 Group The On Chip CAN Interface Configuration Examples for Message Objects Configuration Example of a Transmission Object This object shall be configured for transmission It shall be transmitted automatically in response to remote frames but no receive interrupts shall be generated for this object MCR Data bytes are not written completely gt
24. hange of bit BOFF or EWARN in the status partition CPS Clock Prescaler Control Bit 0 Standard mode the input clock is divided 2 1 The minimum input frequency to achieve a baudrate of 1 MBaud is f py 16 MHz 1 Fast mode the input clock is used directly 1 1 The minimum input frequency to achieve a baudrate of 1 MBaud is fcpy 8 MHz TM Test Mode must be 0 Make sure that this bit is always cleared when writing to the Control Register as this bit controls a special test mode that is used for production testing During normal operation however this test mode may lead to undesired behaviour of the device User s Manual 19 7 1999 09 pee Infineon Inrineon C1 64 Group The On Chip CAN Interface Bit Function Status Bits LEC Last Error Code This field holds a code which indicates the type of the last error occurred on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared 0 No Error 1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed 2 Form Error Wrong format in fixed format part of a received frame 3 AckError The message this CAN controller transmitted was not acknowledged by another node Bit1Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level 1 but the monitored
25. makes it easy to use User s Manual 19 2 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface Tx Rx Shift Register The Transmit Receive Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor The Bit Stream Processor BSP is a sequencer controlling the sequential data stream between the Tx Rx Shift Register the CRC Register and the bus line The BSP also controls the EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP Cyclic Redundancy Check Register This register generates the Cyclic Redundancy Check CRC code to be transmitted after the data bytes and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic The Error Management Logic EML is responsible for the fault confinement of the CAN device Its counters the Receive Error Counter and the Transmit Error Counter are incremented and decremen
26. mbination 111 Idle Disconnected No port assigned Default after Reset recessive 1 This assignment is compatible with previous derivatives where the assignment of CAN interface lines was fixed User s Manual 19 36 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface The location of the CAN interface lines can now be selected via software according to the requirements of an application Compatible Assignment IPC 000g makes the C164 suitable for applications with a given hardware board layout The CAN interface lines are connected to the port pins to which they are hardwired in previous derivatives Full Address Assignment IPC 010g or 011g removes the CAN interface lines completely from Port 4 The maximum external address space of 4 MByte is available in this case The CAN interface lines are mapped to Port 8 Two pairs of Port 8 pins can be selected No Assignment IPC 111g disconnects the CAN interface lines from the port logic This avoids undesired currents through the interface pin drivers while the C164 is in a power saving state After reset the CAN interface lines are disconnected Note Assigning CAN interface signals to a port pin overrides the other alternate function of the respective pin segment address on Port 4 CAPCOM lines on Port 8 User s Manual 19 37 1999 09
27. ol options available for this interrupt such as enabling disabling level and group priority and interrupt or PEC service see note below The on chip CAN module is connected to an XBUS interrupt control register As for all other interrupts the node interrupt request flag is cleared automatically by hardware when this interrupt is serviced either by standard interrupt or PEC service Note As a rule CAN interrupt requests can be serviced by a PEC channel However because PEC channels only can execute single predefined data transfers there are no conditional PEC transfers PEC service can only be used if the request is known to be generated by one specific source and that no other interrupt request will be generated in between In practice this seems to be a rare case Since an interrupt request of the CAN module can be generated due to different conditions the appropriate CAN interrupt status register must be read in the service routine to determine the cause of the interrupt request The interrupt identifier INTID a number in the Port Control Interrupt Register PCIR indicates the cause of an interrupt When no interrupt is pending the identifier will have the value 00y If the value in INTID is not 00 then there is an interrupt pending If bit IE in the control status register is set also the interrupt signal to the CPU is activated The interrupt signal to the interrupt node remains active until INTID gets 00 i e all inter
28. ontrol Register U LGML Global Mask Long ODP8 Port 8 Open Drain Control Register U LMLM Last Message Mask XPOIC CAN1 Interrupt Control Register MCHn Configuration Register of Message n U LARn Arbitration Register of Message n Figure 19 1 Registers Associated with the CAN Module User s Manual 19 1 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud The minimum CPU clock frequency to achieve 1 MBaud is fcpy 2 8 16 MHz depending on the activation of the CAN module s clock prescaler The CAN module uses two pins of Port 4 or Port 8 to interface to a bus transceiver It provides Full CAN functionality on up to 15 full sized message objects 8 data bytes each Message object 15 may be configured for Basic CAN functionality with a double buffered receive object Both modes provide separate masks for acceptance filtering which allows the acceptance of a number of identifiers in Full CAN mode and also allows disregarding a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects during operation of the module and are equipped with buffers for the maximum message length of 8 bytes 19 1 Functional Blocks of the CAN Module The CAN module combines several functional blocks see figure below that work in parallel and contribute to the controllers performance These uni
29. required restricting CPU accesses to the CAN module until the anticipated updating is complete PCIR Port Control Interrupt Register XReg EF024 Reset value XXXXy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IPC INTID 1 AV rh Bit Function INTID Interrupt Identifier This number indicates the cause of the interrupt if pending 004 Interrupt Idle There is no interrupt request pending 014 Status Change Interrupt The CAN controller has updated not necessarily changed the status in the Control Register This can refer to a change of the error status of the CAN controller EIE is set and BOFF or EWRN change or to a CAN transfer incident SIE must be set like reception or transmission of a message RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The CPU may clear RXOK TXOK and LEC however writing to the status partition of the Control Register can never generate or reset an interrupt To update the INTID value the status partition of the Control Register must be read 024 Message 15 Interrupt Bit INTPND in the Message Control Register of message object 15 last message has been set The last message object has the highest interrupt priority of all message objects 02 N Message N Interrupt Bit INTPND in the Message Control Register of message object N has been set N 1 14 Note that a message interrupt code is only displayed if there is
30. roup The On Chip CAN Interface Disabling the CAN Module When the CAN module is disabled by setting bit CANDIS in register SYSCON3 peripheral management no register accesses are possible Also the module s logic blocks are stopped and no CAN bus transfers are possible After re enabling the CAN module CANDIS 0 it must be reconfigured as after returning from Power Down mode Note Incoming message frames can still be recognized not received in this case by monitoring the receive line CAN RXD For this purpose the receive line CAN RXD can be connected to a fast external interrupt via register EXISEL CAN Module Reset The on chip CAN module is connected to the XBUS Reset signal This signal is activated when the C164 s reset input is activated when a software reset is executed and in case of a watchdog reset Activating the CAN module s reset line triggers a hardware reset This hardware reset disconnects the CAN TXD output from the port logic clears the error counters resets the busoff state e switches the Control Register s low byte to 014 leaves the Control Register s high byte and the Interrupt Register undefined does not change the other registers including the message objects notified as UUUU Note The first hardware reset after power on leaves the unchanged registers in an undefined state of course The value 01 in the Control Registers low byte prepares for the module initialization
31. rupt requests have been serviced or until interrupt generation is disabled CSR IE 0 Note The interrupt node is activated only upon a 0 1 transition of the CAN interrupt signal The CAN interrupt service routine should only be left after INTID has been verified to be 00 The interrupt with the lowest number has the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one INTID is also updated when the respective source request has been processed This is indicated by clearing the INTPND flag in the respective object s message control register MCRn or by reading the status partition of register CSR in case of a status change interrupt The updating of INTID is done by the CAN state machine and takes up to 6 CAN clock cycles 1 CAN clock cycle 1 or 2 CPU clock cycles determined by the prescaler bit CPS depending on current state of the state machine Note A worst case condition can occur when BRP 00 AND the CAN controller is storing a just received message AND the CPU is executing consecutive accesses to the CAN module In this rare case the maximum delay may be 26 CAN clock cycles The impact of this delay can be minimized by clearing bit INTPND at an early stage User s Manual 19 9 1999 09 Infineon inrineon C1 64 Group The On Chip CAN Interface of interrupt processing and if
32. sceiver o 2 a lt O CAN_TXD Physical Layer Figure 19 12 Connection to a Single CAN Bus User s Manual 19 35 1999 09 Infineon technologies Port Control C164 Group The On Chip CAN Interface The receive data line and the transmit data line of the CAN module are alternate port functions Make sure that the respective port pin for the receive line is switched to input in order to enable proper reception The respective port driver for the transmit will automatically be switched ON This provides a standard pin configuration without additional software control and also works in emulation mode where the port direction registers cannot be controlled The receive and transmit line of the CAN module may be assigned to several port pins of the C164 under software control This assignment is selected via bitfield IPC Interface Port Connection in register PCIR Table 19 3 Assignment of CAN Interface Lines to Port Pins IPC CAN RXD CAN TXD Notes 000 P4 5 P4 6 Compatible assignments CAN1 1 001 Reserved Do not use this combination 010 P8 0 P8 1 Port 4 available for segment address lines A21 A16 4 MByte external address space 011 P8 2 P8 3 Port 4 available for segment address lines A21 A16 4 MByte external address space 100 Reserved Do not use this combination 101 Reserved Do not use this combination 110 Reserved Do not use this co
33. ted by commands from the Bit Stream Processor According to the values of the error counters the CAN controller is set into the states error active error passive and busoff The CAN controller is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 It goes busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in this state until the busoff recovery sequence is finished Additionally there is the bit EWRN in the Status Register which is set if at least one of the error counters equals or exceeds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit User s Manual 19 4 1999 09 Infineon Inrineon C1 64 Group The On Chip CAN Interface Bit Timing Logic This block BTL monitors the busline input CAN RXD and handles the busline related bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant busline transition at Start of Frame hard synchronization and on any further recessive to dominant busline transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time The programming of
34. ts and the functions they provide are described below Each of the message objects has a unique identifier and its own set of control and status bits Each object can be configured with its direction as either transmit or receive except the last message which is only a double receive buffer with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status bits giving the CPU full flexibility in detecting when a remote data frame has been sent or received For general purpose two masks for acceptance filtering can be programmed one for identifiers of 11 bits and one for identifiers of 29 bits However the CPU must configure bit XTD Normal or Extended Frame Identifier for each valid message to determine whether a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance filtering allowing a large number of infrequent objects to be handled by the system The object layer architecture of the CAN controller is designed to be as regular and orthogonal as possible This
35. ved remote frame with same identifier as this message object NEWDAT 0 load message into buffer u TXRQ 1 RMTPND 1 send message transmission successful INTPND 1 TXRQ 0 RMTPND 0 0 reset INTPND 1 1 set Figure 19 6 CAN Controller Handling of Transmit Objects DIR 1 User s Manual 19 23 1999 09 Infineon technologies C164 Group The On Chip CAN Interface received frame with same identifier as this message object NEWDAT 0 load identifier and control into buffer serenge tane E isaisa MSGLST 1 store message NEWDAT 1 TXRQ 0 RMTPND 0 n INTPND 1 transmission successful TXRQ 0 RMTPND 0 yes INTPND 1 0 reset 1 set Figure 19 7 CAN Controller Handling of Receive Objects DIR 0 User s Manual 19 24 1999 09 Infineon ies reus The On Chip CAN Interface Power Up all bits undefined TXIE application specific RXIE application specific INTPND 0 RMTPND 0 TXRQ 0 CPUUPD 1 Identifier application specific NEWDAT 0 Direction transmit DLC application specific MSGVAL 1 XTD application specific Initialization CPUUPD 1 Update Start NEWDAT 1 Update write calculate message contents Update End CPUUPD 0 no update message Figure 19 8 CPU Handling of Transmit Objects DIR 1 User s Manual 19 2
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