STM8 SWIM communication protocol and debug module
Contents
1. liiis 17 Decoding table for breakpoint interrupt generation lille ee eee 23 STMB registers Lees het aoa eR ere edad AU Yu uon RR e E p aper bees 34 Peripherals which are frozen by the bits of the DM ENFCTR register for each STM8 product rr 35 Document revision history llseeeeeeee e rn 36 Doc ID 14024 Rev 3 ky UM0470 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Debug system block diagram 2 re 6 SWIM pin external connections rn 7 SWIM activation sequence hr 8 SWIM activation timing diagram rn 9 SWIM entry sequence hh 10 High speed bit format 0 0 0 ce ete eee 11 Low speed bit format 0 000 cc eee 12 Command format Host gt Target 0 ee 13 Data format Target gt Host a auauua aaea 13 Timings on SWIM pin RR rn 17 Debug module block diagram naana aane 21 STMB8 Instruction Model 000000 24 STM8 Debug Module Stall Timing 000 eee 24 STM8 DM Data Break Timing cece eee 25 STM8 DM instruction break timing 000 c eee eta 25 STM8 DM step timing RII II hn 25 Doc ID 14024 Rev 3 5 37 Debug system overview UM0470 1 6 37 Debug system overview The2. wv UM0470 Sf i User manual STM8 SWIM communication protocol and debug module Introduction This manual has been written for developers who need to build programming testing or debugging tools for the STM8 microcontroller family It explains the debug architecture of the STMB8 core The STM8 debug system consists of two modules e DM Debug module e SWIM Single wire interface module Related documentation e How to program STM8S and STMBA Flash program memory and data EEPROM PM0051 STMB8A version is not published yet e How to program STM8L Flash program memory and data EEPROM PM0054 June 2011 Doc ID 14024 Rev 3 1 37 www st com Contents UM0470 Contents 1 Debug system overview 2 eee 6 2 Communication layer uu sas he Rn n rie dca ce cane eR RR wa a 7 3 Single wire interface module SWIM 8 3 1 Operating modes sccicccene pede ge dsbeevews eaenree dew bavee AGA 8 3 2 SWIM entry sequence ssseeeseeeeee ens 9 3 3 Bit TOEIat iussis ea p UR was i erkeer pi C Ead ANDA 11 3 3 1 High speed bit format eee 11 3 3 2 Low speed bit format lisse 12 3 4 SWIM communication protocol 0 00 e eee 13 3 5 SWIM commandS gba pe eset GAGAWA pee gue s PECTARESCELGS 14 3 5 1 SRST system reset 0 2 0 0 cece tees 14 3 5 2 ROTF read on the fly cc teens 14 3 5 3 WOTF write on the fly lllllllelsele B 15 3 6 SW
3. 0 is greater or equal to 5 Figure 6 High speed bit format To PL lt gt 4 T owpeoxe pose WO age cquo lt gt 0 ANAN AHA N KAN Doc ID 14024 Rev 3 11 37 UM0470 Single wire interface module SWIM 3 3 2 12 37 Low speed bit format 1 bit is generated with twenty two HSI oscillator pulses The bit format is 2 pulses at 0 followed by 20 pulses at 1 for 1 value 20 pulses at 0 followed by 2 pulses at 1 for 0 value When the SWIM receives a data packet it will decode T when the number of consecutive samples at 0 is less or equal to 8 0 when the number of consecutive samples at 0 is greater or equal to 9 Figure 7 Low speed bit format lt gt 1 NANNANANANANANANANANANA lt gt 0 ANANANANAANANANANANANANA Doc ID 14024 Rev 3 UM0470 Single wire interface module SWIM 3 4 SWIM communication protocol When in ACTIVE mode communication can be initiated by host or device Each byte or command is preceded by a 1 bit header in order to arbitrate if both host and device initiate the communication at the same time The host header is 0 in order to have the priority over the device in case of arbitration due to open drain capability The host can start the transfer only if there is no transfer on going Figure 8 Command format Host
4. 4 96 Figure 10 Timings on SWIM pin l N P sss SWIM pin N lt tbo tb1 y K t Table 3 SWIM pin characteristics Timings for HSI 10 MHz Parameter Symbol a LSI 32 to 64 kHz ormula Min Max Fall time on SWIM pin tr TBD 50 ns Rise time on SWIM pin t TBD 96 ns Inter bit time The time which SWIM pin tib TBD gt 0 stays high between 2 bits Inter frame time Time between end of a tit TBD 0 frame and the next one High speed tpo TBD 768 ns 832 ns Low time for a bit at O Low speed tpo TBD 1 6 us 2 4 us Low time for a bit at 1 High speed Tb1 TBD 192 ns 208 ns High Speed Low speed Tb1 TBD 150 ns 250 ns Injected current on SWIM TBD 8 mA pin Doc ID 14024 Rev 3 17 37 Single wire interface module SWIM UM0470 3 10 STM8 SWIM registers 3 10 1 SWIM control status register SWIM CSR Address 7F80h Reset value 00h This register is reset only by a power on reset or by SWIM SRST command if the RST bit 21 in the SWIM CSR register 7 6 5 4 3 2 1 0 SAFE MASK NO ACCESS SWIM DM HS OSCOFF RST HSIT PRI rw r rw rw rw rw r rw Bit 7 SAFE_MASK Mask internal RESET sources This bit can be read or written through SWIM only It cannot be accessed through the STM8 bus It includes the Watchdog reset 0 Internal Reset sources are not masked 1 Internal reset sources are masked Bit 6 NO ACCESS Bus not
5. DM breakpoint register 1 extended byte DM BKR1E STM8 Address 7F90h Reset value 1111 1111 FFh 7 6 5 4 3 2 1 0 BK1 23 16 rw rw rw rw rw rw rw rw BK1 23 16 Breakpoint 1 extended byte value Bits 7 0 This register is written by software to define the extended 8 address bits of Breakpoint 1 4 12 2 DM breakpoint register 1 high byte DM_BKR1H Address 7F91h Reset value 1111 1111 FFh 7 6 5 4 3 2 1 0 BK1 15 8 rw rw rw rw rw rw rw rw BK1 15 8 Breakpoint 1 high byte value Bits 7 0 This register is written by software to define the higher 8 address bits of Breakpoint 1 4 12 3 DM breakpoint register 1 low byte DM BKR1L Address 7F92h Reset value 1111 1111 FFh 7 6 5 4 3 2 i j BK1 7 0 rw rw rw rw rw hw m Bits z o BK1 7 0 Breakpoint 1 high byte value This register is written by software to define the lower 8 address bits of Breakpoint 1 Doc ID 14024 Rev 3 27 37 Debug module DM UM0470 4 12 4 4 12 5 4 12 6 28 37 DM breakpoint register 2 extended byte DM BKR2E Address 7F93h Reset value 1111 1111 FFh BK2 23 16 BK2 23 16 Breakpoint 2 extended byte value Bits 7 0 This register is written by software to define the extended 8 address bits of Breakpoint 2 DM breakpoint register 2 high byte DM BKR2H Address 7F94h Reset value 1111 1111 FFh BK2 15 8 BK2 15 8 Breakpoint 2 high byte value Bits 7 0 This register
6. STM8 debug system interface allows a debugging or programming tool to be connected to the MCU through a single wire bidirectional communication based on open drain line It provides non intrusive read write access to RAM and peripherals during program execution The block diagram is shown in Figure 1 Figure 1 Debug system block diagram LSI oscillator y STM8 SWIM SWIM Entry SWIM pin 1 gt Comm Command Layer Decode Debug module DM HSI oscillator STM8 Core s Peripherals Flash Data EEPROM The debug module uses the two internal clock sources present in the device the LSI Low Speed Internal clock usually in the range 30 kHz 200 kHz depending on the product one and the HSI High Speed Internal clock usually in the range 10 MHz to 25 MHz depending on the device The clocks are automatically started when necessary Doc ID 14024 Rev 3 UM0470 Communication layer 2 Communication layer The SWIM is a single wire interface based on asynchronous high sink 8 mA open drain bidirectional communication While the CPU is running the SWIM allows non intrusive read write accesses to be performed on the fly to the RAM and peripheral registers for debug purposes In addition while the CPU is stalled the SWIM allows read write accesses to be performed to any other part
7. decoded the CPU is stalled and the STALL and SWBKF bits are set by hardware to indicate that a software breakpoint has occurred To resume execution the debugger must restore the user s instruction then set the FLUSH bit and clear the STALL bit Timing description This paragraph defines when the Debug Module stalls the CPU when using the different breakpoint sources e The STM8 instruction can be modelized in time with an op code operand FETCH phase DECODE and EXECUTION phases as shown in Figure 12 The timing information is based on this models Figure 12 STMB8 Instruction Model INSTRUCTION FETCH OP CODE operand 1 5 bytes 1 to 5 tepy 1 to 10 tepy 1 2 tcpu DECODE EXECUTE Abort The stall is generated immediately on writing the STALL bit in the DM_CSR2 register Figure 13 STM8 Debug Module Stall Timing INSTRUCTION 1 INSTRUCTION 2 INSTRUCTION 3 f DM Stall generated STALL REQUEST Doc ID 14024 Rev 3 ky UM0470 Debug module DM 4 8 Data breakpoint A stall is generated when SWIM is active after the end of the current instruction execution Figure 14 STM8 DM Data Break Timing d Fetch2 Dec2 n Exe2 1 Exe3 stalled D rd1 D wr1 v Stall generated DATA B
8. gt Target Command Data1 0 b2 bil bol pblack o bz bel bs bal b3 b2 b1 bol pol ackl Italic Bit sent by the Host Bold Bit sent by the device Each command sent by the host is made of e 1command ROTF WOTF or SWRST made of Header 1 bit at 0 b2 b0 3 bit command pb parity bit XOR between all b i ack acknowledge 1 bit at 1 The receiver must send the not acknowledge value if it has detected a parity error NACK not acknowledge 1 bit at 0 or it is not yet ready e optionally several data packets in case of WOTF made of Header 1 bit at 0 b7 b0 8 bit data pb parity bit sent after data XOR between all b i ack acknowledge Figure 9 Data format Target gt Host data n 1 data n data n 1 55 1 bz be b5 ba b3 b2 b1 bo pbl ack Italic Bit sent by the Host Bold Bit sent by the device Each data frame is made of Header 1 bit at 1 b7 bO 8 bit data pb parity bit sent after data ack acknowledge Doc ID 14024 Rev 3 13 37 Single wire interface module SWIM UM0470 3 5 3 5 1 3 5 2 14 37 SWIM commands The Host can send a command when the line is idle or after each data byte from device After sending the command the host releases the line When the SWIM is ready to answer to the command it initiates the transfer If a new command from the host occurs while a command is pending in
9. is set by WOTF command to generate an ABORT equivalent command It is also set by an DM trap interrupt event This bit is cleared by WOTF command to re start the CPU 0 CPU runs normally 1 CPU is stalled Bit 2 1 Reserved Must be kept at 0 Bit 10 FLUSH Flush decode This bit is set by software to flush the instruction decode phase after a PC modification It is cleared by hardware when the flush is completed 0 Default status 1 Flush decode 32 37 a Doc ID 14024 Rev 3 UM0470 Debug module DM 4 12 11 DM enable function register DM ENFCTR Address 7F9Ah Reset Value 1111 1111 FFh 7 0 ENFCT7 ENFCT6 ENFCT5 ENFCT4 ENFCT3 ENFCT2 ENFCT1 ENFCTO rw rw rw rw rw rw rw rw ENFCTx Enable function This bit is set and cleared by software it allows to freeze a particular function of a peripheral when the core is stalled The ENFCTx bit definitions are product dependent 0 Function is frozen when CPU is stalled by DM 1 Function is active Bits 7 0 See Appendix A for a full description of the DM ENFCTR register Doc ID 14024 Rev 3 33 37 Debug module DM UM0470 4 12 12 Summary of SWIM DM and core register maps Table 5 STM8 registers STM8 Register 9 7 6 5 4 3 2 1 0 address name A A7 A6 A5 A4 A3 A2 A1 AO VIRO Reset value 0 0 0 0 0 0 0 0 7FO1h PCE PC23 PC22 PC21 PC
10. write 1 Break on data write Bit 0 Reserved Doc ID 14024 Rev 3 29 37 Debug module DM UM0470 4 12 8 DM control register 2 DM CR2 Address 7F97h Reset value 0000 0000 00h 7 6 5 4 3 2 1 0 Reserved FV ROM Reserved FV RAM rw rw Bit 7 3 These bits are reserved and must be kept at 0 Bit 2 FV_ROM Remap Vector table in ROM This bit is set or cleared by software It remaps the vector table to a ROM location product dependent instead of program memory usually 8000h 0 Vector table is in Program Memory area 8000h 1 Vector table is in ROM memory area depends on the product Bit 1 Reserved must be kept at 0 Bit O FV_RAM Remap vector table in RAM This bit is set or cleared by software It remaps the interrupt vector table to a RAM location instead of program memory usually 8000h 0 Vector table is in Program Memory area 8000h 1 Vector table is in RAM memory area address depends on the product 30 37 a Doc ID 14024 Rev 3 UM0470 Debug module DM 4 12 9 DM control status register 1 DM CSR1 Address 7F98h Reset value 0001 0000 10h 7 6 5 4 3 2 1 0 Reserved STE STF RST BRW BK2F BK1F Reserved rw rw r r r r Bit 7 Reserved STE Step mode enable Read Write Bit 6 This bit is set and cleared by software It enables Step mode 0 Step mode disabled 1 Step mode enabl
11. 1 Data Write on lt BK1 or BK2 lt 1 0 0 0 1 0 1 0 Data Read on lt BK1 or BK2 lt 1 0 1 0 1 0 1 1 Data R W on lt BK1 or BK2 lt 1 0 0 1 0 1 1 X X Disabled 0 0 x 1 0 0 0 0 Instruction fetch on BK1 then on BK2 0 1 x 1 0 0 0 1 Data Write on BK1 or BK2 10 or 01 or 11 0 1 0 0 1 0 Data Read on BK1 or BK2 10 or 01 or 11 1 1 0 0 1 1 Data R W on BK1 or BK2 10 or 01 or 11 0 1 1 0 1 0 0 Instruction fetch on BK1 or BK2 10 or 01 or 11 x 1 0 1 0 1 Instruction fetch on BK1 Data Write on BK2 10 or 01 x 0 1 0 1 1 0 Instruction fetch on BK1 Data Read on BK2 10 or 01 x 1 1 0 1 1 1 Instruction fetch on BK1 Data R W on BK2 10 or 01 x 0 1 1 1 0 X X Disabled 0 0 x 1 1 1 0 0 Data Write in Stack on 3 BK1 Instruction fetch on BK2 10 or 01 0 x 1 1 1 0 1 Data Write in Stack on lt BK1 Data Write on BK2 10 or 01 or 11 0 1 1 1 1 0 Data Write in Stack on lt BK1 Data Read on BK2 10 or 01 0 1 1 1 1 1 1 Data Write in Stack on lt BK1 Data R W on BK2 10 or 01 or 11 0 0 1 Ky Doc ID 14024 Rev 3 23 37 Debug module DM UM0470 4 5 4 6 4 7 24 37 Software breakpoint mode Software breakpoint mode is reserved for debugging tools to insert breakpoints into user code by substituting a user instruction with a software break reserved BKPT instruction 38b Software breakpoint mode is enabled using the SWBKPE bit in the DM control status register 2 DM CSR2 When a BKPT instruction is
12. 20 PC19 PC18 PC17 PC16 7F02h PCH PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 7F03h PCL PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO 7FO4h XH X15 X14 X13 X12 X11 X10 X9 X8 Reset value 0 0 0 0 0 0 0 0 XL X7 X6 X5 X4 X3 X2 X1 Xo fr h Reset value 0 0 0 0 0 0 0 0 7F06h YH Y15 Y14 Y13 Y12 Yi1 Y10 Y9 Y8 Reset value 0 0 0 0 0 0 0 0 YL Y7 Y6 Y5 Y4 Y3 Y2 y1 YO 7FO7h Reset value 0 0 0 0 0 0 0 0 7F08h SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 7F09h SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO CC V n H Io N Fd C 7FOAh Reset value 0 0 d 0 1 0 0 0 7F80h SWIM CSR SAFE MASK NO ACCESS SWIM DM HS OSCOFF RST HSIT PRI Reset value 0 0 0 0 0 0 0 0 7F90h DM BK1RE BK1R23 BK1R22 BK1R21 BK1R20 BK1R19 BKIR18 BK1R17 BK1R16 Reset value 1 1 1 1 1 1 1 1 DM BK1RH BK1R15 BK1R14 BK1R13 BK1R12 BKIR11 BK1R10 BK1R9 BK1R8 7F91h Reset value 1 1 1 1 1 1 1 1 DM BK1RL BK1R7 BK1R6 BK1R5 BK1R4 BK1R3 BK1R2 BK1R1 BK1RO 7F92h Reset value 1 1 1 1 1 1 1 1 DM BK2RE BK2R23 BK2R22 BK2R21 BK2R20 BK2R19 BK2R18 BK2R17 BK2R16 7F93h Reset value 1 1 1 1 1 1 1 1 DM BK2RH BK2R15 BK2R14 BK2R13 BK2R12 BK2R11 BK2R10 BK2R9 BK2R8 7F94h Reset value 1 1 1 1 1 1 1 1 7F95h DM BK2RL BK2R7 BK2R6 BK2R5 BK2R4 BK2R3 BK2R2 BK2R1 BK2RO Reset value 1 1 1 1 1 1 1 1 7F96h DM CR1 WDGOFF Reserved BC2 BC1 BCO BIR BIW Reserved Reset value 0 0 0 0 0 0 0 0 DM CR2 FV ROM Reserved FV RAM 7F97h Reset value Reserved 0 0 0 7F98h DM CSR1 Reserved STE STF RST BRW BK2F BK1F Reserved Reset value 0 0 0 0 0 0 0 0 7F99h
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14. D 14024 Rev 3 19 37 Debug module DM UM0470 4 4 1 4 2 20 37 Debug module DM Introduction The Debug Module DM allows the developer to perform certain debugging tasks without using an emulator For example the DM can interrupt the MCU to break infinite loops or output the core context stack at a given point The DM is mainly used for in circuit debugging Main features e Two conditional breakpoints break on instruction fetch data read or write stack access Software breakpoint control Step mode External Stall capability on WOTF command in SWIM mode Watchdog and peripherals control DM Version identification capability Interrupt Vector Table selection Doc ID 14024 Rev 3 ky UM0470 Debug module DM Figure 11 Debug module block diagram WATCHDOG mi v Debug Module DM WATCHDOG CONTROL LOGIC DM REGISTERS xx READ WRITE ke LOGIC a DM BK7 DM BK2 Swim H SWIM LA Y BC2 DM BC1 SEMEN SWBKF BREAKPOINT Sco l4 EMU DMA i ig flag LOGIC interface la BIR SOFTWARE gt p E BREAK RESET Y i m DM CR1 STE STF RSTBRW BK2F BK1F l STM8 CPU v DM STALL DM STALI TRAP Fro
15. DM CSR2 Reserved Reserved SWBKE SWBKF STALL Res Reserved FLUSH Reset value 0 0 0 0 0 0 0 7E9Ah DM ENFCTR ENFCT7 ENFCT6 ENFCT5 ENFCT4 ENFCT3 ENFCT2 ENFCT1 ENFCTO Reset value 1 1 1 1 1 1 1 1 1 The reset value for the SP and PC registers is product dependent Refer to the device datasheet for more details 34 37 Doc ID 14024 Rev 3 a UM0470 Description of the DM ENFCTR register for each STM8 product Appendix A Description of the DM ENFCTR register for each STM8 product Some peripherals can be frozen through the debug module during debug using the DM ENFCTR register address 7F9Ah Table 6 shows the peripherals which are frozen by the bits ENFCTO to ENFCT7 of the DM ENFCTR register Table 6 Peripherals which are frozen by the bits of the DM ENFCTR register for each STM8 product DM ENFCTR SIM8AFS1A STMBAF616 STM8AF51B STM8S103 903 STM8L101 STM8L15x register 91M85207 208 STM8S105 056 Kbyte die 8 Kbyte die 8 Kbyte die 32 Kbyte die 128 Kbyte die 32 Kbyte die Bit Peripheral Timer4 Timer4 Timer4 Timer4 2 2 ENFCTO System timer System timer System timer System timer KG KG ENFCT1 Timer2 Timer2 Tmer2 Tmer2 Timer2 Timer2 ENFCT2 Timer3 Timer3 Tmer3 Not used Timer3 Timer3 ENFCT3 Timer1 Timer1 Tmer1 Timer1 bib astiussd Timer1 ENC IS bit not used bit not used bit not used bit not used Timers uu beg bit not used bit not us
16. IM communication reset c eee eens 15 3 7 CPU register access eee 16 3 8 SWIM communication in Halt mode a 16 3 9 Physical layer aaah rw e RR ERG IRR Ra na bea ee kes hea a tar 17 3 10 STMS SWIM registers i na GA PWE ke ewes KAG Na KURA HUGE ERE 18 3 10 1 SWIM control status register SWIM CSR 002 0a 18 3 10 2 SWIM clock control register CLK SWIMCCR 19 4 Debug module DM Leere 20 4 1 Introduction RR I I Ree 20 4 2 Main features hr 20 4 3 DEDU NAA AA 22 4 3 1 Reset AA AA 22 4 3 2 Breakpolnts 122v ERE RR ADEL KUNG eda e eb TR Rs Kh a 22 4 3 3 hona T TC 22 4 3 4 Watchdog control re 22 4 3 5 Interaction with SWIM 0222 eh 22 4 4 Breakpoint decoding table 0 00 eee eee 23 2 37 Doc ID 14024 Rev 3 ky UM0470 Contents 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 Software breakpoint mode 00 0 24 Timing description Cawag dp Ew PR AKA es a RA RR a RR CR hex 24 hp lt 2 change ene T TUTTTTTT 24 Data breakpoint 22 024 deca ses EX Chee eee ee ews RR REG NA ER ERE 25 Instruction breakpoint 225 22 se eed xa Ro RR RR RR Re awe ye we 25 Step ModE 5 p Code Tar eR RERO EET GERE RE hess RE ES e MEE 25 Application notes es cn tee RERO EORR ROI E M RR OG RR RU RACER RUE 26 4 11 1 Illegal Memory access sseseseees B 26 4 11 2 Forbidden stack access c eet e
17. REAK REQUEST 4 9 Instruction breakpoint In the STM8 on an instruction break DM stalls the CPU before the selected instruction execution while the instruction is in the decode stage See Figure 15 Note When the specified address does not correspond to a valid instruction address no stall is generated Figure 15 STM8 DM instruction break timing M pect EXE ExEC2 sabo DEC2 INSTRUCTION BREAK REQUEST STALL Request DM servicing 4 10 Step mode The STM8 CPU stall is activated before the instruction execution in the first decode cycle of the instruction See Figure 16 Figure 16 STM8 DM step timing t p DEC1 ced DEC2 DEC2 DEC2 EXEC2 EXEC2 EXEC2 PEC DECA EXECA Y Y v A 1st DM 2nd DM 3rd DM 4th DM STEP Break break break break ENABLE served served served served CPU Stalled CPU Stalled CPU Stalled CPU Stalled Note When Step mode and Instruction Break on the next instruction mode are both enabled both the STF and the BKxF flags are set When you clear the STALL bit the step function continues its normal operation Doc ID 14024 Rev 3 25 37 Debug module DM UM0470 4 11 4 11 1 4 11 2 4 11 3 26 37 Application notes Illegal Memory access To verify if the program attempts to write or read in an illegal part of memory reserved area select the Data R W on BK1 lt lt BK2 condition where BK1 and BK2 are the lower and upper addresses of the reserved memory Forbidden stack ac
18. SWIM the pending command is cancelled and the new command is decoded except in case of WOTF Three commands are available They are listed in Table 1 Table 1 SWIM command summary Command Binary Code SRST 000 ROTF 001 WOTF 010 Reserved for future use SRST system reset Format 1 command from Host to Target SRST Parameters None SRST command generates a system reset only if SWIM CSR SWIM DM bit is set ROTF read on the fly Format 1 command followed by the number of bytes to be read followed by the address on three bytes ROTF N QE H L D D N Parameters N The 8 bits are the number of bytes to read from 1 to 255 E H L This is the 24 bit address to be accessed D These are the data bytes read from the memory space If the host sends a NACK to a data byte the device will send the same byte again If SWIM_DM bit is cleared ROTF can only be done on SWIM internal registers Doc ID 14024 Rev 3 ky UM0470 Single wire interface module SWIM 3 5 3 3 6 WOTF write on the fly 1 command followed by the number of bytes to be written followed by the address on three bytes WOTF N E H L D D 4N Parameters N The 8 bits are the number of bytes to write from 1 to 255 QE H L This is the 24 bit address to be accessed D These are the data bytes to write in the memor
19. SWIM entry sequence or to be switched to I O mode by the application software I O This state is entered by the software application by setting the SWIM disable bit SWD bit in the core configuration register CFG GCR In this state the user application can use the SWIM pin as a standard I O pin the only drawback is that there is no way to debug the functionality of this pin with the built in debug capabilities In case of a reset the SWIM goes back to OFF mode ACTIVE This mode is entered when a specific sequence is detected on the SWIM pin while in OFF state In this state the SWIM pin is used by the host tool to control the STM8 with 3 commands SRST System Reset ROTF Read On The Fly WOTF Write On The Fly Please note that the SWIM can be set Active and communicate while the device is in RESET state NRST pin forced low Figure 3 SWIM activation sequence SWIM entry sequence Doc ID 14024 Rev 3 ky UM0470 Single wire interface module SWIM 3 2 SWIM entry sequence After a POR and as long as the SWIM is in OFF mode the SWIM pin is sampled for entry sequence detection In order to do this the internal low speed RC clock is automatically turned ON after POR and remains forced ON as long as the SWIM is in OFF mode If the register which forces the SWIM in I O mode is written before the entry sequence is finalized the SWIM enters I O mode Once the SWIM is ACTIVE writin
20. access has to be used The host can restart the program execution by resetting the STALL bit using the SWIM commands Watchdog control Using the WDGOFF bit in the DM control register 1 DM CR1 you can configure the Window Watchdog and Independent Watchdog counters to be stopped while the CPU is stalled by the Debug Module This bit must be set before the watchdogs are activated If a watchdog is enabled by Hardware Watchdog option bit the WDGOFF bit has no effect on it Interaction with SWIM The SWIM sends the status bit which indicates the SWIM is active or not When SWIM is not active the DM will not generate any break stall request to the CPU Doc ID 14024 Rev 3 ky UM0470 Debug module DM 4 4 Breakpoint decoding table Table 4 Decoding table for breakpoint interrupt generation DM CR1 DM CSR1 BREAK CONDITIONS BC2 BC1 BCO BIR BIW BK1F BK2F BRW 0 0 0 0 0 Disabled RESET state 0 0 x 0 0 0 0 1 Data Write on BK1 and Data BK2L 1 0 0 0 0 0 1 0 Data Read on BK1 and Data BK2L 1 0 1 0 0 0 1 1 Data R W on BK1 and Data BK2L 1 0 0 1 0 0 1 0 0 Instruction fetch BK1 lt lt BK2 1 0 x 0 0 1 0 1 Data Write on BK1 lt lt BK2 1 0 0 0 0 1 1 0 Data Read on BK1 lt lt BK2 1 1 0 0 1 1 1 Data R W on BK1 lt lt BK2 1 0 0 1 0 1 0 0 0 Instruction fetch on lt BK1 or BK2 lt 1 0 x 0 1 0 0
21. accessible This bit can be read through SWIM only to determine the bus is accessible or not It is set automatically if the device is in HALT WFI or readout protection mode 0 Bus is accessible 1 Bus is not accessible Caution Depending on the SWIM revision in some devices the NO ACCESS bit indicates only that the device is in HALT mode Bit 5 SWIM DM SWIM for Debug Module This bit can be read or written to 1 through SWIM only It cannot be accessed through the STM8 bus 0 The SWIM can access only SWIM CSR register SWIM reset command has no effect 1 The whole memory range can be accessed with ROTF and WOTF commands The SRST command generates a Reset Bit 4 HS High Speed This bit can be read or written through SWIM only It cannot be accessed through STM8 bus 0 Low speed bit format 1 High speed bit format The speed change occurs when the communication is IDLE It is reset by the SWIM communication reset condition as described in Section 3 6 Bit 3 OSCOFF Oscillators Off control bit This bit can be read or written through SWIM only It cannot be accessed through STM8 bus 0 HSI oscillator remains ON in halt mode 1 HSI oscillator is not requested ON in Halt mode 18 37 a Doc ID 14024 Rev 3 UM0470 Single wire interface module SWIM RST SWIM Reset Control Bit This bit can be read or written through SWIM only It cannot be accessed through Bit 2 STM8 bus 0 SWIM is n
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23. cess If part of the stack contains specific data or instructions that should not be overwritten the DM can be used to prevent access to these locations Select one of the Data Write in Stack on Q BK1 conditions and set BK1 to the upper value where the specific data are located in the stack If the STM8 tries to overwrite these values after an interrupt or a CALL DM will generate a break The four possible associated conditions allow to manage another breakpoint capability at the same time DM break After an DM break the CPU is stalled through the EMU Stall signal While the CPU is stalled the SWIM can read write any memory location or memory mapped register The program can be continued from the breakpoint by resetting the Stall bit If a change of PC is needed the SWIM must write the new PC value using the method described in Section 3 7 CPU register access In order to fetch the code from the new PC address the SWIM must set the FLUSH bit in the DM control status register 2 DM CSR2 before resetting the STALL bit Doc ID 14024 Rev 3 ky UM0470 Debug module DM 4 12 DM registers These registers are read write only through the SWIM interface In this section the following abbreviations are used read write rw SWIM can read and write to these bits via the ROTF WOTF commands read only r SWIM can only read these bits via the ROTF command 4 12 1
24. ed STF Step Flag Read Only This bit indicates that the stall was generated by Step mode It is set and cleared by Bit 5 hardware Writing to this bit does not change the bit value 0 Step mode stall did not occur 1 Step mode stall occurred RST Reset Flag Read Only This bit is set by hardware when the CPU was stalled by the debug module DM just after reset It is cleared by hardware when the STALL bit is cleared Writing to Bit 4 en this bit does not change the bit value 0 No reset occurred 1 A reset occurred BRW Break on Read Write Flag Read Only This bit gives the value of the read write signal when a break occurs Its value is not significant for instruction fetch breaks It is set by hardware depending on the Bit 3 breakpoint conditions see Table 4 Decoding table for breakpoint interrupt generation on page 23 and is cleared by hardware depending on the next breakpoint conditions Writing to this bit does not change the bit value 0 Breakpoint on write 1 Breakpoint on read BK2F Breakpoint 2 Flag Read Only This bit indicates that the DM stall was generated by Breakpoint 2 It is set by hardware depending on the control conditions see Table 4 Decoding table for Bit 2 breakpoint interrupt generation on page 23 and is cleared by hardware when the STALL bit is cleared Writing to this bit does not change the bit value 0 Breakpoint 2 did not occur 1 Breakpoint 2 occurred BK1F Breakpoint 1 Flag Read Only This bit ind
25. ed mers bit not used bit not used DMA mE 2 popes bit not used bit not used Pee bit not used bit not used RIG 2 2 2 2 mE mE ENE GIA ke Ug PS NG bit not used bit not used ky Doc ID 14024 Rev 3 35 37 Revision history UM0470 Revision history 36 37 Table 7 Document revision history Date Revision Changes 15 Jan 2008 1 Initial release 10 Dec 2009 Updated documentation references in Introduction Section 3 2 SWIM entry sequence updated Figure 4 and explanation Section 3 3 Bit format replaced OBL bit with HSIT bit Added Appendix A 06 Jun 201 1 Introduction updated titles of reference documents Updated name of IOM bit to SWIM disable bit SWD in Section 3 1 Operating modes Figure 3 and SWIM control status register SWIM CSR Updated name of MCR register to CFG_GCR register in Section 3 1 Operating modes a Doc ID 14024 Rev 3 UM0470 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services descri
26. ee 26 4411 3 DM break daa tesia oie PAG NG KG BET ERROR Re Aedui dicha eere rg 26 DM registers a ducts sce eee ANNA a HONG PINANG adeb EO IDA AE 27 4 12 1 DM breakpoint register 1 extended byte DM BKR1E 27 4 12 2 DM breakpoint register 1 high byte DM BKR1H 27 4 12 3 DM breakpoint register 1 low byte DM BKR1L 27 4 12 4 DM breakpoint register 2 extended byte DM BKR2E 28 4 12 5 DM breakpoint register 2 high byte DM BKR2H 28 4 12 6 DM breakpoint register 2 low byte DM BKR2L 28 4 12 7 DM control register 1 DM CR1 lelselselselerssne 29 4 12 8 DM control register 2 DM CR2 llselsleleeslsen 30 4 12 9 DM control status register 1 DM CSR1 lle 31 4 12 10 DM control status register 2 DM CSR2 Less 32 4 12 11 DM enable function register DM ENFCTR 20 aaa 33 4 12 12 Summary of SWIM DM and core register maps 34 Appendix A Description of the DM ENFCTR register foreach SIMS product sisse tek KA ABA EROR Red a 35 Revision NISLOTY ws ida aca RC c owl La RR eee Re ee acl ew awe 36 ky Doc ID 14024 Rev 3 3 37 List of tables UM0470 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 4 37 SWIM command summary 2 ehh 14 CPU register memory mapping in STM8 2 sees 16 SWIM pin characteristics
27. g this bit has no influence on communication and the SWIM interface remains in ACTIVE mode If an application uses the SWIM pin as standard I O it puts the SWIM interface in I O mode in the initialization section of the software code typically this is performed just after the reset However even in this case it is still possible to put the SWIM interface in ACTIVE mode by forcing the RESET pin to O and keep it low for the duration of the SWIM entry sequence As long as the SWIM is in OFF mode the SWIM entry sequence is detected at any moment during reset or when the application is running If both the SWIM pin and the reset pin are multiplexed with I Os the way to enter SWIM ACTIVE state is to power down the MCU device power up and to maintain the reset until the end of the SWIM entry sequence Figure 4 SWIM activation timing diagram SWIM CSR 5 and 7 set SWIM pin i i T 9 4 Reset 1 2 3 4 5 6 Reset rising Ut 0 8 Option byte loading i D a HSI ADC ON m eps LSI OSC ON ai17411 Doc ID 14024 Rev 3 9 37 Single wire interface module SWIM UM0470 10 37 SWIM activation is shown in Figure 4 and each segment on the diagram is described below 1 To make the SWIM active the SWIM pin must be forced low during a period of 16 us which is 64 pulses minimum at the frequency of HSI After this first pulse at O the SWIM detects a specific
28. icates that the DM interrupt was generated by Breakpoint 1 It is set by hardware depending on the control conditions see Table 4 Decoding table for Bit 1 breakpoint interrupt generation on page 23 and is cleared by hardware when the STALL bit is cleared Writing to this bit does not change the bit value 0 Breakpoint 1 did not occur 1 Breakpoint 1 occurred Bit 0 Reserved 4 Doc ID 14024 Rev 3 31 37 Debug module DM UM0470 4 12 10 DM control status register 2 DM CSR2 Address 7F99h Reset value 0000 0000 00h 7 6 5 4 3 2 1 0 Reserved SWBRK SWBKF STALL Reserved FLUSH Bits 7 6 Reserved Must be kept at 0 Bit 5 SWBKE Software breakpoint control bit read write This bit is used to enable disable the software breakpoint capability with NOP instruction 0 DM does not generate any event when NOP SW BRK instruction is fetched by CPU 1 DM generates an event CPU stalled in SWIM mode when a software break instruction is fetched by CPU Bit 4 SWBKF Software breakpoint status bit read only This flag is set when the CPU executes the software break instruction 0 No software break instruction detected 1 Software break instruction detected This bit is cleared when the STALL bit is cleared Bit 3 STALL CPU stall control bit RN only in SWIM mode This bit is used to stall the CPU This bit is kept cleared if the device is not in SWIM mode This bit
29. is written by software to define the higher 8 address bits of Breakpoint 2 DM breakpoint register 2 low byte DM BKR2L Address 7F95h Reset value 1111 1111 FFh 7 6 5 4 3 2 i S BK2 7 0 rw rw rw rw rw rw rw rw Bits 7 0 BK2 7 0 Breakpoint 2 high byte value l This register is written by software to define the lower 8 address bits of Breakpoint 2 Doc ID 14024 Rev 3 ky UM0470 Debug module DM 4 12 7 4 DM control register 1 DM CR1 Address 7F96h Reset value 0000 0000 00h 7 6 5 4 3 2 1 0 WDGOFF Reserved BC 2 0 BIR BIW Reserved rw rw rw rw rw rw WDGOFF Watchdog control enable This bit must be set or cleared by software before the watchdogs WWDG and or Bit 7 IWDG are activated This bit has no effect if the hardware watchdog option is selected 0 Watchdog counters are not stopped while CPU is stalled by DM 1 Watchdog counters are stopped while CPU is stalled by DM Bit 6 Reserved BC 2 0 Breakpoint control Bits 5 3 These bits are set and cleared by software they are used to configure the breakpoints as shown in Table 4 BIR Break on read control This bit enables a breakpoint on a data read operation It is set and cleared by Bit 2 software 0 No break on data read 1 Break on data read BIW Break on write control This bit enables a breakpoint on a data write operation It is set and cleared by Bit 1 software 0 No break on data
30. m Slave DM 4 3j i when let i available SWTRAP bit lt EXT STALL Ba MANAGEMENT SALE gt SWTRF FV_ROM nap FV RAM DM CR2 PERIPHERALS Timers USB ENFCTx DM ENFCT Doc ID 14024 Rev 3 21 37 Debug module DM UM0470 4 3 4 3 1 4 3 2 4 3 3 4 3 4 4 3 5 22 37 Debug The DM registers can be read and written only through the SWIM interface STM8 core has no access to these registers Reset Once the SWIM is active and SWIM DM bit is set in SWIM CSR register a data read breakpoint at the reset vector address is automatically set due to the reset values of the debug module registers This breakpoint can be used to initialize the debug session Breakpoints The DM generates a stall to the core when a breakpoint is reached When the processor is stalled the host can read or modify any address in memory Access to the processor registers is explained in Section 3 7 CPU register access To restart the program execution the STALL bit in DM CSR2 must be cleared using the WOTF command of the SWIM protocol Abort To use the Abort function the host must write the STALL bit in the DM CSR2 using the SWIM WOTF command No interrupt is generated The core is stalled in the current state Using the SWIM commands the host can read and modify the status of the MCU If the CPU registers must be modified the procedure described in Section 3 7 CPU register
31. of the MCU s memory space Data EEPROM and program memory CPU registers A X Y CC SP can also be accessed These registers are mapped in memory and can be accessed in the same way as other memory addresses e Register peripherals and memory can be accessed only when the SWIM DM bit is set e Whenthe system is in HALT WFI or readout protection mode the NO ACCESS flag in the SWIM CSR register is set In this case it is forbidden to perform any accesses because parts of the device may not be clocked and a read access could return garbage or a write access might not succeed The SWIM can perform a MCU device software reset The SWIM pin can also be used by the MCU target application as a standard I O port with some restrictions if you also want to use it for debug The safest way is to provide a strap option on the application PCB Figure 2 SWIM pin external connections STM8 Application O 4 e e _ SWIM pin SWIM interface for tools 4 34 9 Jumper selection for debug purposes Doc ID 14024 Rev 3 7137 Single wire interface module SWIM UM0470 3 3 1 Note 8 37 Single wire interface module SWIM Operating modes After a Power On Reset powering of the device the SWIM is reset and enters in its OFF mode 1 OFF In this mode the SWIM pin must not be used as an I O by the application It is waiting for the
32. ot reset when a SRST command occurs 1 SWIM is reset when a SRST command occurs SWIM will re enter OFF mode HSIT High Speed Internal Clock is trimmed This bit is read only through SWIM only It cannot be accessed through STM8 bus It Bit 1 is set when the HSIT bit is set in the core configuration register and reset by an external reset 0 High Speed Internal Clock is not trimmed SWIM must remain in low speed mode 1 High Speed Internal Clock is trimmed SWIM high speed mode is allowed PRI SWIM access priority This bit can be read or written through SWIM only Usually the SWIM accesses to system resources are non intrusive SWIM having the lowest priority This can be overridden by setting this bit Bit O 0 Non intrusive access by SWIM to system resources low priority 1 Intrusive access by SWIM to system resources SWIM has priority CPU is stalled Note The SWD bit is located in the STM8 core configuration register Refer to the corresponding datasheet for information on this register 3 10 2 SWIM clock control register CLK SWIMCCR Address Offset 50CDh product dependent Reset value xxxx 0000 xOh 7 6 5 4 3 2 1 0 Reserved SWIMCLK rw Bits 7 1 Reserved must be kept cleared SWIMCLK SWIM clock divider This bit is set and cleared by software Bit 0 0 SWIM clock divided by 2 1 SWIM clock not divided by 2 Note this register is not present in some STMB8 devices 4 Doc I
33. s active in low speed bit format see Section 3 3 2 Figure 5 SWIM entry sequence SWIM Active SWIM pin tb 1 ms 500 us SWIM entry sequence Doc ID 14024 Rev 3 ky UM0470 Single wire interface module SWIM 3 3 3 3 1 Bit format The bit format is a Return To Zero format which allows synchronization of every bit Two communication speeds are available At SWIM activation the low speed is selected The high speed is selected by setting the HS bit in the SWIM CSR register with the SWIM protocol When entering SWIM mode during the RESET phase it is possible that the option bytes have not yet been loaded from non volatile memory to their respective registers Option byte loading is triggered by any internal or external reset In order to ensure proper system behavior the HS bit should not be set until the option byte loading is finished At the end of the option byte loading the HSIT bit in the SWIM CSR is set by hardware High speed bit format 1 bit is generated with ten HSI oscillator pulses The bit format is 2 pulses at O followed by 8 pulses at 1 for 1 value 8 pulses at 0 followed by 2 pulses at 1 for 0 value When the SWIM receives a data packet it will decode 1 when the number of consecutive samples at 0 is less or equal to 4 0 when the number of consecutive samples at
34. sequence to guarantee robustness in the SWIM active state entry The SWIM entry sequence is 4 pulses at 1 kHz followed by 4 pulses at 2 kHz The frequency ratio is detected and allows SWIM entry The ratio can be easily detected whatever the internal RC frequency The waveform of the entry sequence is shown in Figure 5 Note that the sequence starts and ends with the SWIM pin at 1 After the entry sequence the SWIM enters in SWIM active state and the HSI oscillator is automatically turned ON After this delay the SWIM sends a synchronization frame to the host Synchronization frame description A synchronization frame of 128 x HSI clock periods with the SWIM line at O is sent out by the MCU device to allow for the measurement of the RC by the debug host An advanced debug host can re calibrate its clock to adapt to the frequency of Internal RC Before starting a SWIM communication the SWIM line must be released at 1 to guarantee that the SWIM is ready for communication at least 300 ns Write OAOh in the SWIM CSR setting bit 5 allows the whole memory range and SRST command to be accessed setting bit 7 masks the internal reset sources Release reset which starts the option byte loading sequence Wait 1 ms for stabilization Once option byte loading has occurred and stabilization time is reached the CPU is in phase 8 STMBS is stalled and HSI 16 Mhz see STM8S datasheets for accuracy SWIM clock is at HSI 2 8 Mhz SWIM i
35. ter writing a new value in the Program Counter PCE PCH PCL Table 2 CPU register memory mapping in STM8 CPU register Memory location CU AO 00 o PCE 7F01h PCH 7F02h PCL 7F03h XH 7F04h XL 7F05h YH 7F06h YL 7F07h SPH 7F08h SPL 7F09h CC 7FOAh SWIM communication in Halt mode To maintain the communication link with the debug host the HSI oscillator remains on when the MCU enters Halt mode This means that halt mode power consumption measurements have no meaning when the SWIM is active The NO ACCESS bit in the SWIM CSR register is set when the system is in HALT WFI or readout protection mode This means the bus is not accessible in this case The OSCOFF bit in the SWIM CSR register is used to switch off the oscillator In this case debug control is lost as long as the device is in Halt mode and the SWIM pin is high The only way to recover the debug control is to induce a falling edge on SWIM pin this will re enable the HSI oscillator Doc ID 14024 Rev 3 ky UM0470 Single wire interface module SWIM 3 9 Physical layer During the communication the SWIM pin will be in pseudo open drain configuration The SWIM pin in the device is capable of sinking 8 mA when it drives the line to 0 The external pull up on the SWIM line should be sized in such a way that the maximum rise time t of the SWIM line should be less than 1 sampling period of the bit which is 100 ns
36. y space If a byte D i has not been written when the following byte D i 1 arrives D i 1 will be followed by a NACK In this case the Host must send D i 1 again until it is acknowledged For the last byte if it is not yet written when a new command occurs the new command will receive a NACK and will not be taken into account If SWIM DM bit is cleared WOTF can only be done on SWIM internal registers SWIM communication reset In case of a problem during communication the host can reset the communication and the on going command by sending 128 x HSI clock periods low on the SWIM pin If the SWIM logic detects that the SWIM pin is low for more than 64 x HSI clock periods it will reset the communication state machine and will switch the SWIM to low speed mode SWIM CSR HS 0 This is to allow for variation in the frequency of the internal RC oscillator In response to this communication reset SWIM will send the synchronization frame which is 128x HSI oscillator periods low on DBG pin Doc ID 14024 Rev 3 15 37 Single wire interface module SWIM UM0470 3 7 3 8 16 37 CPU register access The CPU registers are mapped in the STM8 memory and they can be read or written directly using the ROTF and WOTF SWIM commands Write operations to the CPU registers are committed only when the CPU is stalled To flush the instruction decode phase you must set the FLUSH bit in the DM control status register 2 DM CSR2 af
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