Lab Report Outline - the GMU ECE Department
Contents
1. following windows to be used in this simulation e Source e Signals e Wave KodelSim SEEE 5 4d source ors testbench vhd P ty i E Ei panai I E m m 1 ee fe pe cas othr oes ee author Dr Ron Hayne view signals SOUTCE a pie Date May 26 2003 sone 4 Course ECES32 frie WAYE EEN File Name ord testbhench vhd wave 6 Design Units ORS Testbench l A Purpose of Code Tis 2s top terii bs bith a is provided for tli taci ist noe Hardware modeled This testhench crf BEBEBE 5 In the Signals window select View gt Wave gt Signals in Region The signals from the test bench will be loaded into the Wave window so their values can be traced during the simulation Wave default oo0 l Uns 0 ns sd Y 2 p e e a 2 1 d a ar a a Allh AA Note You can also select View gt Wave gt Signals in Design to trace signals internal to your design 6 Before starting the simulation make sure the Run Length is set to an appropriate interval in the main ModelSim window For this example the testbench was built with a 100 ns period ModelSim SE EE 34d dit Design View Run Macro Options window Help eS ee A eae a Toh Sd z WBA Wey eB Wave add Wave simon testhench Volk 15 gt 7 Now you can run the simulation for 100 ns using the Run menu in the main ModelSim window or using the Run button in the toolbar in either the main or wave win2. Now you are ready to begin editing your VHDL source code and compiling your project for simulation Creating Editing VHDL Files There are several ways to create edit VHDL source files prior to compilation and simulation e Use the Notepad editor from within ModelSim e Create the files outside of ModelSim and Import them into your project e Use a UNIX editor like vi emacs or pico e Use an external text editor and upload download the files to cpe02 For this part of the tutorial use one of these methods to create the VHDL files or3 vhd and or3_testbench vhd or3 vhd Author Dr Ron Hayne Date z April oy 2003 WOuUrse Hem oo7 File Name t OFS 00 Design Units ORI Purpose of Code This is an example circuit provided for gt the Mentor Graphics Tutorial Hardware modeled Behavioral model of a 3 1input OR gate Model Limits None Known Known Errors None known Design Library gt work Dependencies None gt Environment Simulator Mentor Graphics ModelSim V5 4d m Plhetrorm Uns SunOS 5 6 Change List most recent on top Date Who What O7Jun03 rjh Update to ESA coding stds 13Apr03 rjh Creation library IEEE use IEEE std_logic_1164 all entity OR3 is OCL A an Sed logic B in Sed logic C 3 in std logic A out sta Logic end Ons architecture BEHAVE of begin OR3 is 2 x BO B Or C arter 10 ns end B
3. you can create or import new VHDL files edit existing files as well as compile them by selecting Options gt Edit Project from the main window Import work a Add to Library Compiling and Simulating VHDL 1 Compile the file or3 vhd into your work library using the Compile button on the toolbar DE by selecting Design gt Compile from the main ModelSim window Compile HDL Source Files dit Design View Run Macro Options Window J Yocom reportprogress J00 work work home dab statvriaynemgc wWork ecedae _labsfora vAdy Model Technology Madelsim SEEE vcom 54d Compiler 2000 03 sep 15 2000 Loading package standard Loading package std_logic_1l1b4 Compiling entity ors Compiling architecture behave of ors ModelSim 2 Next you need to compile the file or3_testbench vhd which contains VHDL 93 syntax into your work library Before compiling you need to set the Default Options for the compiler to Use 1993 Language Syntax This only needs to be done once since these compiler options will be retained unless reset 3 Now its time to load the design unit using the Load Design button from the toolbar ora ayo Rae Rot EE er Rae ane SaaS e E F A mm ee ee Seren ce Note Load the or3_testbench entity since this is what drives the simulation and provides the test vectors to the or3 entity 4 Once the design is loaded use the View menu in the main ModelSim window to open the
4. EHAVE or3_test_bench vhd Reno Date Course File Name Design Units PULDOSe OL Code Hardware modeled Model Limits KNOWN Fie rors Design Library Dependencies Sse AMAA ie Ores mae Simulator Platitorm Dre Ron Hayne May 26 2003 ECE o2 or3_testbench vhd OR3_Testbench This is a top level testbench for the OR3 example which is provided for the Mentor Graphics Tutorial This testbench creates an instance of the OR3 circuit and then drives the inputs and checks the results VHDL 93 Syntax report None known work OR3 Mentor Graphics ModelSim V5 4d UNI DUNO Duc3 Change List most recent on top Date Who What Q7Jun0O3 rjh Update to ESA coding stds 26May03 xr yh Creati library TEBE use IEEE std_logic_1164 use JERE S td logic uns i entity OR3_Testbench is enc ORS Test bench on AL One dral arehuveecture LPestbench of ORS Test bench 2s Signal Input Suewog re Voc Or Gown o 0 lt TOUT Signal A lt Sed ogee component OR3 POLE Ay aan Std Tog G B z Sn SEC _bog es Cc an Cd boo aC 2 amp Our Src Logie end component begin Component Instantiation Tested Circu urt 2 OR3 port map Cycle through test vectors and evaluate the results process begin Wake tor 100 iris case Input is when 000 gt assert 4 O report Test Failed when others gt
5. Mentor Graphics Tutorial This document is intended to assist ECE Students taking ECE 331 Digital Systems Design ECE 332 Digital Design Lab ECE 445 Computer Organization and ECE 545 Introduction to VHDL in setting up their computing environment for using Mentor Graphics tools on cpe02 gmu edu It also contains a basic tutorial for running VHDL simulations using the ModelSim software The Mentor Graphics software is designed to operate in an X terminal environment on unix workstations MGC is currently installed on cpe02 gmu edu This means that MGC software can be accessed from the X terminals in Room 133 of S amp T II as well as from other on off campus X terminals e g Linux ssh or under MS Windows using the X windows emulator Cygnus XFree86 via gmu ftp All MS Windows machines available in the ECE Departmental Labs located in S amp T II rooms 203 and 265 as well as S amp T I rooms 2A and 2B have this X terminal emulator installed on them To start this terminal and connect to cpe02 simply click on the cpe02 icon visible on the desktop in the top left corner of the screen Please keep in mind that an off campus access over a dial up connection is less than satisfactory in either environment although suitable performance may be possible through a DSL or Cable Modem connection Initial Setup Specific Instructions for setting up your computing environment on cpe02 gmu edu 1 Log in to cpe02 using the username and password given t
6. assert 42 1 report Test Failed end case Iput s Inpuc TOOT end process end Testbench Notepad Editor 1 From the ModelSim main window select File gt New gt New Source Modelsin SE EE 3 40 le Edit Design View Run Macro Options Window Tim port Source q Mew Project ranscript i ranscript As r Transcript Options and enter the name of the file you want to create Create Project Source File 2 You can now use the Notepad editor to create edit your VHDL source code Importing VHDL source files 1 Create VHDL files in your project directory HOME mgc_home ece332_labs e Create edit the files using a UNIX editor OR e Use a web browser of ftp program to download upload the files to cpe02 2 From the ModelSim main window select File gt New gt Import Source Modelsin SE EE 3 40 e Edit Design View Run Macro Options Window Hel P Mew BSA Open P Mew Delete PI Mew source Change Directory at Ear ee at 4 koir GCroiarct Wey T iL a rl Tia a a eee 5 aE TASC LIL cave Transcript As a k j p i pa r m w maa i Hear Iranscripi Options F and use the Browse button to select your previously created loaded file Import Project Source File Select File ora testhench vhd Files of type PO 3 From here you can also choose to edit your VHDL file in Notepad just to make sure Editing Your Project At any time while using ModelSim
7. dows The values of the signals will be updated in the Signals window and traced in the Waves window Wave default Window ile Edit Cursor zoom Format Window 54 lip k EF fors_testbench input 000 o ford testhenchz U Ons Note The values shown in the Waves window are relative to the cursor which will be discussed later 8 Continue running the simulation using the Run command until all input combinations have been applied to the test circuit 000 to 111 Alternately you can use the buttons described below to control starting stopping and restarting the simulation Note Use the Run All command with caution Main Window Toolbar 1 HodelSim File Edit Design View Run Macro Options Window Help Ee H 4RR HP cP se er s j S S E F Fi S o F r Reloads the design and resets the simulation time to zero Ra Run the current simulation for the specified run length Continue the current simulation run until the end of specified run length or until it hits a breakpoint or specified break event Run All Run the current simulation forever or until it hits a breakpoint or specified break event Stop the current simulation run Steps the current simulation to the next VHDL statement 9 The Wave window can now be used to examine the values of signals at any time during the simulation using the buttons described below Wave Window Toolbar wave default File Edit Cursor Zoom Fo
8. he following ModelSim SE EE Quick Guide Provides quick reference to important commands variables and tools ModelSim SE EE User s Manual Describes how to configure and use ModelSim including topics such as design libraries VHDL simulation the GUI SDF timing annotation etc ModelSim SE EE Command Reference Describes ModelSim commands and associated options that are used from a command prompt or within macro files Includes a section on command syntax ModelSim SE EE Tutorial Leads you step by step through common tasks such as compilation simulation debugging and using the Wave window The same documentation is also available directly on cpe02 using Adobe Acrobat Reader To read the documentation at your unix prompt type acroread amp After the program starts may take a few minutes open the file opt mgc fpgadv40 Modeltech docs se_docs pdf The next time you start the acrobat reader this file will be in the list of files from which you can select so you won t need to type it in each time
9. o you in class 2 Open the Workspace Menu by clicking with right mouse button anywhere on the desktop go to the Tools menu and click on Terminal The terminal window will open with the user dab path gt prompt inside The user part of the prompt shows your user name and path your current directory 3 Prepare the working directory by typing INGVAR at the prompt This command will create the directory mgc_work and copy example files to this directory Note This step should only be performed once otherwise your directory and work will be reinitialized ModelSim Start up You are now ready to start the ModelSim software and run a sample VHDL simulation 1 At the prompt type cd mgc_work to change your working directory Note Always start ModelSim from this directory Otherwise the software may have difficulty finding and modifying files 2 At the prompt type vsim amp to start the ModelSim software Note The amp causes the command to run in the background keeping the UNIX prompt available for further commands 3 Upon opening ModelSim for the first time you will see a Welcome to ModelSim dialog box If this screen is not available you can enable it by selecting Help gt Enable Welcome from the Main window It will then display the next time you start ModelSim Welcome to ModelSim 54d By clicking the Always open last project radio button you can skip this screen and proceed directly to your pr
10. oject 4 To create a Project to organize all your laboratory work click the Create a Project button In the Create a New Project dialog box select the Create a new project from scratch radio button then click the Browse button to select the New Project s Home Simply click OK to create the new project directory in your mgc_work directory where you started ModelSim Files of type Dae cancel Next type in ece332_1abs or other appropriate name in the New Project Name box Create a New Project fhomedab stattrhaynemaoac work ecedde labs Selecting OK causes the project directory to be created with a default working library In the dialog box that asks if you want to create a new HDL source file for your project click No 5 Finally to open your new project and begin work select it from the pull down menu arrow to the right of the Open Project button and text box Welcome to ModelSim 5 4d ae Crear apaec ao ei ee homefdab statmayneringe workfeceda labsfecedga2_labs mpt ontimgceTpqadva de Modeltech bin examples projectsmixedmixed mpt optrmgcfpgady4 dy Modeltech bin examples projectsmixed mixed mot e optrmgcifpgadr4 A Modeltechbin Jexamples projectsiverilogiverilog mpf o optrmgacipgadi4 i Modeltechbin Jexamples projectseyhdivhdl rmpf Then click Open Project or Done in the Welcome to ModelSim dialog box
11. rmat window Add Cursor Add a cursor to the center of the waveform pane 10 In the Wave window Zoom in 2x and select the signal or3_testbench z Next use Find Next Transition to advance the cursor to 110 ns where Z changes from 0 to 1 Wave default File Edit Cursor 400m Format Window a fora_testbenchvinput io jo00 ip 0 1 O10 O11 if 00 i 0 if 10 ia 11 OOO 21 0 1 0 1 ord testhbenchyz You can see from the signal values shown that the simulation is correctly modeling the behavior described in the VHDL source code for or3 vhd Specifically the signal assignment statement below indicates that the signal Z should change to 1 10 ns after C changes to 1 at 100 ns Z a A or B Or C after 10 ns 11 Lastly you can print the waveforms from the simulation From the menu in the Wave window select File gt Print Postscript or use the Print button on the toolbar Choose Print command and enter Ip Use the Signal Selection and Time Range radio buttons to control the waveforms to be printed To obtain a printout of your VHDL source code from your project directory at the Unix prompt type enscripi PpIp oro vhd These commands will send your printouts to a pay for print printer MGC Software Documentation Further documentation on the MGC software is available on line From the main ModelSim window select Help gt SE EE Documentation gt SE EE Bookcase for access to t
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