TVME8240 - TEWS TECHNOLOGIES
Contents
1. 8 2 8 8 Reset Register sssssuse 8 2 8 4 Status Register 8 2 4 Local Space 1 Address Map 8 2 5 Local Space 2 Address Map 8 2 6 Local Space 3 Address Map 8 3 IP Interrupts esses nennen nnn 9 DIR 9 1 Board UO Overview RE ER KEER EE RE 9 2 JUMP si Et ee lid ii 9 2 1 Boot Jumper 9 2 2 VME System Controller Jumper Ha RE N EE N EE EE Sed 9 3 1 PAIL CED EE AN ER arena 9 3 2 FUSE LED u u n RSA aio 9 3 3 ACTIED cocinada EE are 9 3 4 SYS EED rim rd de dis GE MERLUICUII eC 9 4 1 RST Switch eene 9 4 2 ABT Sie RE eterne ose tddi TVME8240 User Manual Issue 1 2 9 TEWS S TECHNOLOGIES Page 5 of 70 TEWS S TECHNOLOGIES 9 5 el E CG 59 9 5 1 VME Interface Connectors ese ee ee ee ee ee n ee ee ee ee ee ee ee ee ee ee ee 59 9 5 11 VME Ae e e TEE 59 95 1 2 VME e e e 60 9 5 2 IP Interface Connectors ee ee Re Re Re Re Re Re ke Re ee ee ee ee ee ee ee ee ee ee ee 61 9 5 2 1 IP Aere Lulu te TE 61 9522 IP enne TEE 61 9 5 3 PCI Expansion Connector ees se n AA ee ee ee ee ke ee 62 9 5 4 Serial Interface Connectors ee ee ee ee2. a a ee ee ee ge ee 20 3 5 2 Status Register OXFFE4 Oo00O1 entente sinet 21 3 5 8 LED Register OXFFE4 0003 ees ee ee ee ee ee ee de Ge ee ee AA ee cnn nn ee n nennen nnns nen 21 4 lae EE uuu ET 23 4 1 MPC8240 Configuration Register AR RAAK KEER KRAAK u u u J T 23 4 1 1 Configuration Register Access 23 4 1 2 Configuration Register Gettnge eee 24 4 2 MPEB240 EPIC Register eke ees ee ee ene nee eee ee c nio aa see aera wee ee ee ee 27 4 2 1 EPIC Register Access iis esse ee ee ee ee ke ee se ee AA ee Ge ee Ge ee n ran 27 4 2 2 EPIC Register Settings ener nnns 27 4 2 2 1 Global Configuration Register GCR ee RR AA ee 27 4 2 2 2 EPIC Interrupt Configuration Register EICH 27 4 2 2 3 Serial Interrupt Vector Priority Registers SVPR 27 4 2 2 4 EPIC Register Programming sse enne 27 4 3 ucc 28 4 3 1 IAC EE PROM EE RO OE OR EE 28 TVME8240 User Manual Issue 1 2 9 Page 4 of 70 5 FLASH PROGRANMNMIINGQ 5 1 8 bit Wide Socket Boot FLASH 5 2 64 bit Wide On Board Memory FLASH 6 VME BUS INTERFACE ccce 6 1 Universe ll PCI Header 6 2 Universe ll Power Up O
3. z x Lu 8 B o m SYSCON Op Iesst HB EE By z Y IP Slot A ul Ro olje m tn lt z n a D ul ud IP Slot B FAIL FUSE LED ACTISYS LED El SERIAL B ADAPTER CONNECTOR RTS SWITCH ABT SWITCH z 3 A d q IP Slot C n 2 e E ollo a a IP Slot D 12C PLD JTAG CPU JTAG PCI EXPANSION CONNECTOR Figure 9 1 Board I O Overview TVME8240 User Manual Issue 1 2 9 Page 55 of 70 TEWS S TECHNOLOGIES 9 2 Jumper 9 2 1 Boot Jumper Boot Jumper Execute Memory FLASH Program after board initialization Jumper Installed Execute PMON Bug Program EIERE after board initialization Table 9 1 Boot Jumper The boot jumper status can be read in the Utility Status Register After board initialization the boot jumper determines the address of the next program instruction The 8 bit wide socket Boot FLASH must always be installed and provide the board initialization code at the system reset vector If used the first instruction in the Memory FLASH must reside at address OxFFOO 0100 9 2 2 VME System Controller Jumper VME SYSTEM CONTROLLER JUMPER Jumper 1 2 Installed Not VME System Controller VME System Controller Auto Configuration Jumper 2 3 Installed No Jumper Installed VME System Controller Table 9 2 VME System C
4. eee TABLE 5 3 BOOT FLASH SECTOR MAP emere TABLE 5 4 MEMORY FLASH COMMAND CYCLES eee TABLE 5 5 MEMORY FLASH AUTO SELECT CODES eee TABLE 5 6 MEMORY FLASH SECTOR MAP eee TABLE 6 1 UNIVERSE II PCI HEADER ener TABLE 7 1 21143 PCI HEADER ee u ee ee see ee ee ee ee se ee ee ee ee ee ee ee ee ge ee ee ee ee ee ee ee TABLE 7 2 21143 CONFIGURATION EEPROM SETTINGS eee TABLE 7 3 21143 CONFIGURATION EEPROM CONTENT eee TABLE 9 1 PCI9030 PCI HEADER nemen TABLE 9 2 PCI9030 LOCAL CONFIGURATION REGISTER eese TABLE 9 3 PCI9080 CONFIGURATION EEPROM SETTINGS TABLE 9 4 PCI9080 CONFIGURATION EEPROM CONTENT enne TABLE 9 5 PCI9030 LOCAL SPACE ASSIGNMENT eee TABLE 9 6 LOCAL SPACE 0 ADDRESS MAP IP INTERFACE REGISTER TVME8240 User Manual Issue 1 2 9 TEWS S TECHNOLOGIES Page 7 of 70 TEWS S TECHNOLOGIES TABLE 9 7 REVISION ID REGISTER comic eri D Rr ERE DRM n ERR ERE ee OR EP a e eee 47 TABLE 9 8 IP X CONTROL REGISTER u u u uuu ee ee ee ge ee Ge ee Ge ee Ge ee ee rennen nr AR rst ense nr ee ee ee ee ke ee Sasa 48 TABLE 9 9 RESET REGISTER u dea tre etn RE sata ert eet eee veda aite ie e rn RRE Bee eed un 49 BR CENTER 52 TABLE 9 11 LOCAL SPACE 1 ADDRESS MAP IP A D ID INT VO SPACE ee se ee se ee ee ee ee ee ee ee 52 TABLE 9 12 LOCAL SPACE 2 ADDRESS MAP
5. Bit Name Description 15 MSB Hn Read 13 Undefined 12 i 11 Write 10 No Effect 9 8 7 6 5 Read 4 FPGA Logic Revision ID 8 PENJO Write 2 No Effect 1 0 LSB Table 8 7 Revision ID Register TVME8240 User Manual Issue 1 2 9 Page 47 of 70 TEWS S TECHNOLOGIES 8 2 3 2 IP X Control Registers The IP X Control Registers can be used to control IP interrupts recover time and clock rate There is one IP X Control Register for each IP Slot A D Bit Name Description 15 MSB si Read 13 Undefined 12 11 Write 10 No Effect Should be written with O s 9 8 7 0 IP Interrupt 1 Disabled bis 1 IP Interrupt 1 Enabled 6 0 IP Interrupt 0 Disabled ER 1 IP Interrupt O Enabled 5 0 IP Interrupt 1 Level Sensitive INE RENSE 1 IP Interrupt 1 Edge Sensitive 4 0 IP Interrupt 0 Level Sensitive Eee 1 IP Interrupt O Edge Sensitive 3 0 IP Error Interrupt Disabled EER 1 IP Error Interrupt Enabled 2 0 IP Timeout Interrupt Disabled TIME INTER 1 IP Timeout Interrupt Enabled 1 0 IP Recover Time Disabled REESEN 1 IP Recover Time Enabled 0 0 IP Clock Rate 8 MHz LSB SEINE 1 IP Clock Rate 32 MHz Table 8 8 IP X Control Register After power up or board reset all bits in the IP X Control Registers are cleared If IP recover time is enabled for an IP slot an IP cycle for this slot will not begin until the IP recover tim
6. Ox0E00 0x0000 OxOFOO 0x0000 0x0000 Ox0000 OxO800 Ox0001 0x40 Ox0400 0x0001 0x0000 0x0001 0x0200 0x0001 oxoooo 0x0000 0x50 OxD541 0x60A0 0x1541 Ox20A2 Ox1541 Ox20A2 Ox1501 Ox20A2 0x60 Ox0000 Ox0000 0x0800 0x0081 0x0400 0x0201 0x0100 Ox0001 0x70 Ox0280 0x0001 0x0030 0x0049 0x007A Ox4000 0x0224 0x9252 0x80 Ox0000 Ox0000 0x0000 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF Ox90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxAO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxBO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxCO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Table 8 4 PCI9030 Configuration EEPROM Content 8 2 IP Interface The IP FPGA provides the interface between the PCI9030 local bus and the IP slots The IP FPGA also provides the IP Interface Control Registers The IP FPGA is configured at power up or board reset by an on board serial PROM Board Initialization software should verify successful FPGA configuration in the Utility Status Reg
7. 1141043 Ir el N OE EE N 70 11 10 5 od ea EE RE N AE N EE EE N 70 TVME8240 User Manual Issue 1 2 9 Page 6 of 70 List of Figures FIGURE 1 1 BLOCK DIAGRAM TVME8240 FRONT WO FIGURE 1 2 BLOCK DIAGRAM TVM8240 BOARD LAYOUT FRONT I O FIGURE 10 1 BOARD VO OVERVIEW eese nnnm TABLE 1 1 FEATURES TVMES8240 senes TABLE 2 1 PCI ARBITER ASSIGNMENT ee ee se ee see ee ee ee ee ge ee Ge ee ee ee ee ee ee ee TABLE 2 2 PCI IDSEL ASSIGNMENTT eren TABLE 2 3 EPIC SERIAL INTERRUPT ASSIGNMENT eee TABLE 2 4 STATUS INDICATORS nennen TABLE 3 1 ADDRESS MAP PROCESSOR VIEW eee TABLE 3 2 SUPPORTED TRANSFER GLEN TABLE 3 3 PCI ADDRESS TRANSLATION eene TABLE 3 4 ADDRESS MAP PCI MEMORY MASTER VIEW eene TABLE 3 5 ADDRESS MAP PCI VO MASTER VIEW eee TABLE 3 6 ADDRESS MAP PERIPHERAL DEVICES DETAIL TABLE 3 7 ADDRESS MAP UTILITY REGISTER DETAIL eene TABLE 3 8 CONTROL REGISTER iese rte ttt rein ri aida TABLE 3 9 STATUS REGISTER eene nennen TABLE 3 10 EED REGISTER Lii reir Lie ete e TABLE 4 1 MPC8240 CONFIGURATION REGISTER SETTINGS TABLE 4 2 l2C EEPROM CONTENT nnn ennemi TABLE 5 1 BOOT FLASH COMMAND CYCLES eee TABLE 5 2 BOOT FLASH AUTO SELECT CODES
8. OD c The serial port signals are shown in the TVME8240 pin function E g for serial port A the external TXD line must be connected to pin 2 RXD input of the serial port A connector not to pin 3 TXD output The serial interface signals are also available on the VME P2 connector For each serial port only one connection scheme is allowed at a time either via the VME P2 connector or via the DB9 connector at the front plate Serial port A mode is RS232 always Serial port B mode is configurable by an adapter card Factory default is RS232 adapter card A RS422 adapter card can be ordered 9 5 5 LAN Interface Connector Pin Signal TD TD RD NC NC RD NC NC Table 9 10 LAN Connector 8P RJ45 oc AJOIN 00 TVME8240 User Manual Issue 1 2 9 Page 65 of 70 TEWS S TECHNOLOGIES 10 Installation and Use Notes 10 1 NVRAM Real Time Clock Control The TVME8240 provides a M48T59 NVRAM RTC device with a snaphat battery plugged on top The snaphat battery provides power for the SRAM cells when the main power supply is off The TVME8240 is shipped with the snaphat battery installed on top of the M48T59 NVRAM device The Real Time Clock function of the M48T59 device is turned off by default to save battery energy If the M48T59 Real Time Clock function has been turned off factory default it must be enabled again before using any other board resources e g
9. TVME230 IP Span or Motorola PMC Span TVME8240 User Manual Issue 1 2 9 Page 12 of 70 TEWS S TECHNOLOGIES 2 3 1 PCI Arbiter Assignment The TVME8240 uses the MPC8240 integrated PCI arbiter for arbitration of PCI devices The MPC8240 integrated PCI arbiter provides PCI arbitration for the MPC8240 itself and up to five external PCI Masters The TVME8240 uses the following PCI arbiter assignment for the various PCI devices PCI Arbiter PCI Device GNT REQ Line 0 Universe ll VME PCI Bridge 1 21143 LAN Controller 2 SYM53C875 SCSI Controller 3 PCI Expansion e g PMC span 4 N A Table 2 1 PCI Arbiter Assignment 2 3 2 PCI IDSEL Assignment The MPC8240 CPU provides capability for generating PCI configuration cycles The TVME8240 uses the following IDSEL assignment for the various on board PCI devices Device Number Address Line PCI Device 0d13 ObO 1101 AD13 Universe ll VME PCI Bridge 0d14 ObO 1110 AD14 21143 LAN Controller 0d15 ObO 1111 AD15 SYM53C875 SCSI Controller 0d16 0b1_0000 AD16 PCI9030 PCI Target Chip Table 2 2 PCI IDSEL Assignment TVME8240 User Manual Issue 1 2 9 Page 13 of 70 TEWS TECHNOLOGIES 2 4 VME Bus Interface The TVME8240 uses the Universe ll VME PCI Bridge Tundra to build the VME interface The Universe ll VME PCI Bridge provides a 32 bit address 32 bit data VME interface Please refer to the Universe ll
10. 16 0x0800 0x66 Local 0x3C LSW Local Chip Select 0 CSOBASE 15 0 0x0081 0x68 Local 0x42 MSW Local Chip Select 1 CS1BASE 31 16 0x0400 Ox6A Local 0x40 LSW Local Chip Select 1 CS1BASE 15 0 0x0201 0x6C Local 0x46 MSW Local Chip Select 2 CS2BASE 31 16 0x0100 Ox6E Local 0x44 LSW Local Chip Select 2 CS2BASE 15 0 0x0001 0x70 Local 0x4A MSW Local Chip Select 3 CS3BASE 31 16 0x0280 0x72 Local 0x48 LSW Local Chip Select 3 CS3BASE 15 0 0x0001 0x74 Local 0x4E Serial EEPROM Write Protect PROT_AREA 7 0 0x0030 0x76 Local 0x4C LSW Interrupt Control Status INTCSR 15 0 0x0049 0x78 Local 0x52 MSW Miscellaneous CNTRL 31 16 0x007A Ox7A Local 0x50 LSW Miscellaneous CNTRL 15 0 0x4000 0x7C Local 0x56 MSW General Purpose I O Control GPIOC 31 16 0x0224 Ox7E Local 0x54 LSW General Purpose I O Control GPIOC 15 0 0x9252 0x80 Local 0x72 MSW Power Management Data Select 0x0000 0x82 Local 0x70 LSW Power Management Data Select 0x0000 0x84 Local 0x76 MSW Power Management Data Scale 0x0000 0x86 Local 0x74 LSW Power Management Data Scale 0x0000 Table 8 3 PCI9030 Configuration EEPROM Settings TVME8240 User Manual Issue 1 2 9 Page 44 of 70 TEWS S TECHNOLOGIES EEPROM 0x00 0x02 0x04 0x06 0x08 OXOA 0x0C OxOE Address Ox00 Ox9030 Ox10B5 0x0280 0x0000 0x0680 0x0000 0x2030 0x1498 0x10 Ox0000 Ox0040 0x0000 0x0100 Ox4801 Ox4801 0x0000 0x0000 0x20 Ox0000 Ox4CO6 0x0000 0x0003 OxOFFF OxFFOO OxOFFF OxFCOO 0x30
11. 4 1 2 Configuration Register Settings TEWS S TECHNOLOGIES Register Offset Register Description Size Access Type Setting Byte 0x00 Vendor ID 2 R 0x1057 Motorola 0x02 Device ID 2 R 0x0003 MPC8240 0x04 PCI Command Register 2 R W 0x0006 0x06 PCI Status Register 2 R C Status 0x08 Revision ID 1 R Reset_Value 0x09 Standard Programming 1 R 0x00 Host Interface Ox0A Subclass 1 R 0x00 OXOB Class Code 1 R 0x06 Host 0x0C Cache Line Size 1 R W Reset Value 0x0D Latency Timer 1 R W Reset_Value OxOE Header Type 1 R 0x00 OxOF BIST Control 1 R 0x00 0x10 Local Memory Base Address 4 R W Reset_Value Register LMBAR 0x14 Peripheral Control Status 4 R W OxFCFO 0000 Register Base Address PCSRBAR 0x30 Expansion ROM Base 4 R 0x0000 0000 Address 0x3C Interrupt Line 1 R W Reset_Value 0x3D Interrupt Pin 1 R 0x01 Ox3E MAX GNT 1 R 0x00 Ox3F MAX LAT 1 R 0x00 0x40 Bus Number 1 R W 0x00 0x41 Subordinate Bus Number 1 R W 0x00 0x46 PCI Arbiter Control Register 2 R W 0x8000 0x70 Power Management 2 R W 0x0000 Configuration Register 1 0x72 Power Management 1 R W 0x40 Configuration Register 2 0x73 Output Driver Control 1 R W 0xCO Register 0x74 Clock Driver Control 2 R W 0x0000 Register 0x78 Embedded Utilities Memory 4 R W OxFCFO 0000 Block Base Address EUMBBAR 0x80 Memory Starting Address 4 R W 0x4040_ 4000 0x84 Registers 0x4040_4040 0x88 0x8C
12. EROMBRD 0x0000_0000 0x3C Local Chip Select 0 CSOBASE 0x0800_0081 0x40 Local Chip Select 1 CS1BASE 0x0400 0201 0x44 Local Chip Select 2 CS2BASE 0x0100 0001 0x48 Local Chip Select 3 CS3BASE 0x0280_0001 0x4C Serial EEPROM Interrupt Control 8 Status PROT AREA 0x0030 0049 INTCSR 0x50 Miscellaneous CNTRL 0x007A 4000 0x54 General Purpose VO GPIOC 0x0224 9252 Shown values are register values after serial EEPROM configuration Table 8 2 PCI9030 Local Configuration Register TVME8240 User Manual Issue 1 2 9 Page 42 of 70 8 1 3 PCI9030 Configuration EEPROM Basic PCI9030 register configuration is loaded from an on board serial EEPROM at power up or board TEWS S TECHNOLOGIES reset EEPROM Register Offset Register Description Register Bits Value Offset Affected 0x00 PCI 0x02 Device ID PCIIDR 31 16 0x9030 0x02 PCI 0x00 Vendor ID PCIIDR 15 0 0x10B5 0x04 PCI 0x06 PCI Status PCISR 15 0 0x0280 0x06 PCI 0x04 PCI Command Reserved 0x0000 0x08 PCI 0x0A Class Code PCICCR 15 0 0x0680 OXOA PCI 0x08 Class Code Revision PCICR 7 0 0x0000 PCIREV 7 0 0x0C PCI 0x2E Subsystem ID PCISID 15 0 0x2030 OxOE PCI 0x2C Subsystem Vendor ID PCISVID 15 0 0x1498 0x10 PCI 0x36 MSB New Capability Pointer Reserved 0x0000 0x12 PCI 0x34 LSB New Capability Pointer CAP PTR 7 0 0x0040 0x14 PCI 0x3E Max Lat Max Gnt Reserved 0x0000 0x16
13. Extended Memory Starting 4 R W 0x0000 0000 Address Registers 0x0000 0000 TVME8240 User Manual Issue 1 2 9 Page 24 of 70 TEWS S TECHNOLOGIES Register Offset Register Description Size Access Type Setting Byte 0x90 0x94 Memory Ending Address 4 R W 0x4F4F_4F3F Registers 0x4F4F_4F4F 0x98 0x9C Extended Memory Ending 4 R W 0x0000 0000 Address Registers 0x0000 0000 OxAO Memory Bank Enable 1 R W 0x01 Register OxAS3 Page Mode Register 1 R W 0x00 OxA8 Processor Interface 4 RAN OxFF14 1298 Configuration Register 1 OxAC Processor Interface 4 R W 0x0000 0600 Configuration Register 2 0xB8 ECC Single Bit Error 1 R W 0x00 Counter Register OxB9 ECC Single Bit Error Trigger 1 R W 0x00 Register 0xCO Error Enabling Register 1 1 R W Reset_Value 0xC1 Error Detection Register 1 1 R C Status 0xC3 Processor Internal Bus Error 1 R C Status Status Register 0xC4 Error Enabling Register 2 1 R W Reset Value 0xC5 Error Detection Register 2 1 R C Status 0xC7 PCI Bus Error Status 1 R C Status Register 0xC8 Processor PCI Error 4 R Reset Value Address Register OxEO Address Map B Options 1 R W 0xCO Register AMBOR OxFO Memory Control 4 R W 0x03E8_0000 Configuration Register 1 MCCR1 OxF4 Memory Control 4 R W 0x0A40 OF8C Configuration Register 2 MCCR2 OxF8 Memory Control 4 R W 0x0620_0000 Configuration Register 3 MCCR3 OxFC Memory Control 4 R W 0x2500 2220 Confi
14. Interrupt 1 Request Write 0 No Effect 1 Clear Edge Sensitive IP B Interrupt 1 Status Read 0 No Interrupt 0 Request on IP B 2 INTO B 1 Active IP_B Interrupt 0 Request Write 0 No Effect 1 Clear Edge Sensitive IP B Interrupt 0 Status Read 0 No Interrupt 1 Request on IP A 1 INTI A 1 Active IP A Interrupt 1 Request Write 0 No Effect 1 Clear Edge Sensitive IP A Interrupt 1 Status TVME8240 User Manual Issue 1 2 9 Page 51 of 70 TEWS S TECHNOLOGIES Bit Name Description Read 0 No Interrupt 0 Request on IP A 0 1 Active IP A Interrupt O Request LSB Te Write 0 No Effect 1 Clear Edge Sensitive IP_A Interrupt O Status Table 8 10 Status Register 8 2 4 Local Space 1 Address Map The PCI9030 local space 1 is used for the IP A D ID INT and VO space The PCI base address for local space 1 is PCIBAR3 at offset Ox1C in the PCI9030 PCI configuration register space Offset Size Description Base PCI Base Address 3 Byte Start End 0x0000 0000 0x0000 007F 128 IP A I O Space 0x0000 0080 0x0000 OOBF 64 IP A ID Space 0x0000 00CO 0x0000 00FF 64 IP A INT Space 0x0000 0100 0x0000 017F 128 IP B VO Space 0x0000 0180 0x0000 01BF 64 IP B ID Space 0x0000_01C0 0x0000_01FF 64 IP B INT Space 0x0000 0200 0x0000 027F 128 IP C VO Space 0x0000 0280 0x0000 02BF 64 IP C ID Space 0x0000 02C0 0x0000 OFF 64 IP C INT Space 0x0000 0300 0x0
15. Serial Interrupt Assignment table Please refer to chapter Interrupt Controller for the EPIC serial interrupt assignment 4 2 2 4 EPIC Register Programming The EPIC Programming Guidelines from the MPC8240 manual should be followed TVME8240 User Manual Issue 1 2 9 Page 27 of 70 4 312C The TVME8240 provides an on board I2C EEPROM for board specific data 4 3 1 12C EEPROM EEPROM Description Content Offset 0x00 Check sum see note below 0x01 Number Of Valid Bytes Following e g 0x06 0x02 Board Type High Byte 0x2030 for 0x03 Board Type Low Byte TVME8240 0x04 Board Option High Byte e g Ox000B for 0x05 Board Option Low Byte TVME8240 11 0x06 Board Version Major V lt major gt lt minor gt 0x07 Board Version Minor e g 0x0100 V1 0 0x08 m Factory Reserved OXOF 0x10 is Reserved OxFF Table 4 2 12 EEPROM Content The address of the on board I2C EEPROM is 0b000 TEWS S TECHNOLOGIES Writes to the on board I2C EEPROM must be enabled in the Utility Control Register The check sum is the 2 s complement of the lower byte of the sum of all used locations of the 12C EEPROM except the check sum byte TVME8240 User Manual Issue 1 2 9 Page 28 of 70 TEWS S TECHNOLOGIES 5 FLASH Programming 5 18 bit Wide Socket Boot FLASH The TVME8240 provides 1 MB of 8 bit wide socket Boot FLASH using two 512 K x 8 bit 32 pin PLCC FLASH devices The Boot FLASH
16. address range is OXFFFO 0000 to OXFFFF FFFF Boot FLASH Socket XU1 is for the lower 512 K address range of the Boot FLASH OXFFFO 0000 to OxFFF7 FFFF Boot FLASH Socket XU2 is for the upper 512 K address range of the Boot FLASH OxFFF8 0000 to OxFFFF FFFF The Boot FLASH data bus port width is 8 bit For writes to the Boot FLASH only byte 8 bit transfer sizes are allowed Writes to the Boot FLASH must be enabled in the Utility Control Register The 8 bit wide socket Boot FLASH must always be installed and provide the board initialization code at the system reset vector Command Cycles 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle Sequence Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read 1 RA RD Reset 1 Base OxFO 0x000 Auto 4 Base OxAA Base 0x55 Base 0x90 Base MID Select 0x555 Ox2AA 0x555 0x000 Base DID 0x001 Write 4 Base OxAA Base 0x55 Base OxAO WA WD 0x555 Ox2AA 0x555 Chip 6 Base OxAA Base 0x55 Base 0x80 Base OxAA Base 0x55 Base 0x10 Erase 0x555 Ox2AA 0x555 0x555 Ox2AA 0x555 Sector 6 Base OxAA Base 0x55 Base 0x80 Base OxAA Base 0x55 SAx 0x30 Erase 0x555 Ox2AA 0x555 0x555 Ox2AA Table 5 1 Boot FLASH Command Cycles TVME8240 User Manual Issue 1 2 9 Page 29 of 70 TEWS S TECHNOLOGIES All the Boot FLASH c
17. ee 64 9541 Serial POM A serrer natnra oo e O 64 9 54 2 Serial POM Berenice re ida ed niai re dk c ri a rr e d da 64 9 5 5 LAN Interface Connector eese nemen ee ee ee ee nennen nnn nnne ensis 65 10 INSTALLATION AND USE NOTES 66 10 1 NVRAM Real Time Clock Control EE EE EE EE RE RE EE RE RE RE EE RE EE nnn nnn nnn nnn nnns nana Re RR RR anna nnn 66 11 TECHNICAL INFORMATION Q Q T 67 11 1 Gi TEE 67 BEA MOM ORY uu EE EE a da 67 11 3 Other Devices EN 67 114 VME En E 67 11 5 Ethernet InterfaGe iii is sees ss se du we n sven we ya aud Add REY NY aan Eed 67 11 6 Asynchronous Serial Interface KEER ER EER KA AR u u u uu u u u 68 11 7 PCI Expansion Connector U u ERA RE Ee RR Ee RR Ee RR EER uuu uu T 68 11 8 Power Requirements uses esse KERE RR RE REGEER RE REG RR KERE GR RR KERE GR RR KERE GR RR uu u GR RR KERE GR RR KERE GR RR EE Ee ee 68 11 9 IndustryPack Interface RR KERE GR RR KERE GR u RR KERE GR AR RE ERG GR u GR RR KERE GR RR KERE GR J J J 69 19 1 Cogie Interface nu RE AE eps ua bann 69 11 92 uzte TU UII ILES 69 11 10 PhysicalData si EE es 70 TITO ME RK sau ie n E EO Oe Ek DO EEN 70 TRO Pon EC 70 RUE ie EE iaa 70
18. ll The Universe ll does only provide a limited option for mapping a VME bus error event to the Universe II LINT interrupt pins To overcome this limitation the TVME8240 logic directly monitors the Universe II VX_BERR output that is used for asserting VME bus errors The TVME8240 VME bus error interrupt is handled via the Utility Registers in the Peripheral Devices address space Please see the Address Map section for details 6 5 Universe ll VME Bus Modes On the TVME8240 the Universe ll supports VME bus A32 24 16 master and slave address modes and D32 16 8 master and slave data transfer modes TVME8240 User Manual Issue 1 2 9 Page 35 of 70 TEWS TECHNOLOGIES 7 LAN Interface The Intel 21143 Ethernet controller is used for the TVME8240 Ethernet interface The 21143 is accessible on the TVME8240 PCI bus The 21143 INT interrupt output is mapped to the serial interrupt no 2 of the MPC8240 EPIC The 21143 is reset by a PCI reset Please refer to the 21143 manual for a detailed description of the 21143 Ethernet Controller 7 121143 PCI Header The 21143 PCI device number is 14 Register PCI Configuration Register Setting Offset 31 24 23 16 15 8 7 0 0x00 Device ID Vendor ID 0x0019 1011 21143 Intel 0x04 Status Command 0x0280 0007 0x08 Class Code Revisi
19. to 55 C forced air cooling Non Operating Temperature Range 40 C to 85 C 11 10 3 Weight TVME8240 11 372 5 g 11 10 4 Humidity 5 to 90 non condensing 11 10 5 Form Factor e Standard one slot GU VME e 3 row a b c VME P1 amp P2 connectors PCI expansion board occupies an additional VME slot if installed TVME8240 User Manual Issue 1 2 9 Page 70 of 70
20. 00 0000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x0003_0100 7 Read back value after writing all 1 s Table 6 1 Universe ll PCI Header 6 2 Universe ll Power Up Options The TVME8240 uses the default Universe ll power up option configuration See the Universe ll user manual for details TVME8240 User Manual Issue 1 2 9 Page 34 of 70 TEWS TECHNOLOGIES 6 3 Universe ll Reset Signals The Universe ll PWRRST input is controlled by a power up reset logic The Universe ll RST input is connected to the PCI reset signal The Universe ll LRST output is used to assert a general board reset in case of a VME bus system reset The Universe ll VMERST input is used to assert a VME bus system reset in case of a general board reset The Universe ll VRSYSRST and VXSYSRST signals are mapped to the VME bus SYSRST signal If the Universe ll is the VME bus system controller a general board reset will also assert a VME bus system reset If the Universe ll is not the VME bus system controller a VME bus system reset will also assert a general board reset 6 4 Universe ll Interrupts The Universe ll LINT 4 7 interrupt pins are not used The Universe ll LINT 0 3 interrupt pins are used as outputs and are mapped to the serial interrupts no 5 8 of the MPC8240 EPIC 6 4 14 VME Bus Error Interrupt The TVME8240 provides a dedicated interrupt source for VME bus error events asserted by the Universe
21. 000 037F 128 IP D VO Space 0x0000 0380 0x0000_03BF 64 IP D ID Space 0x0000_03C0 0x0000_03FF 64 IP D INT Space Table 8 11 Local Space 1 Address Map IP A D ID INT VO Space The TVME8240 will perform write cycles to the IP ID space Any access to the IP INT space will assert the IP INTSEL signal on the selected IP slot The TVME8240 will perform write cycles to the IP INT space The user should perform IP INT space read cycles on the desired IP slot to generate an IP INTSEL cycle and read the interrupt vector For this read cycle the address must reflect if the IP INTSEL cycle is for IP INTO or for IP INT1 TVME8240 User Manual Issue 1 2 9 Page 52 of 70 TEWS TECHNOLOGIES 8 2 5 Local Space 2 Address Map The PCI9030 local space 2 is used for the IP A D Memory space 16 bit port The PCI base address for local space 2 is PCIBAR4 at offset 0x20 in the PCI9030 PCI configuration register space Offset Size Description Base PCI Base Address 4 Byte Start End 0x0000 0000 0x007F FFFF 8M IP A MEM Space 16 bit 0x0080 0000 OXOOFF FFFF 8M IP B MEM Space 16 bit 0x0100 0000 Ox017F FFFF 8M IP C MEM Space 16 bit 0x0180 0000 0x01FF_FFFF 8M IP D MEM Space 16 bit Table 8 12 Local Space 2 Address Map IP A D Memory Space 16 bit 8 2 6 Local Space 3 Address Map The PCI9030 local space 3 is used for the IP A D Memory space 8 bit port The PCI base address for lo
22. A MSW Local Space 1 Remap LAS1BA 31 16 0x0400 TVME8240 User Manual Issue 1 2 9 Page 43 of 70 TEWS S TECHNOLOGIES EEPROM Register Offset Register Description Register Bits Value Offset Affected 0x42 Local 0x18 LSW Local Space 1 Remap LAS1BA 31 16 0x0001 0x44 Local Ox1E MSW Local Space 2 Remap LAS2BA 31 16 0x0000 0x46 Local 0x1C LSW Local Space 2 Remap LAS2BA 31 16 0x0001 0x48 Local 0x22 MSW Local Space 3 Remap LAS3BA 31 16 0x0200 0x4A Local 0x20 LSW Local Space 3 Remap LAS3BA 31 16 0x0001 0x4C Local 0x26 MSW Local Exp ROM Remap EROMBA 31 16 0x0000 Ox4E Local 0x24 LSW Local Exp ROM Remap EROMBA 15 0 0x0000 0x50 Local 0x2A MSW Local Space 0 Descriptor LASOBRD 31 0 0xD541 0x52 Local 0x28 LSW Local Space 0 Descriptor LASOBRDI15 0 0x60A0 0x54 Local 0x2E MSW Local Space 1 Descriptor LAS1BRD 31 0 0x1541 0x56 Local 0x2C LSW Local Space 1 Descriptor LAS1BRD 15 0 0x20A2 0x58 Local 0x32 MSW Local Space 2 Descriptor LAS2BRD 31 0 0x1541 0x5A Local 0x30 LSW Local Space 2 Descriptor LAS2BRD 15 0 0x20A2 0x5C Local 0x36 MSW Local Space 3 Descriptor LAS3BRD 31 0 0x1501 Ox5E Local 0x34 LSW Local Space 3 Descriptor LAS3BRD 15 0 0x20A2 0x60 Local 0x3A MSW Local Exp ROM Descriptor EROMBRDI31 16 0x0000 0x62 Local 0x38 LSW Local Exp ROM Descriptor EROMBRDI15 0 0x0000 0x64 Local Ox3E MSW Local Chip Select 0 CSOBASE 31
23. D 96 AD44 97 AD47 98 AD46 99 AD49 100 AD48 101 AD51 102 AD50 103 AD53 104 AD52 105 AD55 106 AD54 107 AD57 108 AD56 109 AD59 110 AD58 111 AD61 112 AD60 113 AD63 114 AD62 Table 9 6 PCI Expansion Connector The PCI Expansion Connector type is AMP 2 767004 4 TVME8240 User Manual Issue 1 2 9 Page 63 of 70 TEWS S TECHNOLOGIES 9 5 4 Serial Interface Connectors 9 5 4 1 Serial Port A Y 5 Signal DCD input RXD input TXD output DTR output GND DSR input RTS output CTS input RI input OO O OI GOO N c Table 9 7 Serial Port A DB9 male Connector 9 5 4 2 Serial Port B RS232 Adapter TVME8240 A1 10 The RS232 adapter card TVME824 A1 10 will be delivered with every TVME8240 board Y 5 Signal Reserved RXD input TXD output Reserved GND Reserved RTS output CTS input Reserved O0O J DO OI A O N c Table 9 8 Serial Port B DB9 male Connector RS232 TVME8240 User Manual Issue 1 2 9 Page 64 of 70 TEWS TECHNOLOGIES RS422 Adapter TVME8240 A1 11 The RS422 adapter card TVME8240 A1 11 can be ordered separately H 5 RS422 RXD input RXD input TXD output TXD output GND RTS output RTS output CTS input CTS input Table 9 9 Serial Port B DB9 male Connector RS422 COIN OD a RI
24. ES Description Value Block Length 0x86 Block Type 0x02 Media Code 0x01 0x23 0x24 0x25 GPR Seq Word 1 0x26 0x0801 GPR Seg Word 1 0x0001 0x28 Block Length 0x93 Block Type 0x03 PHY 0x00 GPR Seg Length 0x00 RST Seq Length 0x03 0x2A 0x2B 0x2C 0x2D 0x2E RST Sequence 1st Word 0x0801 RST Sequence 2nd Word 0x0000 RST Sequence 3rd Word 0x0001 Media Capabilities 0x7800 Nway Advertisement 0x01E0 FDX Bit Map 0x5000 TTM Bit Map 0x1800 0x2F 0x31 0x33 0x35 0x37 0x39 0x3B PHY Ins Ind 0x00 Reserved OxSE 0x00 0x7B 7 TE Table 7 2 21143 Configuration EEPROM Settings Ox3D TVME8240 User Manual Issue 1 2 9 Page 38 of 70 TEWS S TECHNOLOGIES EEPROM 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C OxOE Address 0x00 0x1498 0x2030 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x10 IDCRC 0x0104 0x0100 Oxuv06 Oxyzwx 0x2000 0x0000 0x0000 0x20 0x0800 0x8602 0x0102 0x0801 0x0001 0x0393 0x0000 0x0103 0x30 0x0008 0x0100 0x0000 OxE078 0x0001 0x0050 0x0018 0x0000 0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x70 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 ROMCRC ICCRC 0x00 ID Block CRC ROMCRC SROM CRC MAC Addr 00 01 06 uv wx yz Table 7 3 21143 Configuration EEPROM Cont
25. Ethernet The PMON date command can be used to enable the Real Time Clock function Setup Start the Real Time Clock function PMON date 200408101445 00 Tue Aug 10 14 45 00 2004 PMON reboot Stop the Real Time Clock function This is recommended for TVME8240 board storage PMON gt date x Clock is stopped PMON gt TVME8240 User Manual Issue 1 2 9 Page 66 of 70 TEWS S TECHNOLOGIES 11 Technical Information 11 1 Processor Motorola MPC8240 Integrated Host PPC 250 MHz Core Frequency Embedded Version MPC603e G2 Processor Core Floating Point Unit DMA Controller 16 Kbyte I Cache 16 kbyte D Cache Four cascadable 31 bit timer 11 2 Memory 64 Mbyte 64 bit wide SDRAM 83 MHz 8 Mbyte 64 bit wide Flash Memory 11 3 Other Devices 8 Kbyte NVRAM M48T59 with exchangeable battery 1 Mbyte 8 bit wide Boot Flash two PLCC sockets 11 4 VME Interface Tundra Universe ll A16 A32 Master Slave Address Modes D08 D64 Master Slave Data Transfer Modes RR PRI VME bus Arbiter IRQ 1 7 any of seven IRQs System Controller Jumper Yes No Auto Detect Four Location Monitors DMA Controller VME Bus Error Interrupt 11 5 Ethernet Interface Intel 21143TD Controller PCI DMA support 10Base T 100Base TX Interface on RJ 45 front panel connector 10Base T 10Base2 AUI Port on VME P2 connector TVME8240 User Manual Issue 1 2 9 Page 67 of 70 TEWS S TECHNOLOGIES 11 6 Asynchronous Serial Inter
26. FE_FFFF SA15 64 K OxFFFF_0000 0xFFFF_FFFF Table 5 3 Boot FLASH Sector Map TVME8240 User Manual Issue 1 2 9 Page 30 of 70 TEWS S TECHNOLOGIES 5 2 64 bit Wide On Board Memory FLASH The TVME8240 provides 8 Mbyte of 64 bit wide board mounted Memory FLASH using four 1 M x16 bit FLASH devices The Memory FLASH address range is OXFFOO 0000 to OxFF7F_FFFF The Memory FLASH data bus port width is 64 bit For writes to the Memory FLASH only double word 64 bit transfer sizes are allowed Writes to the Memory FLASH must be enabled in the Utility Control Register TVME8240 User Manual Issue 1 2 9 Page 31 of 70 TECHNOLOGIES TEWS S o 8 01000100 0 000 00 JA 0L000L00X0 OEOOOEOOXO O o 8VVV 2X0 AE oseg vue joe SS00SS00 SS00SS00 I GG00SS00X0 GG00SS00X0 o o 0SSS LXO 0SSS LXO ka 2 oseg eseg o S VOOVVOO V00VV00 9 JA CIN aia OM VVYOOVVOOXO VV00VV00x0 O o 0000 0X0 8000 0x0 8VVV 2X0 8VVV 2X0 NI 3 eseg eseg vM eseg oseg o es 06000600 0V000V00 08000800 08000800 9 8 06000600X0 0V000V00x0 08000800X0 08000800X0 o Is 8VVV 2X0 8VVV cXO 8VVV ZX0 8VVV ZX0 BE eseg eseg eseg eseg o S SS00SS00 SS00SS00 SS00SS00 SS00SS00 9 8 SG00SS00X0 SS00SS00X0 SS00SS00x0 SS00SS00X0 O 2 y 0SSS 1X0 0SSS 1x0 0SSS Leg 0SSS La N 2 eseg aseg eseg aseg o IS 04000400 VV00VV00 V00VV00 V00VV00 V00VV00 9 qu 04000400X0 VV00
27. FF SA3 16K OXFFOO COOO OxFFOO_FFFF SA4 16K OXFFO1 0000 OxFFO1_3FFF SA511 16K OxFF7F C000 OXFF7F FFFF Table 5 6 Memory FLASH Sector Map TVME8240 User Manual Issue 1 2 9 Page 33 of 70 6 VME Bus Interface The Tundra Universe ll VME PCI bridge is used as the TVME8240 VME PCI bridge The Universe ll is accessible on both the VME bus and the TVME8240 PCI bus TEWS TECHNOLOGIES Please refer to the Universe ll manual for a detailed description of the Universe ll VME PCI bridge 6 1 Universe ll PCI Header The Universe ll PCI device number is 13 Register PCI Configuration Register Setting Offset 31 24 23 16 15 8 7 0x00 Device ID Vendor ID 0x0000_10E3 Universe Tundra 0x04 Status Command 0x0200_0007 0x08 Class Code Revision ID 0x0680_0001 0x0C Reserved Header Latency Cache Line 0x0000 0000 0x10 PCI Base Address 0 OxFFFF_F0o1 Configuration Register UO Mapped 4 Kbyte 0x14 PCI Base Address 1 OxFFFF F000 Configuration Register Memory Mapped 4 Kbyte 0x18 PCI Unimplemented 0x0000 0000 0x1C PCI Unimplemented 0x0000_0000 0x20 PCI Unimplemented 0x0000_0000 0x24 PCI Unimplemented 0x0000_0000 0x28 PCI Reserved 0x0000_0000 0x2C PCI Reserved 0x0000 0000 0x30 PCI Unimplemented 0x0000 0000 0x34 PCI Reserved 0x0000 0000 0x38 PCI Reserved 0x00
28. IP A D MEMORY SPACE 16 BIT 53 TABLE 9 13 LOCAL SPACE 3 ADDRESS MAP IP A D MEMORY SPACE 8 BIT 53 TABLE 10 3 BOOT JUMPER ert bede sd eed La deu ee gel id UFU UP ase HE b ERE ee EGO Dek did 56 TABLE 10 4 VME SYSTEM CONTROLLER JUMPER sese nnne 56 TABLE 10 5 VME P1 CONNECTOR eene ee ee eren nne trennen rris trente ee nennen ener net 59 TABLE 10 6 VME P2 CONNECTOR teinte ei he ec rd eae tae a d ee eeu ies 60 TABLE 10 7 2 PPI CONNECTOR EE 61 TABLE 10 8 PCI EXPANSION GONNEGTOR ee ee cece eee ee ee eee ee ee cae ee ke eek ek ee ee ee re Ge ee ee ee Gee ee nt 63 TABLE 10 10 SERIAL PORT A DB9 MALE CONNECTOR ees ee eee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 64 TABLE 10 11 SERIAL PORT B DB9 MALE CONNECTOR RG 64 TABLE 10 12 SERIAL PORT B DB9 MALE CONNECTOR RS422 esse ee se ee ee ee ee ee se ee ee ee ee ee ee ee ee ee 65 TABLE 10 13 LAN CONNECTOR 8P BAR ee ese ee se ee se ee ee ee cae ee ee ek eek ee Re u L ee ee ee Ge ee ee Ge ee Ge ennt 65 TABLE 12 1 MIBF DATA ER edd tendre D v ru tV es 70 TVME8240 User Manual Issue 1 2 9 Page 8 of 70 1 Introduction TEWS TECHNOLOGIES The TVME8240 is a VME single slot Single Board Computer SBC using the Motorola MPC8240 Embedded PowerPC Processor The board provides four single IndustryPack IP slots supporting single and double sized IP modules
29. ME_IRQ1 VME_A8 31 12V NC 12V 32 5V 5V 5V Table 9 3 VME P1 Connector TVME8240 User Manual Issue 1 2 9 Page 59 of 70 TEWS S TECHNOLOGIES 9 5 1 2 VME P2 Connector Pin Row A Row B Row C 1 SCSI DO 45V AUI CD 2 SCSI Di GND AUI CD 3 SCSI D2st NC AUI TD 4 SCSI_D3 VME_A24 AUI_TD 5 SCSI D4 VME A25 AU RD 6 SCSI D5s VME A26 AUI RD 7 SCSI_D6 VME_A27 12VLAN 8 SCSI D7 VME A28 NC 9 SCSI PARO VME A29 NC 10 SCSI ATN VME A30 NC 11 SCSI_BSY VME_A31 NC 12 SCSI_ACK GND NC 13 SCSI_RST 5V NC 14 SCSI_MSG VME_D16 NC 15 SCSI_SEL VME_D17 NC 16 SCSI CD VME D18 NC 17 SCSI REQ amp VME D19 NC 18 SCSI IO VME D20 SER RXDB i 19 SER TXDB o VME D21 NC 20 NC VME D22 SER CTSB i 21 NC VME D23 NC 22 NC GND NC 23 NC VME D24 NC 24 NC VME D25 NC 25 SER RXDB i VME D26 NC 26 SER TXDB o VME D27 SER RTSB o 27 SER CTSB i VME D28 SER TXDA o 28 NC VME D29 SER RXDA i 29 SER_RTSB o VME D30 SER RTSA o 30 NC VME D31 SER CTSA i 31 NC GND SER DTRA o 32 NC 45V SER DCDA i Table 9 4 VME P2 Connector The serial port signals SER x are shown in the TVME8240 pin function E g for serial port A the external TXD line must be connected to pin C28 SER RXDA NOT to pin C27 SER TXDA For serial port B The SER xB pins are used as the RS422 sign
30. PCI 0x3C Interrupt Pin PCIIPR 7 0 0x0100 Reserved 0x18 PCI 0x42 MSW Power Management Capabilities PMC 14 11 5 3 0 0x4801 Ox1A PCI 0x40 LSW Power Management Capabilities PM NEXT 7 0 0x4801 PMCAPID 7 0 0x1C PCI 0x46 MSW Power Management Data PMCSR Reserved 0x0000 Bridge Support Ext Ox1E PCI 0x44 LSW Power Management Control Status PMCSR 14 8 0x0000 0x20 PCI 0x4A MSW Hot Swap Control Status Reserved 0x0000 0x22 PCI 0x48 LSW Hot Swap Next Capability Pointer HS_NEXT 7 0 0x4C06 Hot Swap Control HS_CNTL 7 0 0x24 PCI 0x4E PCI Vital Product Data Address Reserved 0x0000 0x26 PCI 0x4C PCI Vital Product Data Next Capability PVPD NEXT 7 0 0x0003 Pointer PCI Vital Product Data Control PVPD_CNTL 7 0 0x28 Local 0x02 MSW Local Space 0 Range LASORRI31 16 OxOFFF 0x2A Local 0x00 LSW Local Space 0 Range LASORR 15 0 OxFFOO 0x2C Local 0x06 MSW Local Space 1 Range LAS1RR 381 16 OxOFFF Ox2E Local 0x04 LSW Local Space 1 Range LAS1RR 15 0 OxFCOO 0x30 Local 0x0A MSW Local Space 2 Range LAS2RRI31 16 OxOEO0 0x32 Local 0x08 LSW Local Space 2 Range LAS2RR 15 0 0x0000 0x34 Local OxOE MSW Local Space 3 Range LAS3RR 31 16 0x0F00 0x36 Local 0x0C LSW Local Space 3 Range LASSRR 15 0 0x0000 0x38 Local 0x12 MSW Local Exp ROM Range EROMRR 31 16 0x0000 Ox3A Local 0x10 LSW Local Exp ROM Range EROMRRI15 0 0x0000 0x3C Local 0x16 MSW Local Space 0 Remap LASOBA 31 16 0x0800 Ox3E Local 0x14 LSW Local Space 0 Remap LASOBA 15 0 0x0001 0x40 Local Ox1
31. TEWS The Embedded VO Company TECHNOLOGIES TVME8240 Single Board Computer with IndustryPack Interface Version 1 2 User Manual Issue 1 2 9 December 2009 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com TVME8240 Single Board Computer with IndustryPack Interface Available Board Options TMVE8240 11 MPC8240 250 MHz 64 MB SDRAM 1 8 MB FLASH Fast Ethernet Front Panel I O TVME8240 User Manual Issue 1 2 9 TEWS S TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 2002 2009 by TEWS TECHNOLOGIES GmbH All tra
32. VV00X0 VV00VV00X0 VV00VV00X0 VV00VV00X0 O v Is 8VVV ZX0 8vvv ZX0 8VVV 2X0 8vvv 2x0 g VH 0000 0X0 eseg oseg 9seg oseg seg o 9 o T CO gt O E man Ka LLI ER 3 9 98 g 2 38 o o oO 20 or Oo x a in O Nu Page 32 of 70 Table 5 4 Memory FLASH Command Cycles TVME8240 User Manual Issue 1 2 9 TEWS S TECHNOLOGIES All the Memory FLASH command cycles are write cycles except the 1st cycle of the Read command and the 4th cycle of the Auto Select command which are read cycles The Memory FLASH base address is OXFFO0 0000 For Write commands the program should poll for RD WD from RA z WA after the 4th cycle For Erase commands the program should poll for RD OxFFFFFFFFFFFFFFFF from the Memory FLASH base address for Chip Erase or SAx for Sector Erase after the 6th cycle Symbols DID Device ID MID Manufacturer ID RA Read Address RD Read Data SA Sector Address WA Write Address WD Write Data Manufacturer Device Manufacturer ID Device ID SST 39VF160 OXOOBFOOBFOOBFOOBF 0x2782278227822782 SST 39VF1601 OXOOBFOOBFOOBFOOBF 0x234B234B234B234B SST 39VF1602 OXOOBFOOBFOOBFOOBF 0x234A234A234A234A Table 5 5 Memory FLASH Auto Select Codes Sector Sector Sector Address Range Size Byte SST 39xF160 Uniform SAO 16K OxFFOO 0000 OxFFOO_3FFF SA1 16K OXFFOO 4000 OxFFOO_7FFF SA2 16K OXFFOO 8000 OxFFOO_BF
33. al lines when the RS422 adapter is used The SER xB pins are used as the RS232 signal lines when the RS232 adapter is used and are used as the RS422 signal lines when the RS422 adapter is used For each serial port only one connection scheme is allowed at a time either via the VME P2 connector or via the front plate DB9 connector Please see the SCSI Interface section for using 16bit SCSI Targets on the VME P2 connector TVME8240 User Manual Issue 1 2 9 Page 60 of 70 TEWS S TECHNOLOGIES 9 5 2 IP Interface Connectors 9 5 2 1 IP P1 Connector Pin Signal Pin Signal 1 GND 2 CLK 3 RESET 4 DO 5 D1 6 D2 7 D3 8 D4 9 D5 10 D6 11 D7 12 D8 13 D9 14 D10 15 D11 16 D12 17 D13 18 D14 19 D15 20 BSO 21 BS1 22 12V 23 12V 24 5V 25 GND 26 GND 27 5V 28 WRITE 29 IDSEL 30 NC 31 MEMSEL 32 NC 33 INTSEL 34 DMAACK 35 IOSEL 36 RSVO 37 Al 38 DMAEND 39 A2 40 ERROR 41 A3 42 INTREQO 43 A4 44 INTREO1 45 A5 46 STROBE 47 A6 48 ACK 49 RSV1 50 GND Table 9 5 IP P1 Connector The following signals have an on board pull up resistor 4K7 3 3V RESET WRITE IDSEL IOSEL INTSEL MEMSEL DMAACK DMAEND ERRORH INTREQO INTREQ1 RSVO RSV1 STROBE ACK DMA is not supported on the IP interface 9 5 2 2 IP P2 Connector For each IP slot the IP P2 connector signals IP module I O lines are routed dir
34. board initialization software TVME8240 User Manual Issue 1 2 9 Page 40 of 70 8 1 1 PCI9030 PCI Header The PCI9030 PCI device number is 16 TEWS S TECHNOLOGIES Register PCI Configuration Register Setting Offset 31 24 23 16 15 8 7 0 0x00 Device ID Vendor ID 0x9030 10B5 PCI9030 PLX Technology 0x04 Status Command 0x0280 0003 0x08 Class Code Revision ID 0x0680 0000 OXOC Not Supported Header Not Supported Cache Line 0x0000 0000 0x10 PCI Base Address 0 PCIBARO OxFFFF_FF80 PCI9030 Local Configuration Register Memory Mapped 128 Byte 0x14 PCI Base Address 1 PCIBAR1 OxFFFF FF81 PCI9030 Local Configuration Register UO Mapped 128 Byte 0x18 PCI Base Address 2 PCIBAR2 OxFFFF_FFOO Local Space 0 256 Byte 0x1C PCI Base Address 3 PCIBAR3 OxFFFF FCoo Local Space 1 1 Kbyte 0x20 PCI Base Address 4 PCIBAR4 OXFEOO 0000 Local Space 2 32 Mbyte 0x24 PCI Base Address 5 PCIBAR5 OXFFOO 0000 Local Space 3 16 Mbyte 0x28 Not Supported 0x0000 0000 0x2C Subsystem ID Subsystem Vendor ID 0x2030_1498 TVME8240 TEWS TECHNOLOGIES 0x30 PCI Expansion ROM Base Address 0x0000_0000 0x34 Reserved Cap Pointer 0x0000_0040 0x38 Reserved 0x0000_0000 0x3C Not Supported Not Supported Interrupt Pin Interrupt Line 0x0000_0100 0x40 PM Capabili
35. cal space 3 is PCIBAR5 at offset 0x24 in the PCI9030 PCI configuration register space TVME8240 User Manual Issue 1 2 9 Offset Size Description Base PCI Base Address 5 Byte Start End 0x0000 0000 0x003F_FFFF 4M IP A MEM Space 8 bit 0x0040_0000 0x007F FFFF 4M IP B MEM Space 8 bit 0x0080 0000 OxOOBF FFFF 4M IP C MEM Space 8 bit 0x00CO 0000 OXOOFF FFFF 4M IP D MEM Space 8 bit Table 8 13 Local Space 3 Address Map IP A D Memory Space 8 bit The 8 bit IP Memory space should be used for memory space linear byte addressing of IP modules that use IP data lines D7 0 only Page 53 of 70 TEWS S TECHNOLOGIES 8 3 IP Interrupts The IP FPGA maps all IP interface interrupts sources Timeout Error INTO INT1 to the PCI9030 local interrupt input 1 LINT1 The PCI9030 PCI Target Chip maps its local interrupt inputs to its PCI interrupt output INTA The PCI9030 PCI interrupt output is mapped to the serial interrupt no 4 of the MPC8240 EPIC The PCI9030 local interrupt 2 LINT2 is not used Upon detecting EPIC Serial Interrupt No 4 read the IP Status Register to determine the IP interrupt source Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register Error interrupts should be disabled after being noticed once TVME8240 User Manual Issue 1 2 9 Page 54 of 70 TEWS S TECHNOLOGIES 9 Board UO 9 1 Board VO Overview
36. ccessible on the front panel The ABORT switch can be used to generate a CPU interrupt TVME8240 User Manual Issue 1 2 9 Page 16 of 70 3 Address Maps TEWS TECHNOLOGIES The TVME8240 uses the MPC8240 address map B in host mode The following address maps reflect MPC8240 configuration register settings done by board initialization software 3 1 Address Map Processor View Processor Address Size Description Start End Byte 0x0000 0000 TOP DRAM DRAM SIZE SDRAM Memory 64 bit wide 64 Mbyte TOP DRAM 0x03FF_FFFF TOP DRAM Ox3FFF FFFF 1G DRAM SIZE Reserved 1 0x4000_0000 Ox7FFF FFFF 1G Reserved 0x8000 0000 OxFCEF FFFF 2G 49M PCI MEM Space OxFCFO 0000 OxFCFF FFFF 1M MPC8240 EUMB OXFDOO 0000 OxFDFF FFFF 16 M PCI MEM Space 0 based OXFEOO 0000 OXFEOO FFFF 64K PCI VO Space 0 based OxFEO1 0000 OxFE7F FFFF 8M 64K Reserved OxFE80 0000 OxFEBF FFFF 4M PCI VO Space 0 based OxFECO 0000 OxFEDF FFFF 2M Configuration Address Register OxFEEO 0000 OxFEEF FFFF 1M Configuration Data Register OxFEFO 0000 OxFEFF FFFF 1M PCI Interrupt Acknowledge OXFFOO 0000 OxFF7F FFFF 8M Memory FLASH 64 bit wide OxFF80 0000 OxFFDF FFFF 6M Reserved OxFFEO 0000 OxFFEF FFFF 1M Peripheral Devices 8 bit wide OxFFFO 0000 OxFFFF FFFF 1M Boot FLASH 8 bit wide Table 3 1 Address Map Processor View Device Read Write SDRAM All All Memory FLASH All 64 bit Only Pe
37. ces and Boot FLASH Table 3 4 Address Map PCI Memory Master View TVME8240 User Manual Issue 1 2 9 Page 18 of 70 3 3 Address Map PCI VO Master View TEWS TECHNOLOGIES PCI VO Address Size Description Start End Byte 0x0000 0000 0x0000 FFFF 64 K PCI VO Space 0x0001 0000 0x007F FFFF 8M 64K Reserved 0x0080 0000 OxOOBF FFFF 4M PCI VO Space OXOOCO 0000 OxFFFF FFFF 4G 12M Reserved Table 3 5 Address Map PCI I O Master View The MPC8240 does not responding as a target to PCI VO cycles 3 4 Address Map Peripheral Devices Detail Address Size Description Start End Byte OxFFEO 0000 OxFFEO 1FFF 8K NVRAM RTC OxFFEO 2000 OxFFE3_FFFF 256 K 8K Reserved OxFFE4_0000 OxFFE4_0003 4 UTILITY REG OxFFE4_0004 OxFFE7 FFFF 256K 4 Reserved OxFFE8 0000 OxFFE8 0007 8 UART CH A OxFFE8 0008 OxFFE8 OOOF 8 UART CH B OxFFE8 0010 OxFFEF FFFF 512 K 16 Reserved Table 3 6 Address Map Peripheral Devices Detail For read or write accesses to the Peripheral Devices only 8 bit byte transfer sizes are allowed For the NVRAM RTC register map please refer to the M48T59 device documentation For the UART register map please refer to the XR16C2550 documentation TVME8240 User Manual Issue 1 2 9 Page 19 of 70 TEWS S TECHNOLOGIES 3 5 Address Map Utility Register Detail Address Size Reg
38. demarks mentioned are property of their respective owners Page 2 of 70 TEWS S TECHNOLOGIES Issue Description Date 1 0 Initial Issue June 2002 14 General Update Power Requirements added September 2002 1 2 MTBF Data added February 2003 1 3 Added Technical Information May 2003 1 4 Board Options Update May 2004 1 5 Added Installation and Use section Corrected Memory Flash First Instruction offset July 2004 Updated Technical Information Changed Clock Ratio Recommendation for the MPC8240 EPIC Int Config Reg We Added Note for 16 bit aa 8 bit SCSI Interface January 2008 Added Weight to Technical Information Section 1 7 Response to VME System Reset has changed September 2005 1 8 Added VME Bus Error Interrupt capability August 2006 1 2 9 New Notation for User Manual and Engineering Documentation December 2009 TVME8240 User Manual Issue 1 2 9 Page 3 of 70 TEWS S TECHNOLOGIES Table of Contents 1 INTEODUGETION ese ewe 9 ES MN QUIN OE EE EO EE IE EE EE EE NEG 9 12 ie do ell EER EE RE TR ER ER 10 2 DESCRIPTION ER EE EO N EE AE NEE N 11 2 1 POCOS O cientes RS ee ER au Deo ad 11 2 2 Local Memory BUS ie ee ese an aa Ia oe Se ke ae N ED ee GE eaves Cua eame GE ee 11 2 2 1 FLASH M Mory ATE 11 2 2 2 SDRAM Memonm A 11 2 2 3 NVRAM Real Time Clock n ee AA Ge ee ee nns 11 2 2 4 16550 compatible Dual UART ee
39. e el 50 pin 50 pin 50 pin 50 pin 4 x 50 pin Flat Cable Connector Figure 1 1 Block Diagram TVME8240 Front VO SP 1 MEE IP Slot A SP 2 MEE IP Slot B Status ee LED ER 10 100 BaseT m IP Slot C IP Slot D PCI Expansion p Figure 1 2 Block Diagram TVM8240 Board Layout Front VO TVME8240 User Manual Issue 1 2 9 Page 10 of 70 TEWS S TECHNOLOGIES 2 Description 2 1 Processor The TVME8240 uses the Motorola MPC8240 Embedded PowerPC processor 2 2 Local Memory Bus The TVME8240 uses the MPC8240 integrated memory controller for accessing the local memory devices The TVME8240 provides the following devices on the local memory bus e Board mounted Memory FLASH 8 Mbyte 64 bit wide e Socket Boot FLASH 1Mbyte 8 bit wide e SDRAM memory 64 Mbyte 64 bit wide e NVRAM 8 Kbyte 8 bit wide Real Time Clock Watchdog M48T59 compatible e 16550 compatible Dual UART 8 bit wide e Utility Registers 8 bit wide 2 2 1 FLASH Memory The TVME8240 provides two banks of FLASH memory e Bank 0 consists of two 32 pin PLCC sockets each populated with a 512 K x 8 bit FLASH device for a total of 1 Mbyte 8 bit wide Boot FLASH e Bank 1 consists of four 1 M x 16 bit on board FLASH devices providing a total of 8 Mbyte 64 bit wide Mem
40. e is expired The IP recover time is app 1us TVME8240 User Manual Issue 1 2 9 Page 48 of 70 TEWS S TECHNOLOGIES 8 2 3 3 Reset Register The Reset Register can be used to assert the IP RESET signal and to detect when the IP RESET signal is negated Bit Name Description 15 MSB 14 13 12 11 10 Read 9 Undefined x Write 7 No Effect Should be written with 0 s 6 5 4 3 2 1 Read 0 IP RESET Signal is De asserted 0 BEES ed EE Signal is Asserted ER 0 No Effect 1 Assert IP RESET Signal Automatic Negation Table 8 9 Reset Register The IP RESET signal is also asserted at power up or board reset TVME8240 User Manual Issue 1 2 9 Page 49 of 70 TEWS S TECHNOLOGIES 8 2 3 4 Status Register The Status Register can be used to read IP timeout error and interrupt status The IP timeout time is app 8ps An IP timeout occurs if the IP module fails to generate the IP ACK signal within the IP timeout time An IP timeout is not reported to the PCI9030 or the PCI Master but in the Status Register For timeout reads all F s are returned Bit Name Description Read 0 No Timeout on IP D 15 1 IP_D Timeout has occurred MSB TIME_D Write 0 No Effect 1 Clear IP D Timeout Status Read 0 No Timeout on IP C i h 14 TIME_C 1 IPC Timeout has occurred Write 0 No Effect 1 Clear IP_C Timeout S
41. ectly to the appropriate pins of the 50P IP I O ribbon cable connector TVME8240 User Manual Issue 1 2 9 Page 61 of 70 TEWS S TECHNOLOGIES 9 5 3 PCI Expansion Connector Pin Signal Pin Signal 1 3 3V 2 3 3V 3 CLK 4 INTA 5 GND 6 INTB 7 PONRST 8 INTC 9 HRST 10 INTD 11 TDO 12 TDI 13 TMS 14 TCK 15 TRST 16 PRSNT 17 GNT GND 18 REQ 19 12V 20 12V 21 PERRA 22 SERR 23 LOCK 24 SDONE 25 DEVSEL 26 SBO 27 GND 28 GND 29 TRDY 30 IRDY 31 STOP 32 FRAME 33 GND 34 GND 35 ACK64 36 NC 37 REQ64 38 NC 39 PAR 40 RST 41 C BE1 42 C BEO 43 C BE3 44 C BE2 45 AD1 46 ADO 47 AD3 48 AD2 49 AD5 50 AD4 51 AD7 52 AD6 53 AD9 54 AD8 55 AD11 56 AD10 57 AD13 5V 58 AD12 59 AD15 60 AD14 61 AD17 62 AD16 63 AD19 64 AD18 65 AD21 66 AD20 67 AD23 68 AD22 69 AD25 70 AD24 71 AD27 72 AD26 73 AD29 74 AD28 75 AD31 76 AD30 77 PAR64 78 NC 79 C BE5 80 C BE4 81 C BE7 82 C BE6 TVME8240 User Manual Issue 1 2 9 Page 62 of 70 TEWS TECHNOLOGIES Pin Signal Pin Signal 83 AD33 84 AD32 85 AD35 86 AD34 87 AD37 88 AD36 89 AD39 90 AD38 91 AD41 92 AD40 93 AD43 94 AD42 95 AD45 GN
42. ent 7 321143 Ports The 21143 MII port connects to an Intel LXT970 Fast Ethernet transceiver to build the Fast Ethernet interface available at the RJ45 connector on the front plate The 21143 AUI port connects to the VME P2 connector The 21143 10Base T TP port is not used 7 421143 GEP Pin Usage The 21143 GEP 0 pin is used as an output that connects to the LXT970 Fast Ethernet transceiver reset input A low on the GEP 0 output holds the LXT970 in reset The LXT970 is also reset by a PCI reset The 21143 GEP 3 1 pins are used as inputs Interrupts for GEP 1 0 inputs must be disabled 7 5 Media Capabilities 10 100Base TX Ethernet interface on the RJ45 front panel connector AUI port for a 10Base T or 10Base2 Ethernet interface on the VME P2 Connector TVME8240 User Manual Issue 1 2 9 Page 39 of 70 TEWS S TECHNOLOGIES 8 IP Bus Interface The TVME8240 IP interface is accessible in the PCI Memory space The PCI9030 PCI Target Chip from PLX Technology is used as the PCI target device for accessing the IP interface A FPGA is used on the PCI9030 local bus to build the IP interface and provide IP Interface Control Registers 8 1 PCI9030 PCI Target Chip The PCI9030 provides four local spaces 0 3 that are used for the TVME8240 IP interface Basic PCI9030 register configuration is loaded from a serial EEPROM after power up or board reset Programming of the PCI9030 PCI and local configuration registers is scope of the
43. face e Dual 16C550 compatible UART 1 8432 MHz clock source e Port 1 RS232 configuration Port 2 RS232 Adapter default RS422 Adapter option e Max baud rate 115kbps e Two DB9 front panel connectors 11 7 PCI Expansion Connector e 32 bit 33 MHz PCI Interface 114 pin connector e 5V PCI Signaling Voltage PCI Expansion Board may drive 3 3V or 5V PCI signal levels PCI Expansion Board must tolerate 5V PCI signal levels e Supports Motorola PMC Span TEWS IP Span TVME230 11 8 Power Requirements The TVME8240 uses the 5V 12V and 12V power supply pins available on the VME P1 and P2 connectors as the main power supply The TVME8240 3 3V board power supply is generated on board using the VME 5V power supply 5V Supply On board load 2 8Atyp 4A max Additional load optional VO e PCI Expansion Connector unfused e P interface 2A fused for IP slots A B 2A fused for IP slots C D Max 2A for the total of IP slots A B max 2A for the total of IP slots C D TVME8240 User Manual Issue 1 2 9 Page 68 of 70 TEWS S TECHNOLOGIES 12V Supply On board load 3mA max not required for system function only used in the 12V fuse status sensing logic Additional load optional VO e PCI Expansion Connector unfused e VME P2 Connector LAN Power 1A fused e P interface Available on all IP slots fused for a total of 2A max 1A per IP Slot 12V Supply On board load 3mA max not req
44. guration Register 4 MCCR4 Table 4 1 MPC8240 Configuration Register Settings TVME8240 User Manual Issue 1 2 9 Page 25 of 70 TEWS S TECHNOLOGIES Board initialization software notes The MEMGO bit in the MCCR1 register offset OXFO must not be set until all other memory configuration parameters have been appropriately configured The DLL RESET bit in the AMBOR register offset OXEO must be explicitly set and then cleared by software during initialization TVME8240 User Manual Issue 1 2 9 Page 26 of 70 TEWS S TECHNOLOGIES 4 2 MPC8240 EPIC Register The TVME8240 uses the MPC8240 EPIC in serial mode as the board interrupt controller 4 2 1 EPIC Register Access The EPIC Registers are part of the MPC8240 Embedded Utility Memory Block EUMB The EUMB base address is set in the EUMBBAR Register For the TVME8240 memory map the EUMB base address is set to OXFCFO 0000 4 2 2 EPIC Register Settings 4 2 2 1 Global Configuration Register GCR Offset from EUMBBAR Ox4 1020 The mode bit in the GCR must be set for EPIC mixed mode operation 4 2 2 2 EPIC Interrupt Configuration Register EICR Offset from EUMBBAR Ox4 1030 The EICR clock ratio field should be set to 0x2 for optimized interrupt performance The EICR SIE bit must be set to enable Serial Interrupt Mode 4 2 2 3 Serial Interrupt Vector Priority Registers SVPR The polarity and sense bits in the SVPRs must be configured accordingly to the EPIC
45. he TVME8240 is the VME bus system controller a board reset will also trigger a VME bus system reset 9 4 2 ABT Switch The ABT ABORT switch can be used to generate a CPU interrupt The Abort Switch is mapped to serial interrupt no 1 of the MPC8240 EPIC Serial interrupt no 1 must be configured as edge sensitive TVME8240 User Manual Issue 1 2 9 Page 58 of 70 9 5 Connectors 9 5 1 VME Interface Connectors 9 5 1 1 VME P1 Connector TEWS S TECHNOLOGIES Pin Row A Row B Row C 1 VME DO VME BBSY VME D8 2 VME D1 VME BCLR VME D9 3 VME D2 VME ACFAIL VME D10 4 VME Di VME BGINO VME D11 5 VME D4 VME BGOUTO Z VME D12 6 VME D5 VME BGIN1 VME D13 7 VME D6 VME BGOUT1 VME D14 8 VME D7 VME BGIN2 VME D15 9 GND VME BGOUT2 GND 10 VME SYSCLK VME BGINS3 VME SYSFAIL 11 GND VME_BGOUT3 VME_BERR 12 VME_DS1 VME_BRO VME_SYSRST 13 VME DSO VME BR1 VME LWORD 14 VME WRITE VME BR2 VME AMS 15 GND VME_BR3 VME_A23 16 VME_DTACK VME AMO VME A22 17 GND VME AM1 VME A21 18 VME AS VME AM2 VME A20 19 GND VME_AM3 VME_A19 20 VME IACK GND VME A18 21 VME_IACKIN NC VME_A17 22 VME_IACKOUT NC VME_A16 23 VME_AM4 GND VME_A15 24 VME_A7 VME_IRQ7 VME_A14 25 VME_A6 VME_IRQ6 VME_A13 26 VME_A5 VME_IRQ5 VME_A12 27 VME_A4 VME IRQ4 VME A11 28 VME A3 VME_IRQ3 VME_A10 29 VME_A2 VME IRQ2 VME A9 30 VME Ai V
46. ister TVME8240 User Manual Issue 1 2 9 Page 45 of 70 8 2 1 PCI9030 Local Space Assignment The PCI9030 local spaces must be used to access the IP interface The PCI base address for each TEWS S TECHNOLOGIES local space can be obtained from the PCI9030 PCI configuration register space PCI9030 Size Port Endian PCI Space IP Interface Space Local Byte Width Mode Space Bit 0 256 16 Big Mem IP Interface Register 1 1K 16 Big Mem IP A D ID INT IO Space 2 32M 16 Big Mem IP A D MEM Space 16 bit 3 16M 8 Big Mem IP A D MEM Space 8 bit Table 8 5 PCI9030 Local Space Assignment 8 2 2 Local Space 0 Address Map The PCI9030 local space 0 is used for the IP interface registers The PCI base address for local space 0 is PCIBAR2 at offset 0x18 in the PCI9030 PCI configuration register space Offset Size Register Base PCI Base Byte Address 2 0x00 2 REVISION ID 0x02 2 IP A CONTROL 0x04 2 IP B CONTROL 0x06 2 IP C CONTROL 0x08 2 IP D CONTROL OXOA 2 RESET 0x0C 2 STATUS OxOE 2 Reserved 0x10 OxFF 240 Reserved Table 8 6 Local Space 0 Address Map IP Interface Register TVME8240 User Manual Issue 1 2 9 Page 46 of 70 8 2 3 IP Interface Register 8 2 3 1 Revision ID Register The Revision ID Register shows the revision of the on board IP FPGA logic TEWS S TECHNOLOGIES
47. ister Name Byte OXFFE4 0000 1 CONTROL OXFFE4 0001 1 STATUS OxFFE4 0002 1 Reserved OXFFE4 0003 1 LED Table 3 7 Address Map Utility Register Detail 3 5 1 Control Register OXFFE4 0000 Bit Name Access Reset Function 0 0 Normal Board Operation MSB BREST iii 1 Assert Board Reset 0 I2C EEPROM Writes Disabled 1 6 FEP WE SCH A 1 12C EEPROM Writes Enabled 2 MEM_FLASH_WE RW 0 0 Memory FLASH Writes Disabled 1 Memory FLASH Writes Enabled 3 BOOT FLASH WE RW 0 0 Boot FLASH Writes Disabled 1 Boot FLASH Writes Enabled Write as 0 4 Reserved I I Undefined for Reads 0 VME Bus Error Interrupt Disabled REN iid 1 VME Bus Error Interrupt Enabled Write as 0 9 Reseed I I Undefined for Reads 7 Reserved _ Write as 0 LSB Undefined for Reads Table 3 8 Control Register A board reset is also performed at power up A board reset will perform a general board hardware reset re configuration of the IP FPGA PCI reset and CPU reset If the TVME8240 is the VME bus system controller a board reset will also trigger a VME bus system reset TVME8240 User Manual Issue 1 2 9 Page 20 of 70 TEWS S TECHNOLOGIES 3 5 2 Status Register OxFFE4 0001 Bit Name Access Reset Function wen EE S E pes vem MET CEEREN S FOU UD a SERB MODE I i E s or No Adapter 3 ABORT SW R _ 0 Abort Switch Not Active 1 Abort Switch Active 4 Reserved Undefined fo
48. manuals for details 2 5 LAN Interface The TVME8240 uses the 21143 10 100Base TX Ethernet LAN Controller Intel with the LXT970 Fast Ethernet Transceiver Intel on its MII interface to build the Ethernet interface A 10 100Base TX Ethernet interface is available on an 8P RJ45 connector on the front panel A 10Base T AUI interface is available at the VME P2 connector Please refer to the 21143 and LXT970 manuals for details 2 6IP Bus Interface The TVME8240 uses a XC28100 FPGA Xilinx for the IndustryPack interface logic The TVME8240 uses the PCI9030 PCI Target Chip PLX Technologies to access the IndustryPack FPGA from the PCI bus Four single sized IP slots A D are provided Double sized IP modules 16 bit can be used on combined IP slots A B or C D The clock rate for each IP slot is programmable to be 8 MHz or 32 MHz Please refer to the IP interface section for details 2 7 PCI Expansion Interface The TVME8240 provides a 114 pin PCI expansion connector for using existing VME PCI Expansion Boards e g TEWS TECHNOLOGIES TVME230 IP Span or Motorola PMC Span TVME8240 User Manual Issue 1 2 9 Page 14 of 70 TEWS S TECHNOLOGIES 2 8 Asynchronous Serial Interface The TVME8240 provides two asynchronous serial interface ports used by the on board Dual UART Port A is a fix RS232 port Port B can be configured for RS232 or RS422 by an adapter card Both serial ports are available on DB9 male connectors on the front pa
49. n Register Access The MPC8240 Configuration Registers are accessed in two steps 1 A 32 bit register address 0x8000 OOnn is written to the CONFIG ADDR port at OXFECO 0000 where nn is the word aligned register offset 2 Data is accessed at the CONFIG DATA port at OXFEEO 000m where m is the offset within the word aligned address depending on transfer size Data can be accessed multiple times at the CONFIG DATA port until the CONFIG ADDR port value is changed All of the MPC8240 Configuration Registers are intrinsically little endian Therefore all of the following Configuration Register settings are shown in little endian order Since on the TVME8240 the MPC8240 processor and peripheral logic operates in big endian mode software must either use byte reversed load store instructions or byte swap the values for the CONFIG ADDR and CONFIG DATA port access E g for reading the Device ID Register offset 0x02 one should write 0x0000 0080 0x00 is the word aligned offset for 0x02 to OXFECO 0000 and read the half word 0x0300 at OXFEEO 0002 E g for setting the Output Driver Control Register offset 0x73 one should write 0x7000 0080 0x70 is the word aligned offset for 0x73 to OXFECO 0000 and write the byte OxCO to OXFEEO 0003 E g for setting the EUMBBAR Register offset 0x78 to OXFCFO 0000 one should write 0x78000080 to OXFECO 0000 and write the word OxOOOOFOFC to OxFEEO 0000 TVME8240 User Manual Issue 1 2 9 Page 23 of 70
50. nel or on the VME P2 connector 2 9 Interrupt Controller The TVME8240 uses the MPC8240 integrated Embedded Programmable Interrupt Controller EPIC in the serial mode The following interrupt sources are available Serial Edge Level Polarity Interrupt Source Interrupt No 0 Level Low VME Bus Error 1 Edge Low ABORT Switch 2 Level Low 21143 3 Level Low SYM53C875 4 Level Low PCI9030 5 Level Low Universe ll LINTO 6 Level Low Universe ll LINT1 7 Level Low Universe ll LINT2 8 Level Low Universe ll LINT3 9 Level Low PCI Expansion INTA 10 Level Low PCI Expansion INTB 11 Level Low PCI Expansion INTC 12 Level Low PCI Expansion INTD 13 Level Low Real Time Clock 14 Level Low UART Channel A 15 Level Low UART Channel B Table 2 3 EPIC Serial Interrupt Assignment TVME8240 User Manual Issue 1 2 9 Page 15 of 70 TEWS S TECHNOLOGIES 2 10 Status Indicators The TVME8240 provides four status indicators visible on the front panel Function Label Color Description em ae eet Ee Board Activity ACT Green EE M xi Board Failure FAIL Red User controlled Fuse ao Table 2 4 Status Indicators 2 11 Reset Switch The TVME8240 provides a momentary RESET switch accessible on the front panel The RESET switch can be used to generate a board hardware reset 2 12 Abort Switch The TVME8240 provides a momentary ABORT switch a
51. ommand cycles are write cycles except the 1st cycle of the Read command and the 4th cycle of the Auto Select command which are read cycles The base address for the lower 512 K Boot FLASH device is OXFFFO 0000 The base address for the upper 512 K Boot FLASH device is OXFFF8 0000 For Write commands the program should poll for RD WD from RA z WA after the 4th cycle For Erase commands the program should poll for RD z OxFF from the Boot FLASH device base address for Chip Erase or SAx for Sector Erase after the 6th cycle Symbols DID Device ID MID Manufacturer ID RA Read Address RD Read Data SA Sector Address WA Write Address WD Write Data Manufacturer Device Manufacture ID Device ID AMD 29F040B 0x01 OXA4 ST 29F040B 0x20 OxE2 Table 5 2 Boot FLASH Auto Select Codes Sector Sector Sector Address Range Size Byte SAO 64 K OxFFFO 0000 OxFFFO FFFF SA1 64K OxFFF1 0000 OxFFF1 FFFF SA2 64 K OxFFF2 0000 OxFFF2_FFFF SA3 64 K OXFFF3 0000 OxFFF3_FFFF SA4 64 K OxFFF4_0000 OxFFF4_FFFF SA5 64 K OxFFF5 0000 OxFFF5_FFFF SA6 64 K OxFFF6 0000 OxFFF6_FFFF SA7 64 K OxFFF7_0000 OxFFF7_FFFF SA8 64 K OxFFF8 0000 OxFFF8_FFFF SA9 64 K OxFFF9 0000 OxFFF9 FFFF SA10 64 K OxFFFA 0000 OXFFFA FFFF SA11 64 K OxFFFB 0000 OxFFFB_FFFF SA12 64 K OxFFFC 0000 OxFFFC_FFFF SA13 64 K OxFFFD 0000 OxFFFD FFFF SA14 64K OxFFFE 0000 OxFF
52. on ID 0x0200 0041 0x0C Reserved Header Latency Cache Line 0x0000 0000 0x10 PCI Base Address 0 OXFFFF_FF81 Configuration Register l O Mapped 128Byte 0x14 PCI Base Address 1 OXFFFF_FCOO Configuration Register Memory Mapped 1 Kbyte 0x18 Reserved 0x0000_0000 0x1C Reserved 0x0000_0000 0x20 Reserved 0x0000_0000 0x24 Reserved 0x0000_0000 0x28 Card bus CIS Pointer 0x0000_0000 0x2C Subsystem ID Subsystem Vendor ID 0x2030_1498 TVME8240 TEWS TECHNOLOGIES 0x30 PCI Expansion ROM Base Address 0x0000_0000 0x34 Reserved Cap Pointer 0x0000_0000 0x38 Reserved 0x0000_0000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x2814 0100 Read back Value after writing all 1 s Table 7 1 21143 PCI Header TVME8240 User Manual Issue 1 2 9 Page 36 of 70 TEWS S TECHNOLOGIES 7 221143 Configuration EEPROM Some parts of the 21143 configuration EEPROM are used directly by the 21143 upon reset Some parts of the 21143 configuration EEPROM are used by software drivers Value 0x1498 0x2030 Card bus CIS Pointer High 0x0000 Card bus CIS Pointer Low 0x0000 E CU 0x0000 E a 0x0000 NG p ee GE 0x0100 IEEE Network Address 6 Byte Ox uv 06 IEEE Network Address 6 Byte Ox yz wx a9 0 Dev Ox1A N N Controller 0 Info Leaf Offset 0x0020 EUR SE Selected Connection Type Pp 0x0800 TVME8240 User Manual Issue 1 2 9 Page 37 of 70 TEWS S TECHNOLOGI
53. ontroller Jumper The VME system controller jumper controls the Universe ll BGIN3 input signal which the Universe ll samples at the end of VME SYSRST to determine VME System Controller mode TVME8240 User Manual Issue 1 2 9 Page 56 of 70 TEWS TECHNOLOGIES 9 3 LEDs During board reset all LEDs are ON 9 3 1 FAIL LED The FAIL LED Red can be set by software control via the Utility LED Register to indicate a failure condition 9 3 2 FUSE LED The FUSE LED Red is set by hardware control if any of the on board resettable fuses triggers There is one resettable fuse for each of the following power supplies e IP Slot AB 5V e IP Slot C D 5V e IP Slot A B C D 12V e IP Slot A B C D 12V e VME P2 LAN 12V 9 3 3 ACT LED The ACT Activity LED Green is set by hardware control if there is any activity on the Local Memory bus or PCI bus 9 3 4 SYS LED The SYS System Controller LED Green is set by hardware control if the Universe VME PCI Bridge is the VME bus System Controller TVME8240 User Manual Issue 1 2 9 Page 57 of 70 TEWS S TECHNOLOGIES 9 4 Switches 9 4 1 RST Switch The RST RESET switch can be used to generate a board reset A board reset is also performed at power up A board reset can also be asserted by software programming the Utility Control Register A board reset will perform a general board hardware reset re configuration of the IP FPGA PCI reset and CPU reset If t
54. ory FLASH 2 2 2 SDRAM Memory The TVME8240 provides four 8 M x 16 bit SDRAM devices building up 64 Mbyte 64 bit wide SDRAM memory 2 2 3 NVRAM Real Time Clock The TVME8240 uses an ST M48T59 compatible device to provide 8 KB of non volatile static RAM and real time clock The M48T59 device consists of two parts e A 28 pin 330mil SO device which contains the RTC 8 Kbyte SRAM and sockets for the Snaphat battery e A Snaphat battery that is placed on top of the device Please refer to the M48T59 manual for details TVME8240 User Manual Issue 1 2 9 Page 11 of 70 TEWS TECHNOLOGIES 2 2 4 16550 compatible Dual UART The TVME8240 uses the Exar XR16C2550 16550 compatible Dual UART with a 1 8432 MHz clock oscillator providing two asynchronous serial ports Please refer to the XR16C2550 manual for details 2 2 5 Utility Registers The TVME8240 provides some additional registers for board control and status functions Please refer to the address map section of this manual for details 2 3 PCI Bus The TVME8240 implements a 32 bit 33 MHz PCI bus The TVME8240 implements the following devices on the PCI bus MPC8240 PowerPC CPU Local Memory Controller Local PCI Bridge PCI Arbiter System Clock Generation Interrupt Controller Universe ll VME PCI Bridge 21143 10 100Base TX Ethernet LAN Controller PCI9030 PCI Local Target Chip Optional PCI Devices on PCI Expansion Connector e g TEWS TECHNOLOGIES
55. ptions 6 3 Universe Reset Signals 6 4 Universe ll Interrupts eere 6 4 1 VME Bus Error Interrupt 6 5 Universe ll VME Bus Modes 7 LAN INTERFACE eren 7 1 21143 PCI Header 7 2 21143 Configuration EEPROM 7 43 21143 POFS u u ee ee n ee Ge ee Ee GE ee raja se ede 7 4 21143 GEP Pin Usage 7 5 Media Capabilities 8 IP BUSINTERFAGDE oi iese sasie ae ae ie ae dee ie ae ee da ie 8 1 PC19030 PCI Target Chip 8 1 1 PCI9030 PCI Header 8 1 2 Local Configuration Register 8 1 3 PCI9030 Configuration EEPROM 8 2 IP interface J KERE ee EE 8 2 1 PCI9030 Local Space Assignment 8 2 2 Local Space 0 Address Map 8 2 3 IP Interface Register 8 2 3 1 Revision ID Register 8 2 3 2 IP X Control Registers
56. r Reads 0 IP FPGA Configuration Not Done 1 IP FPGA Configuration Done Reads 0 No VME Bus Error Event 1 VME Bus Error Event occurred Writes 6 VME BERR R C Write as 1 to clear VME Bus Error u Status and or to clear VME Bus Error Interrupt Status This status bit is capable of generating an interrupt if enabled in the Control Register 5 FPGA DONE H I LSB Reserved Undefined for Reads Table 3 9 Status Register Board initialization software should verify successful IP FPGA configuration 3 5 3 LED Register OXFFE4 0003 Bit Name Access Reset Function Me mus mw o EERS 1 Reserved 7 I Mierer Reads 2 Reserved 7 7 R Reads 3 Reserved 5 Werer Reads 4 Reserved 7 I dc m Reads 5 Reserved Write as 0 TVME8240 User Manual Issue 1 2 9 Page 21 of 70 TEWS S TECHNOLOGIES Undefined for Reads Write as 0 g BEES I I Undefined for Reads 7 R d _ _ Write as 0 LSB ee Undefined for Reads TVME8240 User Manual Issue 1 2 9 Table 3 10 LED Register Page 22 of 70 TEWS S 4 MPC8240 The TVME8240 uses the MPC8240 in host mode with address map B The MPC8240 processor and peripheral logic are configured to operate in big endian mode 4 1 MPC8240 Configuration Register Setting up the MPC8240 Configuration Registers is scope of the board initialization software 4 1 1 Configuratio
57. ripheral Devices 8 bit Only 8 bit Only Boot FLASH All 8 bit Only Table 3 2 Supported Transfer Sizes TVME8240 User Manual Issue 1 2 9 Page 17 of 70 TEWS S TECHNOLOGIES Processor Address Translated PCI Address PCI Space Start End Start End 0x8000 0000 OXFCEF FFFF 0x8000 0000 OxFCEF FFFF MEM OXFDOO 0000 OxFDFF FFFF 0x0000 0000 OXOOFF FFFF MEM OxFEOO 0000 OxFEO0 FFFF 0x0000 0000 0x0000 FFFF VO OxFE80 0000 OxFEBF FFFF 0x0000 0080 OxOOBF FFFF VO Table 3 3 PCI Address Translation 3 2 Address Map PCI Memory Master View PCI Memory Address Size Description Start End Byte 0x0000 0000 TOP DRAM DRAM SIZE SDRAM Memory 64 bit wide 64 Mbyte TOP DRAM 0x03FF_FFFF TOP DRAM OxSFFF FFFF 1G DRAM SIZE Reserved 1 0x4000_0000 Ox7FFF FFFF 1G Reserved 0x8000 0000 OxFCEF FFFF 2G 49M PCI Memory Space OxFCFO 0000 OxFCFO OFFF 4K PCI accessible MPC8240 EUMB OxFCFO 1000 OxFCFF FFFF 1M 4K Reserved OxFDOO 0000 OxFDFF FFFF 16M SDRAM Memory 0 Based OxFEOO 0000 OxFEFF FFFF 16M Reserved OXFFOO 0000 OxFF7F FFFF 8M Memory FLASH 64 bit wide OxFF80 0000 OxFFDF FFFF 6M Reserved OxFFEO 0000 OxFFEF FFFF 1M Peripheral Devices 8 bit wide OxFFFO 0000 OxFFFF FFFF 1M Boot FLASH 8 bit wide On the TVME8240 the MPC8240 responds as a target to PCI Memory cycles for accessing SDRAM PCI accessible MPC8240 EUMB Memory FLASH Peripheral Devi
58. running at 8 MHz or 32 MHz and front VO ribbon cable connectors 1 1 Features Processor MPC8240 Embedded PowerPC Processor Timer DMA 12C Interrupt Controller FLASH Memory 1 Mbyte 8 bit wide socket Boot FLASH 8 Mbyte 64 bit wide on board Memory FLASH System Memory 64 Mbyte 64 bit wide Synchronous DRAM LAN Interface 21143 10 100Base TX Ethernet Controller 21143 MII Port amp LXT970 Fast Ethernet Transceiver for RJ45 10 100Base TX 21143 AUI Port for VME P2 10Base T IndustryPack Interface Four single sized Two double sized Industry Pack modules 16 bit supported 8 MHz 32 MHz selectable for each slot Front VO ribbon cable connectors PCI Expansion Capability PMC Span support NVRAM amp RTC 8 Kbyte M48T59 device Asynchronous Serial Interface One fix RS232 Port DB9 VME P2 One RS232 RS422 Adapter Port DB9 VME P2 RS232 Default Miscellaneous RESET switch ABORT switch Front panel status indicators Form Factor Standard 6U VME Table 1 1 Features TVME8240 TVME8240 User Manual Issue 1 2 9 Page 9 of 70 TEWS S TECHNOLOGIES 1 2 Block Diagram MK48T59 Snaphat Battery MCP8240 250Mhz Two PLCCs in sockets NVRAM RTC f DB 9 M DB 9 M FLASH 8 MB 64 2 Channel serial SDRAM GAMB 64 PCI Local Bus 32 bit 33 MHz Memory 8 Controller PCI Bridg
59. se ee RA Ge AA Ge Ge n ee ee trenes 12 2 2 5 Utility Register8 Uu uu se se Ge AA Ge AA Re ERA AA AA Ge AA ee RA AG ee ee RA Ad sn ee nnns 12 d 3 WEE 12 2 3 1 PCI Arbiter Assignment ee ee ee Ge RA AA AA ee RA Ge AA nn AR Re ee ee au 13 2 3 2 PCI IDSEL Assignment AAA 13 2 4 VME Bus Interface ad 14 2 55 CAN Interface EE 14 2 6 IPBuslnterface XX 14 2 7 PCL Expansion Interface coo eoe dee ee Ia EE ee ee ee dee ua kausa 14 2 8 Asynchronous Serial Interface KEER KERE U U U KERE AR KRAKE KEER ER Ee ansa AR ERG ee ER Ee 15 2 9 WR Tu Eege a de UE 15 CL MEET UE CG 16 2 11 Toe EE N N EE EE EE 16 2 12 Dieu EE N u EO N EE aada aaa 16 3 ADDRESS MAPS I a 17 3 1 Address Map Processor View l U ER RR RE EE ER uu ER RR KERE u u ER RR RE EE ER ER 17 3 2 Address Map PCI Memory Master View esse ee Re RR Rae EE EER KA AR RR GR u u u u 18 3 3 Address Map PCI UO Master View AR RA AR KEER ER EER KRAAK u u u u u 19 3 4 Address Map Peripheral Devices Detail RE EE ER RE EE ER ER RE EE ER RR RR EE ER RR RE EE ER RR RE EE ER RR RE EE ER Een 19 3 5 Address Map Utility Register Detail KEER EE EER AR KA AR REG u KERR u u u 20 3 5 1 Control Register 0xFFE4_0000
60. tatus Read 0 No Timeout on IP B I B Ti h 13 TIME B 1 um imeout has occurred Write 0 No Effect 1 Clear IP B Timeout Status Read 0 No Timeout on IP A 12 TIME A 1 dum Timeout has occurred Write 0 No Effect 1 Clear IP A Timeout Status Read 0 No Error on IP D 11 ERR D 1 IP D ERROR Signal Asserted Write No Effect Read O No Error on IP C 10 ERR C 1 IP_C ERROR Signal Asserted Write No Effect Read 0 No Error on IP B 9 ERR B 1 IP B ERROR Signal Asserted Write No Effect TVME8240 User Manual Issue 1 2 9 Page 50 of 70 TEWS S TECHNOLOGIES Bit Name Description Read 0 No Error on IP A 8 ERR A 1 IP A ERROR Signal Asserted Write No Effect Read 0 No Interrupt 1 Request on IP D 7 INT D 1 Active IP_D Interrupt 1 Request ES Write 0 No Effect 1 Clear Edge Sensitive IP D Interrupt 1 Status Read 0 No Interrupt 0 Request on IP D 6 INTO D 1 Active IP D Interrupt O Request Write 0 No Effect 1 Clear Edge Sensitive IP D Interrupt O Status Read 0 No Interrupt 1 Request on IP C 5 wn C 1 deeg IP C Interrupt 1 Request Write 0 No Effect 1 Clear Edge Sensitive IP C Interrupt 1 Status Read 0 No Interrupt O Request on IP C 4 INTO C 1 Active IP C Interrupt O Request Write 0 No Effect 1 Clear Edge Sensitive IP C Interrupt O Status Read 0 No IP B Interrupt 1 Request 3 wn B 1 Active IP_B
61. ties PM NxtCap PM CaplD 0x4801_4801 0x44 PM Data PM CSR EXT PM CSR 0x0000_0000 0x48 Reserved HS CSR HS NxtCap HS CaplD 0x0000_4C06 0x4C VPD Address VPD NxtCap VPD CaplD 0x0000_0003 0x50 VPD Data 0x0000_0000 Read back Value after writing all 1 s Table 8 1 PCI9030 PCI Header TVME8240 User Manual Issue 1 2 9 Page 41 of 70 TEWS S TECHNOLOGIES 8 1 2 Local Configuration Register The PCI base address for the PCI9030 Local Configuration Registers can be obtained from the PCIBARO PCI Memory mapped register at offset 0x10 or from the PCIBAR1 PCI VO mapped register at offset 0x14 in the PCI9030 PCI configuration register space Register Local Configuration Register Name Setting Offset 0x00 Local Space 0 Range LASORR OxOFFF FFOO 0x04 Local Space 1 Range LAS1RR OxOFFF FCOO 0x08 Local Space 2 Range LAS2RR OxOEO0 0000 OXOC Local Space 3 Range LASSRR OxOFO0 0000 0x10 Expansion ROM Range EROMRR 0x0000 0000 0x14 Local Space 0 Remap LASOBA 0x0800 0001 0x18 Local Space 1 Remap LAS1BA 0x0400 0001 0x1G Local Space 2 Remap LAS2BA 0x0000_0001 0x20 Local Space 3 Remap LAS3BA 0x0200_0001 0x24 Expansion ROM Remap EROMBA 0x0000_0000 0x28 Local Space 0 Descriptor LASOBRD OxD541 60A0 0x2C Local Space 1 Descriptor LAS1BRD 0x1541 20A2 0x30 Local Space 2 Descriptor LAS2BRD 0x1541 20A2 0x34 Local Space 3 Descriptor LAS3BRD 0x1501_20A2 0x38 Expansion ROM Descriptor
62. uired for system function only used in the 12V fuse status sensing logic Additional load optional VO e PCI Expansion Connector Unfused e P interface Available on all IP slots fused for a total of 2A max 1A per IP Slot Power Supply Pins on VME Connectors The VME P1 and P2 connectors are rated for 2A max 20 C appr 1 5A max 70 C per pin For the 5V power supply there are 3 pins on the VME P1 connector and 3 pins on the VME P2 connector For the 12V power supply there is 1 pin on the VME P1 connector For the 12V power supply there is 1 pin on the VME P1 connector This must be considered for the total power supply load on board load plus additional I O load 11 9 IndustryPack Interface 11 9 1 Logic Interface e Four single size two double size IP slots e Spaces available for each IP slot 128 byte VO space 64 byte ID space 64 byte INT space 8 Mbyte MEM space 16 bit 4 Mbyte MEM space 8 bit linear e Data bus width 16 bit e Clock rate 8 MHz 32 MHz selectable for each IP slot 11 9 2 1 0 Interface e Four 50 pin planar connectors for ribbon cable front VO e 1A max continuous dc current per IP I O line TVME8240 User Manual Issue 1 2 9 Page 69 of 70 TEWS S TECHNOLOGIES 11 10 Physical Data 11 10 1 MTBF Based on calculation TVMES8240 Board Option MTBF Value 11 205002h Table 11 1 MTBF Data 11 10 2 Temperature Operating Temperature Range 0 C
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