Datasheet - Mouser Electronics
Contents
1. Details Spec ID Parameter Description Min Typ Max Units Conditions SID70 TRISEF Rise time in fast strong mode 2 12 ns 3 3 V Vppp Cload 25 pF SID71 TEALLF Fall time in fast strong mode 2 12 ns 3 3 V Vppp Cload 25 pF SID72 TRISES Rise time in slow strong mode 10 60 3 3 V Vppp Cload 25 pF SID73 TFALLS Fall time in slow strong mode 10 60 3 3 V Vppp Cload 25 pF SID74 FGPIOUT1 GPIO Four 3 3V lt VDDD lt 5 5 V 16 MHz 90 1 0 25 pF Fast strong mode load 60 40 duty cycle SID75 Fepiout2 GPIO Foyt 1 71 Vs VpppS 3 3 V 16 MHz 90 10 25 pF Fast strong mode load 60 40 duty cycle SID76 FGPIOUT3 GPIO Four 3 3 V lt Vppp lt 5 5 V 7 MHz 90 1 0 25 pF Slow strong mode load 60 40 duty cycle SID245 FGpiouT4 GPIO Four 1 71 V SVppp lt 3 3 V 3 5 MHz 90 10Y6 25 pF Slow strong mode load 60 40 duty cycle SID246 FGPIOIN GPIO input operating frequency 16 MHz 90 10 Vio 1 71 V lt Vppp lt 5 5 V XRES Table 7 XRES DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID77 Vin Input voltage high threshold 0 7 x V CMOS Input VDDD SID78 VIL Input voltage low threshold 0 3 x V CMOS Input VDDD SID79 RpuLLuUP Pull up resistor 3 5 5 6 8 5 kQ SID80 Cin Input capacitance 3 7 pF SID81 VHYSXRES Input voltage hysteresis 05 Vpp mV Typical hysteresis is 200 mV for Vpp gt 4 5V Table 8 XRES AC2. Acronyms Table 30 Acronyms Used in this Document continued Table 30 Acronyms Used in this Document Acronym Description Acronym Description ETM embedded trace macrocell ab s analog local bus FIR finite impulse response see also IIR ADC analog to digital converter ERE flash patch and breakpoint AG analog global a full speed AHB AMBA advanced microcontroller bus archi GPIO general purpose input output applies to a PSoC tecture high performance bus an ARM data pin transfer bus HVI high voltage interrupt see also LVI LVD ALU arithmetic logic unit IC integrated circuit AMUXBUS _ analog multiplexer bus IDAC current DAC see also DAC VDAC API application programming interface IDE integrated development environment APSR application program status register 12C or IIC Inter Integrated Circuit a communications ARM advanced RISC machine a CPU architecture protocol ATM automatic thump mode IIR infinite impulse response see also FIR BW bandwidth ILO internal low speed oscillator see also IMO CAN Controller Area Network a communications IMO internal main oscillator see also ILO protocol INL integral nonlinearity see also DNL CMRR common mode rejection ratio I O input output see also GPIO DIO SIO USBIO CPU central processing unit IPOR initial power on reset CRC cyclic redundancy check an error checking IPSR interrupt program status register protocol IRQ interrupt request DAC digital to
3. Spec ID Parameter Description Min Typ Max Units Details Conditions SID173 VPE Erase and program voltage 1 71 5 5 V Table 16 Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID174 Taowwene Row block write time erase and 20 ms Row block 128 bytes program SID175 TRrowerase Row erase time 13 ms SID176 TROWPROCRAN Row program time after erase 7 ms SID178 TBULKERASE Bulk erase time 16 KB 15 ms SID180 701 Tpevprog Total device program time 7 5 seconds SID181110 FEND Flash endurance 100K cycles SID182101 Fees Flash retention Ta lt 55 C 100K 20m years P E cycles SID182Al0 Flash retention Ta lt 85 C 10K 10112 years P E cycles System Resources Power on Reset POR Table 17 Power On Reset PRES Spec ID Parameter Description Min Typ Max Units Details Conditions SID CLK 6 SR POWER UP Power supply slew rate 1 67 V ms SID185170 VRISEIPOR Rising trip voltage 0 80 1 5 V SID186 70 VFALLIPOR Falling trip voltage 0 70 1 4 V Table 18 Brown out Detect BOD for Vecp Spec ID Parameter Description Min Typ Max Units Details Conditions SID190 70 VEALLPPOR BOD trip voltage in active and 1 48 1 62 V sleep modes SID192 T0 VEALLDPSLP BOD trip voltage in Deep Sleep 1 11 1 5 V Notes 9 It can take as much as 20 milliseconds to write to Flash During this time the device should not be Reset or Flash operations will
4. 4 Digital Peripherals eceeeeeeeeeeeeeeeneeeeenneeeeeeees 16 CPU and Memory Subsystem 0 0 0 eeeseeeeeeeeeneeeeeees 4 Memo aaa aan Gaan aan 18 System RESOUrCES ua 4 System RESOUICES aaa maa 18 Analog BIOCKS aaa aan lban 5 Ordering Information csccseeeeesseeesseeeeeeeeeeneeeeeeeeneee 21 Fixed Function Digital ce eeeeeseeeeseeeeeerneeeeeeees 5 Part Numbering Conventions cceeeeeeseeeeees 21 GPIO oy eves eee AG AA totes ee ee aes GI eee dee 5 PACKAGING maan nannannaaananaaaaasaaa sa 23 Special Function Peripherals 1 17 00000200suna su unuas 5 Package Outline Drawings Uu Ll anna naanan awww ans anwn 24 PIN OURS cacccesseniccsatsericesasanesaveaseaceueieensdsasauneenanaiaanacessincaseiaad 6 AC ONYMS nanana aaa aaah 26 POWOM sssssctsscnsavessincanederssctateesiduenseeutesscersssdessnadesiennontveaitoecatis 8 Document Conventions ceceeceeesseeeeeeeeeeeeteeneeeeeeees 28 Unregulated External Supply essees 8 Units Of MeasUre Lama 28 Regulated External Supply 0 eeecesseeeseeeeesneeeeeees 8 Revision History Development Support cccseccesseeeeeseeeeesneeeeseeeenseeeenees 9 Sales Solutions and Legal Information 31 Documentation oo eee cece eeenteeeeeeeeteeeeeeteeeeeaaeeeeenaes 9 Worldwide Sales and Design Support a 31 ONNE aenn a 9 ProdUCtS aaa ar Aa 31 AA E EERE 9 PSOC SOlUHHONS aaa hanuman 91 AA ATA AA AN 10 Cypress
5. Description of Change New datasheet for new device family Changed status from Advance to Preliminary Submission Date 05 23 2014 Change 07 23 2014 Document Number 001 92145 Description Title Automotive PSoC 4 PSoC 4000 Family Datasheet Programmable System on Chip PSoC Updated description above Table 3 SNPR ECN SNPR Updated Memory Revision xk Updated Electrical Specifications Updated Table 16 Added Note 11 and referred the same note in minimum value of SID182 spec Updated Device Level Specifications Added Note 12 and referred the same note in minimum value of SID182A spec 4388517 4425292 A Updated Electrical Specifications Updated Device Level Specifications 12 12 2014 Updated Table 3 Updated entire table Updated Analog Peripherals Updated Comparator Added maximum value of leyp1 parameter as 110 pA B 4594824 Updated Table 10 JICG Updated Table 9 Added maximum value of leyp2 parameter as 85 pA Changed maximum value of Tcomp1 parameter from 50 ns to 90 ns Changed maximum value of Tcomp2 parameter from 100 ns to 110 ns Updated Digital Peripherals Added Timer Counter Pulse Width Modulator TCPWM Removed Timer Removed Counter Removed Pulse Width Modulation PWM Updated 1 C Updated Table 13 Changed maximum value of 154 parameter from 10 5 pA to 25 pA Added maximum value of li2 4 parameter as 2 5 pA Updated Power on Reset POR
6. Updated Table 17 Updated entire table Updated Memory Added maximum value of TguLkerase parameter as 15 ms Added maximum value of Tpeyproc parameter as 7 5 seconds Updated Table 16 Updated System Resources Updated Power on Reset POR Updated Table 18 Added maximum value of VfaLLppor parameter as 1 62 V Changed minimum value of Veaitpps_p parameter from 1 14 V to 1 11 V Updated Internal Main Oscillator Updated Table 20 Changed maximum value of lyo1 parameter from 1000 pA to 250 pA Changed maximum value of limo2 parameter from 325 pA to 180 pA Updated Table 21 Added maximum value of Tstartimo parameter as 7 ps Page 29 of 31 Document Number 001 92145 Rev D Automotive PSoC 4 PSoC 4000 Family Datasheet mo pl CYPRESS PERFORM Revision History continued Description Title Automotive PSoC 4 PSoC 4000 Family Datasheet Programmable System on Chip PSoC Document Number 001 92145 tai Orig of Submission PIPE Revision ECN Change Date Description of Change B cont 4594824 JICG 12 12 2014 Updated Packaging Updated Table 27 Added values for Ty parameter corresponding to Condition For A grade devices Changed maximum value of Tj parameter corresponding to Condition For S grade devices from 100 C to 120 C Removed T jc parameter and its details C 4615131 SNPR 01 06 2015 Changed status from Preliminary to Final D 4669514
7. Serial Communication m Multi master IZC block with the ability to do address matching during Deep Sleep and generate a wake up on match Timing and Pulse Width Modulation m One 16 bit Timer Counter Pulse Width Modulator TCPWM block m Center aligned Edge and Pseudo Random modes m Comparator based triggering of Kill signals for motor drive and other high reliability digital logic applications Cypress Semiconductor Corporation Document Number 001 92145 Rev D 198 Champion Court Up to 20 Programmable GPIO Pins m 24 pin QFN and 16 pin SOIC packages m GPIO pins on Ports O 1 and 2 can be CapSense or have other functions m Drive modes strengths and slew rates are programmable Temperature Ranges m A Grade 40 C to 85 C m S Grade 40 C to 105 C m Automotive Electronics Council AEC Q100 qualified PSoC Creator Design Environment m Integrated Development Environment IDE provides schematic design entry and build with analog and digital automatic routing m Applications Programming Interface API component for all fixed function and programmable peripherals Industry Standard Tool Compatibility m After schematic entry development can be done with ARM based industry standard development tools San Jose CA 95134 1709 408 943 2600 Revised February 24 2015 sg Automotive PSoC 4 PSoC CYPRESS 4000 Family Datasheet To PERFORM Contents Functional Definition
8. 025T Tn SID216 113 T_SWDI_HOLD T 1 f SWDCLK 0 25 T ns SID217113 T SWDO VALID T 1 f SWDCLK 0 5 T ns SID217Al31 T_SWDO_HOLD T 1 SWDCLK fg WO Lng 2 Internal Main Oscillator Table 20 IMO DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions SID218 limot IMO operating current at 48 MHz 7 250 HA SID219 limo2 IMO operating current at 24 MHz 180 PA Table 21 IMO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID223 FimoTOL1 Frequency variation at 24 and 2 2V lt Vpp lt 5 5 V and 32 MHz trimmed 25 C lt T lt 85 C for A grade devices and 25 C lt Ta lt 105 C for S grade devices SID223A Fimototvecp Frequency variation trimmed 4 All SID226 TSTARTIMO IMO startup time 7 us SID228 TJITRMSIMO2 RMS jitter at 24 MHz 145 ps Internal Low Speed Oscillator Table 22 ILO DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions SID231113 litot ILO operating current E 0 3 1 05 pA SID233173 liLOLEAK ILO leakage current 2 15 nA Table 23 ILO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions siD23413T Tere ot lOstartuptime P 2 ms SID236 73 TILODUTY ILO duty cycle 40 50 60 Yo SID237 FILOTRIM1 ILO frequency range 20 40 80 kHz Note 13 Guaranteed by characterization Documen
9. 4 5 mA Sleep Mode Vppp 1 71 to 5 5 V SID25 Ipp20 IC wakeup WDT on 6 MHz E 1 1 7 mA SID25A IDD20A IC wakeup WDT on 12 MHz 1 4 mA Deep Sleep Mode Vpp 1 8 to 3 6 V Regulator on SID31 Ipp26 IC wakeup and WDT on 2 5 8 2 HA Deep Sleep Mode Vpp 3 6 to 5 5 V Regulator on SID34 Ipp29 IC wakeup and WDT on 2 5 12 KA Deep Sleep Mode Vpp Vccp 1 71 to 1 89 V Regulator bypassed SID37 Ipp32 IC wakeup and WDT on 2 5 9 2 KA XRES Current SID307 IDD XR Supply current while XRES asserted 2 5 mA Note 2 Maximum values corresponds to values at higher temperature 105 C Document Number 001 92145 Rev D Page 11 of 31 _ __ m E CYPRESS PERFORM Table 4 AC Specifications Automotive PSoC 4 PSoC 4000 Family Datasheet Details Spec ID Parameter Description Min Typ Max Units Conditions SID48 Fopu CPU frequency DC 16 MHz 1 71 lt Vpp lt 5 5 sip49FI TsLEEP Wakeup from Sleep mode 0 us SID50I TDEEPSLEEP Wakeup from Deep Sleep mode 35 us GPIO Table 5 GPIO DC Specifications Spec ID Parameter Description Min Typ Max Units Aa SID57 Vi Input voltage high threshold 0 7 x V CMOS Input VDDD SID58 Vir Input voltage low threshold 0 3 x V CMOS Input VDDD SID241 Vid LVTTL input Vppp lt 2 7 V 0 7x V VDDD SID242 Vit LVTTL inp
10. Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID83 2 TRESETWIDTH Reset pulse width 5 us BID 194 0 TresetwaAke _ Wake up time from reset release 3 ms Note 6 Guaranteed by characterization Document Number 001 92145 Rev D Page 13 of 31 f CYPRESS PERFORM Analog Peripherals Automotive PSoC 4 PSoC 4000 Family Datasheet Comparator Table 9 Comparator DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID330 6 lomp4 Block current High Bandwidth mode 110 HA SID331 61 lomp2 Block current Low Power mode 7 7 85 pA SID332 61 VOEFSET1 Offset voltage High Bandwidth mode 10 30 mv SID333 6 VOFFSET2 Offset voltage Low Power mode 10 30 V SID334 6 Zcmp DC input impedance of comparator 35 MQ SID338 6 VINP COMP Comparator input range 0 3 6 V Max input voltage is lower of 3 6 V or VDD Table 10 Comparator AC Specifications Guaranteed by Characterization Details Spec ID Parameter Description Min Typ Max Units Conditions SID336 61 Tcomp1 Response Time High Bandwidth mode 90 ns 50 mV overdrive SID337 6 Tcomp2 Response Time Low Power mode 110 ns 50 mV overdrive Document Number 001 92145 Rev D Page 14 of 31 EF a pra a CYPRESS PERFORM Automotive PSoC 4 PSoC 4000 Famil
11. select CMOS or LVTTL m Individual control of input and output buffer enabling disabling in addition to the drive strength modes m Selectable slew rates for dV dt related noise control to improve EMI The pins are organized in logical entities called ports which are 8 bit in width less for Ports 2 and 3 During power on and reset the blocks are forced to the disable state so as not to crowbar any inputs and or cause excess turn on current A multiplexing network known as a high speed I O matrix is used to multiplex between various signals that may connect to an I O pin Data output and pin state registers store respectively the values to be driven on the pins and the states of the pins themselves Every I O pin can generate an interrupt if so enabled and each I O port has an interrupt request IRQ and interrupt service routine ISR vector associated with it 4 for PSoC 4000 Special Function Peripherals CapSense CapSense is supported in the PSoC 4000 through a CSD block that can be connected to up to 16 pins through an analog mux bus via an analog switch pins on Port 3 are not available for CapSense purposes CapSense function can thus be provided on any available pin or group of pins in a system under software control A PSoC Creator component is provided for the CapSense block to make it easy for the user Shield voltage can be driven on another mux bus to provide water tolerance capability Water tolerance is prov
12. Automotive PSoC 4 PSoC 4000 Family Datasheet Programmable System on Chip PSoC PERFORM General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM Cortex MO CPU while being AEC Q100 compliant It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing The PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture It is a combination of a microcontroller with standard communication and timing peripherals a capacitive touch sensing system CapSense with best in class performance and general purpose analog PSoC 4000 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs Features 32 bit MCU Subsystem m 16 MHz ARM Cortex MO CPU m Up to 16 KB of flash with Read Accelerator m Up to 2 KB of SRAM Programmable Analog m Two current DACs IDACs for general purpose or capacitive sensing applications m One low power comparator with internal reference Low Power 1 71 V to 5 5 V operation m Deep Sleep mode with wake up on interrupt and 2C address detect Capacitive Sensing m Cypress Capacitive Sigma Delta CSD provides best in class signal to noise ratio SNR and water tolerance m Cypress supplied software component makes capacitive sensing design easy m Automatic hardware tuning SmartSense
13. Developer Community nissene OF naang lng 10 Technical Support Laan settee OT nA an NTE 11 Dinaanan jee naghang 14 Tools Electrical Specifications Absolute Maximum Ratings Device Level Specifications Analog Peripherals Document Number 001 92145 Rev D Page 2 of 31 ee _ _ __ m F CYPRESS PERFORM Automotive PSoC 4 PSoC 4000 Family Datasheet Figure 1 Block Diagram PSoC 4000 Cortex MO 16 MHz NVIC IRQMX T AHB Lite System Resources Lite Power Sleep Control Peripherals POR REF PWRSYS Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog Power Modes Active Sleep Deep Sleep PSoC 4000 devices include extensive support for programming testing debugging and tracing both hardware and firmware The ARM Serial Wire Debug SWD interface supports all programming and debug features of the device Complete debug on chip functionality enables full device debugging in the final system using the standard production device It does not require special interfaces debugging pods simulators or emulators Only the standard programming connections are required to fully support debug The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4000 devices The SWD interface is fully compatible with indust
14. KUK 02 24 2015 Updated Ordering Information No change in part numbers Updated Part Numbering Conventions Document Number 001 92145 Rev D Page 30 of 31 Automotive PSoC 4 PSoC F CYPRESS 4000 Family Datasheet PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions Automotive cypress com go automotive psoc cypress com solutions Clocks amp Buffers cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Interface cypress com go interface Cypress Developer Community Lighting amp Power Control cypress com go powerpsoc Community Forums Blogs Video Training cypress com go plc Technical Support Memory cypress com go memory PSoC cypress com go psoc cypress com go support Touch Sensing cypress com go touch USB Controllers cypress com go USB Wireless RF cypress com go wireless Cypress Semiconductor Corporation 2014 2015 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be us
15. LUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 92145 Rev D Revised February 24 2015 Page 31 of 31 All products and company names mentioned in this document may be the trademarks of their respective holders Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Cypress Semiconductor CY8CKIT 044
16. SoC 4000 consists of the internal main oscillator IMO and the internal low frequency oscillator ILO and provision for an external clock Figure 2 PSoC 4000 MCU Clocking Architecture IMO 3 D p Divide By External Clock connects to GPIO pin B 4 P Fcpu The Fepy signal can be divided down to generate synchronous clocks for the analog and digital peripherals There are four clock dividers for the PSoC 4000 each with 16 bit divide capability The 16 bit capability allows flexible generation of fine grained frequency values and is fully supported in PSoC Creator IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 4000 It is trimmed during testing to achieve the specified accuracy The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz The IMO tolerance with Cypress provided calibration settings is 2 24 and 32 MHz ILO Clock Source The ILO is a very low power 40 kHz oscillator which is primarily used to generate clocks for the watchdog timer WDT and peripheral operation in Deep Sleep mode ILO driven counters can be calibrated to the IMO to improve accuracy Cypress provides a software component which does the calibration Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the
17. analog converter see also IDAC VDAC ITM instrumentation trace macroc ll DFB digital filter block LCD liquid crystal display RIO NN aa AE digital LIN NAE Network a communications DMIPS Dhrystone million instructions per second R ace DMA direct memory access see also TD LUT lookup table DNL differential nonlinearity see also INL LVD low voltage detect see also LVI DNU go nor use LVI low voltage interrupt see also HVI Dh port wills data registers LVTTL low voltage transistor transistor logic DSI digital system interconnect MAC multiply accumulate DWT data watchpoint and trace MCU microcontroileruhit ECC error correcting code MISO masterinslavecaut ECO external crystal oscillator NG no connect EEPROM electrically erasable programmable read only NMI nonmaskable interrupt memory EMI electromagnetic interference NRZ non retuinto zero EMIF external memory interface NVIC nested vectored interrupt controller EOC and of conversion NVL nonvolatile latch see also WOL EOF andi frame opamp operational amplifier EPSR execution program status register PAL programmable array logic see also PLD ESD electrostatic discharge PO program counter PCB printed circuit board Document Number 001 92145 Rev D Page 26 of 31 ka BUG lt E CYPRESS PERFORM Table 30 Acronyms Used in this Document continued Automotive PSoC 4 PSoC 4000 Family Datasheet Table 30 Acronyms Used in this Document
18. ass capacitor parasitic should be simulated to design and obtain optimal bypassing An example of a bypass scheme follows Vppjo is available on the 16 QFN package Figure 5 24 pin QFN Bypass Scheme Example Unregulated External Supply Power supply connections when 1 8 sVpp lt 5 5V 1 8 Vto5 5V PSoC 4000 s DD 4 LF 0 1HF Veep 0 1 UF Vss Document Number 001 92145 Rev D Automotive PSoC 4 PSoC 4000 Family Datasheet Regulated External Supply In this mode the PSoC 4000 is powered by an external power supply that must be within the range of 1 71 to 1 89 V note that this range needs to include the power supply ripple too In this mode the Vpp and Vccp pins are shorted together and bypassed The internal regulator is disabled in the firmware An example of a bypass scheme follows Figure 6 24 pin QFN Bypass Scheme Example Regulated External Supply Power supply connections when 1 71 lt Vpop lt 1 89 V PSoC 4000 1 71 V to 1 89 V e DD IF Vecp ape 0 1 uF Page 8 of 31 SSS aa F CYPRESS PERFORM Development Support The PSoC 4000 family has a rich set of documentation devel opment tools and online resources to assist you during your development process Visit www cypress com go psoc4 to find out more Documentation A suite of do
19. be interrupted and cannot be relied on to have completed Reset sources include the XRES pin software resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activated 10 Guaranteed by characterization 11 Cypress provides a retention calculator to calculate the retention lifetime based on customers individual temperature profiles for operation over the 40 C to 105 C ambient temperature range Contact customercare cypress com 12 Cypress provides a retention calculator to calculate the retention lifetime based on customers individual temperature profiles for operation over the 40 C to 105 C ambient temperature range Contact customercare cypress com Document Number 001 92145 Rev D Page 18 of 31 ng ras eA ee a lt lt CYPRESS PERFORM SWD Interface Table 19 SWD Interface Specifications Automotive PSoC 4 PSoC 4000 Family Datasheet Spec ID Parameter Description Min Typ Max Units Details Conditions SID213 F SWDCLK1 3 3 V SVpp lt 5 5 V 14 MHz SWDCLKs 1 3 CPU clock frequency SID214 F SWDCLK2 1 71 V lt Vpp lt 3 3 V 7 MHz SWDCLK ss 1 3 CPU clock frequency SID215113 T_SWDI_SETUP T 1fSWDCLK
20. c independent buses that go around the periphery of the chip These buses called amux buses are connected to firmware programmable analog switches that allow the chip s internal resources IDACs comparator to connect to any pin on Ports 0 1 and 2 Fixed Function Digital Timer Counter PWM TCPWM Block The TCPWM block consists of a 16 bit counter with user programmable period length There is a capture register to record the count value at the time of an event which may be an I O event a period register that is used to either stop or auto reload the counter when its count is equal to the period register and compare registers to generate compare value signals that are used as PWM duty cycle outputs The block also provides true and complementary outputs with programmable offset between them to allow use as dead band programmable complementary PWM outputs It also has a Kill input to force outputs to a predetermined state for example this is used in motor drive systems when an over current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention Serial Communication Block SCB The PSoC 4000 has a serial communication block which imple ments a multi master I2C interface 12C Mode The hardware 1 C block implements a full multi master and slave interface it is capable of multi master arbitration This block is capable of operating at speeds of up to 400 kbps Fa
21. continued Document Number 001 92145 Rev D Acronym Description Acronym Description PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor transistor logic PLA programmable logic array TX transmit PLD programmable logic device see also PAL UART Universal Asynchronous Transmitter Receiver a PLL phase locked loop communications protocol PMDD package material declaration data sheet UDE universal digital block POR power on reset USB Universal Serial Bus PRES precise power on reset USBIO ee PSoC pins used to connect to PRS pse do random sequence VDAC voltage DAC see also DAC IDAC PS port read data register WDT watchdog timer PSoC Programmable System olny WOL write once latch see also NVL PSRR power supply rejection ratio WRES watchdog timer reset POM pulse width modulator XRES external reset I O pin RAM random access memory XTAL crystal RISC reduced instruction set computing RMS root mean square RTC real time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC CT switched capacitor continuous time SCL I2C serial clock SDA I2C serial data S H samp
22. cumentation supports the PSoC 4000 family to ensure that you can find answers to your questions quickly This section contains a list of some of the key documents Software User Guide A step by step guide for using PSoC Creator The software user guide shows you how the PSoC Creator build process works in detail how to use source control with PSoC Creator and much more Component Datasheets The flexibility of PSoC allows the creation of new peripherals components long after the device has gone into production Component data sheets provide all of the information needed to select and use a particular component including a functional description API documentation example code and AC DC specifications Application Notes PSoC application notes discuss a particular application of PSoC in depth examples include brushless DC motor control and on chip filtering Application notes often include example projects in addition to the application note document Document Number 001 92145 Rev D Automotive PSoC 4 PSoC 4000 Family Datasheet Technical Reference Manual The Technical Reference Manual TRM contains all the technical detail you need to use a PSoC device including a complete description of all PSoC registers The TRM is available in the Documentation section at www cypress com psoc4 Online In addition to print documentation the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around t
23. d Figure 6 show the set of power supply pins as implemented for the PSoC 4000 The system has one regulator in Active mode for the digital circuitry There is no analog regulator the analog circuits run directly from the Vpp input There is a separate regulator for the Deep Sleep mode The supply voltage range is either 1 8 V 5 externally regulated or 1 8 V to 5 5 V unregulated exter nally regulated internally with all functions and circuits operating over that range The PSoC 4000 family allows two distinct modes of power supply operation Unregulated External Supply and Regulated External Supply Unregulated External Supply In this mode the PSoC 4000 is powered by an external power supply that can be anywhere in the range of 1 8 to 5 5 V This range is also designed for battery powered operation For example the chip can be powered from a battery system that starts at 3 5 V and works down to 1 8 V In this mode the internal regulator of the PSoC 4000 supplies the internal logic and the Vecp output of the PSoC 4000 must be bypassed to ground via an external capacitor 0 1 uF X5R ceramic or better Bypass capacitors must be used from Vppp to ground The typical practice for systems in this frequency range is to use a capacitor in the 1 uF range in parallel with a smaller capacitor 0 1 uF for example Note that these are simply rules of thumb and that for critical applications the PCB layout lead induc tance and the byp
24. e part numbering convention described in the following table All fields are single character alphanumeric 0 1 2 9 A B Z unless stated otherwise The part numbers are of the form CY8C4ABCDEF XYZ where the fields are defined as follows Examples Cypress Prefix 4 PSoC4 Architecture 0 4000 Family Family Group within Architecture 1 16 MHz Speed Grade 4 16KB Flash Capacity ra BARA Package Code A AEC Q100 40 C to 85 C S AEC Q100 40 C to 105 C Document Number 001 92145 Rev D Temperature Range Peripheral Set CY8C 4ABCDEF xxx TJ Page 21 of 31 ers Automotive PSoC 4 PSoC d CYPRESS 4000 Family Datasheet PERFORM The Field Values are listed in the following table Field Description Values Meaning CY8C Cypress prefix 4 Architecture 4 PSoC 4 A Family 0 4000 Family B CPU speed 1 16 MHz 4 48 MHz C Flash capacity 3 8 KB 4 16 KB 5 32 KB 6 64 KB 7 128 KB DE Package code SX SOIC LQ QFN F Temperature range A S Automotive XYZ Attributes code 000 999 Code of feature set in specific family Document Number 001 92145 Rev D Page 22 of 31 Automotive PSoC 4 PSoC 4000 Family Datasheet Packaging Table 26 Package List Spec ID Package Description BID 26 24 pin QFN 24 pin 4 x 4 x 0 6 mm QFN with 0 5 mm pitch BID 40 16 pin SOIC 16 pin 150 Mil SOIC Table 27 Package Cha
25. ed for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INC
26. he world 24 hours a day 7 days a week Tools With industry standard cores programming and debugging interfaces the PSoC 4000 family is part of a development tool ecosystem Visit us at www cypress com go psoccreator for the latest information on the revolutionary easy to use PSOC Creator IDE supported third party compilers programmers debuggers and development kits Page 9 of 31 Z Automotive PSoC 4 PSoC Sa CYPRESS 4000 Family Datasheet Electrical Specifications Absolute Maximum Ratings Table 2 Absolute Maximum Ratings Spec ID Parameter Description Min Typ Max Units Bled tie SID1 VDDD ABS Digital supply relative to Vss 0 5 6 V SID2 Vecp ABS Direct digital core voltage input relative 0 5 7 1 95 V T to Vss SID3 VGPIO_ABS GPIO voltage 0 5 Vppt0 5 V SID4 IGPIO_ABS Maximum current per GPIO 25 25 mA SID5 IGPIO injection GPIO injection current Max for Vip gt 0 5 0 5 mA Current injected Vppp and Min for Vj lt Vss per pin BID44 ESD HBM Electrostatic discharge human body 2200 V model BID45 ESD_CDM Electrostatic discharge charged device 500 V model BID46 LU Pin current for latch up 140 140 mA Note 1 Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability The Maximum Storage Tem
27. high range SID315A IDAC26p72 Output current of IDAC2 7 bits in 152 4 KA low range SID320 IDACOFFSET All zeroes input 1 LSB SID321 IDACgain Full scale error less offset 10 SID322 IDACwismatcH Mismatch between IDACs 7 LSB SID323 IDACsET8 Settling time to 0 5 LSB for 8 bit 10 us Full scale transition No IDAC external load SID324 IDACsg17 Settling time to 0 5 LSB for 7 bit 10 NG Full scale transition No IDAC external load SID325 CMOD External modulator capacitor 2 2 nF 5 V rating X7R or NPO cap Document Number 001 92145 Rev D Page 15 of 31 bn Tian Z Automotive PSoC 4 PSoC CYPRESS 4000 Family Datasheet PERFORM Digital Peripherals Timer Counter Pulse Width Modulator TCPWM Table 12 TCPWM Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID TCPWM 1 ITCPWM1 Block current consumption at 3 MHz 45 pA All modes TCPWM SID TCPWM 2 ITCPWM2 Block current consumption at 8 MHz 145 HA All modes TCPWM SID TCPWM 2A ITCPWM3 Block current consumption at 16 MHz 160 yA All modes TCPWM Fc max CLK SYS SID TCPWM 3 TCPWMppeo Operating frequency Fc MHz Maximum 16 MHZ SID TCPWM 4 TPWMenext Input trigger pulse width 2IFc ns For all trigger events Minimum possible width of Overflow i P Underflow and CC SID TCPWM 5 TPWMex7 Output t
28. ical thermal and electrical performance Page 24 of 31 Note 15 Dimensions of the QFN package drawings are in millimeters Document Number 001 92145 Rev D Automotive PSoC 4 PSoC 4000 Family Datasheet a Fa CYPRESS PERFORM Figure 8 16 pin SOIC 150 Mils Package Outline PIN 1 ID 8 1 NOTE 1 DIMENSIONS IN INCHESIMM MAX 2 REFERENCE JEDEC MS 012 3 PACKAGE WEIGHT refer to PMDD spec 001 04308 0 150 3 810 0 157 3 987 0 230 5 842 0 244 6 197 PART 16 15 STANDARD PKG SZ16 15 LEAD FREE PKG 0 01010 254 X 45 9 16 0 386 9 804 016 0 406 i3998 SEATING PLANE 00160 4061 E 0 061 1 549 a CI 0 0075 0 190 0 0098 0 249 ig 0 068 1 727 ing paang NN paang t re 0 004 0 102 0 01610 406 0 03510 889 51 85068 E i 0 004t0 1023 ee 0 050L1 270 BSC 0 013800 350 _ Ly 0 019200 487 0 009810 249 Document Number 001 92145 Rev D Page 25 of 31 peu FE Sa 2 CYPRESS PERFORM Automotive PSoC 4 PSoC 4000 Family Datasheet
29. ided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input Proximity sensing can also be implemented The CapSense block has two IDACs which can be used for general purposes if CapSense is not being used both IDACs are available in that case or if CapSense is used without water tolerance one IDAC is available Page 5 of 31 Cypress PERFORM Automotive PSoC 4 PSoC 4000 Family Datasheet Pinouts The following is the pin list for PSoC 4000 All Port pins support GPIO Ports O 1 and 2 support CSD CapSense and analog mux bus connections Table 1 PSoC 4000 Pin Descriptions 24 QFN 16 SOIC Pin Name Pin Name TCPWM Signals Alternate Functions 1 P0 0 TRINO TRINO Trigger Input 0 2 P0 1 TRIN1 3 P0 1 TRIN1 CMPO_0 TRIN1 Trigger Input 1 CMPO_0 Sense Comp Out CMPO 0 3 P0 2 TRIN2 4 P0 2 TRIN2 TRIN2 Trigger Input 2 4 P0 3 TRIN3 TRIN3 Trigger Input 3 5 P0 4 TRIN4 5 P0 4 TRIN4 CMPO 0 TRIN4 Trigger Input 4 CMPO_0 Sense Comp Out External CMPO EXT CLK EXT_CLK Clock CMOD Cap 6 VCCD 6 VCCD 7 VDD 7 VDD 8 VSS 8 VSS 9 P0 5 9 P0 5 10 P0 6 10 P0 6 11 P0 7 12 P1 0 13 P1 1 OUTO 11 P1 1 OUTO OUTO PWM OUT 0 14 P1 2 SCL 12 P1 2 SCL 12C SCL SWD Clock SWD_CLK SWD_CLK 15 P1 3 SDA 13 P1 3 SDA I2C Data SWD Data SWD_IO SWD_IO 16 P1 4 UNDO UNDO Underflow Out 17 P1 5 OVFO OVFO Ove
30. le and hold SINAD signal to noise and distortion ratio SIO special input output GPIO with advanced features See GPIO SOC start of conversion SOF start of frame SPI Serial Peripheral Interface a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug a test protocol SWV single wire viewer TD transaction descriptor see also DMA Page 27 of 31 Z Automotive PSoC 4 PSoC Sar CYPRESS 4000 Family Datasheet Document Conventions Units of Measure Table 31 Units of Measure Symbol Unit of Measure C degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz kQ kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MQ mega ohm Msps megasamples per second HA microampere uF microfarad uH microhenry Us microsecond UV microvolt uW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt Q ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number 001 92145 Rev D Page 28 of 31 Q W na W ay Hi tn TA Revision History Orig of PERFORM Automotive PSoC 4 PSoC 4000 Family Datasheet
31. mer to make Page 3 of 31 a E Jf CYPRI ESS Functional Definition CPU and Memory Subsystem CPU The Cortex M0 CPU in the PSoC 4000 is part of the 32 bit MCU subsystem which is optimized for low power operation with extensive clock gating Most instructions are 16 bits in length and the CPU executes a subset of the Thumb 2 instruction set This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex M3 and M4 It includes a nested vectored interrupt controller NVIC block with eight interrupt inputs and also includes a Wakeup Interrupt Controller WIC The WIC can wake the processor from the Deep Sleep mode allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode The CPU also includes a debug interface the SWD interface which is a 2 wire form of JTAG The debug configuration used for PSoC 4000 has four breakpoint address comparators and two watchpoint data comparators Flash The PSoC 4000 device has a flash module with a flash accel erator tightly coupled to the CPU to improve average access times from the flash block The low power flash block is designed to deliver zero wait state WS access time at 16 MHz The flash accelerator delivers 85 of the single cycle SRAM access performance on average SRAM Two KB of SRAM are provided with zero wait state access at 16 MHz SROM A supervisory ROM that contains b
32. oot and configuration routines is provided System Resources Power System The power system is described in detail in the section on Power on page 8 It provides an assurance that voltage levels are as required for each respective mode and either delays mode entry for example on power on reset POR until voltage levels are as required for proper functionality or generates resets for example on brown out detection The PSoC 4000 operates with a single external supply over the range of either 1 8 V 5 externally regulated or 1 8 to 5 5 V internally regulated and has three different power modes transitions between which are managed by the power system The PSoC 4000 provides Active Sleep and Deep Sleep low power modes All subsystems are operational in Active mode The CPU subsystem CPU flash and SRAM is clock gated off in Sleep mode while all peripherals and interrupts are active with instan taneous wake up on a wake up event In Deep Sleep mode the high speed clock and associated circuitry is switched off wake up from this mode takes 35 US Document Number 001 92145 Rev D Automotive PSoC 4 PSoC 4000 Family Datasheet Clock System The PSoC 4000 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching In addition the clock system ensures that there are no metastable conditions The clock system for the P
33. perature is 150 C in compliance with JEDEC Standard JESD22 A103 High Temperature Storage Life When used below Absolute Maximum conditions but above normal operating conditions the device may not operate to specification Document Number 001 92145 Rev D Page 10 of 31 _ __ m E C ee a YPRESS PERFORM Device Level Specifications All specifications are valid for 40 C lt Ty lt 85 C for A grade devices and 40 C lt Ta lt 105 C for S grade devices except where noted Specifications are valid for 1 71 V to 5 5 V except where noted Table 3 DC Specifications Typical values measured at Vpp 3 3 V and 25 C Automotive PSoC 4 PSoC 4000 Family Datasheet Spec ID Parameter Description Min Typ Max Units Gag SID53 Vpp Power supply input voltage 1 8 5 5 V With regulator enabled SID255 Vpp Power supply input voltage Vecp 1 71 1 89 V Internally Vpp unregulated supply SID54 Vpplo Vppio domain supply 1 71 Vpp V SID55 Cerc External regulator voltage bypass 0 1 UF X5R ceramic or better SID56 Cexc Power supply bypass capacitor 1 HF X5R ceramic or better Active Mode Vpp 1 8 to 5 5 V SID9 Ipps Execute from flash CPU at 6 MHz 2 0 2 85 mA SID12 IPD8 Execute from flash CPU at 12 MHz 3 2 3 75 mA SID16 Ipp11 Execute from flash CPU at 16 MHz 4 0
34. racteristics Parameter Description Conditions Min Typ Max Units Ta Operating ambient temperature For A grade devices 40 25 00 85 C Ta Operating ambient temperature For S grade devices 40 25 00 105 C Ty Operating junction temperature For A grade devices 40 100 C Tj Operating junction temperature For S grade devices 40 120 C Tya Package 0 24 pin QFN 38 01 C Watt Tja Package 954 16 pin SOIC 142 14 C Watt Table 28 Solder Reflow Peak Temperature Maximum Peak Package Temperature Maximum Time at Peak Temperature All 260 C 30 seconds Table 29 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 020 Package MSL All MSL 3 Page 23 of 31 Document Number 001 92145 Rev D Sy Automotive PSoC 4 PSoC CYPRESS 4000 Family Datasheet PERFORM Package Outline Drawings Figure 7 24 pin QFN EPAD Sawn Package Outline TOP VIEW SIDE VIEW BOTTOM VIEW i UUUUUU I NG CT osoen a 1 a T per aaa Bo Kill MC 9 4020 IAD trti oO H 001 13937 E NOTES 1 588 HATCH IS SOLDERABLE EXPOSED 2 REFERENCE JEDEC MO 24 PACKAGE WEIGHT 29 t 3 mg DIMENSIONS ARE IN MILLIMETE If not connected to ground it should be electrically floating and not connected to any other signal ALL 4 The center pad on the QFN package should be connected to ground VSS for best mechan
35. rflow Out 18 P1 6 OVFO UNDO 14 P1 6 OVFO UNDO nOUTO Complement of CMPO_0 Sense Comp Out Internal nOUTO CMPO_0O nOUT0 CMPO 0 OUTO not OUT Reset function during POR must not have load to ground during POR 19 P1 7 MATCH EXT C 15 P1 7 MATCH EXT_C MATCH Match Out External Clock LK LK 20 P2 0 16 P2 0 21 P3 0 SDA 1 P3 0 SDA I2C Data SWD IO SWD_IO SWD_IO 22 P3 1 SCL 2 P3 1 SCL 12C Clock SWD Clock SWD_CLK SWD_CLK 23 P3 2 OUTO PWM OUT 0 24 XRES XRES External Reset Document Number 001 92145 Rev D Page 6 of 31 Automotive PSoC 4 PSoC 4000 Family Datasheet s CYPRESS PERFORM Descriptions of the Pin functions are as follows VDD Power supply for both analog and digital sections VSS Ground pin VCCD Regulated digital supply 1 8 V 2596 Pins belonging to Ports 0 1 and 2 can all be used as CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins that can be driven by the firmware Pins on Port 3 can be used as GPIO in addition to their alternate functions listed above The following packages are provided 24 pin QFN and 16 pin SOIC Figure 3 24 pin QFN Pinout un Se See SOO tS Y oo ise ise N T hn A Figure 4 16 pin SOIC Pinout 16 SOIC Top View Document Number 001 92145 Rev D Page 7 of 31 SS SSS Nag AA F CYPRESS PERFORM Power The following power system diagrams Figure 5 an
36. rigger pulse widths 2 Fc ns Counter equals Compare value outputs Minimum time SID TCPWM 5A TCpes Resolution of counter 1 Fe ns between successive counts SID TCPWM 5B PWM PWM resolution Fc ns Minimum pulse width i RER of PWM Output Minimum pulse width SID TCPWM 5C Qres Quadrature inputs resolution 1 Fec ns between Quadrature phase inputs Note 7 Guaranteed by characterization Document Number 001 92145 Rev D Page 16 of 31 Automotive PSoC 4 PSoC 4000 Family Datasheet bn Fa W CYPRESS PERFORM PC Table 13 Fixed IZC DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID149 loca Block current consumption at 100 kHz 25 HA SID150 li2c2 Block current consumption at 400 kHz 135 HA SID152 li2c4 IZC enabled in Deep Sleep mode CU 2 5 HA Table 14 Fixed I2C AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID153 Fioci Bit rate 400 Kbps Note 8 Guaranteed by characterization Document Number 001 92145 Rev D Page 17 of 31 Memory j CYPRESS PERFORM Table 15 Flash DC Specifications Automotive PSoC 4 PSoC 4000 Family Datasheet
37. ry standard third party tools The PSoC 4000 family provides a level of security not possible with multi chip application solutions or with microcon trollers It has the following advantages m Allows disabling of debug features m Robust flash protection m Allows customer proprietary functionality to be implemented in on chip programmable blocks Document Number 001 92145 Rev D Read Accelerator System Interconnect Single Multi Layer AHB PCLK Peripheral Interconnect MMIO SPCIF ROM 4 KB SRAM 2 KB SRAM Controller Flash 16KB ROM Controller 1x TCPWM 1x SCB 12C LOSS GPIO 4x ports 20 x GPIOs The debug circuits are enabled by default and can only be disabled in firmware If they are not enabled the only way to re enable them is to erase the entire device clear flash protection and reprogram the device with new firmware that enables debugging Additionally all device interfaces can be permanently disabled device security for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences All programming debug and test interfaces are disabled when maximum device security is enabled Therefore PSoC 4000 with device security enabled will have only limited capability for failure analysis This is a trade off the PSoC 4000 allows the custo
38. set timeout occurs The watchdog reset is recorded in a Reset Cause register which is firmware readable Reset The PSoC 4000 can be reset from a variety of sources including a software reset Reset events are asynchronous and guarantee reversion to a known state The reset cause is recorded ina register which is sticky through reset and allows software to determine the cause of the reset An XRES pin is reserved for external reset on the 24 pin package An internal POR is provided on the 16 pin package The XRES pin has an internal pull up resistor that is always enabled Voltage Reference The PSoC 4000 reference system generates all internally required references A 1 2 V voltage reference is provided for the comparator The IDACs are based on a 5 reference Page 4 of 31 SSS aa Sa CYPRESS SS az _ PERFORM Analog Blocks Low power Comparators The PSoC 4000 has a low power comparator which uses the built in voltage reference Any one of up to 16 pins can be used as a comparator input and the output of the comparator can be brought out to a pin The selected comparator input is connected to the minus input of the comparator with the plus input always connected to the 1 2 V voltage reference Current DACs The PSoC 4000 has two IDACs which can drive any of up to 16 pins on the chip These IDACs have programmable current ranges Analog Multiplexed Buses The PSoC 4000 has two concentri
39. st Mode and has flexible buffering options to reduce interrupt overhead and latency for the CPU It also supports EZ12C that creates a mailbox address range in the memory of the PSoC 4000 and effectively reduces C commu nication to reading from and writing to an array in memory In addition the block supports an 8 deep FIFO for receive and transmit which by increasing the time given for the CPU to read data greatly reduces the need for clock stretching caused by the CPU not having read data on time The I2C peripheral is compatible with the 12C Standard mode and Fast mode devices as defined in the NXP I2C bus specification and user manual UM10204 The I2C bus I O is implemented with GPIO in open drain modes Document Number 001 92145 Rev D Automotive PSoC 4 PSoC 4000 Family Datasheet The PSoC 4000 is not completely compliant with the I2C specin the following respect m GPIO cells are not overvoltage tolerant and therefore cannot be hot swapped or powered up independently of the rest of the Cc system GPIO The PSoC 4000 has up to 20 GPIOs The GPIO block imple ments the following m Eight drive modes a Analog input mode input and output buffers disabled a Input only a Weak pull up with strong pull down a Strong pull up with weak pull down a Open drain with strong pull down a Open drain with strong pull up a Strong pull up with strong pull down a Weak pull up with weak pull down m Input threshold
40. t Number 001 92145 Rev D Page 19 of 31 Automotive PSoC 4 PSoC 4000 Family Datasheet CYPRESS i Typ Max Units MHz Details Conditions PERFORM Table 24 External Clock Specifications Spec ID Parameter Description Min SID305 41 ExtClkFreq External clock input frequency 0 SID306 74 ExtCIkDuty Duty cycle measured at Vpp 2 45 55 Table 25 Block Specs Spec ID Parameter Description Min Typ Max Units Details Conditions siD262174 TCLKSWITCH System clock source switching time 3 4 Periods Note 14 Guaranteed by characterization Document Number 001 92145 Rev D Page 20 of 31 y Sa Pad F CYPRESS PERFORM Ordering Information The PSoC 4000 part numbers and features are listed in the following table Automotive PSoC 4 PSoC 4000 Family Datasheet MPN Features Package Operating Temperature N Dn szialelolo 5 5 9 6 a o oO SISh2 28 ele sa e Ss amp 8 S o kun oO Q Q O ols zla lz la giz m D gG 3 o a o s S d5 2 o 3 la le e 2 2 2 lo KE Ka 5 gt pee o o F x o 2 CY8C4014SXA 421 16 16 2 Vv 1 1 1 1 1 Vv Vv CY8C4014LQA 422 16 16 2 Vv 1 1 1 1 1 Vv CY8C4014SXS 421 16 16 2 Y 1 1 1 1 1 Vv CY8C4014LQS 422 16 16 2 Vv 1 1 1 1 1 Vv Part Numbering Conventions PSoC 4 devices follow th
41. ut Vppp lt 2 7 V 0 3 x V VDDD SID243 Va LVTTL input Vppp 2 2 7 V 2 0 V SID244 Vir LVTTL input Vppp 2 2 7 V 0 8 V SID59 VoH Output voltage high level Vppp V lop 4 mA at 0 6 3 V Vppp SID60 VoH Output voltage high level Vppp V lon 1 mA at 0 5 1 8 V Vppp SID61 VoL Output voltage low level 0 6 V lo 4 mA at 1 8 V Vppp SID62 VoL Output voltage low level 0 6 V lo 10 mA at SID62A VoL Output voltage low level 0 4 V loL 3 mAat3 V VDDD SID63 RpuLLup Pull up resistor 3 5 5 6 8 5 kQ SID64 RpuLLDOWN Pull down resistor 3 5 5 6 8 5 kQ SID65 lie Input leakage current absolute value 2 nA 25 C Vppp 3 0 V SID66 Cin Input capacitance 3 7 pF SID67F VHYSTTL Input hysteresis LVTTL 15 40 mV Vppp22 7V SID68P Vuyscmos Input hysteresis CMOS 0 05 x mV Vpp lt 4 5 V VDDD SID68AP Vuyscmossvs Input hysteresis CMOS 200 7 mV Vpp gt 4 5 V SID69P IDIODE Current through protection diode to 100 KA Vpp Vss SID69AP ITOT GPIO Maximum total source or sink chip 85 mA current Notes 3 Guaranteed by characterization 4 Vjy must not exceed Vppp 0 2 V 5 Guaranteed by characterization Document Number 001 92145 Rev D Page 12 of 31 n is 2 CYPRESS PERFORM Table 6 GPIO AC Specifications Guaranteed by Characterization Automotive PSoC 4 PSoC 4000 Family Datasheet
42. y Datasheet CSD Table 11 CSD and IDAC Block Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions CSD and IDAC Specifications SYS PER 3 VDD RIPPLE Max allowed ripple on power supply 50 mV VDD gt 2V with ripple DC to 10 MHz 25 C Ta Sensitivity 0 1 pF SYS PER 16 VDD RIPPLE 1 8 Max allowed ripple on power supply 25 mV VDD gt 1 75V with DC to 10 MHz ripple 25 C T Parasitic Capacitance p lt 20 pF Paba 2 0 4 pF SID CSD 15 VREF Voltage reference for CSD and 1 1 1 2 1 3 V Comparator SID CSD 16 IDAC1IDD IDAC1 8 bits block current 1125 HA SID CSD 17 IDAC2IDD IDAC2 7 bits block current 1125 HA SID308 Vesp Voltage range of operation 1 71 5 5 V 1 8 V 5 or 1 8 V to 5 5 V SID308A VCOMPIDAC Voltage compliance range of IDAC 0 8 Vpp 0 8 V SID309 IDAC1pn DNL for 8 bit resolution 1 1 LSB SID310 IDAC1 NL INL for 8 bit resolution 3 3 LSB SID311 IDAC2pn DNL for 7 bit resolution 1 1 LSB SID312 IDAC2 NL INL for 7 bit resolution 3 3 LSB SID313 SNR Ratio of counts of finger to noise 5 Ratio Capacitance range of 9 to Guaranteed by characterization 35 pF 0 1 pF sensitivity SID314 IDAC1gp11 Output current of IDAC1 8 bits in 612 KA high range SID314A IDAC1cRT2 Output current of IDAC1 8 bits in 306 HA low range SID315 IDAC2gp71 Output current of IDAC2 7 bits in 304 8 HA
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