Integrated Device Technology
Contents
1. 12 21 0 mA 0 lt Vour lt 0 3 V cl 0 Switching 17A V Vout _ mA 0 3 VeclO lt Vour lt 0 9 1 0 32 V 1 0 0 7 4 0 16 V cl O See Note 1 mA 0 7 V l 0 lt Vour lt Vecl O lo AC 16 1 0 mA Vecl O gt Vour gt 0 6 V cl 0 Switching 326 T Vour eri mA 0 6 V Cl O gt Vout gt 0 1 V cl O 438 4 0 mA Vour 0 18 4 0 See Note 2 mA 0 18 V 41 0 gt Vour gt 0 Vi 0 3 0 3 V 1 0 0 5 V cl 0 5 5 V Capacitance EE 10 5 pF Leakage Inputs 10 HA Vcc max V O LEak w o 10 uA Vcc max P ull ups downs 1 0 EAK WITH 80 uA Vcc max P ull ups downs Table 18 DC Electrical Characteristics Note 1 lop AC max 88N ccl O Vout Vccl 0 Vout 04 1 0 Note 2 loi max 256Nccl 0 Vour Vccl O Vout 38 of 53 January 19 2006 IDT RC32434 AC Test Conditions Input Reference Voltage 500 RC32434 Test Output e 500 Point Value Parameter Units SSTL I O Other I O Input pulse levels 0 to 2 5 0 to 3 3 V Input rise fall 0 8 1 0 ns Input reference level 0 5 51 0 0 5 Vccl 0 V Output reference levels 1 25 15 V AC testload 35 35 pF Figure 23 AC Test Conditions 39 of 53 January 19 2006 IDT RC32434 Absolute Maximum Ratings Symbol Parameter2. Bererence 266MHz 300MHz 350MHz 400MHz Condi Timing Signal Symbol Edge Unit tions Diagram g Min Max Min Max Min Max Min Max Reference Reset COLDRSTN none osc 1 086 OSC ms oldreset Figures 4 Trise_6a none 5 0 5 0 5 0 5 0 ns Cold reset anda RSTN input Tpw_6b none ACLK ns Warm reset RSTN output Tdo 6c COLDRSTN 15 0 15 0 15 0 15 0 ns Coldreset falling MADDR 15 0 Tdz 602 COLDRSTN 30 0 30 0 30 0 30 0 ns Coldreset boot vector falling 692 RSTN falling 5 CLK 5 CLK 5 CLK 5 CLK ns Warm reset Tzd_6d2 RSTN rising 2 CLK 2 CLK 2 CLK ns Warm reset Table 6 Reset and System AC Timing Characteristics 1 The COLDRSTN minimum pulse width is the oscillator stabilization time OSC with stable 2 The values for this symbol were determined by calculation not by testing 3 RSTN is a bidirectional signal It is treated as an asynchronous input 17 of 53 January 19 2006 IDT RC32434
3. guarantee functional timing provided the RC 32434 DDR layout guidelines are adhered to Rafaren 266MHz 300MHz 350MHz 400MHz Timing Signal Symbol Ed x Unit Diagram g Min Max Min Max Min Max Min Max Reference Memory Bus DDR Access DDRDATA 15 0 Tskew 7g DDRDQSx 0 0 9 0 0 8 0 0 7 0 0 0 6 ns SeeFigures 6 Tdo 7 ix p 19 10 ur p or 15 05 34 DDRDM 1 0 Tdo 7l DDRDQSx 12 1 9 1 0 1 7 0 7 1 5 0 5 1 4 ns DDRDQS 1 0 Tdo 7i DDRCKP 0 75 0 75 0 75 0 75 0 7 0 7 0 7 0 7 ns DDRADDR 13 0 Tdo 7m DDRCKP 1 0 4 0 1 0 4 3 1 0 4 0 10 4 0 ns DDRBA 1 0 DDRCASN DDRCKE DDRCSN DDRRASN DDRWEN Table 7 DDR SDRAM Timing Characteristics Meets DDR timing requirements for 150MHz clock rate DDR SDRAMs with 300 ps remaining margin to compensate for PCB propagation mismatches which is adequate to 2 Setup times are calculated as applicable clock period Tdo max For example if the DDR is running at 266MHz it uses a 133MHz input clock The period fora 133MHz clock is 7 5ns If the Tdo max value is 4 6ns the parameter is 7 5ns minus 4 6ns 2 9ns The DDR spec for this parameter is 1ns so there is 1 9ns of slack left over for board propagation Calculations for Tps are similar butsince this parameter is taken relative to the DDRDQS signals which are referenced on both edges the effective period with 133MHz input clock is only 3 75ns So if the max is 1 9ns we have 3 75ns minus 1 9ns 1 8
4. 266MHz 300MHz 350MHz 400MHz Timing Reference Condi Signal Symbol Edae Unit toas Diagram g Min Max Min Max Min Max Min Max Reference EJ TAG and J TAG JTAG TCK Tper 16a none 25 0 50 0 25 0 50 0 25 0 50 0 25 0 50 0 ns See Figure 19 Thigh 16a 10 0 25 0 10 0 25 0 10 0 25 0 10 0 25 0 ns Tlow 16a JTAG 51 Tsu 16b JTAG 24 24 24 24 ns JAG TDI ITR 16 nising emen esp Si JTAG TDO Tdo 16c JTAG TCKfal 113 11 3 113 11 3 ns Tdz 160 ng eer T e e ABER JTAG TRST Tpw 16d none 250 250 250 250 ns N EJTAG 51 Tsu 16e JTAG TCK 2 0 2 0 2 0 2 0 ns Thid_6e nising oak Ih ns Table 14 J TAG AC Timing Characteristics l The J TAG specification IEEE 1149 1 recommends that both TMS and 5 should be held at 1 while the signal applied at TAG_TRST_N changes from 0 to 1 Otherwise a race may occur if TAG_TRST_N is deasserted going from low to high on a rising edge of J when either TAG_TMS or EJ TAG_TMS is low because the TAP controller might go to either the Run Test Idle state or stay in the Test Logic R eset state 2 The values for this symbol were determined by calculation not by testing 32 of 53 January 19 2006 IDT RC32434 Tlow_16a a gt Tper_16a Thigh_16a lt
5. O01gF 100pF s Vss V P LL VegPLL Figure 21 PLL Filter Circuit for Noisy Environments 34 of 53 January 19 2006 IDT RC32434 Recommended Operating Supply Voltages Symbol Parameter Minimum Typical Maximum Unit Voc Common ground 0 0 0 V V PLL PLL ground 1 0 supply except for SSTL_21 3 135 3 3 3 465 V V cSI O DDR I O supply for SSTL 2 2 315 2 5 2 625 V V P LL PLL supply digital 1 1 1 2 1 3 V V AP LL PLL supply analog 3 135 3 3 3 465 V V Core Internal logic supply 1 1 1 2 13 V DDRVREF2 SSTL_2 input reference 0 5 51 0 Q 5 VccSI O 0 5 51 0 voltage Ver SSTL_2 termination voltage DDRVREF 0 04 DDRVREF DDRVREF 0 04 V Table 15 RC32434 Operating Voltages 1 SSTL_2 I Os are used to connect to DDR SDRAM 2 P eak to peak AC noise DDRVREF may not exceed 2 DDRVREF DC Var of the SSTL_2 transmitting device must track DDRVREF of the receiving device Recommended Operating Temperatures Grade Temperature Commercial 0 C to 70 C Ambient Industrial 40 C to 85 C Ambient Table 16 RC32434 Operating Temperatures Capacitive Load Deration Refer to the 79RC 32434 IBIS Model on the IDT web site www idt com 35 of 53 January 19 2006 IDT RC32434 Power on Sequence Three power on sequences are given below Sequence 1 is recommended because it will prevent 1 0 conflicts and
6. JTAG_TCK 2 N d N N Thld 16b p x lt Tsu 16 gt JTAG TDI gt Thid 16b gt FK Tsu 160 gt JTAG GD ss Thid 166 K Tsu 16 TMS gt lt Tdo_16c lt Tdz_16c JTAG TDO K Tpw 16d gt JTAG Figure 19 J TAG AC Timing Waveform The IEEE 1149 1 specification requires that the TAG and EJ TAG controllers be reset at power up whether or not the interfaces are used for a boundary scan or a probe Reset can occur through a pull down resistor on J TAG_TRST_N if the probe is not connected However on chip pull up resistors are implemented on the RC32434 due to an IEEE 1149 1 requirement Having on chip pull up and external pull down resistors for the JTAG TRST N signal requires special care in the design to ensure that a valid logical level is provided to J TAG_TRST_N such as using a small external pull down resistor to ensure this level overrides the on chip pull up An alternative is to use an active power up reset circuit for JTAG TRST which drives J TAG TRST low only at power up and then holds J TRST high afterwards with a pull up resistor Figure 20 shows the electrical connection of the EJ TAG probe target system connector VDD 3 3 RC32434 1 JTAG TRST lt TRST ug OND JTAG TDI lt
7. MITXCLIK N N 9f Tdo 9f MIITXEN MIITXD 3 0 MIITXER lt x Ve Y Thigh_9i Tper 3i Tlow 9i RMIRECIK YN C N SN Tdo 9j RMITXEN 159 9 91 gt TE RMII TXD LO X X X X y 9j Thigh 9i Tlow 9i RMIREECIK N N FN WE a NN Tsu 9k RMIICRS_DV RMII RXER V T Y v RMII RXD 1 0 Figure 10 Ethernet AC Timing Waveform 26 of 53 January 19 2006 IDT RC32434 Ref 266MHz 300MHz 350MHz 400MHz Condi Timing Signal Symbol 2 Unit tions Diagram g Min Max Min Max Min Max Min Max Reference 10 150 30 0 150 300 150 300 150 30 0 ns 66 2 SeeFigure 11 PCI Thigh 10a 6 0 6 0 6 0 6 0 ns Tlow_10a Tslew_10a 15 4 0 15 4 0 15 4 0 15 4 0 Vins PCIAD 31 0 Tsu 10b PCICLK rising 3 0 3 0 3 0 3 0 ns PCIBEN 3 0 PCIDEVSELN Thld 10b 0 0 0 0 ns PCIFRA Tdo_10b 2 0 6 0 2 0 6 0 2 0 6 0 2 0 6 0 ns MEN PCIIR 5 DYN Tdz_10b _ 14 0 _ 14 0 _ 14 0 _ 14 0 ns PCILOCKN Tzd 10b3 2 0 _ 2 0 _ 2 0 _ 2 0 ns PCIPAR PCI PERRN PCIS TOPN PCITRDY PCIGNTN 3 0 Tsu 10 PCICLK rising 5 0 5 0 5 0 5 0 ns PCIREQNI3 01 10c 1 591 91 91 1s Tdo 10c 2 0 6 0 2 0 6
8. 5 92 ns Tzd_8k2 ns WEN Tdo 81 rising 0 4 3 7 0 4 3 0 4 3 0 4 3 ns 8l ns Tzd 817 ns Table 8 Memory and Peripheral Bus AC Timing Characteristics Part 2 of 2 l The RC32434 provides bus turnaround cycles to prevent bus contention when going from read to write write to read and during extemal bus ownership For example there are no cycles where an external device and the R C32434 are both driving See Chapter 6 Device Controller in the RC32434 User Reference Manual 2 The values for this symbol were determined by calculation not by testing 3 The frequency of EXTCLK is programmable See the External Clock Divider MDATA 5 4 description in Table 3 of this data sheet WAITACKN must meet the setup and hold times if itis synchronous or the minimum pulse width if it is asynchronous 22 of 53 January 19 2006 IDT RC32434 ge EXTCLK NF NZS Vv NZS V0 4 4 FN Tdo_8a riow 21 01 Addr 21 0 2 2 T do 8b gt MADDR 25 22 wa Addr25 22 RWN Tdo_8i Tdo 8i gt CSN 3 0 e WEN 1111 8 gt Thld 8c I Tdz 8c lt gt Tsu 8c Tzd_8c gt 7 01 Data Tdo_8e Bde Tdo_8e BDIRN read data Tdo_8f c Tdo_8f BOEN WAITACK
9. B15 MADDR 3 F15 DDRDM 0 K15 DDRADDR 10 P15 DDRADDR 2 B16 MADDR 1 16 DDRDATA 7 K16 DDRADDR 12 P16 DDRCSN Gl IRXDV L1 SDA R1 PCIAD 25 Table 20 RC32434 Pinout Part 1 of 2 41 of 53 January 19 2006 IDT RC32434 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt 2 BDIRN 62 MITXER L2 SCL R2 PCICBEN 3 C3 COLDRSTN G3 MIIRXER L3 8 1 PCIAD 23 4 WEN 64 MIITXCLK L4 SDI R4 PCIAD 21 C5 DATA 3 65 1 0 L5 Vec 1 0 R5 PCIAD 17 C6 DATA 5 G6 Vc L6 Vss R6 PCIRSTN C7 GPIO 6 1 67 V L7 Vss R7 PCICBEN 2 C8 ADDR 21 68 V L8 Vec CORE R8 PCITRDYN C9 ADDR 18 69 Vcc L9 Vss R9 PCICBEN 1 C10 MADDR 14 610 Ves 10 Veg R10 PCIAD 12 C11 JTAG TMS 611 Vo 11 Ves R11 PCIAD 8 C12 Vec APLL G12 Vec DDR L12 Vec DDR R12 PCIAD 5 CLK 613 DDRDM I L13 DDRADDR 9 R13 PCIAD 3 C14 MADDR 4 614 DDRDQS I L14 DDRWEN R14 PCIAD O C15 ADDR 0 615 DDRDATA 10 15 DDRCASN R15 PCIGNTN 2 C16 DDRDATA O G16 DDRDATA 11 L16 DDRADDR 8 R16 DDRADDR I D1 IRXD 0 IIMDIO 1 GPIO 12 1 PCIAD 24 D2 ICL H2 IIMDC 2 PCIAD 31 T2 GPIO 13 1 D3 ICRS H3 GPIO 0 1 3 GPIO I1 1 T3 PCIAD 22 D4 IRXD 1 H4 GPIO 1 1 4
10. CLK COLDRSTN RSTN Na I 1 1 1 1 MADDR 15 0 ra s u wAI L Driven XK MADDR 21 16 X Driven IP X MEN JI ll jr der d lt pia gt gt 4000 CLK gt 4000 CLK COLDRSTN sampled negated high by the RC32434 clock cycles Clock cycles 1 EXTBCV is asserted i e pulled up COLDRSTN is asserted by external logic The RC32434 responds by immediately tri stating the bottom 16 bits of the memory and peripheral address bus MADDR 15 0 driving the remaining address bus signals i e MADDR 21 16 and asserting RSTN EXTCLK is undefined at this point 2 External logic drives the boot configuration vector on MADDR 15 0 3 External logic negates COLDRSTN and tri states the boot configuration vector on MADDR 15 0 In response the RC32434 stops sampling the boot configuration vector and retains the boot configuration vector value seen two clock cycles earlier i e the value on the MADDR 15 0 ines two rising edges of CLK earlier Within 16 CLK clock cycles after COLDRSTN is sampled negated the RC32434 begins driving MADDR 15 0 he RC32434 waits for the P LL to stabilize he RC32434 then begins generating EXTCLK After at least 4000 CLK clock cycles the RC32434 tri states RSTN Atleast 4000 CLK clock cycles after negating RSTN the RC 32434 samples RSTN If RSTN is negated cold reset has completed and the RC32434 CPU begins executing
11. 300 ns SDA Tsu 12b 5 rising 250 250 250 250 ns Thld 12b 0 345 0 345 0 345 0 345 us Trise_12b 1000 1000 1000 1000 ns Tfall 12b 30 300 300 300 ns Start or repeated start 12c SDA falling 41 41 41 41 us condition Thld 12c 40 40 40 40 us Stop condition Tsu 12d SDA rising 40 40 40 40 us Bus free time between Tdelay 12e 41 47 47 41 us a stop and start condi tion SCL Frequency none 0 400 0 400 0 400 0 400 kHz 400 KHz Thigh_12a 0 6 06 0 6 06 us Tlow_12a Trise 12a 30 300 300 300 ns Tfall 12a 300 300 300 300 ns SDA Tsu 12b SCL rising 100 100 100 100 ns Thld 12b 0 0 9 0 0 9 0 0 9 0 0 9 us Trise 12b 30 300 30 300 ns Tfall 12ba 3001 300 300 300 ns Table 11 Timing Characteristics Part 1 of 2 29 of 53 January 19 2006 IDT RC32434 Reference 266MHz 300MHz 350MHz 400MHz Timing Signal Symbol Edge Unit Conditions Diagram g Min Max Min Max Min Max Min Max Reference Start or repeated start 12 SDA falling 06 0 6 06 06 us 400 KHz See Figure 14 condition Thid_12c 8 los 06 06
12. In satellite mode assertion of this signal initiates a warm reset PCISERR 10 PCI System Error This signal is driven by agent to indicate address ity error data parity error during a special cycle command or any other system error Requires an external pull up PCISTOP 10 PCI Stop Driven the bus target to terminate the current bus transaction For example to indicate a retry PCITRDY 10 PCI Target Ready Driven by the bus target to indicate that the current data complete General Purpose Input Output GPIO 0 1 0 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name 0500 Alternate function UART channel 0 serial output GPIO 1 1 0 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name UOSINP Alternate function UART channel 0 serial input GPIO 2 10 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name UORTSN Alternate function UART channel 0 request to send GPIO 3 1 0 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name UOCTSN Alternate function UART channel 0 clear to send Table 1 Pin Description Part 3 of 6 6 of 53 January 19 2006 IDT RC32434 Signal Type Name Description GPIO 4 1 0 G
13. TXER 0 LVTTL Low Drive MDC 0 LVTTL Low Drive MDIO I O LVTTL Low Drive pull up JTAG TAG_TMS LVTTL ST pull up EJTAG TMS LVTTL ST pull up TAG TRST N LVTTL ST pull up TAG TCK LVTTL ST pull up TAG_TDO 0 LVTTL Low Drive TAG TDI LVTTL ST pull up System CLK LVTTL ST EXTBCV LVTTL ST pull down EXTCLK 0 LVTTL High Drive COLDRSTN LVTTL ST RSTN 10 Low Drive STI pull up pull up on board Table 2 Pin Characteristics Part 2 of 2 1 External pull up required in most system applications Some applications may require additional pull ups not identified in this table 2 Use a 2 2K pull up resistor for 12C pins 11 of 53 January 19 2006 IDT RC32434 Boot Configuration Vector The encoding of the boot configuration vector is described in Table 3 and the vector inputis illustrated in Figure 4 The value of the boot configura tion vector read in by the RC32434 during a cold reset may be determined by reading the Boot Configuration Vector BCV Register Signal Name Description MADDR 3 0 CPU Pipeline Clock Multiplier This field specifies the value by which the PLL multi plies the master clock input CLK to obtain the processor clock frequency P CLK For master clock input frequency constraints refer to Table 3 2 in the RC32434 User Man ual 0x0 PLL Bypass 0x1 Multiply by 3 0x2 Multiply by 4 0x3 Multiply by 5 Reserved 0x4 Multiply by 5 0x5 Multiply
14. 0 2 0 6 0 2 0 6 0 ns PCIRSTN out 10d one 4000 4000 4000 4000 _ ns See Figures 15 CLK and 16 PCIRSTN Tpw 10e one 2 CLK 2 CLK 2 ns vingun 108 PCIRSTN 6 CLK 6 6 CLK e cuo ns falling PCISERRN Tsu 10f rising 3 0 3 0 3 0 3 0 ns See Figure 11 Thid_10f 0 _ 0 _ 0 0 ns Tdo_10f 2 0 6 0 2 0 6 0 2 0 6 0 2 0 6 0 ns PCIMUINTN Tdo 100 PCICLK rising 4 7 11 1 47 111 4 1 11 1 47 11 1 ns Table 10 PCI AC Timing Characteristics This PCI interface conforms to the PCI Local Bus Specification Rev 2 2 must be equal to or less than two times PCICLK lt 2 ICLK with a maximum PCICLK of 66 MHz The values for this symbol were determined by calculation not by testing PCIRSTN is an output in host mode and an input in satellite mode meet the PCI delay specification from reset asserted to outputs floating the P CI reset should be logically combined with the COLDRSTN input instead of input on PCIRSTN PCISERRN and PCIMUINTN use open collector 1 0 types m m n 27 of 53 January 19 2006 IDT RC32434 Thigh_10a Tlow_10a 104 lt PCICLK N j 10b y Tzd_10b Bussed output gt 10c Point to point output X lt gt Thld_10b 100 gt lt Bussed inp
15. 0 E16 DDRDATA 5 0 E14 DDRDATA 6 0 E13 DDRDATA 7 10 16 DDRDATA 8 10 F14 DDRDATA 9 10 F13 DDRDATA 10 0 G15 DDRDATA 11 0 616 DDRDATA 12 0 H15 DDRDATA 13 0 H16 DDRDATA 14 0 H14 Table 24 RC32434 Alphabetical Signal List Part 2 of 7 45 of 53 January 19 2006 IDT RC32434 Signal Name Type Location Signal Category DDRDATA 15 1 0 H13 DDR Bus DDRDM 0 0 F15 DDRDM I 0 613 00800510 0 116 DDRDQS 1 0 G14 DDRRASN 0 M13 DDRVREF DDRWEN 0 L14 EJTAG_TMS 4 JTAG EJTAG EXTBCV 011 System EXTCLK 0 GPIO 0 10 H3 General Purpose Input Output GPIO 1 10 H4 GPIO 2 0 13 GPIO 3 10 Jl GPIO 4 10 8 GPIO 5 10 B8 GPIO 6 10 C7 GPIO 7 10 Al GPIO 8 10 L3 GPIO 9 10 4 GPIO 10 10 P3 GPIO 11 10 3 GPIO 12 10 1 GPIO 13 10 T2 TAG_TCK J2 JTAG EJTAG TAG TDI A12 TAG TDO 0 K1 TAG_TMS C11 TAG_TRSTN D12 Table 24 RC32434 Alphabetical Signal List Part 3 of 7 46 of 53 January 19 2006 IDT RC32434 Signal Name I O Type Location Signal Category ADDR 0 0 15 Memory and Peripheral Bus ADDR 1 0 B16 ADDR 2 0 A16 ADDR 3 0 B15 ADDR 4 0 C14 ADDR 5 0 15 ADDR 6 0 14 ADDR 7 0 A14 ADDR 8 0 B13 ADDR 9 0 A13 A
16. 10 300 10 300 ns Ethernet MII Mode MISC Tper_9c None 399 96 400 4 399 96 400 4 399 96 400 4 399 96 400 4 ns 10 Mbps See Figure 10 140 260 140 260 140 260 140 260 ns Tlow_9c Trise 9c 3 0 3 0 3 0 3 0 ns Tfall 9c MIRXCIG Tper_9d None 39 9 40 0 39 9 40 0 39 9 40 0 39 9 40 0 ns 100 Mbps Thigh 9d 14 0 26 0 14 0 26 0 14 0 26 0 14 0 26 0 ns Tlow 9d Trise 9d 2 0 2 0 2 0 2 0 ns Tfall_9d MIIRXD 3 0 Tsu 9e MIIXRXCLK 10 0 10 0 10 0 10 0 5 coed Thid_9 sig 10 0 10 0 10 0 10 0 MIIRXER 76 x 5 x E 1 MIITXD 3 0 Tdo_9f MIIXTXCLK 0 0 25 0 0 0 25 0 0 0 25 0 0 0 25 0 ns MIITXENP rising MIITXER Ethernet RMII Mode RMIIREFCLK 9i None 19 9 20 1 19 9 20 1 19 9 20 1 19 9 20 1 ns See Figure 10 Thigh 9i 7 0 13 0 1 0 13 0 1 0 13 0 1 0 13 0 ns Tlow 9i RMIITXEN Tdo 9j MIIRXCLK 2 0 2 0 2 0 2 0 ns RMIITXD 1 0 rising RMIICRSDV Tsu_9k 5 5 145 5 5 14 5 5 5 145 5 5 145 ns RMIIRXER RMIIRXD 1 0 Table 9 Ethernet AC Timing Characteristics 25 of 53 January 19 2006 IDT RC32434 Thigh_9a Tlow_9a 9a MIIMDC UE ob gt 9b MIIMDIO output X X gt leThld 9b Tsu 9b MIIMDIO input X X Thigh_9d Tlow_9d Tper_9d j MIIRXCLK gh N N N gt Thld_9e Tsu_9e lt MIIRXDV MIIRXD 3 0 MIIRXER X X X X X Thigh_9d Tlow_9d Tper_9d I
17. GPIO 9 1 4 PCIAD 19 D5 DATA 7 5 V CORE 5 Vec 1 0 T5 PCIAD 16 D6 DATA 2 V CORE 6 0 T6 PCICLK D7 DATA 0 H7 Va T V _ 0 T7 PCIGNTN 0 D8 ADDR 20 H8 Veg 8 Vee CORE 8 PCIDEVSELN D9 ADDR 19 9 Va 9 Vec CORE T9 PCIPAR D10 MADDR 15 10 Vo 10 Vec 1 0 T10 13 11 EXTBCV 11 Veo 11 V DDR T11 PCIAD 9 D12 JTAG_TRST Vec CORE 12 V DDR T12 PCIADI6 D13 WAITACKN H13 DDRDATA 15 13 DDRRASN T13 PCIAD 2 D14 DDRDATA 2 14 DDRDATA 14 14 DDRBAT I PCIAD 1 D15 DDRDATA 3 H15 DDRDATA 12 15 DDRADDR 6 T15 PCIGNTN 1 D16 DDRDATA H16 DDRDATA 13 16 DDRADDR 7 T16 PCIGNTN 3 Table 20 RC32434 Pinout Part 2 of 2 42 of 53 January 19 2006 IDT RC32434 RC32434 Alternate Signal Functions Pin GPIO Alternate Pin GPIO Alternate AT GPIO 7 MADDR 25 3 GPIO 2 UORTS A8 GPIO 4 MADDR 22 L3 GPIO 8 CPU B8 GPIO 5 MADDR 23 1 GPIO 12 PCIGNTN 5 C7 GPIO 6 MADDR 24 3 GPIO 11 PCIREQN 5 H3 GPIO O 00500 4 GPIO 9 PCIREQNIA H4 GPIO 1 UOSINP GPIO 10 PCIGNTN 4 Ji GPIOB UOCTSN T2 GPIO 13 PCIMUINTN Table 21 RC32434 Alternate Signal Functions RC32434 Power Pins Vec 1 0 DDR Vec Core Vec PLL Vec 5 11 8 11 C12 E6 E12 E9 F12 F9 E10 G12 H5 F5 K12 H6 G5 L12 H12 K5 M11 J5 K6 M12 1
18. Hz Tper_5a 8 0 40 0 8 0 40 0 8 0 40 0 8 0 40 0 ns Thigh_5a 40 60 40 60 40 60 40 60 of Tlow_5a 5 Trise_5a 3 0 3 0 3 0 3 0 ns Tfall 5a Tjiter 5a 0 1 0 1 0 1 0 1 ns Table 5 Clock Parameters 1 The CPU pipeline clock P CLK speed is selected during cold reset by the boot configuration vector see Table 3 Refer to Chapter 3 Clocking and Initialization in the RC32434 User Reference Manual for the allowable frequency ranges of CLK and PCLK 2 CLK is the internal IP Bus clock Itis always equal to PCLK divided by 2 This clock cannot be sampled externally 3 The ethernet clock MIIXR XCLK and MIIXTXCLK frequency must be equal to or less than 1 2 MIIXRXCLK and lt 1 2 ICLK PCICLK must be equal to or less than two times PCICLK lt 2 ICLK with a maximum P CICLK of 66 MHz gt The input clock CLK is input from the external oscillator to the internal PLL Tlow 5a Thigh lt gt 5 y N h y N 2 Y gt S Tjitter 5a 5a Trise 5a Tfall 5a Figure 3 Clock Parameters Waveform 16 of 53 January 19 2006 IDT RC32434 AC Timing Characteristics Values given below are based on systems running at recommended operating temperatures and supply voltages shown in Tables 15 and 16
19. MHz Pipeline Clk 350 MHz Pipeline Clk 400 MHz Pipeline Clk Integrated Core Processor 1 2V 0 1V Core Voltage 32 bit Embedded Microprocessor for Tech Support email rischelp idt com phone 408 284 8208 January 19 2006
20. Min Unit Vecl 0 1 0 supply except for SSTL_22 0 6 4 0 V V cSI O DDR 1 0 supply forSSTL 22 0 6 4 0 V VccCore Core Supply Voltage 0 6 2 0 V VecPLL PLL supply digital 0 6 2 0 V VecAPLL PLL supply analog 0 6 4 0 V Vinl O 1 0 Input Voltage except for SSTL 2 0 6 Vecl 0 0 5 V VinS1 0 1 0 Input Voltage for SSTL 2 0 6 51 0 0 5 Ambient Operating Temperature 40 85 C Industrial Ta Ambient Operating Temperature 0 70 G Commercial T Storage Temperature 40 125 C Table 19 Absolute Maximum Ratings 1 Functional and tested operating conditions are given in Table 15 Absolute maximum ratings are stress ratings only and func tional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause perma nent damage to the device 2 SSTL 2 1105 are used to connect to DDR SDRAM 40 of 53 January 19 2006 Package Pin out 256 BGA Signal Pinout for the RC32434 The following table lists the pin numbers signal names and number of alternate functions for the RC32434 device Signal names ending with an nor active when low Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt 1 RWN El MIIR XD 3 1 GPIO 3 1 1 PCIAD 29 A
21. SP See Figures r eo ras on SDO Tdo 15c SCK rising or 0 60 0 60 0 60 0 60 ns SP falling SCK SDI Tpw 15e None 2 2 ICLK _ 2 ICLK 2 ICLK ns Bit 1 0 SDO Table 13 SPI AC Timing Characteristics 1 In SPI mode the SCK period and sampling edge are programmable In P CI mode the SCK period is fixed and the sampling edge is rising Thigh_15a _ 15 5 N N 2 N Thld_15b Tsu_15b gt SDI X MSB X bt6 X bis X bit4 X bit3 X 2 X btl X LSB X gt Tdo_15c SDO X MSB X 6 X bits X bit X bit3 X bit2 X btl X LSB X Control bits 0 0 in the SPI Control Register SPC Figure 16 SPI Timing Waveform Clock Polarity 0 Clock Phase 0 Thigh 15a 15 woe SCK Thld 15b Tsu 15b SDI X MSB X bit X bit5 X bt3 X bt2 X Tdo_15c 5 0 X MSB X bit X bits X bit4 X bt3 X bit2 X btl X LSB X Control bits CPOL 20 CPHA 1 in the SPI Control Register SPC Figure 17 SPI Timing Waveform Clock Polarity 0 Clock Phase 1 31 of 53 January 19 2006 IDT RC32434 V V A SCK SDI SDO input 4 15 Figure 18 SPI AC Timing Waveform Bit 1 0 Mode
22. SSTL_2 DDRDM 1 0 0 SSTL 2 DDRDQS 1 0 1 0 SSTL 2 DDRRASN 0 SSTL_2 DDRVREF Analog DDRWEN 0 SSTL_2 PCT Bus Interface PCIAD 31 0 10 PCICBEN 3 0 10 PCIDEVSELN 10 pull up on board PCIFRAMEN 10 pull up board PCIGNTN 3 0 10 pull up on board PCIIRDY 10 pull up board PCILOCK 10 PCIPAR 10 PCIPERR 10 PCIREQN 3 0 10 pull up on board PCIRSTN 10 pull down on board PCISERR 10 Open Collector pull up on board PCISTOP 10 pull up board PCITRDY 10 pull up board General Purpose I 0 GPTO 8 0 10 LVTTL High Drive pull up GPIO 13 9 10 pull up board Serial Peripheral SCK LVTTL High Drive pull up pull up on board Interface SD 10 LVTTL High Drive pull up pull up on board 5 0 10 LVTTL High Drive pull up pull up on board 2C Bus Interface SCL 10 LVTTL Low Drive STI pull up on board SDA 10 LVTTL Low Drive STI pull up on board2 Table 2 Pin Characteristics Part 1 of 2 10 of 53 January 19 2006 IDT RC32434 Internal Function Pin Type Buffer 1 0 Type Resistor Notes Ethernet Interfaces MIICL LVTTL ST pull down CRS LVTTL ST pull down RXCLK LVTTL ST pull up RXD 3 0 LVTTL ST pull up RXDV LVTTL ST pull down RXER LVTTL ST pull down TXCLK LVTTL ST pull up TXD 3 0 0 LVTTL Low Drive TXENP 0 LVTTL Low Drive
23. WR WR NOP NOP NOP NOP NOP DDRCKE i i i i Tdo 7m DDRBA 1 0 ok up BNKx _ G b QD QN DDRDQSx 579 71 o T l DDRDMIL 0 FF ineo cp FF DDRDQSx i i i i t 76 7 i DDRDATAL 15 0P I DO X D1X 022 D3 1 DDRCMD contains DDRRASN DDRCASN and DDRWEN 2 DDRDATA is either 32 bits or 16 bits wide depending the DBW control bit in DDRC Register see Chapter 7 DDR Controller in the RC32434 User Reference Manual Figure 7 DDR SDRAM Timing Waveform Write Access 266MHz 300MHz 350MHz 400MHz Timing Reference Condi Signal Symbol Edge Unit tions Diagram Min Max Min Max Min Max Min Max Reference Memory and Peripheral Bus See Figures 8 MADDRQLO Tdo EXTCLK rising 04 45 04 45 04 45 04 45 ns 09 8 _ _ _ _ _ _ _ _ ns Tzd 8 5 MADDR 25 22 Tdo 8b rising 0 4 45 0 4 45 0 4 45 0 4 45 ns Tdz 80 5 Tzd_8b2 5 Table 8 Memory and Peripheral Bus Timing Charac
24. and the Min and Max values for Thigh Tlow 9d were changed to 14 0 and 26 0 respectively December 8 2005 In Table 18 corrected error for Capacitance Max value from 8 0 to 10 5 January 19 2006 Removed all references to NVRAM 3 of 53 January 19 2006 IDT RC32434 Pin Description Table The following table lists the functions of the pins provided on the RC32434 Some of the functions listed may be multiplexed onto the same pin The active polarity of a signal is defined using a suffix Signals ending with an N are defined as being active or asserted when at a logic zero low level All other signals including clocks buses and select lines will be interpreted as being active or asserted when ata logic one high level Signal Type Name Description Memory and Peripheral Bus BDIRN 0 Extemal Buffer Direction Controls the direction of the external data bus buffer for the memory and peripheral bus If the RC32434 memory and peripheral bus is connected to the A side of a transceiver such as an IDT74F CT245 then this pin may be directly connected to the direction control 0 BDIR pin of the transceiver BOEN Extemal Buffer Enable This signal provides an output enable control for an external buffer on the memory and peripheral data bus WEN Write Enables This signal is the memory and peripheral bus write enable sig nal CSN 3 0 Chip Selects These signals are use
25. valid output takes to become tri stated Tsu Input set up Amount of time before the reference clock edge that the input must be valid Thid Input hold Amount of time after the reference clock edge that the input must remain valid Tpw Pulse width Amount of time the input or output is active for asynchronous signals Tslew Slew rate The rise or fall rate for a signal to go from a high to low or low to high X clock Timing value This notation represents a value of X multiplied by the clock time period of the specified clock Using 5 CLK as an example X 5 and the oscillator clock CLK 25MHz then the timing value is 200 Tskew Skew The amount of time two signal edges deviate from one another Table 4 AC Timing Definitions 15 of 53 January 19 2006 IDT RC32434 System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures as shown in Tables 15 and 16 266MHz 300MHz 350MHz 400MHz Timing Parameter Symbol Reference Units Diagram Edge Min Max Min Max Min Max Min Max Reference PCLK Frequency none 200 266 200 300 200 350 200 400 Hz See Figure 3 Tper 3 8 5 0 3 3 5 0 2 85 5 0 2 5 5 0 ns ICLK23 4 Frequency none 100 133 100 150 100 175 100 200 Hz Tper 1 5 10 0 6 7 10 0 5 7 10 0 5 0 10 0 ns Frequency none 25 125 25 125 25 125 25 125
26. 1 L5 12 M5 L8 M6 8 M7 9 M10 Table 22 RC32434 Power Pins 43 of 53 January 19 2006 IDT RC32434 RC32434 Ground Pins Vss Vss Vss PLL F6 J6 11 12 F7 7 F8 J8 F10 J9 F11 10 66 K7 G7 K8 G8 K9 G9 K10 G10 K11 G11 L6 H7 L7 H8 19 H9 L10 H10 L11 H11 Table 23 RC32434 Ground Pins RC32434 Signals Listed Alphabetically The following table lists the RC32434 pins in alphabetical order Signal Name I O Type Location Signal Category BDIRN 0 C2 Memory and Peripheral Bus BOEN 0 Bl CLK System COLDRSTN C3 CSN 0 0 A4 Memory and Peripheral Bus CSN 1 0 B4 CSN 2 0 A3 CSN 3 0 B3 Table 24 RC32434 Alphabetical Signal List Part 1 of 7 44 of 53 January 19 2006 IDT RC32434 Signal Name I O Type Location Signal Category DDRADDR 0 0 P14 DDR Bus DDRADDR 1 0 R16 DDRADDR 2 0 P15 DDRADDR 3 0 15 DDRADDR 4 0 14 DDRADDR 5 0 13 DDRADDR 6 0 15 DDRADDR 7 0 16 DDRADDR 8 0 L16 DDRADDR 9 0 L13 DDRADDR 10 0 K15 DDRADDR I11 0 K14 DDRADDR 12 0 K16 DDRADDR 13 0 E15 DDRBA 0 0 16 DDRBA I 0 M14 DDRCASN 0 L15 DDRCKE 0 K13 DDRCKN 0 13 DDRCKP 0 15 DDRCSN 0 P16 DDRDATA 0 0 C16 DDRDATA 1 0 D16 DDRDATA 2 0 014 DDRDATA 3 0 D15 DDRDATA 4
27. 2 OE E2 MIIR XD 2 2 JTAG TCK 2 PCIAD 28 CSN 2 MIITXD 0 3 GPIO 2 1 3 PCIAD 30 A4 CSN 0 E4 MIITXD 1 4 EJTAG TMS 4 PCIAD 18 A5 MADDR 10 E5 10 5 Ve CORE 5 PCIREQN I A6 MDATAI6 E6 V c 1 0 6 V 6 PCIREQN 2 AT GPIO 7 1 Vec 1 0 1 Ves 1 PCIIRDY A8 GPIOH 1 E8 Voc CORE 8 Vg 8 PCILOCK 9 ADDR 16 E9 Vec CORE 9 Ves 9 PCIPERR A10 ADDR 13 E10 V I 0 10 Ve 10 PCIAD 15 11 Veg PLL Ell V DDR 11 Ve CORE 11 PCIAD 11 A12 JTAG_TDI E12 Vc DDR 12 Ve CORE 12 PCICBEN 0 A13 ADDR 9 E13 DDRDATA 6 13 DDRCKN 13 DDRADDR 5 14 ADDR 7 DDRDATA 5 14 DDRVREF 14 DDRADDR 4 Al5 ADDR 5 E15 DDRADDR 13 15 DDRCKP 15 DDRADDR 3 A16 ADDR 2 E16 DDRDATA 4 16 DDRDQS 0 16 DDRBA 0 1 BOE F1 ITXD 2 K1 TG_TDO 1 PCIAD 27 B2 RSTN F2 IRXCLK K2 SCK P2 PCIAD 26 CSN 3 F3 ITXD 3 K3 Reserved P3 GPIO 10 1 B4 CSN 1 F4 ITXENP K4 500 4 PCIAD 20 B5 ADDR 11 F5 Vecl 0 K5 Vec 1 0 P5 B6 DATA I F6 Veg K6 Vall P6 PCIREQN 0 7 DATAM F7 V amp Veg P7 B8 GPIOD 1 F8 KO Ves P8 B9 ADDR 17 F9 Ve CORE K9 Ves P9 PCISERRN B10 MADDR 12 F10 Veg KO Veg P10 PCIAD 14 B11 V PLL FIL V amp K11 Vs P11 PCIAD 10 B12 Veg APLL F12 V DDR K12 V DDR P12 PCIADI7 B13 MADDR 8 F13 DDRDATA 9 K13 DDRCKE PCIAD 4 B14 MADDR 6 14 DDRDATA 8 K14__ DDRADDR 11 P14 DDRADDR 0
28. 5ns for Tps The DDR data sheet specs a value of 0 5ns for 266MHz so this leaves 1 35ns slack for board propagation delays 19 of 53 January 19 2006 DDRCKP DDRCKN DDRCSN DDRADDR 13 0 DDRCMD DDRCKE DDRBA 1 0 DDRDM 1 0 DDRDQSx ideal DDRDATA 15 0 ideal DDRDQSx min DDRDATA 15 07 DDRDQSx max DDRDATA 15 0 7m Tac max gt Col AO Col A2 Tdo 7m 1 N 1 1 N 1 1 1 1 N lt RD RD lt XPRECH ACTV X NOP Tdo 7m i gt BNKx BNKx T T T 1 i 1 T 1 D0XD1 lt XD2XD3 Tac min i MP i Lot 1 1 i gt lt Tskew_ 7g 1 DDRCMD contains DDRRASN DDRCASN and DDRWEN 2 DDRDATA is either 32 bits or 16 bits wide depending on the DBW control bitin DDRC Register see Chapter 7 DDR Controller inthe RC32434 User Reference Manual gt lt Tskew_ 7g L DOXDIXD2 D3 20 of 53 January 19 2006 Figure 6 DDR SDRAM AC Timing Waveform SDRAM Read Access IDT RC32434 DDRCKP DDRCKN Tdo_7m DDRCSN 7m DDRADDR 13 0 Row gt Colao ColA2 a Tdo 7m DDRCMD NOP ACTV gt X NOP
29. DDR 10 0 A5 ADDR 11 0 B5 ADDR 12 0 B10 ADDR 13 0 A10 ADDR 14 0 C10 ADDR 15 0 D10 ADDR 16 0 A9 ADDR 17 0 B9 ADDR 18 0 C9 ADDR 19 0 D9 ADDR 20 0 D8 ADDR 21 0 C8 DATA 0 10 07 DATA 1 0 B6 10 06 DATA 3 10 C5 0 B7 DATA 5 10 6 DATA 6 0 6 DATA 7 10 D5 Table 24 RC32434 Alphabetical Signal List Part 4 of 7 47 of 53 January 19 2006 IDT RC32434 Signal Name I O Type Location Signal Category CL D2 Ethernet Interface CRS D3 MDC 0 H2 MDIO I O H1 RXCLK F2 RXD 0 D1 RXD 1 D4 RXD 2 E2 RXD 3 El RXDV Gl RXER G3 TXCLK G4 TXD 0 0 E3 TXD 1 0 E4 TXD 2 0 F1 TXD 3 0 F3 TXENP 0 FA TXER 0 62 0 0 2 Memory Bus PCIAD 0 0 R14 PCI Bus Interface PCIAD 1 0 14 PCIAD 2 0 T13 PCIAD 3 0 R13 PCIAD A 0 P13 PCIAD 5 0 R12 PCIAD 6 0 T12 PCIAD 7 0 P12 8 0 11 PCIAD 9 0 T11 PCIAD 10 0 P11 PCIAD 11 IO N11 PCIAD 12 0 R10 PCIAD 13 10 10 PCIAD 14 0 P10 PCIAD 15 0 N10 PCIAD 16 0 5 Table 24 RC32434 Alphabetical Signal List Part 5 of 7 48 of 53 January 19 2006 IDT RC32434 Signal Name Ty
30. HAMFER METALLIZED OR INK MARK INDENTATION OR OTHER FEATURE OF THE PACKAGE BODY UNLESS OTHERWISE SPECIFIED i DIMENSIONS ARE IN MELIMETERS Integroted Device Technology Inc ALL DIMENSIONS ARE IN MILLIMETERS Foard tuit 2975 Stender Way Santa Clara 95054 XX 4010 i QU Soo Ray THIS DRAWING CONFORMS TO PUBLICATION 95 REGISTRATION MO 192 Xni 400 408 727 6116 FAX 408 492 8074 VARIATION AAF 1 EXCEPTIONS b 0 41 0 46 0 51 DAW 3 BC256 PACKAGE OUTLINE 96 09 00 17 0 X 17 0 mm BODY CABGA DRAWING No SUE SCALE 5 4093 C DO SCALE DRAWING SHEET 2 CHECKED 52 of 53 IDT RC32434 Ordering Information T9RCXX YY XXXX 999 A A Product 0perating Device Speed Package Temp range Type Voltage Type Process Blank BC 266 300 350 400 434 H T9RC32 Valid Combinations 79RC32H434 266BC 300 350BC 400BC 256 pin CABGA package Commercial Temperature 79R C32H 434 266BCI 300BCI 350BCI 256 pin CABGA package Industrial Temperature CORPORATE HEADQUARTERS for SALES 1 DT 6024 Silver Creek Valley Road 800 345 7015 or 408 284 8200 San ose CA 95138 fax 408 284 2775 www idt com 53 of 53 Commercial Temperature 0 C to 70 C Ambient Industrial Temperature 40 C to 85 C Ambient 256 pin CABGA 266 MHz Pipeline Clk 300
31. IDT Interprise Integrated RC32434 Communications Processor interprise Device Overview The RC32434 is a member of the IDT Interprise family of PCI integrated communications processors It incorporates a high perfor mance CPU core and a number of on chip peripherals The integrated processor is designed to transfer information from 1 0 modules to main memory with minimal CPU intervention using a highly sophisticated direct memory access DMA engine All data transfers through the RC32434 are achieved by writing data from an on chip 1 0 peripheral to main memory and then out to another I O module Features 32 bit CPU Core MIPS32 instruction set Cache Sizes 8KB instruction and data caches 4 Way set associative cache line locking non blocking prefetches 16 dual entry J TLB with variable page sizes Sentry instruction TLB 3 entry data TLB Max issue rate of one 32x16 multiply per clock issue rate of one 32x32 multiply every other clock CPU control with start stop and single stepping Software breakpoints support Hardware breakpoints on virtual addresses ICE Interface that is compatible with v2 5 of the EJ TAG Spec ification Block Diagram PCI Interface 32 bit PCI revision 2 2 compliant Supports host or satellite operation in both master and target modes Support for synchronous and asynchronous operation PCI clock supports frequencies from 16 MHz to 66 MHz PCI arbiter i
32. N Figure 8 Memory and Peripheral Bus AC Timing Waveform Read Access 23 of 53 January 19 2006 IDT RC32434 NX N N NN N Tdo_8a MADOR 21 0 W w lt Addr 21 0 _ 8b MADDRD522 a www Addr 25 22 C Tdo_8j RWN H 8 CSNI3 0 1do 8I WEN 1111 gt Byte Enables X 1111 OEN gt 8c 7 0 au Data BDIRN Tdo_8f BOEN 2 N WAITACKN Figure 9 Memory and Peripheral Bus AC Timing Waveform Write Access 24 of 53 January 19 2006 IDT RC32434 values for this symbol were determined by calculation not by testing ethemet clock MIIRXCLK and MIITXCLK frequency must be equal to or less than 1 2 MIIRXCLK and lt 1 2 ICLK Reference 266MHz 300MHz 350MHz 400MHz Condi Timing Signal Symbol Ed e Unit tins Diagram g Min Max Min Max Min Max Min Max Reference Ethernet MIIMDC Tper_9a None 30 0 30 0 30 0 30 0 ns See Figure 10 Thigh_9a 12 0 12 0 12 0 B 12 0 ns Tlow_9a MIIMDIO Tsu_9b MIIMDC rising 10 0 10 0 10 0 10 0 ns Thld 9b 0 0 0 0 0 0 0 0 ns Tdo_9b 10 300 10 300
33. TDI a OND 2 TD GND GND eee EJTAG TMS lt lt TMS u z OND JTAG lt TCK iai pg OND rst DINT Reset soft hard i i veco voltage reference Other reset T Tm ane sources arget System gt Reset Circuit lt Figure 20 Target System Electrical EJ TAG Connection 33 of 53 January 19 2006 IDT RC32434 Using the EJ TAG Probe In Figure 20 the pull up resistors for TAG_TDO RST the pull down resistor for and the series resistor for TAG_TDO must be adjusted to the specific design However the recommended pull up down resistor is 1 0 because a low value reduces crosstalk on the cable to the connector allowing higher TAG_TCK frequencies A typical value for the series resistor is 33 Recommended resistor values have 5 toler ance If a probe is used the pull up resistor on J TAG_TDO must ensure that the J TAG TDO level is high when no probe is connected and the JTAG output is tri stated This requirement allows reliable connection of the probe if itis hooked up when the power is already on hot plug The pull up resistor value of around 47 should be sufficient Optional diodes to protect against overshoot and undershoot voltage can be added on the Signals of the chip with EJ TAG If a probe is used the RST signal must have a pull up resistor because it is controlled by an open collector OC driver in the probe and thus is activ
34. TE THICKNESS 10 02 02 Ai BALL PAD CORNER o o OO OOO QO OjO NOTES UNLESS OTHERWISE SPECIFIED ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME 14 5 1994 REPRESENTS THE BASIC SOLDER BALL GRID PITCH MD IS THE MAXIMUM SOLDER BALL MATRIX SIZE IN THE D DIRECTION ME IS THE MAXIMUM SOLDER BALL MATRIX SIZE IN THE E DIRECTION N IS THE MAXIMUM ALLOWABLE NUMBER OF SOLDER BALLS DIMENSION b IS MEASURED THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM Z PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY BOTTOM VIEW THE WNS SOLD HE SPHERICAL CROWNS OF THE SOLDER BALLS 256 SOLDER BALLS 1 ID CORNER MUST BE IDENTIFIED IDENTIFICATION MAY BE BY MEANS OF C
35. WAITACKN 013 Memory and Peripheral Bus WEN 0 C4 Reserved K3 L1 L2 Table 24 RC32434 Alphabetical Signal List Part 7 of 7 50 of 53 January 19 2006 IDT RC32434 RC32434 Package Drawing 256 pin CABGA REVISIONS DESCRIPTION DATE APPROVED INITIAL RELEASE 06 09 00 D G JEDEC VARIATION MODIFICATION 07 11 00 0 6 UPDATE THICKNESS 10 02 02 VARIATION 1 1 BALL PAD CORNER MIN NOM MAX 130 140 170 31 36 A1 65 70 75 7 00 BSC 15 00 BSC e 17 00 85 15 00 BSC T Pobbw 2 D ala m me a i 6 N SEATING PLANE i SIDE VIEW as Integrated Device Technology Inc 2975 Stender Way Santa Clara CA 95054 XX 4010 dt Xxx 40 05 408 727 6116 FAX 408 492 8074 APPROVALS DATE P BC256 PACKAGE OUTLINE DRAW 09 00 am 8 ovo 170 X 17 0 mm BODY CHECKED DRAWING No SIZE SCALE REV PSC 4093 C 02 DO NOT SCALE DRAWING SHEET 1 OF 2 IDT RC32434 RC32434 Package Drawing Page Two REVISIONS DESCRIPTION DATE APPROVED INITIAL_ RELEASE 06 09 00 JEDEC VARIATION MODIFICATION 07 11 00 UPDA
36. by 6 Reserved 0x6 Multiply by 6 0x7 Multiply by 8 0x8 Multiply by 10 0 9 through OxF Reserved MADDR 5 4 External Clock Divider This field specifies the value by which the IPBus clock which is always 1 2 P CLK is divided in order to generate the external clock outputon the EXTCLK pin 0x0 Divide by 1 0x1 Divide by 2 0x2 Divide by 4 0x3 reserved MADDR 6 Endian This bit specifies the endianness 0x0 little endian 0x1 big endian MADDR 7 Reset Mode This bit specifies the length of time the RSTN signal is driven 0x0 Normal reset RSTN driven for minimum of 4000 clock cycles If the internal boot configuration vector is selected the expiration of an 18 bit counter operating at the master clock input CLK frequency is used as the PLL stabilization delay 0 1 Reserved MADDR 10 8 PCI Mode This bit controls the operating mode of the PCI bus interface The initial value ofthe EN bit in the P CIC register is determined by the PCI mode 0x0 Disabled EN initial value is zero 0x1 PCI satellite mode with PCI target not ready EN initial value is one 0 2 PCI satellite mode with suspended CPU execution EN initial value is one 0x3 PCI host mode with external arbiter EN initial value is zero 0x4 PCI host mode with internal arbiter using fixed priority arbitration algorithm EN initial value is zero 0x5 PCI host mode with internal arbiter using round robin arbitration algo
37. by taking MIPS reset exception S49 QUY Ge Figure 4 COLD Reset Operation with External Boot Configuration Vector AC Timing Waveform Note For a diagram showing the COLD Reset Operation with Internal Boot Configuration Vector see Figure 3 6 in the RC32434 User Reference Manual 18 of 53 January 19 2006 IDT RC32434 o innnnn nuni COLDRSTN RSTN UN DET MDATAU O __ FFFF_FFFF x Mem Control Signals Active x Deasserted X Active Kae clock Cycles clock Cycles 1 Warm reset condition caused by assertion of RSTN by an external agent 2 RC32434 tri states the data bus MDATA T 0 negates all memory control signals and itself asserts RSTN The RC32434 continues to drive the address bus throughout the entire warm reset 3 RC32434 negates RSTN after 4000 master clock CLK clock cycles 4 External logic negates RSTN 5 The RC32434 samples RSTN negated at least 4000 master clock CLK clock cycles after step 3 and starts driving the data bus MDATA 7 0 6 CPU begins executing by taking a MIPS soft reset exception The assertion of CSN 0 will occur no sooner than 16 clock cycles after the RC32434 samples RSTN negated i e step 5 Figure 5 Externally Initiated Warm Reset AC Timing Waveform
38. d to select an external device on the mem ory and peripheral bus MADDR 21 0 Address Bus 22 bit memory and peripheral bus address bus MADDR 25 22 are available as GPIO alternate functions MDATAI7 0 Data Bus 8 bit memory and peripheral data bus During a cold reset these pins function as inputs that are used to load the boot configuration vector OEN Output Enable This signal is asserted when data should be driven by an exter nal device on the memory and peripheral bus RWN Read Write This signal indicates whether the transaction on the memory and peripheral bus is a read transaction or a write transaction A high level indicates a read from an external device A low level indicates a write to an external device WAITACKN Wait or Transfer Acknowledge When configured as wait this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle When configured as a transfer acknowledge this signal is asserted during a transaction to signal the completion of the transaction DDR Bus DDRADDR 13 0 DDR Address Bus 14 bit multiplexed DDR address bus This bus is used to transfer the addresses to the DDR devices DDRBA 1 0 DDR Bank Address These signals are used to transfer the bank address to the DDRs DDRCASN DDR Column Address Strobe This signal is asserted during DDR transac tions DDRCKE DDR Clock Enable The DDR clock enable si
39. ect differential clocking outputs and data strobes Memory and I O Controller RC32434 uses a dedicated local memory lO controller including a de multiplexed 8 bit data and 26 bit address bus It includes all of the signals required to interface directly to a maximum of four Intel or Motorola style external peripherals 2 of 53 January 19 2006 IDT RC32434 DMA Controller The DMA controller consists of 6 independent DMA channels all of which operate in exactly the same manner The DMA controller off loads the CPU core from moving data among the on chip interfaces external peripherals and memory The controller supports scatter gather DMA with no alignment restrictions making it appropriate for communications and graphics systems UART Interface The RC32434 contains a serial channel UART that is compatible with the industry standard 16550 UART I C Interface The standard 12 interface allows the RC32434 to connect to a number of standard external peripherals for a more complete system solution The RC32434 supports both master and slave operations General Purpose 1 0 Controller The RC32434 has 14 general purpose input output pins Each pin may be used as an active high or active low level interrupt or non maskable interrupt input and each signal may be used as a bit input or output port System Integrity Functions The RC32434 contains a programmable watchdog timer that gener ates a non maskable interrup
40. ely pulled low only The pull up resistor is responsible for the high value when not driven by the probe of 25pF The input on the target system reset circuit must be able to accept the rise time when the pull up resistor charges the capacitance to a high logical level Vcc 1 0 must connect to a voltage reference that drops rapidly to below 0 5V when the target system loses power even with a capacitive load of 25pF The probe can thus detect the lost power condition For additional information on EJ TAG refer to Chapter 17 of the RC32434 User Reference Manual Phase Locked Loop PLL The phase locked loop PLL multiplies the external oscillator input pin CLK according to the parameter provided by the boot configuration vector to create the processor clock PCLK Inherently PLL circuits are only capable of generating clock frequencies within a limited range PLL Filters It is recommended that the system designer provide a filter network of passive components for the PLL analog and digital power supplies The PLL circuit power and PLL circuit ground should be isolated from power and ground with a filter circuit such as the one shown in Figure 21 Because the optimum values for the filter components depend upon the application and the system noise environment these values should be considered as starting points for further experimentation within your specific application RC32434 10 ohm Vec M 4 VecPLL V P LL l0ogF
41. eneral Purpose I 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name MADDR 22 Alternate function Memory and peripheral bus address GPIO 5 1 0 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name MADDR 23 Alternate function Memory and peripheral bus address GPIO 6 0 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name MADDR 24 Alternate function Memory and peripheral bus address The value of this pin may be used as a counter timer clock input see Counter Timer Clock Select Register in Chapter 14 Counter Timers of the RC32434 User Manual GPIO 7 I O General Purpose 1 0 This can be configured as general purpose 1 0 pin Alternate function pin name MADDR 25 Alternate function Memory and peripheral bus address The value of this pin may be used as a counter timer clock input see Counter Timer Clock Select Register in Chapter 14 Counter Timers of the RC32434 User Manual GPIO 8 10 General Purpose 1 0 This be configured as a general purpose 1 0 pin Alternate function pin name CPU Alternate function CPU or DMA debug output pin GPIO 9 1 0 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name PCIREQN 4 Alternate function P CI Request 4 GPIO 10 1 0 General Purpose 1 0 This
42. ernet MII Transmit Coding Error When this signal is asserted together with MIITXENP the ethernet PHY will transmit symbols which are not valid data or delimiters MIIMDC 0 MII Management Data Clock This signal is used as a timing reference for transmission of data on the management interface MIIMDIO JO MII Management Data This bidirectional signal is used to transfer data between the station management entity and the ethernet PHY EJ TAG TAG JTAG TMS JTAG Mode The value on this signal controls the test mode select of the boundary scan logic or J TAG Controller When using the EJ TAG debug inter face this pin should be left disconnected since there is an internal pull up or driven high Table 1 Pin Description Part 5 of 6 8 of 53 January 19 2006 IDT RC32434 Signal Type Name Description EJTAG EJ TAG Mode The value on this signal controls the test mode select of the EJTAG Controller When using the J TAG boundary scan this pin should be left disconnected since there is an internal pull up or driven high JTAG TRST N J TAG Reset This active low signal asynchronously resets the boundary scan logic J TAG TAP Controller and the EJ TAG Debug TAP Controller An external pull up on the board is recommended to meet the TAG specification in cases where the tester can access this signal However for systems running in func tional mode one of the following should occur 1 acti
43. gnal is asserted by the ethernet PHY when either the transmit or receive medium is not idle Ethernet MII Receive Clock This clock is continuous clock that provides timing reference for the reception of data This pin also functions as the RMII REF_CLK input MIIRXD 3 0 Ethernet MII Receive Data This nibble wide data bus contains the data received by the ethernet PHY This pin also functions as the RMII RXD 1 0 input MIIRXDV Ethernet MII Receive Data Valid The assertion of this signal indicates that valid receive data is in the MII receive data bus This pin also functions as the RMII CRS_DV input MIIRXER Ethernet MII Receive Error The assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the MII receive data bus This pin also functions as the RMII RX ER input TXCLK Ethernet MII Transmit Clock This clock is a continuous clock that provides a timing reference for the transfer of transmit data TXD 3 0 0 Ethernet MII Transmit Data This nibble wide data bus contains the data to be transmitted This pin also functions as the RMII TXD 1 0 output TXENP 0 Ethernet MII Transmit Enable The assertion of this signal indicates that data is presenton the MII for transmission This pin also functions as the RMII TX EN output MIITXER 0 Eth
44. gnal is asserted during normal DDR operation This signal is negated following a cold reset or during a power down operation DDRCKN DDR Negative DDR clock This signal is the negative clock of the differential DDR clock pair Table 1 Pin Description Part 1 of 6 4 of 53 January 19 2006 IDT RC32434 Signal Type Name Description DDRCKP 0 DDR Positive DDR clock This signal is the positive clock of the differential DDR clock pair DDRCSN 0 DDR Chip Selects This active low signal is used to select DDR device s on the DDR bus DDRDATA 15 0 1 0 DDR Data Bus 16 bit DDR data bus is used to transfer data between RC32434 and the DDR devices Data is transferred on both edges of the clock DDRDM 1 0 0 DDR Data Write Enables Byte data write enables are used to enable specific byte lanes during DDR writes DRDM 0 corresponds DDRDATA T 0 DDRDM 1 corresponds to DDRDATA 15 8 DDRDQS 1 0 I O DDR Data Strobes DDR byte data strobes are used to clock data between DDR devices and the RC32434 These strobes are inputs during DDR reads and outputs during DDR writes DRDQS 0 corresponds to DDRDATA 7 0 DDRDQS I corresponds to DDRDATA 15 8 jw jw DDRRASN 0 DDR Row Address Strobe The DDR row address strobe is asserted during DDR transactions DDRVREF DDR Voltage Reference SSTL 2 DDR voltage reference is generated by an external source DDRWEN 0 DDR Wr
45. gy Inc 1 of 53 January 19 2006 2005 Integrated Device Technology Inc DSC 6214 IDT RC32434 Memory and Peripheral Device Controller Provides glueless interface to standard SRAM Flash ROM dual port memory and peripheral devices Demultiplexed address and data buses 8 bit data bus 26 bit address bus 4 chip selects control for external data bus buffers Automatic byte gathering and scattering Flexible protocol configuration parameters programmable number of wait states 0 to 63 programmable postread post write delay 0 to 31 supports external wait state generation supports Intel and Motorola style peripherals Write protect capability per chip select Programmable bus transaction timer generates warm reset when counter expires Supports up to 64 MB of memory per chip select DMA Controller 6DMA channels two channels for PCI PCI to Memory and Memory to PCI two channels for the Ethernet interface and two channels for memory to memory DMA operations Provides flexible descriptor based operation Supports unaligned transfers ie source or destination address may be on any byte boundary with arbitrary byte length Universal Asynchronous Receiver Transmitter UART Compatible with the 16550 and 16450 UARTs 16 byte transmit and receive buffers Programmable baud rate generator derived from the system clock Fully programmable serial characteristics 5 6 7 or 8 bit characters Eve
46. is used to interface to in circuit emulator tools providing access to internal registers and enabling the part to be controlled externally simplifying the system debug process The use of this core allows IDT s customers to leverage the broad range of software and development tools available for the MIPS archi tecture including operating systems compilers and in circuit emula tors PCI Interface The PCI interface on the RC32434 is compatible with version 2 2 of the PCI specification An on chip arbiter supports up to six external bus masters supporting both fixed priority and rotating priority arbitration Schemes The part can support both satellite and host PCI configura tions enabling the RC32434 to actas a slave controller for a PCI add in card application or as the primary PCI controller in the system The PCI interface can be operated synchronously or asynchronously to the other 1 0 interfaces on the RC32434 device Ethernet Interface The RC32434 has one Ethernet Channel supporting 10Mbps and 100Mbps speeds to provide a standard media independent interface MII or RMII allowing a wide range of external devices to be connected efficiently Double Data Rate Memory Controller The RC32434 incorporates a high performance double data rate DDR memory controller which supports x16 memory configurations up to 256MB This module provides all of the signals required to interface to discrete memory devices including a chip sel
47. ite Enable DDR write enable is asserted during DDR write transac tions PCI Bus PCIAD 31 0 1 0 PCI Multiplexed Address Data Bus Address is driven by bus master during initial PCIFRAMEN assertion Data is then driven by the bus master during writes or by the bus target during reads PCICBEN 3 0 10 PCI Multiplexed Command Byte Enable Bus P Cl commands are driven by the bus master during the initial PCIFRAMEN assertion Byte enable signals are driven by the bus master during subsequent data phase s PCICLK PCI Clock Clock used for all PCI bus transactions PCIDEVSELN I O PCI Device Select This signal is driven by a bus target to indicate that the tar get has decoded the address as one of its own address spaces PCIFRAMEN I O PCI Frame Driven by a bus master Assertion indicates the beginning of a bus transaction Negation indicates the last data PCIGNTN 3 0 uo PCI Bus Grant In PCI host mode with internal arbiter The assertion of these signals indicates to the agent that the internal RC 32434 arbiter has granted the agent access to the PCI bus In PCI host mode with external arbiter PCIGNTN 0 asserted by an external arbiter to indicate to the RC32434 that access to the PCI bus has been granted PCIGNTN 3 1 unused and driven high In PCI satellite mode PCIGNTN 0 This signal is asserted by an external arbiter to indicate to the RC32434 that access to the PCI bus has been granted PCIGNTN 3 1 un
48. n odd or no parity bit generation and detection 1 1 1 2 or 2 stop bit generation Line break generation and detection False start bit detection Internal loopback mode Supports standard 100 Kbps mode as well as 400 Kbps fast mode Supports 7 bit and 10 bit addressing Supports four modes master transmitter master receiver Slave transmitter slave receiver Additional General Purpose Peripherals Interrupt controller System integrity functions General purpose 1 0 controller Serial peripheral interface SPI Counter Timers Three general purpose 32 bit counter timers Timers may be cascaded Selectable counter timer clock source JTAG Interface Compatible with IEEE Std 1149 1 1990 CPU Execution Core The 32 bit CPU core is 100 compatible with the MIPS 32 instruction set architecture ISA Specifically this device features the 4Kc CPU core developed by MIPS Technologies Inc www mips com This core issues a Single instruction per cycle includes a five stage pipeline and is optimized for applications that require integer arithmetic The CPU core includes 8 KB instruction and 8 KB data caches Both caches are 4 way set associative and can be locked on a per line basis which allows the programmer control over this precious on chip memory resource The core also features a memory management unit MMU The CPU core also incorporates an enhanced joint test access group EJ TAG interface that
49. n Host mode supports 6 external masters fixed priority or round robin arbitration 10 like PCI Messaging Unit Ethernet Interface 10 and 100 Mb s ISO IEC 8802 3 1996 compliant Supports MII or RMII PHY interface Supports 64 entry hash table based multicast address filtering 512 byte transmit and receive FIFOs Supports flow control functions outlined in IEEE Std 802 3x 1997 DDR Memory Controller Supports up to 256MB of DDR SDRAM 1 chip select supporting 4 internal DDR banks Supports a 16 bit wide data port using x8 or x16 bit wide DDR SDRAM devices Supports 64 Mb 128 Mb 256 Mb 512 Mb and 1Gb DDR SDRAM devices Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs Automatic refresh generation Ine Interrupt q CEU co 4 Controller ICE MMU lt D Cache 1 Cache 3 Counter Timers PMBus DDR DDR 16 bit Controllers MIR MII Pe bys aC Controller 1 Ethernet 10 100 Interface DMA Controller IPBus 2227 Arbiter Memory amp lO Bus System 1UART GPIO SPI PCI Controller Integrity 16550 Interface Controller Monitor Memory amp i GPIO Pins SPI Bus PCI Bus Peripheral Bus 8 bit Serial Channel PCI Arbiter Host Mode IDT and the IDT logo are trademarks of Integrated Device Technolo
50. or IDT Power Normal 1 27 1 82 1 36 1 90 1 45 2 02 1 54 2 15 W Processors on the IDT web site Dissipation mode www idt com Standby 0 73 0 78 0 84 0 90 W mode Table 17 RC32434 Power Consumption 1 The RC 32434 enter Standby mode by executing WAIT instructions Minimal I O switching is assumed On chip logic outside the CPU core continues to function Power Curve The following graph contains a power curve that shows power consumption at various core frequencies Typical Power Curve 1 60 1 55 1 50 1 45 1 40 Power W 1 35 1 30 1 25 266 300 350 400 Core Frequency MHz Figure 22 RC32434 Typical Power Usage 37 of 53 January 19 2006 IDT RC32434 DC Electrical Characteristics Values based on systems running at recommended supply voltages as shown in Table 15 Note See Table 2 Pin Characteristics for a complete 1 0 listing Para I O Type meter Min Typical Max Unit Conditions LOW Drive lo 14 0 mA Vo 0 4V m 120 mA Vow 1 5V HIGH Drive la 41 0 mA Vo 0 4V m m 42 0 mA Voy 1 5V Schmitt Trigger 0 3 0 8 V Input STI putat V 20 E 10 05 V SSTL 2 forDDR loi 1 6 mA Vo 0 5V SDRAM loH 7 6 mA Von 1 76V Vi 0 3 0 5 51 0 0 18 V 0 5 51 0 0 18 VecSI O 0 3
51. pe Location Signal Category PCIAD 17 0 R5 PCI Bus Interface PCIAD 18 0 N4 PCIAD 19 0 T4 PCIAD 20 0 P4 PCIAD 21 0 R4 PCIAD 22 0 T3 PCIAD 23 0 R3 PCIAD 24 0 1 PCIAD 25 0 R1 PCIAD 26 0 P2 PCIAD 27 0 Pl PCIAD 28 0 N2 PCIAD 29 0 N1 PCIAD 30 0 N3 PCIAD 31 0 M2 PCIBEN 0 0 N12 PCIBEN 1 10 R9 PCIBEN 2 10 R7 10 R2 PCICLK 6 PCIDEVSEL 0 T8 PCIFRAME 0 P7 PCIGNTN 0 10 7 PCIGNTNI1 0 15 PCIGNTND2 0 R15 PCIGNTN 3 10 16 PCIIRDY 0 1 PCILOCKN 10 8 PCIPAR 0 T9 PCIPERRN 0 9 PCIREQN 0 0 P6 PCIREQN 1 10 5 PCIREQN 2 10 6 PCIREQN 3 0 P5 PCIRSTN 10 R6 PCISERRN 0 P9 Table 24 RC32434 Alphabetical Signal List Part 6 of 7 49 of 53 January 19 2006 IDT RC32434 Signal Name Type Location Signal Category PCISTOPN 0 P8 PCI Bus Interface PCITRDYN 0 R8 RSTN 0 B2 System RWN 0 Al Memory and Peripheral Bus SCK 0 K2 Serial Peripheral Interface SCL 0 L2 lC SDA 0 L1 SDI 0 L4 Serial Peripheral Interface SDO 0 K4 Vcc APLL C12 Power Vcc Core E8 E9 F9 H5 H12 J5 11 12 L8 M8 M9 Vcc DDR E12 F12 G12 K12 L12 M11 M12 0 E5 E6 E7 E10 F5 G5 K5 K6 L5 M5 M6 M7 M10 Vcc PLL B11 Vss F6 F7 F8 F10 Ground F11 66 67 G8 G9 G10 G11 H7 H8 H9 H10 H11 6 11 18 19 110 K7 K8 K9 K10 K11 L6 L7 L9 110 111 Vss APLL B12 Vss PLL All
52. pin can be configured as a general purpose 1 0 pin Alternate function pin name PCIGNTN 4 Alternate function PCI Grant 4 GPIO 11 1 0 General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name PCIREQN 5 Alternate function PCI Request 5 GPIO 12 1 0 General Purpose I 0 This pin can be configured as a general purpose 1 0 pin Alternate function pin name PCIGNTN 5 Alternate function PCI Grant 5 GPIO 13 1 0 General 1 0 This can be configured as a general purpose 1 0 pin Alternate function pin name PCIMUINTN Alternate function P CI Messaging unit interrupt output SPI Interface SCK 10 Serial Clock This signal is used as the serial clock output This may be used as a bit input output port Table 1 Pin Description Part 4 of 6 7 of 53 January 19 2006 IDT RC32434 Signal Type Name Description SDI 10 Serial Data Input This signal is used shift in serial data This be used as a bit input output port SDO 10 Serial Data Output This signal is used shift out serial data Bus Interface SCL 10 Clock I2C bus clock SDA Jo PC Data Bus l C bus data bus Ethernet Interfaces MIICL Ethernet MII Collision Detected This signal is asserted by the ethernet PHY when a collision is detected MIICRS Ethernet MII Carrier Sense This si
53. ration to be loaded and the internal PLL to lock onto the master clock CLK RSTN I O Reset The assertion of this bidirectional signal initiates a warm reset This sig nal is asserted by the RC32434 during a warm reset Table 1 Pin Description Part 6 of 6 Pin Characteristics Note Some input pads of the RC32434 do not contain internal pull ups or pull downs Unused inputs should be tied off to appropriate levels This is especially critical for unused control signal inputs such as WAITACKN which if left floating could adversely affect the RC32434 s operation Also any input pin left floating can cause a slight increase in power consumption 9 of 53 January 19 2006 IDT RC32434 Internal Function Pin Type Buffer 1 0 Type 41 Notes Memory and Peripheral BDIRN 0 LVTTL High Drive Bus BOEN 0 LVTTL High Drive WEN 0 LVTTL High Drive CSN 3 0 0 LVTTL High Drive MADDR 21 0 I 0 LVTTL High Drive MDATA 7 0 1 0 LVTTL High Drive OEN 0 LVTTL High Drive RWN 0 LVTTL High Drive WAITACKN LVTTL STI pull up DDR Bus DDRADDRT I3 0 0 SSTL_2 DDRBA 1 0 0 SSTL_2 DDRCASN 0 SSTL_2 DDRCKE 0 SSTL_2 LVC MOS DDRCKN 0 SSTL_2 DDRCKP 0 SSTL 2 DDRCSN 0 SSTL 2 DDRDATA 15 0 1 0
54. rithm EN initial value is zero 0x6 reserved 0x7 reserved Table 3 Boot Configuration Encoding Part 1 of 2 12 of 53 January 19 2006 IDT RC32434 Signal Name Description MADDR 11 Disable Watchdog Timer When this bit is set the watchdog timer is disabled follow ing a cold reset 0 0 Watchdog timer enabled 0 1 Watchdog timer disabled MADDR 13 12 Reserved These pins must be driven low during boot configuration MADDR 15 14 Reserved Must be set to zero Table 3 Boot Configuration Encoding Part 2 of 2 13 of 53 January 19 2006 IDT RC32434 Logic Diagram RC32434 System Signals Ethernet EJ TAG TAG Signals General Purpose 1 0 SPI CLK COLDRSTN RSTN EXTCLK EXTBCV i MIIR MIIRX MIITX JTAG TRST N JTAG TCK JTAG TD JTAG TDO JTAG_TMS EJTAG TMS GPIO 13 0 SDO SCK SDI SDA SCL RC32434 BDIRN BOEN WEN CSN 3 0 MADDR 21 0 7 0 RWN WAITACKN RADDR 13 0 R BA 1 0 RCASN RCKE RCKN RCKP RCSN RDATA 15 0 RDM 1 0 RDQS 1 0 RRASN RVREF RWEN CJ C QU QU QU U U U UO UO UO Jc CU C Q QU QU 0000 00 00 PCIAD 31 0 PCICBEN 3 0 PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN 3 0 PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN 3 0 PCIRSTN PCISERRN PCISTOPN PCITRDYN VccCore Vccl O V
55. ss VccPLL VssPLL Memory and Peripheral Bus DDR Bus PCI Bus Power G round Figure 1 Logic Diagram 14 of 53 January 19 2006 IDT RC32434 AC Timing Definitions Below are examples of the AC timing characteristics used throughout this document gt Tlow k Thigh clock b E ug lt gt Tdo su in Output signal 1 f I Tzd Taz Output signal 2 0 Tsu lt Thld Input Signal 1 asp 2 N 4 Signal 1 Z N Signal 2 gt Tskew Signal 3 Figure2 AC Timing Definitions Waveform Symbol Definition Tper Clock period Tlow Clock low Amount of time the clock is low in one clock period Thigh Clock high Amount of time the clock is high in one clock period Trise Rise time Low to high transition time Tfall Fall time High to low transition time Tjitter J itter Amount of time the reference clock or signal edge can vary on either the rising or falling edges Tdo Data out Amount of time after the reference clock edge that the output will become valid The minimum time represents the data output hold The maximum time represents the earliest time the designer can use the data Tzd Z state to data valid Amount of time after the reference clock edge that the tri stated output takes to become valid Tdz Data valid to Z state Amount of time after the reference clock edge that the
56. t NMI when the counter expires and also contains an address space monitor that reports errors in response to accesses to undecoded address regions Thermal Considerations The RC32434 is guaranteed in an ambient temperature range of 0 to 70 C for commercial temperature devices and 40 to 85 for industrial temperature devices Revision History November 3 2003 Initial publication Preliminary Information December 15 2003 Final version In Table 7 changed maximum value for Tskew in 266MHz category and changed values for Tdo in all speed grades for signals DDRADDR etc In Table 8 changed minimum values in all speed grades for all Tdo signals and for Tsu and Tzd in MDATA 7 0 In Table 16 added reference to Power Considerations document In Table 17 added 2 rows under PCI and Notes 1 and 2 J anuary 5 2004 Table 19 Pin F6 was changed from Vcc 1 0 to Vss In Table 23 pin F6 was deleted from the Vcc 1 0 row and added to the Vss row January 27 2004 In Table 3 revised description for MADDR 3 0 and changed 4096 cycles to 4000 for MADDR 7 Note MADDR was incorrectly labeled as MDATA in previous data sheet March 29 2004 Added Standby mode to Table 16 Power Consumption April 19 2004 Added the 2C feature In Table 20 pin L1 becomes SDA and pin L2 becomes SCL May 25 2004 In Table 9 signals MIIRXCLK and MIITXCLK the Min and Max values for Thigh Tlow 9c were changed to 140 and 260 respectively
57. teristics Part 1 of 2 21 of 53 January 19 2006 IDT RC32434 266MHz 300MHz 350MHz 400MHz Timing Signal Symbol W Unit Diagram in Max Min Max Min Max Min Max Reference MDATAI7 0 Tsu_8c EXTCLK rising 6 0 _ 6 0 _ 6 0 _ 6 0 _ ns See Figures 8 Thid 8 J ns ARS conie Tdo_8c 0 4 4 5 0 4 4 5 0 4 4 5 0 4 4 5 ns Tdz 8c 0 0 5 0 0 5 0 0 5 0 0 5 ns Tzd 8c 0 4 33 0 4 33 04 33 0 4 3 3 ns EXTCLIC Tper 8d none 15 _ 66 6 66 666 ns BDIRN Tdo 8e rising 0 4 3 8 0 4 3 8 0 4 3 8 0 4 3 8 ns Tdz 8e ns Tzd_8e2 ns BOEN Tdo_8f rising 0 4 3 8 0 4 3 8 0 4 3 8 0 4 3 8 ns Tdz 8f _ _ _ _ _ _ _ _ ns Tzd 8f ns WAITACKN Tsu_8h rising 6 5 6 5 6 5 6 5 ns Thld 8h 0 x 0 0 0 x ns 8h none 2 EXTCLK 2 EXTCLK 2 EXTCLK 2 EXTCLK ns CSN 3 0 Tdo 81 rising 0 4 40 0 4 40 0 4 40 0 4 40 ns Tdz 8i ns Tzd 8i _ _ _ _ _ _ _ _ ns RWN 8j rising 0 4 3 8 0 4 3 8 0 4 3 8 0 4 3 8 ns Tdz 8j ns Tzd 8j ns OEN 8k rising 0 4 40 0 4 40 0 4 4 0 0 4 4 0
58. us Stop condition Tsu 12d SDA rising 06 06 06 06 us Bus free time between Tdelay 12e 13 13 13 13 us a stop and start condi tion Thld 12c Table 11 AC Timing Characteristics Part 2 of 2 1 For more information see the I2C Bus specification by Philips Semiconductor m low_ aie Thigh_ Thld 12c Tsu 12d Tdelay 12e Figure 14 2 AC Timing Waveform 266MHz 300MHz 350MHz 400MHz Timing Reference Condi Signal Symbol Edge Unit tons Diagram g Min Max Min Max Min Max Min Max Reference GPIO GPIO 13 0 Tpw 13b None 2 ICLK 2 ICLK 2 ICLK 2 ICLK ns See Figure 15 Table 12 GPI0 AC Timing Characteristics 1 The values for this symbol were determined by calculation not by testing GPIO asynchronous input X Tpw 130 gt Figure 15 GPIO AC Timing Waveform 30 of 53 January 19 2006 IDT RC32434 Referen 266MHz 300MHz 350MHz 400MHz Condi Timing Signal Symbol jo E Unit Diagram Min Max Min Max Min Max Min tions Reference spi SCK Tper 15a None 100 166667 100 166667 100 166667 100 166667 ns SP See Figures Thigh 15a 40 83353 40 83353 40 833533 40 83353 ms TM E Tlow 15a SDI Tsu 15b SCK risingor 60 60 60 60 ns
59. used and driven high PCIIRDYN JO PCI Initiator Ready Driven by the bus master to indicate that the current datum can complete Table 1 Pin Description Part 2 of 6 5 of 53 January 19 2006 IDT RC32434 Signal Type Name Description PCILOCKN 10 PCI Lock This signal is asserted by an external bus master to indicate that an exclusive operation is occurring PCIPAR 10 PCI Parity Even parity ofthe P CIAD 31 0 bus Driven by the bus master during address and write Data phases Driven by the bus target during the read data phase PCIPERRN 10 PCI Parity Error If a parity error is detected this signal is asserted by the receiving bus agent 2 clocks after the data is received PCIREQN 3 0 10 PCI Bus Request In PCI host mode with internal arbiter These signals are inputs whose assertion indicates to the internal RC32434 arbiter that an agent desires ownership of the PCI bus In PCI host mode with external arbiter PCIREQN O asserted by the RC32434 to request ownership of the PCI bus PCIREQN 3 1 unused and driven high In PCI satellite mode PCIREQN O this signal is asserted by the R C32434 to request use of the PCI bus PCIREQN I function changes to P CIIDSEL and is used as a chip select during configuration read and write transactions PCIREQN 3 2 unused and driven high PCIRSTN 10 PCI Reset In host mode this signal is asserted by the RC32434 to generate PCI reset
60. ut Xvalid X Thld 10c Tsu lc gt Point to point input X valid X Figure 11 PCI AC Timing Waveform COLDRSTN cold reset Tpw 100 gt E PCI interface enabled PCIRSTN output stel X RSTN N warm reset Note During and after cold reset PCIRSTN is tri stated and requires a pull down to reach a low state After the PCI interface is enabled in host mode PCIRSTN will be driven either high or low depending on the reset State of the RC32434 Figure 12 PCI AC Timing Waveform PCI Reset in Host Mode 28 of 53 January 19 2006 IDT RC32434 cue Su PCIRSTN input MDATA 5 0 EO SEE PCI bus signals RSTN N X lt gt Tpw_10e Tdz 10 gt warm reset f 5 c j Figure 13 PCI AC Timing Waveform PCI Resetin Satellite Mode Referente 266MHz 300MHz 350MHz 400MHz M Timing Signal Symbol Edge Min Max Min Max Min Max Min Max Unit Conditions 2 eference Pc SCL Frequency none 0 100 0 100 0 100 0 100 kHz 100 KHz See Figure 14 Thigh_12a 40 40 40 40 us Tlow_12a Trise 12a 1000 1000 1000 1000 ns Tfall 12a 3001 30 300
61. vely drive this signal low with control logic 2 statically drive this signal low with an external pull down on the board 3 clock J TAG while holding EJ TAG_TMS and or TAG_TMS high JTAG_TCK J TAG Clock This is an input test clock used to clock the shifting of data into or out of the boundary scan logic J TAG Controller or the EJ TAG Controller is independent of the system and the processor clock with a nomi nal 5096 duty cycle JTAG TDO J TAG Data Output This is the serial data shifted out from the boundary scan logic J TAG Controller or the EJ TAG Controller When no data is being shifted out this signal is tri stated JTAG TD J TAG Data Input This is the serial data input to the boundary scan logic J TAG Controller or the EJ TAG Controller System CLK Master Clock This is the master clock input The processor frequency is a mul tiple of this clock frequency This clock is used as the system clock for all mem ory and peripheral bus operations EXTBCV Load External Boot Configuration Vector When this pin is asserted i e high the boot configuration vector is loaded from an externally supplied value during a cold reset EXTCLK External Clock This clock is used for all memory and peripheral bus opera tions COLDRSTN Cold Reset The assertion of this signal initiates a cold reset This causes the processor state to be initialized boot configu
62. will also allow the input signals to propagate when the I O powers are brought up Note The ESD diodes may be damaged if one of the voltages is applied and one of the other voltages is ata ground level A Recommended Sequence t2 gt 0 whenever possible V Core tl 2 can be 0 V amp SI O followed by V I 0 Vccl O 3 3V VccSI O 2 5V VccCore 1 2V Vecl 0 VecSI 0 VecCore gt Time B Reverse Voltage Sequence If sequence is not feasible then Sequence B can be used t1 lt 50 5 and t2 lt 50ms to prevent damage A VcclO Vccl 0 3 3V VccSI O VccSI O 2 5V VccCore 1 2V VccCore i 1 gt P 1 Time t o C Simultaneous Power up Vccl O VccSI O and VccCore be powered up simultaneously 36 of 53 January 19 2006 Power Consumption Parameter 266MHz 300MHz 350MHz 400MHz Unit m Conditions Typ Max Typ Max Typ Max Typ Max lec 1 0 215 270 220 275 225 280 230 285 mA 35 pF 2202950 lec 510 DDR 70 8 75 90 85 100 95 110 mA ambient 25 Max values use the maximum volt lec Core Normal 325 510 350 550 400 610 450 670 mA ages listed in Table 15 Typical val lec PLL mode ues use the typical voltages listed Standby 20 240 260 280 ma inthattable f mode Note For additional information see Power Considerations f
Download Pdf Manuals
Related Search