Home

TXMC633 - powerbridge.de

Contents

1. Enable then ISP Mode in the ISP Mode Enable Register GER ENA y Assure that User FPGA Configuration Mode is set to SPI Flash Set FP_CFG_MD 0 y Set the reading start address and write instruction in the ISP Write SPI Address to q Configuration Register ISP SPLADD y Write SPI Instruction to ISP_SPI_INS y Start the Instruction with ISP Command Register Start Instruction with ISP_SPI_INS_CMD 1 y Read i lt Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for A next write instruction Instruction Busy yes no y Read one page of SPI Data from In Circuit Programming Data Space Read SPI Data from and write to Data file ISP Data Space and Write to Data file Process could be repeated until all needed data are written to the Data file ye no After completion the reading process the ISP Mode bit must cleared to set configuration path back to User FPGA l amis a TXMC633 User Manual Issue 1 0 1 Page 35 of 71 TEWSS TECHNOLOGIES 7 4 9 Generate Spartan6 Configuration Data To use the maximum configuration speed the TXMC633 must be configured to use the 32 MHz external master clock as CCLK To use this configuration feature the following configuration option must be set Enable External Master Clock g ExtMasterCcik en enable Setup External Master Clock Devision g ExtMasterCcl
2. Spartan 6 Slices Flip DSP48A1 Block CMTs GTP Flops Slices RAM Kb Transceivers LX45T 6 822 54 576 58 2 088 4 LX100T 15 822 126 576 180 4 824 6 4 Table 7 1 TXMC633 FPGA Feature Overview The board supports JTAG master serial mode configuration from SPI Flash or SelectMAP configuration via Configuration FPGA Register The FPGA is equipped with 4 I O banks and 4 MGT multi gigabit transceiver Bank Veco VREF Signals Remarks Bank 0 3 3V none dig Front I O Interface Bank 1 1 5V 0 75V DDR3 Bank GPIO LED Local Bus Interface Debug pull up down config Bank 2 3 3V none dig Back I O Interface Configuration Bank 3 3 3V none dig Front I O Interface GTP Bank Description Remarks MGTO PCle Endpoint Block to PCle Switch MGT1 MGT connection to XMC connector P16 MGT2 MGT connection to XMC connector P16 MGT3 MGT connection to XMC connector P16 Table 7 2 FPGA Bank Usage The FPGA s VCCAUX is connected to the 3 3V supply TXMC633 User Manual Issue 1 0 1 Page 25 of 71 TEWSS TECHNOLOGIES 7 3 User FPGA Gigabit Transceiver GTP The TXMC633 provides one MGT as Spartan 6 PCI Express Endpoint Block and three MGT for high speed XMC P16 interface PCle Interface PCle X1 Interface PCle Clock 125 MHz Figure 7 2 GTP Block Diagram GTP Signal FPGA Connected
3. Figure 10 3 Pin Assignment P16 Back I O Connector TXMC633 xx TXMC633 User Manual Issue 1 0 1 Page 62 of 71 TEWSS TECHNOLOGIES 10 5 X2 JTAG Header This header directly connects a JTAG interface cable to the JTAG pins to the on board User FPGA JTAG chain The pinout of this header matches the pinout of the Xilinx Platform Cable USB II This allows the direct usage of Xilinx software tools like Chipscope or IMPACT with the Platform Cable USB II The connector is a 2 mm dual row shrouded header 10 5 1 Connector Type Connector Type 2 00 mm Pitch Milli Grid Header Source amp Order Info Molex 877601416 or compatible 10 5 2 Pin Assignment Pin Signal Description 1 NC Not Connected 2 VREF JTAG Reference Voltage 3 3V 3 GND Ground 4 TMS Test Mode Select Input 5 GND Ground 6 TCK Test Clock 7 GND Ground 8 TDO Test Data Output TAP Controller TDI 9 GND Ground 10 TDI Test Data Input TAP Controller TDO 11 GND not connected on the TXMC633 12 TRST not connected on the TXMC633 13 PGND Used on TXMC633 for XILINX Header present detection 14 NC HALT INIT WP signal Optional Not connected on the TXMC633 Table 10 2 Pin Assignment JTAG Header X2 TXMC633 User Manual Issue 1 0 1 Page 63 of 71 TEWSS TECHNOLOGIES 10 6 X3 Debug Connector 10 6 1 Connector Type Connector Type 20 pin 1 mm FPC Flexible Printed Circuit Connector
4. Wait on ISP SPI Instruction Done for successful process end Instruction Busy no y e e FP_CFG_MD After completion the instruction process the ISP Mode bit must be cleared to Der CET set configuration path back to User FPGA TXMC633 User Manual Issue 1 0 1 Page 36 of 71 TEWSS TECHNOLOGIES 7 4 11 Board Configuration FPGA The Board Configuration FPGA BCF is factory configured and handles the basic board setup Changing or erase the BCF content leads to an inoperable TXMC633 FPGA configuration TXMC633 User Manual Issue 1 0 1 Page 37 of 71 TEWSS TECHNOLOGIES 7 5 Clocking 7 5 1 FPGA Clock Sources As a central clock generator of TXMC633 the Si5338 clock generator is used This provides all necessary clocks for the User FPGA and the Configuration FPGA The following figure depicts an abstract User FPGA clock flow E Hi GTP 123 CLKO PCle CLK125 3 f GIP 10 CLKO Figure 7 5 FPGA Clock Sources The following table lists the available clock sources on the TXMC633 FPGA Clock Pin Name FPGA Pin Source Description Number MGTREFCLKO_101 A10 B10 SI5338 low jitter clock 125 MHz generator PCle Reference clock MGTREFCLKO_113 A12 B12 PCle Switch 100 MHz differential Reference PI7C9XG404 clock input IO_L30P_GCLK1_2 Y13 S15338 low jitter clock MCB CLK generator 62 5 MHz IO L43
5. net DDR A 11 loc H19 Bank 1 net DDR_A 12 loc F22 Bank 1 config prohibit G19 Bank 1 DDR_A 13 config prohibit F20 Bank 1 DDR_A 14 net DDR BA O loc KIT Bank 1 net DDR_BA 1 loc L17 Bank 1 net DDR_BA 2 loc K18 Bank 1 net DDR CK P loc K20 Bank 1 net DDR_CK_N loc L19 Bank 1 net DDR DQ 0 loc R20 Bank 1 net DDR_DO 1 loc R22 Bank 1 net DDR_DO 2 loc P21 Bank 1 net DDR_DQ 3 loc P22 Bank 1 net DDR_DO 4 loc L20 Bank 1 net DDR DQ 5 loc L22 Bank 1 net DDR_DO 6 loc M21 Bank 1 net DDR DO T loc M22 Bank 1 net DDR_DO 8 log I21 Bank 1 net DDR DQ 9 loc 1722 Bank 1 net DDR DQ 10 loc U20 Bank 1 net DDR_DO 11 loc U22 Bank 1 net DDR_DQ 12 loc W20 Bank 1 net DDR_DQ 13 loc W22 Bank 1 net DDR_DO 14 loc Y21 Bank 1 net DDR DQ 15 loc Y22 Bank 1 net DDR_CKE loc F21 Bank 1 net DDR_ODT loc J22 Bank 1 net DDR_LDOS_P loc N20 Bank 1 net DDR_LDOS_N loc N22 Bank 1 net DDR_UDOS_P loc V21 Bank 1 net DDR_UDOS_N loc V22 Bank 1 net DDR CAS n loc K22 Bank 1 net DDR_RAS_n loc K21 Bank 1 net DDR_WE_n loc K19 Bank 1 net DDR_LDM loc N19 Bank 1 net DDR_UDM loc P20 Bank 1 net DDR_RESET_n loc H18 Bank 1 net DDR RZQ loc F18 Bank 1 net DDR ZIO loc P19 Ban
6. 3 1 ESD Protection The TXMC633 is sensitive to static electricity Packing unpacking and all other handling of the TXMC633 has to be done in an ESD EOS protected Area 3 2 Thermal Considerations Forced air cooling is recommended during operation Without forced air cooling damage to the device can occur 3 3 Assembling Hints When disassembling the TXMC633 from carrier board please keep the mechanical stress as low as possible TXMC633 User Manual Issue 1 0 1 Page 11 of 71 TEWSS TECHNOLOGIES 4 PCI Device Topology The TXMC633 consists of two FPGAs Both FPGA are designed as a PCle PCI endpoint devices One FPGA is the User FPGA which could be programmed with user defined FPGA code The second FPGA takes control of on board hardware functions of TXMC633 and also the configuration control of the User FPGA The Configuration FPGA PCI endpoint is connected via a PCI to PCle Bridge to the first x1 Downstream Port of the PCIe Switch Pericom PI7C9X2G404SL The User FPGA Spartan6 PCle endpoint is directly connected to the second x1 Downstream Port The x1 Upstream Port of the PCle Switch is connected to the XMC P15 Connector communicating with the host system Figure 4 1 PCle PCI Device Topology Device Vendor ID Device ID Class Description as shown by Ispci Code 0x12D8 0x2404 0x060400 PCI bridge PI7C9X2G404SL Pericom 0x04h to indicate device as PCI to P
7. Master Serial SPI mode On delivery the SPI configuration Platform Flash contains the TEWS example application for the TXMC633 Spartan6 device 7 4 1 Master Serial SPI Flash Configuration It is important for User FPGA Configuration via ISP Master Mode that the ISP Mode Enable ISP EN is set to disable the ISP Mode This is the default value after the Power Up See also Register Description of TXMC633 Configuration Device TXMC633 User Manual Issue 1 0 1 Page 27 of 71 TEWSS TECHNOLOGIES 7 4 2 Manually User FPGA SPI Flash Reconfiguration A manually User FPGA Reconfiguration could be release with User FPGA Reconfigure Command in the Global Configuration Register Set the User FPGA Reconfigure Command to set the User FPGA to configuration state with all FPGA I O pins are High Z Use the following procedure to release a User FPGA SPI Re configuration Assure that ISP Mode Enable is disabled Set ISP_ENA 0 y By Re configuring the Spartan6 the XILINX PCle endpoint is reloaded Set S6 LINK ENA 0 and is temporarily not available on the PCI bus To avoid error messages Z of the PCle switch the link between the PCle Switch and the Spartan6 is disabled y Set FP_CFG_MD 0 Set the User FPGA Configuration Mode FP_CFG_MD to Master Serial Set FP_RE_CFG 1 SPI and set and the Re Configuration is prepared y Set FP RE CFG 0 Release a Re configuration by setting the FP RE CF
8. C17 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 61 gt C18 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 62 gt A20 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 63 gt B20 OUTPUT LVCMOS33 0 8 SLOW Table 7 6 Digital Front I O Interface TXMC633 User Manual Issue 1 0 1 Page 42 of 71 TEWSS TECHNOLOGIES 7 7 Back I O Interface P14 Back I O Pins of the TXMC633 are direct routed to the Spartan6 FPGA The I O functions of these FPGA pins are directly dependent on the configuration of the FPGA The Spartan6 VCCO voltage is set to 3 3V so only the 3 3V I O standards LVCMOS33 LVTTL33 and LVDS 33 are possible for using on TXMC633 back UO interface Signal Name men Direction Eder Bier BACK 100 AA4 IN OUT LVDS 33 2 BACK 100 AB4 IN OUT LVDS 33 2 BACK 101 W6 IN OUT LVDS_33 2 BACK 101 Y6 IN OUT LVDS 33 2 BACK 102 T7 IN OUT LVDS 33 2 BACK 102 U6 IN OUT LVDS 33 2 BACK 103 Y7 IN OUT LVDS 33 2 BACK 103 AB7 IN OUT LVDS 33 2 BACK 104 V7 IN OUT LVDS 33 2 BACK 104 W8 IN OUT LVDS_33 2 BACK 105 AA8 IN OUT LVDS_33 2 BACK 105 AB8 IN OUT LVDS 33 2 BACK 106 T8 IN OUT LVDS 33 2 BACK 106 U8 IN OUT LVDS 33 2 BACK 107 R9 IN OUT LVDS_33 2 BACK 107 R8 IN OUT LVDS 33 2 BACK 108 Y9 IN OUT LVDS 33 2 BACK 108 AB9 IN OUT LVDS 33 2 BACK 109 U9 IN OUT LVDS_33 2 BACK 109 V9 INOUT LVDS_33 2 BACK 1010 AA10 IN OUT LVDS 33 2 BACK 1010 AB10 IN OUT LVDS 33 2 BA
9. Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron a o GE ZE EE EE et EE GE of urt T O T O O T O 1 0 T O 1 0 T O T O 1 0 T O 1 0 T O O T O T O 1 0 T O 1 0 T O 1 0 T O X1 X1 X1 X1 X1 X1 X1 x1 x1 X1 X1 X1 X1 X1 X1 X1 X1 X1 x1 x1 x1 X1 TXMC633 User Manual Issue 1 0 1 Page 67 of 71 TEWSS TECHNOLOGIES ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne i EE et ih ut ep GE EE GE GT Ce pb ER F urt er EE EE EE et et urt E ER EE Et EE ut tut EE GT EE EE ft EE ce CP E et GE GE EE CG CS ROER GE EE EE G GE GE OE EE EE EE CG cb GE AE ECKE EE GE Gr EE ct FPGA IO FPGA_IO FPGA LO FPGA ID FPGA IO FPGA IO FPGA IO FPGA IO FPGA IO FPGA IO FPGA IQ FPGA IO FPGA IO FPGA IQ FPGA IO FPGA IO FPGA IO FPGA IO FPGA IQ FPGA IO FBGA IQ FPGA IQ FPGA IO FPGA IO FPGA IO FEGA TO FPGA IO FPGA IQ FPGA IQ FPGA IQ FPGA IQ FPGA IO FPGA IQ FPGA TO FPGA IQ FPGA IQ FPGA_ IQ FPGA IO FPGA IQ FPGA IO FPGA IO FPGA IQ BACK IO BACK 10 BACK IO BACK IO BACK IO BACK T BACK IO BACK TO BACK IO
10. Source amp Order Info AMP 2 487951 0 2 84953 0 or Molex 0522072060 10 6 2 Pin Assignment Pin Signal UO Description 1 JTAG SEL O A 4 7k pull up to 3 3 Volt is located on the TXMC633 2 3 3V O JTAG reference I O voltage 3 TDO O Test Data Output Input at JTAG Interface 4 GND Ground 5 TDI Test Data Input Output at JTAG Interface 6 TMS Test Mode Select Input 7 GND Ground 8 TCK Test Clock 9 GND Ground 10 USER RxD FPGA UART Receive Data Input 11 1 5V O UART reference I O voltage 12 USER TxD O FPGA UART Transmit Data Output 13 GND Ground 14 FPGA RxD Used for Configuration FPGA on TXMC633 15 3 3V O 3 3V reference I O voltage 16 FPGA_TxD O Used for Configuration FPGA on TXMC633 17 GND Ground 18 3 3V O 3 3 Volt 19 1 5V O User signal reference I O voltage 20 GPIO_BUT User signal connected to the FPGA A 4 7k pull up to 1 5 Volt is located on the TXMC633 Table 10 3 Pin Assignment Debug Connector X3 TXMC633 User Manual Issue 1 0 1 Page 64 of 71 TEWSS TECHNOLOGIES 11 Appendix A This appendix contains the signal to pin assignments for the Spartan6 FPGA Simulation Tool Owner TEWS TECHNOLOGIES GmbH Am Bahnhof 7 D 25469 Halstenbek Tel 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail support tews com Copyright c 2014 TEWS TECHNOLOGIES GmbH History S Version 1 SE 29 04 2014
11. TXMC633 User Manual Issue 1 0 1 Page 46 of 71 TEWSS TECHNOLOGIES 7 8 2 SPI Flash The TXMC633 provides a Winbond W25Q32 32 Mbit serial Flash memory this Flash is used as FPGA configuration source default configuration source After configuration it is always accessible from the FPGA so it also can be used for code or user data storage The SPI EEPROM is connected via Quad x4 SPI interface to Spartan6 configuration interface SPI PROM Signal Bank Veco Pin Description Spartan6 CLK 2 3 3V Y20 Serial Clock CCLK CSi 2 3 3V AA3 Chip Select CSO B DI bit0 2 3 3V AB20 Serial Data input MOSI MISO 0 DO bit1 2 3 3V AA20 Serial Data output DIN MISO 1 WP bit2 2 3 3V R13 MISO 2 HOLD bit3 2 3 3V T14 MISO 3 Table 7 9 FPGA SPI Flash Connections TXMC633 User Manual Issue 1 0 1 Page 47 of 71 TEWSS TECHNOLOGIES 7 9 Serial Number Allocation The TXMC633 Module Serial Number is stored on board on the module and can be read on both FPGA devices The Configuration FPGA MachXO2 provides a Serial Number Register in the local register space For the User FPGA Spartan6 an I2C Master interface is needed to read the serial number via an 12C interface from the Configuration FPGA For this purpose the Configuration FPGA provides an I2C slave interface Signal Bank Veco Pin Description FPGA_SCL 1 1 5V R17 Serial Clock A negative edge clock data out FPGA
12. Value 31 6 5 PULL_CNT Reserved I O Pull Resistor Controller 0 Spartan6 User FPGA controls Pull Resistor 1 MachXO2 FPGA controls Pull Resistor R W 0 4 S6_LINK_ENA 1 Spartan6 to PCle Switch LINK is enabled 0 Spartan6 to PCle Switch LINK is disabled R W 1 3 FP_INIT_STAT User FPGA INIT_B Pin Status 0 FPGA INIT_B Pin Level is Low active 1 FPGA INIT_B Pin Level is High not active 2 FP_DONE_STAT User FPGA DONE Pin Status The FPGA Done pin is high in case of successful FPGA configuration 0 FPGA DONE Pin Level is Low not active 1 FPGA DONE Pin Level is High active 1 FP_RE_CFG After power up the FPGA automatically configures from the on board SPI Flash in Master Serial SPI mode User FPGA Re Configuration 1 Set all FPGA UO pins to High Z and prepare a User FPGA Re Configuration 1 gt 0 Start User FPGA Re Configuration R W 0 0 FP_CFG_MD Set User FPGA Configuration Mode O Master Serial SPI 1 Slave SelectMap Parallel After power up the User FPGA automatically configures from the on board SPI Flash in Master Serial SPI mode RW 0 Table 5 1 TXMC633 User Manual Issue 1 0 1 User FPGA Configuration Control Status Register Page 16 of 71 TEWSS TECHNOLOGIES 5 2 2 User FPGA Configuration Data Register 0xD4 Reset Value ISP Select Map Write Data w Write Data Register for direct SeleciMap FPGA progra
13. Write 32bit Config Data to ISP FP DAT End of File no yes i 1 3 Write OxFF to Dummy Write accesses to create configuration clock cycles while ISP FP DAT lt FP_DONE_STAT is low e A successful configuration of the User FPGA is indicated with Reading FP_DONE_STAT FP_DONE_STAT in the User FPGA Configuration Control Status Register and the on board User FPGA Done LED 0 FPGA DONE Pin Level is Low FPGA is not configured DONE 1 1 FPGA DONE Pin Level is High FPGA is configured ves no After Re configuration was successful the User FPGA Configuration Mode and Set FP MD 0 the ISP Mode could be disabled Also the link between the PCle Switch and the Set ISP ENA 0 Spartan6 must be enabled Set S6 LINK ENA 1 TXMC633 User Manual Issue 1 0 1 Page 29 of 71 TEWSS TECHNOLOGIES If not all configuration data bytes are written the User FPGA is not configured correctly An incomplete configuration could be aborted with the ISP SPI RST CMD Command The number of bytes that must be written corresponds to the size of the XILINX configurations files Typically the bin or the bit file could be used as data source The bit file is the standard generated programming file This is a binary configuration data file which contains header information that does not need to be downloaded to the FPGA For generating the bin file the BitGen option g Binary yes must be used Th
14. 44 TE AE AE AE AAA AAA RAN RA ad EH MCB 3 I O Termination net DDR DO net DDR DOS MCB 3 1 0 Standards net DDR_DO ios net DDR_A ios net DDR_BA ios net DDR DOS ios net DDR CK ios net DDR CKe ios net DDR RAS n ios net DDR CAS n ios net DDR WE n ios net DDR ODT ios net DDR RESET n ios net DDR DM ios net DDR RZQ ios net DDR ZIO ios MCB 3 Pin Location net DDR A O net DDR_A 1 net DDR A 2 net DDR A 3 net DDR A 4 net DDR A S net DDR A 6 net DDR A 7 net DDR A 8 net DDR A 9 net DDR A 10 HE HE in term in term tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard tandard LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC R11 T11 Constraints for Clock AA12 AB12 W12 y12 T12 U12 v13 W13 BALA AB14 W14 Y14 U14 U13 y15 AB15 AA16 AB16 Y16 W15 yl6 VIS T15 yl5 y17 AB17 AA18 AB18 WLI yig VIT W18 SSTLIS II SSTLIS II Masks H21 H22 G22 J20 ZON M20 MLS 6205 E20 azz als Address HE SE SE FE SE FE FE SE SE GE GE SE GE SE SE FE SE SR SR GE SR GE GE SE FE SE SE SE GE SE OE H dh de SE SE FE SE de GE GE Sik Se Bank Bank Bank Ba
15. LL BUS 6 OC net LL BUS 7 OC net PULL IN O loc net PULL IN 1 loc net PULL IN 2 loc net PULL IN 3 loc net PULL IN 4 loc net PULL IN 5 loc net PULL IN 6 loc net PULL IN 7 loc net DWNRST2 n loc He HEHE AE HEFE HEHE FE HE FE E FE a fe de a EEE HEE HEHE A EE E Section General Purpose I O HE 44441 444 4 FE HE FE E ak TE FE FE FE FE FE FE 44 FE FE EEE HEE HEE E E E E EEE EE SE I O Standards net USER_LED iostandard net FPGA_SDA iostandard net FPGA_SCL iostandard net USER_RXD iostandard net USER_TXD iostandard net USER BUT iostandard Location Constraints net USER LED O oc net USER LED 1 OC net FPGA SDA oc net FPGA_SCL oc net USER_RXD loc net USER_TXD loc net USER_BUT loc SP6_CLK period MCB_CLK SP6_CLK 32 MHz high 50 period MCB_CLK 62 5 MHz high 50 USER_CLK period USER CLK 83 3325 MHz high 50 E AE AE AE FE AE AE FE AE FE EAE EE F 44 444444444444 LVCMOS15 LVCMOS15 LVCMOS15 B22 316 317 C20 c22 L15 K16 D21 U19 T20 N16 P16 M17 M18 R15 R16 L3 E AE AE AE FE AE AE FE AE FE AE AE FE HE AE AE AE AE FE AE AE AE AE FE EH HE LVCMOS15 LVCMOS15 LVCMOS15 LVCMOS15 LVCMOS15 LVCMOS15 M16 N15 P18 R17 T17 T19 T18 ARR AE
16. LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC GL DS RI TT p5 yan HA Vie p4 TOU N7 R4 GELS FLT HI El Da TRES NE HI can Gan GI VES Jan Tan D4 RA F7 Eo TES E6 got G8 NRE ga NE F14 611 tara BLE C19 Cor HIO ALT A18 ele ETE A20 B20 pl teo ARQ WI RAL vi AS Wan rin po F2 Hp KL 31 EI B1 von RI TES va LA M3 sk de SE SE FE SE Sik FE GE e e Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank OO OO OO OO OO OO OO OO LU GALA OO Wo OO OO U OO GA GA GA W Wo UL Wo LU GA OO GA GA GA GA WWW WWW OW W GA GA GA L y y y L L ly y Y Y y y L ly W Y uu Fron
17. LVCMOS33 0 8 SLOW FPGA_OE lt 32 gt M6 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 33 gt H3 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 34 gt C4 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 35 gt G4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 36 gt G3 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 37 gt K3 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 38 gt J4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 39 gt T4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 40 gt D4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 41 gt K4 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 42 gt F7 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 43 gt F9 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 44 gt E5 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 45 gt E6 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 46 gt J6 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 47 gt G8 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 48 gt K6 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 49 gt H8 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 50 gt M8 OUTPUT LVCMOS33 3 8 SLOW TXMC633 User Manual Issue 1 0 1 Page 41 of 71 TEWSS TECHNOLOGIES FPGA OE lt 51 gt tt F14 OUTPUT LVCMOS33 3 8 SLOW FPGA 0E lt 52 gt G11 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 53 gt H14 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 54 gt B18 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 55 gt C19 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 56 gt G9 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 57 gt H10 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 58 gt A17 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 59 gt A18 OUTPUT LVCMOS33 0 8 SLOW FPGA 0E lt 60 gt
18. The User JTAG Chain is accessible from the JTAG Header or from the Debug Connector These interfaces are connected in parallel so only one connection should be made to avoid signal contentions possible hardware damage For direct FPGA configuration FPGA read back or in system diagnostics with ChipScope the JTAG Header can be used to access the JTAG chain Also an indirect SPI PROM programming is possible via JTAG Chain Figure 7 3 User JTAG Chain The TEWS Factory JTAG Chain is accessible from the XMC P15 connector L LOMXOP XIC2001I PI709X2G404 Figure 7 4 TEWS Factory JTAG Chain TXMC633 User Manual Issue 1 0 1 Page 31 of 71 TEWSS TECHNOLOGIES 7 4 5 Programming User FPGA SPI Configuration Flash For programming the User FPGA SPI Configuration Flash the User FPGA Configuration Mode must be set to Master Serial SPI and the ISP Mode must be enabled The following procedure is required for User FPGA SPI Configuration Flash programming and subsequent reconfiguration of the User FPGA Enable then ISP Mode in the ISP Mode Enable Register Set ISP ENA 1 y Assure that User FPGA Configuration Mode is set to SPI Flash Set FP_CFG_MD 0 y Read Config Data f Read Configuration data from Configuration File and write Data to Config File and e the In Circuit Programming Data Space 256Byte 1 SPI Flash Write config data to
19. Vi J3 RASH CASH K22 SSTL15 II 49 90 Vi K3 CASH WER K19 SSTL15 II 49 90 Vi L3 WER CS 100Q GND L2 CSi RESET H18 LVCMOS15 4 7kQ GND T2 RESET CKE F21 SSTL15 II 4 7kQ GND K9 CKE ODT J22 SSTL15 II 49 90 Vi K1 ODT DQO R20 SSTL15 II ODT E3 DQO DQ1 R22 SSTL15 II ODT F7 DQ1 DQ2 P21 SSTL15 II ODT F2 DQ2 TXMC633 User Manual Issue 1 0 1 Page 45 of 71 TEWSS TECHNOLOGIES Signal DDR I O Standard Termination Memory Device SS 3 Pin Name Pin DQ3 P22 SSTL15_ll ODT F8 DQ3 DQ4 L20 SSTL15_ll ODT H3 DQ4 DQ5 L22 SSTL15 II ODT H8 DQ5 DQ6 M21 SSTL15 II ODT G2 DQ6 DQ7 M22 SSTL15 II ODT H7 DQ7 DQ8 T21 SSTL15 II ODT D7 DQ8 DQ9 T22 SSTL15 II ODT C3 DQ9 DQ10 U20 SSTL15 II ODT C8 DQ10 DQ11 U22 SSTL15 II ODT C2 DQ11 DQ12 W20 SSTL15 II ODT A7 DQ12 DQ13 W22 SSTL15 II ODT A2 DQ13 DQ14 Y21 SSTL15 II ODT B8 DQ14 DQ15 Y22 SSTL15 II ODT A3 DQ15 LDQS N20 DIFF SSTL15 II ODT F3 LDQS LDQS N22 DIFF SSTL15 II ODT G3 LDQSH UDQS V21 DIFF SSTL15 II ODT C7 UDQS UDQS V22 DIFF_SSTL15_Il ODT B7 UDQS LDM N19 SSTL15 II ODT E7 LDM UDM P20 SSTL15 II ODT D3 UDM CK K20 DIFF SSTL15 II 1000 J7 CK CK L19 DIFF SSTL15 II K7 CK RZQ F18 SSTL15 II 100Q GND ZIO P19 SSTL15 II open Table 7 8 DDR3 SDRAM Interface For details regarding the DDR3 SDRAM interface please refer to the DDR3 SDRAM Data Sheet and the Xilinx UG388 Spartan 6 FPGA Memory Controller User Guide
20. direct SeleciMap FPGA or SPI Flash programming Must be set to 0 when the User FPGA should configure from the SPI Flash e g after SPI Flash programming in Master Serial SPI mode Note that for ISP Direct FPGA Programming the FPGA must first be set to Slave SelectMap configuration mode RW 0 Table 5 4 ISP Control Register 5 2 5 ISP Command Register 0xE8 Bit Symbol Description Reset Access Value 31 2 Reserved 1 ISP_SPI_RST_CMD ISP SPI Reset Command Bit Writing a 1 sets the Instruction Busy Bit in the ISP Status Register if not already set Breaks any ISP SPI instruction in progress and resets the ISP SPI logic Check the Instruction Busy Bit in the ISP Status Register for reset done status Always read as 0 RW 0 ISP SPI Start Instruction Command Bit Writing a 1 sets the SPI Instruction Busy Bit in the ISP Status Register and starts the configured 0 ISP SPI INS CMD SPI instruction Ignored lost while the Instruction Busy Bit is set in the ISP Status Register Always read as 0 RW 0 Table 5 5 ISP Command Register SPI TXMC633 User Manual Issue 1 0 1 Page 18 of 71 5 2 6 ISP Status Register OxEC TEWSS TECHNOLOGIES Bit 31 2 Symbol Description Reserved Reset Value 0x00 0000 Access ISP SPL INS BSY ISP SPI Instruction Busy Status Set amp Cleared automatic
21. ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne ne PE CE ER GE GT E ot urt st Et GR stork stut ce ER GE EE AR tut GP OR GR et EE ut ot E EE SE EE ER tt At ot EE OR ET At GT ut GE ER ict oct ct CE ZE EE CR och ut rust dr EE ct dt urt stut OR GR utt ER ut ft A FS NG NG VG Vg PG SG FN E Et FG SG GN MG EE FG FG MGE PG ko Mezi Si e ke a a Sc P PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA OE PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO PGA IO 14 IS 16 7 18 19 20 21 22 23 24 25 26 27 28 29 30 Sch 32 34 35 36 37 39 40 41 42 43 44 45 46 47 48 49 50 SI 52 53 54 55 56 97 58 59 60 61 63 o JO DWNL OH DNHHHHHHHHHHO POOOIAUISWNEoO LOC LOC LOC LOC LOC LOC LOC LOC LOC
22. page each time can be programmed maximum BE 7 Space vr Write SPI Address t Set the programming start address and write instruction in the ISP ISP SPI ADD j Configuration Register y Write SPI Instruction to ISP_SPI_INS y Start Instruction with Start the Instruction with ISP Command Register ISP SPI INS CMD 1 y Read ISP Status 4 Register Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for next write instruction Instruction Busy yes no Process should be repeated until all configuration data is written to End of Fle the SPI Flash e After completion the data programming the ISP Mode bit must cleared to set configuration path to User FPGA and a a ra et ISP ENA 0 Reconfiguration could be released A successful configuration of the User FPGA is indicated with FP DONE STAT in the User FPGA Configuration Control Status Register and the on board User FPGA Done LED Programming Instruction always starts at address 0x00 to write data from ISP Programming Data Space to SPI flash If not all configuration data bytes are written the User FPGA is not configured correctly TXMC633 User Manual Issue 1 0 1 Page 32 of 71 TEWSS TECHNOLOGIES As a source for the User FPGA SPI Configuration Flash data should the mcs file This file format can be created from the Dit file by using the XILINX IMPACT or PROMGen software Besides the pure configuration data the mcs file format includes SPI Flas
23. signals are driven Valid signals are driving zero for low level and for high level the line must be set to High Z CNT Lines 1 O Lines Description Spartan6 Pins IO PULL 7 6 IO 48 10_63 9677 pull down R16 R15 IO PULL 5 4 IO 31 10 47 ObZO pull up to 3 3V M18 M17 IO PULL 3 2 IO 16 10 30 0b0Z pull up to 5V P16 N16 G PULL 16 00 lo is 09900 pul upor puldown T20 U19 Table 7 12 I O Pull Configuration An additional option of setting the l O Pull Configuration offers the Configuration FPGA Using the User FPGA Configuration Control Status Register the control can be taken to the Configuration FPGA Use the l O Pull Resistor Configuration Register of the Configuration FPGA to set the wanted pull voltage TXMC633 User Manual Issue 1 0 1 Page 50 of 71 TEWSS TECHNOLOGIES 7 11 User GPIO The TXMC633 has some general purpose l O and debug signals connected to User FPGA Bank 1 The required signaling standard is LVCMOS15 due to Memory Controller Block usage Two pins of the FPGA are routed to the Debug Connector for use as debug interface UART This is not a real RS 232 interface A RS 232 transceiver or USB UART that can work with 1 5V I O voltage should connect to these signals such as TEWS TA900 A general purpose l O Signal is also connected to the Debug Connector When used with the TEWS TA900 this signal is connected to a Push button and must be configured as FPGA input Al
24. to Pins MGTO 101 MGTTX B6 A6 used for PCI Express MGTRX D7 C7 Endpoint Block MGT1 101 MGTTX B8 A8 connected to XMC P16 MGTRX D9 C9 MGTO 123 MGTTX B14 A14 connected to XMC P16 MGTRX D13 C13 MGT1_123 MGTTX B16 A16 connected to XMC P16 MGTRX D15 C15 Table 7 3 MGT Connections The MGT clock MGTO 101 PCI Express Endpoint Block clock reference of 125 MHz is generated by the S15338 low jitter clock generator The MGTO 123 is connected directly to the PCle Switch PI7C9X2G4048 reference clock MGT1 101 and MGT1 123 are not used on the TXMC633 GTP Signal FPGA Connected to Pins MGTO 101 MGTREFCLK A10 B10 125 MHz derived 515338 clock generator MGT1 101 MGTREFCLK C11 D11 not connected MGTO 123 MGTREFCLK A12 B12 100 MHz from PCle Switch MGT1_123 MGTREFCLK E12 F12 not connected Table 7 4 Multi Gigabit Transceiver Reference Clocks TXMC633 User Manual Issue 1 0 1 Page 26 of 71 TEWSS TECHNOLOGIES 7 4 User FPGA Configuration The Spartan6 could be configured by the following interfaces e Master Serial SPI Flash Configuration Interface e JTAG Interface via JTAG Header or TEWS Debug connector e PCle Interface via MachXO2 Configuration FPGA Slave Select Map Interface Configuration The change of the configuration mode is done with a configuration register of the MachXO2 FPGA At Power up the TXMC633 Spartan 6 FPGA always configures via x4 SPI Interface by
25. 06 46 BACK 1022 15 BACK 107 47 BACK 1023 16 BACK 107 48 BACK 1023 17 BACK 108 49 BACK 1024 18 BACK 108 50 BACK 1024 19 BACK 109 51 BACK 1025 20 BACK 109 52 BACK 1025 21 BACK 1010 53 BACK 1026 22 BACK 1010 54 BACK 1026 23 BACK 1011 55 BACK 1027 24 BACK 1011 56 BACK 1027 25 BACK 1012 57 BACK 1028 26 BACK 1012 58 BACK 1028 27 BACK 1013 59 BACK 1029 28 BACK 1013 60 BACK 1029 29 BACK 1014 61 BACK 1030 TXMC633 User Manual Issue 1 0 1 Page 61 of 71 Pin differential Pin differential UO I O 30 BACK 1014 62 BACK 1030 31 BACK 1015 63 BACK 1031 32 BACK 1015 64 BACK 1031 TEWSS TECHNOLOGIES Figure 10 2 Pin Assignment P14 Back I O Connector TXMC633 10 4 P16 Back I O Connector 10 4 1 Connector Type Pin Count 114 Connector Type XMC Connector 114 pol Male Source amp Order Info K39400885 Samtec ASP 105885 01 10 4 2 Pin Assignment NA A B D E F 1 Tx 0 Tx 0 Tx 1 Tx 1 2 GND GND GND GND 3 Tx 2 Tx 2 4 GND GND GND GND 6 GND GND GND GND 7 8 GND GND GND GND 9 Reserved Reserved Reserved Reserved 10 GND GND GND GND 11 Rx 0 Rx 0 Rx 1 Rx 1 12 GND GND GND GND 13 Rx 2 Rx 2 14 GND GND GND GND 15 z 16 GND GND GND GND 17 18 GND GND GND GND e 19
26. 14 D IO 16 IO 18 IO 20 IO 22 IO 24 IO 26 IO 28 IO 30 IO 32 IO 34 IO 36 IO 38 IO 40 IO 42 IO 44 IO 46 D IO 48 IO 50 IO 52 IO 54 IO 56 1058 10 29A 1058 1060 10 30a 1060 67 1061 10 30B 10 61 34 1062 X1 Al X2 x4 Pin X0 X1 X3 GND 43 GND GND GND IO 31A IO 62 68 IO 63 IO 31B X2 x4 e 10_3B IO 4B 105B 106B IO 7B IO 8B 10 9B IO 10B IO 11B IO 12B IO 13B IO 14B IO 15B IO 33 IO 35 IO 37 IO 39 IO 41 IO 43 IO 45 IO 47 GND IO 49 IO 51 IO 53 IO 55 IO 57 IO 59 IO 29B IO 59 IO 63 Table 10 1 Pin Assignment Front Panel I O Connector X1 TXMC633 User Manual Issue 1 0 1 Page 60 of 71 TEWSS TECHNOLOGIES 10 3 Back I O XMC Connector P14 10 3 1 Connector Type Connector Type 64 pol Mezzanine SMD Connector Source amp Order Info Molex 71436 2864 or compatible 10 3 2 Pin Assignment Pin differential Pin differential I O I O 1 BACK 100 33 BACK 1016 2 BACK 100 34 BACK 1016 3 BACK 101 35 BACK 1017 4 BACK 101 36 BACK 1017 5 BACK 102 37 BACK 1018 6 BACK 102 38 BACK 1018 7 BACK 103 39 BACK 1019 8 BACK 103 40 BACK 1019 9 BACK 104 41 BACK 1020 10 BACK 104 42 BACK 1020 11 BACK 105 43 BACK 1021 12 BACK 105 44 BACK 1021 13 BACK 106 45 BACK 1022 14 BACK 1
27. 2 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 5 gt Y3 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 6 gt U1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 7 gt V3 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 8 gt U3 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 9 gt N3 OUTPUT LVCMOS33 3 8 SLOW TXMC633 User Manual Issue 1 0 1 Page 40 of 71 TEWSS TECHNOLOGIES FPGA_OE lt 10 gt N6 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 11 gt P8 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 12 gt R7 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 13 gt M2 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 14 gt G1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 15 gt D3 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 16 gt RI OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 17 gt T3 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 18 gt P5 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 19 gt U4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 20 gt H4 OUTPUT LVCMOS33 3 8 SLOW FPGA OE lt 21 gt tt J7 OUTPUT LVCMOS33 3 8 SLOW FPGA OE lt 22 gt tt P4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 23 gt T6 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 24 gt N7 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 25 gt R4 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 26 gt G13 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 27 gt F17 OUTPUT LVCMOS33 0 8 SLOW FPGA_OE lt 28 gt H1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 29 gt El OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 30 gt D2 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 31 gt B3 OUTPUT
28. 4 I O Lines are divided into four groups which can be configured as 3 3V pull up 5V pull up or pull down In addition the Pull Resistors can float If the Pull Resistors float the user should keep in mind that the 16 I O Lines of the group are connected via their Pull Resistors The default adjustment is that the USER FPGA code must control the I O Pull Configuration depending on USER FPGA UO Function see also chapter I O Pull Configuration TXMC633 User Manual Issue 1 0 1 Page 21 of 71 TEWSS TECHNOLOGIES 5 2 10 TXMC633 Serial Number OxF8 Reset Bit Symbol Description Access Value The value is the unique serial number of each r 31 0 S NUMBER TXMC633 module Table 5 10 TXMC633 Serial Number Example 0x008F DDOF gt SNo 9428239 The serial number can also be read via an I2C interface from Spartan6 5 2 11 MachXO2 FPGA Code Version 0xFC spe Reset Bit Symbol Description Access Value The value shows the MachXO2 FPGA Firmware r an PODE NE code version of the TXMC633 module Table 5 11 MachXO2 FPGA Code Version Example 0x0000_0100 gt bit 32 downto 24 reserved 0x0000_0100 gt bit 23 downto 16 Major FPGA Code Version 0x0000_0100 gt bit 23 downto 16 Minor FPGA Code Version TXMC633 User Manual Issue 1 0 1 Page 22 of 71 TEWSS TECHNOLOGIES 6 Interrupts 6 1 Interrupt Sources 6 1 1 User FPGA Spartan6 The FPGA in
29. 7 gt A5 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 38 gt F5 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 39 gt H6 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 40 gt C5 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 41 gt K5 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 42 gt F8 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 43 gt F10 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 44 gt H5 IN OUT LVCMOS33 3 8 SLOW FPGA 10 lt 45 gt tt G6 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 46 gt G7 IN OUT LVCMOS33 3 8 SLOW FPGA 10 lt 47 gt tt K7 IN OUT LVCMOS33 3 8 SLOW FPGA 10 lt 48 gt tt L6 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 49 gt M7 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 50 gt H11 IN OUT LVCMOS33 3 8 SLOW FPGA_10 lt 51 gt F15 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 52 gt H12 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 53 gt E16 IN OUT LVCMOS33 0 8 SLOW FPGA 10 54 G16 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 55 gt D19 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 56 gt K8 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 57 gt H13 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 58 gt G15 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 59 gt P7 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 60 gt F16 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 61 gt A19 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 62 gt N4 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 63 gt P3 IN OUT LVCMOS33 3 8 SLOW FPGA_OE lt 0 gt Ni OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 1 gt M1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 2 gt Y1 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 3 gt V2 OUTPUT LVCMOS33 3 8 SLOW FPGA_OE lt 4 gt Y
30. 71 TEWSS TECHNOLOGIES 7 4 7 Sector Erasing User FPGA SPI Configuration Flash For Sector Erasing the User FPGA SPI Configuration Flash the User FPGA Configuration Mode must be set to Master Serial SPI and the ISP Mode must be enabled Enable then ISP Mode in the ISP Mode Enable Register egg at Y Assure that User FPGA Configuration Mode is set to SPI Flash Set FP CFG MD 0 Y e i i i i Write SPI Address to Write Sector Address to the ISP Configuration Register ISP SPI ADD L y Set the Chip Erase instruction in the ISP Configuration Register Write SPI Instruction to ISP SPI INS Y Start Instruction with Start the Instruction with ISP Command Register ISP SPI INS CMD 1 y Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for Read ISP Status a Register erasing process end Instruction Busy ye no Process could be repeated for other sectors After completion the erasing process the ISP Mode bit should be Set soia cleared to set configuration path to User FPGA or a User FPGA SPI SR EN Configuration Flash programming process could be done TXMC633 User Manual Issue 1 0 1 Page 34 of 71 TEWSS TECHNOLOGIES 7 4 8 Reading User FPGA SPI Configuration Flash For Reading the User FPGA SPI Configuration Flash the User FPGA Configuration Mode must be set to Master Serial SPI and the ISP Mode must be enabled
31. AE 46 FE E AE AE FE FE 46 46 AE FE FE FE AE AE FE AE FE E AE e FE AE EH FE tt EE dt Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank pannan nn n H PEHHHH H E w Group Group Group Group Group Group Group Group 0 0 16 16 32 32 48 48 15 15 31 31 47 47 63 63 PCI Express Reset AE AE AE AE EEE BF E AE AE AE AE AE AE AE AE AE AE AE AE FE AR BF Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank panpan n Input Debug Debug Debug Debug Debug Only Connector Connector Connector Connector Connector X3 X3 X3 X3 x3 TXMC633 User Manual Issue 1 0 1 Page 71 of 71
32. BACK TO BACK CO BACK IO BACK IO BACK IO BACK IO BACK TO BACK TO BACK 10 BACK IO BACK IQ BACK IO BACK IO BACK IO BACK TO BACK 10 BACK TO BACK IO BACK IO BACK IO BACK IO 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 38 40 41 42 43 44 45 46 47 48 49 50 31 52 53 54 55 56 57 58 59 60 61 62 63 U U pon U a vo Oo A AO UD BWWNNHHOO U U U U U PRPRPRPRPRPRPRPRER Oo BBWONNHHOO LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC M4 AGUS TELE por DIT DLE NRO DI A2 MES EST ga E4 Da AA TAG Ms P5 HE TEET KO w FQ FLO VEST GE GT KT Lo M7 HIL FLIS WHT OM ELG ELEV DL 1KO HLIST GLS p7 FIG VALG Nan p3 AAA ABA We WGN SEIT U6 VE AB7 V7 W8 DAB AB8 TTO Ue RITI RE TEOT AB9 yan vg AA10 AB10 w10 TYTO ELOT DG Bt vil AB11 vii W11 de de de SE SE de de SE de FE SE de GE Sik Sik Se
33. CI Bridge 0x06h to indicate device as Bridge device Ox104C 0x8240 0x060400 PCI bridge Texas Instruments XIO2001 Texas 0x04h to indicate device as PCI to PCI Bridge Instruments 0x06h to indicate device as Bridge device XC6SLX45T 2 user defined Device identification for the User ak programmable FPGA is defined by user The data will be created with the Spartan 6 PCI XC6SLX100T 2 Express Endpoint block generation 0x1498 0x9279 0x068000 Bridge Device TEWS Technologies GmbH LCMXO2 TEWS Device 9279 TXMC633 Table 4 1 On Board PCle PCI Devices TXMC633 User Manual Issue 1 0 1 Page 12 of 71 4 1 User FPGA Spartan6 TEWSS TECHNOLOGIES The User FPGA address map depends on the user application and is not part of this target specification 4 2 Configuration FPGA MachXO2 4 2 1 PCI Configuration Registers PCR PCI CFG Write 0 to all unused Reserved bits PCI Initial Values Register writeable Hex Values Address a 24 23 16 15 8 7 0 0x00 Device ID Vendor ID N 9279 1498 0x04 Status Command Y 0480 000B 0x08 Class Code Revision ID N 068000 01 0x0C BIST Header Type PCI Latency Cache Line Y 7 0 00 00 00 08 Timer Size 0x10 PCI Base Address 0 for Local Address Space 0 Y FFFFFFOO 0x14 PCI Base Address 1 for Local Address Space 1 Y FFFFFFOO 0x18 PCI Base Address 2 for Local Address Space 2 N 00000000 0x1C PCI Base Address 3 for Local Add
34. CK 1011 W10 IN OUT LVDS 33 2 BACK 1011 Y10 IN OUT LVDS 33 2 BACK 1012 T10 IN OUT LVDS 33 2 BACK 1012 U10 IN OUT LVDS 33 2 BACK 1013 Y11 IN OUT LVDS 33 2 BACK 1013 AB11 IN OUT LVDS 33 2 BACK 1014 V11 IN OUT LVDS_33 2 BACK 1014 W11 IN OUT LVDS_33 2 BACK 1015 R11 IN OUT LVDS 33 2 BACK 1015 T11 IN OUT LVDS_33 2 BACK 1016 AA12 IN OUT LVDS_33 2 TXMC633 User Manual Issue 1 0 1 Page 43 of 71 TEWSS TECHNOLOGIES BACK 1016 AB12 IN OUT LVDS_33 2 BACK 1017 W12 IN OUT LVDS 33 2 BACK 1017 Y12 IN OUT LVDS 33 2 BACK 1018 T12 IN OUT LVDS 33 2 BACK 1018 U12 IN OUT LVDS_33 2 BACK 1019 V13 IN OUT LVDS 33 2 BACK 1019 W13 IN OUT LVDS 33 2 BACK 1020 AA14 IN OUT LVDS 33 2 BACK 1020 AB14 IN OUT LVDS 33 2 BACK 1021 W14 IN OUT LVDS 33 2 BACK 1021 Y14 IN OUT LVDS 33 2 BACK 1022 U14 IN OUT LVDS 33 2 BACK 1022 U13 IN OUT LVDS 33 2 BACK 1023 Y15 IN OUT LVDS 33 2 BACK 1023 AB15 IN OUT LVDS 33 2 BACK 1024 AA16 IN OUT LVDS 33 2 BACK 1024 AB16 IN OUT LVDS 33 2 BACK 1025 Y16 IN OUT LVDS 33 2 BACK 1025 W15 IN OUT LVDS 33 2 BACK 1026 U16 IN OUT LVDS 33 2 BACK 1026 V15 IN OUT LVDS 33 2 BACK 1027 T15 IN OUT LVDS 33 2 BACK 1027 U15 IN OUT LVDS 33 2 BACK 1028 Y17 IN OUT LVDS 33 2 BACK 1028 AB17 IN OUT LVDS 33 2 BACK 1029 AA18 IN OUT LVDS 33 2 BACK 1029 AB18 IN OUT LVDS 33 2 BACK 1030 W17 IN OUT LVDS 33 2 BACK 1030 Y18 IN
35. E SE SE SE SE SE FE SE SR GE GE SE SE SE SE FE SE SR SE GE SR GE SE SE sik SE Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank LA GA OO OO 4 OO OO OO L L LU GA GA DO 0 Wo L Lo 0090 LL DOG AO OO OW NNNNNNNPENNPNNNNNNNENNNNNNNNNNNNNN ON Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron Fron PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC T O O T O 1 0 T O 1 0 T O 1 0 T O 1 0 T O T O 1 0 T O O T O 1 0 T O T O O T O O T O 1 0 T O 1 0 T O 1 0 T O T O 1 0 T O 1 0 T O 1 0 T O 1 0 T O 1 0 T O 1 0 GE EE EE tert GE RR i E ee E Rc E E EE EE EE EE GE GE GE EE E EE GE GE a eE EE ER ER GE al GE GEI GE EI Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back B
36. G bit of the User FPGA Configuration Control Status Register to 0 y Reading FP_DONE_STAT Assure that the FPGA DONE Pin status shows a successful FPGA Configuration 0 FPGA DONE Pin Level is Low FPGA is not configured 1 FPGA DONE Pin Level is High FPGA is configured yes H Set S6_LINK_ENA 1 The link between the PCle Switch and the Spartan6 must be enabled A successful User FPGA configuration is indicated with FPGA_DONE status in the Global Status Register and the on board User FPGA Done LED It must be considered in any case that the Re configuration of the User FPGA also Re configure the PCle Endpoint of the User FPGA This has the consequence that the PCI Header of User FPGA PCle Endpoint is no longer exists For this purpose it is necessary to disable the link between the PCle switch and the User FPGA PCle Endpoint and enable after Re configuration Addition after Re Configuration the User FPGA PCle Endpoint the PCI Header must be configured again If the PCIe interface of the User FPGA PCle Endpoint does not change Device ID Vendor ID Class Code and PCI bars do not change the PCI header could be saved before the Re configuration and written back to configuration space after the Re configuration TXMC633 User Manual Issue 1 0 1 Page 28 of 71 TEWSS TECHNOLOGIES 7 4 3 Slave Select Map Configuration For direct User FPGA configuration via PCle Interface the User FPGA Configu
37. IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 11 gt H2 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 12 gt K1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 13 gt J1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 14 gt F1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 15 gt B1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 16 gt T2 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 17 gt R3 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 18 gt T5 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 19 gt V5 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 20 gt L4 IN OUT LVCMOS33 3 8 SLOW FPGA_10 lt 21 gt M3 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 22 gt M4 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 23 gt A3 IN OUT LVCMOS33 0 8 SLOW FPGA 10 lt 24 gt tt C1 IN OUT LVCMOS33 3 8 SLOW FPGA 10 lt 25 gt tt B2 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 26 gt D17 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 27 gt D18 IN OUT LVCMOS33 0 8 SLOW FPGA_lO lt 28 gt K2 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 29 gt D1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 30 gt A2 IN OUT LVCMOS33 0 8 SLOW FPGA_10 lt 31 gt F3 IN OUT LVCMOS33 3 8 SLOW FPGA_10 lt 32 gt E3 IN OUT LVCMOS33 3 8 SLOW TXMC633 User Manual Issue 1 0 1 Page 39 of 71 TEWSS TECHNOLOGIES FPGA_10 lt 33 gt J3 IN OUT LVCMOS33 3 8 SLOW FPGA_10 lt 34 gt E4 IN OUT LVCMOS33 3 8 SLOW FPGA 10 lt 35 gt tt D5 IN OUT LVCMOS33 0 8 SLOW FPGA_10 lt 36 gt A4 IN OUT LVCMOS33 0 8 SLOW FPGA_10 lt 3
38. Initial Version Comments none E SE de de SE dh SE de de SE de de de GE SE SE FE H Section Miscellaneous Set VCC aux power supply values necessary for Spartan 6 architecture config vccaux 3 3 Additional Bank Supply Information find below Bank No Supply 0 3 3V 1 1 5V 2 3 3v 3 JIN Prohibit usage of pins that are not allowed for user I 0 dd tt TEWS TECHNOLOGIES E AAA AAA PP aE EE EE EH a EE EE EEE ER EEE HAE a A Project Name TMXC633 UCF File Name tmxc633 ucf Target Device XC6SLXxxT xFGG484 Design Tool Xilinx ISE Design Suit Embedded 14 7 Description The file lists all FPGA pins that are connected on the TXMC633 dd de E A A A E de A AA A A A A A A A A A A E A A A A 3 HORSE RR EHR REE EHR RAE EHR ARETE RAE EH RAE ER EEE F AE AE AE E AE AE AE FE HR RRR AE EH HAE TH HAE EE FE E AE E ER AAT GE config prohibit Y20 Bank 2 CCLK config prohibit AA21 Bank 2 FPGA_MO config prohibit TELE Bank 2 FPGA_M1 config prohibit AB20 Bank 2 MOSI MISOO CSI B config prohibit AA20 Bank 2 DO MISOL config prohibit R13 Bank 2 D1 MISO2 config prohibit T14 Bank 2 D2 MISO3 config prohibit AA6 Bank 2 FPGA_D3 config prohibit AB6 Bank 2 FPGA_D4 config prohibit Y5 Bank 2 FPGA_D5 config prohibit AB5 Bank 2 FPGA D6 config prohibit W9 Bank 2 FPGA D7 config prohibit Y8 Bank 2 FPGA_RDWR_B TXMC633 User Ma
39. Lines XC6SLX100T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 User Manual Issue 1 0 1 TEWSS TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with amp following i e IP RESETH Access terms are described as W Write Only R Read Only RW Read Write R C Read Clear R S Read Set 2015 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 71 TEWSS TECHNOLOGIES Issue Description Date 1 0 0 Initial issue December 2014 1 0 1 Changes in the BCC firmware and also changes in the process April 2015 description TXMC633 User Manual Issue 1 0 1 Page 3 of 71 TEWSS TECHNOLOGIES Table of Contents T PRODUCT DESCRIPTION WE 8 2 TECHNICAL SPECIFICATION o ccoo Eug 9 3 HANDLING AND OPERATIO
40. N INSTRUCTION ii 11 Sd ESD Protection sta std eee lid 11 3 2 Themmal Considerations i leiiainaii op ak mn an n kk SEENEN SES 11 33 Assembling Melu CEET 11 A PCIDEVICE TOPOLOGY aussi a a ka kk 12 41 User FPGA Spartan6 ccoo o iii 13 4 2 Configuration FPGA MachXO2 e rre rra ENNEN 13 4 2 1 PCI Configuration Registers DCH 13 4 2 2 PCI BAR OLENE cnn crm 13 4 2 2 1 Local Configuration Register Space nn anna nana cnc narran nnnnccna 14 4 2 2 2 In System Programming Data Space seara ereranarra narrar 15 5 REGISTER DESCRIPTION 16 A 16 52 Gonfiguration dl CT E 16 5 2 1 User FPGA Configuration Control Status Register OxDO i 16 5 2 2 User FPGA Configuration Data Register 0xD4 i 17 5 2 3 ISP Configuration Register ONEA errar aaaaaareeaaaera near nanaanaa 17 5 2 4 ISP Control Register 0xEO i 18 5 2 5 ISP Command Register 0xEB i 18 5 2 6 ISP Status Register ONE 19 5 2 7 Interrupt Enable Register OXCO reter aer arar rre rre rn 19 5 2 8 Interrupt Status Register OXC4 rn 20 5 2 9 I O Pull Resistor Configuration Register 0xF4 rata 21 5 2 10 TXMC633 Serial Number OXF8 i 22 5 2 11 MachXO2 FPGA Code Version ONE 22 G INTERRUPTS inci ii 23 61 Interrupt SOUIces asia ni
41. OCKINO EE 38 7 5 1 FPGA Clock Tee 38 O Erontl O Interface lui it 39 LT Baciol O Hun EE 43 K MEMON POPE gian 45 7 8 1 DDR3 SDRAM uil iaia 45 7 8 2 SPRF ASI kek kas dwa od dad ia 47 7 9 Serial Number Allocationi iini iii 48 7 9 1 Device Addressing and Operation 48 7 9 2 Read Opera iii is iia acid 49 7 9 3 Write Operativa a a ir 49 7 10 VO Pull Configuration EE 50 FT USO GPIO RE 51 7 12 On Board Indicators coin enel 52 7 13 Thermal Management c ccceeccceeeeeeeseeeeeseseeneeseseeneeseseeneeseseneeeseseeneeseseeneeseseeneesaseeneeseseeneeenseenens 53 8 DESIGN HELP cca 54 3 1 Example DESION sisien ennai on dok AD AOne 54 9 INSTALLATION cl 55 931 Ire tun E 55 9 1 1 TTL WO Blut 55 9 1 2 Differential I O Interface aaanssssaaasosssanooossasaanosssanososasonn 56 9 1 3 Back VO Interface vwaw ka eka j af a kal diia indicada 56 92 FPGA Debug Connector eke ei kaka not tb e piti pa pin mn ab ki ko ia kn kl ko n ki aa on akne kn pan bk EES 57 9 2 1 Connecting TA900 to TXMC633 Debug Connector iii 57 93 FPGAJTAG Connector oi rana EES See 58 10 PIN ASSIGNMENT UO CONNECTOR ennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 59 DOLD Overview rocio ira 59 10 2 X1 Front Panel I O Connector momia 59 10 21 Connector Type sia aia 59 10 22 PiInAssignment sagaer eee 60 10 3 Back I O XMC Connector P14 rnnsrnnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnvennnnnnnnnnnn
42. OUT LVDS 33 2 BACK 1031 V17 IN OUT LVDS_33 2 BACK 1031 W18 IN OUT LVDS 33 2 Table 7 7 Digital Back I O Interface TXMC633 User Manual Issue 1 0 1 Page 44 of 71 TEWSS TECHNOLOGIES 7 8 Memory The TXMC633 is equipped with a 128 Mbytes 16 bit wide DDR3 SDRAM and a 32 Mbit non volatile SPI Flash The SPI Flash can also be used as configuration memory 7 8 1 DDR3 SDRAM The TXMC633 provides a MT41 96 ball DDR3 memory device The memory is accessible through the Memory Controller Block hard IPs in bank 1 of the Spartan 6 FPGA The memory component s CS is fixed to GND The address bits A14 and A13 are memory address expansion bits Signal DDR I O Standard Termination Memory Device pon Ge Pin Name Pin AO H21 SSTL15 II 49 90 Vi N3 A0 AI H22 SSTL15 II 49 90 Vi P7 AI A2 G22 SSTL15 II 49 90 Vi P3 A2 A3 J20 SSTL15 II 49 90 Vi N2 A3 A4 H20 SSTL15 II 49 90 Vi P8 A4 A5 M20 SSTL15 II 49 90 Vi P2 A5 A6 M19 SSTL15 II 49 90 Vit R8 A6 A7 G20 SSTL15 II 49 90 Vit R2 A7 A8 E20 SSTL15 II 49 90 Vi T8 A8 A9 E22 SSTL15 II 49 90 Vi R3 A9 A10 J19 SSTL15 II 49 90 Vi L7 A10 AP A11 H19 SSTL15 II 49 90 Vi R7 A11 A12 F22 SSTL15 II 49 90 Vi N7 A12 BCN A13 G19 SSTL15 II 49 90 Vo T3 NC A13 A14 F20 SSTL15 II 49 90 Vi T7 NC A14 BAO K17 SSTL15 II 49 90 Vi M2 BAO BA1 L17 SSTL15 II 49 90 Vit N8 BA1 BA2 K18 SSTL15 II 49 90 Vi M3 BA2 RAS K21 SSTL15 II 49 90
43. P GCLK22 3 M5 S15338 low jitter clock USER CLK generator 83 3325 MHz IO L30N GCLKO 2 AB13 S15338 low jitter clock 32 00 MHz Clock Input generator After configuration this clock could be used by FPGA design IO L3ON GCLKO USERCCLK 2 AB13 Configuration FPGA Used for external configuration clock CCLK Table 7 5 Available FPGA clocks TXMC633 User Manual Issue 1 0 1 Page 38 of 71 TEWSS TECHNOLOGIES 7 6 Front I O Interface Each of the 64 digital front IO channels is realized with single ended or differential digital buffers Each channel provides an I O data signal and an output enable signal which is direct connected to the FPGA device The I O channels are accessible through the I O Bank 0 and Bank 3 of the Spartan 6 FPGA The subsequent table lists required I O setting for correct interfacing Signal Name Ku Direction IO Standard IO Bank ER Foie FPGA_lO lt 0 gt P1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 1 gt P6 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 2 gt AA2 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 3 gt Wi IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 4 gt AAT IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 5 gt V1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 6 gt W3 IN OUT LVCMOS33 3 8 SLOW FPGA 10 lt 7 gt tt W4 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 8 gt T1 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 9 gt P2 IN OUT LVCMOS33 3 8 SLOW FPGA_lO lt 10 gt F2
44. PGA JTAG CONNECTOR X2 ion ae 58 FRONT PANEL I O CONNECTOR NUMBERING AA 59 PIN ASSIGNMENT P14 BACK I O CONNECTOR TXMC633 62 PIN ASSIGNMENT P16 BACK I O CONNECTOR TXMC633 XX ie 62 Page 6 of 71 TEWSS TECHNOLOGIES List of Tables TABLE 2 1 TECHNICAL SPECIFICATION ccoccciiconnccniconnr KEE interece anan nansanabonna 10 TABLE 4 1 ON BOARD PCIE PCI DEVICES nono tate aaanaaasenosenoseassaoosanosonososososoononononone 12 TABLE 4 2 PCI CONFIGURATION REGISTERS ereta ereareaeerarnana 13 TABLE 4 3 PCI BAR OVERVIEW corno 13 TABLE 4 4 LOCAL CONFIGURATION REGISTER SPACE ear 14 TABLE 5 1 USER FPGA CONFIGURATION CONTROL STATUS REGISTER esseere 16 TABLE 5 2 ISP SELECT MAP DATA REGISTER qu ee inn crac rra rre rin 17 TABLE 5 3 ISP CONFIGURATION REGISTER noni 17 TABLE 5 4 ISP GONTR L REGISTER cuina e AN 18 TABLE 5 5 ISP COMMAND REGISTER GP 18 TABLE 5 6 ISP STATUS REGISTER coord edi iia 19 TABLE 5 7 INTERRUPT ENABLE REGISTER cnn cenar reir 19 TABLE 5 8 INTERRUPT STATUS REGISTER nono onaaasenoseaosssanssoosanosonosonosonoonononnnone 20 TABLE 5 9 WO PULL RESISTOR CONFIGURATION REGISTER 21 TABLE 5 10 TXMC633 SERIAL NUMBER 22 TABLE 5 11 MACHXO2 FPGA CODE VERSION taa ana asenoseaasssasssnosenosanosonososoononononone 22 TABLE 7 1 TXMC633 FPGA FEATURE OVERVIEW cnn cenar r
45. SDA 1 1 5V P18 Serial Data Table 7 10 User FPGA 12C Interface to Configuration FPGA The Configuration 12C Interface provides only one readable register The Serial Number Register is a 32 bit wide read only register The Slave Address of the Serial Number Register is 061010101 The support frequencies are between 100kHz up to 400kHz Reset Bit Symbol Description Access Value The value is the unique serial number of each r DIO S NUMBER TXMC633 module Table 7 11 TXMC633 Serial Number Example 0x008F DDOF gt SNo 9428239 7 9 1 Device Addressing and Operation The TXMC633 Configuration FPGA uses a standard 7 bit Slave Address The eight bit of the slave address is the Read write operation select bit Ljo 1 0 1 0 1 AM RA MSB LSB Figure 7 6 Configuration FPGA Slave Address TXMC633 Configuration FPFA I2C Slave typically Start and Stop condition Start Stop Figure 7 7 Configuration FPGA Start and Stop condition TXMC633 User Manual Issue 1 0 1 Page 48 of 71 TXMC633 Configuration FPFA I2C Slave Output Acknowledge Figure 7 8 Configuration FPGA Output Acknowledge 7 9 2 Read Operation The TXMC633 Configuration FPGA provides only one 32 bit register which could from User FPGA TEWSS TECHNOLOGIES be read via 12C Interface The read operation starts with a 12C start condition followed by a 7 bit slave address The read write bit in the devi
46. The Embedded I O Company E VVS D TECHNOLOGIES TXMC633 Reconfigurable FPGA with 64 TTL I O 32 Differential I O Lines Version 1 0 User Manual Issue 1 0 1 April 2015 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com TXMC633 10R 64 TTL Front I O and 64 direct FPGA I O Lines XC6SLX45T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 11R 32 Differential Front UO and 64 direct FPGA I O Lines XC6SLX45T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 12R 32 TTL and 16 Differential Front I O and 64 direct FPGA UO Lines XC6SLX45T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 13R 32 Differential M LVDS Front I O and 64 direct FPGA IO Lines XC6SLX45T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 14R 32 TTL and 16 Differential M LVDS Front I O and 64 direct FPGA I O Lines XC6SLX45T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 20R 64 TTL Front I O and 64 direct FPGA I O Lines XC6SLX100T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 21R 32 Differential Front UO and 64 direct FPGA I O Lines XC6SLX100T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 22R 32 TTL and 16 Differential Front I O and 64 direct FPGA I O Lines XC6SLX100T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 23R 32 Differential M LVDS Front I O and 64 direct FPGA I O Lines XC6SLX100T 2 Spartan 6 FPGA 128 MB DDR3 TXMC633 24R 32 TTL and 16 Differential M LVDS Front I O and 64 direct FPGA I O
47. able 5 7 Interrupt Enable Register TXMC633 User Manual Issue 1 0 1 Page 19 of 71 5 2 8 Interrupt Status Register 0xC4 TEWSS TECHNOLOGIES a See Reset Bit Symbol Description Access Value 31 2 Reserved 0 ISP SPI Instruction Done Event Interrupt Status When set the PCI INTA interrupt is asserted 1 ISP INS IS The Interrupt is cleared by writing a 1 R C 0 0 Interrupt not active or disabled 1 Interrupt active and enabled ISP SPI Page Data Done Event Interrupt Status When set the PCI INTA interrupt is asserted 0 ISP_DAT_IS The Interrupt is cleared by writing a 1 R C 0 0 Interrupt not active or disabled 1 Interrupt active and enabled TXMC633 User Manual Issue 1 0 1 Table 5 8 Interrupt Status Register Page 20 of 71 TEWSS TECHNOLOGIES 5 2 9 I O Pull Resistor Configuration Register 0xF4 Bit Symbol Description Access ee 31 8 Reserved 0 7 6 PULL G3 WO Group pull up pull down selecton Value could be changed only if PULL_CNT is set to 5 4 PULL_G2 MachXO2 controlling 00 pull down 3 2 PULL Gi 01 pull up to 3 3V User 10 pull up to 5V FPGA 11 No pull up or pull down RW Pin adjustment 1 O lines are summarized in the following groups ka RE GO 1 0_0 VO 15 G1 I O 16 VO 31 G2 1 0 32 UO 47 G3 10 48 VO 63 Table 5 9 UO Pull Resistor Configuration Register Each TTL I O Line has a 4k7 Pull Resistor The 6
48. ack Back Back Back Back Back Back Back Back X1 X1 X1 X1 X1 x1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 x1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 x1 x1 x1 x1 x1 X1 X1 X1 X1 X1 X1 X1 I O T O 1 0 T O O T O T O T O 1 0 T O 1 0 T O 1 0 T O 1 0 1 0 T O 1 0 T O 1 0 1 0 T O 1 0 T O 1 0 I O T O 1 0 T O 1 0 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 TXMC633 User Manual Issue 1 0 1 Page 68 of 71 TEWSS TECHNOLOGIES net BACK IO P 15 net BACK IO N 15 net BACK IO P 16 net BACK IO N 16 net BACK IO P 17 net BACK IO N 17 net BACK IO P 18 net BACK IO N 18 net BACK IO P 19 net BACK IO N 19 net BACK IO P 20 net BACK IO N 20 net BACK IO P 21 net BACK IO N 21 net BACK IO P 22 net BACK IO N 22 net BACK IO P 23 net BACK IO N 23 net BACK IO P 24 net BACK IO N 24 net BACK IO P 25 net BACK IO N 25 net BACK IO P 26 net BACK IO N 26 net BACK IO P 27 net BACK IO N 27 net BACK IO P 28 net BACK IO N 28 net BACK IO P 29 net BACK IO N 29 net BACK IO P 30 net BACK IO N 30 net BACK IO P 31 net BACK IO N 31 4444 4444 4444444444444 44444 Section DDR3 Memory MCB1 FERRARA
49. ally by HW Includes SPI Flash internal program erase times When clear again after being set a new ISP SPI instruction may be started Capable of generating an event based interrupt 0 No ISP SPI Instruction in Progress 1 ISP SPI Instruction in Progress ISP SPL DAT BSY ISP SPI Data Transfer Busy Status Set amp Cleared automatically by HW Does not include SPI Flash internal program erase times When clear again after being set new SPI Flash page data may be written to the ISP Data Space in program mode or SPI Flash page data is available in the ISP data space in read mode Capable of generating an event based interrupt 0 No ISP SPI Data Transfer in Progress 1 ISP SPI Data Transfer in Progress Table 5 6 ISP Status Register 5 2 7 Interrupt Enable Register 0xC0 Bit Symbol Description Reset Access Value 31 2 ISP INS IE ISP DAT IE Reserved ISP SPI Instruction Done Event Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled Status Register is 0 source ISP SPI Page Data Request Event Interrupt Enable 0 Interrupt Disabled 1 Interrupt Enabled Status Register is 0 source While disabled the corresponding bit in the Interrupt RW 0 Disabling interrupts does not affect the interrupt While disabled the corresponding bit in the Interrupt R W 0 Disabling interrupts does not affect the interrupt T
50. c D15 Bank 123 XMC P16 MGT RX P Lane 3 net MGTRX3_N loc C15 Bank 123 XMC P16 MGT RX_N Lane 3 net FPGA_REFCLK_P oc A12 Bank 123 PCI Express Reference Clock 100 MHz CLK_P via PI7C9X2G404 PCI Express Switch net FPGA_REFCLK_N loc BI2 Bank 123 PCI Express Reference Clock 100 MHz CLK N via PI7C9X2G404 PCI Express Switch FE aE a a aE aE a aE aE A aE HE aE aE aE aE HE aE aE aE HE HE aE aE HE aa aE aE EE aa HE HE aE aE aE aE aE HE Section I O Lines FEAE AE FE EEE REE EH RR TR RARE e EEE EEE EEE E Define I O St net FPGA_OE net FPGA_IO net BACK_IO_P net BACK_IO_N Location Constraints net FPGA OE 0 net FPGA OE 1 net FPGA OE 2 net FPGA OE 3 net FPGA OE 4 net FPGA OE 5 net FPGA OE 6 net FPGA OE 7 net FPGA OE 8 net FPGA OE 9 net FPGA OE 10 net FPGA OE 11 net FPGA OE 12 net FPGA OE 13 andard xy ja ja ja ja iostandard iostandard iostandard iostandard LVCMOS33 LVCMOS33 LVDS 33 LVDS 33 NI M1 Y3 V3 U3 R7 D M2 yin V2 yo Ul D N3 NG pg D Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank Dank NN OO W GA GA uy y ly y y y y ly ly Y Ww w w TXMC633 User Manual Issue 1 0 1 Page 66 of 71 TEWSS TECHNOLOGIES ne ne ne ne ne ne ne ne
51. ce address byte is set to one The configuration FPGA acknowledged the address and began to transmit all four data byte of the TXM633 Serial Number Register Each byte must be acknowledged The sequence must be completed with a stop condition by the User FPGA S T A E Slave Address A A C C K SN lwByte K XO gt A C K UO gt mI S AT CO SNr hight Byte KP PE dl M L S S B B D Figure 7 9 Configuration FPGA Slave Access 7 9 3 Write Operation A 12C write operation is not implemented TXMC633 User Manual Issue 1 0 1 Page 49 of 71 TEWSS TECHNOLOGIES 7 10 1 0 Pull Configuration Each TTL I O Line has a 4k7 Pull Resistor The 64 I O Lines are divided into four groups which can be configured as 3 3V pull up 5V pull up or pull down In addition the Pull Resistors can float If the Pull Resistors float the user should keep in mind that the 16 I O Lines of the group are connected via their Pull Resistors The normal behaviour is that the User FPGA code controls the I O Pull Configuration depending on User FPGA I O Function The User FPGA Spartan6 IO PULL Interface configuration signals are connected via Configuration FPGA to four analog multiplexer With these multiplexers the desired voltage can be adjusted directly from the User FPGA Altogether there are eight controller lines which switch the four analog multiplexer for the I O Pull Voltage The user must therefore always ensure that valid
52. ee 23 6 1 1 User FPGA Spartan6 csi ii treige 23 6 1 2 Configuration FPGA MachXO2 ii 23 DZ Intertupt bierg lge ee 23 6 2 1 User FPGA Spartanb E 23 6 2 2 Configuration FPGA MachXO2 4 seeiatevesi bas se tye ala 23 7 FUNCTIONAL DESCRIPTO Nucia an 24 TA User FPGA Block Diagrammer aaa 24 Ta OSenFPGA aie ERR RR ko oO a a ii 25 7 3 User FPGA Gigabit Transceiver GTP rrnnnnvnnrnnnnvevnnnnnvnnnnnnnvevnnnnnnnvennnnrnnnnnnnnnrennnnnnnennnnnenennnner 26 7 4 User FPGA Configuration rrrnvrnnnnvnnnnnvnnnnvnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 27 7 4 1 Master Serial SPI Flash Configuration nara cnn ran 27 7 4 2 Manually User FPGA SPI Flash Reconfiguration errar 28 7 4 3 Slave Select Map Configuration iii 29 7 4 4 Gonfiguration Via JTA Gis sea teka e kte ok kaka enten veden cotas 31 7 4 5 Programming User FPGA SPI Configuration Flash 32 7 4 6 Erasing User FPGA SPI Configuration Flash 33 7 4 7 Sector Erasing User FPGA SPI Configuration Flash 34 7 4 8 Reading User FPGA SPI Configuration Flash 35 TXMC633 User Manual Issue 1 0 1 Page 4 of 71 TEWSS TECHNOLOGIES 7 4 9 Generate Spartan6 Configuration Data 36 7 4 10 SPI PROM Quad Mode enable ea aaat ta aaat aaa aatassaaaoassaanasosssaaosoessanososssanososasonn 36 714 11 Board G ntiguration FPGA ista pad in vi e aw ia e de ad n a n a kt a pisan kn 37 7 5 CI
53. els TXMC633 x0 64 ESD protected TTL lines TXMC633 x1 32 differential I O lines TXMC633 x2 32 TTL and 16 differential I O lines TXMC633 x3 32 M LVDS I O lines TXMC633 x4 32 TTL and 16 M LVDS I O lines TTL signaling voltage level maximum current 32 mA ElA 422 485 signaling level or M LVDS Standard TIA ElA 899 I O Connector Front UO HD68 SCSI 3 type Connector AMP 787082 7 or compatible PMC P14 I O 64 pin Mezzanine Connector XMC P16 I O 114 pin Mezzanine Connector Physical Data Power Requirements Depends on FPGA design With TXMC633 FPGA Example Design without external load typical O 5V VPWR typical O 12V VPWR TXMC633 xx 0 650 A 0 300 A Temperature Range Operating 40 to 85 C Storage 40 to 85 TXMC633 User Manual Issue 1 0 1 Page 9 of 71 TEWSS TECHNOLOGIES MTBF TXMC633 xx 320000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment Gg 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F Notice 2 formulas are used for FIT rate calculation Humidity 5 95 non condensing Weight TXMC633 xx 1309 Table 2 1 Technical Specification TXMC633 User Manual Issue 1 0 1 Page 10 of 71 3 TEWSS TECHNOLOGIES Handling and Operation Instruction
54. gth and consequently the capacitance of a flat cable connected to the TXMC633 module should be kept as short as possible to prevent large cross talk To reduce the cross talk on the TXMC633 not all 64 I O lines should be switched at the same time For example the output lines should be switched in groups of 8 signals in steps of 12ns meaning that after about 100ns the switching process is completed TXMC633 User Manual Issue 1 0 1 Page 55 of 71 TEWSS TECHNOLOGIES Each I O Line has a 4k7 Pull Resistor These Pull Resistors can be configured as 3 3V pull up 5V pull up or pull down In addition the Pull Resistors can float Based on placement groups are needed for the pull voltage If the Pull Resistors float the user should keep in mind that the I O Lines of one group are connected via their Pull Resistors Pull Resistor configuration must be set with User FPGA code 9 1 2 Differential I O Interface Each of the 32 TXMC633 x1 x3 or 16 TXMC633 x2 x4 differential I O line pairs is realized with an I O and output enable pin at the XILINX FPGA connected to a differential I O Buffer For TXMC633 x1 x2 a MAX3078E an ESD protected RS485 RS422 transceiver and a 1200 termination resistor is provided For TXMC633 x3 x4 a SN65MLVD206 a Multipoint LVDS Line Driver and Receiver and a 1000 termination resistor is provided See the following figure for more information of the differential I O circuitry Figure 9 2 Differe
55. h button on the TEWS TA900 and must be configured as FPGA input Figure 9 3 Debug Connector X3 9 2 1 Connecting TA900 to TXMC633 Debug Connector USB serial FPGA UART A to XILINX Platfrom Cable USB II TXMC633 User Manual Issue 1 0 1 Page 57 of 71 TEWSS TECHNOLOGIES 9 3 FPGA JTAG Connector The FPGA JTAG connector X2 lets the user directly connect a JTAG interface cable to the on board User FPGA JTAG chain e g for FPGA read back and real time debugging of the User FPGA design using Xilinx ChipScope A through hole right angle 90 connector with 7 x 2 pins and 2 mm pitch is mounted Molex 0877601416 or compatible With a mounted 2 mm pitch flat cable this is of cause a violation of the maximum component height given by the CMC specification be sure that there is enough space to carrier board Figure 9 4 FPGA JTAG Connector X2 TXMC633 User Manual Issue 1 0 1 Page 58 of 71 TEWSS TECHNOLOGIES 10 Pin Assignment I O Connector 10 1 Overview 10 2 X1 Front Panel I O Connector Pin 68 Pin 35 Figure 10 1 Front Panel I O Connector Numbering 10 2 1 Connector Type Pincom fe TT Connector Type HD68 SCSI 3 type female connector Source amp Order Info AMP 787082 7 or compatible TXMC633 User Manual Issue 1 0 1 Page 59 of 71 10 2 2 Pin Assignment TEWSS TECHNOLOGIES G G 100 10 0A IO OA IO 10 IO 12 IO
56. h specific configuration data These data are needed to ensure a correct configuration of the User FPGA from the SPI PROM How to generate the mcs file out of bit file by using XILINX IMPACT or PROMGen software please refer to XILINX IMPACT documentation TXMC633 xx User FPGA SPI Configuration device SPI Flash Winbond W25Q32BV 32M Data Width 4 bit or SPI Flash Winbond W25Q32FV 32M Data Width 4 bit 7 4 6 Erasing User FPGA SPI Configuration Flash For Chip Erasing the User FPGA SPI Configuration Flash the User FPGA Configuration Mode must be set to Master Serial SPI and the ISP Mode must be enabled Enable then ISP Mode in the ISP Mode Enable Register SeUisP_ENA 1 Y Assure that User FPGA Configuration Mode is set to SPI Flash Set FP CFG MD 0 Y Set the Chip Erase instruction in the ISP Configuration Register Write SPI Instruction to ISP_SPI_INS Y Start Instruction with Start the Instruction with ISP Command Register ISP_SPI_INS_CMD 1 Y Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for hr lt erasing process end Y Instruction Busy yes no y Set FP_CFG_MD 0 Set ISP ENA 0 After completion the erasing process the ISP Mode bit should be cleared to set configuration path to User FPGA or a User FPGA SPI Configuration Flash programming process could be done TXMC633 User Manual Issue 1 0 1 Page 33 of
57. is is also a binary configuration data file but without header information For configure the Spartan6 FPGA of the TXMC633 both files could be used Both binary configuration data file have addition data to the actual configuration data Two examples are provided here In the bit file the data can be used from the offset 0x000000b0 For the bin file the data can be used starting at offset 0x00000050 Example bit file 0x00000000 00 OF Que OQ D c0 Og 0 OG r0 OG OG OL Gil OO Ze bit file 0x00000010 header 0x00000020 0x00000030 0x00000040 0x00000050 0x00000060 add S6 0x00000070 Config 0x00000080 Data 0x00000090 0x000000a0 0x000000b0 TXMC633 0x000000c0 Config 0x000000d0 Data 0x000000e0 0x000000 0 0x0016aa60 eo Example bin file 0x00000000 add S6 0x00000010 Config 0x00000020 Data 0x00000030 0x00000040 TXMC633 0x00000050 Config 0x00000060 Data 0x00000070 0x00000080 0x0016aa60 BE See also the XILINX User Guide ug380 Spartan6 FPGA Configuration for more information about Configuration Details and Configuration Data File Formats TXMC633 User Manual Issue 1 0 1 Page 30 of 71 TEWSS TECHNOLOGIES 7 4 4 Configuration via JTAG The TXMC633 provides two JTAG chains which are accessible by one of the following connector options User JTAG Chain e 14 pin JTAG Header e Debug Connector TEWS Factory configuration Chain e XMC Connector P15
58. k 1 config probibit F19 Bank 1 DDR3 Reference Voltage config prohibit D22 Bank 1 DDR3 Reference Voltage config prohibit R19 Bank 1 DDR3 Reference Voltage Additional Constratints config mcb performance standard General MCB constraints E dede dak d A ak d 4 a f 4 a cf a af a 4 EEE HEE RHE RHE H Section Clocking dede A ak de ak d 4 a f dt a cf dt a af de a a REE HEHE 4 Rd Ak de Ak A A A A A H I O Standards net MCB CLK iostandard LVCMOS33 Bank 2 net SP6 CLK iostandard LVCMOS33 Bank 2 net USER CLK iostandard LVCMOS33 Bank 3 Location Constraints net SP6 CLK loc AB13 Bank 2 net MCB CLK loc Y13 Bank 2 net USER_CLK loc M5 Bank 3 TXMC633 User Manual Issue 1 0 1 Page 70 of 71 TEWSS TECHNOLOGIES Additional Constraints net SP6 CLK tnm net timespec TS SP6 CLK net MCB CLK tnm net timespec TS MCB CLK net USER CLK tnm net timespec TS USER CLK H 4444444 HE AE HEHE TE HE FE E FE d FE a HE FE E FE TE FE a HEE HEE HEE HEE HEHE HEE Section Module Management E FETE EE AE HE EEE FE E FE RHE RHEE HEE HEE HE EE E E E E EH I O Standards net LL BUS iostandard net PULL IN iostandard net DWNRST2 n iostandard Location Constraints net LL BUS O loc net LL BUS 1 loc net LL BUS 2 OC net LL BUS 3 loc net LL BUS 4 loc net LL BUS 5 loc net
59. k divide 1 To use the maximum data transfer speed of the User FPGA SPI Configuration Flash the SPI Configuration Bus Width must be set to the x4 Set SPI Configuration Bus Width g SPI buswidth 4 Without this option the configuration time for the Spartan6 FPGA exceed the maximum PCIe bus setup time 7 4 10 SPI PROM Quad Mode enable Be due to the required SPI Configuration Bus Width X4 the Quad Mode of the SPI Flash must always be enabled Therefor the SPI Flash on the TXMC633 provides a non volatile register This bit is always programmed during TEWS factory test and programming process The Quad Mode enable bit is non volatile so it is not necessary to re enable this bit every SPI Flash programming process Even when programming the SPI Flash with the Xilinx IMPACT tool this bit is automatically programmed If this bit is not active the Spartan6 FPGA could not be configured from the SPI Flash If this bit be cleared once it can be reprogrammed using the SPI Flash Quad Mode enable instruction Set ISP ENA 1 Enable then ISP Mode in the ISP Mode Enable Register y Set FP_CFG_MD 0 Assure that User FPGA Configuration Mode is set to SPI Flash y Write SPI Instruction Set the SPI Flash Quad Mode enable instruction in the ISP Configuration 0x31 to v Start Instruction with ISP_SPI_INS_CMD 1 Start the Instruction with ISP Command Register y Read ISP Status Register
60. mming mode 31 0 ISP_FP_DAT Must be written with 32 bit FPGA programming data until the FPGA Done pin goes high after the actual programming data writing some dummy data may be required Bit Symbol Description Access Table 5 2 ISP Select Map Data Register The ISP Select Map Data Register is used to write data within the User FPGA Slave Select Map Configuration directly to the User FPGA 5 2 3 ISP Configuration Register OxE4 Bit Symbol Description Access Jure 31 24 SPI Flash Address A A0 w Ox00 23 16 ISP SPI ADD SPI Flash Address A15 A8 w 0x00 15 8 SPI Flash Address A23 A16 w 0x00 SPI Flash Instruction Code w 0x00 Supported Instructions 0x02 Page Program 7 0 ISP SPI INS 0x20 Sector Erase 0x60 Chip Erase 0x03 Read Data 0x31 SPI Flash Quad Mode enable Table 5 3 ISP Configuration Register TXMC633 User Manual Issue 1 0 1 Page 17 of 71 5 2 4 ISP Control Register 0xE0 TEWSS TECHNOLOGIES Bit Symbol Description Reset Access Value 31 1 Reserved 0 ISP EN ISP Mode Enable 0 Disable ISP Mode 1 Enable ISP Mode This bit controls on board analog signal multiplexers for signal connections between the MachXO2 CPLD the User FPGA configuration interface and the on board SPI Flash When set the MachXO2 CPLD is both SPI Flash Master and FPGA Configuration Interface Master Must be set to 1 for
61. nk Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank 5V 5V 5V 5V DV SV SV SV DV DV MV 5V SV DV PRPPRPRPRPRPRPRPRPRPREER NNNNONENNNNNNNNDNNNNNNNNENNNNNNNNNNNNN PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC and Controls Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank 1 PRPPPRPRPRPRP PR Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back Back FE AE AE AE FE RARER AAA EE RAE FE E AE RAE EHH FE AE AE AE FE E AE AE AE FE E AE AE FE FE FE AE TH FE FE AE AE FE FE FE E AE FE AE FE E AE FE AE FE AE AE FE HE O T O 1 0 T O I O O T O 1 0 T O O T O 1 0 T O 1 0 T O 1 0 T O 1 0 T O O T O O T O O O T O 1 0 T O 1 0 I O T O 1 0 T O 1 0 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 P14 HEHE 4 HEHE 4 TXMC633 User Manual Issue 1 0 1 Page 69 of 71 TEWSS TECHNOLOGIES
62. nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnner 61 10 3 1 Connector Type iii enveis 61 1032 Pin ASSIQNMON yo va cases k evil potko oe ridebanen 61 10 4 P16 Back ise dE TEE 62 10 4 1 Connector Type aio iaia 62 ER EE ell aliena ina 62 UE WER ER E E 63 10 5 1 Connector Type EE 63 UK SCHER ell EE 63 10 6 X3 Debug Connector rrrsvvnnnsvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenn 64 10 6 1 Connector Type siii ii 64 10 622 Pin Assignment assessment ici 64 11 APPENDIX ia 65 TXMC633 User Manual Issue 1 0 1 Page 5 of 71 FIGURE 1 1 FIGURE 4 1 FIGURE 7 1 FIGURE 7 2 FIGURE 7 3 FIGURE 7 4 FIGURE 7 5 FIGURE 7 6 FIGURE 7 7 FIGURE 7 8 FIGURE 7 9 FIGURE 9 1 FIGURE 9 2 FIGURE 9 3 FIGURE 9 4 FIGURE 10 1 FIGURE 10 2 FIGURE 10 3 TXMC633 User Manual Issue 1 0 1 TEWSS TECHNOLOGIES List of Figures BLOCK RUE IO 8 PGIE PCLDEVICE TOPOLOGY wee assent dain ent deta 12 FPGA BLOCK DIAGRAM ME 24 GTP BLOCK DIAGRAM fis caia ari 26 USER JTAG CHAIN score delicia 31 TEWS FACTORY JTAG CHAIN cdi 31 WEI Ae eil e 38 CONFIGURATION FPGA SLAVE ADDRESS eee 48 CONFIGURATION FPGA START AND STOP CONDITION 48 CONFIGURATION FPGA OUTPUT ACKNOWLEDGE A 49 CONFIGURATION FPGA SLAVE ACCESS eae 49 GIN EGGE 55 DIFFERENTIALVO INTERFACE viverra ide 56 DEBUG CONNEGTOR X3 sunnier dre akadierne 57 F
63. nterface to the FPGA pins The logic levels of the buffers are TTL compatible meaning that the minimum high level is 2 0V and the maximum low level is 0 8V The nominal output high voltage is 3 3V The buffer outputs are followed by 470 serial resistors for signal integrity reasons The 4 7kQ pull resistors guaranty a TTL compatible logic level when outputs are tristate and not driven externally As an option the pull up voltage can be set to 5V by an analogue multiplexer to weakly drive a higher voltage than 3 3V by setting the output to tristate This means instead of toggling the corresponding bit of the output register the output enable register bit is set to 0 for an output high level or 1 to pull the output low the OUT_REG bit is 0 For example when connecting to a standard 5V CMOS logic input not TTL compatible levels a high level of minimum 3 5V is required A second option is set the pull voltage to GND to build pull down functionality This means instead of toggling the corresponding bit of the output register the output enable register bit is set to 0 for an output low level or 1 to drive the output high the OUT_REG bit must be 1 Please note that the pull up or pull down resistor can only drive high impedance inputs A TVS array protects against ESD shocks See the following figure for more information of the TTL I O circuitry 5V 3 3V or GND Figure 9 1 TTL I O Interface Please note that the len
64. ntial I O Interface Please consider that each TXMC633 M LVDS line has its own termination If more than four lines are connected together some termination resistors must be removed The actual data transmission rate depends on different factors like connection cable length FPGA design etc 9 1 3 Backl O Interface P14 Back I O Pins of the TXMC633 are direct routed to the Spartan6 FPGA The I O functions of these FPGA pins are directly dependent on the configuration of the FPGA The Spartan6 VCCO voltage is set to 3 3V so only the 3 3V I O standards LVCMOS33 LVTTL33 and LVDS 33 are possible for using on TXMC633 back UO interface TXMC633 User Manual Issue 1 0 1 Page 56 of 71 TEWSS TECHNOLOGIES 9 2 FPGA Debug Connector The Debug Connector X3 of the TXMC633 can be used to connect a debug adapter if necessary The debug adapter must be connected to the TXMC633 prior to XMC Carrier installation It is recommended to use the TEWS TA900 Debug Adapter The Debug Connector provides three logical interfaces JTAG FPGA UART and one General Purpose User Signal USER BUT The JTAG interface consists of the signals TDI TDO TMS TCK uses 3 3V I O voltage and can run with up to 6 MHz The FPGA UART consists of Rx and Tx and uses 1 5V UO voltage Communication settings depend on the FPGA programming The General Purpose User Signal uses 1 5V I O voltage When used with the TEWS TA900 this signal is connected to a Pus
65. nual Issue 1 0 1 Page 65 of 71 TEWSS TECHNOLOGIES config prohibit y4 Bank 2 FPGA INIT B config prohibit AA3 Bank 2 CSO B config prohibit C3 f Bank 0 HSWAPEN FE aE a a aE aE aE aE AE EE HE aE HE aE EE HE aE aE HE aa aE EEE HE aE HE EEE aE aaa REI H Section GTP Transceiver FG Location Constraints net PER2_P oc B6 Bank 101 MGT PCI Express TX_P net PER2_N loc A6 Bank 101 MGT PCI Express TX_N net PET2_P loc D7 Bank 101 MGT PCI Express RX_P net PET2_N oc C7 Bank 101 MGT PCI Express RX_N net MGTTX1_P loc B8 Bank 101 XMC P16 MGT TX P Lane 1 net MGTTX1_N loc A8 Bank 101 XMC P16 MGT TX_N Lane 1 net MGTRX1_P loc D9 Bank 101 XMC P16 MGT RX_P Lane 1 net MGTRX1_N loc C9 Bank 101 XMC P16 MGT RX_N Lane 1 net PCIe CLK125 P loc A10 Bank 101 PCI Express Reference Clock 125 MHz CLK_P via SI5338 modified net PCIe CLK125 N loc B10 Bank 101 PCI Express Reference Clock 125 MHz CLK_N via SI5338 modified net MGTTX2 P loc B14 Bank 123 XMC P16 MGT TX_P Lane 2 net MGTTX2 N loc A14 Bank 123 XMC P16 MGT TX_N Lane 2 net MGTRX2_P loc D13 Bank 123 XMC P16 MGT RX_P Lane 2 net MGTRX2_N oc C13 Bank 123 XMC P16 MGT RX_N Lane 2 net MGTTX3 P loc B16 Bank 123 XMC P16 MGT RX_P Lane 3 net MGTTX3_N loc A16 Bank 123 XMC P16 MGT RX_N Lane 3 net MGTRX3 P lo
66. point LVDS Transceiver The TXMC633 x4 provides 32 TTL and 16 differential I O Multipoint LVDS Transceiver For customer specific I O extension or inter board communication the TXMC633 xx provides 64 FPGA I Os on P14 and 3 FPGA Multi Gigabit Transceiver on P16 P14 I O lines could be configured as 64 single ended LVCMOS33 or as 32 differential LVDS33 interface All I O lines are individually programmable as input or output Setting as input sets the I O line to tri state and could be used with on board pull up also as tri stated output Each TTL I O line has a pull resistor The pull voltage level is programmable to be either 3 3V 5V and additionally GND The differential RS485 I O lines are terminated by 1200 resistors and the differential MLVDS I O lines are terminated by 1000 resistors The User FPGA is connected to a 128 Mbytes 16 bit wide DDR3 SDRAM The SDRAM interface uses a hardwired internal Memory Controller Block of the Spartan 6 The User FPGA is configured by a platform SPI flash or via PCle download The flash device is in system programmable An in circuit debugging option is available via a JTAG header for read back and real time debugging of the FPGA design using Xilinx ChipScope User applications for the TXMC633 with XC6SLX45T 2 FPGA can be developed using the design software ISE Project Navigator ISE and Embedded Development Kit EDK IDE versions are 14 7 Licenses for both design tools are required TEWS offe
67. r Estimator XPE or XPower Analyzer to determine whether additional cooling requirements as forced air cooling apply Forced air cooling is recommended during operation The TXMC633 has a heat sink mounted on the Spartan 6 FPGA TXMC633 User Manual Issue 1 0 1 Page 53 of 71 TEWSS TECHNOLOGIES Design Help 8 1 Example Design User applications for the TXMC633 can be developed using the TXMC633 FPGA Example Application design TEWS offers this FPGA Example design which consists of well documented basic example It includes an ucf file with all necessary pin assignments and basic timing constraints The example design covers the main functionalities of the TXMC633 It implements a PCle endpoint with interrupt support register mapping DDR3 memory access and basic UO functions lt comes as a Xilinx ISE 14 7 project with source code and as a ready to download bit stream This example design can be used as a starting point for own projects The TXMC633 FPGA Example Application design can be developed using the design software ISE Project Navigator ISE and Embedded Development Kit EDK IDE versions are 14 7 Licenses for both design tools are required For TXMC633 FPGA Example Application design see also the included User Manual TXMC633 User Manual Issue 1 0 1 Page 54 of 71 TEWSS TECHNOLOGIES Installation 9 1 I O Interface 9 1 1 TTL I O Interface Each of the 64 TTL I O lines is realized with a 74LVC2G241 dual buffer as an i
68. ration Mode must be set to Slave SelectMap Mode The on board logic sets the User FPGA in configuration state with all FPGA I O pins switches to High Z User FPGA is now ready for new configuration data The following procedure is required for Select Map Mode User FPGA configuration Re configuration Set ISP_ENA 1 y Set S6_LINK_ENA 0 er pui y By Re configuring the Spartan6 the XILINX PCle endpoint is reloaded and is Set FP CFG MD 1 temporarily not available on the PCI bus To avoid error messages of the PCle Set FP RE CFG 1 switch the link between the PCle Switch and the Spartan6 is disabled First the In System Program ISP Mode must be enabled Y Check response of the Spartan6 by reading the FPGA INIT_B pin value If the Reading Level is low the Spartan6 FPGA is in Reset Mode and then configuration EN STAT process could be continued yes Release a Re configuration by setting the FP RE CFG bit of the User FPGA Configuration Control Status Register to 0 y SetFP_RE_CFG 0 Check response of the Spartan6 by reading the FPGA INIT_B pin value While the FPGA INIT_B pin Level is low the Spartan6 isn t ready for configuration FP_INIT_STAT If FPGA INIT _B pin high then the configuration data must be continually written to the ISP SelectMap Data Register Typically 373103 PCI write accesses are necessary for configure a Spartan6 6SLX45T Y yes
69. re rre nin 25 TABLE 7 2 FPRGA TE EE 25 TABLE 73 MGT CONNECTIONS cocida 26 TABLE 7 4 MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS ccoo anno noc nanncnns 26 TABLE 75 AVAILABLE FPGA GLOGKS cocinan eta eden 38 TABLE 7 6 DIGITAL FRONT WO INTERFACE rr oaia aa aaia 42 TABLE 7 7 DIGITAL BACK I O INTERFACE cece i 44 TABLE 7 8 DDR3 SDRAM INTERFACE i 46 TABLE 7 9 FPGA SPI FLASH CONNECTION 47 TABLE 7 10 USER FPGA I2G INTERFACE TO CONFIGURATION EPOGA nono noconanncnn 48 TABLE 7 11 TXMC633 SERIAL NUMBER reta rera cera aer aerea aearananana 48 TABLE 7 12 VO PULL CONFIGURATION 50 TABLE 7 13 FPGA GENERAL PURPOSE W O ocio i 51 TABLE 7 14 BOARD STATUS AND USER LEDS era rereereaaaerannan 52 TABLE 10 1 PIN ASSIGNMENT FRONT PANEL I O CONNECTOR NI 60 TABLE 10 2 PIN ASSIGNMENT JTAG HEADER A7 63 TABLE 10 3 PIN ASSIGNMENT DEBUG CONNECTOR X3 TXMC633 User Manual Issue 1 0 1 Page 7 of 71 TEWSS TECHNOLOGIES Product Description The TXMC633 is a standard single width Switched Mezzanine Card XMC compatible module providing a user configurable XC6SLX45T 2 or XC6SLX100T 2 Spartan 6 FPGA The TXMC633 x0 has 64 ESD protected TTL lines the TXMC633 x1 provides 32 differential I O lines using EIA 422 EIA 485 compatible ESD protected line transceivers The TXMC633 x2 provides 32 TTL and 16 differential l Os The TXMC633 x3 provides 32 differential I O lines using Multi
70. ress Space 3 N 00000000 0x20 PCI Base Address 4 for Local Address Space 4 N 00000000 0x24 PCI Base Address 5 for Local Address Space 5 N 00000000 0x28 PCI CardBus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N 9279 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 Table 4 2 PCI Configuration Registers 4 2 2 PCI BAR Overview Size mon Endian BAR Space Prefetch Width Description Byte Mode Bit 0 256 MEM No 32 Little Local Configuration Register Space 1 256 MEM No 32 Little In System Programming Data Space Table 4 3 PCI Bar Overview TXMC633 User Manual Issue 1 0 1 Page 13 of 71 4 2 2 1 Local Configuration Register Space TEWSS TECHNOLOGIES api Register Name Size Bit 0x00 OxBF Reserved OxCO Interrupt Enable Register 32 OxC4 Interrupt Status Register 32 0xC8 Reserved 32 OxCC Reserved 32 OxDO User FPGA Configuration Control Status Register 32 0xD4 User FPGA Configuration Data Register Slave SelectMAP 32 0xD8 Reserved 32 OxDC Reserved 32 OxEO ISP Control Register SPI 32 OxE4 ISP Configuration Register SPI 32 OxE8 ISP Command Register SPI 32 OxEC ISP Status Register SPI 32 OxFO Reserved OxF4 I O Pull Resistor Configuration Regi
71. rs a well documented basic FPGA Example Application design lt includes an ucf file with all necessary pin assignments and basic timing constraints The example design covers the main functionalities of the TXMC633 It implements local Bus interface to local Bridge device register mapping DDR3 memory access and basic I O It comes as a Xilinx ISE project with source code and as a ready to download bit stream 3x MGT Power Supply Figure 1 1 Block Diagram TXMC633 User Manual Issue 1 0 1 Page 8 of 71 TEWSS TECHNOLOGIES 2 Technical Specification XMC Interface Mechanical Interface Switched Mezzanine Card XMC Interface confirming to ANSI VITA 42 0 2008 Auxiliary Standard Standard single width 149mm x 74mm Electrical Interface PCI Express x1 Link Base Specification 1 1 compliant interface conforming to ANSI VITA 42 3 2006 XMC PCI Express Protocol Layer Standard On Board Devices PCI Express Switch PCI Express to PCI Bridge PI7C9X2G404 Pericom XIO2001 Texas Instruments PCI Express Endpoint Spartan 6 PCI Express Endpoint Block User configurable FPGA TXMC633 1x XC6SLX45T 2 Xilinx TXMC633 2x XC6SLX100T 2 Xilinx SPI Flash W25Q32BV Winbond 32 Mbit contains TXMC633 FPGA Example or compatible DDR3 RAM MT41J64M16 Micron or MT41K64M16 Micron 64 Meg x 16 Bit Board Configuration FPGA LCMXO2 2000HC Lattice I O Interface Number of Chann
72. so two free user programmable LEDs are connected to the User FPGA Bank 1 Signal Bank Veco Pin Description GPIO_LEDO 1 1 5V M16 4x green on board LEDs GPIO LEID N15 FPGA BUT 1 1 5V T18 General Purpose User l O FPGA RXD 1 1 5V T17 Serial Debug Interface is accessible via TEWS FPGA TXD 1 1 5V Tig debug connector Table 7 13 FPGA General Purpose UO TXMC633 User Manual Issue 1 0 1 Page 51 of 71 TEWSS TECHNOLOGIES 7 12 On Board Indicators The TXMC633 provides a couple of board status LEDs as shown below These include Power Good and FPGA configuration status indications as well as four general purpose LEDs Board Status LEDs LED Color Description Power Good Green Power Good Signal for all on board power supplies DONE Green Configuration FPGA DONE Pin LED MachXO2 Indicates successful FPGA configuration User DONE Green User FPGA DONE Pin LED Spartan6 Indicates successful FPGA configuration USER LED1 Green Design dependent can be controlled by USERLED2 Green the User FPGA Refer to chapter User GPIO GPIO LED1 Green Configuration FPGA depends GPIO LED2 Green Table 7 14 Board Status and User LEDs TXMC633 User Manual Issue 1 0 1 Page 52 of 71 TEWSS TECHNOLOGIES 7 13 Thermal Management Power dissipation is design dependent Main factors are device utilization frequency and GTP transceiver usage Use the Xilinx XPowe
73. ster 32 OxF8 TXMC633 Serial Number 32 OxFC MachXO2 FPGA Code Version 32 Table 4 4 Local Configuration Register Space TXMC633 User Manual Issue 1 0 1 Page 14 of 71 TEWSS TECHNOLOGIES 4 2 2 2 In System Programming Data Space The In System Programming Data Space is used for passing user FPGA configuration data for in system programming of the User FPGA SPI Flash For ISP write program instructions the data must be written zero based to the ISP Data Space before the instruction is started The data must cover a complete SPI Flash memory page For ISP read instructions the data can be read zero based from the ISP Data Space after the instruction is done The data is passed for a complete SPI Flash memory page The ISP Data Space size is 256 byte covering an SPI Flash Memory Page All supported SPI Flash read and write instructions are page based Control and status register for In System programming are located in the Local Configuration Register Space The data register for direct FPGA in system programming is also located in the Local Configuration Register Space TXMC633 User Manual Issue 1 0 1 Page 15 of 71 5 Register Description 5 1 User FPGA TEWSS TECHNOLOGIES The FPGA register description depends on the user application and is not part of this specification 5 2 Configuration FPGA 5 2 1 User FPGA Configuration Control Status Register OxDO Bit Symbol Description Reset Access
74. terrupt sources depend on the user application and are not part of this target specification 6 1 2 Configuration FPGA MachXO2 The Configuration FPGA provides two interrupt sources Both interrupts are only available during SPI programming instructions The Slave Select Map Mode does not provide interrupt support e ISP SPI Instruction Done Event Interrupt Event based interrupt that becomes active when the ISP SPI Instruction Busy status bit changes from busy to not busy e ISP SPI Page Data Done Event Interrupt Event based interrupt that becomes active when the ISP SPI Data Busy status bit changes from busy to not busy 6 2 Interrupt Handling 6 2 1 User FPGA Spartan6 The interrupt handling depends on the user application and is not part of this target specification 6 2 2 Configuration FPGA MachXO2 Both Interrupts of the MachXO2 FPGA must be cleared via writing access to the corresponding Interrupt Status Flag in the Interrupt Status Register TXMC633 User Manual Issue 1 0 1 Page 23 of 71 TEWSS TECHNOLOGIES 7 Functional Description 7 1 User FPGA Block Diagram Figure 7 1 FPGA Block Diagram TXMC633 User Manual Issue 1 0 1 Page 24 of 71 TEWSS TECHNOLOGIES 7 2 User FPGA The FPGA is a Spartan 6 LX45T 2 or LX100T 2 FPGA Each Spartan 6 FPGA in a FGG484 package provides two Memory Controller Blocks and one Endpoint Block for PCI Express x1 Linkage

Download Pdf Manuals

Related Search

Related Contents

Samsung VC-7414V Kullanıcı Klavuzu    iDJ PRO - Quickstart Guide - v1.2  BULLETIN D`ADHÉSION 2015 - Neurothérapie & Nicotine  Hauck 530016  Máquinas y accesorios  Vergleichende physikalische Farbmessung und sensorische  MANUAL DE INSTRUCCIONES PARA SOLDADORA DE ARCO  PRIMERGY BX600 S2 Blade Server System Unit Hardware  FGP$ 1000 A1 (LB ) Artikel  

Copyright © All rights reserved. Failed to retrieve file