EVBUM2061 - NB3H83905CDGEVB Evaluation Board User`s Manual
Contents
1. 4 Digital Voltmeter Agilent 34410A or 34401 or equivalent 5 Matched Cables gt 20 GHz SMA connectors Storm or Semflex or equivalent 6 Time Transition Convertor Agilent 14534 250 ps or equivalent 7 Phase noise Analyzer Agilent 5052 or equivalent Step 2 Lab Set Up Procedure Split Supplies into LOW impedance 50 Ohm equipment or probes 1 Test Supply Setup VDDO and GND Supplies may be centered on 0 0 V to permit direct connection to an Oscilloscope module with 50 Ohm to GND per Figure 4 and Table 1 Connect all board supplies using banana jack or clip anvil Receiver scope Figure 4 Typical Device Termination Setup and Termination Test Setup Table 1 Test Voltages 1 56 to 1 73 V Datasheet Spec Condition TEST SETUP VDD TEST SETUP VDDO TEST SETUP DUT GND VDD VDDO 3 135 V to 3 465 V 1 56 to 1 73 V 1 56 to 1 73 V 3 3 V Nom 5 VDD VDDO 2 375 V to 2 625 V 1 1875 1 3125 V 1 1875 1 3125 V 2 5 V Nom 5 0 8 to 1 0 V 0 8 to 1 0 V 1 955 to 2 1525 V 2 335 to 2 465 V 0 8 to 1 0 V 1 575 to 1 625 0 8 to 1 0 V VDD VDDO 1 6 V to 2 0 V 1 8 V Nom 0 2 V VDD 3 135 V to 3 465 V 3 3 V Nom VDDO 2 375 V to 2 625 V 2 5 V Nom VDD 3 135 V to 3 465 V 3 3 V Nom VDDO 1 6 V to 2 0 V 1 8 V Nom VDD 2 375 V to 2 625 V 2 5 V Nom VDDO 1 6 V to 2 0 V 1 8 V Nom 2 Inputs For a Single Ended operation bridge the small gap in2. The board may be adapted for insertion testing by removing the device and adding a 16 Lead SOIC socket M amp M 50 000 00112 9 Separate supply connectors for VDD VDDO SMAGND and DUTGND banana jacks and anvil clips Contents Descriptions Board Features Board Layout Maps Test and Measurement Setup Procedures Appendix 1 Pin to Board Connection Information Appendix 2 Board Top and Bottom Layer Designs Appendix 3 Bill of Materials Lamination Stackup BACK Figure 1 NB3H83905CDGEVB Evaluation Board Semiconductor Components Industries LLC 2012 February 2012 Rev 1 Publication Order Number EVBUM2061 D NB3H83905CDGEVB Board Layout Maps VDD ANVIL Connector XTALIN SMA EN1 SMA DUTGND ANVIL Connector VDD CAP C8 BCLKO 36115 11 35104 1485833905 poise SMAGND ANVIL Connector VDDO ANVIL Connector 1 36112 36103 Figure 2 FRONT XTALIN XTALOUT Crystal Mount Crystal Mount DUTGND 3 6 VDD 4 40 __ Connector VDDO Connector SMAGND Connector Figure 3 BACK http onsemi com 2 NB3H83905CDGEVB TEST AND MEASUREMENT SET UP AND PROCEDURE Step 1 Equipment 1 Signal Generator Agilent 33250A HP8133 or equivalent 2 Tektronix TDS8000 Oscilloscope 3 Power Supply Agilent 6624A or AG6626A DC or equivalent
3. arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmati
4. located at the device footprint outline in the trace line to the 1 1875 to 1 3125 V 0 8 to 1 0 V 1 1875 to 1 3125 V 1 1875 to 1 3125 V 0 8 to 1 0 V 0 8 to 1 0 V SMA connector XTALIN Use a LVCMOS Clock amplitude signal from 3 MHz to 100 MHz on the pin16 Note the levels must be shifted according to the http onsemi com NB3H83905CDGEVB supply voltages Transitions Edges should about 250 ps or use TTC Time transition Convertor such as Agilent 14534 250 ps or an equivalent Do not drive XTALOUT Termination of the signal generator may be needed with 50 Ohms to SMA ground For Crystal operation use a fundamental Parallel Resonant crystal see Datasheet Table 3 from 3 MHz to 40 MHz across pins 1 and 16 The Crystal mount is located on the back of the board and permanently connected to the device inputs by traces Crystal Load capacitance C1 and C2 values should consider all parasitic capacitances Datasheet Figure 1 shows the typical NB3H83905C device crystal interface using a parallel resonant crystal The frequency accuracy can be fine tuned by adjusting the and C2 values For example a parallel crystal with loading capacitance CL 18 pF would use 1 15 pF and C2 15 pF as initial values These values may be adjusted to fine tune frequency accuracy Increasing the and C2 values will reduce the operational frequency Enable 1 and 2 see Datasheet Table 2 levels mu
5. 142 0711 821 2 Edge Mount JMP1 JMP2 SPC TECHNOLOGY Header Single Row Newark 93734 SPC20481 Pitch Spacing 2 54 mm Jumper Block SPC TECHNOLOGY Jumper Pitch Spacing 2 54 mm Newark 84K8570 2 Shunt SPC19808 1 XTAL Abracon ABL 25 000MHZ 25 Mhz Through Hole AT Cut Newark 1301637 1 B2F Fundamental Crystal 2 XTAL Pin Mill Max crystal pin receptacle connector 0462 0 15 15 11 27 04 0 Bourns CRO603 J O00ELF Resistor Chip 0 Q 0603 1 10 W Mouser 652 CR0603 J O00ELF 196 Lamination Stack co Sikscreen Plating Tw 0 030 Zo 50 Ohm Cu 1 2 02 0 0007 Dielectric 0 017 Cu 1 2 02 0 0007 ADJUST Cu 1 2 Oz 0 0007 ADJUST 1 2 02 0 0007 Bottom Plating lt lt 01 Top Metal 02 Inner 1 SMAGND 03 Inner 2 VDD DUTGND 0 062 0 005 04 Bottom Metal Bottom Silkscreen 01 Top Metal 02 SMAGND 03 VDD DUTGND 04 Bottom Metal http onsemi com 7 NB3H83905CDGEVB ON Semiconductor and uD are registered trademarks of Semiconductor Components Industries LLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability
6. NBSHS3905CDGEVB 83905 Evaluation Board User s Manual Device Description The NB3H83905CDG device is a 1 8 V 2 5 V or 3 3 V VDD core Crystal input 1 6 LVTTL LVCMOS fanout buffer with outputs powered by flexible 1 8 V 2 5 V or 3 3 V supply with VDD gt VDDO The core inputs accept a fundamental Parallel Resonant crystal from 3 MHz to 40 or Single Ended LVCMOS Clock from 3 MHz to 100 MHz Core supply must be equal or greater voltage than the output supply See datasheet NB3H83905C D www onsemi com Evaluation Board Description NB3H83905CDGEVB Evaluation board is designed to provide a flexible and convenient platform to quickly program evaluate and verify the performance and operation of the NB3H83905CDG SOIC 16 device under test With the device removed this NB3H83905CDGEVB Evaluation board is designed to accept a 16 Lead SOIC socket M amp M Specialties Inc 1 800 892 8760 www mmspec com M amp M 50 000 00112 to permit use as an insertion test fixture 8 2 44819150 30839050 EVALUATION BOARD 012971 ONOVNS 90102 ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL Board Features Crystal source mount or external clock source SMA input One 25 Mhz crystal is supplied SOIC 16 NB3H83905CDG device is solder mounted
7. put for BCLKO 1 2 3 4 Output block Switches only when HIGH Open default condition HIGH due to an internal pullup resistor to VCC XTALIN XTAL_IN Crystal Oscillator Input from Crystal Single ended Clock Input CLK Interface 15 EN ENABLE 1 LVTTL LVCMOS Input SMAGND or SMAGND SMA connectors GND Should be connected equipment GND SMAGND_TP http onsemi com NB3H83905CDGEVB APPENDIX 2 BOARD TOP AND BOTTOM LAYER DESIGNS Semiconductor 5 NB3H83905C EVALUATION BOARD 307 Figure 5 Top Layer Design http onsemi com 5 NB3H83905CDGEVB E 3 Figure 6 Bottom Layer Design http onsemi com 6 NB3H83905CDGEVB APPENDIX 3 BILL OF MATERIALS LAMINATION STACKUP AND ASSEMBLY NOTES BANANA1 VDD Deltron 579 0500 Connector Banana Jack Mouser 164 6219 2 VDDO BANANA2 DUT Deltron 579 0500 Connector Banana Jack Deltron Mouser 164 6218 1 GND SMA GND Black 571 0500 BANANAS SMA Deltron 579 0500 Connector Banana Jack Deltron Mouser 164 7140 1 GND Green 571 0500 05 06 Kemet C0805C104K5RACTU Cap Chip 0 1 uF 0805 50V 10 Digi Key 399 1170 1 ND C8 C9 C10 C11 Kemet T491D226K016AS Cap Chip 22 uF 10 Mouser 80 T491D226K016AS 2 C1 C2 Kemet CO805C150J1GACTU_ Cap Chip 15 pF 10 Mouser 80 C0805C150J1G J1 J10 Johnson 142 0711 821 PCB SMA Connector SMA Mouser 530
8. st be shifted according to the supply voltages Open default condition will force a HIGH enabled due to an internal pullup resistor to VCC 3 Outputs Connect LVCMOS outputs to the oscilloscope with matched cables NOTE THE READINGS OF THE OUTPUT VOLTAGE LEVELS WILL BE OFFSET With this split supply the device outputs will be parallel terminated by the oscilloscope or frequency counter input module s internal 50 Ohms to GND impedance APPENDIX 1 DEVICE PIN TO BOARD CONNECTION INFORMATION see current Datasheet Table 2 Device Pins to Board Connection Device Pin Board Description Connection 1 XTAL_OUT Crystal Oscillator Output to drive Crystal Interface 2 ENABLE 2 LVTTL LVCMOS Input Synchronous Enable Input for BCLK5 Output Switches only when HIGH Open default condition HIGH due to an internal pul lup resistor to VCC 3 7 11 DUTGND or GND GND GND Supply pins All VDD and VDDO pins must be externally DUTGND TP connected to power supply to guarantee proper operation 4 6 8 10 BCLKO 1 2 BCLKO 1 2 LVCMOS Buffered Clock outputs 12 14 3 4 5 3 4 5 Outputs Output Positive Supply pins All VDD and VDDO pins must be externally connected to power supply to guarantee proper opera tion Bypass with 0 01 uF cap to GND Output Positive Supply pins All VDD and VDDO pins must be externally connected to power supply to guarantee proper opera tion Bypass with 0 01 uF to GND Synchronous Enable In
9. ve Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 ee Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2061 D Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information ON Semiconductor NB3H83905CDGEVB
Download Pdf Manuals
Related Search