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IOS-482 User`s Manual

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1. LNdLNO H3MWlL L YaN YALNNOO Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions Qacromag com http www acromag com
2. External Trigger 00 Disabled Default st ai LOW Trigger 10 Active HIGH Trigger Gate Off Continue when high Stop when low 12 11 10 Clock Source 000 internal Default 05 2 2MHz 13 Input Debounce Enable EN Disabled Default Input Enabled Reject Reinitialize or Trigger Pulses ote less than or S to 2 5us Interrupt Ense Disable Interrupt Service Default Enable Interrupt Service No Debounce Applied to any Counter Timer Module 2 1 COUNTER CONTROL REGISTER WATCHDOG TIMER OPERATION Table 3 12 Counter Control Register Watchdog Timer 1 The default state of the output pin is high output has pullup installed Bit 3 specifies the active output polarity when the output is driven 2 The available clock sources are determined by the operational frequency of the carrier board For an 8MHz carrier bit 0 of the Board Control Register located at the base address plus an offset of OH must be set low Fora 32MHz carrier the bit must be set high Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 22 105 482 I O Server Module User s Manual Counter Timer Module COUNTER CONTROL REGISTER Event Counting Operation Positive or negative polarity events can be counted Event Counting is selected by setting Counter Control Register bits 2 to 0 to logic 100 and setting bits 12 to 10 to logi
3. Counter Constant B Register Read Write This read write register is used to store the counter timer constant B value It is necessary to load the constant value into the counter in one clock cycle Thus a 16 bit write access is required The addresses corresponding to the Counter Constant B registers are given in Table 3 2 Digital Input Register Read Base 58H This 8 bit read only register contains the value of the Digital TTL inputs A read value of one symbolizes a logic high while a value of zero represents a logic low Table 3 7 identifies the position of the available input bits FUNCTION BENE 1 DIn2 2 7 Not Used Reading this register is possible via 16 bit or 8 bit data transfers Digital Output Register Read Write Base This 8 bit read write register contains the value of the Digital TTL outputs To set a digital output high write a one to the proper bit position To set the value logic low write a zero to the proper bit On power up output bits are initialized to logic 1 Table 3 8 identifies the position of the available output bits 0 DOut1 Writing to this register is possible via 16 bit or 8 bit data transfers A software or hardware reset will set bits 0 to 5 to logic 1 Counter Timer Module 1 3 CONTROL REGISTERS Table 3 7 105 482 Digital Input Register 1 Digital Input bits will read logic 1 if left unconnected 2 All bits labe
4. Connection In7_A Enable Input In7_B Signal Input In7_C Ext Trigger Out7 Output 2 Write the following information BDA4H to Counter 7 Control Register located at base address plus an offset of 14H Bits Logic 2 1 0 Sets the counter to Frequency Measurement 3 Sets the output to active low 5 4 Sets the Enable Pulse input InA to active high 7 6 Enables the Signal input InB to active high Enables the external Trigger Input InC to active low Sets the counter to Frequency Measurement mode 9 8 12 11 10 13 Enables input debounce on InA InB and 14 Not used 15 Enables interrupts Counter Timer Module 3 7 PROGRAMMING EXAMPLES Figure 3 5 Event Counting waveform In the figure each represents an interrupt Table 3 26 Frequency Measurement Pin Assignments for Counter 7 Note Make sure all inputs and outputs are properly grounded Table 3 27 Frequency Measurement Control Register 7 Settings Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 8 105 482 I O Server Module User s Manual Counter Timer Module PROGRAMMING EXAMPLES Figure 3 6 Frequency Measurement waveform In the figure each represents an interrupt Table 3 28 Pulse Width Measurement Pin Assignments for Counter 9 Note Make sure all inputs and outputs are properly grounded 3 Do n
5. The Counter Control Register is cleared set to 0 following a reset thus disabling the counter timer Reading or writing to this register is possible via 16 bit or 8 bit data transfers Eight modes of operation are provided quadrature position measurement pulse width modulation watchdog timer event counting frequency measurement pulse width measurement period measurement and one shot pulse mode The following sections describe the features of each method of operation and how to best use them Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com X1 X2 X4 105 482 I O Server Module User s Manual Counter Timer Module 1 D Quadrature Position Measurement COUNTER CONTROL REGISTER The counter timers may be used to perform position measurements from quadrature motion encoders Bits 2 to 0 of the Counter Control Register set to logic 001 configure the counter for quadrature measurement A quadrature encoder can have up to three channels A B and Index When channel A leads channel B by 90 in a quadrature cycle the counter increments When channel B leads channel A by 90 in a quadrature cycle the counter decrements The number of increments or decrements per cycle depends on the type of encoding X1 X2 or X4 A LEADS B STOPPED B LEADS A Figure 3 1 Shows a quadrature cycle and the CH B T L T L resulting increments and decrements for X1 X2 and UpCik
6. 05 482 BLOCK DIAGRAM 49 Trademarks are the property of their respective owners Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com 4 105 482 I O Server Module User s Manual Counter Timer Module E TOR The I O Server Module IOS Series IOS 482 module provides support for ten independent 16 bit multifunction counter timers Each counter timer can be configured for quadrature position measurement pulse width modulated output watchdog timer event counter frequency measurement pulse width measurement period measurement or one shot pulse output Important Note The following IOS model are accessories to the IOS Server Models IOS 7200 05 7200 105 7400 and IOS 7400 WIN which are cULus Listed This equipment is suitable for use in Class Division 2 Groups A B and D or non hazardous locations only Table 1 1 The 05 482 OPERATING TEMPERATURE module temperature ranges UO Type RANGE KEY 5 482 COUNTER TIMER e TTL I O 105 482 Counter Timer I O is available as TTL only Mixed FEATURES TTL and RS485 RS422 I O options are available on the IOS 483 Only RS485 RS422 1 0 is available on the IOS 484 model e Quadrature Position Measurement Three input signals can be used to determine bi directional motion The sequence of logic high pulses for two input signals A and B indicate direction and a third signal index is used
7. The counter reload and trigger signals are periodic Additionally debounce and interrupts are enabled Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Counter Timer Module 3 D PROGRAMMING 1 Connect the inputs output to the following pins unpowered EXAMPLES Pin Connection 5 Reload In5_B Ext Clock Table 3 22 Watchdog Pin Assignments for Counter 5 In5_C Ext Trigger Out5 Output Note Make sure all inputs and outputs are properly grounded 2 Write the following information B56BH to Counter 5 Control Register located at base address plus an offset of 10H Bits toge Operation Table 3 23 Watchdog 2 1 0 Sets the counter to Watchdog mode Counter Control Register 5 3 Sets the output to active high Settings 5 4 Enable the Counter Reload input InA to active high 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active low 12 11 10 Sets the clock to an external source 13 Enables input debounce on InA and InC 14 Not used 15 Enables interrupts 3 Write the 16 bit value 5H to Counter 5 Constant A Register located at the base address plus an offset of 38H In order to determine the correct Constant A Register value first calculate the period of the selected clock Th
8. or repeated each time it is re triggered One Shot generation is selected by setting Counter Control Register bits 2 to 0 to logic 111 The Counter Constant A value controls the time until the pulse goes active The duration of the pulse high or low is set via the Counter Constant B value Note that the Constant value defines the logic high pulse width if active high output is selected and a low pulse if active low output is selected The counter goes through a full countdown sequence for each Counter Constant value When the 0 count is detected on the next rising edge of the clock the output toggles to the opposite state and the Counter Constant B value is loaded into the counter and countdown resumes decrementing by one each clock cycle For example a counter constant value of 7 will provide a pulse duration of 7 clock cycles of the selected clock then 125ns will be added for the count detection of O Note that this extra delay is only 31 25ns for 32MHz carrier operation InA can be used as a Gate Off signal to stop and start the counter and thus output When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will enable the one shot counter while a logic high will stop the one shot counter When InA is enabled for active high Gate Off operation a logic high will enable the one shot counter while a logic low will stop the one shot counter InB can be used to input an exte
9. value Constant B Reg Count down from value loaded Defines duration of active pulse Constant B can be reloaded on occurrence of an Index signal Counter Read Back Reg Gives the Count value at the time of the read Gives the Count value at the time read Gives count value reflecting measurement Gives count value reflecting pulse measured Gives count value reflecting period measured Gives count value reflecting position measurement Interrupt On Edge Transitions On Terminal Count of 0 Upon reach of count limit Upon end of enable pulse Upon end of pulse measurement Upon end of period measurement On Index or Constant A count limit Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 44 105 482 I O Server Module User s Manual Counter Timer Module 4 0 THEORY OF OPERATION FIELD INPUT OUTPUT SIGNALS COUNTER TIMERS DIGITAL I O This section contains information regarding the hardware of the 05 482 A description of the basic functionality of the circuitry used on the board is also provided Refer to OS 482 BLOCK DIAGRAM as you review this material A Field Programmable Gate Array FPGA installed on the IOS Module provides an interface to the carrier board The interface to the carrier board allows complete control of all board functions The field I O interface to the I
10. FUNCTION 2 1 0 Specifies the Counter Mode Event Counting 3 Output Polarity Output Pin ACTIVE Level Active LOW Default Active HIGH InA Polarity Gate Off 00 Disabled Default Active LOW In A 0 Continue Counting In A 1 Stop Counting Active HIGH In A 0 Stop Counting In A 1 Continue Counting Disabled InB Polarity Event Input Disabled Default Active LOW Events 10 Active HIGH Events Disabled InC Polarity External Trigger 00 Disabled Default Active LOW Trigger 10 Active HIGH Trigger Up when logic low Down when logic high 11 Count Control 12 11 10 Specifies the Counter Mode 000 Event Counting 13 Input Debounce Enable Disabled Default Input Enabled Reject Gate Off Event Input Up Down or Pulses 1055 less than or equal to 2 5us Interrupt E Disable Interrupt Service Default Enable Interrupt Service No Debounce Applied to any Counter Timer Module 2 3 COUNTER CONTROL REGISTER EVENT COUNTING OPERATION Table 3 13 Counter Control Register Event Counting 1 The default state of the output pin is high output has pullup installed Bit 3 specifies the active output polarity when the output is driven Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 24 105 482 I O Server Module User s Manual Counter Timer Module COUNTER CONTROL REGISTER Frequency Measurement
11. clock to an external source 13 Disables input debounce on InA and InC 14 Not used 15 Enables interrupts 3 Write the 16 bit value 4H to Counter 9 Constant A Register located at base address plus an offset 40H for the non active portion of the pulse and 1H to Counter 9 Constant B Register located at base address plus an offset 54H for the active portion of the pulse Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 105 482 I O Server Module User s Manual Counter Timer Module PROGRAMMING EXAMPLES Figure 3 9 One Shot Pulse waveform In the figure each represents an interrupt In order to determine the necessary Counter Constant values first calculate the period of the selected clock internal or external The period is calculated by taking the inverse of the clock frequency In this case 1 200 2 is equal to 5us Then take the total time for the low portion of the pulse and divide it by the clock period For this example 20us 5us is equal to 4 Convert this value to Hex and the result is the total count that is placed in the appropriate Counter Constant Register Since it has been stipulated that the pulse is active high 4H is written to the Counter 9 Constant A Register which contains the value for the non active low portion of the pulse The same procedure is used to calculate the Constant B value Take the total period of the high portion of th
12. enclosure is required to meet compliance Counter Functions Quadrature Position Measurement Pulse Width Modulation Watchdog Timer Event Counting Frequency Measurement Period Measurement Pulse Width Measurement and One Shot Repetitive Counter The 05 482 has a total of ten 16 bit TTL counters available for use Each Counter has an InA InB and InC input port These TTL input ports are used to control Start Stop Reload Event Input External Clock Trigger and Up Down operations e Vi 2 0V minimum e Vy 0 8V maximum Pull up Resistors 4 7KQ pull up resistors are installed on all inputs Debounce Interval 2 5us Enabled Disable via Counter Control Register Each Counter has one Output Port The TTL output ports are used for waveform output watchdog active indicator or 1 75ps pulse upon counter function completion Counter output is programmable as active high or low Vou 2 4V minimum e 0 55V maximum e loy 15 0mA e 64mA Pull up Resistors 4 7KQ pull up resistor is installed for each Counter Output Selectable Counter Clock Frequencies 8MHz 4MHz 2MHz 1MHz 0 5MHz or External up to 2MHz Minimum Event 125ns Minimum Pulse Measurement 125ns Minimum Period Measurement 300ns Minimum Gate Trigger Pulse 125ns SPECIFICATIONS COUNTER TIMERS Counter Input Input Electrical Characteristics Counter Output Output Electrical Characteristics 8MHz IOS Carrier Opera
13. for 1 75 If debounce was enabled the output pulse will occur 2 5us after the completion of the input signal Additionally the counter must be re triggered before any further measurements take place For more information see the Input Period Measurement description One Shot Pulse Mode Example The objective for this example is to use the One Shot Pulse mode using 16 bit Counter 9 The output pulse is active high with the low portion 20us long and the high portion 5 us long Additionally the counter has an external clock an active high Gate off signal and an active high External Trigger Interrupts are enabled Assume the external clock has a frequency of 200KHz 1 Connect the inputs output to the following pins unpowered Pin Connection Table 3 32 One Shot Pulse Ing Gate Off Pin Assignments for Counter 9 In9_B Ext Clock In9_C Ext Trigger Out9 Output Note Make sure all inputs and outputs are properly grounded 2 Write the following information 966FH to Counter 9 Control Register located at base address plus an offset of 18H Bis Logic Operation Table 3 93 One Shot Pulse 2 1 0 Sets the counter to One Shot Pulse generation mode 011 0 Register 9 Settings 3 Sets the output to active high 5 4 Sets the Gate Off input InA to active high 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active high 12 11 10 Sets the
14. to initialize the counter X1 X2 and X4 decoding is also implemented X1 decoding executes one count per duty cycle of the A and B signals while X2 and X4 execute two and four counts per duty cycle respectively e Pulse Width Modulation Each counter can be programmed for pulse width modulation The duration of the logic high and low levels of the output signal can be independently controlled An external gate signal can also be used to start stop generation of the output signal e Watchdog Timer Each counter can be configured as a countdown timer for implementation as a watchdog timer A gate off signal is available for use to stop the count down operation Interrupt generation upon a countdown to zero condition is available e Event Counter Each counter can be configured to count input pulses or events A gate off signal is provided to control count up or count down with each event Interrupt generation upon programmed count condition is available e Frequency Measurement Each counter can be configured to count how many active edges are received during a period defined by an external count enable signal An interrupt can be generated upon measurement complete e Programmable Interface Polarity The polarities of the counter s external trigger input and output pins are programmable for active high or low operation e Digital I O The 05 482 has 6 TTL outputs and 2 TTL inputs available for use Acromag In
15. to logic 1 the output signal will be driven active while the index condition remains true QUADRATURE POSITION Encoder output signals be noisy It is recommended that the InA MEASUREMENT InB and InC input signals be debounced by setting bit 13 of the Counter Control register to logic 1 Noise transitions less than 2 5us will be removed with debounce enabled Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions Qacromag com http www acromag com 1 8 105 482 I O Server Module User s Manual Counter Timer Module COUNTER CONTROL REGISTER Pulse Width Modulation Pulse width modulated waveforms may be generated at the counter timer output The pulse width modulated waveform is generated continuously Pulse Width Modulation generation is selected by setting Counter Control Register bits 2 to 0 to logic 010 Counter Constant A value controls the time until the pulse goes active The duration of the pulse is set via the Counter Constant B register Note that a high pulse will be generated if active high output is selected while a low pulse will be generated if active low output is selected The counter goes through a countdown sequence for each Counter Constant value When the 0 count is detected the output toggles to the opposite state Then the second Counter Constant value is loaded into the counter and countdown resumes decrementing by one for each rising edge of the clock selected via Con
16. when used for input pulse measurement 14 Not Used bit reads back as 0 ee Enable Disable Interrupt Service Default Enable Interrupt Service 12 11 10 No Debounce Applied to any Counter Timer Module 2 7 COUNTER CONTROL REGISTER INPUT PULSE WIDTH MEASUREMENT Table 3 15 Counter Control Register Input Pulse Width Measurement 1 The default state of the output pin is high output has pullup installed Bit 3 specifies the active output polarity when the output is driven 2 The available clock sources are determined by the operational frequency of the carrier board For an 8MHz carrier bit 0 of the Board Control Register located at the base address plus an offset of OH must be set low Fora 32MHz carrier the bit must be set high Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com 28 105 482 I O Server Module User s Manual Counter Timer Module COUNTER CONTROL REGISTER Input Period Measurement The counter timer may be used to measure the period of an input signal at the counter input InA Setting bits 2 to 0 of the Counter Control Register to logic 110 configures the counter for period measurement The first input cycle after period measurement is triggered will be measured InA is used to input the signal to be measured Period measurement can be initiated on the active low or high portion of the waveform The p
17. 1 0 Specifies the Counter Mode One Shot Generation MODE 3 Output Polarity Output Pin ACTIVE Level Table 3 17 Counter Control 0 Active LOW Default Register Active HIGH One Shot Pulse InA Polarity Gate Off Polarity m Disabled Default Active LOW output pin is high output has In A 0 Output Enabled pullup installed Bit 3 In A 1 Output Disabled specifies the active output Active HIGH polarity when the output is In A 0 Output Disabled driven 11 In A21 Output Enabled Disabled oa External Clock Input Disabled Default External Clock Enabled 10 External Clock Enabled InC Polarity External Trigger 00 Disabled Default 10 Active HIGH Trigger Disabled 12 11 10 Clock Source 2 The available clock sources Carrier Operational Freq 32MHz are by the m operational frequency of the 000 Loco Ihe carrier board For an 8MHz Internal carrier bit 0 of the Board Internal Control Register located at the Internal 16MHz base address plus an offset of Internal 32MHz 0H must be set low Fora External Clock Up to 2MHz Up to 8MHz MUSEDE 13 Input Debounce Enable EZ Disabled Default No Debounce Applied to any Input Enabled Reject Gate Off or Trigger Pulses noise less than or equal to 2 5us Not Used bit reads back as 0 15 Interrupt Enable 0 Disable Interrupt Service Default Enable Interrupt Service Acromag Inc Te
18. Acromag 9 THE LEADER IN INDUSTRIAL 1 05 482 Counter Timer Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 848 B11C007 2 105 482 I O Server Module User s Manual TABLE OF CONTENTS IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring Counter Timer Module component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information KEY 105 482 COUNTER TIMER FEATURES 4 The information of this manual IOS MODULE Win32 DRIVER SOFTWARE 5 may change without notice IOS MODULE LINUX SOFTWARE 5 Acromag makes no warranty of any kind with regard to this material including but not 2 0 PREPARATION FOR USE eds UNPACKING AND 6 y and fitness for a particular BOARD 6 CONNECTORS nere eru rna ace rena 6 purpose Furthe
19. DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation BOARD CONFIGURATION CONNECTORS IOS Field I O Connector P2 Table 2 1 105 482 Field I O Pin Connections The 05 482 has 10 TTL 16 bit counters available It also has 2 TTL Digital Inputs and 6 TTL Digital Outputs The Digital are emphasized in bold italics Counter Timer Module For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Power should be removed from the board when installing IOS modules cables termination panels and field wiring Refer to the following discussion for configuration and assembly instructions Model IOS 482 Counter Timer Boards have no jumpers or switches to configure all configuration is through software commands P2 provides the field I O interface connector for mating IOS modules to the carrier board P2 is a 50 pin female rece
20. Link Libraries DLLS that are compatible with a number of programming environments including Visual C Visual Basic NET Borland C Builder and others The DLL functions provide a high level interface to the IOS carrier and modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers Acromag provides a software product sold separately consisting of Linux amp software This software Model IOSSW API LNX is composed of Linux libraries designed to support applications accessing I O Server Modules installed on Acromag Industrial I O Server systems The software is implemented as a library of functions which link with existing user code Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection KEY 105 482 COUNTER TIMER FEATURES IOS MODULE Win32 DRIVER SOFTWARE IOS MODULE LINUX SOFTWARE 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions Qacromag com http www acromag com 6 105 482 I O Server Module User s Manual CAUTION SENSITIVE ELECTRONIC
21. OS module is provided through connector P2 refer to Table 2 1 These pins are tied to the inputs and outputs of EIA RS485 RS422 line transceivers or TTL transceivers RS485 signals received are converted from the required EIA RS485 RS422 voltages signals to the TTL levels required by the FPGA Likewise TTL signals are converted to the EIA RS485 RS422 voltages for data output transmission The FPGA provides the necessary interface to the RS485 RS422 transceivers or TTL transceivers for control of data The field I O interface to the carrier board is provided through connector P2 refer to Table 2 1 Field I O points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring this effect may cause operational errors and with extreme abuse possible circuit damage Counter timer input control signals are TTL logic level and InA InB and InC are available via the field connector P1 See Table 2 1 for the list of these signals and their corresponding pin assignments Counter timer out signals OUT1 to 10 are TTL logic levels and are available via the P1 field I O connector See Table 2 1 for the output signals and their corresponding pin assignments Digital input output signals DIN1 to 2 and DOut1 to 6 are TTL logic levels and are available via the P1 field I O connector Each line ha
22. Operation Frequency Measurement is selected by setting Counter Control Register bits 2 to 0 to logic 100 and setting bits 12 to 10 to logic 111 The counter counts how many InB edges low to high or high to low are received during the InA enable interval The frequency is the number of counts divided by the duration of the InA enable signal InA is used as an enable signal to start frequency measurement The InA signal must be a pulse of known width When InA is configured via bits 5 and 4 of the control register as an active low enable input a logic low input will enable frequency measurement while a logic high will stop frequency measurement When InA is configured as an active high enable signal a logic high will enable frequency measurement while a logic low will stop frequency measurement InB is used to input the signal whose frequency is to be measured Input pulses occurring at input InB of the counter are counted while the enable signal present on InA is active When the InA signal goes inactive the counter output will generate a 1 75us output pulse and an optional interrupt InC can be used as an external trigger input When control register bits 9 and 8 are set to logic 01 or 10 the InC input functions as an external trigger input Frequency measurement may also be internally triggered via the Trigger Control Register at the base address offset 04H initial trigger software or external starts frequency
23. Period Measurement Example The objective for this example is to use the Input Period Measurement operation using 16 bit Counter 9 The high to low transition of the input signal will begin measurement Additionally the counter has an external clock and an active high External Trigger The output of the counter is active high and interrupts are enabled Assume the external clock has a frequency of 250KHz 1 Connect the inputs output to the following pins unpowered Table 3 30 Input Period Pin Connection 2 9 Pulse Input ssignments for Counter In9 B Ext Clock In9_C Ext Trigger Out9 Output Note Make sure all inputs and outputs are properly grounded 2 Write the following information 965EH to Counter 9 Control Register located at base address plus an offset of 18H Table 3 31 Input Period Bits logic Operation Measurement Control Register 2 1 0 Sets the counter to Input Period Measurement 3 Sets the output to active high 5 4 Sets the Pulse input InA to active low 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active high 12 11 10 Sets the clock to an external source 13 Disables input debounce on InA and InC 14 Not used 15 Enables interrupts 3 Do not write to either of the Counter 9 Constant Registers They are not required for input period measurement and
24. TIVE Level Table 3 14 Counter Control B Active LOW Default Register 1 Active HIGH Frequency Measurement X Pis ied E of Known Width iTe dbura ih output pin is high output has Aclve Loin Pulse pullup resistor installed Bit 3 Active HIGH Pulse specifies the active output Disabled polarity when the output is Signal Measured Counted driven Disabled Default Active LOW Pulse Counted Active HIGH Pulse Counted 10 Disabled InC Polarity External Trigger 00 Disabled Default Active LOW Trigger 10 Active HIGH Trigger Disabled 12 11 10 Specifies the Counter Mode 13 Input Debounce Enable Disabled Default No Debounce Applied to any Input EX Enabled Reject Frequency Input Enable or Trigger ts noise less m or equal to 2 5us Interrupt rape Disable Interrupt Service Default Enable Interrupt Service Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com 26 105 482 I O Server Module User s Manual Counter Timer Module COUNTER CONTROL REGISTER Input Pulse Width Measurement Setting bits 2 to 0 of the Counter Control Register to logic 101 configures the counter for pulse width measurement After pulse width measurement is triggered the first input pulse is measured InA is used to input the pulse to be measured An active low or high pulse can be measured InB can be used to input an external clock fo
25. U X4 encoding An X1 encoding Increment occurs on the rising edge of channel A when channel A leads channel B An X1 encoding decrement occurs on the falling edge of channel A when channel B leads channel A For X2 encoding two increments or decrements on each edge of channel A result from each cycle The counter increments when A leads B and decrements when B leads A For X4 encoding four increments or decrements on each edge of channel A and B result from each cycle The counter increments when A leads B and decrements when B leads A Quadrature measurement must be triggered internally via the Counter Trigger Register at the base address offset 04H An initial software trigger starts quadrature position measurement operation InA and InB input signals are used to input the channel A and channel B input signals respectively The counter will increment when channel A leads channel B and will decrement when channel B leads channel A Three rates of increments and decrements are available X1 X2 and X4 which are programmed via counter timer control register bits 5 and 4 Channel B is enabled for input by setting bit 6 to a logic 1 InC can be used for the Index signal Encoders that have an index channel can cause the counter to reload with the Counter Constant B value in a specified phase of the quadrature cycle Reload can be programmed to occur in any one of the four phases in a quadrature cycle You must ensure that the Ind
26. Width Modulation mode 3 Sets the output to active high 5 4 Enable the Gate Off input InA to active high 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active high 12 11 10 Sets the clock to an external source 13 Enables input debounce on InA and InC 14 Not used 15 Enables interrupts Counter Timer Module 3 3 PROGRAMMING EXAMPLES Figure 3 2 Quadrature waveform In the figure each represents an interrupt Table 3 20 PWM Pin Assignments for Counter 3 Note Make sure all inputs and outputs are properly grounded Table 3 21 PWM Counter Control Register 3 Settings Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 34 105 482 I O Server Module User s Manual Counter Timer Module PROGRAMMING EXAMPLES Figure 3 3 PWM waveform In the figure an i represents an interrupt 3 Write the 16 bit value 3H to Counter 3 Constant A Register located at base address plus an offset 34H for the non active portion of the pulse and 1H to Counter 3 Constant B Register located at base address plus an offset 48H for the active portion of the pulse In order to determine the necessary Counter Constant values first calculate the period of the selected clock internal or external The period is calculated by taking the inverse of the clock frequency In this case 1 500KHz is equal to 2us Then take the
27. a counter timer pending interrupt A counter timer pending interrupt can also be released by disabling interrupts via bit 15 of the Counter Control registers 0 CounterrTimer 1 Interrupt PendngiSiear 6 Counter Timer 7 Interrupt Pending Clear e Gounter Timer 9 Interrupt Pending Clear o Counter Timer 10 ntemupiPendmgOear Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IOS 482 I O Server Module User s Manual Counter Timer Module 1 1 A Counter Timer that is not interrupt enabled will never set its interrupt status flag A Counter Timer interrupt can be cleared by writing a 1 to its bit position in the Interrupt Status Clear Register writing a 1 acts as a reset signal to clear the set state The interrupt will be generated again if the condition which caused the interrupt to occur remains Writing 0 to a bit location has no effect That is a pending interrupt will remain pending Writing to this register is possible via 16 bit or 8 bit data transfers A power up or system reset clears all interrupts setting all bits in the Interrupt Status Clear Register to logic 0 Counter Trigger Register Write Base 04H This register is used to implement software triggering for all counter timers Writing a 1 to the counter s corresponding trigger bit of this register will cause the counter function to be triggered Table 3 5 i
28. ad Counter Timer Module Board Control Register Read Write Base 00H This read write register is used to identify the IOS48x model set the carrier operational frequency and for software reset The function of each of the board control register bits is described in Table 3 3 This register can be read or written with either 8 bit or 16 bit data transfers A power up or system reset sets board control register bit O to logic 0 FUNCTION IOS Carrier Clock Speed Read Write Bit 0 8MHz Carrier 1 32MHz Carrier This bit must be set correctly for proper operation 1to7 Not Used Identify IOS48x model Read Only Bits 111 105 482 10 9 8 150 105 483 001 05 484 11 to 14 Not Used Software Reset Write logic 1 to this bit to reset the 05 482 Interrupt Status Clear Register Read Write Base 02H This read write register is used to determine the pending status of the Counter Timer interrupts and release pending interrupts Counter Timer interrupt status clear bits 0 to 9 reflect the status of each of the Counter Timers A 1 bit indicates that an interrupt is pending for the corresponding counter timer Counter Timer and its corresponding interrupt Pending Clear bits are as shown in Table 3 4 Read of this bit reflects the interrupt pending status of the counter timer logic 0 Interrupt Not Pending 1 Interrupt Pending Write a logic 1 to this bit to release
29. adrature Position Measure Channel A InB Input External Clock External Clock Event Input Signal Measured Counted External Clock External Clock Channel B InC Input External Trigger External Trigger or Gate Off for start stop control External Trigger or Up Down Count Control External Trigger External Trigger External Trigger Internal Software Trig Starts Waveform Generation Starts Count Down Start Event Counting Start Frequency Measurement on next active edge of InA signal Next complete pulse after trigger is measured Next complete period after trigger is measured Starts Quadrature Measurement Counter Timer Output Output Waveform Output is active from trigger until terminal count 1 75us pulse is output upon reaching the count limit 1 75us pulse is output upon end of frequency measurement 1 75us pulse is output upon end of pulse measurement 1 75us pulse is output upon end of period measurement Output pulse while index or programmed count limit remains true Constant A Reg Count down from value loaded Defines duration until active pulse Counts down from value loaded Must always load before trigger Note that InA input can be used to reload Count Limit Input events are counted up to the count limit An interrupt can be generated when the counter equals the Constant A
30. c O00 Input pulses or events occurring at the input InB of the counter will increment the counter until it reaches the Counter Constant A value Upon reaching the count limit an output pulse of 1 75us will be generated at the counter output pin and an optional interrupt may be generated Additionally the internal event counter is cleared The counter will continue counting again from 0 until it reaches the Counter Constant A value Once triggered event counting will continue until disabled via Control register bits 2 to 0 InA can be used as a Gate Off signal to stop and start event counting When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will enable event counting while a logic high will stop event counting When InA is enabled for active high Gate Off operation a logic high will enable event counting while a logic low will stop event counting InB is used as the event input signal Active high or low input events can be selected via Control register bits 7 and 6 A minimum event pulse width InB of 125ns is required for correct pulse detection with input debounce disabled Programmable clock selection is not available in event counter mode InC can be used to either control up down counting or as an external trigger input When control register bits 9 and 8 are set to logic 11 InC functions as an Up Down signal When the Up Down signal is high the counter is i
31. c Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Counter Timer Module D e Pulse Width or Period Measurement Each counter be configured to measure pulse width or waveform period In addition an interrupt can be generated upon measurement complete e One Shot and Repetitive One Shot A one shot pulse waveform may also be generated by each counter The duration of the pulse and the delay until the pulse goes active is user programmable A repetitive one shot can be initiated with repetitive trigger pulses e internal or External Triggering A software or hardware trigger is selectable to initiate quadrature position measurement pulse width modulation watchdog countdown event counting frequency measurement pulse width measurement period measurement or one shot e Conduction Cooled Module I O modules employ advanced thermal technologies A thermal pad and module cover wicks heat away from the module and transfers the energy to a heat spreading friction plate Heat moves to the enclosure walls where it is dissipated by the external cooling fins Acromag provides a software product sold separately to facilitate the development of Windows Embedded Standard applications interfacing with Server Modules installed on Acromag Industrial I O Server systems This software Model IOSSW DEV WIN consists of a low level driver and Windows 32 Dynamic
32. dentifies the trigger bit location corresponding to each of the counters The contents of this register are not stored and merely act to trigger the corresponding counters Table 3 5 105 482 Counter o Trigger Register 1 All bits wil return logic 0 when read 6 Counter Trigger 8 Comtr9Tigge 9 OomtrioTiggg Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com 1 2 105 482 I O Server Module User s Manual Counter Timer Module CONTROL REGISTERS Table 3 6 05 482 Counter Stop Register 1 All bits will return logic 0 when read Note that the Counter Constant Registers are cleared set to 0 following a system or software reset Triggering may be used to initiate quadrature position measurement pulse width modulation watchdog timer initiates countdown event counting frequency measurement pulse width measurement period measurement or one shot Writing to this register is possible via 16 bit or 8 bit data transfers Counter Stop Register Write Base 06H This register is used to stop the counters of one or a group of Counter Timers Writing a 1 to the counter s corresponding stop bit of this register will cause the counter to be disabled That is bits 2 1 and 0 of the counter control register are cleared to 000 thus disabling the counter Table 3 6 identifies th
33. down to InA input can be used to reload the counter with the Constant A register value InA reload input is enabled via Control register bits 5 and 4 The counter can also be reloaded via a software write to the Counter Constant A register Writing to the Counter Constant A register will load the value directly into the counter even if watchdog counting is actively counting down InB can be used to input an external clock for watchdog timing Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input The timer can alternatively be internally clocked using control register bits 12 11 and 10 Available frequencies vary depending on carrier operational frequency InC can be used to either continue stop watchdog counting or as an external trigger input When control register bits 9 and 8 are set to logic 11 InC functions as a Continue Stop signal When the Continue Stop signal is high the counter continues counting when low the counter stops counting Alternately when control register bits 9 and 8 are set to logic 01 or 10 the InC input functions as an external trigger input The watchdog timer may also be internally triggered via the Trigger Control Register at the base address offset 04H When triggered the counter timer contents are decremented by one for each clock cycle until it reaches 0 upon which a watc
34. e User s Manual Counter Timer Module m ar eomer ones neser m Generi cemenA oo GemetosmenA eomer cesena neose oa camer conn neser ee _ e eomer coana _ e eomer comin Aronia 9 Gener ossi _ e Generi cesena neose Genes ossi ss cemere en camer Comte Breyer a comin 8 reper a e eomer corans neser _ e camer comin Repay camer econ Sepa _ camer con rese eo camera cose Sepia e s caer cnn 57 Counter 10 Constant B Register Not Used Digital Input Register Not Used Digital Output Register Not Used Interrupt Vector 1 The 05 482 will return 0 for Register all addresses that are Not SF 5E Used Not Used 7F 7E Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 105 482 I O Server Module User s Manual CONTROL REGISTERS CAUTION Bit 0 of the Board Control Register must be set correctly for proper module operation Table 3 3 Board Control Register 1 All bits labeled Not Used and the Software Reset bit will return logic O when read CONTROL REGISTERS Table 3 4 05 482 Counter Timer Interrupt Status Clear 1 All bits labeled Not Used will return logic O when re
35. e period is calculated by taking the inverse of the clock frequency In this case 1 500KHz is equal to 2 5 counter Constant B Then take the total duration of the watchdog timer and divide it by the clock 50 910818 m Watchdog mode period For this example 10us 2us is equal to five Converted to Hex this is the number to write to the Counter 5 Constant A Register 4 The following is a waveform diagram of this example Figure 3 4 Watchdog InA J waveform IB InC 1 5 10us Output NEN In the figure each Interrupts i i represents an interrupt In Watchdog mode the counter must be loaded InA and then triggered InC for each cycle While this can be done internally or externally failure to follow this procedure will cause unpredictable results Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 6 105 482 I O Server Module User s Manual Counter Timer Module PROGRAMMING Note that the InA and InC inputs run off the internal 8 2 or 32 2 EXAMPLES clock Those signals may not be synchronous with the selected clock For further information see the Watchdog Timer Operation description Event Counting Operation Example The objective for this example is to create an Event Counter that will count the number of active high events on InB using 16 bit Counter 7 The output is acti
36. e pulse and divide it by the period of the clock For this example 5us 5us is equal to 1 Converting to hex 1H is written to Counter 9 Constant B Register since it contains the active high portion of the pulse 4 The following is a waveform diagram of this example InA e i nC Gate Off 20 Counter 2005 Ou owe F5usd F5usd Interrupts i i The Gate Off signal InA is used as a pause mechanism The counter register and output remain constant while the Gate Off signal is active In this example this occurs when InA is logic low Note that the InA and InC inputs run off the internal 8MHz or 32MHz clock Those signals may not be synchronous with the selected clock For further information see the One Shot Pulse Mode description Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Function Description InA Input Pulse Width Modulation One Shot Gate Off for start stop control Counter Timer Module 453 Table 3 34 Counter Timer Modes Overview Watchdog Counter Reload Event Counting Gate Off for start stop control Frequency Measure Enable Frequency Measurement for Set Duration Pulse Measure Next complete pulse after trigger is measured Period Measure Next complete period after trigger is measured Qu
37. e stop bit location corresponding to each of the counters The bits of this register are not stored and merely act to stop the corresponding counter when set logic high comers 6 Couter7Stp 00 0 0 0 y 8 jCouter9Stp 00 y 9 Counter10 Stop Writing to this register is possible via 16 bit or 8 bit data transfers Counter Read Back Register Read Only This read only register is a dynamic function register that returns the current value held in the counter It is updated with the value stored in the internal counter each time it is read The internal counter is generally initialized with the value in the Counter Constant Register and its value is incremented or decremented according to the application The addresses corresponding to the Counter Read Back registers are given in Table 3 2 This register must be read using 16 bit accesses Counter Constant A Register Read Write This read write register is used to store the counter timer constant A value initial value for the various counting modes It is necessary to load the constant value into the counter in one clock cycle Thus access to this register is allowed on a 16 bit basis only The addresses corresponding to the Counter Constant A registers are given in Table 3 2 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual
38. ed Pin Connection Int_A Channel A In Channel In1 Index Outi Output 2 Write the following information A9E9H to Counter 1 Control Register located at base address plus an offset of 08H Bits logc Sets the counter to Quadrature Position Measurement Sets the output to active high Sets encoding to X2 and enables Channel A InA Enables Channel B InB Sets the Index condition to occur when A 1 and B 1 Provides for interrupt and reload to occur on index Not used Enables input debounce on InA InB and InC Not used Enables interrupts 3 Write the 16 bit value OH to Counter 1 Constant B Register located at base address plus an offset 44H for the counter reload value The Constant B Register contains the reload value of the counter Therefore in this example when an index pulse occurs and Channel A and B are equal to one the counter loads zero This value relies on the specific application While Counter Constant A is not used in this example it has other applications in Quadrature Position Measurement Refer to the description of Quadrature mode for further information Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual 4 The following is a waveform diagram of this example Since Quadrature mode does not accept external tr
39. eriod of signal is the time the signal is low added to the time the signal is high before it repeats InB can be used to input an external clock for period measurement Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input Period measurement can alternatively be internally clocked using control register bits 12 11 and 10 Available frequencies vary depending on carrier operational frequency InC can be used to externally trigger period measurement Additionally Period Measurement can be triggered internally via the Counter Trigger Register at the base address offset 04H An initial trigger software or external starts period measurement at the beginning of the next active period The period being measured serves as an enable control for an up counter whose value can be read from the Counter Read Back Register When triggered the counter is reset Then the active polarity of InA starts period measurement The counter increments by one for each clock pulse during the input signal period InA The resultant period is equivalent to the count value read from the Counter Read Back Register multiplied by the clock period A 1 75us output pulse will be generated at the counter output pin to signal the completion of a given measurement Note that the measured period may be in error by 1 clock cycle Reading a counter value o
40. ex channel is high during at least a portion of the phase you specify for reload The phase can be selected via the counter timer control register bits 9 8 and 7 as seen in Table 3 10 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 05 482 I O Server Module User s Manual COUNTER CONTROL REGISTER QUADRATURE POSITION MEASUREMENT Table 3 10 Counter Control Register Quadrature Position Measurement 1 The default state of the output pin is high output has pullup resistor installed Bit 3 specifies the active output polarity when the output is driven The quadrature measurement value can be read from the Counter Read Back Register Counter Timer Module An interrupt can be generated upon index reload or when the counter value equals the constant value stored in the Counter Constant A Register Interrupts must be enabled via the interrupt enable bit 15 of the Counter Control Register The interrupt type must also be selected via bits 10 and 11 of the Counter Control Register The interrupt will remain pending until released by setting the required bit of the Counter Timer Interrupt Status Clear register or setting bit 15 of the Counter Control register to 0 Note that interrupts in Quadrature Position Measurement are generated whenever the interrupt conditions exists If a pending interrupt is cleared but the interrupt conditions still exists another interr
41. f OXFFFF hex indicates that the pulse duration is longer than the current counter size and clock frequency can measure Upon reading of this overflow value you must select a slower frequency and re measure An interrupt can be generated upon completion of a given period measurement if enabled via the interrupt enable bit of the Counter Control Register bit 15 The interrupt will be generated upon completion of the first complete waveform cycle after the counter is triggered The interrupt will occur even if an external clock is selected but no clock signal is provided on InB The count value will be zero in this case The interrupt once driven active will remain pending until released by setting the required bit of the Interrupt Status Clear register at the base address offset 02H A pending interrupt can also be cleared by setting Counter Control register bit 15 to logic low Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual FUNCTION 2 1 0 Specifies the Counter Mode 3 Output Polarity Output Pin ACTIVE Level 0 Active LOW Default Active HIGH InA Polarity Signal Measured 00 Disabled Default Active LOW portion of the signal starts period measurement Active HIGH portion of the signal starts period measurement Disabled InB Polarity External Clock Input Disabled Default External Clock Enabled External Clock E
42. hdog timer time out occurs For example a counter constant value of 30 will provide a time out delay of 30 clock cycles of the selected clock However due to the asynchronous relationship between the trigger and the selected clock one clock cycle of error can be expected The counter can be read from the Counter Read Back register at any time during watchdog operation Upon time out the counter output pin returns to its inactive state The 105 482 will also issue an interrupt upon detection of a count value equal to 0 if enabled via bit 15 of the Counter Control Register This could be useful for alerting the host that a watchdog timer time out has occurred and may need to be reinitialized The interrupt will remain pending until the watchdog timer is reinitialized and the interrupt is released by setting the required bit of the Counter Timer Interrupt Status Clear register Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Output Polarity Output Pin ACTIVE Level 0 Active LOW Default Active HIGH InA Polarity Counter Reload ME l Active LOW In A 0 Counter Reinitialized In A 1 Inactive State Active HIGH 10 In A 0 Inactive State In A 1 Counter Reinitialized 11 Disabled Iu External Clock Input Disabled Default External Clock Enabled External Clock Enabled Disabled ee InC GPS PERS
43. iggers assume that a software trigger has already occurred InA LILII 5 Inc o E Se LI l IB reload reload Interrupts i i When the index condition is true the counter will reload the value in Counter Constant B register and an interrupt is generated The output remains active for as long as the Index condition holds true For further information on encoder counting index pulse conditions interrupts and outputs see the Quadrature Position Measurement description Pulse Width Modulation Example The objective for this example is to create a pulse width modulated with an active high pulse of 2us and a low pulse of 6us using 16 bit Counter The counter has an external active high gate off trigger and clock signals The output is active high Assume the external clock has a frequency of 500KHz The Gate Off signal will become active after 2 PWM cycles Additionally debounce and interrupts are enabled 1 Connect the inputs output to the following pins unpowered Connection In3_A In3_B In3_C Out3 Description Gate Off Ext Clock Ext Trigger Output 2 Write the following information BG6AH to Counter Control Register located at base address plus an offset of OCH Bits Logic 2 1 0 Sets the counter to Pulse
44. l 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 32 105 482 I O Server Module User s Manual Counter Timer Module PROGRAMMING EXAMPLES Table 3 18 Quadrature Pin Assignments for Counter 1 Note Make sure all inputs and outputs are properly grounded Table 3 19 Quadrature Counter Control Register 1 Settings The following section provides sample applications for each of the counter modes of operation This includes I O pin assignments register settings required calculations and waveform diagrams All examples assume 8 2 carrier operation even addressing and that all values are read and written in hex These assumptions may differ depending on the system and software being used Quadrature Position Measurement Example The objective for this example is to employ Quadrature Position Measurement using 16 bit Counter 1 Suppose that an encoder connected to the shaft of a motor provides three signals Two of the signals A and B are out of phase by 90 and provide directional information For this example Channel A will always lead B The third signal C is an Index pulse that is active every four revolutions A pulses Assume that X2 encoding is used and on the index pulse when Channel A and B are equal to one an active high output and interrupt are generated and the counter is reloaded to zero Additionally debounce is enabled 1 Connect the inputs output to the following pins unpower
45. led Not Used will return logic O when read Table 3 8 OS 482 Digital Input Register 1 Bit is initialized to logic 1 2 All bits labeled Not Used will return logic O when read Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 4 105 482 I O Server Module User s Manual Counter Timer Module Table 3 9 05 482 Interrupt Vector Register COUNTER CONTROL REGISTER Interrupt Vector Register Read Write Base 5CH The Interrupt Vector Register maintains an 8 bit interrupt pointer for all channels configured as input channels The Vector Register can be written with an 8 bit interrupt vector as seen in Table 3 9 This vector is provided to the carrier and system bus upon an active INTSEL cycle Reading or writing to this register is possible via 16 bit or 8 bit data transfers Interrupt Vector Register 07 06 05 04 03 02 01 00 Interrupts are released on access to the Interrupt Status register Issue of a software or hardware reset will clear the contents of this register to O Counter Control Register Read Write This register is used to configure counter timer functionality It defines the counter mode output polarity input polarity clock source debounce enable and interrupt enable The 05 482 has ten 16 bit Counter Timers The memory map addresses corresponding to the control registers are given in Table 3 2
46. measurement upon the active edge of the InA enable signal The Counter Constant A Register is not used for frequency measurement Do not write to this register while the counter is actively counting since this will cause the counter to be loaded with the Constant A value Reading the Counter Read Back Register will return the current count variable A minimum event pulse width InB is required for correct pulse detection with input debounce disabled A carrier operating at 8MHz requires an 125ns event pulse while a carrier operating at 32MHz requires an 31 25ns event pulse With debounce enabled a minimum event pulse width of 2 5us is required for correct pulse detection Programmable clock selection is not available for frequency measurement If the Interrupt Enable bit 15 of the Counter Control Register is set an interrupt is generated when the input InA enable pulse goes inactive An interrupt will remain pending until released by setting the required bit of the Interrupt Status Clear register at the base address offset 02H A pending interrupt can also be cleared by setting the Counter Control register bit 15 to logic low Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com IOS 482 I O Server Module User s Manual Counter Timer Module 2 D COUNTER CONTROL REGISTER FUNCTION FREQUENCY 2 1 0 Specifies the Counter Mode MEASUREMENT OPERATION 3 Output Polarity Output Pin AC
47. n the count down mode when low the counter counts up The counter will not count down below a count of zero Alternately when control register bits 9 and 8 are set to logic 01 or 10 the InC input functions as an external trigger input Event counting may also be internally triggered via the Trigger Control Register at the base address offset 04H The Counter Constant A Register holds the count to value constant Reading the Counter Read Back Register will return the current count variable The Counter Constant A value must not be left as 0 The counter upon trigger starts counting from 0 and since the counter would match the count to value the counter resets and starts counting from zero again If the Interrupt Enable bit of the Counter Control Register is set bit 15 an interrupt is generated when the number of input pulse events is equal to the Counter Constant A register value The internal counter is then cleared and will continue counting events until the counter constant A value is again reached and a new interrupt generated An interrupt will remain pending until released by setting the required bit of the Counters Interrupt Status Clear register at the base address offset 02H A pending interrupt can also be cleared by setting Control register bit 15 to logic low Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Bit s
48. nabled Disabled InC Polarity External Trigger 00 Disabled Default Active LOW Trigger 10 Active HIGH Trigger Disabled Clock Source 000 internal Defaut OSMHz 13 Input Debounce Enable BE Default og ve put Enabled Reject Source or Trigger Pulses noise less than or equal to 2 5us Using Debounce will add an error of up to 800ns when used for period measurement LL Not Used bit reads back as 0 Interrupt Enable Disable Interrupt Service Default Enable Interrupt Service 12 11 10 No Debounce Applied to any Counter Timer Module 2 O COUNTER CONTROL REGISTER INPUT PERIOD MEASUREMENT Table 3 16 Counter Control Register Input Period Measurement 1 The default state of the output pin is high output has pullup installed Bit 3 specifies the active output polarity when the output is driven 2 The available clock sources are determined by the operational frequency of the carrier board For an 8MHz carrier bit 0 of the Board Control Register located at the base address plus an offset of OH must be set low Fora 32MHz carrier the bit must be set high Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 105 482 I O Server Module User s Manual Counter Timer Module COUNTER CONTROL REGISTER One Shot Pulse Mode One Shot pulse mode provides an output pulse that is asserted one time
49. nal Trigger Disabled Ke 51530 2 The available clock sources are determined by the 000 SMHz eratona frequency ofthe 221 Control Register located at the base address plus an offset of OH must be set low For a 32MHz car he bit must be 13 Input Debounce Enable set high 9 Disabled Default No Debounce Applied to any Input Enabled Reject Gate Off or Trigger Pulses noise than or equal to 2 56 Interrupt Disable Interrupt Service Default Enable Interrupt Service Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 20 105 482 I O Server Module User s Manual Counter Timer Module COUNTER CONTROL REGISTER Watchdog Timer Operation The watchdog operation counts down from a programmed Counter Constant A value until it reaches 0 While counting the counter output will be in its active state the output polarity is programmable Upon time out the counter output will return to its inactive state and an optional interrupt may be generated Watchdog operation is selected by setting Counter Control Register bits 2 to 0 to logic 011 A timed out watchdog timer will not re cycle until it is reloaded and then followed with a new trigger Failure to cause a reload would generate an automatic time out upon re triggering since the counter register will contain the 0 it previously counted
50. nal triggers Triggers issued while running will cause the Constant A and B values to load at the wrong time In addition changing the Control register setting while running can also cause the Constant A and B values to load at the wrong time Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IOS 482 I O Server Module User s Manual Counter Timer Module 1 If the Interrupt Enable bit of the Counter Control Register is set bit 15 COUNTER CONTROL an interrupt is generated when the output pulse transitions from low to high REGISTER and also for transitions from high to low Thus an interrupt is generated at each pulse transition PULSE WIDTH MODULATION Bit s FUNCTION Table 3 11 Counter Control 2 1 0 Specifies the Counter Mode Register Pulse Wiath Modulation 3 Output Polarity Output Pin ACTIVE Level 1 The default state of the 0 Active LOW Default output pin is high output has Active HIGH pullup installed Bit 3 InA Polarity Gate Off Polarity specifies the active output Disabled Default polarity when the output is driven Active fen In 0 Counter is Enabled In A 1 Counter is Disabled Active HIGH In 0 Counter is Disabled In A 1 Counter is Enabled 11 Disabled ne LO External Clock Input Disabled Default External Clock Enabled 10 External Clock Enabled InC Polarity External Trigger 00 Disabled Default 10 Active HIGH Exter
51. nt counter size and clock frequency can measure Upon reading of this overflow value you must select a slower frequency and re measure An interrupt can be generated upon completion of a given pulse width measurement the pulse has returned to the opposite polarity if enabled via the interrupt enable bit of the Counter Control Register bit 15 The interrupt will remain pending until released by setting the required bit of the Interrupt Status Clear register at the base address offset 02H A pending interrupt can also be cleared by setting the Counter Control register bit 15 to logic low Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual FUNCTION Specifies the Counter Mode Output Polarity Output Pin ACTIVE Level 0 Active LOW Default Active HIGH InA Polarity Pulse Polarity to be Measured 00 Diabed Deaut 01 Active LOW Pulse is Measured Active HIGH Pulse is Measured Disabled InB Polarity External Clock Input Disabled Default External Clock Enabled 10 External Clock Enabled InC Polarity External Trigger 00 Disabled Default 10 Active HIGH Trigger Disabled Clock Source 000 internal Defaut OSMHz _ 2MHz 13 Input Debounce Enable EN a Default EN Enabled Reject Input Pulse Measured or Trigger Pulses noise less than or equal to 2 5us Using Debounce will add an error of up to 800ns
52. ot write to either of the Counter 7 Constant Registers They are not required for frequency measurement and writing to them can cause errors 4 The following is a waveform diagram of this example 5Qus lA 1 Jh T P P OP LEES l y Inc LI Output Interrupts i The frequency of the signal is calculated by dividing the value in the Counter 7 Read Back Register located at base address plus an offset of 28H by the duration of the InA enable signal Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal for calculations In this case the pulse length is 50us The value in the Read Back Register is 9 since there were nine high pulses during the enable signal Therefore the frequency is 9 50us which is equal to 180KHz Note that the counter must be re triggered before the next frequency measurement can take place Additionally the output pulse is active for 1 75us Since debounce was enabled the output pulse will occur 2 5 after the completion of the enable signal For further information see the Frequency Measurement Operation description Input Pulse Width Measurement Example The objective for this example is to use the Pulse Width Measurement Operation using 16 bit Counter 9 The pulse to be measured is active low Additionally the counter has an external clock and an active low External Trigger The output of the counter is active high and in
53. ptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area The field and logic side connectors are keyed to avoid incorrect assembly Description Description mA e Dm 3 mA 8 3 ma 9 ow 3 20 45 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual meg 22571 DOut5 w amp c 25 wb P2 pin assignments are unique to each IOS model see Table 2 1 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board 2471 9m sj The 05 482 is non isolated between the logic and field I O grounds since output common is electrically connected to the IOS module ground Consequently the field I O connections are not isolated from the carrier board and backplane Two ounce copper ground plane foil has been employed in the design of this model to help minimize the effects of ground bounce impedance drops and switching transients However care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections To minimize high levels of EMI the signal g
54. r Acromag assumes no responsibility for IOS Field Connector 2 PES 6 any errors that may appear I O Noise and Grounding Considerations 7 this manual and makes no commitment to update or 3 0 PROGRAMMING INFORMATION keep current the information contained in this manual No IOS IDENTIFICATION 7 part of this manual may be MEMORY MAP cerner ren eene 8 copied or reproduced in any Board Control 10 form without the prior written Interrupt Status Clear Register 10 consent of Acromag Inc Counter Trigger Register 11 Counter Stop 12 Counter Read Back Register 12 Counter Constant A Register 12 Counter Constant B Register 13 Digital Input 13 Digital Output Register 13 Interrupt Vector 14 COUNTER CONTROL REGISTER 14 Quadrature Position Measurement 15 Pulse Width Modulation 18 Watchdog Timer Operation 20 Event Counting Operation 22 Frequency Measurement Operation 24 Inp
55. r Pulse Width Measurement Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input Pulse Width Measurement can alternatively be internally clocked using control register bits 12 11 and 10 Available frequencies vary depending on carrier operational frequency InC can be used to externally trigger Pulse Width Measurement Additionally Pulse Width Measurement can be triggered internally via the Counter Trigger Register at the base address offset 04H An initial trigger software or external starts pulse width measurement at the beginning of the next active pulse For pulse width measurement the pulse width being measured serves as an enable control for an up counter whose value can be read from the Counter Read Back Register When triggered the counter is reset and then increments by one for each clock pulse while the input signal level remains in the active state high or low according to the programmed polarity of input InA The resultant pulse width is equivalent to the count value read from the Counter Read Back Register multiplied by the clock period An output pulse will be generated at the counter output pin to signal the completion of a given measurement Note that the measured pulse may be in error by 1 clock cycle Reading a counter value of OXFFFF hex indicates that the pulse duration is longer than the curre
56. represents an interrupt The length of the low portion of the InA pulse is calculated by multiplying the number in the Counter 9 Read Back Register located at base address plus an offset of 2CH by the period of the selected clock Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal for calculations In this case the value in the Read Back Register is 9 since there were nine high pulses during the active InA signal The period of the clock is calculated by taking the inverse of the frequency of the clock For this example the frequency was 100KHz Therefore the clock period is 1 100KHz which is equal to 10us The clock period multiplied by the Read Back Register 10us x 9 is equal to 90 5 the duration of the active low InA pulse This value may be in error by 1 clock period Note that the InA and InC inputs run off the internal 8MHz or 32MHz clock Those signals may not be synchronous with the selected clock The output pulse is active for 1 75us If debounce was enabled the output pulse will occur 2 5us after the completion of the input pulse Additionally the counter must be re triggered before any further measurements take place For more information see the Pulse Width Measurement description Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 40 105 482 I O Server Module User s Manual Counter Timer Module PROGRAMMING EXAMPLES Input
57. rnal clock for use in one shot Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input One Shot pulse mode can alternatively be internally clocked via control register bits 12 11 and 10 Available frequencies vary depending on carrier operational frequency InC can be used to externally trigger One Shot pulse mode Additionally a one shot pulse can be triggered internally via the Counter Trigger Register at the base address offset 04H An initial trigger software or external causes the one shot signal to be generated with no additional triggers required Additional triggers must not be input until the one shot pulse has completed count down of the Constant B value If the Interrupt Enable bit 15 of the Counter Control Register is set an interrupt is generated when the pulse transitions from low to high and also when the pulse transitions from high to low The interrupt will remain pending until released by setting the required bit of the Interrupt Status Clear register at the base address offset 02H A pending interrupt can also be cleared by setting the Counter Control register bit 15 to logic low Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com IOS 482 I O Server Module User s Manual Counter Timer Module 3 1 COUNTER CONTROL REGISTER ONE SHOT PULSE 2
58. round connection at the field I O port 50 should be used to provide a path for induced common mode noise and currents The ground path provides a low impedance path to reduce emissions This Section provides the specific information necessary to program and operate the IOS 482 module The 05 482 ID Space is shown in Table 3 1 Note that the base address for the IOS module ID space refer to the I O Server manual must be added to the addresses shown to properly access the ID information Execution of an ID Space Read operation requires 0 wait states Field Description Hex Offset Numeric From ID Base Value Address Acromag ID Code IOS Model Code Reserved e e e PROM Bytes 1 8 cR 1803 w nousa Not Used FS Counter Timer Module 7 1 Do Not Connect Pin has direct connection to FPGA Reserved for programming purposes TDI Pin has active pull up CONNECTORS I O Noise and Grounding Considerations 3 0 PROGRAMMING INFORMATION IOS Identification Space Read Only Table 3 1 05 482 ID Space Identification ID 1 The lOS model number is represented by a two digit code within the ID space The 05 482 is represented by 45 Hex Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions Qacromag com http www acromag com 8 105 482 I O Server Module User s Manual Counter Timer Module MEMORY MAP This board is addressable in the Server Module I O
59. s a 4 7K pullup resistor to 5V See Table 2 1 for the list of these signals and their corresponding pin assignments Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board Whena board is first produced and when any repair is made it is tested placed ina burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Choose the Support hyperlink in our web
60. site s top navigation row then select Embedded Board Products Support or go to http Awww acromag com subb_support cfm to access e Application Notes Frequently Asked Questions FAQ s Knowledge Base Tutorials Software Updates Drivers An email question can be submitted from within the Knowledge Base or through the Contact Us hyperlink at the top of any web page Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed at the bottom of this page When needed complete repair services are also available Counter Timer Module 45 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS PRELIMINARY SERVICE PROCEDURE WHERE TO GET HELP WWW acromag com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 46 105 482 I O Server Module User s Manual Counter Timer Module 6 0 SPECIFICATIONS PHYSICAL Table 6 1 Power Requirements 5V Maximum rise time of 100m seconds ENVIRONMENTAL Physical Configuration Single I O Server Module Length 4 030 in 102 36 mm Width 1 930 in 49 02 mm Board Thickness 0 062 in 1 59 mm Height 0 500 in 12 7 mm Connectors e lOS Logic Interface 50 pin female receptacle header AMP 173279 3 or equivalent e Field I O 50 pin female receptacle header AMP 173279 3 or eq
61. space to monitor and control the status and configuration of up to ten 16 bit counter timers two digital inputs and six digital outputs The I O space may be as large as 64 16 bit words 128 bytes but the 05 482 uses only a portion of this space The memory space address map for the 05 482 is shown in Table 3 2 Note that the base address for the 05 482 in memory space must be added to the addresses shown to properly access the 05 482 registers Accesses are generally performed on a 16 bit basis DO D15 but 8 bit DO D8 EO accesses are possible in most cases Table 3 2 05 482 Memory Byte Map 08 Board Control Register Counters Eur Status Clear Register E Counter Trigger Register Em Counter Stop Register Counter 1 Control Register EN Counter 2 Control Register ES Counter 3 Control Register Counter 4 Control Register EN Counter 5 Control Register EN Counter 6 Control Register Counter 7 Control Register Counter 8 Control Register Counter 9 Control Register Counter 10 Control Register Counter 1 Read Back Register Counter 2 Read Back Register Counter 3 Read Back Register Counter 4 Read Back Register Counter 5 Read Back Register Counter 6 Read Back Register o2 Counter 7 Read Back Register Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com IOS 482 I O Server Modul
62. terrupts are enabled Assume the external clock has a frequency of 100KHz 1 Connect the inputs output to the following pins unpowered Pin Connection 9 Pulse Input 9 Ext Clock In9_C Ext Trigger Out9 Output Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Counter Timer Module 3 PROGRAMMING 2 Write the following information 959DH to Counter 9 Control Register EXAMPLES located at base address plus an offset of 18H Bits logic _ Operation Table 3 29 Pulse Wiath 2 1 0 Sets the counter to Pulse Width Measurement Measurement Control Register 3 Sets the output to active high 9 5 4 Sets the Pulse input InA to active low 7 6 Enables the external clock input InB 9 8 Enables the external Trigger Input InC to active low 12 11 10 Sets the clock to an external source 13 Disables input debounce on InA and InC 14 Not used 15 Enables interrupts 3 Do not write to either of the Counter 9 Constant Registers They are not required for pulse width measurement and writing to them can cause errors 4 The following is a waveform diagram of this example Figure 3 7 Pulse Width I Li L L LLL Measurement waveform EMM M 9 events 4 InB InC Output In the figure each Interrupts
63. tion Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 48 105 482 I O Server Module User s Manual Counter Timer Module SPECIFICATIONS 32MHz IOS Carrier Selectable Counter Clock Frequencies 32MHz 16MHz 8MHz 4MHz Operation 2Mhz or External up to 8 2 Minimum I P Event 31 25ns Minimum Pulse Measurement 31 25ns Minimum Period Measurement 150ns Minimum Gate Trigger Pulse 31 25ns DIGITAL I O Digital I O Specifications for TTL Digital Inputs 1 2 and TTL Digital Outputs 1 6 are the same as the counter inputs and outputs See the Input Electrical Characteristics and Output Electrical Characteristics sections on the previous page Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com Counter Timer Module 4 105 482 I O Server Module User s Manual 9546 106 M9019 01 18 9 32018 487 501 peKp dsip 1ou sjoUBis 0 1 oyibigs 6 YALNNOO 19 91 YALNNOO 119 91 YALNNOO 119 91 1 sng 319071 IOHLNOO YAWIL YALNNOO sna vOdd 01 0 FINO 2 2 uaj4ng ILL AS i 0140 LONI YW444N 111 01230 TEN H3J4na8 111 OLJOLVNI H3J4na8 111 d 3OVJH3 NI
64. total time for the low portion of the pulse and divide it by the clock period For this example 6us 2us is equal to 3 Convert this value to Hex and the result is the total count that is placed in the appropriate Counter Constant Register Since it has been stipulated that the pulse is active high 3H is written to Counter 3 Constant A Register which contains the value for the non active low portion of the pulse The same procedure is used to calculate the Constant B value Take the total period of the high portion of the pulse and divide it by the period of the clock Here 2us 2us is equal to 1 Converting to hex 1H is written to Counter 3 Constant B Register since it contains the active high portion of the pulse 4 The following is a waveform diagram of this example hA Inc 1 r bus Gate Off Output Counter disgbled F2usd F 2us4 Interrupts i i i i Note that the InA and InC inputs run off the internal 8MHz or 32MHz clock Those signals may not be synchronous with the selected clock For further information see the Pulse Width Modulation Operation description Watchdog Timer Operation Example The objective for this example is to create a Watchdog Timer with a countdown length of 10us using 16 bit Counter 5 with an external active high counter reload clock and active low trigger signals The output is active high Assume the external clock has a frequency of 500KHz
65. trol Register bits 12 11 and 10 For example a counter constant value of 3 will provide a pulse duration of 3 clock cycles of the selected clock Note when the maximum internal clock frequency is selected 8MHz or 32 2 a delay of one extra clock cycle will be added to the counter constant value InA can be used as a Gate Off signal to stop and start the counter and thus the pulse width modulated output When InA is enabled via bits 5 and 4 of the control register for active low Gate Off input a logic low input will enable pulse width modulation counting while a logic high will stop PWM counting When InA is enabled for active high Gate Off operation a logic high will enable PWM counting while a logic low will stop PWM counting InB can be used to input an external clock for use in PWM Bits 7 and 6 must be set to either logic 01 or 10 Additionally the clock source bits 12 11 and 10 must be set to logic 101 to enable external clock input PWM can alternatively be internally clocked using control register bits 12 11 and 10 Available frequencies vary depending on the carrier operational frequency InC can be used to externally trigger Pulse Width Modulation generation Additionally PWM can be triggered internally via the Counter Trigger Register at the base address offset 04H An initial trigger software or external causes the pulse width modulated signal to be generated After an initial trigger do not issue additio
66. uivalent Power Module Requirements 105 482 Operating Temperature 40 to 85 C Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 Non Isolated Logic and field commons have a direct electrical connection Resistance to RFI Complies with EN61000 4 3 3 V m 80 to 1000MHz AM amp 900MHz Keyed and European Norm EN50082 1 with no digital upsets Conducted F Immunity Complies with EN61000 4 6 3V rms 150kHz to 80MHz and European Norm EN50082 1 with no digital upsets Electromagnetic Interference Immunity EMI No register upsets under the influence of EMI from switching solenoids commutator motors and drill motors Surge Immunity Not required for signal I O per European Norm EN50082 1 Electric Fast Transient Immunity EFT Complies with EN61000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN50082 1 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Counter Timer Module 4 7 Electrostatic Discharge ESD Immunity Complies with 61000 4 2 Level 3 8 enclosure port air discharge Level 2 4KV enclosure port contact discharge Level 1 2KV I O terminal contact discharge and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class B equipment Shielded cable with I O connections in a shielded
67. upt will be generated FUNCTION 2 1 0 Specifies the Counter Mode 3 Output Polarity Output Pin ACTIVE Level 0 Active LOW Default Active HIGH 5 4 InA Channel 00 Disabled Default 01 X1 Encoding 10 X2 Encoding 11 X4 Encoding ne Channel B Disabled Default Enabled 9 8 c Index Channel Interrupt Reload occurs when Index signal 1 and the A amp B input signals are as selected below See Control bits 11 amp 10 for additional interrupt load control 000 Disabled Default 101 110 and 111 also Disable 11 10 Interrupt Condition Select 00 No Interrupt Selected 11 Interrupt on Index but do not reload counter on Index Not Used bit reads back as 0 13 Input Debounce Enable Disabled Default Input Enabled Reject A B or Index Pulses less than or equal to 2 5us Not Used bit reads back as 0 Interrupt Enable Disable Interrupt Service Default Enable Interrupt Service No Debounce Applied to any Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual Counter Timer Module 1 7 Counter Control register bits 11 and 10 used to control the COUNTER CONTROL operation of the counter output signal With bits 11 and 10 set to 01 the REGISTER output signal will be driven active while the counter equals the counter Constant A value With bit 11 set
68. urs the counter resets to zero and starts incrementing again For this example an interrupt and output pulse will occur every five events Therefore 5H is written to the Counter 7 Constant A Register Note that all values are stored and read in Hex Counter Constant B Register is not used in Event Counting mode Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 105 482 I O Server Module User s Manual 4 The following is a waveform diagram of this example EN B Ee Inc p 5 Events 34 Gote Off4 F2 I 3 Interrupts i i The Gate Off signal is used in this example to pause the counter While the Gate Off signal is non active logic high the counter and output will remain constant Additionally the output pulse is active for 1 75us upon the detection of the final event For further information see the Event Counting Operation description Frequency Measurement Operation Example The objective for this example is to use the Frequency Measurement Operation using 16 bit Counter 7 The enable signal and the signal measured are active high Additionally the counter has an active low External Trigger The output of the counter is active low and interrupts and debounce are enabled Assume the enable pulse has a duration of 50 1 Connect the inputs output to the following pins unpowered Pin
69. ut Pulse Width Measurement 26 Input Period Measurement 28 One Shot Pulse Mode 30 Acromag Inc Tel 248 295 0310 248 624 9234 Email solutions acromag com http www acromag com IOS 482 I O Server Module User s Manual Counter Timer Module 3 PROGRAMMING EXAMPLES 32 TABLE OF Quadrature Position Measurement Example 32 CONTENTS Pulse Width Modulation Example 33 Watchdog Timer Operation Example 34 Event Counting Operation Example 36 Frequency Measurement Operation Example 37 Input Pulse Width Measurement Example 38 Input Period Measurement Example 40 One Shot Pulse Mode Example 41 4 0 THEORY OF OPERATION FIELD INPUT OUTPUT SIGNALS 44 2 44 Digital l O 5 52 Ile tek swe 44 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE 45 PRELIMINARY SERVICE PROCEDURE 45 WHERE TO GET HELP cesses 45 6 0 SPECIFICATIONS PHYSIGAL eed creo 46 ENVIRONMENTAL ener nennen 46 65 2222 2 1 47 DIGITAL l Q 2 5 5 P to enr event teens 48 SERVER MODULE COMPLIANCE 48 DRAWINGS
70. ve low Additionally the counter has an active low Gate Off and an active low External Trigger After every five events the event counter interrupts 1 Connect the inputs output to the following pins unpowered Table 3 24 Event Counting Pin Connection Pin Settings for Counter 7 In7_A Gate Off In7_B Event Input In7_C Ext Trigger Out7 Output Note Make sure all inputs and outputs are properly grounded 2 Write the following information 8194H to Counter 7 Control Register located at base address plus an offset of 14H Table 3 25 Event Counter Bis Logic Opeaion Control Register 7 Settings 2 1 0 Sets the counter to Event Counting mode 3 Sets the output to active low 5 4 Enable the Gate Off input InA to active low 7 6 Enables the Event input InB to active high 9 8 Enables the external Trigger Input InC to active low 12 11 10 Sets the counter to Event Counting mode 13 Disables input debounce on InA InB and InC 14 Not used 15 Enables interrupts 3 Write the 16 bit value 5H to Counter 7 Constant A Register located at the base address plus an offset of 3CH In Event Counting when the Constant A Register is equal to the value in the Counter 7 Read Back Register in this case located at base address plus an offset of 28H there is an output pulse and an interrupt Furthermore when this condition occ
71. writing to them can cause errors 4 The following is a waveform diagram of this example Figure 3 8 Input Period Measurement waveform InA Li JJ k 8 events _ InB nm x Er InC 4 S _ Output In the figure each represents an interrupt Interrupts The period of one cycle of the InA waveform is calculated by multiplying the number in the Counter 9 Read Back Register located at the base address plus an offset of 2CH by the period of the selected clock Note that the value in the Read Back Register is stored in Hex and requires conversion to decimal for calculations In this case the value in the Counter Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com IOS 482 I O Server Module User s Manual Counter Timer Module 4 1 PROGRAMMING 9 Read Back Register is 8 since there were eight high pulses during one EXAMPLES InA period The period of the clock is calculated by taking the inverse of the frequency of the clock For this example the frequency was 250KHz Therefore the clock period is 1 250KHz which is equal to 4us The clock period multiplied by the Read Back Register 4us x 8 is equal to 32us the period of the InA waveform This value may be in error by 1 clock period Note that the InA and InC inputs run off the internal 8MHz or 32MHz clock Those signals may not be synchronous with the selected clock The output pulse is active

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