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EFM8UB2 Reference Manual

1. Bit 7 6 5 4 3 2 1 0 REGODIS VBSTAT Reserved REGOMD STOPCF Reserved REG1MD Reserved Access RW R RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xC9 Bit Name Reset Access Description 7 REGODIS 0 RW Voltage Regulator REGO Disable This bit enables or disables the VREGO Voltage Regulator Value Name Description 0 ENABLED Enable the VREGO Voltage Regulator 1 DISABLED Disable the VREGO Voltage Regulator 6 VBSTAT 0 R VBUS Signal Status This bit indicates whether the device is connected to a USB network Value Name Description 0 NOT_SET VBUS signal currently absent device not attached to USB network 1 SET VBUS signal currently present device attached to USB network 5 Reserved Must write reset value 4 REGOMD 0 RW VREGO Voltage Regulator Mode This bit selects the Voltage Regulator mode for VREGO When REGOMD is set to 1 the VREGO voltage regulator operates in lower power suspend mode Value Name Description 0 NORMAL VREGO Voltage Regulator in normal mode 1 LOW POWER VREGO Voltage Regulator in low power mode 3 STOPCF 0 RW VREG1 Stop Mode Configuration This bit configures the VREG1 regulator s behavior when the device enters stop mode Value Name Description 0 ACTIVE VREG1 Regulator is still active in stop mode Any enabled reset source will reset the device 1 SHUTDOWN VREG1 Regulator is shut down in stop mode Only the RSTb pin or power c
2. Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address OxF5 Bit Name Reset Access Description 7 B7 1 RW Port 4 Bit 7 Input Mode Value Name Description 0 ANALOG P4 7 pin is configured for analog mode 1 DIGITAL P4 7 pin is configured for digital mode 6 B6 1 RW Port 4 Bit 6 Input Mode See bit 7 description 5 B5 1 RW Port 4 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 4 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 4 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 4 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 4 Bit 1 Input Mode See bit 7 description 0 BO 1 RW Port 4 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled Port 4 consists of 8 bits P4 0 P4 7 TQFP48 packages and is unavailable on LOFP32 and QFN32 packages silabs com Smart Connected Energy friendly Rev 0 2 106 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 22 PAMDOUT Port 4 Output Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address Bit Name Reset Access Description 7 B7 0 RW
3. AMXON setting Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name 000000 ADCON O P2 0 P1 0 P1 0 000001 ADCON 1 P2 1 P1 1 P1 1 000010 ADCON 2 P2 2 P1 2 P1 2 000011 ADCON 3 P2 3 P1 3 P1 3 000100 ADCON 4 P2 5 P1 4 P1 4 000101 ADCON 5 P2 6 P1 5 P1 5 000110 ADCON 6 P3 0 P1 6 P1 6 000111 ADCON 7 P3 1 P1 7 P1 7 001000 ADCON 8 P3 4 P2 0 P2 0 001001 ADCON 9 P3 5 P2 1 P2 1 001010 ADCON 10 P3 7 P2 2 P2 2 001011 ADCON 11 P4 0 P2 3 P2 3 001100 ADCON 12 P4 3 P2 4 P2 4 001101 ADCON 13 4 4 2 5 2 5 001110 ADCON 14 P4 5 P2 6 P2 6 001111 ADCON 15 P4 6 P2 7 P2 7 010000 ADCON 16 Reserved P3 0 P3 0 010001 ADCON 17 P0 3 PO0 0 0 010010 ADCON 18 P0 4 PO 1 PO 1 010011 ADCON 19 P1 1 4 4 010100 ADCON 20 P1 2 P0 5 P0 5 010101 ADCON 21 P1 0 Reserved Reserved 010110 ADCON 22 P1 3 Reserved Reserved 010111 ADCON 23 P1 6 Reserved Reserved 011000 ADCON 24 P1 7 Reserved Reserved 011001 ADCON 25 P2 4 Reserved Reserved 011010 ADCON 26 P2 7 Reserved Reserved silabs com Smart Connected Energy friendly Rev 0 2 113 EFM8UB2 Reference Manual Analog to Digital Converter ADCO AMXON setting Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name 011011 ADCON 27 P3 2 Reserved Reserved 011100 ADCON 28 P3 3 Reserved Reserved 011101 ADCON 29 P3 6 Reserved Reserved 011110 ADCON 30 Internal VREF 011111 ADCON 31 Ground 100000 ADCON 32 P4 1 Reser
4. Bit 7 6 4 3 2 1 0 ISOUD Reserved USBINH USBRST RESUME SUSMD SUSEN Access RW RW RW RW RW R RW Reset 0 0 0 0 0 0 0 0 Indirect Address 0 01 Bit Name Reset Access Description 7 ISOUD 0 RW Isochronous Update Mode This bit affects all IN Isochronous endpoints Value Name Description 0 IN TOKEN When firmware writes INPRDY 1 USBO will send the packet when the next IN token is received 1 SOF TOKEN When firmware writes INPRDY 1 USBO will wait for a SOF token before send ing the packet If an IN token is received before a SOF token USBO will send a zero length data packet 6 5 Reserved Must write reset value 4 USBINH 0 RW USBO Inhibit This bit is set to 1 following a power on reset POR or an asynchronous USBO reset Firmware should clear this bit after the USBO transceiver initialization is complete Firmware cannot set this bit to 1 Value Name Description 0 ENABLED USBO enabled 1 DISABLED USBO inhibited All USB traffic is ignored 3 USBRST 0 RW Reset Detect This bit is set to 1 by hardware when reset signalling is detected on the bus Upon this detection the following occur 1 The USBO Address is reset FADDR 0x00 2 Endpoint FIFOs are flushed 3 Control status registers are reset to 0x00 EOCSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH 4 USB register INDEX is reset to 0x00 5 USB interrupts excluding the suspend interrupt are enabled and their corresponding flags cleared 6
5. Bit 7 6 5 4 3 2 1 0 T3SPLIT TR3 T3CSS T3XCLK Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 SFR Address 0x91 Bit Name Reset Access Description 7 TF3H 0 RW Timer 3 High Byte Overflow Flag Set by hardware when the Timer 3 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 3 overflows from OxFFFF to 0x0000 When the Timer 3 interrupt is enabled setting this bit causes the CPU to vector to the Timer 3 interrupt service routine This bit must be cleared by firmware 6 0 RW Timer 3 Low Byte Overflow Flag Set by hardware when the Timer 3 low byte overflows from OxFF to 0x00 TF3L will be set when the low byte overflows regardless of the Timer 3 mode This bit must be cleared by firmware 5 TF3LEN 0 RW Timer 3 Low Byte Interrupt Enable When set to 1 this bit enables Timer 3 Low Byte interrupts If Timer 3 interrupts are also enabled an interrupt will be gen erated when the low byte of Timer 3 overflows 4 TF3CEN 0 RW Timer 3 Capture Enable When set to 1 this bit enables Timer 3 Capture Mode If TF3CEN is set and Timer 3 interrupts are enabled an interrupt will be generated based on the selected input capture source and the current 16 bit timer value in TMR3H TMR3L will be cop ied to TMR3RLH TMR3RLL 3 T3SPLIT 0 RW Timer 3 Split Mode Enable When this bit is set Timer 3 operates as two 8 bit timers wit
6. Bit 7 6 5 3 1 0 XCLKVLD XOSCMD Reserved XFCN Access R RW RW RW Reset 0 0x0 0 0x0 SFR Page ALL SFR Address 0xB1 Bit Name Reset Access Description 7 XCLKVLD 0 R External Oscillator Valid Flag Provides External Oscillator status and is valid at all times for all modes of operation except External CMOS Clock Mode and External CMOS Clock Mode with divide by 2 In these modes XCLKVLD always returns 0 Value Name Description 0 NOT_SET External Oscillator is unused or not yet stable 1 SET External Oscillator is running and stable 6 4 XOSCMD 0x0 RW External Oscillator Mode Value Name Description 0x0 DISABLED External Oscillator circuit disabled 0x2 CMOS External CMOS Clock Mode 0x3 CMOS_DIV_2 External CMOS Clock Mode with divide by 2 stage 0 4 RC DIV 2 RC Oscillator Mode with divide by 2 stage 0x5 C DIV 2 Capacitor Oscillator Mode with divide by 2 stage 0x6 CRYSTAL Crystal Oscillator Mode Ox7 CRYSTAL DIV 2 Crystal Oscillator Mode with divide by 2 stage 3 Reserved Must write reset value 2 0 XFCN 0 0 RW External Oscillator Frequency Control Controls the external oscillator bias current The value selected for this field depends on the frequency range of the external oscillator silabs com Smart Connected Energy friendly Rev 0 2 60 EFM8UB2 Reference Manual Reset Sources and Power Supply Monitor 9 Reset Sources and Power Supply Monitor
7. Parameter Description Min Units Tacs Address Control Setup Time 0 3 x ns Tacw Address Control Pulse Width 1 X 16 x Tsysc_k ns TACH Address Control Hold Time 0 x ns TALEH Address Latch Enable High Time 1 x 4 X ns TALEL Address Latch Enable Low Time 1 x 4 X ns Twos Write Data Setup Time 1 x 19 x TSySCLK ns TwbH Write Data Hold Time 0 3 x ns Tros Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns Note is equal to one period of the device system clock SYSCLK silabs com Smart Connected Energy friendly Rev 0 2 168 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 3 6 1 Multiplexed Mode Figure 15 6 Multiplexed 16 bit MOVX Timing on page 169 through Figure 15 8 Multiplexed 8 bit MOVX with Bank Select Timing on page 171 show the timing diagrams for the different External Memory Interface multiplexed modes and MOVX operations Muxed 16 bit Write A 15 8 m EMIF Address 8 MSBs from DPH A 15 8 m AD 7 0 m EMIF Address 8 LSBs from DPL EMIF Write Data i AD 7 0 m WRb WRb 1 gt WDS WDH i T T T 05 ACW gt Muxed 16 bit Read A 15 8 m EMIF Address 8 MSBs from DPH A 15 8 m AD 7 0 m EMIF Address 8 LSBs from DPL EMIF Read Dat
8. Configuration Logic EXTCLK 8 ECI X Channel 0 CEXO Mode Control Capture Compare Figure 14 1 PCA Block Diagram 14 2 Features 16 bit time base Programmable clock divisor and clock source selection Upto five independently configurable channels 8 or 16 bit PWM modes edge aligned operation Frequency output mode Capture on rising falling or any edge Compare function for arbitrary waveform generation Software timer internal compare mode Integrated watchdog timer silabs com Smart Connected Energy friendly Rev 0 2 137 EFM8UB2 Reference Manual Programmable Counter Array 14 3 Functional Description 14 3 1 Counter Timer The 16 bit PCA counter timer consists of two 8 bit SFRs PCAOL and PCAOH PCAOH is the high byte of the 16 bit counter timer and PCAOL is the low byte Reading PCAOL automatically latches the value of PCAOH into a snapshot register the following PCAOH read accesses this snapshot register Note Reading the PCAOL Register first guarantees an accurate reading of the entire 16 bit PCAO counter Reading PCAOH or PCAOL does not disturb the counter operation The CPS2 CPSO bits in the PCAOMD register select the timebase for the counter timer When the counter timer overflows from OxFFFF to 0x0000 the Counter Overflow Flag CF in PCAOMD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled
9. OxD8 ALL PCA Control 0 PCAOCPHO OxFC ALL PCA Channel 0 Capture Module High Byte PCAOCPH1 OxEA ALL PCA Channel 1 Capture Module High Byte PCAOCPH2 OxEC ALL PCA Channel 2 Capture Module High Byte PCAOCPH3 OxEE ALL PCA Channel 3 Capture Module High Byte PCAOCPH4 OxFE ALL PCA Channel 4 Capture Module High Byte PCAOCPLO OxFB ALL PCA Channel 0 Capture Module Low Byte PCAOCPL1 OxE9 ALL PCA Channel 1 Capture Module Low Byte PCAOCPL2 OxEB ALL PCA Channel 2 Capture Module Low Byte PCAOCPL3 OxED ALL PCA Channel 3 Capture Module Low Byte PCAOCPLA OxFD ALL PCA Channel 4 Capture Module Low Byte PCAOCPMO OxDA ALL PCA Channel 0 Capture Compare Mode PCAOCPM1 OxDB ALL PCA Channel 1 Capture Compare Mode PCAOCPM2 OxDC ALL PCA Channel 2 Capture Compare Mode OxDD ALL PCA Channel 3 Capture Compare Mode PCAOCPM4 OxDE ALL PCA Channel 4 Capture Compare Mode PCAOH OxFA ALL PCA Counter Timer High Byte PCAOL OxF9 ALL PCA Counter Timer Low Byte PCAOMD OxD9 ALL PCA Mode silabs com Smart Connected Energy friendly Rev 0 2 16 EFM8UB2 Reference Manual Special Function Registers Register Address SFR Pages Description PCONO 0x87 ALL Power Control PFEOCN OxAF ALL Prefetch Engine Control PSCTL Ox8F ALL Program Store Control PSW OxDO ALL Program Status Word REFOCN OxD1 ALL Voltage Reference Control REGO1CN
10. 14 4 4 PCAOH PCA Counter Timer High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address Bit Name Reset Access Description 7 0 PCAOH 0x00 RW PCA Counter Timer High Byte The PCAOH register holds the high byte MSB of the 16 bit PCA Counter Timer Reads of this register will read the con tents of a snapshot register whose contents are updated only when the contents of PCAOL are read When the WDTE bit is set to 1 the PCAOH register cannot be modified by firmware To change the contents of the PCAOH register the Watchdog Timer must first be disabled Rev 0 2 150 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Programmable Counter Array 14 4 5 PCAOCPMO PCA Channel 0 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xDA Bit Name Reset Access Description 7 16 0 RW Channel 0 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled Value Name Description 0 8 BIT 8 bit PWM selected 1 16_BIT 16 bit PWM selected 6 ECOM 0 RW Channel 0 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel
11. silabs com Smart Connected Energy friendly Rev 0 2 104 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 20 P4 Port 4 Pin Latch Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address 0xC7 Bit Name Reset Access Description 7 B7 1 RW Port 4 Bit 7 Latch Value Name Description 0 LOW P4 7 is low Set P4 7 to drive low 1 HIGH P4 7 is high Set P4 7 to drive or float high 6 B6 1 RW Port 4 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 4 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 4 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 4 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 4 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 4 Bit 1 Latch See bit 7 description 0 BO 1 RW Port 4 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input Port 4 consists of 8 bits P4 0 P4 7 TQFP48 packages and is unavailable on LOFP32 and QFN32 packages silabs com Smart Connected Energy friendly Rev 0 2 105 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 21 P4MDIN Port 4 Input Mode
12. B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address 0 0 bit addressable Bit Name Reset Access Description 7 B7 1 RW Port 3 Bit 7 Latch Value Name Description 0 LOW P3 7 is low Set P3 7 to drive low 1 HIGH P3 7 is high Set P3 7 to drive or float high 6 B6 1 RW Port 3 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 3 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 3 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 3 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 3 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 3 Bit 1 Latch See bit 7 description 0 BO 1 RW Port 3 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input Port 3 consists of 8 bits P3 0 P3 7 on TQFP48 packages and 1 bit P3 0 on LQFP32 and QFN32 packages silabs com Smart Connected Energy friendly Rev 0 2 101 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 17 P3MDIN Port 3 Input Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address OxF4 Bit Name Reset Access Description 7 B7 1 RW Port 3 Bit 7
13. Bit 7 6 5 4 3 2 1 0 ADCOGTL Access RW Reset OxFF SFR Page ALL SFR Address 0xC3 Bit 7 0 Name Reset Access Description ADCOGTL OxFF RW Greater Than Low Byte Least Significant Byte of the 16 bit Greater Than window compare register silabs com Smart Connected Energy friendly Rev 0 2 122 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 4 6 ADCOLTH ADCO Less Than High Byte Bit 7 6 5 4 3 2 1 0 ADCOLTH Access RW Reset 0x00 SFR Page ALL SFR Address 0xC6 Bit Name Reset Access Description 7 0 ADCOLTH 0x00 RW Less Than High Byte Most Significant Byte of the 16 bit Less Than window compare register 12 4 7 ADCOLTL ADCO Less Than Low Byte Bit 7 6 5 4 3 2 1 0 ADCOLTL Access RW Reset 0x00 SFR Page ALL SFR Address 0xC5 Bit Name Reset Access Description 7 0 ADCOLTL 0x00 RW Less Than Low Byte Least Significant Byte of the 16 bit Less Than window compare register silabs com Smart Connected Energy friendly Rev 0 2 123 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 4 8 ADCOCNO ADCO Control Bit 7 6 5 4 3 1 0 Name ADEN ADTM ADINT ADBUSY ADWINT ADCM Access RW RW RW RW RW RW Reset 0 0 0 0 0 0x0 SFR Page ALL SFR Address 0xE8 bit addressable Bit Name Reset Access Description 7 ADEN 0
14. SFR Page 0xF SFR Address 0xB9 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 2 SMB1SDD 0x0 RW SMBus 1 Start Detection Window These bits increase the hold time requirement between SDA falling and SCL falling for START detection Value Name Description 0x0 NONE No additional hold time requirement 0 1 SYSCLK Ox1 ADD 2 SYSCLKS Increase hold time window to 2 3 SYSCLKS 0 2 ADD 4 SYSCLKS Increase hold time window to 4 5 SYSCLKs 0x3 ADD 8 SYSCLKS Increase hold time window to 8 9 SYSCLKs 1 0 SMBOSDD 0x0 RW SMBus 0 Start Detection Window These bits increase the hold time requirement between SDA falling and SCL falling for START detection Value Name Description 0 0 No additional hold time window 0 1 SYSCLK Ox1 ADD 2 SYSCLKS Increase hold time window to 2 3 SYSCLKs 0 2 ADD 4 SYSCLKS Increase hold time window to 4 5 SYSCLKs 0x3 ADD 8 SYSCLKS Increase hold time window to 8 9 SYSCLKs silabs com Smart Connected Energy friendly Rev 0 2 239 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 18 5 SMBO Control Registers 18 5 1 SMBOCF SMBus 0 Configuration Bit 7 6 5 4 3 2 1 0 Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS Access RW RW R RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 SFR Address OxC1 Bit Name Reset Access Description 7 ENSMB
15. Regulator Condition SUSEN Bit BIASENB Bit REG1ENB Bit Relative Power Consumption Normal 0 0 0 highest Suspend 1 0 0 low Bias Disabled 1 0 extremely low Disabled x 1 1 off The voltage regulator is enabled in normal mode by default Normal mode offers the fastest response times for systems with dynami cally changing loads For applications which can tolerate a lower regulator bandwidth but still require a tightly regulated output voltage the regulator may be placed in suspend mode Suspend mode is activated when firmware sets the SUSEN bit Suspend mode reduces the regulator bias current at the expense of bandwidth For low power applications that can tolerate reduced output voltage accuracy and load regulation the internal bias current may be disa bled completely using the BIASENB bit If firmware sets the BIASENB bit the regulator will regulate the voltage using a method that is more susceptible to process and temperature variations In addition the actual output voltage may drop substantially under heavy loads The bias should only be disabled for light loads 5 mA or less or when the voltage regulator is disabled If the regulator is not used in a system the VREGIN and VDD pins should be connected together Firmware may disable the regulator by writing both the REG1ENB BIASENB bits in REG1CN to turn off the regulator and all associated bias currents silabs com Smart Connected Energy friendly
16. 1 CT1 GATEO CTO TOM Access RW RW RW RW RW RW Reset 0 0 0x0 0 0 0x0 SFR Page ALL SFR Address 0x89 Bit Name Reset Access Description 7 GATE1 0 RW Timer 1 Gate Control Value Name Description 0 DISABLED Timer 1 enabled when TR1 1 irrespective of INT1 logic level 1 ENABLED Timer 1 enabled only when TR1 1 and INT1 is active as defined by bit IN1PL in register ITO1CF 6 CT1 0 RW Counter Timer 1 Select Value Name Description 0 TIMER Timer Mode Timer 1 increments on the clock defined by T1M in the CKCONO register 1 COUNTER Counter Mode Timer 1 increments on high to low transitions of an external pin T1 5 4 1 0 0 RW Timer 1 Mode Select These bits select the Timer 1 operation mode Value Name Description 0x0 MODEO Mode 0 13 bit Counter Timer Ox1 MODE1 Mode 1 16 bit Counter Timer 0x2 MODE2 Mode 2 8 bit Counter Timer with Auto Reload 0x3 MODE3 Mode 3 Timer 1 Inactive 3 GATEO 0 RW Timer 0 Gate Control Value Name Description 0 DISABLED Timer 0 enabled when TRO 1 irrespective of INTO logic level 1 ENABLED Timer 0 enabled only when TRO 1 and INTO is active as defined by bit INOPL in register ITO1CF 2 CTO 0 RW Counter Timer 0 Select Value Name Description 0 TIMER Timer Mode Timer 0 increments on the clock defined by TOM in the CKCONO register 1 COUNTER Counter Mode Timer 0 increments on high to low transitions of an external pin TO silabs com Smart Connected Energy friendly Rev 0 2
17. EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 28 EOUTCNTH USBO OUT Endpoint Count High Bit 7 6 5 4 3 2 1 0 Reserved EOCH Access R R Reset 0x00 0 0 Indirect Address 0x17 Bit Name Reset Access Description 7 2 Reserved Must write reset value 1 0 EOCH 0 0 R OUT Endpoint Count High EOCH holds the upper 2 bits of the 10 bit number of data bytes in the last received packet in the current OUT endpoint FIFO This number is only valid while OPRDY 1 This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 211 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO 17 Serial Peripheral Interface SP10 17 1 Introduction The serial peripheral interface SPI module provides access to a flexible full duplex synchronous serial bus The SPI can operate as a master or slave device in both 3 wire or 4 wire modes and supports multiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select the SPI in slave mode or to disable master mode operation in a multi master environment avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers NSS can also be configured as a firmware controlled chip select output in master mode or disabled to reduce the number of pins required Additional general p
18. 0 Reset ComparatorO can be configured as a reset source by writing a 1 to the CORSEF flag ComparatorO should be enabled and allowed to settle prior to writing to CORSEF to prevent any turn on chatter on the output from generating an unwanted reset The ComparatorO reset is active low if the non inverting input voltage on CPO is less than the inverting input voltage on the device is put into the reset state After a ComparatorO reset the CORSEF flag will read 1 signifying ComparatorO as the reset source otherwise this bit reads 0 The state of the RSTb is unaffected by this reset silabs com Smart Connected Energy friendly Rev 0 2 64 EFM8UB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 7 PCA Watchdog Timer Reset The programmable watchdog timer WDT function of the programmable counter array PCA can be used to prevent software from running out of control during a system malfunction The PCA WDT function can be enabled or disabled by software as described in the PCA documentation The WDT is enabled and clocked by SYSCLK 12 following any reset If a system malfunction prevents user soft ware from updating the WDT a reset is generated and the WDTRSF bit in RSTSRC is set to 1 The state of the RSTb pin is unaffected by this reset 9 3 8 Flash Error Reset If a flash read write erase or program read targets an illegal address a system reset is generated This may occur due to any of the
19. 18 1 Introduction 18 2 Features 18 3 Functional Description 18 3 1 Supporting Documents Table of Contents 192 192 193 194 194 194 195 195 196 197 197 198 199 200 201 202 203 204 205 206 207 208 209 210 210 211 212 212 212 213 213 214 214 215 216 217 220 220 222 223 223 224 224 224 224 224 302 19 18 3 2 SMBus Protocol 18 3 3 Configuring the SMBus Module 18 3 4 Operational Modes 18 4 SMBus Global Setup Registers 18 4 1 SMBTC SMBus Timing and Pin Control 18 5 SMBO Control Registers 18 5 1 SMBOCF SMBus 0 Configuration 4 18 5 2 SMBOCNO SMBus 0 Control 18 5 3 SMBOADR SMBus 0 Slave Address 18 5 4 SMBOADM SMBus 0 Slave Address Mask 18 5 5 SMBODAT SMBus 0 Data 18 6 SMB1 Control Registers 18 6 1 SMB1CF SMBus 1 Configuration 18 6 2 SMB1CNO SMBus 1 Control 18 6 3 SMB1ADR SMBus 1 Slave Address 18 6 4 SMB1ADM SMBus 1 Slave Address Mask 18 6 5 SMB1DAT SMBus 1 Data Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 1 Introduction 19 2 Features 19 3 Functional Description 19 3 1 System Connections 19 3 2 Timer 0 and Timer 1 19 3 2 1 Operational Modes 19 3 3 Timer 2 Timer 3 Timer 4 and Timer 5 19 3 3 1 16 bit Timer with Auto Reload 19 3 3 2 8 bit Timers with Auto Reload d Mode 19 3 3 3 Capture Mode 19 4 Timer 0
20. 2 SMBO and SMB1 Slave Read Sequence During a read sequence an SMBus master reads data from a slave device The slave in this transfer will be a receiver during the ad dress byte and a transmitter during all data bytes When slave events are enabled INH 0 the interface enters Slave Receiver Mode to receive the slave address when a START followed by a slave address and direction bit READ in this case is received If hardware ACK generation is disabled upon entering Slave Receiver Mode an interrupt is generated and the ACKRQ bit is set The software must respond to the received slave address with an ACK or ignore the received slave address with a NACK If hardware ACK genera tion is enabled the hardware will apply the ACK for a slave address which matches the criteria set up by SMBOADR and SMBOADM The interrupt will occur after the ACK cycle If the received slave address is ignored by software or hardware slave interrupts will be inhibited until the next START is detected If the received slave address is acknowledged zero or more data bytes are transmitted If the received slave address is acknowledged data should be written to SMBODAT to be transmitted The interface enters slave transmitter mode and transmits one or more bytes of data After each byte is transmitted the master sends an acknowledge bit if the acknowledge bit is an ACK SMBODAT should be writ ten with the next data byte If the acknowledge bit is a NACK
21. 3 The packet is overwritten by an incoming OUT packet OPRDY 0 R OUT Packet Ready Hardware sets this read only bit and generates an interrupt when a data packet has been received This bit is cleared only when firmware writes 1 to the SOPRDY bit This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 204 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 21 USBO Endpoint0 Data Count Bit 7 6 5 4 3 2 1 0 Reserved EOCNT Access R R Reset 0 0x00 Indirect Address 0x16 Bit Name Reset Access Description 7 Reserved Must write reset value 6 0 EOCNT 0x00 R Endpoint 0 Data Count This 7 bit number indicates the number of received data bytes in the Endpoint 0 FIFO This number is only valid while OPRDY is 1 This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 205 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 22 EENABLE USBO Endpoint Enable Bit 7 6 4 3 2 1 0 Reserved EEN2 EEN1 Reserved Access R RW RW RW RW Reset 0 1 1 1 1 1 Indirect Address 0 1 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 1 RW Endpoint 3 Enable This bit enable
22. 8 bit dedicated clock clock rate generator Support for multiple masters on the same data lines silabs com Smart Connected Energy friendly Rev 0 2 4 EFM8UB2 Reference Manual System Overview System Management Bus I2C 5 0 and SMB1 The SMBus interface is a two wire bi directional serial bus The SMBus is compliant with the System Management Bus Specifica tion version 1 1 and compatible with the 12 serial bus The SMBus modules include the following features Standard up to 100 kbps and Fast 400 kbps transfer speeds Support for master slave and multi master modes Hardware synchronization and arbitration for multi master mode Clock low extending clock stretching to interface with faster masters Hardware support for 7 bit slave and general call address recognition Firmware support for 10 bit slave address decoding Ability to inhibit all slave states Programmable data setup hold times External Memory Interface EMIFO The External Memory Interface EMIF enables access of off chip memories and memory mapped devices connected to the GPIO ports The external memory space may be accessed using the external move instruction MOVX with the target address specified in either 8 bit or 16 bit formats Supports multiplexed and non multiplexed memory access Four external memory modes Internal only Split mode without bank select Split mode with bank select External only C
23. Figure 11 4 Full Crossbar Map EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 3 4 INTO and INT1 Two direct pin digital interrupt sources INTO and INT1 are included which can be routed to port 0 pins Additional I O interrupts are available through the port match function As is the case on a standard 8051 architecture certain controls for these two interrupt sour ces are available in the 0 1 registers Extensions to these controls which provide additional functionality are available in the ITO1CF register INTO and INT1 are configurable as active high or low edge or level sensitive The INOPL and IN1PL bits in the ITO1CF register select active high or active low the ITO and IT1 bits in TCON select level or edge sensitive The table below lists the possible configurations Table 11 3 INTO INT1 configuration ITO or IT1 INOPL or IN1PL INTO or INT1 Interrupt 1 0 Interrupt on falling edge 1 1 Interrupt on rising edge 0 0 Interrupt on low level 0 1 Interrupt on high level INTO and INT1 are assigned to port pins as defined in the ITO1CF register INTO and INT1 port pin assignments are independent of any crossbar assignments and be assigned to pins used by crossbar peripherals INTO and INT1 will monitor their assigned port pins without disturbing the peripheral that was assigned the port pin via the crossbar To assign a port pin only to INTO and or 1 config ur
24. 13 3 3 SFR Access Control Registers 19 3 3 1 SFRPAGE SFR Page 19 4 Flash Memory 20 4 1 Introduction 20 4 2 Features 21 4 3 Functional Description 22 4 3 1 Security Options 22 4 3 2 Programming the Flash Memory 23 4 3 2 1 Flash Lock and Key Functions 23 4 3 2 2 Flash Page Erase Procedure 23 4 3 2 3 Flash Byte Write Procedure 23 4 3 3 Flash Write and Erase Precautions 24 4 4 Flash Control Registers 25 4 4 1 PSCTL Program Store Control 25 4 4 2 FLKEY Flash Lock and Key 26 4 4 3 FLSCL Flash Scale 27 5 Device Identification 28 5 1 Unique Identifier 28 6 Interrupts 29 Table of Contents 296 6 1 2 29 6 2 Interrupt Sources and Vectors 29 6 2 1 Interrupt Priorities e 2 ll os os o s 7 2 0 29 6 2 2 Interrupt Latency 4 ay ue cs V ue MP Bg 120 6 2 3 5 wo 990 6 3 Interrupt Control Registers 5 1002 6 3 1 IE Interrupt Enable 5 5 1 32 6 3 2 IP Interrupt Priority Pd UIN 6 3 3 EIE1 Extended Interrupt Enable 1 ode GO Ro Ev eck fe GE 6 3 4 EIP1 Extended Interrupt 47 134 6 3 5 EIE2 Extended Interrupt Enable2
25. ADWINT Effects ADWINT 1 ADCOGTH L 0x0080 0x0080 0x007F 0x0041 ADCOLTH L 0x0040 0x0040 ADWINT Not Affected 0x003F 0x0000 ADWINT 1 silabs com Smart Connected Energy friendly Rev 0 2 119 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 3 8 Temperature Sensor An on chip analog temperature sensor is available to the ADC multiplexer input To use the ADC to measure the temperature sensor the ADC mux channel should select the temperature sensor The temperature sensor transfer function is shown in Figure 12 4 Temper ature Sensor Transfer Function on page 120 The output voltage is the positive ADC input when the ADC multiplexer is set correctly The TEMPE bit in register REFOCN enables disables the temperature sensor While disabled the temperature sensor de faults to a high impedance state and any ADC measurements performed on the sensor will result in meaningless data Refer to the electrical specification tables for the slope and offset parameters of the temperature sensor V temp Slope x Temp Offset Temp c V temp Offset Slope Slope V deg C Voltage ie 4 offset V at 0 deg Celsius Temperature Figure 12 4 Temperature Sensor Transfer Function 12 3 8 1 Temperature Sensor Calibration The uncalibrated temperature sensor output is extremely linear and suitable f
26. 261 EFM8UB2 Reference Manual Timers 0 1 Timer2 Timer3 Timer4 and Timer5 Bit Name Reset Access Description 1 0 TOM 0 0 RW Timer 0 Mode Select These bits select the Timer 0 operation mode Value Name Description 0x0 MODEO Mode 0 13 bit Counter Timer Ox1 MODE 1 Mode 1 16 bit Counter Timer 0 2 MODE2 Mode 2 8 bit Counter Timer with Auto Reload 0x3 MODE3 Mode 3 Two 8 bit Counter Timers silabs com Smart Connected Energy friendly Rev 0 2 262 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 4 CKCON1 Clock Control 1 Bit 7 6 5 4 3 2 1 0 Name Reserved T5MH T5ML TAMH TAML Access R RW RW RW RW Reset 0 0 0 0 0 0 SFR Page OxF SFR Address OxEA Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 T5MH 0 RW Timer 5 High Byte Clock Select Selects the clock supplied to the Timer 5 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL CLOCK Timer 5 high byte uses the clock defined by T5XCLK TMR5CN 1 SYSCLK Timer 5 high byte uses the system clock 2 T5ML 0 RW Timer 5 Low Byte Clock Select Selects the clock supplied to Timer 5 If Timer 5 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer Value Name Description 0 EXTERNAL CLOCK Timer 5 low byte uses the c
27. D X D X Ox1 MODE 1 Mode 1 Differential 1 forced D 1 D 0 0x2 MODE2 Mode 2 Differential 0 forced D 0 D 1 0x3 MODE3 Mode 3 Single Ended 0 forced D 0 D 0 2 DFREC 0 R Differential Receiver The state of this bit indicates the current differential value present on the D and D lines when PHYEN 1 Value Name Description 0 DIFFERENTIAL ZERO Differential 0 signalling on the bus 1 DIFFERENTIAL ONE Differential 1 signalling on the bus silabs com Smart Connected Energy friendly Rev 0 2 190 EFM8UB2 Reference Manual Universal Serial Bus USBO Bit Name Reset Access Description 1 Dp 0 R D Signal Status This bit indicates the current logic level of the D pin Value Name Description 0 LOW D signal currently at logic 0 1 HIGH D signal currently at logic 1 0 Dn 0 R D Signal Status This bit indicates the current logic level of the D pin Value Name Description 0 LOW D signal currently at logic 0 1 HIGH D signal currently at logic 1 16 4 2 USBOADR 05 0 Indirect Address Bit 7 6 5 4 3 2 1 0 BUSY AUTORD USBOADR Access RW RW RW Reset 0 0 0x00 SFR Page ALL SFR Address 0x96 Bit Name Reset Access Description 7 BUSY 0 RW 05 0 Register Read Busy Flag This bit is used during indirect USBO register accesses 6 AUTORD 0 RW USBO Register Auto Read Flag This bit is used for block FIFO r
28. EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 12 P2 Port 2 Pin Latch Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address 0xAO bit addressable Bit Name Reset Access Description 7 B7 1 RW Port 2 Bit 7 Latch Value Name Description 0 LOW P2 7 is low Set P2 7 to drive low 1 HIGH P2 7 is high Set P2 7 to drive or float high 6 B6 1 RW Port 2 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 2 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 2 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 2 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 2 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 2 Bit 1 Latch See bit 7 description 0 BO 1 RW Port 2 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input silabs com Smart Connected Energy friendly Rev 0 2 97 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 13 P2MDIN Port 2 Input Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
29. Set to 1 by hardware when a byte of data has been received by UART1 set at the STOP bit sampling time RI remains set while the receive FIFO contains any data Hardware will clear this bit when the receive FIFO is empty If a read of SBUF1 is performed when RI is cleared the most recently received byte will be returned silabs com Smart Connected Energy friendly Rev 0 2 287 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 2 SMOD1 UART1 Mode Bit 7 6 5 4 3 2 1 0 SPT PE SDL XBE SBL Access RW RW RW RW RW RW Reset 0 0 0 0 0 3 0 0 SFR Page ALL SFR Address OxE5 Bit Name Reset Access Description 7 MCE 0 RW Multiprocessor Communication Enable This function is not available when hardware parity is enabled Value Name Description 0 MULTI_DISABLED RI will be activated if the stop bits are 1 1 MULTI_ENABLED RI will be activated if the stop bits and extra bit are 1 The extra bit must be ena bled using XBE 6 5 SPT 0x0 RW Parity Type Value Name Description 0x0 ODD_PARTY Odd 0x1 EVEN_PARITY Even 0x2 MARK_PARITY Mark 0x3 SPACE_PARITY Space 4 PE 0 RW Parity Enable This bit activates hardware parity generation and checking The parity type is selected by the SPT field when parity is ena bled Value Name Description 0 PARITY_DISABLED Disable hardware parity 1 PARITY ENABLED Enable ha
30. ing interrupt enable flag ECF for CF ECOV for COVF and ECCFn for each CCFn PCAO interrupts must be globally enabled before any individual interrupt sources are recognized by the processor PCAO interrupts are globally enabled by setting the EA bit and the EPCAQ bit to logic 1 14 3 3 Capture Compare Modules Each module can be configured to operate independently in one of six operation modes edge triggered capture software timer high speed output frequency output 8 bit pulse width modulator or 16 bit pulse width modulator Table 14 2 PCAOCPM and PCAOPWM Bit Settings for PCA Capture Compare Modules on page 139 summarizes the bit settings in the PCAOCPMn and PCAOPWM registers used to select the PCA capture compare module s operating mode Setting the ECCFn bit in a PCAOCPMnh register enables the mod ule s CCFn interrupt silabs com Smart Connected Energy friendly Rev 0 2 138 EFM8UB2 Reference Manual Programmable Counter Array PCAO Table 14 2 and PCAOPWM Bit Settings for PCA Capture Compare Modules Operational Mode PCAOCPMn Bit Name PWM16 ECOM CAPN MAT Bit Number 7 6 3 2 0 Capture triggered by positive edge on CEXn x x 1 0 0 0 0 A Capture triggered by negative edge on CEXn X X 0 1 0 0 0 A Capture triggered by any transition on CEXn X X 1 1 0 0 0 A Software Timer X B 0 0 1 0 0 A High Speed Output X B 0 0 1 1 0 A Frequency Output X B 0 0 0 1 1 A 8
31. 0 DISABLED Disable the High Frequency Oscillator 1 ENABLED Enable the High Frequency Oscillator 6 IFRDY 1 R Oscillator Frequency Ready Flag Value Name Description 0 NOT SET The Internal High Frequency Oscillator is not running at the programmed frequen Cy 1 SET The Internal High Frequency Oscillator is running at the programmed frequency 5 SUSPEND 0 RW Oscillator Suspend Enable Setting this bit to logic 1 places the internal oscillator in suspend mode The internal oscillator resumes operation when one of the suspend mode awakening events occurs 4 2 Reserved Must write reset value 1 0 IFCN 0 0 RW Oscillator Frequency Divider Control The Internal High Frequency Oscillator is divided by the IFCN bit setting after a divide by 4 stage Value Name Description 0x0 SYSCLK DIV 8 SYSCLK can be derived from Internal H F Oscillator divided by 8 1 5 MHz Ox1 SYSCLK DIV 4 SYSCLK can be derived from Internal H F Oscillator divided by 4 3 MHz 0 2 SYSCLK_DIV_2 SYSCLK can be derived from Internal H F Oscillator divided by 2 6 MHz 0x3 SYSCLK_DIV_1 SYSCLK can be derived from Internal H F Oscillator divided by 1 12 MHz silabs com Smart Connected Energy friendly Rev 0 2 58 EFM8UB2 Reference Manual Clocking and Oscillators 8 4 4 LFOOCN Low Frequency Oscillator Control Bit 7 6 5 4 3 2 1 0 OSCLEN OSCLRDY OSCLF OSCLD Access RW R RW RW Reset 0 1 Varies 0x3 SFR Page ALL SFR
32. 1 OW Power tack Convert or Convert Mode ADTM 0 Track or Convert Convert Track B ADCO Timing for Internal Trigger Source Write 1 to ADBUSY Timer Overflow 123 45 6 7 8 9 1011 12 13 14 15 16 17 18 meu Clocks Low Power or Convert ADTM 1 Track Convert Low Power Mode 1234567289 1011 12 13 14 cee Figure 12 3 Track and Conversion Example Timing Normal Non Burst Operation silabs com Smart Connected Energy friendly Rev 0 2 116 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 3 6 Output Formatting The conversion code format differs between single ended and differential modes The registers ADCOH and ADCOL contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion Data can be right justified or left justified depending on the setting of the ADLJST bit When in single ended mode conversion codes are represented as 10 bit unsigned integers Inputs are measured from 0 to VREF x 1023 1024 Unused bits in the ADCOH and ADCOL registers set to 0 Table 12 3 Single Ended Output Code Example Input Voltage Right Justified ADLJST 0 Left Justified ADLJST 1 ADCOH L ADCOH L VREF x 1023 1024 OxO3FF OxFFCO VREF x 512 1024 0x0200 0x8000 VREF x 256 1024 0x0100 0x4000 0 0x0000 0x0000 When in differential mode conversion codes are rep
33. 1 ENABLED Enable Endpoint 1 IN interrupts 0 EPOE 1 RW Endpoint 0 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 0 interrupts 1 ENABLED Enable Endpoint 0 interrupts This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 201 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 18 OUT1IE USBO OUT Endpoint Interrupt Enable Bit 7 6 5 4 3 2 1 0 Reserved OUT3E OUT2E OUT1E Reserved Access R RW RW RW R Reset 0x0 1 1 1 0 Indirect Address 0 09 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 OUT3E 1 RW OUT Endpoint 3 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 3 OUT interrupts 1 ENABLED Enable Endpoint 3 OUT interrupts 2 OUT2E 1 RW OUT Endpoint 2 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 2 OUT interrupts 1 ENABLED Enable Endpoint 2 OUT interrupts 1 OUT1E 1 RW OUT Endpoint 1 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 1 OUT interrupts 1 ENABLED Enable Endpoint 1 OUT interrupts 0 Reserved Must write reset value This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 202 EFM8UB2 Reference Manual Universal Serial Bus
34. 1 when in Master Mode In slave mode data on MOSI is sampled in the center of each data bit In master mode data on MISO is sampled one SYSCLK before the end of each data bit to provide maximum settling time for the slave device silabs com Smart Connected Energy friendly Rev 0 2 221 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO 17 4 2 SPIOCNO SPIO Control Bit 7 6 5 4 3 2 1 0 SPIF WCOL MODF RXOVRN NSSMD TXBMT SPIEN Access RW RW RW RW RW R RW Reset 0 0 0 0 Ox1 1 0 SFR Page ALL SFR Address OxF8 bit addressable Bit Name Reset Access Description 7 SPIF 0 RW SPIO Interrupt Flag This bit is set to logic 1 by hardware at the end of a data transfer If SPI interrupts are enabled an interrupt will be gener ated This bit is not automatically cleared by hardware and must be cleared by firmware 6 WCOL 0 RW Write Collision Flag This bit is set to logic 1 if a write to SPIODAT is attempted when TXBMT is 0 When this occurs the write to SPIODAT will be ignored and the transmit buffer will not be written If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 5 MODF 0 RW Mode Fault Flag This bit is set to logic 1 by hardware when a master mode collision is detected NSS is low MSTEN 1 and NSSMD 01 If SPI interrupts are enabled
35. 9 1 Introduction Reset circuitry allows the controller to be easily placed in a predefined default condition On entry to this reset state the following occur The core halts program execution Module registers are initialized to their defined reset values unless the bits reset only with a power on reset External port pins are forced to a known state Interrupts and timers are disabled registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power on reset contents of RAM are unaffected during a reset any previously stored data is preserved as long as power is not lost The Port I O latch es are reset to 1 in open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0 0000 Reset Sources Supply Monitor or Power up XX Missing Clock Detector XX Watchdog Timer gt lt ST lt Software Reset gt ST system reset Comparator 0 X XX XX X Flash Error V USB Reset V Figure 9 1 Reset Sources Block Diagram 9 2 Features Reset sources on the device include Power on reset External reset pin Compara
36. CMPO Negative Input Multiplexer Channels Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name Register CMPOMX 000 0 2 1 1 1 P1 1 001 CMPON 1 P2 6 P1 5 1 5 010 2 P3 5 P2 1 P2 1 011 CMPON 3 4 4 2 5 2 5 100 4 P0 4 PO 1 PO 1 101 CMPON 5 Reserved Reserved Reserved 110 CMPON 6 Reserved Reserved Reserved 111 7 Reserved Reserved Reserved Table 13 3 CMP1 Positive Input Multiplexer Channels CMXP Setting in Reg Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name ister CMP1MX 000 CMP1P 0 P2 2 P1 2 P1 2 001 CMP1P 1 P3 0 P1 6 P1 6 010 CMP1P 2 P3 7 P2 2 P2 2 011 CMP1P 3 P4 5 Reserved Reserved 100 CMP1P 4 P1 1 P0 4 P0 4 101 CMP1P 5 Reserved Reserved Reserved 110 CMP1P 6 Reserved Reserved Reserved 111 CMP1P 7 Reserved Reserved Reserved silabs com Smart Connected Energy friendly Rev 0 2 129 EFM8UB2 Reference Manual Comparators CMPO and 1 Table 13 4 CMP1 Negative Input Multiplexer Channels CMXN Setting in Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name Register CMP1MX 000 1 0 2 3 1 3 1 3 001 CMP1N 1 P3 1 P1 7 P1 7 010 CMP1N 2 P4 0 P2 3 P2 3 011 CMP1N 3 P4 6 Reserved Reserved 100 CMP1N 4 P1 2 P0 5 P0 5 101 CMP1N 5 Reserved Reserved Reserved 110 1 6 Reserved Reserved Reserved 111 CMP1N 7
37. PnSKIP PnMDIN Comparator 0 Input P1 0 1 PnSKIP PnMDIN Voltage Reference VREF P1 5 TQFP48 REFOCN PnSKIP PnMDIN P0 7 LQFP32 QFN32 External Oscillator Input XTAL2 P0 7 TQFP48 HFOOCN PnSKIP PnMDIN Not available LQFP32 QFN32 External Oscillator Output XTAL 1 P0 6 TQFP48 HFOOCN PnSKIP PAMDIN Not available LQFP32 QFN32 silabs com Smart Connected Energy friendly Rev 0 2 80 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 3 2 2 Port I O Digital Assignments The following table displays the potential mapping of port I O to each digital function Table 11 2 Port I O Assignment for Digital Functions Digital Function UARTO SPIO SMBO CPO CPOA CP1 CP1A SYSCLK PCAO 4 and TO T1 UART1 SMBus1 Potentially Assignable Port Pins Any port pin available for assignment by the crossbar This includes P0 0 P3 7 pins which have their PnSKIP bit set to 0 The crossbar will always assign UARTO pins to P0 4 and P0 5 SFR s Used For Assignment XBRO XBR1 XBR2 External Interrupt 0 External Interrupt 1 P0 0 PO 7 ITO1CF Conversion Start CNVSTR P1 4 TQFP48 ADCOCNO P0 6 LQFP32 QFN32 External Clock Input EXTCLK P0 3 LQFP32 QFN32 CLKSEL Any pin used for GPIO P0 0 P3 7 POSKIP P1SKIP P2SKIP P3SKIP silabs com Smart Connected Energy friendly Rev
38. R W will be logic 1 READ Serial data is then received from the slave on SDA while the SMBus outputs the serial clock The slave transmits one or more bytes of serial data If hardware ACK generation is disabled the ACKRQ is set to 1 and an interrupt is generated after each received byte Software must write the ACK bit at that time to ACK or NACK the received byte With hardware ACK generation enabled the SMBus hardware will automatically generate the ACK NACK and then post the interrupt It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled Writing a 1 to the ACK bit generates an ACK writing a 0 generates a NACK Software should write a 0 to the ACK bit for the last data transfer to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated The interface will switch to Master Transmitter Mode if SMBODAT is written while an active Master Receiver Figure 18 7 Typical Master Read Se quence on page 234 shows a typical master read sequence as it appears on the bus and Figure 18 8 Master Read Sequence State Diagram EHACK 1 on page 235 shows the corresponding firmware state machine Two received data bytes are shown though any number of bytes may be received Notice that the data byte transferred interrupts occur at different places in the sequence depending on whether hardware ACK g
39. Rev 0 2 142 EFM8UB2 Reference Manual Programmable Counter Array 14 3 7 Frequency Output Mode Frequency Output Mode produces a programmable frequency square wave on the module s associated CEXn pin The capture compare module high byte holds the number of PCA clocks to count before the output is toggled The frequency of the square wave is then defined as follows EL PA CEXn 2x Note A value of 0x00 in the PCAOCPHn register is equal to 256 for this equation Where is the frequency of the clock selected by the CPS2 0 bits in the PCA mode register PCAOMD The lower byte of the cap ture compare module is compared to the PCA counter low byte on a match n is toggled and the offset held in the high byte is added to the matched value in PCAOCPLn Frequency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCAOCPMn register Note The MATn bit should normally be set to 0 in this mode If the MATn bit is set to 1 the CCFn flag for the channel will be set when the 16 bit PCAO counter and the 16 bit capture compare register for the channel are equal PCAOCPLn 8 bit Adder PCAOCPHn Compare Enable 8 bit ECOMn Comparator CEXn TOGn Toggle Enable PCA Clock Figure 14 5 PCA Frequency Output Mode 14 3 8 PWM Waveform Generation The PCA can generate edge aligned PWM waveforms with resolutions of 8 or 16 bits PWM resolution depends on th
40. Rev 0 2 45 EFM8UB2 Reference Manual Power Management and Internal Regulators 7 8 Power Management Control Registers 7 8 1 PCONO Power Control Bit 7 6 5 4 3 2 1 0 GF5 GF4 GF3 GF2 GF1 GFO STOP IDLE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0x87 Bit Name Reset Access Description 7 GF5 0 RW General Purpose Flag 5 This flag is a general purpose flag for use under firmware control 6 GF4 0 RW General Purpose Flag 4 This flag is a general purpose flag for use under firmware control 5 GF3 0 RW General Purpose Flag 3 This flag is a general purpose flag for use under firmware control 4 GF2 0 RW General Purpose Flag 2 This flag is a general purpose flag for use under firmware control 3 GF1 0 RW General Purpose Flag 1 This flag is a general purpose flag for use under firmware control 2 GFO 0 RW General Purpose Flag 0 This flag is a general purpose flag for use under firmware control 1 STOP 0 RW Stop Mode Select Setting this bit will place the CIP 51 in Stop mode This bit will always be read as 0 0 IDLE 0 RW Idle Mode Select Setting this bit will place the CIP 51 in Idle mode This bit will always be read as 0 silabs com Smart Connected Energy friendly Rev 0 2 46 EFM8UB2 Reference Manual Power Management and Internal Regulators 7 8 2 REGO1CN Voltage Regulator Control
41. SMBODAT should not be written to before SI is cleared an error condition may be generated if SMBODAT is written following a received NACK while in slave transmitter mode The interface exits slave trans mitter mode after receiving a STOP The interface will switch to slave receiver mode if SMBODAT is not written following a Slave Trans mitter interrupt Figure 18 11 Typical Slave Read Sequence on page 238 shows a typical slave read sequence as it appears on the bus The corresponding firmware state diagram combined with the slave read sequence is shown in Figure 18 10 Slave State Dia gram EHACK 1 on page 237 Two transmitted data bytes are shown though any number of bytes may be transmitted Notice that all of the data byte transferred interrupts occur after the ACK cycle in this mode regardless of whether hardware ACK generation is enabled Interrupts with Hardware ACK Enabled EHACK 1 Interrupts with Hardware ACK Disabled EHACK 0 Received by SMBus S START Interface STOP 5 R READ Transmitted by SLA Slave Address SMBus Interface Figure 18 11 Typical Slave Read Sequence silabs com Smart Connected Energy friendly Rev 0 2 238 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 18 4 SMBus Global Setup Registers 18 4 1 SMBTC SMBus Timing and Pin Control Bit 7 6 5 4 3 2 1 0 Reserved SMB1SDD SMBOSDD Access RW RW RW Reset 0x0 0x0 0x0
42. Setting the ECF bit in PCAOMD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Clearing the CIDL bit in the PCAOMD register allows the PCA to continue normal operation while the CPU is in Idle mode Table 14 1 PCA Timebase Input Options CPS2 0 Timebase 000 System clock divided by 12 001 System clock divided by 4 010 Timer 0 overflow 011 High to low transitions on max rate system clock divided by 4 1 100 System clock 101 External oscillator source divided by 8 1 110 Low frequency oscillator divided by 8 1 111 Reserved Note 1 Synchronized with the system clock 14 3 2 Interrupt Sources The PCAO module shares one interrupt vector among all of its modules There are are several event flags that can be used to generate a PCAO interrupt They are as follows the main PCA counter overflow flag CF which is set upon 16 bit overflow of the PCAO coun ter an intermediate overflow flag COVF which can be set on an overflow from the 8th 11th bit of the PCAO counter and the individu al flags for each PCA channel CCFn which are set according to the operation mode of that module These event flags are always set when the trigger condition occurs Each of these flags can be individually selected to generate a PCAO interrupt using the correspond
43. Supply Program Memory Crossbar Monitor PCAI WDT Decoder vr 256 Byte RAM SMBus 0 I Port 2 52 po SMBus 1 Drivers XS m Voltage SPI VREGIN 412 Crossbar Control Port 3 GND Xt f Drivers 4 P3 n System Clock Setup External Memory Interface 7 XTAL1 Port External Oscillator Drivers P4 n XTAL2 Control Internal Oscillator Address Clock Low Freq Recovery Oscillator USB Peripheral NZ EE controller D X Full Low Speed Transceiver VBUS x 1 KB RAM Figure 1 1 Detailed EFM8UB2 Block Diagram Analog Peripherals VDD VREF Comparators VDD 10 bit 500ksps ADC Temp Sensor silabs com Smart Connected Energy friendly Rev 0 2 1 EFM8UB2 Reference Manual System Overview 1 2 Power All internal circuitry draws power from the VDD supply pin External I O pins are powered from the VIO supply voltage or VDD on devi ces without a separate VIO connection while most of the internal circuitry is supplied by an on chip LDO regulator Control over the device power can be achieved by enabling disabling individual peripherals as needed Each analog peripheral can be disabled when not in use and placed in low power mode Digital peripherals such as timers and serial buses have their clocks gated off and draw little power when they are not in use Table 1 1 Power Modes Power Mode Details Mode Entry Wake Up Sources No
44. Timer4 and Timer5 19 1 Introduction Six counter timers ar included in the device two are 16 bit counter timers compatible with those found in the standard 8051 and four are 16 bit auto reload timers for timing peripherals or for general purpose use These timers can be used to measure time intervals count external events and generate periodic interrupt requests Timer 0 and Timer 1 are nearly identical and have four primary modes of operation Timer 2 Timer 3 Timer 4 and Timer 5 are also identical and offer both 16 bit and split 8 bit timer functionality with auto reload capabilities Timer 2 and Timer 3 are capable of performing a capture function on the low frequency oscillator output Timer 4 and Timer 5 do not support a capture function Timers 0 and 1 may be clocked by one of five sources determined by the Timer Mode Select bits 1 and the Clock Scale bits SCA1 SCA0 The Clock Scale bits define a pre scaled clock from which Timer 0 and or Timer 1 may be clocked Timer 0 1 may then be configured to use this pre scaled clock signal or the system clock Timer 2 5 may be clocked by the system clock system clock divided by 12 or external oscillator divided by 8 Timer 0 and Timer 1 may also be operated as counters When functioning as a counter a counter timer register is incremented on each high to low transition at the selected input pin TO or T1 Events with a frequency of up to one fourth the system clock frequency can
45. Value Name Description 0 0 DISABLED Positive Hysteresis disabled Ox1 ENABLED MODE1 Positive Hysteresis Hysteresis 1 0 2 ENABLED_MODE2 Positive Hysteresis Hysteresis 2 0x3 ENABLED_MODE3 Positive Hysteresis Hysteresis 3 Maximum 1 0 CPHYN 0x0 RW Comparator Negative Hysteresis Control silabs com Smart Connected Energy friendly Rev 0 2 131 EFM8UB2 Reference Manual Comparators CMPO and 1 Bit Name Reset Access Description Value Name Description 0x0 DISABLED Negative Hysteresis disabled 0x1 ENABLED_MODE1 Negative Hysteresis Hysteresis 1 0x2 ENABLED_MODE2 Negative Hysteresis Hysteresis 2 0x3 ENABLED_MODE3 Negative Hysteresis Hysteresis 3 Maximum 13 4 2 CMPOMD Comparator 0 Mode Bit 7 6 5 4 3 2 1 0 Reserved CPRIE CPFIE Reserved CPMD Access R RW RW R RW Reset 0x0 0 0 0x0 0x2 SFR Page ALL SFR Address 0x9D Bit Name Reset Access Description 7 6 Reserved Must write reset value 5 CPRIE 0 RW Comparator Rising Edge Interrupt Enable Value Name Description 0 RISE INT DISABLED Comparator rising edge interrupt disabled 1 RISE INT ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL INT DISABLED Comparator falling edge interrupt disabled 1 FALL INT ENABLED Comparator falling edge interrupt enabled 3 2 Reserved Must
46. an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 4 RXOVRN 0 RW Receive Overrun Flag This bit is valid for slave mode only and is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPIO shift register If SPI interrupts are enabled an interrupt will be generated This bit is not automatically cleared by hardware and must be cleared by firmware 3 2 NSSMD Ox1 RW Slave Select Mode Selects between the following NSS operation modes Value Name Description 0 0 3_WIRE 3 Wire Slave or 3 Wire Master Mode NSS signal is not routed to a port pin Ox1 4 WIRE SLAVE 4 Wire Slave or Multi Master Mode NSS is an input to the device 0 2 4 WIRE MAS 4 Wire Single Master Mode NSS is an output and logic low TER NSS LOW 0x3 4 WIRE MAS 4 Wire Single Master Mode NSS is an output and logic high TER NSS HIGH 1 TXBMT 1 R Transmit Buffer Empty This bit will be set to logic O when new data has been written to the transmit buffer When data in the transmit buffer is transferred to the SPI shift register this bit will be set to logic 1 indicating that it is safe to write a new byte to the transmit buffer 0 SPIEN 0 RW SPIO Enable Value Name Description 0 DISABLED Disable the SPI module 1 ENABLED Enable the SPI module silabs com Smart Connected Energy friendly
47. be counted The input signal need not be periodic but it must be held at a given level for at least two full system clock cycles to ensure the level is properly sampled Table 19 1 Timer Modes Timer 0 and Timer 1 Modes Timer 2 and Timer 3 Modes Timer 4 and Timer 5 Modes 13 bit counter timer 16 bit timer with auto reload 16 bit timer with auto reload 16 bit counter timer Two 8 bit timers with auto reload Two 8 bit timers with auto reload 8 bit counter timer with auto reload LFOSCO edge or USB SOF capture Two 8 bit counter timers Timer 0 only 19 2 Features Timer 0 and Timer 1 include the following features Standard 8051 timers supporting backwards compatibility with firmware and hardware Clock sources include SYSCLK SYSCLK divided by 12 4 or 48 the External Clock divided by 8 or an external pin 8 bit auto reload counter timer mode 13 bit counter timer mode 16 bit counter timer mode Dual 8 bit counter timer mode Timer 0 Timer 2 Timer 3 Timer 4 and Timer 5 are 16 bit timers including the following features Clock sources include SYSCLK SYSCLK divided by 12 or the External Clock divided by 8 16 bit auto reload timer mode Dual 8 bit auto reload timer mode USB start of frame or falling edge of LFOSCO capture Timer 2 and Timer 3 silabs com Smart Connected Energy friendly Rev 0 2 248 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and T
48. but the hardware will react differently Master Transfers As SPI master all transfers are initiated with a write to SPINDAT and the SPIF flag will be set by hardware to indicate the end of each transfer The general method for a single byte master transfer follows 1 Write the data to be sent to SPInDAT The transfer will begin on the bus at this time 2 Wait for the SPIF flag to generate an interrupt or poll SPIF until it is set to 1 3 Read the received data from SPInDAT 4 Clear the SPIF flag to O 5 Repeat the sequence for any additional transfers Slave Transfers As a SPI slave the transfers are initiated by an external master device driving the bus Slave firmware may anticipate any output data needs by pre loading the SPInDAT register before the master begins the transfer 1 Write any data to be sent to SPInDAT The transfer will not begin until the external master device initiates it 2 Wait for the SPIF flag to generate an interrupt or poll SPIF until it is set to 1 3 Read the received data from SPInDAT 4 Clear the SPIF flag to 0 5 Repeat the sequence for any additional transfers silabs com Smart Connected Energy friendly Rev 0 2 216 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO 17 3 6 SPI Timing Diagrams SCK MCKH MCKL MIS MIH wo MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 8 SPI Master Timing
49. 0 SFR Page OxF SFR Address OxC1 Bit Name Reset Access Description 7 ENSMB 0 RW SMBus Enable This bit enables the SMBus interface when set to 1 When enabled the interface constantly monitors the SDA and SCL pins 6 INH 0 RW SMBus Slave Inhibit When this bit is set to logic 1 the SMBus does not generate an interrupt when slave events occur This effectively removes the SMBus slave from the bus Master Mode interrupts are not affected 5 BUSY 0 R SMBus Busy Indicator This bit is set to logic 1 by hardware when a transfer is in progress It is cleared to logic 0 when a STOP or free timeout is sensed 4 EXTHOLD 0 RW SMBus Setup and Hold Time Extension Enable This bit controls the SDA setup and hold times Value Name Description 0 DISABLED Disable SDA extended setup and hold times 1 ENABLED Enable SDA extended setup and hold times 3 SMBTOE 0 RW SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is configured to Split Mode only the High Byte of the timer is held in reload while SCL is high Timer 3 should be programmed to generate interrupts at 25 ms and the Timer 3 interrupt service routine should reset SMBus communication 2 SMBFTE 0 RW SMBus Free Timeout Detection Enable When this bit is set to logic 1 the bus will be co
50. 0 0 0 0 0 SFR Page ALL SFR Address 0xDC Bit Name Reset Access Description 7 16 0 RW Channel 2 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled Value Name Description 0 8 BIT 8 bit PWM selected 1 16_BIT 16 bit PWM selected 6 ECOM 0 RW Channel 2 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel 2 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 2 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 2 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCF2 bit in the PCAOMD register to be set to logic 1 2 TOG 0 RW Channel 2 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX2 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 2 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is output on the CEX2 pin 8 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel
51. 0 2 81 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 3 3 Priority Crossbar Decoder The priority crossbar decoder assigns a priority to each I O function starting at the top with UARTO The XBRn registers are used to control which crossbar resources are assigned to physical I O port pins When a digital resource is selected the least significant unassigned port pin is assigned to that resource excluding UARTO which is always assigned to dedicated pins If a port pin is assigned the crossbar skips that pin when assigning the next selected resource Additionally the the PnSKIP registers allow software to skip port pins that are to be used for analog functions dedicated digital func tions or GPIO If a port pin is to be used by a function which is not assigned through the crossbar its corresponding PnSKIP bit should be set to 1 in most cases The crossbar skips these pins as if they were already assigned and moves to the next unassigned pin It is possible for crossbar assigned peripherals and dedicated functions to coexist on the same pin For example the port match func tion could be configured to watch for a falling edge on a UART RX line and generate an interrupt or wake up the device from a low power state However if two functions share the same pin the crossbar will have control over the output characteristics of that pin and the dedicated function will only have input access Likewise it is possib
52. 0 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 0 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 0 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCFO bit in the PCAOMD register to be set to logic 1 2 TOG 0 RW Channel 0 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEXO pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 0 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is output on the pin 8 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel 0 Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCFO interrupt Value Name Description 0 DISABLED Disable CCFO interrupts 1 ENABLED Enable a Capture Compare Flag interrupt request when CCFO is set silabs com Smart Connected Energy friendly Rev 0 2 151 EFM8UB2 Reference Manual Programmable Counter Array PCAO
53. 0x00 Indirect Address 0x20 Bit Name Reset Access 7 0 FIFODATA 0x00 RW the Endpoint 0 OUT FIFO Description Endpoint 0 FIFO Access Writing to this FIFO address loads data into the IN FIFO for Endpoint 0 Reading from the FIFO address reads data from This register is accessed indirectly using the USBOADR and USBODAT registers 16 4 7 FIFO1 USBO Endpoint 1 FIFO Access Bit 7 6 4 1 0 FIFODATA Access RW Reset 0x00 Indirect Address 0x21 Bit Name Reset Access 7 0 FIFODATA 0x00 RW the Endpoint 1 OUT FIFO Description Endpoint 1 FIFO Access Writing to this FIFO address loads data into the IN FIFO for Endpoint 1 Reading from the FIFO address reads data from This register is accessed indirectly using the USBOADR and USBODAT registers 16 4 8 FIFO2 USBO Endpoint 2 FIFO Access Bit 7 6 5 4 1 0 FIFODATA Access RW Reset 0x00 Indirect Address 0x22 Bit Name Reset Access Description 7 0 FIFODATA 0x00 RW Endpoint 2 FIFO Access the Endpoint 2 OUT FIFO Writing to this FIFO address loads data into the IN FIFO for Endpoint 2 Reading from the FIFO address reads data from This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 194 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 9 FIFO3 USBO Endpoint 3
54. 11 Non Multiplexed 8 bit MOVX with Bank Select Timing on page 174 show the timing diagrams for the different External Memory Interface non multiplexed modes and MOVX opera tions Nonmuxed 16 bit WRITE A 15 8 ADDRESS 8 MSBs from DPH A 15 8 EMIF ADDRESS 8 LSBs from DPL EMIF WRITE DATA Nonmuxed 16 bit READ A 15 8 EMIF ADDRESS 8 MSBs from 15 8 EMIF ADDRESS 8 LSBs from DPL EMIF READ DATA Figure 15 9 Non Multiplexed 16 bit MOVX Timing Rev 0 2 172 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual External Memory Interface EMIFO Nonmuxed 8 bit WRITE without Bank Select A 15 8 A 15 8 EMIF ADDRESS 8 LSBs from RO or R1 EMIF WRITE DATA Nonmuxed 8 bit READ without Bank Select A 15 8 A 15 8 ADDRESS 8 LSBs from RO R1 EMIF READ DATA Figure 15 10 Non Multiplexed 8 bit MOVX without Bank Select Timing silabs com Smart Connected Energy friendly Rev 0 2 173 EFM8UB2 Reference Manual External Memory Interface EMIFO Nonmuxed 8 bit WRITE with Bank Select A 15 8 EMIF ADDRESS 8 MSBs from EMIOCN 15 8 ADDRESS 8 LSBs from RO or 1 EMIF WRITE DATA Nonmuxed 8 bit READ with Bank Select A 15 8 ADDRESS 8 MSBs from EMIOCN A 15 8 EMIF ADDRESS 8 LSBs from RO or R1 EMIF READ DATA Figure 15 11 Non Multiplexed 8 bit MOVX with Bank Select Timing silabs com
55. 2 Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCF2 interrupt Value Name Description 0 DISABLED Disable CCF2 interrupts 1 ENABLED Enable a Capture Compare Flag interrupt request when CCF2 is set silabs com Smart Connected Energy friendly Rev 0 2 155 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 4 12 PCAOCPL2 PCA Channel 2 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 PCAOCPL2 Access RW Reset 0x00 SFR Page ALL SFR Address 0 Bit Name Reset Access Description 7 0 PCAOCPL2 0x00 RW PCA Channel 2 Capture Module Low Byte The PCAOCPL2 register holds the low byte LSB of the 16 bit capture module write to this register will clear the module s ECOM bit to a 0 14 4 13 2 PCA Channel 2 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name 2 Access RW Reset 0x00 SFR Page ALL SFR Address 0xEC Bit Name Reset Access Description 7 0 PCAOCPH 0x00 RW PCA Channel 2 Capture Module High Byte 2 The PCAOCPH2 register holds the high byte MSB of the 16 bit capture module A write to this register will set the module s ECOM bit to a 1 Rev 0 2 156 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Programmable Counter Array 14 4 14 PCAOCPM3 PCA Channel 3 Capture Compare
56. 3 Functional Description 15 3 1 Overview 15 3 2 Port I O Configuration 4 15 3 2 1 EMIF Pin Mapping 15 3 3 Multiplexed External Memory Interface 15 3 4 Non Multiplexed External Memory Interface 15 3 5 Operating Modes 15 3 6 Timing 15 3 6 1 Multiplexed Mode e 15 3 6 2 Non Multiplexed Mode 15 4 EMIFO Control Registers 15 4 1 EMIOCN External Memory Control 15 4 2 EMIOCF External Memory Configuration 15 4 3 EMIOTC External Memory Timing Control Universal Serial Bus USBO 16 1 Introduction 16 2 Features 16 3 Functional Description 16 3 1 Endpoint Addressing 16 3 2 Transceiver Control 16 3 3 Clock Configuration 16 3 4 VBUS Control 16 3 5 Register Access 16 3 6 FIFO Management 16 3 7 Function Addressing 16 3 8 Function Configuration and Control 16 3 9 Interrupts 16 3 10 Serial Interface Engine 16 3 11 Endpoint 0 16 3 12 Endpoints 1 2 and 3 16 4 USBO Control Registers 16 4 1 USBOXCN USBO Transceiver Control 16 4 2 USBOADR USBO Indirect Address Table of Contents 154 155 156 156 157 158 158 159 160 160 161 161 161 162 162 162 162 165 166 167 168 169 172 175 175 176 178 180 180 180 181 181 181 181 181 182 184 185 186 186 186 187 188 190 190 191 301 17 18 16 4 3 USBODAT USBO Data 16 4 4 INDEX USBO Endpoint Index 16 4 5 CLKREC USBO Clock Recovery Control 16 4 6 0 USBO Endpoint 0 F
57. ADCOL OxFD PCAOCPLA OxBE ADCOH OxFE PCAOCPHA OxBF SFRPAGE OxFF VDMOCN Table 3 2 Special Function Registers by Name Register Address SFR Pages Description ACC OxEO ALL Accumulator ADCOCF OxBC ALL ADCO Configuration silabs com Smart Connected Energy friendly Rev 0 2 14 EFM8UB2 Reference Manual Special Function Registers Register Address SFR Pages Description ADCOCNO OxE8 ALL ADCO Control ADCOGTH OxC4 ALL ADCO Greater Than High Byte ADCOGTL OxC3 ALL ADCO Greater Than Low Byte ADCOH OxBE ALL ADCO Data Word High Byte ADCOL OxBD ALL ADCO Data Word Low Byte ADCOLTH 0xC6 ALL ADCO Less Than High Byte ADCOLTL OxC5 ALL ADCO Less Than Low Byte AMXON OxBA ALL AMUXO Negative Multiplexer Selection AMXOP OxBB ALL AMUXO Positive Multiplexer Selection B OxFO ALL B Register CKCONO Ox8E ALL Clock Control 0 1 OxE4 OxOF Clock Control 1 CLKSEL 0 9 ALL Clock Select CMPOCNO Ox9B ALL Comparator 0 Control 0 CMPOMD Ox9D ALL Comparator 0 Mode CMPOMX Ox9F ALL Comparator 0 Multiplexer Selection 1 Ox9A ALL Comparator 1 Control 0 CMP1MD Ox9C ALL Comparator 1 Mode CMP1MX Ox9E ALL Comparator 1 Multiplexer Selection DPH 0x83 ALL Data Pointer High DPL 0x82 ALL Data Pointer Low EIE1 OxE6 ALL Extended Interrupt Enable 1 EIE OxE7 ALL Extended Interrupt Enable 2 EIP1 OxF6 ALL Extended Interrupt
58. ALL SFR Address 4 Bit Name Reset Access Description 7 B7 0 RW Port 0 Bit 7 Output Mode Value Name Description 0 OPEN_DRAIN PO 7 output is open drain 1 PUSH_PULL 7 output is push pull 6 B6 0 RW Port 0 Bit 6 Output Mode See bit 7 description 5 5 0 RW Port 0 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 0 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 0 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 0 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 0 Bit 1 Output Mode See bit 7 description 0 BO 0 RW Port 0 Bit 0 Output Mode See bit 7 description silabs com Smart Connected Energy friendly Rev 0 2 91 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 7 POSKIP Port 0 Skip Bit 7 6 5 4 3 2 1 0 Name B7 B6 BS B4 B3 B2 1 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xD4 Bit Name Reset Access Description 7 B7 0 RW Port 0 Bit 7 Skip Value Name Description 0 NOT_SKIPPED 0 7 pin is not skipped by the crossbar 1 SKIPPED PO0 7 is skipped by the crossbar 6 B6 0 RW Port 0 Bit 6 Skip See bit 7 description 5 BS 0 RW Port 0 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 0 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 0 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 0 Bit 2 Skip See bit 7 descripti
59. AUSB Reset interrupt is generated if enabled 2 RESUME 0 RW Force Resume Writing a 1 to this bit while in suspend mode SUSMD 1 forces USBO to generate resume signaling on the bus a remote wakeup event Firmware should clear RESUME to 0 after 10 to 15 ms to end the resume signaling An interrupt is gener ated and hardware clears SUSMD when firmware writes RESUME to 0 silabs com Smart Connected Energy friendly SUSMD 0 R Suspend Mode This bit is set to 1 by hardware when USBO enters suspend mode This bit is cleared by hardware when firmware writes RESUME 0 following a remote wakeup or reads the CMINT register after detection of resume signaling on the bus Value Name Description 0 NOT SUSPENDED USBO not in suspend mode Rev 0 2 196 EFM8UB2 Reference Manual Universal Serial Bus USBO Bit Name Reset Access Description 1 SUSPENDED USBO in suspend mode 0 SUSEN 0 RW Suspend Detection Enable Value Name Description 0 DISABLED Disable suspend detection USBO will ignore suspend signaling on the bus 1 ENABLED Enable suspend detection USBO will enter suspend mode if it detects suspend signaling on the bus This register is accessed indirectly using the USBOADR and USBODAT registers 16 4 12 FRAMEL USBO Frame Number Low Bit 7 6 5 4 3 2 1 0 FRMEL Access R Reset 0x00 Indirect Address 0 0 Bit Name Reset Access Description 7
60. Bit Pulse Width Modulator 0 B 0 0 C 0 1 A 16 Bit Pulse Width Modulator 1 B 0 0 C 0 1 A Notes 1 X Don t Care no functional difference for individual module if 1 or 0 2 Enable interrupts for this module PCA interrupt triggered CCFn set to 1 When set to 0 the digital comparator is off For high speed and frequency output modes the associated pin will not toggle In any of the PWM modes this generates a 0 duty cycle output 0 4 C When set a match event will cause the CCFn flag for the associated channel to be set silabs com Smart Connected Energy friendly Rev 0 2 139 EFM8UB2 Reference Manual Programmable Counter Array 14 3 4 Edge Triggered Capture Mode In this mode valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter timer and load it into the corresponding module s 16 bit capture compare register PCAOCPLn and PCAOCPHn The CAPPn and bits in the PCAOCPMn register are used to select the type of transition that triggers the capture low to high transition positive edge high to low transition negative edge or either transition positive or negative edge When a capture occurs the Capture Compare Flag CCFn in PCAOCNO is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardware when the CPU vectors to the interrupt service rou
61. Byte Q lt Interrupts with Hardware ACK Disabled EHACK 0 Received by SMBus S START Interface P STOP Transmitted by W WRITE SMBus Interface SLA Slave Address Figure 18 5 Typical Master Write Sequence silabs com Smart Connected Energy friendly Rev 0 2 232 EFM8UB2 Reference Manual System Management Bus 2 SMBO 5 1 Interrupt STA sent 1 Clear the STA and STO flags 2 Write SMBODAT with the slave address and R W bit set to 1 3 Clear the interrupt flag 51 Interrupt Send Repeated Start More Data to Send 1 Set the STO 1 Set the STA flag flag 2 Clear the 2 Clear the interrupt flag SI interrupt flag SI ACK received 1 Write next data to SMBODAT 2 Clear the interrupt flag SI Interrupt Figure 18 6 Master Write Sequence State Diagram EHACK 1 Rev 0 2 233 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 Master Read Sequence During a read sequence an SMBus master reads data from a slave device The master in this transfer will be a transmitter during the address byte and a receiver during all data bytes The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit
62. Enable a Capture Compare Flag interrupt request when CCF1 is set silabs com Smart Connected Energy friendly Rev 0 2 153 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 4 9 PCAOCPL1 PCA Channel 1 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 PCAOCPL1 Access RW Reset 0x00 SFR Page ALL SFR Address OxE9 Bit Name Reset Access Description 7 0 PCAOCPL1 0x00 RW PCA Channel 1 Capture Module Low Byte PCAOCPL1 register holds the low byte LSB of the 16 bit capture module write to this register will clear the module s ECOM bit to a 0 14 4 10 1 PCA Channel 1 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Name PCAOCPH1 Access RW Reset 0x00 SFR Page ALL SFR Address OxEA Bit Name Reset Access Description 7 0 PCAOCPH 0x00 RW PCA Channel 1 Capture Module High Byte 1 The PCAOCPH1 register holds the high byte MSB of the 16 bit capture module A write to this register will set the module s ECOM bit to a 1 Rev 0 2 154 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Programmable Counter Array 14 4 11 PCAOCPM2 PCA Channel 2 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0
63. FIFO Access Bit 7 6 5 4 3 2 1 0 Name FIFODATA Access RW Reset 0x00 Indirect Address 0x23 Bit Name Reset Access Description 7 0 FIFODATA 0x00 RW Endpoint 3 FIFO Access Writing to this FIFO address loads data into the IN FIFO for Endpoint 3 Reading from the FIFO address reads data from the Endpoint 3 OUT FIFO This register is accessed indirectly using the USBOADR and USBODAT registers 16 4 10 FADDR USBO Function Address Bit 7 6 5 4 3 2 1 0 UPDATE FADDR Access R RW Reset 0 0x00 Indirect Address 0x00 Bit Name Reset Access Description 7 UPDATE 0 R Function Address Update Set to 1 when firmware writes the FADDR register USBO clears this bit to 0 when the new address takes effect Value Name Description 0 NOT_SET The last address written to FADDR is in effect 1 SET The last address written to FADDR is not yet in effect 6 0 FADDR 0x00 RW Function Address This field is the 7 bit function address for USBO This address should be written by firmware when the SET ADDRESS standard device request is received on Endpoint 0 The new address takes effect when the device request completes This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 195 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 11 POWER USBO Power
64. IDE s debugger and programmer interface to the CIP 51 via the C2 interface to provide fast and efficient in system device programming and debugging Third party macro assemblers and C com pilers are also available 10 3 2 Prefetch Engine The CIP 51 core incorporates a 2 byte prefetch engine to enable faster core clock speeds Because the access time of the flash memo ry is 40 ns and the minimum instruction time is 20 ns the prefetch engine is necessary for full speed code execution Instructions are read from flash memory two bytes at a time by the prefetch engine and given to the CIP 51 processor core to execute When running linear code code without any jumps or branches the prefetch engine allows instructions to be executed at full speed When a code branch occurs the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from flash memory The PFEOCN register controls the behavior of the prefetch engine When operating at speeds greater than 25 MHz the prefetch engine must be enabled To enable the prefetch engine both the FLRT and PFEN bit should be set to 1 silabs com Smart Connected Energy friendly Rev 0 2 69 EFM8UB2 Reference Manual CIP 51 Microcontroller Core 10 3 3 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the standard MCS 51 instruction set Standard 8051 de velopment tools can be used to develop software for the
65. INT1 PO Control 1 Timer 1 Timer 2 UART 1 SMBus1 Figure 11 1 Port I O Block Diagram 11 2 Features The port control block offers the following features Up to 40 multi functions pins supporting digital and analog functions Flexible priority crossbar decoder for digital peripheral assignment Two drive strength settings for each port Two direct pin interrupt sources with dedicated interrupt vectors INTO and INT1 Up to 0 direct pin interrupt sources with shared interrupt vector Port Match silabs com Smart Connected Energy friendly Rev 0 2 78 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 3 Functional Description 11 3 1 Port I O Modes of Operation Port pins are configured by firmware as digital or analog I O using the special function registers Port I O initialization consists of the following general steps 1 Select the input mode analog or digital for all port pins using the Port Input Mode register PnMDIN 2 Select the output mode open drain or push pull for all port pins using the Port Output Mode register PNMDOUT 3 Select any pins to be skipped by the I O crossbar using the Port Skip registers PnSKIP 4 Assign port pins to desired peripherals 5 Enable the crossbar XBARE 1 A diagram of the port I O cell is shown in the following figure WEAKPUD Weak Pull Up Disable PxMDOUT x gt 1 for push pull VDD VDD 0 for
66. Input Mode Value Name Description 0 ANALOG P3 7 pin is configured for analog mode 1 DIGITAL P3 7 pin is configured for digital mode 6 B6 1 RW Port 3 Bit 6 Input Mode See bit 7 description 5 B5 1 RW Port 3 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 3 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 3 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 3 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 3 Bit 1 Input Mode See bit 7 description 0 0 1 RW Port 3 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled Port 3 consists of 8 bits P3 0 P3 7 TQFP48 packages and 1 bit P3 0 on LOFP32 and QFN32 packages silabs com Smart Connected Energy friendly Rev 0 2 102 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 18 P3MDOUT Port 3 Output Mode Bit 7 6 5 4 3 2 1 0 Name B7 B6 BS B4 B3 B2 1 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address OxA7 Bit Name Reset Access Description 7 B7 0 RW Port 3 Bit 7 Output Mode Value Name Description 0 OPEN_DRAIN P3 7 output is open drain 1 PUSH PULL P3 7 output is push pull 6 B6 0 RW Port 3 Bit 6 Output Mode See bit 7 description 5 B5 0 RW Port 3 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 3
67. Interrupts Output Shift Register Control Configuration SBUF 8 LSBs Baud Rate Generator Timer 1 Input Shift Register RB8 9 bit START Detection Figure 20 1 UARTO Block Diagram 20 2 Features The UART uses two signals TX and RX and a predetermined fixed baud rate to provide asynchronous communications with other devices The UART module provides the following features Asynchronous transmissions and receptions Baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 8 or 9 bit data Automatic start and stop generation silabs com Smart Connected Energy friendly Rev 0 2 278 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 3 Functional Description 20 3 1 Baud Rate Generation The UARTO baud rate is generated by Timer 1 in 8 bit auto reload mode The TX clock is generated by TL1 the RX clock is generated by copy of TL1 which is not user accessible Both TX and RX timer overflows are divided by two to generate the TX and RX rates The RX timer runs when Timer 1 is enabled and uses the same reload value TH1 However an RX timer reload is forced when START condition is detected on the RX pin This allows receive to begin any time START is detected independent of the TX timer state Baud Rate Generator In Timer 1 TX Clock START y Detection va RX Timer RX Clock Figure 20 2 UARTO Baud Rate Logic Block Diagr
68. O and internal timer sources Output data window comparator allows automatic range checking Two tracking mode options with programmable tracking time Conversion complete and window compare interrupts supported Flexible output data formatting Voltage reference selectable from external reference pin on chip precision reference driven externally on reference pin or VDD supply Integrated temperature sensor 12 3 Functional Description 12 3 1 Clocking The ADC is clocked by an adjustable conversion clock SARCLK which is a divided version of the selected system clock The clock divide value is determined by the ADSC field In most applications SARCLK should be adjusted to operate as fast as possible without exceeding the maximum electrical specifications The SARCLK does not directly determine sampling times or sampling rates 12 3 2 Voltage Reference Options The voltage reference multiplexer for the ADC is configurable to use an externally connected voltage reference the on chip reference voltage generator routed to the VREF pin the unregulated power supply voltage VDD or the regulated 1 8 V internal supply The REFSL bit in the REFOCN register selects the reference source for the ADC For an external source or the on chip reference REFSL should be set to 0 to select the VREF To use VDD as the reference source REFSL should be set to 1 To override this selection and use the internal regulator as the referen
69. PC is reset the watchdog timer is enabled and the system clock defaults to an internal oscillator Program execution begins at location 0 0000 silabs com Smart Connected Energy friendly Rev 0 2 62 EFM8UB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 2 Power On Reset During power up the POR circuit fires When POR fires the device is held in a reset state and the RSTb pin is driven low until the supply voltage settles above Vgsr Two delays are present during the supply ramp time First a delay occurs before the POR circuitry fires and pulls the RSTb pin low A second delay occurs before the device is released from reset the delay decreases as the supply ramp time increases supply ramp time is defined as how fast the supply pin ramps from 0 V to For ramp times less than 1 ms the power on reset time Tpog is typically less than 0 3 ms Additionally the power supply must reach before the POR circuit releases the device from reset On exit from a power on reset the PORSF flag is set by hardware to logic 1 When PORSF is set all of the other reset flags in the RSTSRC register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The content of internal data memory should be assumed to be undefined after a power on reset The su
70. Port 4 Bit 7 Output Mode Value Name Description 0 OPEN_DRAIN P4 7 output is open drain 1 PUSH_PULL P4 7 output is push pull 6 B6 0 RW Port 4 Bit 6 Output Mode See bit 7 description 5 5 0 RW Port 4 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 4 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 4 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 4 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 4 Bit 1 Output Mode See bit 7 description 0 BO 0 RW Port 4 Bit 0 Output Mode See bit 7 description Port 4 consists of 8 bits P4 0 P4 7 on TQFP48 packages and is unavailable on LQFP32 and QFN32 packages silabs com Smart Connected Energy friendly Rev 0 2 107 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 5 INTO and INT1 Control Registers 11 5 1 ITO1CF INTO INT1 Configuration Bit 7 6 5 4 3 2 1 0 IN1PL IN1SL INOPL INOSL Access RW RW RW RW Reset 0 0x0 0 Ox1 SFR Page 0x0 SFR Address 0 4 Bit Name Reset Access Description 7 IN1PL 0 RW INT1 Polarity Value Name Description 0 ACTIVE LOW INT1 input is active low 1 ACTIVE HIGH INT1 input is active high 6 4 IN1SL 0x0 RW INT1 Port Pin Selection These bits select which port pin is assigned to INT1 This pin assignment is independent of the Crossbar INT1 will monitor the assigned port pin without disturbing the peripheral that has been assigne
71. Reserved Reserved Reserved 13 3 4 Output Routing The comparator s synchronous and asynchronous outputs can optionally be routed to port I O pins through the port I O crossbar The output of either comparator may be configured to generate a system interrupt on rising falling or both edges CMPO may also be used as a reset source or as a trigger to kill a PCA output channel The output state of the comparator can be obtained at any time by reading the CPOUT bit The comparator is enabled by setting the bit to logic 1 and is disabled by clearing this bit to logic 0 When disabled the comparator output if assigned to a port I O pin via the crossbar defaults to the logic low state and the power supply to the comparator is turned off Comparator interrupts can be generated on both rising edge and falling edge output transitions The CPFIF flag is set to logic 1 upon a comparator falling edge occurrence and the CPRIF flag is set to logic 1 upon the comparator rising edge occurrence Once set these bits remain set until cleared by software The comparator rising edge interrupt mask is enabled by setting CPRIE to a logic 1 The com parator falling edge interrupt mask is enabled by setting CPFIE to a logic 1 False rising edges and falling edges may be detected when the comparator is first powered on or if changes are made to the hysteresis or response time control bits Therefore it is recommended that the rising edge
72. SFR Address OxCB Bit Name Reset Access 7 0 TMR2RLH 0x00 RW When operating in one of the auto reload modes TMR2RLH holds the reload value for the high byte of Timer 2 TMR2H When operating in capture mode TMR2RLH is the captured value of TMR2H Description Timer 2 Reload High Byte 19 4 12 TMR2L Timer 2 Low Byte Bit 7 6 4 3 2 1 0 TMR2L Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xCC Bit Name Reset Access Description 7 0 TMR2L 0x00 RW Timer 2 Low Byte In 16 bit mode the TMR2L register contains the low byte of the 16 bit Timer 2 In 8 bit mode TMR2L contains the 8 bit low byte timer value silabs com Smart Connected Energy friendly Rev 0 2 267 EFM8UB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 13 TMR2H Timer 2 High Byte Bit 7 6 5 4 3 2 1 0 TMR2H Access RW Reset 0x00 SFR Page 0x0 SFR Address OxCD Bit Name Reset Access Description 7 0 TMR2H 0x00 RW Timer 2 High Byte In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the 8 bit high byte timer value silabs com Smart Connected Energy friendly Rev 0 2 268 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 14 TMR3CNO Timer 3 Control 0
73. SFR Page ALL SFR Address 0x9A Bit Name Reset Access Description 7 CPEN 0 RW Comparator Enable Value Name Description 0 DISABLED Comparator disabled 1 ENABLED Comparator enabled 6 CPOUT 0 R Comparator Output State Flag Value Name Description 0 POS LESS THAN NE Voltage on CP1P lt CP1N G 1 POS GREAT Voltage on CP1P CP1N ER THAN NEG 5 CPRIF 0 RW Comparator Rising Edge Flag Must be cleared by firmware Value Name Description 0 NOT SET No comparator rising edge has occurred since this flag was last cleared 1 RISING EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING EDGE Comparator falling edge has occurred 3 2 CPHYP 0 0 RW Comparator Positive Hysteresis Control Value Name Description 0 0 DISABLED Positive Hysteresis disabled Ox1 ENABLED MODE1 Positive Hysteresis Hysteresis 1 0 2 ENABLED_MODE2 Positive Hysteresis Hysteresis 2 0x3 ENABLED_MODE3 Positive Hysteresis Hysteresis 3 Maximum 1 0 CPHYN 0x0 RW Comparator Negative Hysteresis Control silabs com Smart Connected Energy friendly Rev 0 2 134 EFM8UB2 Reference Manual Comparators CMPO and 1 Bit Name Reset Access Description Value Name Description 0x0 DISABLED Negative Hysteresis disabled 0x1 ENABLED_MODE1 Negative Hysteresis Hysteresis 1 0
74. SFR Page ALL SFR Address OxF3 Bit Name Reset Access Description 7 B7 1 RW Port 2 Bit 7 Input Mode Value Name Description 0 ANALOG P2 7 pin is configured for analog mode 1 DIGITAL P2 7 pin is configured for digital mode 6 B6 1 RW Port 2 Bit 6 Input Mode See bit 7 description 5 B5 1 RW Port 2 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 2 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 2 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 2 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 2 Bit 1 Input Mode See bit 7 description 0 BO 1 RW Port 2 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled silabs com Smart Connected Energy friendly Rev 0 2 98 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 14 P2MDOUT Port 2 Output Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xA6 Bit Name Reset Access Description 7 B7 0 RW Port 2 Bit 7 Output Mode Value Name Description 0 OPEN_DRAIN P2 7 output is open drain 1 PUSH_PULL P2 7 output is push pull 6 B6 0 RW Port 2 Bit 6 Output Mode See bit 7 description 5 5 0 RW Port 2 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 2 Bit 4 Output Mode See
75. Smart Connected Energy friendly Rev 0 2 9 EFM8UB2 Reference Manual Memory Organization OxFFFF Reserved Ox7FFF Lock Byte Ox7FFE Security Page 512 Bytes 0x7E00 32 KB Flash 64 x 512 Byte pages 0x0000 Figure 2 2 Flash Memory Map 32 KB Devices On Chip RAM Accessed with MOV Instructions as Indicated OxFF Upper 128 Bytes Special Function RAM Registers Indirect Access Direct Access 0x80 Ox7F Lower 128 Bytes RAM Direct or Indirect Access 0x30 Ox2F 0x20 Ox1F 0x00 General Purpose Register Banks Figure 2 3 Direct Indirect RAM Memory silabs com Smart Connected Energy friendly Rev 0 2 10 EFM8UB2 Reference Manual Memory Organization On Chip XRAM Accessed with MOVX Instructions OxFFFF Shadow XRAM Duplicates 0x0000 0x0FFF On 4096 B boundaries 0x1000 OxOFFF OxO7FF USB FIFO XRAM 4096 Bytes Wer iis USBCLK Domain 0x0400 0x0000 Figure 2 4 XRAM Memory silabs com Smart Connected Energy friendly Rev 0 2 11 EFM8UB2 Reference Manual Special Function Registers 3 Special Function Registers 3 1 Special Function Register Access The direct access data memory locations from 0x80 to OxFF constitute the special function registers SFRs The SFRs provide control and data exchange with the CIP 51 s resources and peripherals The CIP 51 duplicates the SFRs found in a typical 8051 implementa tion a
76. This field selects the SMBus clock source which is used to generate the SMBus bit rate See the SMBus clock timing sec tion for additional details Value Name Description 0x0 TIMERO Timer 0 Overflow Ox1 TIMER1 Timer 1 Overflow 0 2 TIMER2 HIGH Timer 2 High Byte Overflow 0x3 TIMER2_LOW Timer 2 Low Byte Overflow silabs com Smart Connected Energy friendly Rev 0 2 240 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 18 5 2 SMBOCNO SMBus 0 Control Bit 7 6 5 4 3 2 1 0 MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI Access R R RW RW R R RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 SFR Address OxCO bit addressable Bit Name Reset Access Description 7 MASTER 0 R SMBus Master Slave Indicator This read only bit indicates when the SMBus is operating as a master Value Name Description 0 SLAVE SMBus operating in slave mode 1 MASTER SMBus operating in master mode 6 TXMODE 0 R SMBus Transmit Mode Indicator This read only bit indicates when the SMBus is operating as a transmitter Value Name Description 0 RECEIVER SMBus in Receiver Mode 1 TRANSMITTER SMBus in Transmitter Mode 5 STA 0 RW SMBus Start Flag When reading STA a 1 indicates that a start or repeated start condition was detected on the bus Writing a 1 to the STA bit initiates a start or repeated start on the bus 4 ST
77. a number of available options for data formatting Data transfers begin with a start bit logic low followed by the data bits sent LSB first a parity or extra bit if selected and end with one or two stop bits logic high The data length is variable between 5 and 8 bits A parity bit can be appended to the data and automatically generated and detected by hardware for even odd mark or space parity The stop bit length is selectable between short 1 bit time and long 1 5 or 2 bit times and a multi processor communica tion mode is available for implementing networked UART buses All of the data formatting options can be configured using the SMOD register Note that the extra bit feature is not available when parity is enabled and the second stop bit is only an option for data lengths of 6 7 or 8 bits MARK START ar A gt SPACE BIT TIMES 4 N bits N 2 5 6 7 or8 Figure 21 3 UART1 Timing Without Parity or Extra Bit MARK START SPACE BIT TIMES PARITY N bits N 2 5 6 7 or8 Figure 21 4 UART1 Timing With Parity MARK START ar y SPACE BIT TIMES N bits N 5 6 7 or8 Figure 21 5 UART1 Timing With Extra Bit 21 3 3 Basic Data Transfer UART1 provides standard asynchronous full duplex communication All data sent or received goes through the SBUF1 re
78. a system reset must be issued to resume normal operation 22 4 5 C2FPDAT C2 Flash Programming Data Bit 7 6 5 4 3 2 1 0 C2FPDAT Access RW Reset 0x00 C2 Address OxAD Bit Name Reset Access Description 7 0 C2FPDAT 0x00 RW C2 Flash Programming Data Register This register is used to pass flash commands addresses and data during C2 flash accesses Valid commands are listed below 0x03 Device Erase 0x06 Flash Block Read 0x07 Flash Block Write 0x08 Flash Page Erase silabs com Smart Connected Energy friendly Rev 0 2 294 EFM8UB2 Reference Manual Revision History 23 Revision History 23 1 Revision 0 2 Updated 11 3 3 1 Crossbar Functional Map to properly print the full crossbar map 23 2 Revision 0 1 Initial release silabs com Smart Connected Energy friendly Rev 0 2 295 Table of Contents 1 System Overview 1 1 1 Introduction 1 1 2 2 1 3 IO 2 1 4 Clocking 22 1 5 Counters Timers PWM 1 6 Communications and Other Digital Peripherals 4 1 7 Analog 9 1 8 Reset Sources 6 1 9 Debugging 26 1 10 226 2 Memory Organization sd 2 1 Memory Organization 27 2 2 7 2 3 27 2 4 9 3 Special Function Registers 12 3 1 Special Function Register Access 12 3 2 Special Function Register Memory Map
79. and disabled by software using the VDMEN bit in the VDMOCN register and then firmware performs a software reset the supply monitor will remain disabled and de selected after the reset To protect the integrity of flash contents the supply monitor must be enabled and selected as a reset source if software contains rou tines that erase or write flash memory If the supply monitor is not enabled any erase or write performed on flash memory will be ignor ed Supply Voltage Reset Threshold RSTb Supply Monitor Reset Figure 9 3 Reset Sources 9 3 4 External Reset The external RSTb pin provides a means for external circuitry to force the device into a reset state Asserting an active low signal on the RSTb pin generates a reset an external pullup and or decoupling of the RSTb pin may be necessary to avoid erroneous noise induced resets The PINRSF flag is set on exit from an external reset 9 3 5 Missing Clock Detector Reset The Missing Clock Detector MCD is a one shot circuit that is triggered by the system clock If the system clock remains high or low for more than the MCD time window the one shot will time out and generate a reset After a MCD reset the MCDRSF flag will read 1 signifying the MCD as the reset source otherwise this bit reads 0 Writing a 1 to the MCDRSF bit enables the Missing Clock Detector writing 0 disables it The state of the RSTb is unaffected by this reset 9 3 6 Comparator
80. and the data output pin when configured as a slave It is used to serially transfer data from the slave to the master Data is transferred on the MISO pin most signifi cant bit first The MISO pin is placed in a high impedance state when the SPI module is disabled or when the SPI operates in 4 wire mode as a slave that is not selected When acting as a slave in 3 wire mode MISO is always driven from the internal shift register Serial Clock SCK The SCK signal is an output from the master device and an input to slave devices It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines The SPI module generates this signal when operating as a master and receives it as a slave The SCK signal is ignored by a SPI slave when the slave is not selected in 4 wire slave mode Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD bitfield There are three possible modes that can be selected with these bits NSSMD 1 0 00 3 Wire Master or 3 Wire Slave Mode The SPI operates 3 wire mode and NSS is disabled When operating as a slave device the SPI is always selected in 3 wire mode Since no select signal is present the SPI must be the only slave on the bus in 3 wire mode This is intended for point to point communication between a master and a single slave NSSMD 1 0 01 4 Wire Slave or Multi Master Mode The SPI operates in 4 wire mode and NSS is c
81. and which bits are ignored Any bit set to 1 in SLVM enables comparisons with the corresponding bit in SLV Bits set to 0 are ignored can be either 0 or 1 in the incoming address 0 0 RW Hardware Acknowledge Enable Enables hardware acknowledgement of slave address and received data bytes Value Name Description 0 ADR_ACK_MANUAL Firmware must manually acknowledge all incoming address and data bytes 1 ADR_ACK_AUTOMAT Automatic slave address recognition and hardware acknowledge is enabled IC 18 6 5 SMB1DAT SMBus 1 Data Bit 7 6 5 4 3 2 1 0 SMB1DAT Access RW Reset 0x00 SFR Page OxF SFR Address 0xC2 Bit 7 0 Name Reset Access Description SMB1DAT 0x00 RW SMBus 1 Data The SMB1DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface The CPU can safely read from or write to this register whenever the SI serial inter rupt flag is set to logic 1 The serial data in the register remains stable as long as the SI flag is set When the SI flag is not set the system may be in the process of shifting data in out and the CPU should not attempt to access this register silabs com Smart Connected Energy friendly Rev 0 2 247 EFM8UB2 Reference Manual Timers TimerO Timer1 2 Timer3 Timer4 and Timer5 19 Timers 0 Timer1 Timer2 Timer3
82. defined by the prescale field SCA 1 SYSCLK Counter Timer 0 uses the system clock 1 0 SCA 0 0 RW Timer 0 1 Prescale These bits control the Timer 0 1 Clock Prescaler Value Name Description 0x0 SYSCLK DIV 12 System clock divided by 12 Ox1 SYSCLK DIV 4 System clock divided by 4 0 2 SYSCLK_DIV_48 System clock divided by 48 0x3 EXTOSC_DIV_8 External oscillator divided by 8 synchronized with the system clock silabs com Smart Connected Energy friendly Rev 0 2 259 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 2 TCON Timer 0 1 Control Bit 7 6 5 4 3 2 1 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0x88 bit addressable Bit Name Reset Access Description 7 TF1 0 RW Timer 1 Overflow Flag Set to 1 by hardware when Timer 1 overflows This flag can be cleared by firmware but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine 6 TR1 0 RW Timer 1 Run Control Timer 1 is enabled by setting this bit to 1 5 TFO 0 RW Timer 0 Overflow Flag Set to 1 by hardware when Timer 0 overflows This flag can be cleared by firmware but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine 4 TRO 0 RW Timer 0 Run Control Timer 0 is enabled by setting this bit to
83. enters Slave Receiver Mode when a START followed by a slave address and direction bit WRITE in this case is received If hardware ACK generation is disabled upon entering Slave Receiver Mode an interrupt is generated and the ACKRQ bit is set The software must respond to the received slave address with an ACK or ignore the received slave address with a NACK If hardware ACK generation is enabled the hardware will apply the ACK for a slave address which matches the criteria set up by SMBOADR and SMBOADM The interrupt will occur after the ACK cycle If the received slave address is ignored by software or hardware slave interrupts will be inhibited until the next START is detected If the received slave address is acknowledged zero or more data bytes are received If hardware ACK generation is disabled the ACKRQ is set to 1 and an interrupt is generated after each received byte Software must write the ACK bit at that time to ACK or NACK the received byte With hardware ACK generation enabled the SMBus hardware will automatically generate the ACK NACK and then post the interrupt It is important to note that the appropriate ACK or NACK value should be set up by the software prior to receiving the byte when hardware ACK generation is enabled The interface exits Slave Receiver Mode after receiving a STOP The interface will switch to Slave Transmitter Mode if SMBODAT is written while an active Slave Receiver Figure 18 9 Typical Slave Write Se
84. following A flash write or erase is attempted above user code space A flash read is attempted above user code space A program read is attempted above user code space i e a branch instruction to the reserved area Aflash read write or erase attempt is restricted due to a flash security setting The FERROR bit is set following a flash error reset The state of the RSTb pin is unaffected by this reset 9 3 9 Software Reset Software may force a reset by writing a 1 to the SWRSF bit The SWRSF bit will read 1 following a software forced reset The state of the RSTb pin is unaffected by this reset 9 3 10 USB Reset Writing 1 to the USBRSF bit selects USBO as a reset source With USBO selected as a reset source a system reset will be generated when either of the following occur RESET signaling is detected on the USB network The USB Function Controller USBO must be enabled for RESET signaling to be detected Afalling or rising voltage on the VBUS pin The USBRSF bit will read 1 following a USB reset The state of the RSTb pin is unaffected by this reset silabs com Smart Connected Energy friendly Rev 0 2 65 EFM8UB2 Reference Manual Reset Sources and Power Supply Monitor 9 4 Reset Sources and Supply Monitor Control Registers 9 4 1 RSTSRC Reset Source Bit 7 6 5 4 3 2 1 0 USBRSF FERROR CORSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Access R
85. for details on the locations of each SFR It is good practice inside of interrupt service routines to save the current SFRPAGE at the beginning of the ISR and restore this value at the end Interrupts and SFR Paging In any system which changes the SFRPAGE while interrupts are active it is good practice to save the current SFRPAGE value upon ISR entry and then restore the SFRPAGE before exiting the ISR This ensures that SFRPAGE will remain at the desired setting when returning from the ISR silabs com Smart Connected Energy friendly Rev 0 2 12 EFM8UB2 Reference Manual Special Function Registers 3 2 Special Function Register Memory Map Table 3 1 Special Function Registers by Address Address SFR Page Address SFR Page bit addressable 0x00 OxOF bit addressable 0x00 0x0F 0x80 PO OxCO SMBOCNO SMB1CNO 0x81 SP OxC1 SMBOCF SMB1CF 0x82 DPL OxC2 SMBODAT SMB1DAT 0x83 DPH 0xC3 ADCOGTL 0x84 EMIOTC OxC4 ADCOGTH 0x85 EMIOCF 0 5 ADCOLTL 0x86 LFOOCN 0xC6 ADCOLTH 0x87 PCONO OxC7 P4 0x88 TCON OxC8 TMR2CNO TMR5CNO 0x89 TMOD OxC9 REGO1CN Ox8A TLO OxCA TMR2RLL TMR5RLL 0x8B TL1 OxCB TMR2RLH TMR5RLH 0x8c THO OxCC TMR2L TMR5L 0x8D TH1 OxCD TMR2H TMR5H Ox8E CKCONO OxCE SMBOADM SMB1ADM Ox8F PSCTL OxCF SMBOADR SMB1ADR 0x90 P1 OxDO PSW 0x91 TMR3CNO TMR4CNO OxD1 REFOCN 0x92 TMR3RLL TMR4RLL 0 02 SCON1 0x93 T
86. fraction of an LSB for example 0 25 to settle within 1 4 LSB tis the required settling time in seconds is the sum of the ADC mux resistance and any external source resistance CsAMPLE is the size of the ADC sampling capacitor nis the ADC resolution in bits When measuring any internal source RtotaL reduces to Ryux See the electrical specification tables in the datasheet for ADC mini mum settling time requirements as well as the mux impedance and sampling capacitor values silabs com Smart Connected Energy friendly Rev 0 2 115 EFM8UB2 Reference Manual Analog to Digital Converter ADCO Configuring the Tracking Time The ADTM bit controls the ADC track and hold mode In its default state the ADC input is continuously tracked except when a conver sion is in progress A conversion will begin immediately when the start of conversion trigger occurs When the ADTM bit is logic 1 each conversion is preceded by a tracking period of 4 SAR clocks after the start of conversion signal for any internal conversion trigger source When the CNVSTR signal is used to initiate conversions with ADTM set to 1 ADCO tracks only when CNVSTR is low conver sion begins on the rising edge of CNVSTR Setting ADTM to 1 is primarily useful when AMUX settings are frequently changed and conversions are started using the ADBUSY bit A ADCO Timing for External Trigger Source CNVSTR 123 45 6 7 8 9 10 11 12 13 14 SAR Clocks ADTM
87. friendly Rev 0 2 33 EFM8UB2 Reference Manual Interrupts 6 3 2 IP Interrupt Priority Bit 7 6 5 4 3 2 1 0 Reserved PSPIO PT2 PSO PT1 PX1 PTO Access R RW RW RW RW RW RW RW Reset 1 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0 8 bit addressable Bit Name Reset Access Description 7 Reserved Must write reset value 6 PSPIO 0 RW Serial Peripheral Interface SPIO Interrupt Priority Control This bit sets the priority of the SPIO interrupt Value Name Description 0 LOW SPIO interrupt set to low priority level 1 HIGH SPIO interrupt set to high priority level 5 PT2 0 RW Timer 2 Interrupt Priority Control This bit sets the priority of the Timer 2 interrupt Value Name Description 0 LOW Timer 2 interrupt set to low priority level 1 HIGH Timer 2 interrupt set to high priority level 4 50 0 RW UARTO Interrupt Priority Control This bit sets the priority of the UARTO interrupt Value Name Description 0 LOW UARTO interrupt set to low priority level 1 HIGH UARTO interrupt set to high priority level 3 PT1 0 RW Timer 1 Interrupt Priority Control This bit sets the priority of the Timer 1 interrupt Value Name Description 0 LOW Timer 1 interrupt set to low priority level 1 HIGH Timer 1 interrupt set to high priority level 2 PX1 0 RW External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 inte
88. in order to detect SCL low timeouts The SMBus inter face will force the associated timer to reload while SCL is high and allow the timer to count when SCL is low The timer interrupt serv ice routine should be used to reset SMBus communication by disabling and re enabling the SMBus SMBus Free Timeout detection can be enabled by setting the SMBFTE bit When this bit is set the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods SMBus Pin Swap The SMBus peripheral is assigned to pins using the priority crossbar decoder By default the SMBus signals are assigned to port pins starting with SDA on the lower numbered pin and SCL on the next available pin The SWAP bit in the SMBTC register can be set to 1 to reverse the order in which the SMBus signals are assigned silabs com Smart Connected Energy friendly Rev 0 2 228 EFM8UB2 Reference Manual System Management Bus 2 SMBO and 5 1 SMBus Timing Control The SDD field in the SMBTC register is used to restrict the detection of a START condition under certain circumstances In some sys tems where there is significant mismatch between the impedance or the capacitance on the SDA and SCL lines it may be possible for SCL to fall after SDA during an address or data transfer Such an event can cause a false START detection on the bus These kind of events are not expected a standard SMBus or I2C compliant system Note In mo
89. is pre loa ded into the transmit buffer by writing to SPInDAT and will transfer to the shift register on byte boundaries in the order in which they were written to the buffer When configured as a slave SPIO can be configured for 4 wire or 3 wire operation In the default 4 wire slave mode the NSS signal is routed to a port pin and configured as a digital input The SPI interface is enabled when NSS is logic 0 and disabled when NSS is logic 1 The internal shift register bit counter is reset on a falling edge of NSS When operated in 3 wire slave mode NSS is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode the SPI must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received The bit counter can only be reset by disabling and re enabling the SPI module with the SPIEN bit silabs com Smart Connected Energy friendly Rev 0 2 214 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO 17 3 4 Clock Phase and Polarity Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPINCFG register The CKPHA bit selects one of two clock phases edge used to latch the data The CKPOL bit selects between an active high or active low clock Both master and slave devi
90. mode TnSPLIT should be set to 0 as the full 16 bit timer is used Upon falling edge of the input capture signal the contents of the timer register TMRnH TMRnL are loaded into the reload registers TMRnRLH TMRnRLL and the TFnH flag is set By recording the difference between two successive timer capture values the period of the captured signal can be determined with respect to the selected timer clock Timer Low Clock Capture Source TMRnRLL TMRnRLH TFnH Interrupt Figure 19 8 Capture Mode Block Diagram silabs com Smart Connected Energy friendly Rev 0 2 257 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 Timer 0 1 2 3 4 and 5 Control Registers 19 4 1 CKCONO Clock Control 0 Bit 7 6 5 4 3 2 0 T3MH T3ML T2MH T2ML T1M TOM SCA Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0x0 SFR Page ALL SFR Address 0x8E Bit Name Reset Access Description 7 T3MH 0 RW Timer 3 High Byte Clock Select Selects the clock supplied to the Timer 3 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 3 high byte uses the clock defined by T3XCLK in TMR3CNO 1 SYSCLK Timer 3 high byte uses the system clock 6 T3ML 0 RW Timer 3 Low Byte Clock Select Selects the clock supplied to Timer 3 Selects the clock supplied to the lower 8 bit timer in split 8 bit timer mode V
91. n XBARE Crossbar 1 j WEAK Enable 52 PORT Px x Output ZN PAD Logic Value Port Latch or Crossbar PxMDIN x NI ND 1 for digital 0 for analog To From Analog Peripheral Px x Input Logic Value Reads 0 when pin is configured as an analog I O Lo Se Figure 11 2 Port I O Cell Block Diagram Configuring Port Pins For Analog Modes Any pins to be used for analog functions should be configured for analog mode When a pin is configured for analog I O its weak pull digital driver and digital receiver are disabled This saves power by eliminating crowbar current and reduces noise on the analog input Pins configured as digital inputs may still be used by analog peripherals however this practice is not recommended Port pins configured for analog functions will always read back a value of 0 in the corresponding Pn Port Latch register To configure a pin as analog the following steps should be taken 1 Clear the bit associated with the pin in the PnMDIN register to 0 This selects analog mode for the 2 Set the bit associated with the pin in the Pn register to 1 3 Skip the bit associated with the pin in the PnSKIP register to ensure the crossbar does not attempt to assign a function to the pin silabs com Smart Connected Energy friendly Rev 0 2 79 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts Configuring Port Pins For Digital Modes Any pins to
92. of the C2 protocol Bit Name Reset Access Description 7 0 C2ADD 0x00 RW C2 Address The C2ADD register is accessed via the C2 interface The value written to C2ADD selects the target data register for C2 Data Read and Data Write commands 0x00 C2DEVID 0x01 C2REVID 0x02 C2FPCTL 0 4 C2FPDAT 22 4 2 C2DEVID C2 Device ID Bit 7 6 5 4 3 2 1 0 C2DEVID Access R Reset 0x28 C2 Address 0x00 Reset Access Description 7 0 C2DEVID 0x28 R Device ID This read only register returns the 8 bit device ID 0x28 EFM8UB2 22 4 3 C2REVID C2 Revision ID Bit 7 6 5 4 3 2 1 0 2 Access R Reset Varies C2 Address 0x01 Reset Access Description 7 0 C2REVID Varies R Revision ID This read only register returns the 8 bit revision ID For example 0x02 Revision A silabs com Smart Connected Energy friendly Rev 0 2 293 EFM8UB2 Reference Manual C2 Debug and Programming Interface 22 4 4 C2FPCTL C2 Flash Programming Control Bit 7 6 5 4 3 2 1 0 C2FPCTL Access RW Reset 0x00 C2 Address 0x02 Bit Name Reset Access Description 7 0 C2FPCTL 0x00 RW Flash Programming Control Register This register is used to enable flash programming via the C2 interface To enable C2 flash programming the following co des must be written in order 0x02 0x01 Note that once C2 flash programming is enabled
93. parity of the oldest byte in the FIFO available when reading SBUF 1 does not match the selected parity type This bit must be cleared by firmware Value Name Description 0 NOT SET Parity error has not occurred 1 SET Parity error has occurred 5 Reserved Must write reset value 4 REN 0 RW Receive Enable This bit enables disables the UART receiver When disabled bytes can still be read from the receive FIFO but the receiver will not place new data into the FIFO Value Name Description 0 RECEIVE DISABLED UART1 reception disabled 1 RECEIVE ENABLED UART reception enabled 3 TBX 0 RW Extra Transmission Bit The logic level of this bit will be assigned to the extra transmission bit when XBE 1 in the SMOD1 register This bit is not used when parity is enabled 2 RBX 0 R Extra Receive Bit RBX is assigned the value of the extra bit when XBE 1 in the SMOD1 register This bit is not valid when parity is enabled or when XBE is cleared to 0 1 TI 0 RW Transmit Interrupt Flag Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit When the interrupt is enabled setting this bit causes the CPU to vector to the UART1 interrupt service routine This bit must be cleared by firm ware silabs com Smart Connected Energy friendly Rev 0 2 286 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Reset Access Description 0 RI 0 R Receive Interrupt Flag
94. peripheral will check for a logic 1 on the 9th bit Value Name Description 0 MULTI DISABLED Ignore level of 9th bit Stop bit 1 MULTI ENABLED RI is set and an interrupt is generated only when the stop bit is logic 1 Mode 0 or when the 9th bit is logic 1 Mode 1 4 REN 0 RW Receive Enable Value Name Description 0 RECEIVE DISABLED UARTO reception disabled 1 RECEIVE ENABLED UARTO reception enabled 3 TB8 0 RW Ninth Transmission Bit The logic level of this bit will be sent as the ninth transmission bit in 9 bit UART Mode Mode 1 Unused in 8 bit mode Mode 0 2 RB8 0 RW Ninth Receive Bit RB8 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 1 TI 0 RW Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UARTO after the 8th bit in 8 bit UART Mode or at the begin ning of the STOP bit in 9 bit UART Mode When the UARTO interrupt is enabled setting this bit causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared manually by firmware 0 RI 0 RW Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UARTO set at the STOP bit sampling time When the UARTO interrupt is enabled setting this bit to 1 causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared manually by firmware silabs com Smart Connected Energy friendly Rev 0 2 281 EFM8U
95. proceed While SI is set SCL is held low and SMBus is stalled SI must be cleared by firmware Clearing SI initiates the next SMBus state machine operation 18 6 3 SMB1ADR SMBus 1 Slave Address Bit 7 6 5 4 3 2 1 0 SLV GC Access RW RW Reset 0x00 0 SFR Page OxF SFR Address OxCF Bit Name Reset Access Description 7 1 SLV 0x00 RW SMBus Hardware Slave Address Defines the SMBus Slave Address es for automatic hardware acknowledgement Only address bits which a 1 in the corresponding bit position in SLVM are checked against the incoming address This allows multiple addresses to be recog nized 0 GC 0 RW General Call Address Enable When hardware address recognition is enabled EHACK 1 this bit will determine whether the General Call Address 0x00 is also recognized by hardware Value Name Description 0 IGNORED General Call Address is ignored 1 RECOGNIZED General Call Address is recognized silabs com Smart Connected Energy friendly Rev 0 2 246 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 18 6 4 SMB1ADM SMBus 1 Slave Address Mask Bit 7 6 5 4 3 2 1 0 SLVM EHACK Access RW RW Reset Ox7F 0 SFR Page OxF SFR Address 0xCE Bit Name Reset Access Description 7 1 SLVM Ox7F RW SMBus Slave Address Mask Defines which bits of register SMB1ADR are compared with an incoming address byte
96. register at the time of the update in this equation WDT reset is generated when PCAOL overflows while there is a match between PCAOCPH4 and PCAOH Software may force a WDT reset by writing a 1 to the CCF4 flag in the PCAOCNO register while the WDT is enabled silabs com Smart Connected Energy friendly Rev 0 2 146 EFM8UB2 Reference Manual Programmable Counter Array Watchdog Timer Usage To configure the WDT perform the following tasks 1 Disable the WDT by writing a 0 to the WDTE bit 2 Select the desired PCA clock source with the CPS field 3 Load the WDT PCAOCPL with the desired WDT update offset value 4 Configure the PCA Idle mode set CIDL if the WDT should be suspended while the CPU is in Idle mode 5 Enable the WDT by setting the WDTE bit to 1 6 Reset the WDT timer by writing to PCAOCPH4 The PCA clock source and Idle mode select cannot be changed while the WDT is enabled The watchdog timer is enabled by setting the WDTE or WDLCK bits in the PCAOMD register When WDLCK is set the WDT cannot be disabled until the next system reset If WDLCK is not set the WDT is disabled by clearing the WDTE bit The WDT is enabled following any reset The PCAO counter clock defaults to the system clock divided by 12 PCAOL defaults to 0x00 and PCAOCPL2 defaults to 0 00 This results in a WDT timeout interval of 256 PCA clock cycles or 3072 system clock cycles lists some example timeout intervals for typical
97. reset silabs com Smart Connected Energy friendly Rev 0 2 26 EFM8UB2 Reference Manual Flash Memory 4 4 3 FLSCL Flash Scale Bit 7 6 5 4 3 2 1 0 FOSE Reserved FLRT Reserved Access RW RW RW RW Reset 1 0 0 0 0 0 SFR Page ALL SFR Address 0xB6 Bit Name Reset Access Description 7 FOSE 1 RW Flash One Shot Enable This bit enables the flash read one shot recommended If the flash one shot is disabled the flash sense amps are ena bled for a full clock cycle during flash reads increasing the device power consumption Value Name Description 0 DISABLED Disable the flash one shot 1 ENABLED Enable the flash one shot recommended 6 5 Reserved Must write reset value 4 FLRT 0 RW Flash Read Timing This bit should be programmed to the smallest allowed value according to the system clock speed Value Name Description 0 SYSCLK_BE SYSCLK lt 25 MHz LOW_25 MHZ 1 SYSCLK_BE SYSCLK lt 48 MHz LOW_48 MHZ 3 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Rev 0 2 27 EFM8UB2 Reference Manual Device Identification 5 Device Identification 5 1 Unique Identifier A 128 bit unique identifier UID is pre loaded upon device reset into the last bytes of the XRAM area on all devices The UID can be read by firmware using MOVX instructions and through the debug port As the UID appear
98. silabs com Smart Connected Energy friendly Rev 0 2 89 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 5 POMDIN Port 0 Input Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address OxF1 Bit Name Reset Access Description 7 B7 1 RW Port 0 Bit 7 Input Mode Value Name Description 0 ANALOG PO0 7 pin is configured for analog mode 1 DIGITAL 0 7 pin is configured for digital mode 6 B6 1 RW Port 0 Bit 6 Input Mode See bit 7 description 5 B5 1 RW Port 0 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 0 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 0 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 0 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 0 Bit 1 Input Mode See bit 7 description 0 0 1 RW Port 0 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled silabs com Smart Connected Energy friendly Rev 0 2 90 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 6 POMDOUT Port 0 Output Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page
99. the FIFO RAM directly using MOVX instructions the following conditions must be met 1 The USBFAE bit in register EMIOCF must be set to 1 2 The USB clock must be greater than or equal to twice the SYSCLK USBCLK gt 2 x SYSCLK When the USBFAE bit is set the USB FIFO space is mapped into XRAM space at addresses 0x0400 to 0x07FF The normal XRAM on chip or external at the same addresses cannot be accessed when the USBFAE bit is set to 1 Note The USB clock must be active when accessing FIFO space 16 3 7 Function Addressing The FADDR register holds the current USB function address Software should write the host assigned 7 bit function address to the FADDR register when received as part of a SET ADDRESS command A new address written to FADDR will not take effect USB will not respond to the new address until the end of the current transfer typically following the status phase of the SET ADDRESS com mand transfer The UPDATE bit is set to 1 by hardware when software writes a new address to the FADDR register Hardware clears the UPDATE bit when the new address takes effect silabs com Smart Connected Energy friendly Rev 0 2 185 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 3 8 Function Configuration and Control The USB register POWER is used to configure and control the USB block at the device level enable disable Reset Suspend Resume handling etc USB Reset The USBRST bit is set to 1 by hardwar
100. the bit associated with the pin in the Pn register to 1 This tells the output driver to drive logic high Because the is config ured as open drain the high side driver is disabled and the pin may be used as an input Open drain outputs are configured exactly as digital inputs The pin may be driven low by an assigned peripheral or by writing O to the associated bit in the Pn register if the signal is a GPIO To configure a pin as a digital push pull output 1 Set the bit associated with the pin in the PnMDIN register to 1 This selects digital mode for the pin 2 Set the bit associated with the pin in the PnMDOUT register to 1 This configures the pin as push pull If a digital pin is to be used as a general purpose or with a digital function that is not part of the crossbar the bit associated with the pin in the PnSKIP register can be set to 1 to ensure the crossbar does not attempt to assign a function to the pin The crossbar must be enabled to use port pins as standard port I O in output mode Port output drivers of all I O pins are disabled whenever the crossbar is disabled 11 3 2 Analog and Digital Functions 11 3 2 1 Port I O Analog Assignments The following table displays the potential mapping of port I O to each analog function Table 11 1 Port I O Assignment for Analog Functions Analog Function Potentially Assignable Port Pins SFR s Used For Assignment ADC Input P0 0 PO 7 P1 2 P1 4 ADCOMX
101. the next system reset Flash writes and erases will also be disabled if a flash write or erase is attempted before the key codes have been written properly The flash lock resets after each write or erase the key codes must be written again before another flash write or erase operation can be performed 4 3 2 2 Flash Page Erase Procedure The flash memory is erased one page at a time by firmware using the MOVX write instruction with the address targeted to any byte within the page Before erasing a page of flash memory flash write and erase operations must be enabled by setting the PSWE and PSEE bits in the PSCTL register to logic 1 this directs the MOVX writes to target flash memory and enables page erasure and writing the flash key codes in sequence to the FLKEY register The PSWE and PSEE bits remain set until cleared by firmware Erase operation applies to an entire page setting all bytes in the page to OxFF To erase an entire page perform the following steps 1 Disable interrupts recommended 2 Write the first key code to FLKEY 5 3 Write the second key code to FLKEY OxF1 4 Set the PSEE bit register PSCTL 5 Set the PSWE bit register PSCTL 6 Using the MOVX instruction write a data byte to any location within the page to be erased 7 Clear the PSWE and PSEE bits 4 3 2 3 Flash Byte Write Procedure The flash memory is written by firmware using the MOVX write instruction with the address and data byte to be programm
102. to 1 to generate a STALL handshake in response to an IN token Firmware should clear this bit to 0 to terminate the STALL signal This bit has no effect in Isochronous mode 3 FLUSH 0 RW FIFO Flush Writing a 1 to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO The FIFO pointer is reset and the INPRDY bit is cleared If the FIFO contains multiple packets firmware must write 1 to FLUSH for each packet Hardware resets the FLUSH bit to 0 when the FIFO flush is complete 2 UNDRUN 0 RW Data Underrun Flag The function of this bit depends on the IN Endpoint mode Isochronous Set when zero length packet is sent after an IN token is received while bit INPRDY 0 Interrupt Bulk Set when a NAK is returned in response to an IN token This bit must be cleared by firmware 1 FIFONE 0 RW FIFO Not Empty Value Name Description 0 EMPTY The IN Endpoint FIFO is empty 1 NOT EMPTY The IN Endpoint FIFO contains one or more packets 0 INPRDY 0 RW In Packet Ready Firmware should write 1 to this bit after loading a data packet into the IN Endpoint FIFO Hardware clears INPRDY due to any of the following 1 A data packet is transmitted 2 Double buffering is enabled DBIEN 1 and there is an open FIFO packet slot 3 If the endpoint is in Isochronous Mode ISO 1 and ISOUD 1 INPRDY will read 0 until the next SOF is received An interrupt if enabled will be generated when hardware clears INPRDY as a result of a packet being
103. to a 1 Rev 0 2 158 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Programmable Counter Array 14 4 17 PCAOCPM4 PCA Channel 4 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xDE Bit Name Reset Access Description 7 16 0 RW Channel 4 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled Value Name Description 0 8 BIT 8 bit PWM selected 1 16_BIT 16 bit PWM selected 6 ECOM 0 RW Channel 4 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel 4 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 4 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 4 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCF4 bit in the PCAOMD register to be set to logic 1 2 TOG 0 RW Channel 4 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX4 pin to toggle If the PWM bit is als
104. transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Master 5 Device Device Figure 20 5 Multi Processor Mode Interconnect Diagram silabs com Smart Connected Energy friendly Rev 0 2 280 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 4 UARTO Control Registers 20 4 1 SCONO UARTO Serial Port Control Bit 7 6 5 4 3 2 1 0 SMODE Reserved MCE REN TB8 RB8 Access RW R RW RW RW RW RW RW Reset 0 1 0 0 0 0 0 0 SFR Page ALL SFR Address 0x98 bit addressable Bit Name Reset Access Description 7 SMODE 0 RW Serial Port 0 Operation Mode Selects the UARTO Operation Mode Value Name Description 0 8 BIT 8 bit UART with Variable Baud Rate Mode 0 1 9 BIT 9 bit UART with Variable Baud Rate Mode 1 6 Reserved Must write reset value 5 MCE 0 RW Multiprocessor Communication Enable This bit enables checking of the stop bit or the 9th bit in multi drop communication buses The function of this bit is depend ent on the UARTO operation mode selected by the SMODE bit In Mode 0 8 bits the peripheral will check that the stop bit is logic 1 In Mode 1 9 bits the
105. transmitted This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 207 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 24 EINCSRH USBO IN Endpoint Control High Bit 7 6 5 4 3 2 0 DBIEN ISO DIRSEL Reserved FCDT SPLIT Reserved Access RW RW RW R RW RW R Reset 0 0 0 0 0 0 0x0 Indirect Address 0x12 Bit Name Reset Access Description 7 DBIEN 0 RW IN Endpoint Double Buffer Enable Value Name Description 0 DISABLED Disable double buffering for the selected IN endpoint 1 ENABLED Enable double buffering for the selected IN endpoint 6 ISO 0 RW Isochronous Transfer Enable This bit enables or disables Isochronous transfers on the current endpoint Value Name Description 0 DISABLED Endpoint configured for Bulk Interrupt transfers 1 ENABLED Endpoint configured for Isochronous transfers 5 DIRSEL 0 RW Endpoint Direction Select This bit is valid only when the selected FIFO is not split SPLIT 0 Value Name Description 0 OUT Endpoint direction selected as OUT 1 IN Endpoint direction selected as IN 4 Reserved Must write reset value 3 FCDT 0 RW Force Data Toggle Value Name Description 0 ACK TOGGLE Endpoint data toggle switches only when an ACK is received following a data packet transmission 1 ALWAYS TOGGLE Endpoint data toggle force
106. wi 249 8 3 3 LFOSCO 80 kHz Internal Oscillator BO 8 34 External Crystal 20 22 401 8 3 5 External RC C Modes 53 8 3 6 External CMOS 5 s 155 8 3 7 Clock Configuration 2 w amp aaa x 599 8 4 Clocking and Oscillator Control Registers 56 8 4 1 CLKSEL ClockSelect awh A X ott 56 8 4 2 HFOOCAL High Frequency Oscillator Calibration a Mi a rin b de PUER 57 8 4 3 HFOOCN High Frequency Oscillator Control 58 8 4 4 LFOOCN Low Frequency Oscillator Control 59 8 4 5 XOSCOCN External Oscillator Control 60 9 Reset Sources and Power Supply Monitor 61 921 Introd ctiOnz due mom deos e uh US WI ue det e uox 461 92 JeatureSe a lus vengno Rcs Wo Xt aX due Wi um eT L Rd ar vhs A Table of Contents 297 10 11 9 3 Functional Description 9 3 1 Device Reset 9 3 2 Power On Reset 9 3 3 Supply Monitor Reset 9 3 4 External Reset 9 3 5 Missing Clock Detector Reset 9 3 6 Comparator CMPO Reset 9 3 7 PCA Watchdog Timer Reset 9 3 8 Flash Error Reset 9 3 9 Software Reset 9 3 10 US
107. write reset value 1 0 CPMD 0x2 RW Comparator Mode Select These bits affect the response time and power consumption of the comparator Value Name Description 0x0 MODEO Mode 0 Fastest Response Time Highest Power Consumption 0 1 MODE1 Mode 1 0x2 MODE2 Mode 2 0x3 MODE3 Mode 3 Slowest Response Time Lowest Power Consumption silabs com Smart Connected Energy friendly Rev 0 2 132 EFM8UB2 Reference Manual Comparators CMPO and 1 13 4 3 CMPOMX Comparator 0 Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Reserved CMXN Reserved Access RW RW RW RW Reset 0 0x0 0 0x0 SFR Page ALL SFR Address 0x9F Bit Name Reset Access Description 7 Reserved Must write reset value 6 4 CMXN 0x0 RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 Reserved Must write reset value 2 0 0 0 RW Comparator Positive Input MUX Selection This field selects the positive input for the comparator silabs com Smart Connected Energy friendly Rev 0 2 133 EFM8UB2 Reference Manual Comparators and 1 13 5 CMP1 Control Registers 13 5 1 1 0 Comparator 1 Control 0 Bit 7 6 4 1 Name CPEN CPOUT CPRIF CPFIF CPHYP CPHYN Access RW R RW RW RW RW Reset 0 0 0 0x0 0x0
108. 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxFO bit addressable Bit 7 0 Name Reset Access Description B 0x00 RW B Register This register serves as a second accumulator for certain arithmetic operations silabs com Smart Connected Energy friendly Rev 0 2 75 EFM8UB2 Reference Manual CIP 51 Microcontroller Core 10 4 6 PSW Program Status Word Bit 7 6 5 2 1 0 FO RS OV F1 PARITY Access RW RW RW RW RW RW R Reset 0 0 0 0x0 0 0 0 SFR Page ALL SFR Address 0 0 bit addressable Bit Name Reset Access Description 7 CY 0 RW Carry Flag This bit is set when the last arithmetic operation resulted in a carry addition or a borrow subtraction It is cleared to logic 0 by all other arithmetic operations 6 AC 0 RW Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into addition or a borrow from subtraction the high order nibble It is cleared to logic 0 by all other arithmetic operations 5 FO 0 RW User Flag 0 This is a bit addressable general purpose flag for use under firmware control 4 3 RS 0x0 RW Register Bank Select These bits select which register bank is used during register accesses Value Name Description 0x0 BANKO Bank 0 Addresses 0x00 0x07 Ox1 BANK1 Bank 1 Addresses 0x08 0x0F 0 2 2 Bank 2 Address
109. 0 FRMEL 0x00 R Frame Number Low This register contains bits 7 0 of the last received frame number This register is accessed indirectly using the USBOADR and USBODAT registers 16 4 13 FRAMEH USBO Frame Number High Bit 7 6 5 4 3 2 1 0 Reserved FRMEH Access R R Reset 0x00 0 0 Indirect Address OxOD Bit Name Reset Access Description 7 3 Reserved Must write reset value 2 0 FRMEH 0x0 R Frame Number High This register contains bits 10 8 of the last received frame number This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 197 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 14 IN1INT USBO IN Endpoint Interrupt Bit 7 6 4 3 2 1 0 Name Reserved IN3 IN2 IN1 EPO Access R R R R R Reset 0x0 0 0 0 0 Indirect Address 0 02 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 IN3 0 R IN Endpoint 3 Interrupt Flag This bit is cleared when firmware reads the IN1INT register Value Name Description 0 NOT SET IN Endpoint 3 interrupt inactive 1 SET IN Endpoint 3 interrupt active 2 IN2 0 R IN Endpoint 2 Interrupt Flag This bit is cleared when firmware reads the IN1INT register Value Name Description 0 NOT SET IN Endpoint 2 interrupt inactive 1 SET IN Endpoint 2 interrupt active 1
110. 0 RW SMBus Enable This bit enables the SMBus interface when set to 1 When enabled the interface constantly monitors the SDA and SCL pins 6 INH 0 RW SMBus Slave Inhibit When this bit is set to logic 1 the SMBus does not generate an interrupt when slave events occur This effectively removes the SMBus slave from the bus Master Mode interrupts are not affected 5 BUSY 0 R SMBus Busy Indicator This bit is set to logic 1 by hardware when a transfer is in progress It is cleared to logic 0 when a STOP or free timeout is sensed 4 EXTHOLD 0 RW SMBus Setup and Hold Time Extension Enable This bit controls the SDA setup and hold times Value Name Description 0 DISABLED Disable SDA extended setup and hold times 1 ENABLED Enable SDA extended setup and hold times 3 SMBTOE 0 RW SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low If Timer 3 is configured to Split Mode only the High Byte of the timer is held in reload while SCL is high Timer 3 should be programmed to generate interrupts at 25 ms and the Timer 3 interrupt service routine should reset SMBus communication 2 SMBFTE 0 RW SMBus Free Timeout Detection Enable When this bit is set to logic 1 the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods 1 0 SMBCS 0x0 RW SMBus Clock Source Selection
111. 0 TMR4RLL 0x00 RW Timer 4 Reload Low Byte When operating in one of the auto reload modes TMR4RLL holds the reload value for the low byte of Timer 4 TMRAL When operating in capture mode TMR4RLL is the captured value of TMR4L 19 4 24 TMR4RLH Timer 4 Reload High Byte Bit 7 6 5 4 3 2 1 0 TMR4RLH Access RW Reset 0x00 SFR Page OxF SFR Address 0x93 Bit Name Reset Access Description 7 0 TMR4RLH 0x00 RW Timer 4 Reload High Byte When operating in one of the auto reload modes TMR4RLH holds the reload value for the high byte of Timer 4 TMR4H When operating in capture mode TMR4RLH is the captured value of TMR4H 19 4 22 TMR4L Timer 4 Low Byte Bit 7 6 5 4 3 2 1 0 TMR4L Access RW Reset 0x00 SFR Page OxF SFR Address 0x94 Bit Name Reset Access Description 7 0 TMR4L 0x00 RW Timer 4 Low Byte In 16 bit mode the TMRA4L register contains the low byte of the 16 bit Timer 4 In 8 bit mode TMR4L contains the 8 bit low byte timer value silabs com Smart Connected Energy friendly Rev 0 2 273 EFM8UB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 23 Timer 4 High Byte Bit 7 6 5 4 3 2 1 0 TMR4H Access RW Reset 0x00 SFR Page OxF SFR Address 0x95 Bit Name Reset Access Description 7 0 TMR4H 0x00 RW Timer 4 High Byte In 16 bit mo
112. 0x34 0x34 Ox7F 1 0x34 0x00 General Call 0x34 Ox7E 0 0x34 0x35 0x34 Ox7E 1 0x34 0x35 0x00 General Call 0x70 0x73 0 0x70 0x74 0x78 Ox7C Note These addresses must be shifted to the left by one bit when writing to the SMBOADR register Software ACK Generation In general it is recommended for applications to use hardware ACK and address recognition In some cases it may be desirable to drive ACK generation and address recognition from firmware When the EHACK bit in register SMBOADM is cleared to 0 the firmware on the device must detect incoming slave addresses and ACK or NACK the slave address and incoming data bytes As a receiver writing the ACK bit defines the outgoing ACK value as a transmitter reading the ACK bit indicates the value received during the last ACK cycle ACKRQ is set each time a byte is received indicating that an outgoing ACK value is needed When is set software should write the desired outgoing value to the ACK bit before clearing SI A NACK will be generated if software does not write the ACK bit before clearing SI SDA will reflect the defined ACK value immediately following a write to the ACK bit however SCL will remain low until SI is cleared If a received slave address is not acknowledged further slave events will be ignored until the next START is detec ted SMBus Data Register The SMBus Data register SMBODAT holds a byte of serial data to be transmitted or one that has just been
113. 0x95 Bit Name Reset Access Description 7 0 TMR3H 0x00 RW Timer 3 High Byte In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer 3 In 8 bit mode TMR3H contains the 8 bit high byte timer value silabs com Smart Connected Energy friendly Rev 0 2 271 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 19 TMR4CNO Timer 4 Control 0 Bit 7 6 5 4 3 2 1 0 TF4H TF4L TF4LEN Reserved T4SPLIT TR4 Reserved T4XCLK Access RW RW RW R RW RW R RW Reset 0 0 0 0 0 0 0 0 SFR Page OxF SFR Address 0x91 Bit Name Reset Access Description 7 TF4H 0 RW Timer 4 High Byte Overflow Flag Set by hardware when the Timer 4 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 4 overflows from OxFFFF to 0 0000 When the Timer 4 interrupt is enabled setting this bit causes the CPU to vector to the Timer 4 interrupt service routine This bit must be cleared by firmware 6 TF4L 0 RW Timer 4 Low Byte Overflow Flag Set by hardware when the Timer 4 low byte overflows from OxFF to 0x00 TF4L will be set when the low byte overflows regardless of the Timer 4 mode This bit must be cleared by firmware 5 TF4LEN 0 RW Timer 4 Low Byte Interrupt Enable When set to 1 this bit enables Timer 4 Low Byte interrupts If Timer 4 interrupts are also enabled an interrupt will be gen erated
114. 1 3 IE1 0 RW External Interrupt 1 This flag is set by hardware when an edge level of type defined by IT1 is detected It can be cleared by firmware but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge triggered mode 2 IT1 0 RW Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in register ITO1CF Value Name Description 0 LEVEL INT1 is level triggered 1 EDGE INT1 is edge triggered 1 IEO 0 RW External Interrupt 0 This flag is set by hardware when an edge level of type defined by ITO is detected It can be cleared by firmware but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine edge triggered mode 0 ITO 0 RW Interrupt 0 Type Select This bit selects whether the configured INTO interrupt will be edge or level sensitive INTO is configured active low or high by the INOPL bit in register ITO1CF Value Name Description 0 LEVEL INTO is level triggered 1 EDGE INTO is edge triggered silabs com Smart Connected Energy friendly Rev 0 2 260 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 3 TMOD Timer 0 1 Mode Bit 7 6 4 3 2 1 0
115. 1 2 3 4 and 5 Control Registers 19 4 1 CKCONO Clock Control 0 19 4 2 TCON Timer 0 1 Control 19 4 3 TMOD Timer 0 1 Mode 19 4 4 CKCON1 Clock Control 1 19 4 5 TLO Timer 0 Low Byte 19 4 6 TL1 Timer 1 Low Byte 19 4 7 THO Timer 0 High Byte 19 4 8 TH1 Timer 1 High Byte 19 4 9 TMR2CNO Timer 2 Control 0 19 4 10 TMR2RLL Timer 2 Reload Low Byte 19 4 11 TMR2RLH Timer 2 Reload High Byte 19 4 12 TMR2L Timer 2 Low Byte 19 4 13 TMR2H Timer 2 High Byte 19 4 14 TMR3CNO Timer 3 Control O 19 4 15 TMR3RLL Timer 3 Reload Low Byte 19 4 16 TMR3RLH Timer Reload High Byte 19 4 17 TMR3L Timer 3 Low Byte 19 4 18 TMR3H Timer 3 High Byte Table of Contents 225 227 231 239 239 240 240 241 242 243 243 244 244 245 246 247 247 248 248 248 249 249 249 250 253 255 256 257 258 258 260 261 263 264 264 264 265 266 e 267 267 267 268 269 270 270 270 271 303 20 21 22 19 4 19 19 4 20 19 4 21 19 4 22 19 4 23 19 4 24 19 4 25 19 4 26 19 4 27 19 4 28 Universal Asynchronous Receiver Transmitter 0 UARTO TMR4CNO Timer 4 Control 0 TMRARLL Timer 4 Reload Low Byte TMRARLH Timer 4 Reload High Byte TMRAL Timer 4 Low Byte TMR4H Timer 4 High Byte TMRSCNO Timer 5 Control 0 TMR5RLL Timer 5 Reload Low Byte TMR5RLH Timer 5 Reload High By
116. 1 8 The USB clock may also be derived from an external CMOS clock with various divider options By default the clock to the USB module is turned off to save power Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator this allows the internal oscillator to meet the requirements for USB clock tolerance Clock Recovery should always be used any time the USB block is clocked from the internal HFOSC1 clock in full speed applications When operating the USB module as a low speed function with Clock Recovery software must write 1 to the CRLOW bit to enable low speed Clock Recovery Clock Recovery is typically not necessary in low speed mode Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network This mode is not required or recommended in typical USB environments 16 3 4 VBUS Control The VBUS signal is a dedicated input pin on the device which is used to indicateswhen a host device has been connected to or discon nected from the USB peripheral The USB VBUS line must be connected to the VBUS pin when using the device in a USB network The VBUS signal should only be connected to the VREGIN pin when operating the device as a bus powered function The VBUS pin may also generate interrupts on rising or falling edges if enabled The VBUS interrupt is edge sensitive and has no associated interrupt pending flag Firmware may read the VBSTAT bit i
117. 101 ADCOP 5 P2 6 P1 5 P1 5 000110 ADCOP 6 P3 0 P1 6 P1 6 000111 ADCOP 7 P3 1 P1 7 P1 7 001000 ADCOP 8 P3 4 P2 0 P2 0 001001 ADCOP 9 P3 5 P2 1 P2 1 001010 ADCOP 10 P3 7 P2 2 P2 2 001011 ADCOP 11 P4 0 P2 3 P2 3 001100 ADCOP 12 P4 3 P2 4 2 4 001101 ADCOP 13 4 4 2 5 2 5 001110 ADCOP 14 P4 5 P2 6 P2 6 001111 ADCOP 15 P4 6 P2 7 P2 7 010000 ADCOP 16 Reserved P3 0 P3 0 010001 ADCOP 17 P0 3 0 0 010010 ADCOP 18 P0 4 PO 1 PO 1 010011 ADCOP 19 P1 1 P0 4 P0 4 010100 ADCOP 20 P1 2 P0 5 P0 5 010101 ADCOP 21 P1 0 Reserved Reserved 010110 ADCOP 22 P1 3 Reserved Reserved 010111 ADCOP 23 P1 6 Reserved Reserved 011000 ADCOP 24 P1 7 Reserved Reserved 011001 ADCOP 25 P2 4 Reserved Reserved 011010 ADCOP 26 P2 7 Reserved Reserved 011011 ADCOP 27 P3 2 Reserved Reserved 011100 ADCOP 28 P3 3 Reserved Reserved silabs com Smart Connected Energy friendly Rev 0 2 112 EFM8UB2 Reference Manual Analog to Digital Converter ADCO AMXOP setting Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name 011101 ADCOP 29 P3 6 Reserved Reserved 011110 ADCOP 30 Internal Temperature Sensor 011111 ADCOP 31 VDD Supply Pin 100000 ADCOP 32 P4 1 Reserved Reserved 100001 ADCOP 33 P4 2 Reserved Reserved 100010 ADCOP 34 P4 7 Reserved Reserved 100011 111111 ADCOP 35 ADCOP 63 Reserved Reserved Reserved Table 12 2 ADCO Negative Input Multiplexer Channels
118. 111 1 6 MHz f lt 3 2 MHz K Factor 1590 f 6 8 MHz C 46 pF 8 3 6 External CMOS An external CMOS clock source is also supported as a core clock source The XTAL2 EXTCLK pin on the device serves as the external clock input when running in this mode When not selected as the SYSCLK source the EXTCLK input is always re synchronized to SYSCLK XTAL1 is not used in external CMOS clock mode Note When selecting the EXTCLK pin as a clock input source the pin should be skipped in the crossbar and configured as a digital input Firmware should ensure that the external clock source is present or enable the missing clock detector before switching the CLKSL field The external oscillator valid detector will always return zero when the external oscillator is configured to External CMOS Clock mode 8 3 7 Clock Configuration The USB module is capable of communication as a full or low speed USB function Communication speed is selected via the SPEED bit in USBOXCN When operating as a low speed function the USB clock must be 6 MHz When operating as a full speed function the USB clock must be 48 MHz The USB clock is selected using the USBCLK bit field in the CLKSEL register A typical full speed applica tion would configure the USB clock to run directly from the HFOSC1 oscillator while a typical low speed application would configure the clock for 5 1 8 The USB clock may also be derived from an external CMOS clock with vario
119. 14 4 6 0 PCA Channel 0 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 PCAOCPLO Access RW Reset 0x00 SFR Page ALL SFR Address 0xFB Bit Name Reset Access Description 7 0 PCAOCPLO 0x00 RW PCA Channel 0 Capture Module Low Byte PCAOCPLO register holds the low byte LSB of the 16 bit capture module A write to this register will clear the module s ECOM bit to a 0 14 4 7 PCAOCPHO PCA Channel 0 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxFC Bit Name Reset Access Description 7 0 PCAOCPH 0 00 RW PCA Channel 0 Capture Module High Byte 0 The register holds the high byte MSB of the 16 bit capture module A write to this register will set the module s ECOM bit to a 1 Rev 0 2 152 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Programmable Counter Array 14 4 8 PCAOCPM1 PCA Channel 1 Capture Compare Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xDB Bit Name Reset Access Description 7 16 0 RW Channel 1 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modula
120. 2 2 2 140 6 3 6 EIP2 Extended Interrupt Priority 2 s A 7 Power Management and Internal Regulators 42 TA Introductions mu os we G Gr G D d Go So T sterk GS om 242 7 2 Features 2 2 1483 TS dle tec BAA ie eR IR un SO amp ons Ae del at S 7 4 144 7 5 Suspend Mode 2 2 144 7 6 Shutdown Mode 2 s s 2 2 s s s o s s s s MA 7 7 5V to 3 3V Regulator 5 2525 Ge WS leo XR ge X KJE Rhn Ue DES dE CE Uk DR Gc oS 7 8 Power Management Control Registers AB 7 8 1 PCONO Power Control j AS 4 de WO ve ak Xe X 2 5 WO sn e 7 8 2 REGO1CN Voltage Regulator Control eq dede deg BO at ce ve 8 Clocking and Oscillators 49 8 1 Introduction s 49 82 Features i i G see CM Ee Rm ue lh cos 7249 8 3 Functional Description s ee AY 8 3 1 Clock Selection he Ay Gis es Qe seus Me G uu S4 8 3 2 HFOSCO 48 MHz Internal Oscillator de Wish ue tO GN lof Xm
121. 4 bytes long Endpoint1 is 128 bytes long Endpoint2 is 256 bytes long and Endpoint3 is 512 bytes long FIFO space allocated for Endpoints1 3 is also configurable as IN OUT or both split mode half IN half OUT 0x07FF Endpoint 0 0 07 0 0x07BF Endpoint 1 0x0740 128 Bytes 0x073F i l Configurable as Pen IN OUT or both Split 0x0640 0 06 Endpoint 3 512 Bytes 0x0440 0x043F 0x0400 64 Bytes USB Clock Domain _ System Clock Domain OxO3FF User XRAM 1024 Bytes 0x0000 Figure 16 3 FIFO Memory Map FIFO Split Mode The FIFO space for Endpoints1 3 can be split such that the upper half of the FIFO space is used by the IN endpoint and the lower half is used by the OUT endpoint For example if the Endpoint3 FIFO is configured for Split Mode the upper 256 bytes are used by End point3 IN and the lower 256 bytes are used by Endpoint3 OUT If an endpoint FIFO is not configured for split mode that endpoint IN OUT pair s FIFOs are combined to form a single IN or OUT FIFO In this case only one direction of the endpoint IN OUT pair may be used at a time The endpoint direction IN OUT is determined by the DIRSEL bit in the corresponding endpoint s EINCSRH register silabs com Smart Connected Energy friendly Rev 0 2 184 EFM8UB2 Reference Manual Universal Serial Bus USBO FIFO Double Buffering FIFO slots for Endpoints1 3 can be configured for double buffered mode In this mode the maxi
122. 7 0 SFRPAGE 0x00 RW SFR Page Specifies the SFR Page used when reading writing or modifying special function registers silabs com Smart Connected Energy friendly Rev 0 2 19 EFM8UB2 Reference Manual Flash Memory 4 Flash Memory 4 1 Introduction On chip re programmable flash memory is included for program code and non volatile data storage The flash memory is organized in 512 byte pages It can be erased and written through the C2 interface or from firmware by overloading the MOVX instruction Any indi vidual byte in flash memory must only be written once between page erase operations OxFFFF Reserved OxFBFF Lock Byte OxFBFE Security Page 512 Bytes 0 00 63 KB Flash 126 x 512 Byte pages 0x0000 Figure 4 1 Flash Memory Map 64 KB Devices silabs com Smart Connected Energy friendly Rev 0 2 20 EFM8UB2 Reference Manual Flash Memory OxFFFF Ox7FFF Ox7FFE 0x7E00 0x0000 Reserved Lock Byte Security Page 512 Bytes 32 KB Flash 64 x 512 Byte pages Figure 4 2 Flash Memory Map 32 KB Devices 4 2 Features The flash memory has the following features Up to 64 KB organized in 512 byte sectors In system programmable from user firmware Security lock to prevent unwanted read write erase access silabs com Smart Connected Energy friendly Rev 0 2 21 EFM8UB2 Reference Manual Flash Memory 4 3 Functional Descr
123. A to direct byte 2 2 2 MOV direct Rn Move Register to direct byte 2 2 2 MOV direct direct Move direct byte to direct byte 3 3 3 MOV direct Ri Move indirect RAM to direct byte 2 2 2 MOV direct data Move immediate to direct byte 3 3 3 MOV Ri A Move A to indirect RAM 1 2 2 MOV direct Move direct byte to indirect RAM 2 2 2 MOV Ri data Move immediate to indirect RAM 2 2 2 MOV DPTR data16 Load DPTR with 16 bit constant 3 3 3 MOVC A A DPTR Move code byte relative DPTR to A 1 3 6 MOVC A Move code byte relative PC to A 1 3 3 MOVX A Ri Move external data 8 bit address to A 1 3 3 MOVX Ri A Move A to external data 8 bit address 1 3 3 MOVX A DPTR Move external data 16 bit address to A 1 3 3 MOVX DPTR A Move A to external data 16 bit address 1 3 3 PUSH direct Push direct byte onto stack 2 2 2 POP direct Pop direct byte from stack 2 2 2 XCH A Rn Exchange Register with A 1 1 1 XCH A direct Exchange direct byte with A 2 2 2 XCH A Ri Exchange indirect RAM with A 1 2 2 XCHD Ri Exchange low nibble of indirect RAM with A 1 2 2 Boolean Manipulation CLRC Clear Carry 1 1 1 CLR bit Clear direct bit 2 2 2 Set Carry 1 1 2 SETB bit Set direct bit 2 2 2 CPL C Complement Carry 1 1 1 CPL bit Complement direct bit 2 2 2 ANL C bit AND direct bit to Carry 2 2 2 ANL C bit AND complement of direct bit to Carry 2 2 2 ORL C bit OR direct bit to carry 2 2 2 silabs com Smart Connected
124. ABLED Weak Pullups disabled 6 XBARE 0 RW Crossbar Enable Value Name Description 0 DISABLED Crossbar disabled 1 ENABLED Crossbar enabled 5 T1E 0 RW T1 Enable Value Name Description 0 DISABLED T1 unavailable at Port pin 1 ENABLED T1 routed to Port pin 4 TOE 0 RW TO Enable Value Name Description 0 DISABLED TO unavailable at Port pin 1 ENABLED TO routed to Port pin 3 ECIE 0 RW PCAO External Counter Input Enable Value Name Description 0 DISABLED ECI unavailable at Port pin 1 ENABLED ECI routed to Port pin 2 0 PCAOME 0x0 RW PCA Module I O Enable Value Name Description 0x0 DISABLED All PCA I O unavailable at Port pins 0 1 routed to Port pin 0x2 CEXO CEX1 CEX1 routed to Port pins 0x3 CEXO CEX1 CEX2 CEX1 2 routed to Port pins silabs com Smart Connected Energy friendly Rev 0 2 87 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 0 4 0 5 Reset Access Description CEXO CEX1 2 CEX1 CEX2 CEX3 routed to Port pins EX3 CEXO CEX1 CEX2 CEX1 CEX2 CEX3 CEXA routed to Port pins EX3 CEX4 11 4 3 XBR2 Port I O Crossbar 2 Bit 7 6 5 4 3 2 1 0 Reserved SMB1E URT1E Access RW RW RW Reset 0x00 0 0 SFR Page ALL SFR Address OxE3 Bit Name Reset Access Description 7 2 Reserved Must write reset value 1 SMB1E 0 RW SMBus1 I O
125. ADCOLT registers may be configured to set the ADWINT flag when the ADC output code is above below beween or outside of specific values Table 12 5 ADC Window Comparator Example Above 0x0080 Comparison Register Settings Output Code ADCOH L OxO3FF 0x0081 ADWINT Effects ADWINT 1 ADCOGTH L 0x0080 0x0080 0x007F 0x0001 ADCOLTH L 0x0000 0x0000 ADWINT Not Affected Table 12 6 ADC Window Comparator Example Below 0x0040 Comparison Register Settings ADCOGTH L 0x03FF Output Code ADCOH L OxO3FF OxO3FE 0x0041 ADCOLTH L 0x0040 0x0040 ADWINT Effects ADWINT Not Affected 0x003F 0x0000 ADWINT 1 Table 12 7 ADC Window Comparator Example Between 0x0040 and 0x0080 Comparison Register Settings Output Code ADCOH L ADWINT Effects OxO3FF ADWINT Not Affected 0x0081 ADCOLTH L 0x0080 0x0080 0x007F ADWINT 1 0x0041 silabs com Smart Connected Energy friendly Rev 0 2 118 EFM8UB2 Reference Manual Analog to Digital Converter ADCO Comparison Register Settings ADCOGTH L 0x0040 Output Code ADCOH L 0x0040 0x003F 0x0000 ADWINT Effects ADWINT Not Affected Table 12 8 ADC Window Comparator Example Outside the 0x0040 to 0x0080 range Comparison Register Settings Output Code ADCOH L Ox03FF 0x0081
126. Address 0x86 Bit Name Reset Access Description 7 OSCLEN 0 RW Internal L F Oscillator Enable This bit enables the internal low frequency oscillator Note that the low frequency oscillator is automatically enabled when the watchdog timer is active Value Name Description 0 DISABLED Internal L F Oscillator Disabled 1 ENABLED Internal L F Oscillator Enabled 6 OSCLRDY 1 R Internal L F Oscillator Ready Value Name Description 0 NOT_SET Internal L F Oscillator frequency not stabilized 1 SET Internal L F Oscillator frequency stabilized 5 2 OSCLF Varies RW Internal L F Oscillator Frequency Control Fine tune control bits for the Internal L F oscillator frequency When set to 0000b the L F oscillator operates at its fastest setting When set to 1111b the L F oscillator operates at its slowest setting The OSCLF bits should only be changed by firmware when the L F oscillator is disabled OSCLEN 0 1 0 OSCLD 0x3 RW Internal L F Oscillator Divider Select Value Name Description 0x0 DIVIDE BY 8 Divide by 8 selected 0 1 DIVIDE BY 4 Divide by 4 selected 0x2 DIVIDE BY 2 Divide by 2 selected 0x3 DIVIDE BY 1 Divide by 1 selected OSCLRDY is only set back to 0 in the event of a device reset or a change to the OSCLD bits silabs com Smart Connected Energy friendly Rev 0 2 59 EFM8UB2 Reference Manual Clocking and Oscillators 8 4 5 XOSCOCN External Oscillator Control
127. Address Endpoint 0 Endpoint 0 IN 0 00 Endpoint 0 OUT 0x00 Endpoint 1 Endpoint 1 IN 0x81 Endpoint 1 OUT 0x01 Endpoint 2 Endpoint 2 IN 0x82 Endpoint 2 OUT 0x02 Endpoint 3 Endpoint 3 IN 0x83 Endpoint 3 OUT 0x03 16 3 2 Transceiver Control The USB Transceiver is configured via the USBOXCN register This configuration includes transceiver enable disable pull up resistor enable disable and device speed selection full or low speed When bit SPEED 1 USBO operates as a full speed USB function and the on chip pull up resistor if enabled appears on the D pin When bit SPEED 0 USBO operates as a low speed USB function and the on chip pull up resistor if enabled appears on the D pin The PHYTST bits can be used for transceiver testing The pull up resistor is enabled only when VBUS is present Note The USB clock should be active before the transceiver is enabled 16 3 3 Clock Configuration The USB module is capable of communication as a full or low speed USB function Communication speed is selected via the SPEED bit in USBOXCN When operating as a low speed function the USB clock must be 6 MHz When operating as a full speed function the USB clock must be 48 MHz The USB clock is selected using the USBCLK bit field in the CLKSEL register A typical full speed applica tion would configure the USB clock to run directly from the HFOSC1 oscillator while a typical low speed application would configure the clock for 5
128. Available A10 Address Bit 10 P2 2 Not Available Not Available 11 Address Bit 11 P2 3 Not Available Not Available silabs com Smart Connected Energy friendly Rev 0 2 163 EFM8UB2 Reference Manual External Memory Interface EMIFO Non Multiplexed EMIF Description QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name Signal Name 12 Address Bit 12 P2 4 Not Available Not Available A13 Address Bit 13 P2 5 Not Available Not Available 14 Address Bit 14 P2 6 Not Available Not Available A15 Address Bit 15 P2 7 Not Available Not Available silabs com Smart Connected Energy friendly Rev 0 2 164 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 3 3 Multiplexed External Memory Interface For Multiplexed external memory interface the Data Bus and the lower 8 bits of the Address Bus share the same Port pins AD 7 0 m For most devices with an 8 bit interface the upper address bits are not used and can be used as GPIO if the external memory interface is used in 8 bit non banked mode If the external memory interface is used in 8 bit banked mode or 16 bit mode then the address pins will be driven with the upper address bits and cannot be used as GPIO LEDs A 15 8 m Address Bus 16 bit or 8 bit Ethernet Controller 8 bit E M F Interface AD 7 0 m Address Data Bus WRb RDb ALEm Figure 15 2 Multiplexed Configuration Example M
129. B Reset 9 4 Reset Sources and Supply Monitor Control Registers 9 4 1 RSTSRC Reset Source 9 4 2 VDMOCN Supply Monitor Control CIP 51 Microcontroller Core 10 1 Introduction 10 2 Features 10 3 Functional Description 10 3 1 Programming and Debugging Suppor 10 3 2 Prefetch Engine 10 3 3 Instruction Set 10 4 CPU Core Registers 10 4 1 DPL Data Pointer Low 10 4 2 DPH Data Pointer High 10 4 3 SP Stack Pointer 10 4 4 ACC Accumulator 10 4 5 B B Register 10 4 6 PSW Program Status Word 10 4 7 PFEOCN Prefetch Engine Control Port I O Crossbar and External Interrupts 11 1 Introduction 11 2 Features 11 3 Functional Description 11 3 1 Port I O Modes of Operation 11 3 2 Analog and Digital Functions 11 3 2 1 Port I O Analog Assignments 11 3 2 2 Port I O Digital Assignments 11 3 3 Priority Crossbar Decoder 11 3 3 1 Crossbar Functional Map 11 3 4 INTO and INT1 f 11 3 5 Direct Port I O Access Read Write 11 4 Port I O Control Registers 11 4 1 XBRO Port I O Crossbar 0 11 4 2 XBR1 Port I O Crossbar 1 11 4 3 XBR2 Port I O Crossbar 2 62 62 63 64 64 64 64 65 65 65 65 66 66 67 68 68 69 69 69 69 70 74 74 74 75 75 75 76 77 78 78 78 79 79 80 80 81 82 83 84 84 85 85 87 88 Table of Contents 298 12 11 4 4 Port 0 Pin Latch 11 4 5 POMDIN Port 0 Input Mode 11 4 6 POMDOUT Port 0 Ou
130. B2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 4 2 SBUFO0 UARTO Serial Port Data Buffer Bit 7 6 5 4 3 2 1 0 SBUFO Access RW Reset 0x00 SFR Page ALL SFR Address 0x99 Bit Name Reset Access Description 7 0 SBUFO 0x00 RW Serial Data Buffer This SFR accesses two registers a transmit shift register and a receive latch register When data is written to SBUFO it goes to the transmit shift register and is held for serial transmission Writing a byte to SBUFO initiates the transmission read of SBUFO returns the contents of the receive latch silabs com Smart Connected Energy friendly Rev 0 2 282 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 Universal Asynchronous Receiver Transmitter 1 UART1 21 1 Introduction UART1 is an asynchronous full duplex serial port offering a variety of data formatting options A dedicated baud rate generator with 16 bit timer and selectable prescaler is included which can generate a wide range of baud rates A received data FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs Interrupt Generation TBX extra bit Transmit Buffer Control Configuration SBUF 8 LSBs Dedicated Baud Receive Buffer Rate Generator RBX extra bit Figure 21 1 UART 1 Block Diagram 21 2 Features UART1 provides the following fea
131. Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 3 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 3 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 3 Bit 1 Output Mode See bit 7 description 0 BO 0 RW Port 3 Bit 0 Output Mode See bit 7 description Port 3 consists of 8 bits P3 0 P3 7 TQFP48 packages and 1 bit P3 0 on LOFP32 and QFN32 packages silabs com Smart Connected Energy friendly Rev 0 2 103 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 19 P3SKIP Port 3 Skip Bit 7 6 5 4 3 2 1 0 Name B7 B6 BS B4 B3 B2 1 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xDF Bit Name Reset Access Description 7 B7 0 RW Port 3 Bit 7 Skip Value Name Description 0 NOT_SKIPPED P3 7 pin is not skipped by the crossbar 1 SKIPPED P3 7 pin is skipped by the crossbar 6 B6 0 RW Port 3 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 3 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 3 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 3 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 3 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 3 Bit 1 Skip See bit 7 description 0 BO 0 RW Port 3 Bit 0 Skip See bit 7 description Port 3 consists of 8 bits P3 0 P3 7 TQFP48 packages and 1 bit P3 0 on LOFP32 and QFN32 packages
132. CIP 51 All CIP 51 instructions are the binary and functional equivalent of their MCS 51 counterparts including opcodes addressing modes and effect on PSW flags However instruction timing is much faster than that of the standard 8051 All instruction timing on the CIP 51 controller is based directly on the core clock timing This is in contrast to many other 8 bit architec tures where a distinction is made between machine cycles and clock cycles with machine cycles taking multiple core clock cycles Due to the pipelined architecture of the CIP 51 most instructions execute in the same number of clock cycles as there are program bytes in the instruction Conditional branch instructions take one or two less clock cycles to complete when the branch is not taken as opposed to when the branch is taken The following table summarizes the instruction set including the mnemonic number of bytes and number of clock cycles for each instruction Note It is recommended that the prefetch be used for optimal code execution timing However the prefetch can be disabled when the device is in Suspend mode to save power Table 10 2 CIP 51 Instruction Set Summary Mnemonic Description Clock Cycles prefetch on prefetch on SYSCLK 12 SYSCLK 48 MHz MHz FLRT 0 FLRT 1 Arithmetic Operations ADD A Rn Add register to A 1 1 1 ADD A direct Add direct byte to A 2 2 ADD A Ri Add
133. CKPHA 0 SCK T T MCKH MCKL T T MIS MIH MISO MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 9 SPI Master Timing CKPHA 1 silabs com Smart Connected Energy friendly Rev 0 2 217 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO NSS SCK MOSI PU soz MISO SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 10 SPI Slave Timing CKPHA 0 NSS 4 Tex lt SCK T 6 gt gt lt MOSI gt gt Ton Tus gt gt pm I SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 17 11 SPI Slave Timing CKPHA 1 silabs com Smart Connected Energy friendly Rev 0 2 218 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO Table 17 1 SPI Timing Parameters Parameter Description Min Max Units Master Mode Timing TMCKH SCK High Time 1 x ns TMCKL SCK Low Time 1 x Tsvscik ns Tuis MISO Valid to SCK Shift Edge 1x Tsvscik 20 ns TMIH SCK Shift Edge to MISO Change 0 ns Slave Mode Timing TsE NSS Falling to First SCK Edge 2X ns Tsp Last SCK Edge to NSS Rising 2 x TSYSCLK ns TsEz NSS Falling to MISO Valid 4 X Tevsc
134. DCO Less Than Low Byte 12 4 8 ADCOCNO ADCO Control Table of Contents 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 108 110 110 111 111 111 111 111 111 111 112 112 114 114 117 118 120 120 121 121 121 122 122 122 123 123 124 299 13 14 12 4 9 AMXOP AMUXO Positive Multiplexer Selection 12 4 10 AMXON AMUXO Negative Multiplexer Selection 12 4 11 REFOCN Voltage Reference Control Comparators and CMP1 13 1 Introduction 13 2 Features 13 3 Functional Description 13 3 1 Response Time and Supply Current 13 3 2 Hysteresis 13 3 3 Input Selection 13 3 3 1 Multiplexer Channel Selection 13 3 4 Output Routing 13 4 CMPO Control Registers 13 4 1 CMPOCNO Comparator 0 Control 0 13 4 2 CMPOMD Comparator 0 Mode 13 4 3 CMPOMX Comparator 0 Multiplexer Selection 13 5 CMP1 Control Registers 13 5 1 CMP1CNO Comparator 1 Conta 0 13 5 2 CMP1MD Comparator 1 Mode 13 5 3 CMP1MX Comparator 1 Multiplexer amp eledlidh Programmable Counter Array 0 14 1 Introduction 14 2 Features 14 3 Functional Description 14 3 1 Counter Timer 14 3 2 Interrupt Sources 14 3 3 Modules 14 3 4 Edge Triggered Capture Mode 14 3 5 Software Timer Compare Mode 14 3 6 High Speed Output Mode 14 3 7 Frequency Output Mode 14 3 8 PWM Waveform Generation 14 3 8 1 8 Bit PWM Mod
135. Digital Converter ADCO 12 1 Introduction The ADC is a successive approximation register SAR ADC with 10 bit mode integrated track and hold and a programmable window detector The ADC is fully configurable under software control via several registers The ADC may be configured to measure different signals using the analog multiplexer The voltage reference for the ADC is selectable between internal and external reference sources Positive Input Multiplexer Selection Control Configuration Window Compare VDD SAR Analog to Digital Converter Internal LDO Sensor Negative Input Multiplexer Selection GND Trigger Selection 1 2 2 4 V Reference VREF Internal LDO Clock SYSCLK Divider Figure 12 1 ADC Block Diagram silabs com Smart Connected Energy friendly Greater Than ADWINT Window Interrupt Accumulator ADINT Interrupt Flag ADBUSY On Demand Timer 0 Overflow Timer 1 Overflow CNVSTR External Pin Rev 0 2 110 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 2 Features The ADC module is a Successive Approximation Register SAR Analog to Digital Converter ADC The key features of this ADC mod ule are Up to 32 external inputs Differential or Single ended 10 bit operation Supports an output update rate of 500 ksps samples per second Asynchronous hardware conversion trigger selectable between software external I
136. Enable Value Name Description 0 DISABLED SMBus1 I O unavailable at Port pins 1 ENABLED SMBus1 routed to Port pins 0 URT1E 0 RW UARTI1 I O Output Enable Value Name Description 0 DISABLED UART1 I O unavailable at Port pin 1 ENABLED UART1 TX RX routed to Port pins silabs com Smart Connected Energy friendly Rev 0 2 88 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 4 PO Port 0 Pin Latch Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address 0x80 bit addressable Bit Name Reset Access Description 7 B7 1 RW Port 0 Bit 7 Latch Value Name Description 0 LOW 7 is low Set PO 7 to drive low 1 HIGH 7 is high Set PO 7 to drive or float high 6 B6 1 RW Port 0 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 0 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 0 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 0 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 0 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 0 Bit 1 Latch See bit 7 description 0 BO 1 RW Port 0 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input
137. Endpoint 1 3 OUT General Control Endpoints 1 3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH All OUT endpoints can be used for Interrupt Bulk or Isochronous transfers Isochronous ISO mode is enabled by writing 1 to the ISO bit in register EOUTCSRH Bulk and Interrupt transfers are handled identically by hardware An Endpoint 1 3 OUT interrupt may be generated by the following Hardware sets the OPRDY bit to 1 Hardware generates a STALL condition Operating Endpoints 1 3 as OUT Interrupt or Bulk Endpoints When the ISO bit 0 the target endpoint operates in Bulk or Interrupt mode Once an endpoint has been configured to operate in Bulk Interrupt OUT mode typically following an EndpointO SET INTERFACE command hardware will set the OPRDY bit to 1 and generate an interrupt upon reception of an OUT token and data packet The number of bytes in the current OUT data packet the packet ready to be unloaded from the FIFO is given in the EOUTCNTH and EOUTCNTL registers In response to this interrupt firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to O A Bulk or Interrupt pipe can be shut down or Halted by writing 1 to the SDSTL bit While SDSTL 1 hardware will respond to all OUT requests with a STALL condition Each time hardware generates a STALL condition an interrupt will be generated and the STSTL bit set to 1 The STSTL bit must be reset to 0 by firmware Hardware will automatically set O
138. Energy friendly Rev 0 2 72 EFM8UB2 Reference Manual CIP 51 Microcontroller Core Mnemonic Description Clock Cycles prefetch on prefetch on SYSCLK 12 SYSCLK 48 MHz MHz FLRT 0 FLRT 1 ORL C bit OR complement of direct bit to Carry 2 2 2 MOV C bit Move direct bit to Carry 2 2 2 MOV bit C Move Carry to direct bit 2 2 2 JC rel Jump if Carry is set 2 2 or4 20r6 JNC rel Jump if Carry is not set 2 20r4 20 5 JB bit rel Jump if direct bit is set 3 3or5 3or 7 JNB bit rel Jump if direct bit is not set 3 3or5 3or6 JBC bit rel Jump if direct bit is set and clear bit 3 3or5 3or 7 Program Branching ACALL addr11 Absolute subroutine call 2 4 6 LCALL addr16 Long subroutine call 3 5 7 RET Return from subroutine 1 6 8 RETI Return from interrupt 1 6 7 AJMP addr11 Absolute jump 2 4 6 LJMP addr16 Long jump 3 4 6 SJMP rel Short jump relative address 2 4 6 JMP QA DPTR Jump indirect relative to DPTR 1 3 5 JZ rel Jump if A equals zero 2 20r4 20r5 JNZ rel Jump if A does not equal zero 2 20r4 2or5 CJNE A direct rel Compare direct byte to A and jump if not equal 3 4or6 4or7 CJNE A data rel Compare immediate to A and jump if not equal 3 3or 5 3or 6 CJNE Rn data rel Compare immediate to Register and jump if not 3 3or5 3or6 equal CJNE Ri data rel Compare immediate to indirect and jump if not 3 4or6 4or7 equal DJNZ Rn rel Decrement Register and
139. FF to 0x0000 the 16 bit value in the timer reload registers TMRnRLH and TMRnRLL is loaded into the main timer count register and the High Byte Overflow Flag TFnH is set If the timer interrupts are enabled an interrupt is generated on each timer overflow Additionally if the timer interrupts are enabled and the TFnLEN bit is set an interrupt is generated each time the lower 8 bits TMRnL overflow from OxFF to 0x00 The overflow rate of the timer in split 16 bit auto reload mode is F _ F input Clock F Input Clock TIMERn 216 TMRnRLH TMRnRLL 7 65536 TMRnRLH TMRnRLL TFnL Overflow TFnLEN TFnH Overflow Interrupt TRn Timer Low Clock TMRnRLL TMRnRLH Figure 19 6 16 Bit Mode Block Diagram silabs com Smart Connected Energy friendly Rev 0 2 255 EFM8UB2 Reference Manual Timers TimerO Timer1 2 Timer3 Timer4 and Timer5 19 3 3 2 8 bit Timers with Auto Reload Split Mode When TnSPLIT is set the timer operates as two 8 bit timers TMRnH and TMRnL Both 8 bit timers operate in auto reload mode TMRnRLL holds the reload value for TMRnL TMRnRLH holds the reload value for TMRnH The TRn bit in TMRnCN handles the run control for TMRnH TMRnL is always running when configured for 8 bit auto reload mode As shown in the clock source selection tree the two halves of the timer may be clocked from SYSCLK or by the source selected by the TnXCLK bits The overflow rate of the l
140. FR are the following ANL ORL XRL JBC CPL INC DEC DJNZ and MOV CLR or SETB when the destination is an individual bit in a port SFR For these instructions the value of the latch register not the pin is read modified and written back to the SFR Rev 0 2 84 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 Port I O Control Registers 11 4 1 XBRO Port I O Crossbar 0 Bit 7 6 5 4 3 2 1 0 Name CP1AE CP1E CPOAE CPOE SYSCKE SMBOE SPIOE URTOE Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address OxE1 Bit Name Reset Access Description 7 CP1AE 0 RW Comparator1 Asynchronous Output Enable Value Name Description 0 DISABLED Asynchronous 1 unavailable at Port pin 1 ENABLED Asynchronous 1 routed to Port pin 6 0 RW Comparator1 Output Enable Value Name Description 0 DISABLED CP1 unavailable at Port pin 1 ENABLED CP1 routed to Port pin 5 CPOAE 0 RW Comparator0 Asynchronous Output Enable Value Name Description 0 DISABLED Asynchronous unavailable at Port pin 1 ENABLED Asynchronous routed to Port pin 4 CPOE 0 RW Comparator0 Output Enable Value Name Description 0 DISABLED unavailable at Port pin 1 ENABLED routed to Port pin 3 SYSCKE 0 RW SYSCLK Output Enable Va
141. Flash Programming Control 294 22 4 5 C2FPDAT C2 Flash Programming Data 294 23 Revision History 5 8 Ge E wb cu hoe Sow WES ue sous 18 295 231 RevisIOm 0 2 2 ga ur mob G UE ux TE oe M ugs Seco uo u o295 23 2 Revision 0 1 2 s 295 Table of Contents 296 Table of Contents 305 SILICON LARS ESPET Ls day eis Seas abo dei ET ee 1024 eda ci meer 3 kl E Simpilcity Studio One click access to MCU tools documentation software source code libraries amp more Available for Windows Mac and Linux www silabs com Simplicity MCU Portfolio SW HW Quality Support and Community www silabs com mcu www silabs com simplicity www silabs com quality community silabs com Disclaimer Silicon Laboratories intends to provide customers with the latest accurate and in depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products Characterization data available modules and peripherals memory sizes and memory addresses refer to each specific device and Typical parameters provided can and do vary in different applications Application examples described herein are for illustrative purposes only
142. IFO Access 16 4 7 FIFO1 USBO Endpoint 1 FIFO Access 16 4 8 FIFO2 USBO Endpoint 2 FIFO Access 16 4 9 FIFO3 USBO Endpoint 3 FIFO Access 16 4 10 FADDR USBO Function Address 16 4 11 POWER USBO Power 16 4 12 FRAMEL USBO Frame Number To 16 4 13 FRAMEH USBO Frame Number High 16 4 14 IN1INT USBO IN Endpoint Interrupt 16 4 15 OUT1INT USBO OUT Endpoint Interrupt 16 4 16 USBO Common Interrupt 16 4 17 IN1IE USBO IN Endpoint Interrupt Enable 16 4 18 OUT1IE USBO OUT Endpoint Interrupt Enable 16 4 19 CMIE USBO Common Interrupt Enable 16 4 20 EOCSR USBO EndpointO Control 16 4 21 EOCNT USBO EndpointO Data Count 16 4 22 EENABLE USBO Endpoint Enable 16 4 23 EINCSRL USBO IN Endpoint Control Low 16 4 24 EINCSRH USBO IN Endpoint Control High 16 4 25 EOUTCSRL USBO OUT Endpoint Control Low 16 4 26 EOUTCSRH USBO OUT Endpoint Control High 16 4 27 EOUTCNTL USBO OUT Endpoint Count Low 16 4 28 EOUTCNTH USBO OUT Endpoint Count High Serial Peripheral Interface SPIO 17 1 Introduction 17 2 Features 17 3 Functional Description 17 3 1 Signals 17 3 2 Master Mode Operation 17 3 3 Slave Mode Operation 17 3 4 Clock Phase and Polarity 17 3 5 Basic Data Transfer 17 3 6 SPI Timing Diagrams 17 4 SPIO Control Registers 17 4 1 SPIOCFG SPIO Configuration 17 4 2 SPIOCNO SPIO Control 17 4 3 SPIOCKR SPIO Clock Rate 17 4 4 SPIODAT SPIO Data System Management Bus 2 SMBO and SMB1
143. IN1 0 R IN Endpoint 1 Interrupt Flag This bit is cleared when firmware reads the IN1INT register Value Name Description 0 NOT SET IN Endpoint 1 interrupt inactive 1 SET IN Endpoint 1 interrupt active 0 EPO 0 R Endpoint 0 Interrupt Flag This bit is cleared when firmware reads the IN1INT register Value Name Description 0 NOT SET Endpoint 0 interrupt inactive 1 SET Endpoint 0 interrupt active This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 198 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 15 OUT1INT USBO OUT Endpoint Interrupt Bit 7 6 5 4 3 2 1 0 Name Reserved OUT3 OUT2 OUT1 Reserved Access R R R R R Reset 0x0 0 0 0 0 Indirect Address 0x04 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 OUT3 0 R OUT Endpoint 3 Interrupt Flag This bit is cleared when firmware reads the OUT1INT register Value Name Description 0 NOT_SET OUT Endpoint 3 interrupt inactive 1 SET OUT Endpoint 3 interrupt active 2 OUT2 0 R OUT Endpoint 2 Interrupt Flag This bit is cleared when firmware reads the OUT1INT register Value Name Description 0 NOT_SET OUT Endpoint 2 interrupt inactive 1 SET OUT Endpoint 2 interrupt active 1 OUT1 0 R OUT Endpoint 1 Interrupt Flag This bit is cleared when firmware reads the OUT1INT r
144. K POINTER no 1 2 lt z SRAM Q PSW 4 ADDRESS eo d ALU REGISTER 8 eo B l s DATA BUS i SFR ADDRESS BUFFER sg SFR CONTROL BUS DATA POINTER INTERFACE SFR WRITE DATA SFR READ DATA PC INCREMENTER Ds MEM_ADDRESS PROGRAM COUNTER PC 2 MEM CONTROL a MEMORY PRGM ADDRESS REG IA V INTERFACE MEM WRITE DATA a MEM READ DATA PIPELINE RESET CONTROL LOGIC SYSTEM_IRQs CLOCK INTERRUPT INTERFACE EMULATION IR STOP 08 DEATIONSIRG POWER CONTROL IDLE REGISTER FR Figure 10 1 CIP 51 Block Diagram silabs com Smart Connected Energy friendly Rev 0 2 68 EFM8UB2 Reference Manual CIP 51 Microcontroller Core Performance The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture The CIP 51 core executes 76 of its 109 instructions in one or two clock cycles with no instructions taking more than eight clock cycles The table below shows the distribution of instructions vs the number of clock cycles required for execution Table 10 1 Instruction Execution Timing Clocks to 1 2 2 or 3 3 3 or 4 4 4 or 5 5 8 Execute Number of 26 50 5 14 7 3 1 2 1 Instructions Notes 1 Conditional branch instructions indicated by 2 or 3 3 or 4 and 4 or 5 require extra clock cycles if the branch is taken See the instruc
145. K bit field and the TnML and TnMH bits Timer 2 5 may be clocked by the system clock system clock divided by 12 or external oscillator divided by 8 synchronized with SYSCLK The maximum frequency for the external oscillator is 6 Fsyscik gt Fextosc 7 When operating in one of the 16 bit modes the low side timer clock is used to clock the entire 16 bit timer TnXCLK SYSCLK 12 External Oscillator 8 To Timer Low SYSCLK Clock Input To Timer High Clock Input for split mode Timer Clock Selection Figure 19 4 Timer 2 and 3 Clock Source Selection silabs com Smart Connected Energy friendly Rev 0 2 254 EFM8UB2 Reference Manual Timers 0 Timer1 2 Timer3 Timer4 and Timer5 Capture Sources Capture mode allows an input to be measured against the selected clock source Timer 2 and Timer 3 capable of performing capture function on the low frequency oscillator output Timer 4 and Timer 5 do not support capture function i l I To Timer 2 LFOSCO kd Capture Input I 3 i 1 LFOSCO 4 gt Capture Input 1 Capture Sources Figure 19 5 Timer 2 and 3 Capture Sources 19 3 3 1 16 bit Timer with Auto Reload When TnSPLIT is zero the timer operates as a 16 bit timer with auto reload In this mode the selected clock source increments the timer on every clock As the 16 bit timer register increments and overflows from OxFF
146. Lk ns Tspz NSS Rising to MISO High Z 4 X TevscLk ns SCK High Time 5 X ns Toke SCK Low Time 5 x ns Tsis MOSI Valid to SCK Sample Edge 2 x ns TsiH SCK Sample Edge to MOSI Change 2 X ns Tsou SCK Shift Edge to MISO Change 4 X nS TsiH ee 4 to MISO Change CKPHA 6 x 8 x ns Note 1 is equal to one period of the device system clock SYSCLK silabs com Smart Connected Energy friendly Rev 0 2 219 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO 17 4 SPIO Control Registers 17 4 1 SPIOCFG SPIO Configuration Bit 7 6 5 4 3 2 1 0 SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT Access R RW RW RW R R R R Reset 0 0 0 0 0 1 1 1 SFR Page ALL SFR Address OxA1 Bit Name Reset Access Description 7 SPIBSY 0 R SPI Busy This bit is set to logic 1 when a SPI transfer is in progress master or slave mode 6 MSTEN 0 RW Master Mode Enable Value Name Description 0 MASTER_DISABLED Disable master mode Operate in slave mode 1 MASTER_ENABLED Enable master mode Operate as a master 5 CKPHA 0 RW SPIO Clock Phase Value Name Description 0 DATA_CEN Data centered on first edge of SCK period TERED_FIRST 1 DATA_CEN Data centered on second edge of SCK period TERED_SECOND 4 CKPOL 0 R
147. MR3RLH TMR4RLH OxD3 SBUF1 0x94 TMR3L TMR4L 0xD4 POSKIP 0x95 TMR3H TMR4H OxD5 P1SKIP 0x96 USBOADR OxD6 P2SKIP 0x97 USBODAT OxD7 USBOXCN 0x98 SCONO 0xD8 PCAOCNO 0x99 SBUFO OxD9 PCAOMD Ox9A CMP1CNO OxDA 0x9B CMPOCNO OxDB PCAOCPM1 Ox9C CMP1MD OxDC 2 0 9 CMPOMD OxDD PCAOCPM3 Ox9E CMP1MX OxDE PCAOCPMA Ox9F CMPOMX OxDF P3SKIP OxA0 P2 OxEO ACC silabs com Smart Connected Energy friendly Rev 0 2 13 EFM8UB2 Reference Manual Special Function Registers Address SFR Page Address SFR Page bit addressable 0x00 0x0F bit addressable 0x00 0x0F OxA1 SPIOCFG OxE1 XBRO OxA2 SPIOCKR OxE2 XBR1 OxA3 SPIODAT OxE3 XBR2 OxA4 POMDOUT OxE4 ITO1CF CKCON1 OxA5 P1MDOUT 0 5 SMOD1 OxA6 P2MDOUT OxE6 EIE1 OxA7 P3MDOUT OxE7 EIE2 OxA8 IE OxE8 ADCOCNO OxA9 CLKSEL OxE9 PCAOCPL1 OxAA EMIOCN OxEA PCAOCPH1 OxAB OxEB PCAOCPL2 OxAC SBCON1 OxEC 2 OxAD OxED PCAOCPL3 OxAE PAMDOUT OxEE PCAOCPH3 OxAF PFEOCN OxEF RSTSRC OxBO P3 OxFO B 1 XOSCOCN OxF1 POMDIN 0 2 HFOOCN OxF2 P1MDIN 0xB3 HFOOCAL OxF3 P2MDIN 0 4 SBRLL1 OxF4 P3MDIN 0 5 SBRLH1 OxF5 P4MDIN 0 6 FLSCL OxF6 EIP1 0 7 FLKEY OxF7 EIP2 0xB8 IP OxF8 SPIOCNO 0 9 SMBTC OxF9 PCAOL OxBA AMXON OxFA OxBB AMXOP OxFB PCAOCPLO OxBC ADCOCF OxFC PCAOCPHO OxBD
148. Mode Bit 7 6 5 4 3 2 1 0 16 TOG PWM ECCF Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xDD Bit Name Reset Access Description 7 16 0 RW Channel 3 16 bit Pulse Width Modulation Enable This bit enables 16 bit mode when Pulse Width Modulation mode is enabled Value Name Description 0 8 BIT 8 bit PWM selected 1 16_BIT 16 bit PWM selected 6 ECOM 0 RW Channel 3 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel 3 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 3 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 3 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCF3 bit in the PCAOMD register to be set to logic 1 2 TOG 0 RW Channel 3 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX3 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 3 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is o
149. Must write reset value 4 0 RW PCA Module 4 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF4 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 3 CCF3 0 RW PCA Module 3 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF3 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 2 CCF2 0 RW PCA Module 2 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF2 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 1 CCF1 0 RW PCA Module 1 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF1 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by firmware 0 CCFO 0 RW PCA Module 0 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCFO interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routi
150. O 0 RW SMBus Stop Flag When reading STO a 1 indicates that a stop condition was detected on the bus in slave mode or is pending in master mode When acting as a master writing a 1 to the STO bit initiates a stop condition on the bus This bit is cleared by hardware 3 ACKRQ 0 R SMBus Acknowledge Request Value Name Description 0 NOT SET No ACK requested 1 REQUESTED ACK requested 2 ARBLOST 0 R SMBus Arbitration Lost Indicator Value Name Description 0 NOT_SET No arbitration error 1 ERROR Arbitration error occurred 1 ACK 0 RW SMBus Acknowledge When read as a master the ACK bit indicates whether an ACK 1 or NACK 0 is received during the most recent byte transfer As slave this bit should be written to send an ACK 1 or NACK 0 to a master request Note that the logic level of the ACK bit on the SMBus interface is inverted from the logic of the register ACK bit silabs com Smart Connected Energy friendly Rev 0 2 241 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 Reset Access Description Sl 0 RW SMBus Interrupt Flag This bit is set by hardware to indicate that the current SMBus state machine operation such as writing a data or address byte is complete and the hardware needs additional control from the firmware to proceed While SI is set SCL is held low and SMBus is stalled SI must be cleared by firmware Clearing SI initiates the next SMBus state
151. O OUT endpoint FIFO silabs com Smart Connected Energy friendly Rev 0 2 189 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 USBO Control Registers 16 4 1 USBOXCN USBO Transceiver Control Bit 7 6 5 2 1 0 SPEED PHYTST DFREC Dp Dn Access RW RW RW RW R R R Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xD7 Bit Name Reset Access Description 7 PREN 0 RW Internal Pull up Resistor Enable The location of the pull up resistor D or D is determined by the SPEED bit Value Name Description 0 PULL UP DISABLED Internal pull up resistor disabled device effectively detached from USB network 1 PULL_UP_ENABLED Internal pull up resistor enabled when VBUS is present device attached to the USB network 6 PHYEN 0 RW Physical Layer Enable Value Name Description 0 DISABLED Disable the USBO physical layer transceiver suspend 1 ENABLED Enable the USBO physical layer transceiver normal 5 SPEED 0 RW 05 0 Speed Select This bit selects the USBO speed Value Name Description 0 LOW_SPEED USBO operates as a Low Speed device If enabled the internal pull up resistor appears on the D line 1 FULL_SPEED USBO operates as a Full Speed device If enabled the internal pull up resistor ap pears on the D line 4 3 PHYTST 0x0 RW Physical Layer Test Value Name Description 0x0 MODEO Mode 0 Normal non test mode
152. OxC9 ALL Voltage Regulator Control RSTSRC OxEF ALL Reset Source SBCON1 OxAC ALL UART1 Baud Rate Generator Control SBRLH1 0 5 ALL UART1 Baud Rate Generator High Byte SBRLL1 0xB4 ALL UART1 Baud Rate Generator Low Byte SBUFO 0x99 ALL UARTO Serial Port Data Buffer SBUF1 OxD3 ALL UART1 Serial Port Data Buffer SCONO 0x98 ALL UARTO Serial Port Control SCON1 OxD2 ALL UART1 Serial Port Control SFRPAGE OxBF ALL SFR Page SMBOADM OxCE 0x00 SMBus 0 Slave Address Mask SMBOADR OxCF 0x00 SMBus 0 Slave Address SMBOCF OxC1 0x00 SMBus 0 Configuration SMBOCNO OxCO 0 00 SMBus 0 Control SMBODAT 0 2 0 00 SMBus 0 Data SMB1ADM OxCE OxOF SMBus 1 Slave Address Mask SMB1ADR OxCF OxOF SMBus 1 Slave Address SMB1CF OxC1 OxOF SMBus 1 Configuration SMB1CNO OxCO OxOF SMBus 1 Control SMB1DAT OxC2 OxOF SMBus 1 Data SMBTC 0 9 OxOF SMBus Timing and Pin Control SMOD1 OxE5 ALL UART1 Mode SP 0x81 ALL Stack Pointer SPIOCFG OxA1 ALL SPIO Configuration SPIOCKR OxA2 ALL SPIO Clock Rate SPIOCNO OxF8 ALL SPIO Control SPIODAT OxA3 ALL SPIO Data TCON 0x88 ALL Timer 0 1 Control THO 0 8 Timer 0 High Byte TH1 0x8D ALL Timer 1 High Byte TLO 0x8A ALL Timer 0 Low Byte TL1 0x8B ALL Timer 1 Low Byte silabs com Smart Connected Energy friendly Rev 0 2 17 EFM8UB2 Reference Manual Special Function Registers Register Address SFR Pages Descriptio
153. PRDY when a packet is ready in the OUT FIFO Note that if double buffering is enabled for the target endpoint it is possible for two packets to be ready in the OUT FIFO at a time In this case hardware will set OPRDY to 1 immediately after firmware unloads the first packet and resets OPRDY to 0 A second interrupt will be generated in this case Operating Endpoints 1 3 as OUT Isochronous Endpoints When the ISO bit is set to 1 the target endpoint operates in Isochronous ISO mode Once an endpoint has been configured for ISO OUT mode the host will send exactly one data per USB frame the location of the data packet within each frame may vary however Because of this it is recommended that double buffering be enabled for ISO OUT endpoints Each time a data packet is received hardware will load the received data packet into the endpoint FIFO set the OPRDY bit to 1 and generate an interrupt if enabled Firmware would typically use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to 0 If a data packet is received when there is no room in the endpoint FIFO an interrupt will be generated and the OVRUN bit set to 1 If USBO receives an ISO data packet with a CRC error the data packet will be loaded into the endpoint FIFO OPRDY will be set to 1 an interrupt if enabled will be generated and the DATAERR bit will be set to 1 Software should check the DATAERR bit each time a data packet is unloaded from an IS
154. PUSH_PULL P1 7 output is push pull 6 B6 0 RW Port 1 Bit 6 Output Mode See bit 7 description 5 5 0 RW Port 1 Bit 5 Output Mode See bit 7 description 4 B4 0 RW Port 1 Bit 4 Output Mode See bit 7 description 3 B3 0 RW Port 1 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 1 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 1 Bit 1 Output Mode See bit 7 description 0 BO 0 RW Port 1 Bit 0 Output Mode See bit 7 description silabs com Smart Connected Energy friendly Rev 0 2 95 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 11 P1SKIP Port 1 Skip Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address OxD5 Bit Name Reset Access Description 7 B7 0 RW Port 1 Bit 7 Skip Value Name Description 0 NOT_SKIPPED P1 7 pin is not skipped by the crossbar 1 SKIPPED P1 7 pin is skipped by the crossbar 6 B6 0 RW Port 1 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 1 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 1 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 1 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 1 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 1 Bit 1 Skip See bit 7 description 0 BO 0 RW Port 1 Bit 0 Skip See bit 7 description silabs com Smart Connected Energy friendly Rev 0 2 96
155. Priority 1 2 OxF7 ALL Extended Interrupt Priority 2 EMIOCF 0x85 ALL External Memory Configuration EMIOCN OxAA ALL External Memory Interface Control EMIOTC 0x84 ALL External Memory Timing Control FLKEY 0xB7 ALL Flash Lock and Key FLSCL 0 6 ALL Flash Scale HFOOCAL OxB3 ALL High Frequency Oscillator Calibration 0 2 ALL High Frequency Oscillator Control IE OxA8 ALL Interrupt Enable IP 0xB8 ALL Interrupt Priority ITO1CF OxE4 0 00 1 Configuration LFOOCN 0x86 ALL Low Frequency Oscillator Control PO 0x80 ALL Port 0 Pin Latch silabs com Smart Connected Energy friendly Rev 0 2 15 EFM8UB2 Reference Manual Special Function Registers Register Address SFR Pages Description POMDIN OxF 1 ALL Port 0 Input Mode POMDOUT OxA4 ALL Port 0 Output Mode POSKIP 0 04 ALL Port 0 Skip P1 0x90 ALL Port 1 Pin Latch P1MDIN OxF2 ALL Port 1 Input Mode P1MDOUT 0xA5 ALL Port 1 Output Mode P1SKIP OxD5 ALL Port 1 Skip P2 0 0 Port 2 Pin Latch P2MDIN OxF3 ALL Port 2 Input Mode P2MDOUT OxA6 ALL Port 2 Output Mode P2SKIP OxD6 ALL Port 2 Skip P3 0 0 ALL Port 3 Pin Latch P3MDIN OxF4 ALL Port 3 Input Mode P3MDOUT OxA7 ALL Port 3 Output Mode P3SKIP OxDF ALL Port 3 Skip P4 OxC7 ALL Port 4 Pin Latch P4MDIN OxF5 ALL Port 4 Input Mode P4MDOUT OxAE ALL Port 4 Output Mode
156. R and RD pulse width is 4 SYSCLK cycles 0 4 5 CLOCKS WR and RD pulse width is 5 SYSCLK cycles 0 5 6_CLOCKS WR and RD pulse width is 6 SYSCLK cycles 0 6 7_CLOCKS WR and RD pulse width is 7 SYSCLK cycles Ox7 8 CLOCKS AWR and RD pulse width is 8 SYSCLK cycles 0x8 9 CLOCKS AWR and RD pulse width is 9 SYSCLK cycles 0 9 10 CLOCKS WR RD pulse width is 10 SYSCLK cycles OxA 11 CLOCKS WR and RD pulse width is 11 SYSCLK cycles OxB 12 CLOCKS WR and RD pulse width is 12 SYSCLK cycles OxC 13 CLOCKS WR and RD pulse width is 13 SYSCLK cycles OxD 14 CLOCKS WR and RD pulse width is 14 SYSCLK cycles OxE 15 CLOCKS AWR and RD pulse width is 15 SYSCLK cycles OxF 16 CLOCKS AWR and RD pulse width is 16 SYSCLK cycles 1 0 AHOLD 0x3 RW EMIF Address Hold Time Value Name Description 0x0 0 CLOCKS Address hold time 0 SYSCLK cycles Ox1 1 CLOCK Address hold time 1 SYSCLK cycle 0 2 2 CLOCKS Address hold time 2 SYSCLK cycles silabs com Smart Connected Energy friendly Rev 0 2 178 EFM8UB2 Reference Manual External Memory Interface EMIFO Reset Access Description 0x3 3 CLOCKS Address hold time 3 SYSCLK cycles silabs com Smart Connected Energy friendly Rev 0 2 179 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 Universal Serial Bus USBO 16 1 Introduction The USBO module provides Full Low Speed function for USB peripheral implementations
157. RESINTE 1 Software may force a Remote Wakeup by writing 1 to the RESUME bit POWER 2 When forcing a Remote Wakeup software should write RESUME 0 to end Resume signaling 10 15 ms after the Remote Wakeup is initiated RESUME 1 ISO Update When software writes 1 to the ISOUP bit the isochronous update function is enabled With isochronous update enabled new packets written to an isochronous IN endpoint will not be transmitted until a new Start Of Frame SOF is received If the isochro nous IN endpoint receives IN token before a SOF the USB interface will transmit a zero length packet When ISOUP 1 isochro nous update is enabled for all isochronous endpoints USB Enable The USB module is disabled following a power on reset POR USB is enabled by clearing the USBINH bit Once written to 0 the USBINH can only be set to 1 by a POR or an asynchronous USB reset generated by writing 1 to the USBRST bit Software should perform all USB configuration before enabling the USB module The configuration sequence should be performed as follows 1 Select and enable the USB clock source 2 Reset the USB block by writing USBRST 1 3 Configure and enable the USB Transceiver 4 Perform any USB function configuration interrupts Suspend detect power mode configuration 5 Enable USB by writing USBINH 0 16 3 9 Interrupts The read only USB interrupt flags are located in the USB registers shown in INTINT OUT1INT and CMINT Th
158. RW ADC Enable Value Name Description 0 DISABLED ADCO Disabled low power shutdown 1 ENABLED ADCO Enabled active and ready for data conversions 6 ADTM 0 RW Track Mode Selects between Normal or Delayed Tracking Modes Value Name Description 0 TRACK_NORMAL Normal Track Mode When ADCO is enabled conversion begins immediately fol lowing the start of conversion signal 1 TRACK DELAYED Delayed Track Mode When ADCO is enabled conversion begins 3 SAR clock cy cles following the start of conversion signal The ADC is allowed to track during this time Note that there is not a tracking delay when the external conversion start CNVSTR is used as the start of conversion source 5 ADINT 0 RW Conversion Complete Interrupt Flag Set by hardware upon completion of a data conversion 0 or a burst of conversions ADBMEN 1 Can trigger an interrupt Must be cleared by firmware 4 ADBUSY 0 RW ADC Busy Writing 1 to this bit initiates an ADC conversion when ADCM 000 This bit should not be polled to indicate when a conver sion is complete Instead the ADINT bit should be used when polling for conversion completion 3 ADWINT 0 RW Set by hardware when the contents of ADCOH ADCOL fall within the window specified by ADCOGTH ADCOGTL and ADCOLTH ADCOLTL Can trigger an interrupt Must be cleared by firmware Window Compare Interrupt Flag 2 0 ADCM 0x0 RW Start of Conversion Mode Select Specifies
159. Rev 0 2 222 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO 17 4 3 SPIOCKR SPIO Clock Rate Bit 7 6 5 4 3 2 1 0 SPIOCKR Access RW Reset 0x00 SFR Page ALL SFR Address 2 Bit Reset Access Description 7 0 SPIOCKR 0x00 RW SPIO Clock Rate These bits determine the frequency of the SCK output when the SPIO module is configured for master mode operation The SCK clock frequency is a divided version of the system clock and is given in the following equation where SYSCLK is the system clock frequency and SPIOCKR is the 8 bit value held in the SPIOCKR register fsck SYSCLK 2 SPIOCKR 1 for 0 lt SPIOCKR lt 255 17 4 4 SPIODAT SPIO Data Bit 7 6 5 4 3 2 1 0 SPIODAT Access RW Reset Varies SFR Page ALL SFR Address 0xA3 Bit Name Reset Access Description 7 0 SPIODAT Varies RW SPIO Transmit and Receive Data The SPIODAT register is used to transmit and receive SPIO data Writing data to SPIODAT places the data into the transmit buffer and initiates a transfer when in master mode A read of SPIODAT returns the contents of the receive buffer silabs com Smart Connected Energy friendly Rev 0 2 223 EFM8UB2 Reference Manual System Management Bus I2C SMBO and SMB1 18 System Management Bus I2C 5 0 and SMB1 18 1 Introduction The SMBus I O interface is a two wire bi direction
160. SB SOF CAPTURE Capture source is USB SOF event 1 LFOSC CAPTURE Capture source is falling edge of Low Frequency Oscillator 0 T2XCLK 0 RW Timer 2 External Clock Select T2XCLK selects the external clock source for Timer 2 If Timer 2 is in 8 bit mode T2XCLK selects the external oscillator clock source for both timer bytes However the Timer 2 Clock Select bits T2MH and T2ML may still be used to select between the external clock and the system clock for either timer Value Name Description 0 SYSCLK DIV 12 Timer 2 clock is the system clock divided by 12 silabs com Smart Connected Energy friendly Rev 0 2 266 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 Reset Access Description 1 EXTOSC_DIV_8 Timer 2 clock is the external oscillator divided by 8 synchronized with SYSCLK 19 4 10 TMR2RLL Timer 2 Reload Low Byte Bit 7 6 4 3 2 1 0 TMR2RLL Access RW Reset 0x00 SFR Page 0x0 SFR Address Bit Name Reset Access 7 0 TMR2RLL 0x00 RW When operating in one of the auto reload modes TMR2RLL holds the reload value for the low byte of Timer 2 TMR2L When operating in capture mode TMR2RLL is the captured value of TMR2L Description Timer 2 Reload Low Byte 19 4 11 TMR2RLH Timer 2 Reload High Byte Bit 7 6 4 3 2 1 0 TMR2RLH Access RW Reset 0x00 SFR Page 0x0
161. SFR Page 0x0 SFR Address 0x92 Bit 7 0 Name Reset TMR3RLL 0x00 Access RW Description Timer 3 Reload Low Byte When operating one of the auto reload modes TMR3RLL holds the reload value for the low byte of Timer 3 TMR3L When operating in capture mode TMR3RLL is the captured value of TMR3L 19 4 16 TMR3RLH Timer 3 Reload High Byte Bit 7 6 4 0 TMR3RLH Access RW Reset 0x00 SFR Page 0x0 SFR Address 0x93 Bit 7 0 Name Reset TMR3RLH 0x00 Access RW Description Timer 3 Reload High Byte When operating in one of the auto reload modes TMR3RLH holds the reload value for the high byte of Timer 3 TMR3H When operating in capture mode TMR3RLH is the captured value of TMR3H 19 4 17 TMR3L Timer 3 Low Byte Bit 7 6 4 0 TMR3L Access RW Reset 0x00 SFR Page 0x0 SFR Address 0x94 Bit Name Reset Access Description 7 0 TMR3L 0x00 RW Timer 3 Low Byte In 16 bit mode the TMR3L register contains the low byte of the 16 bit Timer 3 In 8 bit mode TMR3L contains the 8 bit low byte timer value silabs com Smart Connected Energy friendly Rev 0 2 270 EFM8UB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 18 TMR3H Timer 3 High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page 0x0 SFR Address
162. SILICON LABS EFM8 Universal Bee Family EFM8UB2 Reference Manual The EFM8UB2 part of the Universal Bee family of MCUs is a multi purpose line of 8 bit microcontrollers with USB feature set These devices offer high value by integrating a USB peripheral interface with a high pre cision oscillator clock recovery circuit and integrated transceiver making them ideal for any full speed USB applications with no external components required With an efficient 8051 core and precision analog the EFM8UB2 family is also optimal for embedded ap plications EFM8UB2 applications include the following USB I O controls dongles Consumer electronics High speed communication bridge Medical equipment Core Memory Clock Management Energy Management CIP 51 8051 Core 48 MHz Power On Reset Memory Debug Interface up to 64 KB mns 5 V to 3 3 V LDO Regulator E Serial Interfaces I O Ports Timers and Triggers Analog Interfaces Lowest power mode with peripheral operational Normal Idle Suspend El Shutdown EFM8UB2 Reference Manual System Overview 1 System Overview 1 1 Introduction C2D X Port I O Configuration Debug Programming Hardware zu C2CK RSTb X Digital Peripherals ea vu EN ue CIP 51 8051 Controller UT Power On Core Reset Timers 0 1 64 32 KB ISP Flash 2 3 4 5 Priority Brivors DX P1 n
163. SMB1 Hardware Slave Address Recognition The SMBus hardware has the capability to automatically recognize incoming slave addresses and send an ACK without software inter vention Automatic slave address recognition is enabled by setting the EHACK bit in register SMBOADM to 1 This will enable both auto matic slave address recognition and automatic hardware ACK generation for received bytes as a master or slave The registers used to define which address es are recognized by the hardware are the SMBus Slave Address register and the SMBus Slave Address Mask register A single address or range of addresses including the General Call Address 0x00 can be specified using these two registers The most significant seven bits of the two registers are used to define which addresses will be ACKed A 1 in a bit of the slave address mask SLVM enables a comparison between the received slave address and the hardware s slave address SLV for that bit A 0 in a bit of the slave address mask means that bit will be treated as a don t care for comparison purposes In this case either 1 or a 0 value are acceptable on the incoming slave address Additionally if the GC bit in register SMBOADR is set to 1 hard ware will recognize the General Call Address 0x00 Table 18 3 Hardware Address Recognition Examples EHACK 1 Hardware Slave Address Slave Address Mask Slave Addresses Recognized by Hardware SLV SLVM 0x34 Ox7F 0
164. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information specifications and descriptions herein and does not give warranties as to the accuracy or completeness of the included information Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Trademark Information Silicon Laboratories Inc Silicon Laboratories Silicon Labs SiLabs and the Silicon Labs logo CMEMS EFM EFM32 EFR Energy Micro Energy Micro logo and combinations thereof the world s most energy friendly microcontrollers Ember amp EZLink EZMac EZRadio amp EZRadioPRO DSPLL ISOmodem 6 Precision32 ProSLIC SiPHY USBXpre
165. Smart Connected Energy friendly Rev 0 2 174 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 4 EMIFO Control Registers 15 4 1 EMIOCN External Memory Interface Control Bit 7 6 5 4 3 2 1 0 PGSEL Access RW Reset 0x00 SFR Page ALL SFR Address OxAA Bit Name Reset Access Description 7 0 PGSEL 0x00 RW XRAM Page Select The XRAM Page Select field provides the high byte of the 16 bit external data memory address when using an 8 bit MOVX effectively selecting a 256 byte page of RAM 0x00 0x0000 to OxOOFF 0x01 0x0100 to 0x01FF OxFE OxFEO0 to OxFEFF OxFF OxFFOO to OxFFFF silabs com Smart Connected Energy friendly Rev 0 2 175 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 4 2 EMIOCF External Memory Configuration Bit 7 6 5 4 1 Name Reserved USBFAE Reserved MUXMD EMD EALE Access RW RW RW RW RW RW Reset 0 0 0 0 0x0 0x3 SFR Page ALL SFR Address 0x85 Bit Name Reset Access Description 7 Reserved Must write reset value 6 USBFAE 0 RW USB FIFO Access Enable Value Name Description 0 FIFO ACCESS DISA USB FIFO RAM not available through MOVX instructions BLED 1 FIFO ACCESS ENA USB FIFO RAM available using MOVX instructions The 1 KB of USB RAM will BLED be mapped in XRAM space at addresses 0x0400 to 0x07FF The USB clock must be active
166. T token is received while EndpointO is in Transmit Mode EndpointO will remain in Transmit Mode until any of the following occur The USB interface receives an EndpointO SETUP or OUT token Firmware sends a packet less than the maximum EndpointO packet size Firmware sends a zero length packet Firmware should set the DATAEND bit to 1 when sending a zero length packet or sending a packet less than the maximum EndpointO size The SIE will transmit a in response to an IN token if there is no packet ready in the IN FIFO INPRDY 0 silabs com Smart Connected Energy friendly Rev 0 2 187 EFM8UB2 Reference Manual Universal Serial Bus USBO Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USBO one or more OUT requests will be sent by the host When an OUT packet is successfully received by USBO hardware will set the OPRDY bit to 1 and generate an EndpointO interrupt Following this interrupt firmware should unload the OUT packet from the EndpointO FIFO and set the SOPRDY bit to 1 If the amount of data required for the transfer exceeds the maximum packet size for EndpointO the data will be split into multiple pack ets If the requested data is an integer multiple of the maximum packet size for EndpointO as reported to the host the host will send a zero length data packet signaling the end of the transfer Upon reception of the first OUT token for a particular
167. T1 is used with Timer 1 and IN1PL in register ITO1CF determines the INT1 state that starts Timer 1 counting silabs com Smart Connected Energy friendly Rev 0 2 250 EFM8UB2 Reference Manual Timers TimerO Timer1 2 Timer3 Timer4 and Timer5 Pre scaled Clock SYSCLK TLO THO Interrupt Flag Figure 19 1 TO Mode 0 Block Diagram Mode 1 16 bit Counter Timer Mode 1 operation is the same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and configured in Mode 1 in the same manner as for Mode 0 The overflow rate for Timer 0 in 16 bit mode is F F input Clock _ F input Clock TIMERO 216 THO TLO 7 65536 THO TLO silabs com Smart Connected Energy friendly Rev 0 2 251 EFM8UB2 Reference Manual Timers TimerO Timer1 2 Timer3 Timer4 and Timer5 Mode 2 8 bit Counter Timer with Auto Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8 bit counter timers with automatic reload of the start value TLO holds the count and THO holds the reload value When the counter in TLO overflows from all ones to 0x00 the timer overflow flag TFO in the TCON register is set and the counter TLO is reloaded from THO If Timer 0 interrupts are enabled an interrupt will occur when the TFO flag is set The reload value in THO is not changed TLO must be initialized to the desired value before enabling the timer for the first coun
168. The USB function controller USBO consists of a Serial Interface Engine SIE USB transceiver including matching resistors and configurable pull up resistors 1 KB FIFO block and clock recovery mechanism for crystal less operation No external components are required The USBO module is Universal Serial Bus Specification 2 0 compliant USBn Module 4 Clock Recovery Serial Interface Engine SIE Internal USBn Oscillator Data Transfer Endpoint 0 Control EN USB FIFO USBn EP1 Endpoint space in External RAM USBn EP2 Endpoint USBn EP3 Endpoint Figure 16 1 USB Block Diagram 16 2 Features The USBO module includes the following features Full and Low Speed functionality Implements 4 bidirectional endpoints USB 2 0 compliant USB peripheral support no host capability Direct module access to 1 KB of RAM for FIFO memory Clock recovery to meet USB clocking requirements with no external components silabs com Smart Connected Energy friendly Rev 0 2 180 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 3 Functional Description 16 3 1 Endpoint Addressing A total of eight endpoint pipes are available The control endpoint EndpointO always functions as a bi directional IN OUT endpoint The other endpoints are implemented as three pairs of IN OUT endpoint pipes Table 16 1 Endpoint Addressing Scheme Endpoint Associated Pipes USB Protocol
169. USBO 16 4 19 CMIE USBO Common Interrupt Enable Bit 7 6 5 3 2 1 0 Reserved SOFE RSTINTE RSUINTE SUSINTE Access R RW RW RW RW Reset 0x0 0 1 1 0 Indirect Address 0 0 Bit Name Reset Access 7 4 Reserved Must write reset value 3 SOFE 0 RW Start of Frame Interrupt Enable Value Name 0 DISABLED Disable SOF interrupts 1 ENABLED Enable SOF interrupts 2 RSTINTE 1 RW Reset Interrupt Enable Value Name 0 DISABLED Disable reset interrupts 1 ENABLED Enable reset interrupts 1 RSUINTE 1 RW Resume Interrupt Enable Value Name 0 DISABLED Disable resume interrupts 1 ENABLED Enable resume interrupts 0 SUSINTE 0 RW Suspend Interrupt Enable Value Name 0 DISABLED Disable suspend interrupts 1 ENABLED Enable suspend interrupts This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 203 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 20 EOCSR USBO Endpoint0 Control Bit Name 7 SSUEND 6 SOPRDY SDSTL SUEND 3 DATAEND STSTL 1 INPRDY OPRDY Access RW RW RW RW RW RW Reset 0 0 0 0 Indirect Address 0x11 Bit 7 Name Reset Access Description SSUEND 0 RW Serviced Setup End Firmware should set this bit to 1 after servicing a setup
170. W R RW RW R RW RW R Reset Varies Varies Varies Varies Varies Varies Varies Varies SFR Page ALL SFR Address OxEF Bit Name Reset Access Description 7 USBRSF Varies RW USB Reset Enable and Flag Read This bit reads 1 if USB caused the last reset Write Writing a 1 to this bit enables the USBO module as a reset source 6 FERROR Varies R Flash Error Reset Flag This read only bit is set to 1 if a flash read write erase error caused the last reset 5 CORSEF Varies RW Comparator0 Reset Enable and Flag Read This bit reads 1 if Comparator 0 caused the last reset Write Writing a 1 to this bit enables Comparator 0 active low as a reset source 4 SWRSF Varies RW Software Reset Force and Flag Read This bit reads 1 if last reset was caused by a write to SWRSF Write Writing a 1 to this bit forces a system reset 3 WDTRSF Varies R Watchdog Timer Reset Flag This read only bit is set to 1 if a watchdog timer overflow caused the last reset 2 MCDRSF Varies RW Missing Clock Detector Enable and Flag Read This bit reads 1 if a missing clock detector timeout caused the last reset Write Writing a 1 to this bit enables the missing clock detector The MCD triggers a reset if a missing clock condition is detected 1 PORSF Varies RW Power On Supply Monitor Reset Flag and Supply Monitor Reset Enable Read This bit reads 1 anytime a power on or supply monitor reset has occurred Write Writing a 1 to this bit enables the supply monitor as a reset sourc
171. W SPIO Clock Polarity Value Name Description 0 IDLE_LOW SCK line low in idle state 1 IDLE_HIGH SCK line high in idle state 3 SLVSEL 0 R Slave Selected Flag This bit is set to logic 1 whenever the NSS pin is low indicating SPIO is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched ver sion of the pin input 2 NSSIN 1 R NSS Instantaneous Pin Input This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched SRMT 1 R Shift Register Empty This bit will be set to logic 1 when all data has been transferred in out of the shift register and there is no new information available to read from the transmit buffer or write to the receive buffer It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK silabs com Smart Connected Energy friendly Rev 0 2 220 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO Bit Name Reset Access Description 0 RXBMT 1 R Receive Buffer Empty This bit is valid in slave mode only and will be set to logic 1 when the receive buffer has been read and contains no new information If there is new information available in the receive buffer that has not been read this bit will return to logic 0 RXBMT
172. _DIV_12 System clock divided by 12 0 1 SYSCLK_DIV_4 System clock divided by 4 0x2 TO OVERFLOW Timer 0 overflow 0x3 High to low transitions max rate system clock divided by 4 0 4 SYSCLK System clock 0 5 EXTOSC_DIV_8 External clock divided by 8 synchronized with the system clock 0 ECF 0 RW PCA Counter Timer Overflow Interrupt Enable silabs com Smart Connected Energy friendly This bit sets the masking of the PCA Counter Timer Overflow CF interrupt Rev 0 2 149 EFM8UB2 Reference Manual Programmable Counter Array PCAO Bit Name Reset Access Description Value Name Description 0 OVF INT DISABLED Disable the CF interrupt 1 OVF INT ENABLED Enable a PCA Counter Timer Overflow interrupt request when CF is set When the WDTE bit is set to 1 the other bits in the PCAOMD register cannot be modified To change the contents of the PCAOMD register the Watchdog Timer must first be disabled 14 4 3 PCAOL PCA Counter Timer Low Byte Bit 7 6 5 4 3 2 1 0 PCAOL Access RW Reset 0x00 SFR Page ALL SFR Address OxF9 Bit Name Reset Access Description 7 0 PCAOL 0x00 RW PCA Counter Timer Low Byte The PCAOL register holds the low byte LSB of the 16 bit PCA Counter Timer When the WDTE bit is set to 1 the PCAOL register cannot be modified by firmware To change the contents of the PCAOL register the Watchdog Timer must first be disabled
173. a tion should be erased before writing data Value Name Description 0 WRITE DISABLED Writes to flash program memory disabled 1 WRITE ENABLED Writes to flash program memory enabled the MOVX write instruction targets flash memory silabs com Smart Connected Energy friendly Rev 0 2 25 EFM8UB2 Reference Manual Flash Memory 4 4 2 FLKEY Flash Lock and Key Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address 0xB7 Bit Name Reset Access Description 7 0 FLKEY 0x00 RW Flash Lock and Key Write This register provides a lock and key function for flash erasures and writes Flash writes and erases are enabled by writing OxA5 followed OxF1 to the FLKEY register Flash writes and erases are automatically disabled after the next write or erase is complete If any writes to FLKEY are performed incorrectly or if a flash write or erase operation is attempted while these operations are disabled the flash will be permanently locked from writes or erasures until the next device reset If an application never writes to flash it can intentionally lock the flash by writing a non 0xA5 value to FLKEY from firmware Read When read bits 1 0 indicate the current flash lock state 00 Flash is write erase locked 01 The first key code has been written 0xA5 10 Flash is unlocked writes erases allowed 11 Flash writes erases are disabled until the next
174. a AD 7 0 m Figure 15 6 Multiplexed 16 bit MOVX Timing silabs com Smart Connected Energy friendly Rev 0 2 169 EFM8UB2 Reference Manual External Memory Interface EMIFO Muxed 8 bit Write Without Bank Select A 15 8 m Port Latch Controlled GPIO A 15 8 m AD 7 0 m EMIF Address 8 LSBs from RO or R1 EMIF Write Data AD 7 0 m RDb RDb Muxed 8 bit Read Without Bank Select A 15 8 m Port Latch Controlled GPIO A 15 8 m AD 7 0 m EMIF Address 8 LSBs from RO orR1 EMIF Read Data i AD 7 0 m WRb WRb Figure 15 7 Multiplexed 8 bit MOVX without Bank Select Timing silabs com Smart Connected Energy friendly Rev 0 2 170 EFM8UB2 Reference Manual External Memory Interface EMIFO Muxed 8 bit Write with Bank Select A 15 8 m EMIF Address 8 MSBs from EMIOCN A 15 8 m AD 7 0 m EMIF Address 8 LSBs from RO or R1 EMIF Write Data i AD 7 0 m Muxed 8 bit Read with Bank Select A 15 8 m EMIF Address 8 MSBs from EMIOCN A 15 8 m AD 7 0 m EMIF Address 8 LSBs from RO or R1 EMIF Read Data j AD 7 0 m WRb i WRb Figure 15 8 Multiplexed 8 bit MOVX with Bank Select Timing silabs com Smart Connected Energy friendly Rev 0 2 171 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 3 6 2 Non Multiplexed Mode Figure 15 9 Non Multiplexed 16 bit MOVX Timing on page 172 through Figure 15
175. able 11 Address Bit 11 P3 3 Not Available Not Available 12 Address Bit 12 P3 4 Not Available Not Available 13 Address Bit 13 P3 5 Not Available Not Available A14m Address Bit 14 P3 6 Not Available Not Available A15m Address Bit 15 P3 7 Not Available Not Available Table 15 2 Non Multiplexed EMIF Pin Mapping Non Multiplexed EMIF Description QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name Signal Name WRb Write Enable P1 7 Not Available Not Available RDb Read Enable P1 6 Not Available Not Available DO Data Bit 0 4 0 Not Available Not Available D1 Data Bit 1 P4 1 Not Available Not Available D2 Data Bit 2 P4 2 Not Available Not Available D3 Data Bit 3 P4 3 Not Available Not Available D4 Data Bit 4 P4 4 Not Available Not Available D5 Data Bit 5 P4 5 Not Available Not Available D6 Data Bit 6 P4 6 Not Available Not Available D7 Data Bit 7 P4 7 Not Available Not Available AO Address Bit 0 P3 0 Not Available Not Available A1 Address Bit 1 P3 1 Not Available Not Available A2 Address Bit 2 P3 2 Not Available Not Available A3 Address Bit 3 P3 3 Not Available Not Available A4 Address Bit 4 P3 4 Not Available Not Available A5 Address Bit 5 P3 5 Not Available Not Available A6 Address Bit 6 P3 6 Not Available Not Available Address Bit 7 P3 7 Not Available Not Available 8 Address Bit 8 P2 0 Not Available Not Available 9 Address Bit 9 P2 1 Not Available Not
176. al the 13 pF capacitors yield an equivalent capacitance of 12 5 pF across the crystal 15 pF XTAL1 25 MHz II P XTAL2 15 pF Figure 8 4 25 MHz External Crystal Example Crystal oscillator circuits are quite sensitive to PCB layout The crystal should be placed as close as possible to the XTAL pins on the device The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference When using an external crystal the external oscillator drive circuit must be configured by firmware for Crystal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage The divide by 2 stage ensures that the clock derived from the external oscillator has a duty cycle of 5096 The External Oscillator Frequency Control value XFCN must also be specified based on the crystal frequen For example 25 MHz crystal requires an XFCN setting of 111b silabs com Smart Connected Energy friendly Rev 0 2 51 EFM8UB2 Reference Manual Clocking and Oscillators Table 8 1 Recommended XFCN Settings for Crystal Mode XFCN Field Setting Crystal Frequency Approximate Bias Current 000 f lt 20 kHz 0 5 uA 001 20 kHz lt f lt 58 kHz 1 5 pA 010 58 kHz lt f lt 155 kHz 4 8 yA 011 155 kHz f 415 kHz 14 pA 100 415 kHz lt f lt 1 1 MHz 40 pA 101 1 1 MHz f 3 1 MHz 120 pA 110 3 1 MHz f lt 8 2 MHz 550 pA 111 8 2 MHz f lt 25 MHz 2 6
177. al serial bus The SMBus is compliant with the System Management Bus Specifica tion version 1 1 and compatible with the 12C serial bus Data SMBODAT Shift Register SDA State Control Slave Address SCL Logic Recognition Timers 0 Master SCL Clock 1or2 Generation Timer 3 Figure 18 1 SMBus 0 Block Diagram 18 2 Features The SMBus modules include the following features Standard up to 100 kbps and Fast 400 kbps transfer speeds Support for master slave and multi master modes Hardware synchronization and arbitration for multi master mode Clock low extending clock stretching to interface with faster masters Hardware support for 7 bit slave and general call address recognition Firmware support for 10 bit slave address decoding Ability to inhibit all slave states Programmable data setup hold times 18 3 Functional Description 18 3 1 Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I2C Bus and How to Use It including specifications Philips Semiconductor The 12 Specification Version 2 0 Philips Semiconductor System Management Bus Specification Version 1 1 SBS Implementers Forum silabs com Smart Connected Energy friendly Rev 0 2 224 EFM8UB2 Reference Manual System Management Bus I2C SMBO and SMB1 18 3 2 SMBus Protocol The SMBus specification allows any recessive voltage between 3 0 and 5 0 V d
178. all of the potential peripheral to pin assignments available to the crossbar Note that this does not mean any peripheral can always be assigned to the highlighted pins The actual pin assignments are determined by the priority of the enabled peripherals EG EE EN secu ee Pin Number BEBBDSIOMU 4 6 1 2 314 5 6 7 112 3 415 6 7 UARTO TX UARTO RX SPIO SCK SPIO MISO SPIO MOSI SPIO NSS SMBO SDA SMBO SCL 1 1 CMP1 CP1A SYSCLK PCAO CEX1 PCAO0 CEX2 PCAO0 CEX3 PCAO0 CEX4 PCAO ECI 0 0 Pins Not Available on Crossbar Timer1 T1 UART1 TX UART1 RX SMB1 SDA E SMB1 SCL Pin Skip Settings POSKIP 15 25 P3SKIP The crossbar peripherals are assigned in priority order from top to bottom Bl These boxes represent Port pins which can potentially be assigned to a peripheral Special Function Signals are not assigned by the crossbar When these signals are enabled the Crossbar should be manually configured to skip the corresponding port pins E Pins can be skipped by setting the corresponding bit in PnSKIP to 1 NSS is only pinned out when the SPI is in 4 wire mode
179. alue 1 PS1 0 RW UART1 Interrupt Priority Control This bit sets the priority of the UART1 interrupt Value Name Description 0 LOW UARTI interrupt set to low priority level 1 HIGH UARTI interrupt set to high priority level 0 PVBUS 0 RW VBUS Level Interrupt Priority Control This bit sets the priority of the VBUS interrupt Value Name Description 0 LOW VBUS interrupt set to low priority level 1 HIGH VBUS interrupt set to high priority level silabs com Smart Connected Energy friendly Rev 0 2 41 EFM8UB2 Reference Manual Power Management and Internal Regulators 7 Power Management and Internal Regulators 7 1 Introduction All internal circuitry draws power from the VDD supply pin External I O pins are powered from the VIO supply voltage or VDD on devi ces without a separate VIO connection while most of the internal circuitry is supplied by an on chip LDO regulator Control over the device power can be achieved by enabling disabling individual peripherals as needed Each analog peripheral can be disabled when not in use and placed in low power mode Digital peripherals such as timers and serial buses have their clocks gated off and draw little power when they are not in use Power Distribution VREGIN PK X D USB PHY VDD X 7 10 GND X CPU Core XJ Digital I O Interface Port I O Pins Peripheral Logic Figure 7 1 Power System Block Diagram Tabl
180. alue Name Description 0 EXTERNAL_CLOCK Timer 3 low byte uses the clock defined by T3XCLK in TMR3CNO 1 SYSCLK Timer 3 low byte uses the system clock 5 T2MH 0 RW Timer 2 High Byte Clock Select Selects the clock supplied to the Timer 2 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 2 high byte uses the clock defined by T2XCLK in TMR2CNO 1 SYSCLK Timer 2 high byte uses the system clock 4 T2ML 0 RW Timer 2 Low Byte Clock Select Selects the clock supplied to Timer 2 If Timer 2 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer Value Name Description 0 EXTERNAL_CLOCK Timer 2 low byte uses the clock defined by T2XCLK in TMR2CNO 1 SYSCLK Timer 2 low byte uses the system clock 3 T1M 0 RW Timer 1 Clock Select Selects the clock source supplied to Timer 1 Ignored when C T1 is set to 1 Value Name Description 0 PRESCALE Timer 1 uses the clock defined by the prescale field SCA 1 SYSCLK Timer 1 uses the system clock silabs com Smart Connected Energy friendly Rev 0 2 258 EFM8UB2 Reference Manual Timers TimerO 1 2 Timer3 Timer4 and Timer5 Bit Name Reset Access Description 2 TOM 0 RW Timer 0 Clock Select Selects the clock source supplied to Timer 0 Ignored when C TO is set to 1 Value Name Description 0 PRESCALE Counter Timer 0 uses the clock
181. am Timer 1 should be configured for 8 bit auto reload mode mode 2 The Timer 1 reload value and prescaler should be set so that over flows occur at twice the desired UARTO baud rate The UARTO baud rate is half of the Timer 1 overflow rate Configuring the Timer 1 overflow rate is discussed in the timer sections 20 3 2 Data Format UARTO has two options for data formatting All data transfers begin with a start bit logic low followed by the data sent LSB first and end with a stop bit logic high The data length of the UARTO module is normally 8 bits An extra 9th bit may be added to the MSB of data field for use in multi processor communications or for implementing parity checks on the data The SOMODE bit in the SCON reg ister selects between 8 or 9 bit data transfers MARK START BIT DO D1 D2 D3 D4 D5 D6 D7 STOP SPACE BIT BIT TIMES Ff A A A A A A A A A A BIT SAMPLING Figure 20 3 8 Bit Data Transfer STOP MARK START DO x D1 02 D3 D4 Y D5 Y D6 07 Y D8 BIT BIT SPACE y y y 7 m BIT SAMPLING Figure 20 4 9 Bit Data Transfer Rev 0 2 279 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 3 3 Data Transfer UARTO provides standar
182. ample if the entire address space is consecutively written and the data pointer is incremented after each write the write pointer will always point to the first byte of on chip XRAM after the last byte of on chip XRAM has been written 8 bit MOVX operations use the contents of EMIOCN to determine the high byte of the effective address and RO or R1 to determine the low byte of the effective address 16 bit MOVX operations use the contents of the 16 bit DPTR to determine the effective address Split Mode without Bank Select In Split Mode without Bank Select the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the on chip XRAM boundary will access on chip XRAM space Effective addresses above the on chip XRAM boundary will access off chip space 8 bit MOVX operations use the contents of EMIOCN to determine whether the memory access is onchip or off chip However in the No Bank Select mode an 8 bit MOVX operation will not drive the upper bits A 15 8 of the Address Bus during an off chip access This allows firmware to manipulate the upper address bits at will by setting the port state directly via the port latches This behavior is in contrast with Split Mode with Bank Select The lower 8 bits of the Address Bus A 7 0 are driven determined by RO or R1 16 bit MOVX operations use the contents of DPTR to determine whether the memory access is onchip or off chip and unlike 8 bit MOVX
183. and falling edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed before enabling comparator interrupts silabs com Smart Connected Energy friendly Rev 0 2 130 EFM8UB2 Reference Manual Comparators and 1 13 4 CMPO Control Registers 13 4 1 CMPOCNO Comparator 0 Control 0 Bit 7 6 4 1 Name CPEN CPOUT CPRIF CPFIF CPHYP CPHYN Access RW R RW RW RW RW Reset 0 0 0 0x0 0x0 SFR Page ALL SFR Address 0 9 Bit Name Reset Access Description 7 CPEN 0 RW Comparator Enable Value Name Description 0 DISABLED Comparator disabled 1 ENABLED Comparator enabled 6 CPOUT 0 R Comparator Output State Flag Value Name Description 0 5 1 55 Voltage on CPOP lt 1 5 Voltage gt ER THAN NEG 5 CPRIF 0 RW Comparator Rising Edge Flag Must be cleared by firmware Value Name Description 0 NOT SET No comparator rising edge has occurred since this flag was last cleared 1 RISING EDGE Comparator rising edge has occurred 4 CPFIF 0 RW Comparator Falling Edge Flag Must be cleared by firmware Value Name Description 0 NOT SET No comparator falling edge has occurred since this flag was last cleared 1 FALLING EDGE Comparator falling edge has occurred 3 2 CPHYP 0 0 RW Comparator Positive Hysteresis Control
184. and greater than or equal to twice the SYSCLK USBCLK 2 x SYSCLK to access this area with MOVX instructions 5 Reserved Must write reset value 4 MUXMD 0 RW EMIF Multiplex Mode Select Value Name Description 0 MULTIPLEXED EMIF operates in multiplexed address data mode 1 NON MULTIPLEXED EMIF operates in non multiplexed mode separate address and data pins 3 2 EMD 0x0 RW EMIF Operating Mode Select Value Name Description 0x0 INTERNAL ONLY Internal Only MOVX accesses on chip XRAM only All effective addresses alias to on chip memory space Ox1 SPLIT WITH Split Mode without Bank Select Accesses below the internal XRAM boundary are OUT BANK SELECT directed on chip Accesses above the internal XRAM boundary are directed off chip 8 bit off chip MOVX operations use the current contents of the Address high port latches to resolve the upper address byte To access off chip space EMIOCN must be set to a page that is not contained in the on chip address space 0x2 SPLIT WITH BANK S Split Mode with Bank Select Accesses below the internal XRAM boundary are di ELECT rected on chip Accesses above the internal XRAM boundary are directed off chip 8 bit off chip MOVX operations uses the contents of EMIOCN to determine the high byte of the address 0x3 EXTERNAL_ONLY External Only MOVX accesses off chip XRAM only On chip XRAM is not visible to the core 1 0 EALE 0x3 RW ALE Pulse Width Select These bits only have an effect when the EMIF is in multiplex
185. any devices with a slave parallel memory interface such as SRAM chips only support a non multiplexed memory bus When interfac ing to such a device an external latch 74HC373 or equivalent logic gate can be used to hold the lower 8 bits of the RAM address during the second half of the memory cycle when the address data bus contains data The external latch controlled by the ALEm Ad dress Latch Enable signal is automatically driven by the External Memory Interface logic An example SRAM interface showing multi plexed to non multiplexed conversion is shown in below This example is showing that the external MOVX operation can be broken into two phases delineated by the state of the ALEm signal During the first phase ALEm is high and the lower 8 bits of the Address Bus are presented to AD 7 0 m During this phase the address latch is configured such that the Q outputs reflect the states of the D inputs When ALEm falls signaling the beginning of the second phase the address latch outputs remain fixed and are no longer dependent on the latch inputs Later in the second phase the Data Bus controls the state of the AD 7 0 m port at the time RDb or WRb is asserted silabs com Smart Connected Energy friendly Rev 0 2 165 EFM8UB2 Reference Manual External Memory Interface EMIFO A 15 8 m Address Bus ALEm AD 7 0 m Address Data Bus Figure 15 3 Multiplexed to Non Multiplexed Configuration Example 15 3 4 Non Multiplexed E
186. ardware When MASTER A START is generated A STOP is generated Arbitration is lost TXMODE START is generated A START is detected SMBODAT is written before the start of an Arbitration is lost SMBus frame SMBODAT is not written before the start of an SMBus frame STA A START followed by an address byte is re Must be cleared by software ceived STO A STOP is detected while addressed pending STOP is generated slave Arbitration is lost due to a detected STOP ACKRQ A byte has been received and an ACK re After each ACK cycle sponse value is needed only when hard ware ACK is not enabled ARBLOST A repeated START is detected as a MAS Each time is cleared TER when STA is low unwanted repeated START SCL is sensed low while attempting to gen erate a STOP or repeated START condition SDA is sensed low while transmitting a 1 excluding ACK bits ACK The incoming ACK value is low AC The incoming ACK value is high NOT ACKNOWL KNOWLEDGE EDGE SI A START has been generated Must be cleared by software Lost arbitration A byte has been transmitted and an ACK NACK received A byte has been received A START or repeated START followed by a slave address R W has been received A STOP has been received silabs com Smart Connected Energy friendly Rev 0 2 230 EFM8UB2 Reference Manual System Management Bus 2 SMBO and
187. art or repeated start condition was detected on the bus Writing a 1 to the STA bit initiates a start or repeated start on the bus 4 STO 0 RW SMBus Stop Flag When reading STO a 1 indicates that a stop condition was detected on the bus in slave mode or is pending in master mode When acting as a master writing a 1 to the STO bit initiates a stop condition on the bus This bit is cleared by hardware 3 ACKRQ 0 R SMBus Acknowledge Request Value Name Description 0 NOT SET No ACK requested 1 REQUESTED ACK requested 2 ARBLOST 0 R SMBus Arbitration Lost Indicator Value Name Description 0 NOT_SET No arbitration error 1 ERROR Arbitration error occurred 1 ACK 0 RW SMBus Acknowledge When read as a master the ACK bit indicates whether an ACK 1 or NACK 0 is received during the most recent byte transfer As slave this bit should be written to send an ACK 1 or NACK 0 to a master request Note that the logic level of the ACK bit on the SMBus interface is inverted from the logic of the register ACK bit silabs com Smart Connected Energy friendly Rev 0 2 245 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 Reset Access Description Sl 0 RW SMBus Interrupt Flag This bit is set by hardware to indicate that the current SMBus state machine operation such as writing a data or address byte is complete and the hardware needs additional control from the firmware to
188. associated timer enabled and configured to overflow after 25 ms and SMBOTOE set the timer interrupt service routine can be used to reset disable and re enable the SMBus in the event of an SCL low timeout SCL High SMBus Free Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 us the bus is designated as free When the SMBOFTE bit in SMBOCF is set the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods as defined by the timer configured for the SMBus clock source If the SMBus is waiting to generate a Master START the START will be generated following this timeout A clock source is required for free timeout detection even in a slave only implementa tion silabs com Smart Connected Energy friendly Rev 0 2 226 EFM8UB2 Reference Manual System Management Bus 2 SMBO and 5 1 18 3 3 Configuring the SMBus Module The SMBus can operate in both Master and Slave modes The interface provides timing and shifting control for serial transfers higher level protocol is determined by user software The SMBus interface provides the following application independent features Byte wise serial data transfers Clock signal generation on SCL Master Mode only and SDA data synchronization Timeout bus error recognition as defined by the SMBOCF configuration register START STOP timing detection and generation Bus arbitration I
189. ata from a SETUP packet is loaded into the EndpointO FIFO Software should unload the command from the EndpointO FIFO decode the command perform any necessary tasks and set the SOPRDY bit to indicate that it has serviced the OUT packet EndpointO IN Transactions When a SETUP request is received that requires the USB interface to transmit data to the host one or more IN requests will be sent by the host For the first IN transaction firmware should load an IN packet into the EndpointO FIFO and set the INPRDY bit An interrupt will be generated when an IN packet is transmitted successfully Note that no interrupt will be generated if an IN request is received before firmware has loaded a packet into the EndpointO FIFO If the requested data exceeds the maximum packet size for EndpointO as reported to the host the data should be split into multiple packets each packet should be of the maximum packet size excluding the last residual packet If the requested data is an integer multiple of the maximum packet size for EndpointO the last data packet should be a zero length packet signaling the end of the transfer Firmware should set the DATAEND bit to 1 after loading into the End pointO FIFO the last data packet for a transfer Upon reception of the first IN token for a particular control transfer EndpointO is said to be in Transmit Mode In this mode only IN tokens should be sent by the host to EndpointO The SUEND bit is set to 1 if a SETUP or OU
190. ating in one of the auto reload modes TMR5RLL holds the reload value for the low byte of Timer 5 TMRSL When operating in capture mode TMR5RLL is the captured value of TMR5L 19 4 26 TMR5RLH Timer 5 Reload High Byte Bit 7 6 5 4 3 2 1 0 TMRSRLH Access RW Reset 0x00 SFR Page OxF SFR Address 0xCB Bit Name Reset Access Description 7 0 TMR5RLH 0x00 RW Timer 5 Reload High Byte When operating in one of the auto reload modes TMR5RLH holds the reload value for the high byte of Timer 5 TMR5H When operating in capture mode TMR5RLH is the captured value of TMR5H 19 4 27 TMR5L Timer 5 Low Byte Bit 7 6 5 4 3 2 1 0 TMR5L Access RW Reset 0x00 SFR Page OxF SFR Address 0xCC Bit Name Reset Access Description 7 0 TMR5L 0x00 RW Timer 5 Low Byte In 16 bit mode the TMRSL register contains the low byte of the 16 bit Timer 5 In 8 bit mode TMR5L contains the 8 bit low byte timer value silabs com Smart Connected Energy friendly Rev 0 2 276 EFM8UB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 28 TMR5H Timer 5 High Byte Bit 7 6 5 4 3 2 1 0 TMR5H Access RW Reset 0x00 SFR Page OxF SFR Address 0xCD Bit Name Reset Access Description 7 0 TMR5H 0x00 RW Timer 5 High Byte In 16 bit mode the TMR5H register contains the high byte of the 16 bit T
191. be either 0 or 1 in the incoming address 0 0 RW Hardware Acknowledge Enable Enables hardware acknowledgement of slave address and received data bytes Value Name Description 0 ADR_ACK_MANUAL Firmware must manually acknowledge all incoming address and data bytes 1 ADR_ACK_AUTOMAT Automatic slave address recognition and hardware acknowledge is enabled IC 18 5 5 SMBODAT SMBus 0 Data Bit 7 6 5 4 3 2 1 0 SMBODAT Access RW Reset 0x00 SFR Page 0x0 SFR Address 0xC2 Bit 7 0 Name Reset Access Description SMBODAT 0x00 RW SMBus 0 Data The SMBODAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface The CPU can safely read from or write to this register whenever the SI serial inter rupt flag is set to logic 1 The serial data in the register remains stable as long as the SI flag is set When the SI flag is not set the system may be in the process of shifting data in out and the CPU should not attempt to access this register silabs com Smart Connected Energy friendly Rev 0 2 243 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 18 6 SMB1 Control Registers 18 6 1 SMB1CF SMBus 1 Configuration Bit 7 6 5 4 3 2 1 0 5 BUSY EXTHOLD SMBTOE SMBFTE SMBCS Access RW RW R RW RW RW RW Reset 0 0 0 0 0 0 0
192. be used by digital peripherals or as GPIO should be configured as digital I O PnMDIN n 1 For digital I O pins one of two output modes push pull or open drain must be selected using the PNMDOUT registers Push pull outputs PNMDOUT n 1 drive the port pad to the supply rails based on the output logic value of the port Open drain outputs have the high side driver disabled therefore they only drive the port pad to the lowside rail when the output logic value is 0 and become high impedance inputs both high low drivers turned off when the output logic value is 1 When a digital I O cell is placed in the high impedance state a weak pull up transistor pulls the port pad to the high side rail to ensure the digital input is at a defined logic state Weak pull ups are disabled when the cell is driven low to minimize power consumption and they be globally disabled by setting WEAKPUD to 1 The user should ensure that digital I O are always internally or externally pulled or driven to a valid logic state to minimize power consumption Port pins configured for digital always read back the logic state of the port pad regardless of the output logic value of the port pin To configure a pin as a digital input 1 Set the bit associated with the pin in the PnMDIN register to 1 This selects digital mode for the pin 2 lear the bit associated with the pin in the PhMDOUT register to 0 This configures the pin as open drain 3 Set
193. bit 7 description 3 B3 0 RW Port 2 Bit 3 Output Mode See bit 7 description 2 B2 0 RW Port 2 Bit 2 Output Mode See bit 7 description 1 B1 0 RW Port 2 Bit 1 Output Mode See bit 7 description 0 BO 0 RW Port 2 Bit 0 Output Mode See bit 7 description silabs com Smart Connected Energy friendly Rev 0 2 99 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 15 P2SKIP Port 2 Skip Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address OxD6 Bit Name Reset Access Description 7 B7 0 RW Port 2 Bit 7 Skip Value Name Description 0 NOT_SKIPPED P2 7 pin is not skipped by the crossbar 1 SKIPPED P2 7 pin is skipped by the crossbar 6 B6 0 RW Port 2 Bit 6 Skip See bit 7 description 5 B5 0 RW Port 2 Bit 5 Skip See bit 7 description 4 B4 0 RW Port 2 Bit 4 Skip See bit 7 description 3 B3 0 RW Port 2 Bit 3 Skip See bit 7 description 2 B2 0 RW Port 2 Bit 2 Skip See bit 7 description 1 B1 0 RW Port 2 Bit 1 Skip See bit 7 description 0 BO 0 RW Port 2 Bit 0 Skip See bit 7 description silabs com Smart Connected Energy friendly Rev 0 2 100 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 16 P3 Port 3 Pin Latch Bit 7 6 5 4 3 2 1 0
194. ble the on chip supply monitor and enable the supply monitor as a reset source as early in code as possible This should be the first set of instructions executed after the reset vector For C based systems this may involve modifying the startup code added by the C compiler See your compiler documentation for more details Make certain that there are no delays in software between enabling the supply monitor and enabling the supply monitor as a reset source Note The supply monitor must be enabled and enabled as a reset source when writing or erasing flash memory A flash error reset Will occur if either condition is not met As an added precaution if the supply monitor is ever disabled explicitly enable the supply monitor and enable the supply monitor as a reset source inside the functions that write and erase flash memory The supply monitor enable instructions should be placed just after the instruction to set PSWE to a 1 but before the flash write or erase operation instruction Make certain that all writes to the RSTSRC Reset Sources register use direct assignment operators and explicitly do not use the bit wise operators such as AND or OR For example RSTSRC 0x02 is correct RSTSRC 0x02 is incorrect Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1 Areas to check are initialization code which enables other reset sources such as the Missing Clock Detector or Comparator for example and in
195. byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Master SEN SEW Device Device Device Figure 21 6 Multi Processor Mode Interconnect Diagram silabs com Smart Connected Energy friendly Rev 0 2 285 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 UART1 Control Registers 21 4 1 SCON1 UART1 Serial Port Control Bit 7 6 5 4 3 2 1 0 OVR PERR Reserved REN TBX RBX Access RW RW R RW RW R RW R Reset 0 0 Varies 0 0 0 0 0 SFR Page ALL SFR Address 0xD2 Bit Name Reset Access Description 7 OVR 0 RW Receive FIFO Overrun Flag This bit indicates a receive FIFO overrun condition where an incoming character is discarded due to a full FIFO This bit must be cleared by firmware Value Name Description 0 NOT_SET Receive FIFO overrun has not occurred 1 SET Receive FIFO overrun has occurred 6 PERR 0 RW Parity Error Flag When parity is enabled this bit indicates that a parity error has occurred It is set to 1 when the
196. ccess RW Reset 0x00 SFR Page ALL SFR Address 0x82 Bit Name Reset Access Description 7 0 DPL 0x00 RW Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indirectly addressed flash memory or XRAM 10 4 2 DPH Data Pointer High Bit 7 6 5 4 3 2 1 0 RW Reset 0x00 SFR Page ALL SFR Address 0x83 Bit Name Reset Access Description 7 0 DPH 0x00 RW Data Pointer High The register is the high byte of the 16 bit DPTR DPTR is used to access indirectly addressed flash memory or XRAM silabs com Smart Connected Energy friendly Rev 0 2 74 EFM8UB2 Reference Manual CIP 51 Microcontroller Core 10 4 3 SP Stack Pointer Bit 7 6 5 4 3 1 0 SP Access RW Reset 0x07 SFR Page ALL SFR Address 0x81 Bit 7 0 Name Reset Access Description SP 0x07 RW Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incremented before every PUSH operation The SP register defaults to 0x07 after reset 10 4 4 ACC Accumulator Bit 7 6 5 4 3 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxEO bit addressable Bit Name Reset Access Description 7 0 ACC 0x00 RW Accumulator This register is the accumulator for arithmetic operations 10 4 5 B B Register Bit 7 6 5 4 3 1
197. ce source the REGOVR bit can be set to 1 12 3 2 1 Internal Voltage Reference The on chip voltage reference circuit consists of a 1 2 V temperature stable bandgap voltage reference generator and a selectable gain output buffer amplifier The buffer is configured for 1x or 2x gain using the REFBGS bit in register REFOCN On the 1x gain setting the output voltage is nominally 1 2 V and on the 2x gain setting the output voltage is nominally 2 4 V The on chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REFOCN to a 1 The maximum load seen by the VREF pin must be less than 200 pA to GND Bypass capacitors of 0 1 uF and 4 7 uF are recommended from the VREF pin to GND and a minimum of 0 1 is required If the on chip reference is not used the REFBE bit should be cleared to 0 Note When using either an external voltage reference or the on chip reference circuitry the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar 12 3 2 2 Supply or LDO Voltage Reference For applications with a non varying power supply voltage using the power supply as the voltage reference can provide the ADC with added dynamic range at the cost of reduced power supply noise rejection Additionally the internal 1 8 V LDO supply to the core may be used as a reference Neither of these reference sources are routed to the VREF pin and do not require additional external decou pling 12 3 2 3 Externa
198. ces must be configured to use the same clock phase and polarity The module should be disabled by clearing the SPIEN bit when changing the clock phase or polarity Note that CKPHA should be set to 0 on both the master and slave SPI when communicating between two Silicon Labs devices CKPOL 0 CKPHA 0 SCK CKPOL 0 CKPHA 1 CKPOL 1 CKPHA 0 ck TETEN CKPOL 1 CKPHA 1 3 gt z F VVVVVVV ss Xs Ne X Su Ne Figure 17 5 Master Mode Data Clock Timing SCK 1 LI LT LT LT LI LI LT Le SCK CKPOL 1 0 TUT LI LI LIP LI LOI LOI LO vosi wes y X X X X ser X YOM viso us Yme Vers X Y X YX NSS 4 Wire Mode Figure 17 6 Slave Mode Data Clock Timing CKPHA 0 silabs com Smart Connected Energy friendly Rev 0 2 215 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO SCK CKPOL 0 CKPHA 1 5 CKPOL 1 1 MOSI MISO NSS 4 Wire Mode Figure 17 7 Slave Mode Data Clock Timing CKPHA 1 17 3 5 Basic Data Transfer The SPI bus is inherently full duplex It sends and receives a single byte on every transfer The SPI peripheral may be operated on a byte by byte basis using the SPInDAT register and the SPIF flag The method firmware uses to send and receive data through the SPI interface is the same in either mode
199. control transfer EndpointO is said to be in Receive Mode In this mode only OUT tokens should be sent by the host to EndpointO The SUEND bit is set to 1 if a SETUP or IN token is received while EndpointO is in Receive Mode EndpointO will remain in Receive mode until one of the following occurs The SIE receives a SETUP or IN token The host sends a packet less than the maximum EndpointO packet size The host sends a zero length packet Firmware should set the DATAEND bit to 1 when the expected amount of data has been received The SIE will transmit a STALL condi tion if the host sends an OUT packet after the DATAEND bit has been set by firmware An interrupt will be generated with the STSTL bit set to 1 after the STALL is transmitted 16 3 12 Endpoints 1 2 and 3 Endpoints 1 3 are configured and controlled through their own sets of the following control status registers IN registers EINCSRL and EINCSRH and OUT registers EOUTCSRL and EOUTCSRH Only one set of endpoint control status registers is mapped into the USB register address space at a time defined by the contents of the INDEX register Endpoints 1 3 can be configured as IN OUT or both IN OUT Split Mode The endpoint mode Split Normal is selected via the SPLIT bit in register EINCSRH When SPLIT 1 the corresponding endpoint FIFO is split and both IN and OUT pipes are available When SPLIT 0 the corresponding endpoint functions as either IN or OUT the endpoint direct
200. d are not allowed PCA clock source CPS field is frozen PCA Idle control bit CIDL is frozen Module 4 is forced into software timer mode Writes to the Module 4 mode register PCAOCPMA are disabled While the WDT is enabled writes to the CR bit will not change the PCA counter state the counter will run until the WDT is disabled The PCA counter run control bit CR will read zero if the WDT is enabled but user software has not enabled the PCA counter If a match occurs between PCAOCPH4 and PCAOH while the WDT is enabled a reset will be generated To prevent a WDT reset the WDT may be updated with a write of any value to PCAOCPH4 Upon a PCAOCPH4 write PCAOH plus the offset held in PCAOCPLA is loaded into PCAOCPH4 Watchdog WDTE Watchdog Enable 8 bit WDLCK Watchdog Lock comparator Reset Watchdog PCAOL overflow PCAOCPLn 8 bit Adder Adder Enable Write to Watchdog PCAOCPHn Figure 14 8 PCA Module 4 with Watchdog Timer Enabled The 8 bit offset held in PCAOCPH4 is compared to the upper byte of the 16 bit PCA counter This offset value is the number of PCAOL overflows before a reset Up to 256 PCA clocks may pass before the first PCAOL overflow occurs depending on the value of the PCAOL when the update is performed The total offset is then given by the following equation in PCA clocks Offset 256 x PCAOCPL 256 PCAOL Note PCAOL is the value of the PCAOL
201. d asynchronous full duplex communication All data sent or received goes through the SBUFO register and in 9 bit mode the 8 bit in the SCONO register Transmitting Data Data transmission is initiated when software writes a data byte to the SBUFO register If 9 bit mode is used software should set up the desired 9th bit in TB8 prior to writing SBUFO Data is transmitted LSB first from the TX pin The TI flag in SCONO is set at the end of the transmission at the beginning of the stop bit time If Tl interrupts are enabled TI will trigger an interrupt Receiving Data To enable data reception firmware should write the REN bit to 1 Data reception begins when a start condition is recognized on the RX pin Data will be received at the selected baud rate through the end of the data phase Data will be transferred into the receive buffer under the following conditions There is room in the receive buffer for the data MCE is setto 1 and the stop bit is also 1 8 bit mode MCE is setto 1 and the 9th bitis also 1 9 bit mode MCE is 0 stop or 9th bit will be ignored In the event that there is not room in the receive buffer for the data the most recently received data will be lost The RI flag will be set any time that valid data has been pushed into the receive buffer If RI interrupts are enabled RI will trigger an interrupt Firmware may read the 8 LSBs of received data by reading the SBUFO register The RB8 bit in SCONO will re
202. d the port pin via the Crossbar The Crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin Value Name Description 0 0 PO 0 Select P0 0 Ox1 PO 1 Select P0 1 0 2 2 Select P0 2 0x3 3 Select P0 3 0 4 4 Select P0 4 0 5 PO 5 Select P0 5 0 6 PO 6 Select P0 6 0 7 PO 7 Select PO 7 3 INOPL 0 RW INTO Polarity Value Name Description 0 ACTIVE LOW INTO input is active low 1 ACTIVE HIGH INTO input is active high 2 0 INOSL Ox1 RW INTO Port Pin Selection These bits select which port pin is assigned to INTO This pin assignment is independent of the Crossbar INTO will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the Crossbar The Crossbar will not assign the port pin to peripheral if it is configured to skip the selected pin Value Name Description 0 0 PO 0 Select 0 0 0 1 PO 1 Select PO 1 0x2 2 Select P0 2 silabs com Smart Connected Energy friendly Rev 0 2 108 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts Bit Name Reset Access Description 0x3 3 Select P0 3 0 4 4 Select P0 4 0 5 PO 5 Select 0 5 0 6 6 Select P0 6 Ox7 PO 7 Select PO 7 silabs com Smart Connected Energy friendly Rev 0 2 109 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 Analog to
203. d to switch after every data packet is transmitted re gardless of ACK reception 2 SPLIT 0 RW FIFO Split Enable When this bit is set to 1 the selected endpoint FIFO is split The upper half of the selected FIFO is used by the IN endpoint and the lower half of the selected FIFO is used by the OUT endpoint 1 0 Reserved Must write reset value This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 208 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 25 EOUTCSRL USBO OUT Endpoint Control Low Bit 7 6 5 4 3 2 1 0 CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY Access Ww RW RW RW R RW R RW Reset 0 0 0 0 0 0 0 0 Indirect Address 0 14 Bit Name Reset Access Description 7 CLRDT 0 W Clear Data Toggle 6 STSTL 0 RW Sent Stall Flag Hardware sets this bit to 1 when a STALL handshake signal is transmitted This flag must be cleared by firmware 5 SDSTL 0 RW Send Stall Firmware should set this bit to 1 to generate a STALL handshake Firmware should clear this bit to 0 to terminate the STALL signal This bit has no effect in Isochronous mode 4 FLUSH 0 RW FIFO Flush Writing a 1 to this bit flushes the next packet to be read from the OUT endpoint FIFO The FIFO pointer is reset and the OPRDY bit is cleared Multiple packets must be flushed individuall
204. data FIFO allows UART1 to receive multiple bytes before data is lost and an overflow occurs UART 1 provides the following features Asynchronous transmissions and receptions Dedicated baud rate generator supports baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 5 6 7 8 or 9 bit data Automatic start and stop generation Automatic parity generation and checking Three byte FIFO on receive Serial Peripheral Interface SPIO The serial peripheral interface SPI module provides access to a flexible full duplex synchronous serial bus The SPI can operate as master or slave device in both 3 wire or 4 wire modes and supports multiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select the SPI in slave mode or to disable master mode operation in a multi master environment avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers NSS can also be configured as a firmware controlled chip select output in master mode or disabled to reduce the number of pins required Additional general purpose port I O pins can be used to select multiple slave devices in master mode The SPI module includes the following features Supports 3 or 4 wire operation in master or slave modes Supports external clock frequencies up to SYSCLK 2 in master mode and SYSCLK 10 in slave mode Support for four clock phase and polarity options
205. de the TMR4H register contains the high byte of the 16 bit Timer 4 In 8 bit mode TMR4H contains the 8 bit high byte timer value silabs com Smart Connected Energy friendly Rev 0 2 274 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 24 TMR5CNO Timer 5 Control 0 Bit 7 6 5 4 3 2 1 0 TF5H TF5L TFSLEN Reserved T5SPLIT TR5 Reserved T5XCLK Access RW RW RW R RW RW R RW Reset 0 0 0 0 0 0 0 0 SFR Page OxF SFR Address 0xC8 bit addressable Bit Name Reset Access Description 7 TF5H 0 RW Timer 5 High Byte Overflow Flag Set by hardware when the Timer 5 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 5 overflows from OxFFFF to 0x0000 When the Timer 5 interrupt is enabled setting this bit causes the CPU to vector to the Timer 5 interrupt service routine This bit must be cleared by firmware 6 TF5L 0 RW Timer 5 Low Byte Overflow Flag Set by hardware when the Timer 5 low byte overflows from OxFF to 0x00 TF5L will be set when the low byte overflows regardless of the Timer 5 mode This bit must be cleared by firmware 5 0 RW Timer 5 Low Byte Interrupt Enable When set to 1 this bit enables Timer 5 Low Byte interrupts If Timer 5 interrupts are also enabled an interrupt will be gen erated when the low byte of Timer 5 overflows 4 Reserved Mus
206. e 14 3 8 2 16 Bit PWM Mode 14 3 9 Watchdog Timer Mode 14 4 Control Registers 14 4 1 PCAOCNO PCA Control 0 14 4 2 PCAOMD PCA Mode 14 4 3 PCAOL PCA Counter Timer Byte 14 4 4 PCAOH PCA Counter Timer High Byte 14 4 5 PCAOCPMO PCA Channel 0 Capture Compare Mode 14 4 6 PCAOCPLO PCA Channel 0 Capture Module Low Byte 14 4 7 PCAOCPHO PCA Channel 0 Capture Module High Byte 14 4 8 PCAOCPM1 PCA Channel 1 Capture Compare Mode 14 4 9 PCAOCPL 1 PCA Channel 1 Capture Module Low Byte Table of Contents 125 125 126 127 127 127 127 127 128 128 129 130 131 131 132 133 134 134 135 136 137 137 137 138 138 138 138 140 141 142 143 143 145 145 145 148 148 149 150 150 151 152 152 153 154 300 15 16 14 4 10 PCAOCPH1 PCA Channel 1 Capture Module High Byte 14 4 11 PCAOCPM2 PCA Channel 2 Capture Compare Mode 14 4 12 PCAOCPL2 PCA Channel 2 Capture Module Low Byte 14 4 13 2 PCA Channel 2 Capture Module High Byte 14 4 14 PCAOCPM3 PCA Channel 3 Capture Compare Mode 14 4 15 PCAOCPL3 PCA Channel 3 Capture Module Low Byte 14 4 16 PCAOCPH3 PCA Channel 3 Capture Module High Byte 14 4 17 PCAOCPM4 PCA Channel 4 Capture Compare Mode 14 4 18 PCAOCPL4 PCA Channel 4 Capture Module Low Byte 14 4 19 PCAOCPH4 PCA Channel 4 Capture Module High Byte External Memory Interface EMIFO 15 1 Introduction 15 2 Features 15
207. e 0 PINRSF Varies R HW Pin Reset Flag This read only bit is set to 1 if the RSTb pin caused the last reset Reads and writes of the RSTSRC register access different logic in the device Reading the register always returns status information to indicate the source of the most recent reset Writing to the register activates certain options as reset sources It is recommended to not use any kind of read modify write operation on this register When the PORSF bit reads back 1 all other RSTSRC flags are indeterminate Writing 1 to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset silabs com Smart Connected Energy friendly Rev 0 2 66 EFM8UB2 Reference Manual Reset Sources and Power Supply Monitor 9 4 2 VDMOCN Supply Monitor Control Bit 7 6 5 4 3 2 1 0 VDMEN VDDSTAT Reserved Access RW R R Reset Varies Varies Varies SFR Page ALL SFR Address OxFF Bit Name Reset Access Description 7 VDMEN Varies RW Supply Monitor Enable This bit turns the supply monitor circuit on off The supply monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC Selecting the supply monitor as a reset source before it has stabilized may generate a system reset In systems where this reset would be undesirable a delay should be introduced between enabling the supply monitor and selectin
208. e the MSTEN bit should be set to 1 Writing a byte of data to the SPInDAT register writes to the trans mit buffer If the SPI shift register is empty a byte is moved from the transmit buffer into the shift register and a bi directional data transfer begins The SPI module provides the serial clock on SCK while simultaneously shifting data out of the shift register MSB first on MOSI and into the shift register MSB first on MISO Upon completing a transfer the data received is moved from the shift register into the receive buffer If the transmit buffer is not empty the next byte in the transmit buffer will be moved into the shift register and the next data transfer will begin If no new data is available in the transmit buffer the SPI will halt and wait for new data to initiate the next transfer Bytes that have been received and stored in the receive buffer may be read from the buffer via the SPInDAT register 17 3 3 Slave Mode Operation When the SPI block is enabled and not configured as a master it will operate as a SPI slave As a slave bytes are shifted in through the MOSI pin and out through the MISO pin by an external master device controlling the SCK signal A bit counter in the SPI logic counts SCK edges When 8 bits have been shifted through the shift register a byte is copied into the receive buffer Data is read from the receive buffer by reading SPInDAT A slave device cannot initiate transfers Data to be transferred to the master device
209. e 7 1 Power Modes Power Mode Details Mode Entry Wake Up Sources Normal Core and all peripherals clocked and fully operational Idle Core halted Set IDLE bit in PCONO Any interrupt All peripherals clocked and fully operational Code resumes execution on wake event Suspend Core and peripheral clocks halted 1 Switch SYSCLK to USBO Bus Activity Code resumes execution on wake event HFOSCO 2 Set SUSPEND bit in HFOOCN silabs com Smart Connected Energy friendly Rev 0 2 42 EFM8UB2 Reference Manual Power Management and Internal Regulators Power Mode Details Mode Entry Wake Up Sources Shutdown All internal power nets shut down 1 Set STOPCF bit in RSTb pin reset 5V regulator remains active if enabled REGO1CN Power on reset Pins retain state 2 Set STOP bit in PCONO Exit on pin or power on reset 7 2 Features Supports four power modes 1 Normal mode Core and all peripherals fully operational 2 Idle mode Core halted peripherals fully operational core waiting for interrupt to continue 3 Suspend mode be used with USBO peripheral to provide low current in USB suspend Very fast wake up time and code resumes execution at the next instruction 4 Shutdown mode Lowest power state Device is off drawing very little current and waiting ror a pin reset or power on reset Note Legacy 8051 Stop mode is also supported where the internal LDO remain
210. e Auxiliary Enable s Pending Flag s Reset 0x0000 Top External Interrupt 0 0x0003 0 IE EXO TCON_IEO Timer 0 Overflow 0x000B 1 IE ETO TCON TFO External Interrupt 1 0x0013 2 IE EX1 TCON IE1 Timer 1 Overflow 0x001B 3 ET TCON TF1 UART 0 0x0023 4 50 SCONO RI SCONO TI Timer 2 Overflow 0 002 5 IE ET2 TMR2CNO TF2H TMR2CNO TF2L SPIO 0x0033 6 IE ESPIO SPIOCNO MODF SPIOCNO RXOVRN SPIOCNO SPIF SPIOCNO WCOL SMBus 0 0 003 7 EIE1_ESMBO SMBOCN_SI USBO 0x0043 8 EIE1_EUSBO CMIE_RSTINTE CMINT_RSTINT CMIE_RSUINTE CMINT_RSUINT CMIE_SOFE CMINT_SOF CMIE_SUSINTE CMINT_SUSINT EPOE EPO INTINT IN1 IN1IE IN2E IN1INT IN2 IN1IE IN1INT IN3 OUT1IE_OUT1E OUT1INT OUT1 OUT1IE_OUT2E OUT1INT_OUT2 OUTTIE OUT3E OUT1INT_OUT3 ADCO Window Compare 0x004B 9 EIE1_EWADCO ADCOCNO_ADWINT ADCO End of Conversion 0x0053 10 EIE1_EADCO ADCOCNO_ADINT PCAO 0x005B 11 EIE1_EPCAO PCAOCPMO ECCF PCAOCNO CCFO 1 PCAOCPM2 ECCF PCAOCPM3 ECCF 4 ECCF PCAOCNO CCF1 PCAOCNO CCF2 PCAOCNO CCF3 PCAOCNO CCF4 PCAOCNO CF silabs com Smart Connected Energy friendly Rev 0 2 30 EFM8UB2 Reference Manual Interrupts Interrupt Source Priority Primary Enable Auxiliary Enable s Pending Flag s Comparator 0 0x0063 12 EIE1 ECPO CMPOMD CPFIE CMPOCNO CPFIF CMPOMD CPRIE CMPOCNO CPRIF Comparato
211. e associated interrupt enable bits are located in the USB registers IN1IE OUT1IE and CMIE A USB interrupt is generated when any of the USB interrupt flags is set to 1 Note Reading a USB interrupt flag register resets all flags in that register to O 16 3 10 Serial Interface Engine The serial interface engine SIE performs all low level USB protocol tasks interrupting the processor when data has successfully been transmitted or received When receiving data the SIE will interrupt the processor when a complete data packet has been received appropriate handshaking signals are automatically generated by the SIE When transmitting data the SIE will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received The SIE will not interrupt the processor when corrupted erroneous packets are received silabs com Smart Connected Energy friendly Rev 0 2 186 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 3 11 Endpoint 0 EndpointO is managed through the USB register EOCSR The INDEX register must be loaded with 0x00 to access the EOCSR register An 0 interrupt is generated when one of the following occurs A data packet OUT or SETUP has been received and loaded into the EndpointO FIFO The OPRDY bit is set to 1 by hardware An IN data packet has successfully been unloaded from the EndpointO FIFO and transmitted to the host INPRDY is
212. e both set while in Master Mode a STOP followed by a START will be generated The ARBLOST bit indicates that the interface has lost an arbitration This may occur anytime the interface is transmitting master or slave A lost arbitration while operating as a slave indicates a bus error condition ARBLOST is cleared by hardware each time SI is cleared The SI bit SMBus Interrupt Flag is set at the beginning and end of each transfer after each byte frame or when an arbitration is lost Note The SMBus interface is stalled while SI is set if SCL is held low at this time the bus is stalled until software clears SI silabs com Smart Connected Energy friendly Rev 0 2 229 EFM8UB2 Reference Manual System Management Bus 2 SMBO and 5 1 Hardware ACK Generation When the EHACK bit in register SMBOADM is set to 1 automatic slave address recognition and ACK generation is enabled As a re ceiver the value currently specified by the ACK bit will be automatically sent on the bus during the ACK cycle of an incoming data byte As a transmitter reading the ACK bit indicates the value received on the last ACK cycle The ACKRQ bit is not used when hardware ACK generation is enabled If a received slave address is NACKed by hardware further slave events will be ignored until the next START is detected and no interrupt will be generated Table 18 2 Sources for Hardware Changes to SMBOCNO Bit Set by Hardware When Cleared by H
213. e following features Clock sources include SYSCLK SYSCLK divided by 12 or the External Clock divided by 8 16 bit auto reload timer mode Dual 8 bit auto reload timer mode USB start of frame or falling edge of LFOSCO capture Timer 2 and Timer 3 Watchdog Timer WDTO The device includes a programmable watchdog timer WDT integrated within the PCAO peripheral A WDT overflow forces the MCU into the reset state To prevent the reset the WDT must be restarted by application software before overflow If the system experiences a software or hardware malfunction preventing the software from restarting the WDT the WDT overflows and causes a reset Following a reset the WDT is automatically enabled and running with the default maximum time interval If needed the WDT can be disabled by system software The state of the RSTb pin is unaffected by this reset The Watchdog Timer integrated in the PCAO peripheral has the following features Programmable timeout interval Runs from the selected PCA clock source Automatically enabled after any system reset silabs com Smart Connected Energy friendly Rev 0 2 3 EFM8UB2 Reference Manual System Overview 1 6 Communications and Other Digital Peripherals Universal Serial Bus 05 0 The USBO module provides Full Low Speed function for USB peripheral implementations The USB function controller USBO consists of a Serial Interface Engine SIE USB transceiver including matc
214. e low byte of the PCAOCPn register PCAOCPLn To adjust the duty cycle PCAOCPLn should not normally be written directly Instead the recommendation is to adjust the duty cycle using the high byte of the PCAOCPn register register PCAOCPHn This allows seamless updating of the PWM waveform as PCAOCPLn is reloaded automatically with the value stored in PCAOCPHn during the overflow edge edge aligned mode or the up edge in center aligned mode Setting the ECOMn and PWMn bits in the PCAOCPMn register and setting the CLSEL bits in register PCAOPWM to 00b enables 8 Bit Pulse Width Modulator mode If the MATn bit is set to 1 the CCFn flag for the module is set each time a match edge or up edge occurs The COVF flag in PCAOPWM can be used to detect the overflow falling edge which occurs every 256 PCA clock cycles 14 3 8 2 16 Bit PWM Mode A PCA module may also be operated in 16 Bit PWM mode 16 bit PWM mode is independent of the other PWM modes The entire PCAOCP register is used to determine the duty cycle in 16 bit PWM mode To output a varying duty cycle new value writes should be synchronized with the PCA CCFn match flag to ensure seamless updates 16 Bit PWM mode is enabled by setting the ECOMn PWMn and PWM16n bits in the PCAOCPMn register For a varying duty cycle the match interrupt flag should be enabled ECCFn 1 AND MATn 1 to help synchronize the capture compare register writes If the MAThn bit is set to 1 the CCFn flag for
215. e module setup as specified within the individual module PCAOCPMn registers as well as the PCAOPWM register Modules can be configured for 8 bit mode or for 16 bit mode individually using the PCAOCPMn registers silabs com Smart Connected Energy friendly Rev 0 2 143 EFM8UB2 Reference Manual Programmable Counter Array PCAO Edge Aligned PWM When configured for edge aligned mode a module generates an edge transition at two points for every 2N PCA clock cycles where is the selected PWM resolution in bits In edge aligned mode these two edges are referred to as the match and overflow edges The polarity at the output pin is selectable and can be inverted by setting the appropriate channel bit to 1 in the PCAOPOL register Prior to inversion a match edge sets the channel to logic high and an overflow edge clears the channel to logic low The match edge occurs when the the lowest bits of the module s PCAOCPn register match the corresponding bits of the main counter register For example with 8 bit PWM the match edge occurs any time bits 7 0 of the PCAOCPn register match bits 7 0 of the PCAO counter value The overflow edge occurs when an overflow of the PCAO counter happens at the desired resolution For example with 8 bit PWM the overflow edge occurs when bits 7 0 of the PCAO counter transition from all 1s to all Os All modules configured for edge aligned mode at the same resolution align on the ove
216. e the crossbar to skip the selected pin s IEO and IE1 in the TCON register serve as the interrupt pending flags for the INTO and INT1 external interrupts respectively If an INTO or INT1 external interrupt is configured as edge sensitive the corresponding interrupt pending flag is automatically cleared by the hard ware when the CPU vectors to the ISR When configured as level sensitive the interrupt pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit INOPL or IN1PL the flag remains logic O while the input is inactive The external interrupt source must hold the input active until the interrupt request is recognized It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated 11 3 5 Direct Port I O Access Read Write All port I O are accessed through corresponding special function registers When writing to a port the value written to the SFR is latch ed to maintain the output data value at each pin When reading the logic levels of the port s input pins are returned regardless of the XBRn settings i e even when the pin is assigned to another signal by the crossbar the port register can always read its corresponding port I O The exception to this is the execution of the read modify write instructions that target a Port Latch register as the destina tion The read modify write instructions when operating on a port S
217. e to return the last avail able data byte in the RX FIFO silabs com Smart Connected Energy friendly Rev 0 2 289 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 4 SBCON1 UART1 Baud Rate Generator Control Bit 7 6 5 4 3 2 1 0 Reserved BREN Reserved BPS Access RW RW RW RW Reset 0 0 0x0 0x0 SFR Page ALL SFR Address 0xAC Bit Name Reset Access Description 7 Reserved Must write reset value 6 BREN 0 RW Baud Rate Generator Enable Value Name Description 0 DISABLED Disable the baud rate generator UART1 will not function 1 ENABLED Enable the baud rate generator 5 2 Reserved Must write reset value 1 0 BPS 0x0 RW Baud Rate Prescaler Select Value Name Description 0x0 DIV BY 12 Prescaler 12 Ox1 DIV BY 4 Prescaler 4 0 2 DIV_BY_48 Prescaler 48 0x3 DIV_BY_1 Prescaler 1 21 4 5 SBRLH1 UART1 Baud Rate Generator High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address 0xB5 Access Description 7 0 BRH 0x00 RW UART1 Baud Rate Reload High This field is the high byte of the 16 bit UART1 baud rate generator The high byte of the baud rate generator should be written first then the low byte The baud rate is determined by the following equation Baud Rate SYSCLK 65536 BRH1 BRL1 1 2 1 Prescaler si
218. e when Reset signaling is detected on the bus Upon this detection the following occur 1 The USBO Address is reset FADDR 0x00 2 Endpoint FIFOs are flushed 3 Control status registers are reset to 0x00 EOCSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH 4 USB register INDEX is reset to 0x00 5 All USB interrupts excluding the Suspend interrupt are enabled and their corresponding flags cleared 6 A USB Reset interrupt is generated if enabled Writing a 1 to the USBRST bit will generate an asynchronous USB reset All USB registers are reset to their default values following this asynchronous reset Suspend Mode With Suspend detection enabled SUSEN 1 USBO will enter suspend mode when Suspend signaling is detected on the bus An interrupt will be generated if enabled SUSINTE 1 The Suspend interrupt service routine ISR should perform appli cation specific configuration tasks such as disabling appropriate peripherals and or configuring clock sources for low power modes The USB module exits Suspend mode when any of the following occur Resume signaling is detected or generated Reset signaling is detected A device or USB reset occurs If the device itself is in suspend mode the internal oscillator will also exit suspend mode upon any of the above listed events Resume Signaling The USB module exits Suspend mode if Resume signaling is detected on the bus A Resume interrupt will be gen erated upon detection if enabled
219. ead the 8 LSBs of received data by reading the SBUF1 register The RBX bit in SCON1 will represent the extra received bit or the stop bit depending on whether XBE is enabled If the extra bit is enabled it should be read prior to reading SBUF1 21 3 4 Multiprocessor Communications UART1 supports multiprocessor communication between a master processor and one or more slave processors by special use of the extra data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its extra bit is logic 1 in a data byte the extra bit is always set to logic 0 Setting the MCE bit and the XBE bit in the SMOD1 register configures the UART for multi processor communications When a stop bit is received the UART will generate an interrupt only if the extra bit is logic 1 RBX 1 signifying an address byte has been received In the UART interrupt handler software will compare the received address with the slave s own assigned address If the addresses match the slave will clear its MCE bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE bit to ignore all transmissions until it receives the next address
220. eads Value Name Description 0 DISABLED BUSY must be written manually for each USBO indirect register read 1 ENABLED The next indirect register read will automatically be initiated when firmware reads USBODAT USBADDR bits will not be changed 5 0 USBOADR 0x00 RW 05 0 Indirect Register Address These bits hold a 6 bit address used to indirectly access the USBO core registers Reads and writes to USBODAT will target the register indicated by the USBADDR bits silabs com Smart Connected Energy friendly Rev 0 2 191 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 3 USBODAT USBO Data Bit 7 6 5 4 3 2 1 0 Name USBODAT Access RW Reset 0x00 SFR Page ALL SFR Address 0x97 Bit Name Reset Access Description 7 0 USBODAT 0x00 RW 05 0 Data This register is used to indirectly read and write the USBO register targeted by USBOADDR 16 4 4 INDEX USBO Endpoint Index Bit 7 6 5 4 3 2 1 0 Reserved EPSEL Access R RW Reset 0x0 0x0 Indirect Address OxOE Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 0 EPSEL 0 0 RW Endpoint Select Bits This field selects which endpoint is targeted when indexed USBO registers are accessed Value Name Description 0x0 ENDPOINT 0 Endpoint 0 0 1 ENDPOINT_1 Endpoint 1 0 2 ENDPOINT_2 Endpoint 2 0x3 ENDPOINT_3 Endpoint 3 This register is accessed indirectly usin
221. ed mode MUXMD 0 Value Name Description 0x0 1 CLOCK ALE high and ALE low pulse width 1 SYSCLK cycle Ox1 2 CLOCKS ALE high and ALE low pulse width 2 SYSCLK cycles Rev 0 2 176 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual External Memory Interface EMIFO Reset Access Description 0x2 3 CLOCKS ALE high and ALE low pulse width 3 SYSCLK cycles 0x3 4_CLOCKS ALE high and ALE low pulse width 4 SYSCLK cycles silabs com Smart Connected Energy friendly Rev 0 2 177 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 4 3 EMIOTC External Memory Timing Control Bit 7 6 5 1 ASETUP PWIDTH AHOLD Access RW RW RW Reset 0x3 OxF 0x3 SFR Page ALL SFR Address 0x84 Bit Name Reset Access Description 7 6 ASETUP 0x3 RW EMIF Address Setup Time Value Name Description 0 0 0 CLOCKS Address setup time 0 SYSCLK cycles 0 1 1_CLOCK Address setup time 1 SYSCLK cycle 0 2 2_CLOCKS Address setup time 2 SYSCLK cycles 0x3 3_CLOCKS Address setup time 3 SYSCLK cycles 5 2 PWIDTH OxF RW EMIF lt overline gt WR lt overline gt and lt overline gt RD lt overline gt Pulse Width Con trol Value Name Description 0x0 1 CLOCK AWR and RD pulse width is 1 SYSCLK cycle 0 1 2 CLOCKS AWR and RD pulse width is 2 SYSCLK cycles 0 2 3 CLOCKS WR RD pulse width is 3 SYSCLK cycles 0x3 4 CLOCKS W
222. ed provided as normal operands in DPTR and A Before writing to flash memory using MOVX flash write operations must be enabled by setting the PSWE bit in the PSCTL register to logic 1 this directs the MOVX writes to target flash memory and writing the flash key codes in sequence to the FLKEY register The PSWE bit remains set until cleared by firmware A write to flash memory can clear bits to logic 0 but cannot set them A byte location to be programmed should be erased already set to OxFF before a new value is written To write a byte of flash perform the following steps 1 Disable interrupts recommended 2 Write the first key code to FLKEY 0xA5 3 Write the second key code to FLKEY OxF1 4 Set the PSWE bit register PSCTL 5 Clear the PSEE bit register PSCTL silabs com Smart Connected Energy friendly Rev 0 2 23 EFM8UB2 Reference Manual Flash Memory 6 Using the MOVX instruction write a single data byte to the desired location within the desired page 7 Clear the PSWE bit 4 3 3 Flash Write and Erase Precautions Any system which contains routines which write or erase flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range of supply voltage system clock frequency or temperature This accidental execution of flash modifying code can result in alteration of flash memory contents causing a system fai
223. egister Value Name Description 0 NOT_SET OUT Endpoint 1 interrupt inactive 1 SET OUT Endpoint 1 interrupt active 0 Reserved Must write reset value This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 199 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 16 CMINT USBO Common Interrupt Bit 7 6 4 3 2 1 0 Reserved SOF RSTINT RSUINT SUSINT Access R R R R R Reset 0x0 0 0 0 0 Indirect Address 0x06 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 SOF 0 R Start of Frame Interrupt Flag This bit is set by hardware when a SOF token is received This interrupt event is synthesized by hardware an interrupt will be generated when hardware expects to receive a SOF event even if the actual SOF signal is missed or corrupted This bit is cleared when firmware reads the CMINT register Value Name Description 0 NOT_SET SOF interrupt inactive 1 SET SOF interrupt active 2 RSTINT 0 R Reset Interrupt Flag Set by hardware when reset signaling is detected on the bus This bit is cleared when firmware reads the CMINT register Value Name Description 0 NOT_SET Reset interrupt inactive 1 SET Reset interrupt active 1 RSUINT 0 R Resume Interrupt Flag Set by hardware when resume signaling is detected on the bus while USBO is in
224. end SUEND event Hardware clears the SUEND bit when firm ware writes 1 to SSUEND SOPRDY 0 RW Serviced OPRDY Firmware should write 1 to this bit after servicing a received Endpoint 0 packet The OPRDY bit will be cleared by a write of 1 to SOPRDY SDSTL 0 RW Send Stall Firmware can write 1 to this bit to terminate the current transfer due to an error condition unexpected transfer request etc Hardware will clear this bit to 0 when the STALL handshake is transmitted SUEND 0 R Setup End Hardware sets this read only bit to 1 when a control transaction ends before firmware has written 1 to the DATAEND bit Hardware clears this bit when firmware writes 1 to SSUEND DATAEND 0 RW Data End Firmware should write 1 to this bit 1 When writing 1 to INPRDY for the last outgoing data packet 2 When writing 1 to INPRDY for a zero length data packet 3 When writing 1 to SOPRDY after servicing the last incoming data packet This bit is automatically cleared by hardware STSTL 0 RW Sent Stall Hardware sets this bit to 1 after transmitting a STALL handshake signal This flag must be cleared by firmware INPRDY 0 RW IN Packet Ready Firmware should write 1 to this bit after loading a data packet into the Endpoint 0 FIFO for transmit Hardware clears this bit and generates an interrupt under one of the following conditions 1 The packet is transmitted 2 The packet is overwritten by an incoming SETUP packet
225. eneration is enabled The interrupt occurs before the ACK with hardware ACK generation disabled and after the ACK when hardware ACK generation is enabled Interrupts with Hardware ACK Enabled EHACK 1 Data Byte Data Byte Q lt Interrupts with Hardware ACK Disabled EHACK 0 Received by SMBus S START Interface Haud N Transmitted by READ SMBus Interface SLA Slave Address Figure 18 7 Typical Master Read Sequence silabs com Smart Connected Energy friendly Rev 0 2 234 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 STA sent 1 Clear the STA and STO flags 2 Write SMBODAT with the slave address and R W bit set to 1 3 Clear the interrupt flag SI Send Repeated Start 1 Set the STO 1 Set the STA flag flag 2 Clear the 2 Clear the interrupt flag SI interrupt flag SI Interrupt 1 Read Data From SMBODAT 2 Clear the interrupt flag SI Figure 18 8 Master Read Sequence State Diagram EHACK 1 silabs com Smart Connected Energy friendly Rev 0 2 235 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 Slave Write Sequence During a write sequence an SMBus master writes data to a slave device The slave in this transfer will be a receiver during the address byte and a receiver during all data bytes When slave events are enabled INH 0 the interface
226. er and slave events Slave events may be disabled by setting the INH bit With slave events inhibited the SMBus interface will still monitor the SCL and SDA pins however the interface will NACK all received addresses and will not generate any slave interrupts When the INH bit is set all slave events will be inhibited following the next START interrupts will continue for the duration of the current transfer The SMBCS bit field selects the SMBus clock source which is used only when operating as a master or when the Free Timeout detec tion is enabled When operating as a master overflows from the selected source determine both the bit rate and the absolute minimum SCL low and high times The selected clock source may be shared by other peripherals so long as the timer is left running at all times The selected clock source should typically be configured to overflow at three times the desired bit rate When the interface is operating as a master and SCL is not driven or extended by any other devices on the bus the device will hold the SCL line low for one overflow period and release it for two overflow periods is typically twice as large as ow The actual SCL output may vary due to other devices on the bus SCL may be extended low by slower slave devices driven low by contending master devices or have long ramp times The SMBus hardware will ensure that once SCL does return high it reads a logic high state for a minimum of one overfl
227. erflow rate for Timer 0 High in 8 bit mode is F input Clock _ F input Clock 28 THO 7 256 THO FTIMERO Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode settings To run Timer 1 while Timer 0 is in Mode 3 set the Timer 1 Mode as 0 1 or 2 To disable Timer 1 configure it for Mode 3 TOM Pre scaled Clock THO P 8 bits TF1 Interrupt Flag SYSCLK TO TLO P 8 bits TFO Interrupt Flag Figure 19 3 TO Mode 3 Block Diagram 19 3 3 Timer 2 Timer 3 Timer 4 and Timer 5 Timer 2 Timer 3 Timer 4 and Timer 5 are functionally equivalent with the only differences being the top level connections to other parts of the system The timers are 16 bits wide formed by two 8 bit SFRs TMRnL low byte and TMRnH high byte Each timer may operate in 16 bit auto reload mode dual 8 bit auto reload split mode or capture mode silabs com Smart Connected Energy friendly Rev 0 2 253 EFM8UB2 Reference Manual Timers TimerO 1 2 Timer3 Timer4 and Timer5 Clock Selection Clocking for each timer is configured using the TNXCL
228. es Lock Byte Page The level of flash security depends on the flash access method The three flash access methods that can be restricted are reads writes and erases from the C2 debug interface user firmware executing on unlocked pages and user firmware executing on locked pages Table 4 2 Flash Security Summary Firmware Permissions Permissions according to the area firmware is executing from Target Area for Read Write Erase Unlocked User Locked User Page Unlocked Data Locked Data Page Page Page Any Unlocked Page R W E R W E R W E R W E Locked Page except security page reset R W E reset R W E Locked Security Page reset R W reset R W Reserved Area reset reset reset reset R Read permitted W Write permitted E Erase permitted reset Flash error reset triggered n a Not applicable Table 4 3 Flash Security Summary C2 Permissions Target Area for Read Write Erase Permissions from C2 interface Any Unlocked Page R W E Any Locked Page Device Erase Only silabs com Smart Connected Energy friendly Rev 0 2 22 EFM8UB2 Reference Manual Flash Memory Target Area for Read Write Erase Permissions from C2 interface Reserved Area None R Read permitted W Write permitted E Erase permitted Device Erase Only No read write or individual page erase is all
229. es 0x10 0x17 0x3 BANK3 Bank 3 Addresses 0x18 0x1F 2 OV 0 RW Overflow Flag This bit is set to 1 under the following circumstances 1 An ADD ADDC or SUBB instruction causes a sign change overflow 2 A MUL instruction results in an overflow result is greater than 255 3 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases 1 F1 0 RW User Flag 1 This is a bit addressable general purpose flag for use under firmware control 0 PARITY 0 R Parity Flag This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even Rev 0 2 76 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual CIP 51 Microcontroller Core 10 4 7 PFEOCN Prefetch Engine Control Bit 7 6 5 4 3 2 1 0 Reserved PFEN Reserved FLBWE Access R RW R RW Reset 0x0 1 0x0 0 SFR Page ALL SFR Address OxAF Bit Name Reset Access Description 7 6 Reserved Must write reset value 5 PFEN 1 RW Prefetch Enable The prefetch engine should be disabled when the device is in suspend mode to save power Value Name Description 0 DISABLED Disable the prefetch engine SYSCLK 25 MHz 1 ENABLED Enable the prefetch engine SYSCLK gt 25 MHz 4 1 Reserved Must write reset value 0 FLBWE 0 RW Flash Block Write Enable This bit allo
230. etect a LOW SDA and lose the arbitration The winning master continues its transmission without interruption the losing master becomes a slave and receives the rest of the transfer if addressed This arbitration scheme is non de structive one device always wins and no data is lost Clock Low Extension SMBus provides a clock synchronization mechanism similar to 12C which allows devices with different speed capabilities to coexist on the bus A clock low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency SCL Low Timeout If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master cannot force the SCL line high to correct the error condition To solve this problem the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a timeout condition Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition For the SMBus 0 interface Timer 3 is used to implement SCL low timeouts The SCL low timeout feature is enabled by setting the SMBOTOE bit in SMBOCF The associated timer is forced to reload when SCL is high and allowed to count when SCL is low With the
231. ew Low Current Comparators 0 1 Analog comparators are used to compare the voltage of two analog inputs with a digital output indicating which input voltage is higher External input connections to device I O pins and internal connections are available through separate multiplexers on the positive and negative inputs Hysteresis response time and current consumption may be programmed to suit the specific needs of the application The comparator module includes the following features Up to 5 external positive inputs Up to 5 external negative inputs Synchronous and asynchronous outputs can be routed to pins via crossbar Programmable hysteresis between 0 and 20 mV Programmable response time Interrupts generated on rising falling or both edges 1 8 Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition On entry to this reset state the following occur The core halts program execution Module registers are initialized to their defined reset values unless the bits reset only with a power on reset External port pins are forced to a known state Interrupts and timers are disabled All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power on reset The contents of RAM are unaffected during a reset any previously stored data is preserved as long as power is not lost The Port I O la
232. f the SMBO interrupt Value Name Description 0 LOW SMBO interrupt set to low priority level 1 HIGH SMBO interrupt set to high priority level silabs com Smart Connected Energy friendly Rev 0 2 39 EFM8UB2 Reference Manual Interrupts 6 3 5 EIE2 Extended Interrupt Enable 2 Bit 7 6 5 4 3 2 1 0 Name Reserved 5 ET4 ESMB1 Reserved ES1 EVBUS Access R RW RW RW RW RW RW Reset 0x0 0 0 0 0 0 0 SFR Page ALL SFR Address OxE7 Bit Name Reset Access Description 7 6 Reserved Must write reset value 5 ET5 0 RW Timer 5 Interrupt Enable This bit sets the masking of the Timer 5 interrupt Value Name Description 0 DISABLED Disable Timer 5 interrupts 1 ENABLED Enable interrupt requests generated by the TF5L or TF5H flags 4 ET4 0 RW Timer 4 Interrupt Enable This bit sets the masking of the Timer 4 interrupt Value Name Description 0 DISABLED Disable Timer 4interrupts 1 ENABLED Enable interrupt requests generated by the TF4L or TF4H flags 3 ESMB1 0 RW SMBus1 Interrupt Enable This bit sets the masking of the SMB1 interrupt Value Name Description 0 DISABLED Disable all SMB1 interrupts 1 ENABLED Enable interrupt requests generated by 5 1 2 Reserved Must write reset value 1 ES1 0 RW UART1 Interrupt Enable This bit sets the masking of the UART1 interrupt Value Name Description 0 DISABLED Disable UART1 inte
233. ff chip only 4 Set up timing to interface with off chip memory or peripherals 15 3 2 Port I O Configuration When the External Memory Interface is used for off chip access the associated port pins are shared between the EMIF and the GPIO port latches The Crossbar should be configured not to assign any signals to the associated port pins In most configurations the RDb WRb and ALEm pins need to be skipped in the Crossbar to ensure they are controlled by their port latches The External Memory Interface claims the associated port pins for memory operations only during the execution of an off chip MOVX instruction Once the MOVX instruction has completed control of the Port pins reverts to the Port latches The Port latches should be explicitly configured to park the External Memory Interface pins in a dormant state most commonly by setting them to a logic 1 During the execution of the MOVX instruction the External Memory Interface will explicitly disable the drivers on all port pins that are acting as inputs Data 7 0 during a Read operation for example For port pins acting as outputs Data 7 0 during a Write operation for example the External Memory Interface will not automatically enable the output driver The output mode whether the pin is config ured as open drain or push pull of bi directional and output only pins should be configured to the desired mode when the pin is being used as an output The output mode of the port pi
234. g it as a reset source Value Name Description 0 DISABLED Supply Monitor Disabled 1 ENABLED Supply Monitor Enabled 6 VDDSTAT Varies R Supply Status This bit indicates the current power supply status Supply monitor output Value Name Description 0 BELOW Vpp is at or below the supply monitor threshold 1 ABOVE Vpp is above the supply monitor threshold 5 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Rev 0 2 67 EFM8UB2 Reference Manual CIP 51 Microcontroller Core 10 CIP 51 Microcontroller Core 10 1 Introduction The CIP 51 microcontroller core is a high speed pipelined 8 bit core utilizing the standard MCS 51 instruction set Any standard 803x 805x assemblers and compilers can be used to develop software The MCU family has a superset of all the peripherals included with a standard 8051 The CIP 51 includes on chip debug hardware and interfaces directly with the analog and digital subsystems pro viding a complete data acquisition or control system solution DATA BUS i amp 8 ACCUMULATOR e B REGISTER STAC
235. g the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 192 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 5 CLKREC USBO Clock Recovery Control Bit 7 6 5 4 3 2 1 0 CRE CRSSEN CRLOW Reserved Access RW RW RW RW Reset 0 0 0 OxOF Indirect Address OxOF Bit Name Reset Access Description 7 CRE 0 RW Clock Recovery Enable This bit enables disables the USB clock recovery feature Value Name Description 0 DISABLED Disable clock recovery 1 ENABLED Enable clock recovery 6 CRSSEN 0 RW Clock Recovery Single Step This bit forces the oscillator calibration into single step mode during clock recovery Value Name Description 0 DISABLED Disable single step mode normal calibration mode 1 ENABLED Enable single step mode 5 CRLOW 0 RW Low Speed Clock Recovery Mode This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB device Value Name Description 0 FULL_SPEED Full Speed Mode 1 LOW_SPEED Low Speed Mode 4 0 Reserved Must write reset value This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 193 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 6 0 USBO Endpoint 0 FIFO Access Bit 7 6 4 1 0 FIFODATA Access RW Reset
236. gister and when an extra bit is enabled the RBX bit in the SCON1 register silabs com Smart Connected Energy friendly Rev 0 2 284 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Transmitting Data Data transmission is initiated when software writes a data byte to the SBUF1 register If XBE is set extra bit enable software should set up the desired extra bit in TBX prior to writing SBUF1 Data is transmitted LSB first from the TX pin The TI flag SCON1 is set at the end of the transmission at the beginning of the stop bit time If TI interrupts are enabled TI will trigger an interrupt Receiving Data To enable data reception firmware should write the REN bit to 1 Data reception begins when a start condition is recognized on the RX pin Data will be received at the selected baud rate through the end of the data phase Data will be transferred into the receive buffer under the following conditions There is room in the receive buffer for the data MCE is set to 1 and the stop bit is also 1 XBE 0 MCE is set to 1 and the extra bit is also 1 XBE 1 MCE is 0 stop or extra bit will be ignored In the event that there is not room in the receive buffer for the data the most recently received data will be lost The RI flag will be set any time that valid data has been pushed into the receive buffer If RI interrupts are enabled RI will trigger an interrupt Firmware may r
237. h auto reload Value Name Description 0 16 BIT RELOAD Timer 3 operates in 16 bit auto reload mode 1 8 BIT RELOAD Timer 3 operates as two 8 bit auto reload timers 2 TR3 0 RW Timer 3 Run Control Timer 3 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR3H only TMR3L is always enabled in split mode 1 T3CSS 0 RW Timer 3 Capture Source Select This bit selects the source of a capture event when bit TF3CEN is set to 1 Value Name Description 0 USB SOF CAPTURE Capture source is USB SOF event 1 LFOSC_CAPTURE Capture source is falling edge of Low Frequency Oscillator 0 T3XCLK 0 RW Timer 3 External Clock Select silabs com Smart Connected Energy friendly T3XCLK selects the external clock source for Timer 3 If Timer 3 is in 8 bit mode T3XCLK selects the external oscillator clock source for both timer bytes However the Timer 3 Clock Select bits T3MH and T3ML may still be used to select between the external clock and the system clock for either timer Value Name Description 0 SYSCLK_DIV_12 Timer 3 clock is the system clock divided by 12 Rev 0 2 269 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 Reset Access Description 1 EXTOSC_DIV_8 Timer clock is the external oscillator divided by 8 synchronized with SYSCLK 19 4 15 TMR3RLL Timer 3 Reload Low Byte Bit 7 6 4 0 TMR3RLL Access RW Reset 0x00
238. he completion of the next instruction 6 2 Interrupt Sources and Vectors The CIP51 core supports interrupt sources for each peripheral on the device Software can simulate an interrupt for many peripherals by setting any interrupt pending flag to logic 1 If interrupts are enabled for the flag an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt pending flag Refer to the data sheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s 6 2 1 Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels low or high A low priority interrupt service routine can be preempted by a high priority interrupt A high priority interrupt cannot be preempted Each interrupt has an associated interrupt priority bit in the IP and EIPn registers which are used to configure its priority level Low priority is the default If two interrupts are recognized simultaneously the interrupt with the higher priority is serviced first If both interrupts have the same priority level a fixed order is used to arbitrate based on the interrupt source s location in the interrupt vector table Interrupts with a lower number in the vector table have priority 6 2 2 Interrupt Latency Interrupt response time depends on the state of the CPU when the interru
239. hing resistors and configurable pull up resistors 1 KB FIFO block and clock recovery mechanism for crystal less operation No external components are required The USBO module is Universal Serial Bus Specification 2 0 compliant The USBO module includes the following features Full and Low Speed functionality Implements 4 bidirectional endpoints USB 2 0 compliant USB peripheral support no host capability Direct module access to 1 KB of RAM for FIFO memory Clock recovery to meet USB clocking requirements with no external components Universal Asynchronous Receiver Transmitter UARTO UARTO is an asynchronous full duplex serial port offering modes 1 and 3 of the standard 8051 UART Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates Received data buffering allows UARTO to start reception of a second incoming data byte before software has finished reading the previous data byte The UART module provides the following features Asynchronous transmissions and receptions Baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 8 or 9 bit data Automatic start and stop generation Universal Asynchronous Receiver Transmitter UART1 UART1 is an asynchronous full duplex serial port offering a variety of data formatting options A dedicated baud rate generator with 16 bit timer and selectable prescaler is included which can generate a wide range of baud rates A received
240. ifferent devices on the bus may operate at different voltage levels However the maximum voltage on any port pin must conform to the electrical characteristics specifications The bi direc tional SCL serial clock and SDA serial data lines must be connected to positive power supply voltage through pullup resistor or similar circuit Every device connected to the bus must have an open drain or open collector output for both the SCL and SDA lines so that both are pulled high recessive state when the bus is free The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns respectively VDD 5 V VDD 3 V VDD 5 V VDD 3 V Master SlaveDevice SlaveDevice Device 1 2 SDA SCL Figure 18 2 Typical SMBus System Connection Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave and multiple master devices on the same bus are supported If two or more masters attempt to initiate a data transfer simultaneously an arbitration scheme is employed with a single master always winning the arbitration It is not necessary to specify one device as the Master i
241. igh Byte Bit 7 6 5 4 3 2 1 0 Name THO Access RW Reset 0x00 SFR Page ALL SFR Address 0x8C Bit Name Reset Access Description 7 0 THO The THO register is the high byte of the 16 bit Timer 0 0x00 RW Timer 0 High Byte silabs com Smart Connected Energy friendly Rev 0 2 264 EFM8UB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 8 TH1 Timer 1 High Byte Bit 7 6 5 4 3 2 1 0 1 Access RW Reset 0x00 SFR Page ALL SFR Address 0x8D Bit Name Reset Access Description 7 0 TH1 0x00 RW Timer 1 High Byte 1 register is the high byte of the 16 bit Timer 1 silabs com Smart Connected Energy friendly Rev 0 2 265 EFM8UB2 Reference Manual Timers 0 Timer1 2 Timer3 Timer4 Timer5 19 4 9 TMR2CNO Timer 2 Control 0 Bit 7 6 5 4 3 2 1 0 2 TF2L TF2LEN TF2CEN T2SPLIT TR2 T2CSS T2XCLK Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page 0x0 SFR Address OxC8 bit addressable Bit Name Reset Access Description 7 TF2H 0 RW Timer 2 High Byte Overflow Flag Set by hardware when the Timer 2 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 2 overflows from OxFFFF to 0x0000 When the Timer 2 interrupt is enabled setting this bit causes the CPU to vector to the Timer 2 interru
242. imer 2 interrupt Value Name Description 0 DISABLED Disable Timer 2 interrupt 1 ENABLED Enable interrupt requests generated by the TF2L or TF2H flags 4 ESO 0 RW UARTO Interrupt Enable This bit sets the masking of the UARTO interrupt Value Name Description 0 DISABLED Disable UARTO interrupt 1 ENABLED Enable UARTO interrupt 3 ET1 0 RW Timer 1 Interrupt Enable This bit sets the masking of the Timer 1 interrupt Value Name Description 0 DISABLED Disable all Timer 1 interrupt 1 ENABLED Enable interrupt requests generated by the TF1 flag silabs com Smart Connected Energy friendly Rev 0 2 32 EFM8UB2 Reference Manual Interrupts Bit Name Reset Access Description 2 EX1 0 RW External Interrupt 1 Enable This bit sets the masking of External Interrupt 1 Value Name Description 0 DISABLED Disable external interrupt 1 1 ENABLED Enable interrupt requests generated by the INT1 input 1 ETO 0 RW Timer 0 Interrupt Enable This bit sets the masking of the Timer 0 interrupt Value Name Description 0 DISABLED Disable all Timer O interrupt 1 ENABLED Enable interrupt requests generated by the TFO flag 0 EXO 0 RW External Interrupt 0 Enable This bit sets the masking of External Interrupt O Value Name Description 0 DISABLED Disable external interrupt 0 1 ENABLED Enable interrupt requests generated by the INTO input silabs com Smart Connected Energy
243. imer 5 8 bit mode TMR5H contains the 8 bit high byte timer value silabs com Smart Connected Energy friendly Rev 0 2 277 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 0 UARTO 20 Universal Asynchronous Receiver Transmitter 0 UARTO 20 1 Introduction UARTO is an asynchronous full duplex serial port offering modes 1 and 3 of the standard 8051 UART Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates Received data buffering allows UARTO to start reception of a second incoming data byte before software has finished reading the previous data byte UARTO has two associated SFRs Serial Control Register 0 SCONO and Serial Data Buffer 0 SBUFO The single SBUFO location provides access to both transmit and receive registers Note Writes to SBUFO always access the transmit register Reads of SBUFO always access the buffered receive register it is not pos sible to read data from the transmit register With UARTO interrupts enabled an interrupt is generated each time transmit is completed is set SCONO or a data byte has been received RI is set in SCONO The UARTO interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UARTO interrupt transmit complete or receive complete TB8 TI RI 9 bit
244. imer5 19 3 Functional Description 19 3 1 System Connections All four timers are capable of clocking other peripherals and triggering events in the system The individual peripherals select which timer to use for their respective functions Note that the Timer 2 and Timer 3 high overflows apply to the full timer when operating in 16 bit mode or the high byte timer when operating in 8 bit split mode Table 19 2 Timer Peripheral Clocking Event Triggering Function TO Over 1 Over T2High T2Low T3High T4High T4Low T5High 5 Low flow flow Overflow Overflow Overflow Overflow Overflow Overflow Overflow Overflow UARTO Baud Rate Yes SMBus 0 Clock Rate Yes Yes Yes Yes Master SMBus 0 SCL Low Yes Timeout SMBus 1 Clock Rate Yes Yes Yes Yes Master SMBus 1 SCL Low Yes Timeout PCAO Clock Yes ADCO Conversion Yes Yes Yes Yes Yes Yes Yes Yes Yes Start Notes 1 The high side overflow is used when the timer is in 16 bit mode The low side overflow is used 8 bit mode 19 3 2 Timer 0 and Timer 1 Timer 0 and Timer 1 are each implemented as a 16 bit register accessed as two separate bytes a low byte TLO or TL1 and a high byte THO or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate status Timer 0 interrupts can be enabled by setting the ETO bit in the IE register Timer 1 inte
245. indirect RAM toA 2 2 ADD A data Add immediate to A 2 2 ADDC A Rn Add register to A with carry 1 1 ADDC A direct Add direct byte to A with carry 2 2 ADDC A Ri Add indirect RAM to A with carry 2 2 ADDC A data Add immediate to A with carry 2 2 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 2 SUBB A Ri Subtract indirect RAM from A with borrow 2 2 SUBB A data Subtract immediate from A with borrow 2 2 INCA Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC Ri Increment indirect RAM 2 2 DECA Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Ri Decrement indirect RAM 2 2 INC DPTR Increment Data Pointer 1 1 silabs com Smart Connected Energy friendly Rev 0 2 70 EFM8UB2 Reference Manual CIP 51 Microcontroller Core Mnemonic Description Clock Cycles prefetch on prefetch on SYSCLK 12 SYSCLK 48 MHz MHz FLRT 0 FLRT 1 MUL AB Multiply A and B 1 4 4 DIV AB Divide A by B 1 8 8 DAA Decimal adjust A 1 1 1 Logical Operations ANL A Rn AND Register to A 1 1 1 ANL A direct AND direct byte to A 2 2 2 ANL A Ri AND indirect RAM to A 1 2 2 ANL A data AND immediate to A 2 2 2 ANL direct A AND A to direct byte 2 2 2 ANL direct data AND immediate to di
246. int has been configured for ISO IN mode the host will send one IN token data request per frame the location of data within each frame may vary Because of this it is recommended that double buffering be enabled for ISO IN endpoints Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO Note that if double buffering is enabled for the target endpoint it is possible for firmware to load two packets into the IN FIFO at a time In this case hardware will reset IN PRDY to 0 immediately after firmware loads the first packet into the FIFO and sets INPRDY to 1 An interrupt will not be generated in this case an interrupt will only be generated when a data packet is transmitted If there is not a data packet ready in the endpoint FIFO when USBO receives an IN token from the host USBO will transmit a zero length data packet and set the UNDRUN bit to 1 The ISO Update feature can be useful in starting a double buffered ISO IN endpoint If the host has already set up the ISO IN pipe has begun transmitting IN tokens when firmware writes the first data packet to the endpoint FIFO the next IN token may arrive and the first data packet sent before firmware has written the second double buffered data packet to the FIFO The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame the packet will only be sent after a SOF signal has been received
247. ints1 3 OUT Interrupt Flags CMINT 0x06 Common USB Interrupt Flags IN1IE 0x07 EndpointO Endpoints1 3 IN Interrupt Enables OUT1IE 0x09 Endpoints1 3 OUT Interrupt Enables CMIE 0x0B Common USB Interrupt Enables Common Registers FADDR 0x00 Function Address POWER 0x01 Power Management silabs com Smart Connected Energy friendly Rev 0 2 182 EFM8UB2 Reference Manual Universal Serial Bus 05 0 USB Register Name USB Register Address Description FRAMEL OxOC Frame Number Low Byte FRAMEH 0x0D Frame Number High Byte INDEX OxOE Endpoint Index Selection CLKREC OxOF Clock Recovery Control EENABLE Ox1E Endpoint Enable FIFOn 0 20 0 23 Endpoints0 3 FIFOs Indexed Registers EOCSR 0x11 EndpointO Control Status EINCSRL Endpoint IN Control Status Low Byte EINCSRH 0x12 Endpoint IN Control Status High Byte EOUTCSRL 0x14 Endpoint OUT Control Status Low Byte EOUTCSRH 0x15 Endpoint OUT Control Status High Byte 0x16 Number of Received Bytes EndpointO FIFO EOUTCNTL Endpoint OUT Packet Count Low Byte EOUTCNTH 0x17 Endpoint OUT Packet Count High Byte silabs com Smart Connected Energy friendly Rev 0 2 183 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 3 6 FIFO Management 1024 bytes of on chip XRAM are used as FIFO space for the USB block This FIFO space is split between Endpoints0 3 Endpoint is 6
248. ion is selected by the DIRSEL bit in register EINCSRH Endpoints 1 3 can be disabled individually by the corresponding bits in the ENABLE register When an Endpoint is disabled it will not respond to bus traffic or stall the bus All Endpoints are enabled by default Endpoint 1 3 IN General Control Endpoints 1 3 IN are managed via USB registers EINCSRL and EINCSRH All IN endpoints can be used for Interrupt Bulk or Isochro nous transfers Isochronous ISO mode is enabled by writing 1 to the ISO bit in register EINCSRH Bulk and Interrupt transfers are handled identically by hardware An Endpoint 1 3 IN interrupt is generated by any of the following conditions An IN packet is successfully transferred to the host Software writes 1 to the FLUSH bit when the target FIFO is not empty Hardware generates a STALL condition Operating Endpoints 1 3 as IN Interrupt or Bulk Endpoints When the ISO bit 0 the target endpoint operates in Bulk or Interrupt Mode Once an endpoint has been configured to operate in Bulk Interrupt IN mode typically following an EndpointO SET INTERFACE command firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit Upon reception of an IN token hardware will transmit the data clear the INPRDY bit and generate an interrupt Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero length packet to be transmitted upon reception of the next IN token A Bulk or In
249. iption 4 3 1 Security Options The CIP 51 provides security options to protect the flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants The Program Store Write Enable bit PSWE in register PSCTL and the Program Store Erase Enable bit PSEE in register PSCTL bits protect the flash memory from accidental modification by software PSWE must be explicitly set to 1 before software can modify the flash memory both PSWE and PSEE must be set to 1 before software can erase flash memory Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface A Security Lock Byte located in flash user space offers protection of the flash program memory from access reads writes or erases by unprotected code or the C2 interface See the specific device memory map for the location of the security byte The flash security mechanism allows the user to lock n flash pages starting at page 0 where n is the 1s complement number represented by the Security Lock Byte Note The page containing the flash Security Lock Byte is unlocked when no other flash pages are locked all bits of the Lock Byte are 1 and locked when any other flash pages are locked any bit of the Lock Byte is 0 Table 4 1 Security Byte Decoding Security Lock Byte 111111101b 1s Complement 00000010b Flash Pages Locked 3 First two flash pag
250. is enabled or not silabs com Smart Connected Energy friendly Rev 0 2 231 EFM8UB2 Reference Manual System Management Bus I2C SMBO and SMB1 Master Write Sequence During a write sequence an SMBus master writes data to a slave device The master in this transfer will be a transmitter during the address byte and a transmitter during all data bytes The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 0 WRITE master then transmits one or more bytes of serial data After each byte is transmitted an acknowledge bit is generated by the slave The transfer is ended when the STO bit is set and a STOP is generated The interface will switch to Master Receiver Mode if SMBODAT is not written following a Master Transmitter interrupt Figure 18 5 Typical Master Write Sequence on page 232 shows a typical master write sequence as it appears on the bus and Figure 18 6 Master Write Sequence State Diagram EHACK 1 on page 233 shows the corresponding firmware state machine Two transmit data bytes are shown though any number of bytes may be transmitted Notice that all of the data byte transferred interrupts occur after the ACK cycle in this mode regardless of whether hardware ACK generation is enabled Interrupts with Hardware ACK Enabled EHACK 1 2 Data Byte Data
251. it in the FLSCL register has been set appropriately to ensure proper flash read timing silabs com Smart Connected Energy friendly Rev 0 2 56 EFM8UB2 Reference Manual Clocking and Oscillators 8 4 2 HFOOCAL High Frequency Oscillator Calibration Bit 7 6 5 4 3 2 1 0 Reserved OSCICL Access R RW Reset 0 Varies SFR Page ALL SFR Address 0xB3 Bit Name Reset Access Description 7 Reserved Must write reset value 6 0 OSCICL Varies RW Internal Oscillator Calibration These bits determine the internal oscillator period When set to 0000000b the oscillator operates at its fastest setting When set to 1111111b the oscillator operates at its slowest setting The reset value is factory calibrated to generate an internal oscillator frequency of 48 MHz OSCICL should only be changed by firmware when the oscillator is disabled IO SCEN 0 The contents of this register are undefined when USB clock recovery is enabled silabs com Smart Connected Energy friendly Rev 0 2 57 EFM8UB2 Reference Manual Clocking and Oscillators 8 4 3 HFOOCN High Frequency Oscillator Control Bit 7 6 5 4 3 2 1 0 IOSCEN IFRDY SUSPEND Reserved IFCN Access RW R RW R RW Reset 1 1 0 0x0 0x0 SFR Page ALL SFR Address 0xB2 Bit Name Reset Access Description 7 IOSCEN 1 RW Oscillator Enable Value Name Description
252. jump if not zero 2 20r4 2or5 DJNZ direct rel Decrement direct byte and jump if not zero 3 30r5 3 or7 NOP No operation silabs com Smart Connected Energy friendly Rev 0 2 73 EFM8UB2 Reference Manual CIP 51 Microcontroller Core Mnemonic Description Clock Cycles prefetch on prefetch on SYSCLK 12 SYSCLK 48 MHz MHz FLRT 0 FLRT 1 Notes Rn Register RO R7 of the currently selected register bank QRi Data RAM location addressed indirectly through RO or R1 rel 8 bit signed twos complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be a direct access Data RAM location 0x00 0x7F or an SFR 0 80 OxFF e data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2 KB page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP The destination may be anywhere within the 8 KB program memory space There is one unused opcode 0xA5 that performs the same function as All mnemonics copyrighted Intel Corporation 1980 10 4 CPU Core Registers 10 4 1 DPL Data Pointer Low Bit 7 6 5 4 3 2 1 0 DPL A
253. l If a crystal or ceramic resonator is used as the external oscillator the crystal resonator and a 10 resistor must be wired across the XTAL1 and XTAL2 pins Appropriate loading capacitors should be added to XTAL1 and XTAL2 and both pins should be configured for analog I O with the digital output drivers disabled The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation These capacitors are in series as seen by the crystal and in parallel with the stray capacitance of the XTAL1 and XTAL2 pins Note The recommended load capacitance depends upon the crystal and the manufacturer Refer to the crystal data sheet when com pleting these calculations The equation for determining the load capacitance for two capacitors is as follows Ca C tC L C Cp S Figure 8 2 External Oscillator Load Capacitance Where CA and Cg are the capacitors connected to the crystal leads Cg is the total stray capacitance of the PCB The stray capacitance for a typical layout where the crystal is as close as possible to the pins is 2 5 pF per pin If Ca and Cg are the same C then the equation becomes the following C Pp ts Figure 8 3 External Oscillator Load Capacitance with Equal Capacitors For example a tuning fork crystal of 25 MHz has a recommended load capacitance of 12 5 pF With a stray capacitance of 3 pF per pin 6 pF tot
254. l ure that is only recoverable by re flashing the code in the device To help prevent the accidental modification of flash by firmware hardware restricts flash writes and erasures when the supply monitor is not active and selected as a reset source As the monitor is enabled and selected as a reset source by default it is recommended that systems writing or erasing flash simply maintain the default state The following sections provide general guidelines for any system which contains routines which write or erase flash from code Addi tional flash recommendations and example code can be found in AN201 Writing to Flash From Firmware available from the Silicon Laboratories website Voltage Supply Maintenance and the Supply Monitor If the system power supply is subject to voltage or current spikes add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded Make certain that the minimum supply rise time specification is met If the system cannot meet this rise time specification then add an external supply brownout circuit to the RSTb pin of the device that holds the device in reset until the voltage supply reaches the lower limit and re asserts RSTb if the supply drops below the low supply limit Do not disable the supply monitor If the supply monitor must be disabled in the system firmware should be added to the startup routine to ena
255. l Voltage Reference An external reference may be applied to the VREF pin Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference If the manufacturer does not provide recommendations a 4 7 pF in parallel with a 0 1 uF capacitor is recommended Note The VREF pin is a multi function GPIO pin When using an external voltage reference VREF should be configured as an analog input and skipped by the crossbar silabs com Smart Connected Energy friendly Rev 0 2 111 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 3 3 Input Selection The ADC has analog multiplexers which allow selection of external pins the on chip temperature sensor the internal regulated supply VREF the VDD supply or GND for the positive and negative inputs ADC input channels are selected using the AMXOP and AMXON registers Note Any port pins selected as ADC inputs should be configured as analog inputs in their associated port configuration register and configured to be skipped by the crossbar 12 3 3 1 Multiplexer Channel Selection Table 12 1 ADCO Positive Input Multiplexer Channels AMXOP setting Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name 000000 ADCOP 0 P2 0 P1 0 P1 0 000001 ADCOP 1 P2 1 P1 1 P1 1 000010 ADCOP 2 P2 2 P1 2 P1 2 000011 ADCOP 3 P2 3 P1 3 P1 3 000100 ADCOP 4 P2 5 P1 4 P1 4 000
256. labs com Smart Connected Energy friendly Rev 0 2 290 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 4 6 SBRLL1 UART1 Baud Rate Generator Low Byte Bit 7 6 5 4 3 2 1 0 BRL Access RW Reset 0x00 SFR Page ALL SFR Address 0xB4 Bit Name Reset Access Description 7 0 BRL 0x00 RW UART1 Baud Rate Reload Low This field is the low byte of the 16 bit UART1 baud rate generator The high byte of the baud rate generator should be writ ten first then the low byte The baud rate is determined by the following equation Baud Rate SYSCLK 65536 BRH1 BRL1 1 2 1 Prescaler silabs com Smart Connected Energy friendly Rev 0 2 291 EFM8UB2 Reference Manual C2 Debug and Programming Interface 22 C2 Debug and Programming Interface 22 1 Introduction The device includes an on chip Silicon Labs 2 Wire C2 debug interface that allows flash programming and in system debugging with the production part installed in the end application The C2 interface uses a clock signal C2CK and a bi directional C2 data signal C2D to transfer information between the device and a host system Details on the C2 protocol can be found in the C2 Interface Speci fication 22 2 Features The C2 interface provides the following features In system device programming and debugging Non intrusive no firmware or hardware peripheral resources re
257. lag ADWINT 1 EUSBO 0 RW USB USBO Interrupt Enable This bit sets the masking of the USBO interrupt Value Name Description 0 DISABLED Disable all USBO interrupts 1 ENABLED Enable interrupt requests generated by USBO 0 ESMBO 0 RW SMBus 5 0 Interrupt Enable This bit sets the masking of the SMBO interrupt Value Name Description 0 DISABLED Disable all SMBO interrupts 1 ENABLED Enable interrupt requests generated by SMBO silabs com Smart Connected Energy friendly Rev 0 2 37 EFM8UB2 Reference Manual Interrupts 6 3 4 EIP1 Extended Interrupt Priority 1 Bit 7 6 5 4 3 2 1 0 1 PADCO PWADCO PUSBO PSMBO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address OxF6 Bit Name Reset Access Description 7 PT3 0 RW Timer 3 Interrupt Priority Control This bit sets the priority of the Timer 3 interrupt Value Name Description 0 LOW Timer 3 interrupts set to low priority level 1 HIGH Timer 3 interrupts set to high priority level 6 1 0 RW Comparator1 1 Interrupt Priority Control This bit sets the priority of the CP1 interrupt Value Name Description 0 LOW CP1 interrupt set to low priority level 1 HIGH CP1 interrupt set to high priority level 5 PCPO 0 RW Comparator0 Interrupt Priority Control Thi
258. lation frequency and the required XFCN field value determined by the following equation where f is the frequency in MHz C is the capacitor value on XTAL2 in pF and Vpp is the power supply voltage in Volts _ C x Vpp Figure 8 9 C Mode Oscillator Frequency For example assume VDD 3 0 V and f 150 kHz Since a frequency of roughly 150 kHz is desired select the K Factor from as KF 22 TE C x Vpp 22 22 C 9350 MHz x 3 0 C 48 8 pF Figure 8 10 C Mode Oscillator Example Therefore the XFCN value to use in this example is 011 and C is approximately 50 pF The recommended startup procedure for C mode is the same as RC mode silabs com Smart Connected Energy friendly Rev 0 2 54 EFM8UB2 Reference Manual Clocking and Oscillators Recommended XFCN Settings for RC and C Modes Table 8 2 Recommended XFCN Settings for RC and C Modes XFCN Field Setting Approximate Frequency K Factor C Mode Actual Measured Frequency Range C Mode 000 f lt 25 kHz K Factor 0 87 f 11 kHz C 33 pF 001 25 kHz lt f lt 50 kHz K Factor 2 6 f 33 kHz C 33 pF 010 50 kHz f s 100 kHz K Factor 7 7 7 f 98 kHz C 33 pF 011 100 kHz lt 200 kHz K Factor 22 f 270 kHz C 33 pF 100 200 kHz f 400 kHz K Factor 65 f 310 kHz C 46 pF 101 400 kHz lt 800 kHz K Factor 180 f 890 kHz C 46 pF 110 800 kHz lt f lt 1 6 MHz K Factor 664 f 2 0 MHz C 46 pF
259. le for firmware to read the logic state of any digital I O pin as signed to a crossbar peripheral but the output state cannot be directly modified Figure 11 3 Crossbar Priority Decoder Example Assignments on page 82 shows an example of the resulting pin assignments of the device with UARTO and SPIO enabled and P0 3 skipped POSKIP 0x08 UARTO is the highest priority and it will be assigned first The UARTO pins can only appear at fixed locations in this example P0 4 and 0 5 so it occupies those pins The next highest bled peripheral is SPIO P0 0 P0 1 and P0 2 are free so SPIO takes these three pins The fourth pin NSS is routed to P0 6 because 0 3 is skipped 0 4 and 0 5 are already occupied by the UART Any other pins on the device are available for use as general purpose digital I O or analog functions in number 312 T5 4 T8 T8 7 UARTO TX UARTO RX SPIO SCK SPIO MISO SPIO MOSI SPIO NSS 0 0 0 10000 Pin Skip Settings POSKIP UARTO is assigned to fixed pins and has priority over SPIO SPIO is assigned to available un skipped pins Port pins assigned to the associated peripheral P0 3 is skipped by setting POSKIP 3 to 1 Figure 11 3 Crossbar Priority Decoder Example Assignments silabs com Smart Connected Energy friendly Rev 0 2 82 EFM8UB2 Reference Manual 11 3 3 1 Crossbar Functional Map The figure below shows
260. le to electrical interference and is sensitive to layout and to changes in temperature If the system is operating in an electrically noisy environment use the internal oscillator or use an external CMOS clock If operating from the external oscillator switch to the internal oscillator during flash write or erase operations The external oscillator can continue to run and the CPU can switch back to the external oscillator after the flash operation has completed 4 4 Flash Control Registers 4 4 1 PSCTL Program Store Control Bit 7 6 5 4 3 2 1 0 Reserved PSEE PSWE Access R RW RW Reset 0x00 0 0 SFR Page ALL SFR Address 0 8 Bit Name Reset Access Description 7 2 Reserved Must write reset value 1 PSEE 0 RW Program Store Erase Enable Setting this bit in combination with PSWE allows an entire page of flash program memory to be erased If this bit is logic 1 and flash writes are enabled PSWE is logic 1 a write to flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction The value of the data byte written does not matter Value Name Description 0 ERASE DISABLED Flash program memory erasure disabled 1 ERASE ENABLED Flash program memory erasure enabled 0 PSWE 0 RW Program Store Write Enable Setting this bit allows writing a byte of data to the flash program memory using the MOVX write instruction The flash loc
261. ll be serviced upon waking the device If suspend mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins program execution at address 0x0000 7 6 Shutdown Mode In shutdown mode the CPU is halted and the internal LDO is powered down External I O will retain their configured states To enter Shutdown mode firmware should set the STOPCF bit in the regulator control register to 1 and then set the STOP bit in PCONO In Shutdown the RSTb pin and a full power cycle of the device are the only methods of generating a reset and waking the device Note In Shutdown mode all internal device circuitry is powered down and no RAM nor registers are retained The debug circuitry will not be able to connect to a device while it is in Shutdown Coming out of Shutdown mode whether by POR or pin reset will appear as a power on reset of the device silabs com Smart Connected Energy friendly Rev 0 2 44 EFM8UB2 Reference Manual Power Management and Internal Regulators 7 7 5V to 3 3V Regulator The 5 to 3 3 V regulator is powered from the VREGIN pin on the device When active it regulates the input voltage to 3 3 V at the VDD pin providing up to 100 mA for the device and system In addition to the normal mode of operation the regulator has two low power modes which may be used to reduce the supply current and may be disabled when not in use Table 7 2 Voltage Regulator Operational Modes
262. lock defined by TMR5CN 1 SYSCLK Timer 5 low byte uses the system clock 1 T4MH 0 RW Timer 4 High Byte Clock Select Selects the clock supplied to the Timer 4 high byte split 8 bit timer mode only Value Name Description 0 EXTERNAL_CLOCK Timer 4 high byte uses the clock defined by T4XCLK in TMR4CNO 1 SYSCLK Timer 4 high byte uses the system clock 0 T4ML 0 RW Timer 4 Low Byte Clock Select Selects the clock supplied to Timer 4 If Timer 4 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer Value Name Description 0 EXTERNAL_CLOCK Timer 4 low byte uses the clock defined by in TMRACNO 1 SYSCLK Timer 4 low byte uses the system clock silabs com Smart Connected Energy friendly Rev 0 2 263 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 5 TLO Timer 0 Low Byte Bit 7 6 5 4 3 2 1 0 Name TLO Access RW Reset 0x00 SFR Page ALL SFR Address 0x8A Bit Name Reset Access Description 7 0 TLO 0x00 RW Timer 0 Low Byte The TLO register is the low byte of the 16 bit Timer 0 19 4 6 TL1 Timer 1 Low Byte Bit 7 6 5 4 3 2 1 0 TL1 Access RW Reset 0x00 SFR Page ALL SFR Address 0x8B Bit Name Reset Access Description 7 0 TL1 0x00 RW Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 19 4 7 THO Timer 0 H
263. lue Name Description 0 DISABLED SYSCLK unavailable at Port pin 1 ENABLED SYSCLK output routed to Port pin 2 SMBOE 0 RW SMBO I O Enable Value Name Description 0 DISABLED SMBus 01 unavailable at Port pins 1 ENABLED SMBus 0 I O routed to Port pins 1 SPIOE 0 RW SPI I O Enable silabs com Smart Connected Energy friendly Rev 0 2 85 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts Bit Name Reset Access Description Value Name Description 0 DISABLED SPI I O unavailable at Port pins 1 ENABLED SPI I O routed to Port pins The SPI can be assigned either 3 or 4 GPIO pins 0 URTOE 0 RW UARTO I O Output Enable Value Name Description 0 DISABLED UARTO I O unavailable at Port pin 1 ENABLED UARTO TX RX routed to Port pins P0 4 and 0 5 silabs com Smart Connected Energy friendly Rev 0 2 86 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 2 XBR1 Port I O Crossbar 1 Bit 7 6 5 4 3 1 0 WEAKPUD XBARE T1E TOE ECIE PCAOME Access RW RW RW RW RW RW Reset 0 0 0 0 0 0x0 SFR Page ALL SFR Address 0xE2 Bit Name Reset Access Description 7 WEAKPUD 0 RW Port I O Weak Pullup Disable Value Name Description 0 PULL UPS ENABLED Weak Pullups enabled except for Ports whose I O are configured for analog mode 1 PULL UPS DIS
264. mA When the crystal oscillator is first enabled the external oscillator valid detector allows software to determine when the external system clock has stabilized Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior The recommended procedure for starting the crystal is as follows 1 Configure XTAL1 and XTAL2 for analog and disable the digital output drivers 2 Disable the XTAL1 and XTAL2 digital output drivers by writing 1 s to the appropriate bits in the port latch register 3 Configure and enable the external oscillator 4 Wait at least 1 ms 5 Poll for XCLKVLD set 1 6 Switch the system clock to the external oscillator silabs com Smart Connected Energy friendly Rev 0 2 52 EFM8UB2 Reference Manual Clocking and Oscillators 8 3 5 External RC and C Modes External RC Example An RC network connected to the XTAL2 pin can be used as a basic oscillator XTAL1 is not affected in RC mode VDD XTAL1 XTAL2 i Figure 8 5 External RC Oscillator Configuration The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasit ic capacitance in the PCB layout To determine the required XFCN field value first select the RC network value to produce the desired frequency of oscillation according to where f the frequency of oscillation in MHz C the capacitor
265. machine operation 18 5 3 SMBOADR SMBus 0 Slave Address Bit 7 6 5 4 3 2 1 0 SLV GC Access RW RW Reset 0x00 0 SFR Page 0x0 SFR Address OxCF Bit Name Reset Access Description 7 1 SLV 0x00 RW SMBus Hardware Slave Address Defines the SMBus Slave Address es for automatic hardware acknowledgement Only address bits which a 1 in the corresponding bit position in SLVM are checked against the incoming address This allows multiple addresses to be recog nized 0 GC 0 RW General Call Address Enable When hardware address recognition is enabled EHACK 1 this bit will determine whether the General Call Address 0x00 is also recognized by hardware Value Name Description 0 IGNORED General Call Address is ignored 1 RECOGNIZED General Call Address is recognized silabs com Smart Connected Energy friendly Rev 0 2 242 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 18 5 4 SMBOADM SMBus 0 Slave Address Mask Bit 7 6 5 4 3 2 1 0 SLVM EHACK Access RW RW Reset Ox7F 0 SFR Page 0x0 SFR Address OxCE Bit Name Reset Access Description 7 1 SLVM Ox7F RW SMBus Slave Address Mask Defines which bits of register SMBOADR are compared with an incoming address byte and which bits are ignored Any bit set to 1 in SLVM enables comparisons with the corresponding bit in SLV Bits set to 0 are ignored can
266. mes up running from the 48 MHz oscillator divided by 4 then divided by 8 1 5 MHz Provides clock to core and peripherals 48 MHz internal oscillator HFOSCO accurate to 1 5 over supply and temperature corners accurate to 0 25 when using USB clock recovery 80 kHz low frequency oscillator LFOSCO External RC CMOS and high frequency crystal clock options EXTCLK for QFP48 packages External CMOS clock option EXTCLK for QFP32 and QFN32 packages Internal oscillator has clock divider with eight settings for flexible clock scaling 1 2 4 or 8 silabs com Smart Connected Energy friendly Rev 0 2 2 EFM8UB2 Reference Manual System Overview 1 5 Counters Timers and PWM Programmable Counter Array 0 The programmable counter array PCA provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter timers The PCA consists of a dedicated 16 bit counter timer and one 16 bit capture compare mod ule for each channel The counter timer is driven by a programmable timebase that has flexible external and internal clocking options Each capture compare module may be configured to operate independently in one of five modes Edge Triggered Capture Software Timer High Speed Output Frequency Output or Pulse Width Modulated PWM Output Each capture compare module has its own associated I O line CEXn which is routed through the crossbar
267. mpare Enable Interrupt Flag PCA Clock gt gt Figure 14 3 PCA Software Timer Mode Diagram silabs com Smart Connected Energy friendly Rev 0 2 141 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 3 6 High Speed Output Mode In High Speed Output mode a module s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module s 16 bit capture compare register and PCAOCPLn When a match occurs the capture compare flag CCFn in PCAOCNO is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not auto matically cleared by hardware when the CPU vectors to the interrupt service routine It must be cleared by software Setting the TOGn MATn and bits in the PCAOCPMn register enables the High Speed Output mode If ECOMn is cleared the associated retains its state and not toggle on the next match event Note When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the bit to 0 writing to PCAOCPHn sets ECOMn to 1 PCAOCPLn PCAOCPHn MATn Match Enable match gt CCFn Interrupt Flag ECOMn Compare Enable X CEXn PCA Clock t TOGn Toggle Enable Figure 14 4 PCA High Speed Output Mode Diagram silabs com Smart Connected Energy friendly
268. mum packet size is halved and the FIFO may contain two packets at a time This mode is available for Endpoints1 3 When an endpoint is configured for Split Mode dou ble buffering may be enabled for the IN Endpoint and or the OUT endpoint When split mode is not enabled double buffering may be enabled for the entire endpoint FIFO Table 16 3 FIFO Configuration Endpoint Number Split Mode Enabled Maximum IN Packet Size Maximum OUT Packet Size Single Buffer Double Buffer Single Buffer Double Buffer 0 n a 64 1 N 128 64 Y 64 32 64 32 2 N 256 128 Y 128 64 128 64 3 N 512 256 Y 256 128 256 128 FIFO Access Each endpoint is accessed through corresponding FIFOn register read of an endpoint FIFOn register unloads one byte from the FIFO write of an endpoint FIFOn register loads one byte into the endpoint FIFO When an endpoint FIFO is configured for Split Mode a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO Accessing the Unused FIFO Memory Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary The FIFO block operates on the USB clock domain thus the USB clock must be active when accessing FIFO space Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing USB FIFO space To access
269. n TMOD 0x89 ALL Timer 0 1 Mode TMR2CNO OxC8 0 00 Timer 2 Control 0 2 OxCD 0x00 Timer 2 High Byte TMR2L OxCC 0x00 Timer 2 Low Byte TMR2RLH OxCB 0x00 Timer 2 Reload High Byte TMR2RLL OxCA 0x00 Timer 2 Reload Low Byte TMR3CNO 0x91 0x00 Timer 3 Control 0 TMR3H 0x95 0x00 Timer 3 High Byte TMR3L 0x94 0x00 Timer 3 Low Byte TMR3RLH 0x93 0x00 Timer 3 Reload High Byte TMR3RLL 0x92 0x00 Timer 3 Reload Low Byte TMR4CNO 0x91 OxOF Timer 4 Control 0 0 95 OxOF Timer 4 High Byte TMR4L 0x94 OxOF Timer 4 Low Byte TMRARLH 0x93 OxOF Timer 4 Reload High Byte TMR4RLL 0x92 OxOF Timer 4 Reload Low Byte TMR5CNO OxC8 OxOF Timer 5 Control 0 TMR5H OxCD OxOF Timer 5 High Byte TMR5L OxCC OxOF Timer 5 Low Byte TMR5RLH OxCB OxOF Timer 5 Reload High Byte TMR5RLL OxCA OxOF Timer 5 Reload Low Byte USBOADR 0x96 ALL USBO Indirect Address USBODAT 0x97 ALL USBO Data USBOXCN OxD7 ALL USBO Transceiver Control VDMOCN OxFF ALL Supply Monitor Control XBRO OxE1 ALL Port I O Crossbar 0 XBR1 OxE2 ALL Port I O Crossbar 1 XBR2 OxE3 ALL Port I O Crossbar 2 XOSCOCN OxB1 ALL External Oscillator Control silabs com Smart Connected Energy friendly Rev 0 2 18 EFM8UB2 Reference Manual Special Function Registers 3 3 SFR Access Control Registers 3 3 1 SFRPAGE SFR Page Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxBF Bit Reset Access Description
270. n 7 0 PCAOCPH 0x00 RW PCA Channel 4 Capture Module High Byte 4 The PCAOCPHA register holds the high byte MSB of the 16 bit capture module A write to this register will set the module s ECOM bit to a 1 Rev 0 2 160 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual External Memory Interface EMIFO 15 External Memory Interface EMIFO 15 1 Introduction The External Memory Interface EMIF enables access of off chip memories and memory mapped devices connected to the GPIO ports The external memory space may be accessed using the external move instruction MOVX with the target address specified in either 8 bit or 16 bit formats WRb RDb EMIF ALEm Timing Control EMIF_AD6 e e External RAM XRAM Bus Control EMIF EMIF A15 EMIF A14 8 Figure 15 1 EMIF Block Diagram 15 2 Features Supports multiplexed and non multiplexed memory access Four external memory modes Internal only Split mode without bank select Split mode with bank select External only Configurable ALE address latch enable timing Configurable address setup and hold times Configurable write and read pulse widths silabs com Smart Connected Energy friendly Rev 0 2 161 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 3 Functional Description 15 3 1 Overview The device
271. n a system any device who transmits a START and a slave address becomes the master for the duration of that transfer A typical SMBus transaction consists of a START condition followed by an address byte Bits7 1 7 bit slave address 0 R W direc tion bit one or more bytes of data and a STOP condition Bytes that are received by a master or slave are acknowledged with a low SDA during a high SCL see Figure 18 3 SMBus Transaction on page 226 If the receiving device does not ACK the transmit ting device will read a NACK not acknowledge which is a high SDA during a high SCL The direction bit R W occupies the least significant bit position of the address byte The direction bit is set to logic 1 to indicate a READ operation and cleared to logic 0 to indicate a WRITE operation All transactions are initiated by a master with one or more addressed slave devices as the target The master generates the START condition and then transmits the slave address and direction bit If the transaction is a WRITE operation from the master to the slave the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte For READ operations the slave transmits the data waiting for an ACK from the master at the end of each byte At the end of the data transfer the master gener ates a STOP condition to terminate the transaction and free the bus Figure 18 3 SMBus Transaction on page 226 illustrates a t
272. n register REGO1CN at any time to determine the current logic level of the VBUS signal If USB is selected as a reset source a system reset will be generated by activity on the VBUS pin silabs com Smart Connected Energy friendly Rev 0 2 181 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 3 5 Register Access Many of the USBO controller registers are accessed indirectly through two SFRs USBO Address USBOADR and USBO Data USBODAT The USBOADR register selects which USB register is targeted by reads writes of the USBODAT register Endpoint control status registers are accessed by first writing the USB register INDEX with the target endpoint number Once the target endpoint number is written to the INDEX register the control status registers associated with the target endpoint may be accessed USB Controller Special Function Registers Interrupt Registers Common Registers Register EndpointO Control Status Registers Endpoint1 Control Status Registers Endpoint2 Control Status Registers Endpoint3 Control Status Registers Figure 16 2 USB Indirect Register Access Note The USB clock must be active when accessing indirect USB registers Table 16 2 USB Indirect Registers USB Register Name USB Register Address Description Interrupt Registers 0 02 EndpointO Endpoints1 3 IN Interrupt Flags OUT1INT 0x04 Endpo
273. ne This bit is not automatically cleared by hardware and must be cleared by firmware silabs com Smart Connected Energy friendly Rev 0 2 148 EFM8UB2 Reference Manual Programmable Counter Array 14 4 2 PCAOMD PCA Mode Bit 7 6 5 4 3 2 1 0 CIDL WDTE WDLCK Reserved CPS ECF Access RW RW RW R RW RW Reset 0 1 0 0 0x0 0 SFR Page ALL SFR Address OxD9 Bit Name Reset Access Description 7 CIDL 0 RW PCA Counter Timer Idle Control Specifies PCA behavior when CPU is in Idle Mode Value Name Description 0 NORMAL PCA continues to function normally while the system controller is in Idle Mode 1 SUSPEND PCA operation is suspended while the system controller is in Idle Mode 6 WDTE 1 RW Watchdog Timer Enable If this bit is set PCA Module 4 is used as the watchdog timer Value Name Description 0 DISABLED Disable Watchdog Timer 1 ENABLED Enable PCA Module 4 as the Watchdog Timer 5 WDLCK 0 RW Watchdog Timer Lock This bit locks unlocks the Watchdog Timer Enable When WDLCK is set the Watchdog Timer may not be disabled until the next system reset Value Name Description 0 UNLOCKED Watchdog Timer Enable unlocked 1 LOCKED Watchdog Timer Enable locked 4 Reserved Must write reset value 3 1 CPS 0x0 RW PCA Counter Timer Pulse Select These bits select the timebase source for the PCA counter Value Name Description 0x0 SYSCLK
274. ns while controlled by the GPIO latch is unaffected by the External Memory Interface operation and re mains controlled by the PnMDOUT registers In most cases the output modes of all EMIF pins should be configured for push pull mode 15 3 2 1 EMIF Pin Mapping Table 15 1 Multiplexed EMIF Pin Mapping Multiplexed EMIF Sig Description QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name nal Name WRb Write Enable P1 7 Not Available Not Available RDb Read Enable P1 6 Not Available Not Available ALEm Address Latch Enable P1 3 Not Available Not Available ADOm Address Data Bit 0 P4 0 Not Available Not Available AD1m Address Data Bit 1 P4 1 Not Available Not Available AD2m Address Data Bit 2 P4 2 Not Available Not Available AD3m Address Data Bit 3 P4 3 Not Available Not Available AD4m Address Data Bit 4 P4 4 Not Available Not Available silabs com Smart Connected Energy friendly Rev 0 2 162 EFM8UB2 Reference Manual External Memory Interface EMIFO Multiplexed EMIF Sig nal Name Description QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name AD5m Address Data Bit 5 P4 5 Not Available Not Available AD6m Address Data Bit 6 P4 6 Not Available Not Available AD7m Address Data Bit 7 P4 7 Not Available Not Available A8m Address Bit 8 P3 0 Not Available Not Available A9m Address Bit 9 P3 1 Not Available Not Available A10m Address Bit 10 P3 2 Not Available Not Avail
275. nsidered free if SCL and SDA remain high for more than 10 SMBus clock source periods 1 0 SMBCS 0x0 RW SMBus Clock Source Selection This field selects the SMBus clock source which is used to generate the SMBus bit rate See the SMBus clock timing sec tion for additional details Value Name Description 0x0 TIMERO Timer 0 Overflow Ox1 TIMER5 Timer 5 Overflow 0 2 TIMER2 HIGH Timer 2 High Byte Overflow 0x3 TIMER2_LOW Timer 2 Low Byte Overflow silabs com Smart Connected Energy friendly Rev 0 2 244 EFM8UB2 Reference Manual System Management Bus 2 SMBO and SMB1 18 6 2 SMB1CNO SMBus 1 Control Bit 7 6 5 4 3 2 1 0 MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI Access R R RW RW R R RW RW Reset 0 0 0 0 0 0 0 0 SFR Page OxF SFR Address 0xCO bit addressable Bit Name Reset Access Description 7 MASTER 0 R SMBus Master Slave Indicator This read only bit indicates when the SMBus is operating as a master Value Name Description 0 SLAVE SMBus operating in slave mode 1 MASTER SMBus operating in master mode 6 TXMODE 0 R SMBus Transmit Mode Indicator This read only bit indicates when the SMBus is operating as a transmitter Value Name Description 0 RECEIVER SMBus in Receiver Mode 1 TRANSMITTER SMBus in Transmitter Mode 5 STA 0 RW SMBus Start Flag When reading STA a 1 indicates that a st
276. nterrupt generation Status information Optional hardware recognition of slave address and automatic acknowledgement of address data SMBus interrupts are generated for each data byte or slave address that is transferred When hardware acknowledgement is disabled the point at which the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver When a trans mitter i e sending address data receiving an ACK this interrupt is generated after the ACK cycle so that software may read the re ceived ACK value when receiving data i e receiving address data sending an ACK this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value If hardware acknowledgement is enabled these interrupts are always generated after the ACK cycle Interrupts are also generated to indicate the beginning of a transfer when a master START generated or the end of a transfer when a slave STOP detected Software should read the SMBOCNO register to find the cause of the SMBus interrupt silabs com Smart Connected Energy friendly Rev 0 2 227 EFM8UB2 Reference Manual System Management Bus 2 SMBO and 5 1 SMBus Configuration Register The SMBus Configuration register SMBOCF is used to enable the SMBus master and or slave modes select the SMBus clock source and select the SMBus timing and timeout options When the ENSMB bit is set the SMBus is enabled for all mast
277. o obtain other frequencies silabs com Smart Connected Energy friendly Rev 0 2 49 EFM8UB2 Reference Manual Clocking and Oscillators 8 3 3 LFOSCO 80 kHz Internal Oscillator LFOSCO is progammable low frequency oscillator factory calibrated to a nominal frequency of 80 kHz A dedicated divider at the oscillator output is capable of dividing the output clock by 1 2 4 or 8 using the OSCLD bits in the LFOOCN register The OSCLF bits can be used to coarsely adjust the oscillator s output frequency LFOSCO circuit requires very little start up time and may be selected as the system clock immediately following the register write which enables the oscillator Calibrating LFOSCO On chip calibration of the LFOSCO can be performed using a timer to capture the oscillator period when running from a known time base When a timer is configured for L F Oscillator capture mode a rising edge of the low frequency oscillator s output will cause capture event on the corresponding timer As a capture event occurs the current timer value is copied into the timer reload registers By recording the difference between two successive timer capture values the low frequency oscillator s period can be calculated The OSCLF bits can then be adjusted to produce the desired oscillator frequency silabs com Smart Connected Energy friendly Rev 0 2 50 EFM8UB2 Reference Manual Clocking and Oscillators 8 3 4 External Crysta
278. o set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 4 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is output on the CEX4 pin 8 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel 4 Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCF4 interrupt Value Name Description 0 DISABLED Disable CCF4 interrupts 1 ENABLED Enable a Capture Compare Flag interrupt request when is set silabs com Smart Connected Energy friendly Rev 0 2 159 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 4 18 PCAOCPL4 PCA Channel 4 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 4 Access RW Reset 0x00 SFR Page ALL SFR Address OxFD Bit Name Reset Access Description 7 0 PCAOCPL4 0x00 RW PCA Channel 4 Capture Module Low Byte The PCAOCPL4 register holds the low byte LSB of the 16 bit capture module write to this register will clear the module s ECOM bit to a 0 14 4 19 4 PCA Channel 4 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 PCAOCPH4 Access RW Reset 0 00 SFR Page ALL SFR Address OxFE Bit Name Reset Access Descriptio
279. ode without Bank Select This allows firmware to manipulate the upper address bits at will by setting the port state directly The lower 8 bits of the effective address A 7 0 are determined by the contents of RO or R1 16 bit MOVX operations use the contents of DPTR to determine the effective address A 15 0 The full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 15 3 6 Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements The Address Setup time Address Hold time RDb and WRb strobe widths and in multiplexed mode the width of the ALE pulse are all programmable in units of SYSCLK periods The timing for an off chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMIF registers Assuming non multiplexed operation the minimum execution time for an off chip XRAM operation is 5 SYSCLK cycles 1 SYSCLK for RDb or WRb pulse 4 SYSCLKs For multiplexed operations the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles Therefore the minimum execution time of an off chip XRAM operation in multiplexed mode is 7 SYSCLK cycles 2 SYSCLKs for ALEm 1 for RDb or WRb 4 SYSCLKs The programmable setup and hold times default to the maxi mum delay settings after a reset Table 15 3 External Memory Interface Timing
280. on 1 B1 0 RW Port 0 Bit 1 Skip See bit 7 description 0 BO 0 RW Port 0 Bit 0 Skip See bit 7 description silabs com Smart Connected Energy friendly Rev 0 2 92 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 8 P1 Port 1 Pin Latch Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address 0x90 bit addressable Bit Name Reset Access Description 7 B7 1 RW Port 1 Bit 7 Latch Value Name Description 0 LOW P1 7 is low Set P1 7 to drive low 1 HIGH P1 7 is high Set P1 7 to drive or float high 6 B6 1 RW Port 1 Bit 6 Latch See bit 7 description 5 B5 1 RW Port 1 Bit 5 Latch See bit 7 description 4 B4 1 RW Port 1 Bit 4 Latch See bit 7 description 3 B3 1 RW Port 1 Bit 3 Latch See bit 7 description 2 B2 1 RW Port 1 Bit 2 Latch See bit 7 description 1 B1 1 RW Port 1 Bit 1 Latch See bit 7 description 0 BO 1 RW Port 1 Bit 0 Latch See bit 7 description Writing this register sets the port latch logic value for the associated I O pins configured as digital I O Reading this register returns the logic value at the pin regardless if it is configured as output or input silabs com Smart Connected Energy friendly Rev 0 2 93 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 9 P1MDIN P
281. onfigurable ALE address latch enable timing Configurable address setup and hold times Configurable write and read pulse widths 1 7 Analog 10 Bit Analog to Digital Converter ADCO The ADC is a successive approximation register SAR ADC with 10 bit mode integrated track and hold and a programmable window detector The ADC is fully configurable under software control via several registers The ADC may be configured to measure different signals using the analog multiplexer The voltage reference for the ADC is selectable between internal and external reference sources The ADC module is a Successive Approximation Register SAR Analog to Digital Converter ADC The key features of this ADC mod ule are Up to 32 external inputs Differential or Single ended 10 bit operation Supports an output update rate of 500 ksps samples per second Asynchronous hardware conversion trigger selectable between software external I O and internal timer sources Output data window comparator allows automatic range checking Two tracking mode options with programmable tracking time Conversion complete and window compare interrupts supported Flexible output data formatting Voltage reference selectable from external reference pin on chip precision reference driven externally on reference pin or VDD supply Integrated temperature sensor silabs com Smart Connected Energy friendly Rev 0 2 5 EFM8UB2 Reference Manual System Overvi
282. onfigured as an input When operating as a slave NSS selects the SPI device When operating as a master a 1 to 0 transition of the NSS signal disables the master function of the SPI module so that multiple master devices can be used on the same SPI bus NSSMD 1 0 1x 4 Wire Master Mode The SPI operates in 4 wire mode and NSS is enabled as an output The setting of NSSMDO determines what logic level the NSS pin will output This configuration should only be used when operating the SPI as a master device The setting of NSSMD bits affects the pinout of the device When in 3 wire master or 3 wire slave mode the NSS pin will not be map ped by the crossbar In all other modes the NSS signal will be mapped to a pin on the device Master Device Slave Device MISO NSS 5 Figure 17 2 4 Wire Connection Diagram Master Device Slave Device MOSI 7 ya MOSI Figure 17 3 3 Wire Connection Diagram silabs com Smart Connected Energy friendly Rev 0 2 213 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO Master Device 1 Slave Device SCK y SCK MISO X4 x MISO aec 50 QTY port pin XA Master Device 2 55 NORD MISO SCK Figure 17 4 Multi Master Connection Diagram 17 3 2 Master Mode Operation An SPI master device initiates all data transfers on a SPI bus It drives the SCK line and controls the speed at which data is transferred To place the SPI in master mod
283. operations the full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction silabs com Smart Connected Energy friendly Rev 0 2 167 EFM8UB2 Reference Manual External Memory Interface EMIFO Split Mode with Bank Select In Split Mode with Bank Select the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the on chip XRAM boundary will access on chip XRAM space Effective addresses above the on chip XRAM boundary will access off chip space 8 bit MOVX operations use the contents of EMIOCN to determine whether the memory access is onchip or off chip The upper bits of the Address Bus A 15 8 are determined by EMIOCN and the lower 8 bits of the Address Bus A 7 0 are determined by RO or R1 All 16 bits of the Address Bus A 15 0 are driven in Bank Select mode 16 bit MOVX operations use the contents of DPTR to determine whether the memory access is onchip or off chip and the full 16 bits of the Address Bus A 15 0 are driven during the off chip transactions External Only In External Only mode all MOVX operations are directed to off chip space On chip XRAM is not visible to the CPU This mode is use ful for accessing off chip memory located between 0x0000 and the on chip XRAM boundary 8 bit MOVX operations ignore the contents of The upper Address bits A 15 8 are not driven identical behavior to an off chip access in Split M
284. or relative temperature measurements For absolute tem perature measurements offset and or gain calibration is recommended Typically a 1 point offset calibration includes the following steps 1 Control measure the ambient temperature this temperature must be known 2 Power the device and delay for a few seconds to allow for self heating 3 Perform an ADC conversion with the temperature sensor selected as the ADC input 4 Calculate the offset characteristics and store this value in non volatile memory for use with subsequent temperature sensor meas urements Rev 0 2 120 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 4 ADCO Control Registers 12 4 1 ADCOCF ADCO Configuration Bit 7 6 5 4 3 2 1 0 ADSC ADLJST Reserved Access RW RW RW Reset Ox1F 0 0 0 SFR Page ALL SFR Address 0xBC Bit Name Reset Access Description 7 3 ADSC Ox1F RW SAR Clock Divider This field sets the ADC clock divider value It should be configured to be as close to the maximum SAR clock speed as the datasheet will allow The SAR clock frequency is given by the following equation Fclksar Fsysclk ADSC 1 2 ADLJST 0 RW ADCO Left Justify Select Value Name Description 0 RIGHT_JUSTIFIED Data in the ADCOH ADCOL registers is right justified 1 LEFT_JUSTIFIED Data in the ADCOH ADCOL registers is left justified 1 0 Reser
285. ort 1 Input Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 1 BO Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1 SFR Page ALL SFR Address OxF2 Bit Name Reset Access Description 7 B7 1 RW Port 1 Bit 7 Input Mode Value Name Description 0 ANALOG P1 7 pin is configured for analog mode 1 DIGITAL P1 7 pin is configured for digital mode 6 B6 1 RW Port 1 Bit 6 Input Mode See bit 7 description 5 B5 1 RW Port 1 Bit 5 Input Mode See bit 7 description 4 B4 1 RW Port 1 Bit 4 Input Mode See bit 7 description 3 B3 1 RW Port 1 Bit 3 Input Mode See bit 7 description 2 B2 1 RW Port 1 Bit 2 Input Mode See bit 7 description 1 B1 1 RW Port 1 Bit 1 Input Mode See bit 7 description 0 BO 1 RW Port 1 Bit 0 Input Mode See bit 7 description Port pins configured for analog mode have their weak pullup digital driver and digital receiver disabled silabs com Smart Connected Energy friendly Rev 0 2 94 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 4 10 P1MDOUT Port 1 Output Mode Bit 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xA5 Bit Name Reset Access Description 7 B7 0 RW Port 1 Bit 7 Output Mode Value Name Description 0 OPEN_DRAIN P1 7 output is open drain 1
286. ow period Timer Source Overflows SCL Tow Thigh SCL High Timeout Figure 18 4 Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line The minimum SDA setup time defines the abso lute minimum time that SDA is stable before SCL transitions from low to high The minimum SDA hold time defines the absolute mini mum time that the current SDA value remains stable after SCL transitions from high to low EXTHOLD should be set so that the mini mum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns respectively Setup and hold time exten sions are typically necessary for SMBus compliance when SYSCLK is above 10 MHz Table 18 1 Minimum SDA Setup and Hold Times EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time 0 Tiow 4 system clocks or 1 system clock 3 system clocks s w delay 1 11 system clocks 12 system clocks Note Setup Time for ACK bit transmissions and the MSB of all data transfers When using software acknowl edgment the s w delay occurs between the time SMBODAT or ACK is written and when SI is cleared Note that if SI is cleared in the same write that defines the outgoing ACK value s w delay is zero With the SMBTOE bit set Timer 3 should be configured to overflow after 25 ms
287. ow timer in split 8 bit auto reload mode is F F input Clock Finput Clock The overflow rate of the high timer in split 8 bit auto reload mode is F B F input Clock _ F input Clock TIMERn High 28 TMRnRLH 7 256 TMRnRLH The TFnH bit is set when TMRnH overflows from OxFF to 0x00 the TFnL bit is set when TMRnL overflows from OxFF to 0x00 When timer interrupts are enabled an interrupt is generated each time TMRnH overflows If timer interrupts are enabled and TFnLEN is set an interrupt is generated each time either TMRnL or TMRnH overflows When TFnLEN is enabled software must check the TFnH and TFnL flags to determine the source of the timer interrupt The TFnH and TFnL interrupt flags are not cleared by hardware and must be manually cleared by software TMRnRLH TFnH Overflow TRn Interrupt Timer High Clock TFnLEN TMRnRLL TCLK Timer Low 7 1108 TFnL Overflow Figure 19 7 8 Bit Split Mode Block Diagram silabs com Smart Connected Energy friendly Rev 0 2 256 EFM8UB2 Reference Manual Timers 0 Timer1 Timer2 Timer3 Timer4 and Timer5 19 3 3 3 Capture Mode Capture mode allows system event to be measured against the selected clock source When used in capture mode the timer clocks normally from the selected clock source through the entire range of 16 bit values from 0x0000 to OxFFFF Setting TFNCEN to 1 enables capture mode In this
288. owed Must erase entire flash space None Read write and erase are not permitted 4 3 2 Programming the Flash Memory Writes to flash memory clear bits from logic 1 to logic 0 and can be performed on single byte locations Flash erasures set bits back to logic 1 and occur only on full pages The write and erase operations are automatically timed by hardware for proper execution data polling to determine the end of the write erase operation is not required Code execution is stalled during a flash write erase operation The simplest means of programming the flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor Firmware may also be loaded into the device to implement code loader functions or allow non volatile data stor age To ensure the integrity of flash contents it is strongly recommended that the on chip supply monitor be enabled in any system that includes code that writes and or erases flash memory from software 4 3 2 1 Flash Lock and Key Functions Flash writes and erases by user software are protected with a lock and key function The FLKEY register must be written with the cor rect key codes in sequence before flash operations may be performed The key codes are 5 and OxF1 The timing does not mat ter but the codes must be written in order If the key codes are written out of order or the wrong codes are written flash writes and erases will be disabled until
289. pply monitor is enabled following a power on reset RSTb Logic HIGH Logic LOW Power On Reset Figure 9 2 Power On Reset Timing silabs com Smart Connected Energy friendly Rev 0 2 63 EFM8UB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 3 Supply Monitor Reset The supply monitor senses the voltage on the device s supply pin and can generate a reset if the supply drops below the corresponding threshold This monitor is enabled and enabled as reset source after initial power on to protect the device until the supply is ade quate and stable voltage When enabled and selected as reset source any power down transition or power irregularity that causes the supply to drop below the reset threshold will drive the RSTb pin low and hold the core reset state When the supply returns to level above the reset threshold the monitor will release the core from the reset state The reset status can then be read using the device reset sources module After a power fail reset the PORF flag reads 1 and all of the other reset flags in the RSTSRC register are indeterminate The power on reset delay tpog is not incurred after a supply monitor reset The contents of RAM should be presumed invalid after a supply monitor reset The enable state of the supply monitor and its selection as a reset source is not altered by device resets For example if the supply monitor is de selected as a reset source
290. present the 9th received bit in 9 bit mode or the stop bit in 8 bit mode and should be read prior to reading SBUFO 20 3 4 Multiprocessor Communications 9 Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic O Setting the MCE bit of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the ninth bit is logic 1 RB8 1 signifying an address byte has been received In the UART interrupt handler software will com pare the received address with the slave s own assigned 8 bit address If the addresses match the slave will clear its MCE bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE bit to ignore all transmissions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast
291. pt occurs Pending interrupts are sampled and priority deco ded on every system clock cycle Therefore the fastest possible response time is 5 system clock cycles 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR If an interrupt is pending when a RETI is executed a single instruction is executed before an LCALL is made to service the pending interrupt Therefore the maximum response time for an interrupt when no other interrupt is currently being serviced or the new interrupt is of greater priority occurs when the CPU is performing an RETI instruc tion followed by a DIV as the next instruction In this case the response time is 18 system clock cycles 1 clock cycle to detect the interrupt 5 clock cycles to execute the RETI 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR If the CPU is executing an ISR for an interrupt with equal or higher priority the new interrupt will not be serviced until the current ISR completes including the RETI and following instruction If more than one interrupt is pending when the CPU exits an ISR the CPU will service the next highest priority interrupt that is pending silabs com Smart Connected Energy friendly Rev 0 2 29 EFM8UB2 Reference Manual Interrupts 6 2 3 Interrupt Summary Table 6 1 Interrupt Priority Table Interrupt Source Priority Primary Enabl
292. pt service routine This bit must be cleared by firmware 6 TF2L 0 RW Timer 2 Low Byte Overflow Flag Set by hardware when the Timer 2 low byte overflows from OxFF to 0x00 2 will be set when the low byte overflows regardless of the Timer 2 mode This bit must be cleared by firmware 5 TF2LEN 0 RW Timer 2 Low Byte Interrupt Enable When set to 1 this bit enables Timer 2 Low Byte interrupts If Timer 2 interrupts are also enabled an interrupt will be gen erated when the low byte of Timer 2 overflows 4 TF2CEN 0 RW Timer 2 Capture Enable When set to 1 this bit enables Timer 2 Capture Mode If TF2CEN is set and Timer 2 interrupts are enabled an interrupt will be generated based on the selected input capture source and the current 16 bit timer value in TMR2H TMR2L will be cop ied to TMR2RLH TMR2RLL 3 T2SPLIT 0 RW Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with auto reload Value Name Description 0 16 BIT RELOAD Timer 2 operates in 16 bit auto reload mode 1 8 BIT RELOAD Timer 2 operates as two 8 bit auto reload timers 2 TR2 0 RW Timer 2 Run Control Timer 2 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR2H only TMR2L is always enabled in split mode 1 T2CSS 0 RW Timer 2 Capture Source Select This bit selects the source of a capture event when bit TF2CEN is set to 1 Value Name Description 0 U
293. quence on page 236 shows a typical slave write sequence as it appears on the bus The corresponding firmware state diagram combined with the slave read sequence is shown in Figure 18 10 Slave State Diagram EHACK 1 on page 237 Two received data bytes are shown though any number of bytes may be ceived Notice that the data byte transferred interrupts occur at different places in the sequence depending on whether hardware ACK generation is enabled The interrupt occurs before the ACK with hardware ACK generation disabled and after the ACK when hardware ACK generation is enabled Interrupts with Hardware ACK Enabled EHACK 1 Gi E A Data Byte Data Byte p Interrupts with Hardware ACK Disabled EHACK 0 Received by SMBus S START Interface P STOP W WRITE Transmitted by SLA Slave Address SMBus Interface Figure 18 9 Typical Slave Write Sequence silabs com Smart Connected Energy friendly Rev 0 2 236 EFM8UB2 Reference Manual System Management Bus 2 SMBO and 5 1 Interrupt QE 1 Clear STA 2 Read Address R W from SMBODAT gt e 1 Set ACK 2 Clear SI Interrupt b AF 1 Read Data From SMBODAT 2 Clear SI 7 Clear SI Figure 18 10 Slave State Diagram EHACK 1 silabs com Smart Connected Energy friendly Rev 0 2 237 EFM8UB2 Reference Manual System Management Bus
294. quired Allows inspection and modification of all memory spaces and registers Provides hardware breakpoints and single step capabilites Can be locked via flash security mechanism to prevent unwanted access 22 3 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in system debugging and flash programming may be per formed C2CK is shared with the RSTb pin while the C2D signal is shared with a port I O pin This is possible because C2 communica tion is typically performed when the device is in the halt state where all on chip peripherals and user software are stalled In this halted state the C2 interface can safely borrow the C2CK and C2D pins In most applications external resistors are required to isolate C2 interface traffic from the user application RSTb a Input b Output c C2 Interface Master Figure 22 1 Typical C2 Pin Sharing The configuration above assumes the following The user input b cannot change state while the target device is halted The RSTb pin on the target device is used as an input only Additional resistors may be necessary depending on the specific application silabs com Smart Connected Energy friendly Rev 0 2 292 EFM8UB2 Reference Manual C2 Debug and Programming Interface 22 4 C2 Interface Registers 22 4 1 C2ADD C2 Address Bit 7 6 5 4 3 2 1 0 C2ADD Access RW Reset 0x00 This register is part
295. r mined by the setting the CPHYP bits Positive programmable hysteresis CPHYP I Negative programmable hysteresis CPHYN Figure 13 2 Comparator Hysteresis Plot 13 3 3 Input Selection Comparator inputs may be routed to port I O pins or internal signals When connected externally the comparator inputs can be driven from 0 25 V to VDD 0 25 V without damage or upset The CMPnMX register selects the inputs for the associated comparator The CMXP field selects the comparator s positive input CPnP x and the CMXN field selects the comparator s negative input CPnN x Note Any port pins selected as comparator inputs should be configured as analog inputs in their associated port configuration register and configured to be skipped by the crossbar silabs com Smart Connected Energy friendly Rev 0 2 128 EFM8UB2 Reference Manual Comparators CMPO 1 13 3 3 1 Multiplexer Channel Selection Table 13 1 CMPO Positive Input Multiplexer Channels CMXP Setting in Reg Signal Name QFP48 Pin Name QFP32 Pin Name QFN32 Pin Name ister CMPOMX 000 0 2 0 1 0 1 0 001 1 2 5 1 4 1 4 010 2 P3 4 P2 0 P2 0 011 CMPOP 3 P4 3 P2 4 P2 4 100 CMPOP 4 P0 3 0 0 101 CMPOP 5 Reserved Reserved Reserved 110 CMPOP 6 Reserved Reserved Reserved 111 CMPOP 7 Reserved Reserved Reserved CMXN Setting in Table 13 2
296. r 1 0x006B 13 EIET ECP1 CMP1MD CPFIE CMP1CNO_CPFIF CMP1MD_CPRIE CMP1CNO_CPRIF Timer 3 Overflow 0x0073 14 EIET JETS TMR3CN TMR3CN VBUS Level 0x007B 15 EIE2 EVBUS UART 1 0x0083 16 EIE2 ES1 SCON1 RI SCON1 Reserved 0x008B 17 SMBus 1 0x0093 18 EIE2 5 1 SMB1CNO SI Timer 4 Overflow 0 009 19 EIE2_ET4 TMR4CNO_TF4H TMR4CNO_TF4L Timer 5 Overflow 0x00A3 20 EIE2 ETS TMR5CNO TF5H TMR5CNO TF5L silabs com Smart Connected Energy friendly Rev 0 2 31 EFM8UB2 Reference Manual Interrupts 6 3 Interrupt Control Registers 6 3 1 IE Interrupt Enable Bit 7 6 5 4 3 2 1 0 ESPIO ET2 ESO ET1 EX1 ETO EXO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xA8 bit addressable Bit Name Reset Access Description 7 EA 0 RW All Interrupts Enable Globally enables disables all interrupts and overrides individual interrupt mask settings Value Name Description 0 DISABLED Disable all interrupt sources 1 ENABLED Enable each interrupt according to its individual mask setting 6 ESPIO 0 RW SPIO Interrupt Enable This bit sets the masking of the SPIO interrupts Value Name Description 0 DISABLED Disable all SPIO interrupts 1 ENABLED Enable interrupt requests generated by SPIO 5 ET2 0 RW Timer 2 Interrupt Enable This bit sets the masking of the T
297. rated by the TF3L or TF3H flags 6 ECP1 0 RW Comparator1 CP1 Interrupt Enable This bit sets the masking of the CP1 interrupt Value Name Description 0 DISABLED Disable CP1 interrupts 1 ENABLED Enable interrupt requests generated by the comparator 1 CPRIF or CPFIF flags 5 ECPO 0 RW Comparator0 Interrupt Enable This bit sets the masking of the CPO interrupt Value Name Description 0 DISABLED Disable CPO interrupts 1 ENABLED Enable interrupt requests generated by the comparator 0 CPRIF or CPFIF flags 4 EPCAO 0 RW Programmable Counter Array 0 Interrupt Enable This bit sets the masking of the PCAO interrupts Value Name Description 0 DISABLED Disable all PCAO interrupts 1 ENABLED Enable interrupt requests generated by PCAO 3 EADCO 0 RW ADCO Conversion Complete Interrupt Enable This bit sets the masking of the ADCO Conversion Complete interrupt Value Name Description 0 DISABLED Disable ADCO Conversion Complete interrupt 1 ENABLED Enable interrupt requests generated by the ADINT flag 2 EWADCO 0 RW ADCO Window Comparison Interrupt Enable silabs com Smart Connected Energy friendly This bit sets the masking of ADCO Window Comparison interrupt Rev 0 2 36 EFM8UB2 Reference Manual Interrupts Bit Name Reset Access Description Value Name Description 0 DISABLED Disable ADCO Window Comparison interrupt 1 ENABLED Enable interrupt requests generated by ADCO Window Compare f
298. rdware parity 3 2 SDL 0x3 RW Data Length Value Name Description 0x0 5 BITS 5 bits Ox1 6 BITS 6 bits 0 2 7 5 7 bits 0 3 8 5 8 bits 1 XBE 0 RW Extra Bit Enable When enabled the value of TBX in the SCON1 register will be appended to the data field Value Name Description 0 DISABLED Disable the extra bit 1 ENABLED Enable the extra bit silabs com Smart Connected Energy friendly Rev 0 2 288 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 Bit Name Reset Access Description 0 SBL 0 RW Stop Bit Length Value Name Description 0 SHORT Short Stop bit is active for one bit time 1 LONG Long Stop bit is active for two bit times data length 6 7 or 8 bits or 1 5 bit times data length 5 bits 21 4 3 SBUF1 UART1 Serial Port Data Buffer Bit 7 6 5 4 3 2 1 0 SBUF1 Access RW Reset Varies SFR Page ALL SFR Address OxD3 Bit Name Reset Access Description 7 0 SBUF1 Varies RW Serial Port Data Buffer This SFR accesses the transmit and receive FIFOs When data is written to SBUF1 and TXNF is 1 the data is placed into the transmit FIFO and is held for serial transmission Any data in the TX FIFO will initiate a transmission Writing to SBUF1 while TXNF is 0 will over write the most recent byte in the TX FIFO A read of SBUF 1 returns the oldest byte in the RX FIFO Reading SBUF1 when RI is 0 will continu
299. received Software may safely read or write to the data register when the SI flag is set Software should not attempt to access the SMBODAT register when the SMBus is enabled and the SI flag is cleared to logic 0 Note Certain device families have a transmit and receive buffer interface which is accessed by reading and writing the SMBODAT reg ister To promote software portability between devices with and without this buffer interface it is recommended that SMBODAT not be used as a temporary storage location On buffer enabled devices writing the register multiple times will push multiple bytes into the transmit FIFO 18 3 4 Operational Modes The SMBus interface may be configured to operate as master and or slave At any particular time it will be operating in one of the following four modes Master Transmitter Master Receiver Slave Transmitter or Slave Receiver The SMBus interface enters Master Mode any time a START is generated and remains in Master Mode until it loses an arbitration or generates a STOP An SMBus inter rupt is generated at the end of all SMBus byte frames The position of the ACK interrupt when operating as a receiver depends on whether hardware ACK generation is enabled As a receiver the interrupt for an ACK occurs before the ACK with hardware ACK gener ation disabled and after the ACK when hardware ACK generation is enabled As a transmitter interrupts occur after the ACK regard less of whether hardware ACK generation
300. rect byte 3 3 3 ORL A Rn OR Register to A 1 1 1 ORL A direct OR direct byte to A 2 2 2 ORL A Ri OR indirect RAM to A 1 2 2 ORL A data OR immediate to A 2 2 2 ORL direct A OR A to direct byte 2 2 2 ORL direct data OR immediate to direct byte 3 3 3 XRL A Rn Exclusive OR Register to A 1 1 1 XRL A direct Exclusive OR direct byte to A 2 2 2 XRL A Ri Exclusive OR indirect RAM to A 1 2 2 XRL A data Exclusive OR immediate to A 2 2 2 XRL direct A Exclusive OR A to direct byte 2 2 2 XRL direct data Exclusive OR immediate to direct byte 3 3 3 CLRA Clear A 1 1 1 CPLA Complement A 1 1 1 RLA Rotate A left 1 1 1 RLCA Rotate A left through Carry 1 1 1 RRA Rotate A right 1 1 1 RRCA Rotate A right through Carry 1 1 1 SWAP A Swap nibbles of A 1 1 1 Data Transfer MOV A Rn Move Register to A 1 1 1 MOV A direct Move direct byte to A 2 2 2 MOV A Ri Move indirect RAM to A 1 2 2 MOV A data Move immediate to A 2 2 2 silabs com Smart Connected Energy friendly Rev 0 2 71 EFM8UB2 Reference Manual CIP 51 Microcontroller Core Mnemonic Description Clock Cycles prefetch on SYSCLK 12 MHz FLRT 0 prefetch on SYSCLK 48 MHz FLRT 1 MOV Rn A Move A to Register 1 1 1 MOV Rn direct Move direct byte to Register 2 2 2 MOV Rn data Move immediate to Register 2 2 2 MOV direct A Move
301. requency Oscillator 8 0 2 EXTOSC USB clock USBCLK derived from the External Oscillator 0x3 EXTOSC_DIV_2 USB clock USBCLK derived from the External Oscillator 2 0 4 EXTOSC_DIV_3 USB clock USBCLK derived from the External Oscillator 3 0 5 EXTOSC_DIV_4 USB clock USBCLK derived from the External Oscillator 4 0 6 LFOSC USB clock USBCLK derived from the Internal Low Frequency Oscillator 3 OUTCLK 0 RW Crossbar Clock Out Select If the SYSCLK signal is enabled on the Crossbar this bit selects between outputting SYSCLK and SYSCLK synchronized with the Port I O pins Value Name Description 0 SYSCLK Enabling the Crossbar SYSCLK signal outputs SYSCLK 1 SYSCLK SYNC IO Enabling the Crossbar SYSCLK signal outputs SYSCLK synchronized with the Port I O 2 0 CLKSL 0 0 RW System Clock Source Select Bits Value Name Description 0 0 DIVI Clock SYSCLK derived from the Internal High Frequency Oscillator 4 and DED HFOSC DIV 4 scaled per the IFCN bits in register OSCICN Ox1 EXTOSC Clock SYSCLK derived from the External Oscillator circuit 0 2 HFOSC_DIV_2 Clock SYSCLK derived from the Internal High Frequency Oscillator 2 0x3 HFOSC Clock SYSCLK derived from the Internal High Frequency Oscillator 0 4 LFOSC Clock SYSCLK derived from the Internal Low Frequency Oscillator and scaled per the OSCLD bits in register OSCLCN Prior to switching to a system clock frequency gt 25 MHz ensure that the FLRT b
302. resented as 10 bit signed 2 s complement numbers Inputs are measured from VREF to VREF x 511 512 For right justified data the unused MSBs of ADCOH are a sign extension of the data word For left justified data the unused LSBs in the ADCOL register are set to 0 Table 12 4 Differential Output Code Example Input Voltage Right Justified ADLJST 0 Left Justified ADLJST 1 ADCOH L ADCOH L VREF x 511 512 OxO1FF Ox7FCO VREF x 256 512 0x0100 0x4000 0 0x0000 0x0000 VREF x 256 512 OxFFOO 0 000 VREF 0 8000 silabs com Smart Connected Energy friendly Rev 0 2 117 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 3 7 Window Comparator The ADC s programmable window detector continuously compares the ADC output registers to user programmed limits and notifies the system when a desired condition is detected This is especially effective in an interrupt driven system saving code space and CPU bandwidth while delivering faster system response times The window detector interrupt flag ADWINT can also be used in polled mode The ADC Greater Than ADCOGTH ADCOGTL and Less Than ADCOLTH ADCOLTL registers hold the comparison values The window detector flag can be programmed to indicate when measured data is inside or outside of the user programmed limits de pending on the contents of the ADCOGT and ADCOLT registers The following tables show how the ADCOGT and
303. reset to 0 by hardware An IN transaction is completed this interrupt generated during the status stage of the transaction Hardware sets the STSTL bit after a control transaction ended due to a protocol violation Hardware sets the SUEND bit because a control transfer ended before firmware set the DATAEND bit The EOCNT register holds the number of received data bytes in the EndpointO FIFO Hardware will automatically detect protocol errors and send a STALL condition in response Firmware may force a STALL condition to abort the current transfer When a STALL condition is generated the STSTL bit will be set to 1 and an interrupt generated The following conditions will cause hardware to generate a STALL condition The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to 1 The host sends an IN token during an IN data phase after the DATAEND bit has been set to 1 The host sends a packet that exceeds the maximum packet size for EndpointO The host sends a non zero length DATA1 packet during the status phase of an IN transaction Firmware sets the SDSTL bit to 1 EndpointO SETUP Transactions control transfers must begin with a SETUP packet SETUP packets are similar to OUT packets containing an 8 byte data field sent by the host Any SETUP packet containing a command field of anything other than 8 bytes will be automatically rejected by USBO An EndpointO interrupt is generated when the d
304. rflow edge of the waveforms An example of the PWM timing in edge aligned mode for two channels is shown here Counter OxFFFF 0 0000 0 0001 0 0002 0 0003 0 0004 0 0005 Capture Compare Output match edge Capture Compare 0x0005 1 gt gt gt 5 5 2 gt Output 1 overflow edge match edge Figure 14 6 Edge Aligned PWM Timing For a given PCA resolution the unused high bits in the PCAO counter and the PCAOCPn compare registers are ignored and only the used bits of the PCAOCPn register determine the duty cycle A 0 duty cycle for the channel is achieved by clearing the module s ECOM bit to 0 This will disable the comparison and prevent the match edge from occuring Note Although the PCAOCPn compare register determines the duty cycle it is not always appropriate for firmware to update this regis ter directly See the sections on 8 bit and 16 bit PWM mode for additional details on adjusting duty cycle in the various modes N Duty Cycle LUN S Figure 14 7 N bit Edge Aligned PWM Duty Cycle PWM resolution silabs com Smart Connected Energy friendly Rev 0 2 144 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 3 8 1 8 Bit PWM Mode In 8 bit PWM mode the duty cycle is determined by the value of th
305. rmal Core and all peripherals clocked and fully operational Idle Core halted Set IDLE bit in PCONO Any interrupt All peripherals clocked and fully operational Code resumes execution on wake event Suspend Core and peripheral clocks halted 1 Switch SYSCLK to USBO Bus Activity Code resumes execution on wake event HFOSCO 2 Set SUSPEND bit in HFOOCN Shutdown All internal power nets shut down 1 Set STOPCF bit in RSTb pin reset 5V regulator remains active if enabled REGO1CN Power on reset 2 Set STOP bit in PCONO Pins retain state Exit on pin or power on reset 1 3 1 0 Digital and analog resources are externally available on the device s multi purpose I O pins Port pins P0 0 P3 7 can be defined as gen eral purpose GPIO assigned to one of the internal digital resources through the crossbar or dedicated channels or assigned to an analog function Port pins P4 0 P4 7 can be used as GPIO Additionally the C2 Interface Data signal C2D is shared with P3 0 on some packages Up to 40 multi functions pins supporting digital and analog functions Flexible priority crossbar decoder for digital peripheral assignment Two direct pin interrupt sources with dedicated interrupt vectors INTO and INT1 available on PO pins 1 4 Clocking The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources By default the system clock co
306. rrupt Value Name Description 0 LOW External Interrupt 1 set to low priority level 1 HIGH External Interrupt 1 set to high priority level 1 PTO 0 RW Timer 0 Interrupt Priority Control silabs com Smart Connected Energy friendly This bit sets the priority of the Timer 0 interrupt Rev 0 2 34 EFM8UB2 Reference Manual Interrupts Bit Name Reset Access Description Value Name Description 0 LOW Timer 0 interrupt set to low priority level 1 HIGH Timer 0 interrupt set to high priority level 0 0 RW External Interrupt 0 Priority Control This bit sets the priority of the External Interrupt 0 interrupt Value Name Description 0 LOW External Interrupt 0 set to low priority level 1 HIGH External Interrupt 0 set to high priority level silabs com Smart Connected Energy friendly Rev 0 2 35 EFM8UB2 Reference Manual Interrupts 6 3 3 EIE1 Extended Interrupt Enable 1 Bit 7 6 5 4 3 2 1 0 Name ET3 ECP1 ECPO EADCO EWADCO EUSBO ESMBO Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address OxE6 Bit Name Reset Access Description 7 0 RW Timer 3 Interrupt Enable This bit sets the masking of the Timer 3 interrupt Value Name Description 0 DISABLED Disable Timer 3 interrupts 1 ENABLED Enable interrupt requests gene
307. rrupt 1 ENABLED Enable UARTI interrupt 0 EVBUS 0 RW VBUS Level Interrupt Enable This bit sets the masking of the VBUS interrupt Value Name Description 0 DISABLED Disable all VBUS interrupts 1 ENABLED Enable interrupt requests generated by VBUS level sense silabs com Smart Connected Energy friendly Rev 0 2 40 EFM8UB2 Reference Manual Interrupts 6 3 6 EIP2 Extended Interrupt Priority 2 Bit 7 6 5 4 3 2 1 0 Name Reserved PT5 PT4 PSMB1 Reserved PS1 PVBUS Access R RW RW RW RW RW RW Reset 0x0 0 0 0 0 0 0 SFR Page ALL SFR Address OxF7 Bit Name Reset Access Description 7 6 Reserved Must write reset value 5 PT5 0 RW Timer 5 Interrupt Priority Control This bit sets the priority of the Timer 5 interrupt Value Name Description 0 LOW Timer 5 interrupt set to low priority level 1 HIGH Timer 5 interrupt set to high priority level 4 0 RW Timer 4 Interrupt Priority Control This bit sets the priority of the Timer 4 interrupt Value Name Description 0 LOW Timer 4 interrupt set to low priority level 1 HIGH Timer 4 interrupt set to high priority level 3 PSMB1 0 RW SMBus1 Interrupt Priority Control This bit sets the priority of the SMB1 interrupt Value Name Description 0 LOW SMB1 interrupt set to low priority level 1 HIGH SMB1 interrupt set to high priority level 2 Reserved Must write reset v
308. rrupts can be enabled by setting the ET1 bit in the IE register Both counter timers operate in one of four primary modes selected by setting the Mode Select bits T1M1 TOMO in the Counter Timer Mode register TMOD Each timer can be configured independently for the supported operating modes silabs com Smart Connected Energy friendly Rev 0 2 249 EFM8UB2 Reference Manual Timers TimerO 1 2 Timer3 Timer4 and Timer5 19 3 2 1 Operational Modes Mode 0 13 bit Counter Timer Timer 0 and Timer 1 operate as 13 bit counter timers in Mode 0 The following describes the configuration and operation of Timer 0 However both timers operate identically and Timer 1 is configured in the same manner as described for Timer 0 The THO register holds the eight MSBs of the 13 bit counter timer TLO holds the five LSBs in bit positions TLO 4 TLO O The three upper bits of TLO 1 0 7 0 5 are indeterminate and should be masked out or ignored when reading As the 13 bit timer register increments and overflows from Ox1FFF all ones to 0x0000 the timer overflow flag TFO in TCON is set and an interrupt occurs if Timer 0 interrupts are enabled The overflow rate for Timer 0 in 13 bit mode is F F input Clock Finput Clock TIMERO 213 THO TLO 8192 THO TLO The CTO bit in the TMOD register selects the counter timer s clock source When CTO is set to logic 1 high to low transitions at the selected Timer 0 inp
309. rsion source the associated port pin should be skipped in the crossbar settings 12 3 5 Input Tracking Each ADC conversion must be preceded by a minimum tracking time to allow the voltage on the sampling capacitor to settle and for the converted result to be accurate silabs com Smart Connected Energy friendly Rev 0 2 114 EFM8UB2 Reference Manual Analog to Digital Converter ADCO Settling Time Requirements The absolute minimum tracking time is given in the electrical specifications tables It may be necessary to track for longer than the mini mum tracking time specification depending on the application For example if the ADC input is presented with a large series impe dance it will take longer for the sampling cap to settle on the final value during the tracking phase The exact amount of tracking time required is a function of all series impedance including the internal mux impedance and any external impedance sources the sam pling capacitance and the desired accuracy MUX Select Input Channel RCinput Rmux CsauPLE lt Note The value of CsampLe depends on the PGA gain See the electrical specifications for details Figure 12 2 ADC Eqivalent Input Circuit The required ADCO settling time for a given settling accuracy SA may be approximated as follows n t mf SA TOTAL X CSAMPLE Where SA is the settling accuracy given as a
310. ruction Mov 22 3h moves the Boolean value at 0x13 bit 3 of the byte at location 0x22 into the Carry flag Stack A programmer s stack can be located anywhere in the 256 byte data memory The stack area is designated using the Stack Pointer SP SFR The SP will point to the last location used The next value pushed on the stack is placed at SP 1 and then SP is incremen ted A reset initializes the stack pointer to location 0x07 Therefore the first value pushed on the stack is placed at location 0x08 which is also the first register RO of register bank 1 Thus if more than one register bank is to be used the SP should be initialized to a location in the data memory not being used for data storage The stack depth can extend up to 256 bytes External RAM On devices with more than 256 bytes of on chip RAM the additional RAM is mapped into the external data memory space XRAM Addresses in XRAM area accessed using the external move instructions Note The 16 bit MOVX write instruction is also used for writing and erasing the flash memory More details may be found in the flash memory section silabs com Smart Connected Energy friendly Rev 0 2 8 EFM8UB2 Reference Manual Memory Organization 2 4 Memory Map OxFFFF Reserved OxFBFF Lock Byte OxFBFE Security Page 512 Bytes OxFAO0 63 KB Flash 126 x 512 Byte pages 0x0000 Figure 2 1 Flash Memory Map 64 KB Devices silabs com
311. s active but a device reset is required to wake Fully internal core LDO supplies power to majority of blocks 5 to 3 3 V Regulator Allows direct connection to USB supply net Provides up to 100 mA for system level use Low power consumption in Suspend mode 7 3 Idle Mode In idle mode CPU core execution is halted while any enabled peripherals and clocks remain active Power consumption in idle mode is dependent upon the system clock frequency and any active peripherals Setting the IDLE bit in the PCONO register causes the hardware to halt the CPU and enter idle mode as soon as the instruction that sets the bit completes execution All internal registers and memory maintain their original data All analog and digital peripherals can remain active during idle mode Idle mode is terminated when an enabled interrupt is asserted or a reset occurs The assertion of an enabled interrupt will cause the IDLE bit to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the IDLE bit If idle mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins program execution at address 0x0000 Note If the instruction following the write of the IDLE bit is a single byte instruction and an interrupt occurs during the execution phase of
312. s bit sets the priority of the CPO interrupt Value Name Description 0 LOW CPO interrupt set to low priority level 1 HIGH CPO interrupt set to high priority level 4 PPCAO 0 RW Programmable Counter Array PCAO Interrupt Priority Control This bit sets the priority of the PCAO interrupt Value Name Description 0 LOW PCAO interrupt set to low priority level 1 HIGH PCAO interrupt set to high priority level 3 PADCO 0 RW ADCO Conversion Complete Interrupt Priority Control This bit sets the priority of the ADCO Conversion Complete interrupt Value Name Description 0 LOW ADCO Conversion Complete interrupt set to low priority level 1 HIGH ADCO Conversion Complete interrupt set to high priority level 2 PWADCO 0 RW ADCO Window Comparator Interrupt Priority Control silabs com Smart Connected Energy friendly This bit sets the priority of the ADCO Window interrupt Rev 0 2 38 EFM8UB2 Reference Manual Interrupts Bit Name Reset Access Description Value Name Description 0 LOW ADCO Window interrupt set to low priority level 1 HIGH ADCO Window interrupt set to high priority level 1 PUSBO 0 RW USB USB0 Interrupt Priority Control This bit sets the priority of the USBO interrupt Value Name Description 0 LOW USBO interrupt set to low priority level 1 HIGH USBO interrupt set to high priority level 0 PSMBO 0 RW SMBus 5 0 Interrupt Priority Control This bit sets the priority o
313. s in RAM firmware can overwrite the UID during normal operation The bytes in memory will be automatically reini tialized with the UID value after any device reset Firmware using this area of memory should always initialize the memory to a known value as any previous data stored at these locations will be overwritten and not retained through a reset Table 5 1 UID Location in Memory Device XRAM Addresses EFM8UB20F64G MSB OxOFFF OxOFFE OxOFFD OxOFFC OxOFFB OxOFFA OxOFF9 OxOFF8 OxOFF7 OxOFF6 OxOFF5 OxOFFA OxOFF3 OxOFF2 OxOFF1 OxOFFO LSB EFM8UB20F32G MSB 0x07FF 0x07FE 0x07FD 0x07FC 0x07FB 0x07FA 0x07F9 0x07F8 0x07F7 0x07F6 0x07F5 0x07F4 0x07F3 0 07 2 0x07F1 0x07FO LSB Rev 0 2 28 silabs com Smart Connected Energy friendly EFM8UB2 Reference Manual Interrupts 6 Interrupts 6 1 Introduction The MCU core includes an extended interrupt system supporting multiple interrupt sources and priority levels The allocation of interrupt sources between on chip peripherals and external input pins varies according to the specific version of the device Interrupt sources may have one or more associated interrupt pending flag s located in an SFR local to the associated peripheral When a peripheral or external source meets a valid interrupt condition the associated interrupt pending flag is set to logic 1 If interrupts are enabled for the source an interrupt reque
314. s include RAM mapped into the external data memory space XRAM Devices with enough pins also have an External Memory Interface EMIFO which can be used to access off chip memories and memory mapped devices connected to the GPIO ports The external memory space may be accessed using the external move instruction MOVX with the target address specified in either the data pointer DPTR or with the target address low byte in RO or R1 and the target address high byte in the External Memory Inter face Control Register EMIOCN When using the MOVX instruction to access on chip RAM no additional initialization is required and the MOVX instruction execution time is as specified in the core chapter When using the MOVX instruction to access off chip RAM or memory mapped devices both the Port I O and EMIF should be configured for communication with external devices and MOVX instruction timing is based on the value programmed in the Timing Control Register Configuring the External Memory Interface for off chip memory space access consists of four steps 1 Configure the output modes of the associated port pins as either push pull or open drain push pull is most common and skip the associated pins in the Crossbar if necessary 2 Configure port latches to park the EMIF pins in a dormant state usually by setting them to logic 1 3 Select the memory mode on chip only split mode without bank select split mode with bank select or o
315. s or disables Endpoint 3 Value Name Description 0 DISABLED Disable Endpoint 3 no NACK ACK or STALL on the USB network 1 ENABLED Enable Endpoint 3 normal 2 EEN2 1 RW Endpoint 2 Enable This bit enables or disables Endpoint 2 Value Name Description 0 DISABLED Disable Endpoint 2 no NACK ACK or STALL on the USB network 1 ENABLED Enable Endpoint 2 normal 1 EEN1 1 RW Endpoint 1 Enable This bit enables or disables Endpoint 1 Value Name Description 0 DISABLED Disable Endpoint 1 no NACK ACK or STALL on the USB network 1 ENABLED Enable Endpoint 1 normal 0 Reserved Must write reset value This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 206 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 23 EINCSRL USBO IN Endpoint Control Low Bit 7 6 5 4 3 2 1 0 Reserved CLRDT STSTL SDSTL FLUSH UNDRUN FIFONE INPRDY Access R RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Indirect Address 0x11 Bit Name Reset Access Description 7 Reserved Must write reset value 6 CLRDT 0 Clear Data Toggle 5 STSTL 0 RW Sent Stall Flag Hardware sets this bit to 1 when a STALL handshake signal is transmitted The FIFO is flushed and the INPRDY bit cleared This flag must be cleared by firmware 4 SDSTL 0 RW Send Stall Firmware should set this bit
316. s well as implementing additional SFRs used to configure and access the sub systems unique to the MCU This allows the addi tion of new functionality while retaining compatibility with the MCS 51 instruction set The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to OxFF SFRs with addresses ending 0x0 or 0 8 e g TCON SCONO IE etc are bit addressable as well as byte addressable All other SFRs are byte addressable only Unoccupied addresses in the SFR space are reserved for future use Accessing these areas will have an indeterminate effect and should be avoided SFR Paging The CIP 51 features SFR paging allowing the device to map many SFRs into the 0x80 to OxFF memory address space The SFR memory space has 256 pages In this way each memory location from 0x80 to OxFF can access up to 256 SFRs The EFM8UB2 devices utilize multiple SFR pages All of the common 8051 SFRs are available on all pages Certain SFRs are only available on a subset of pages SFR pages are selected using the SFRPAGE register The procedure for reading and writing an SFR is as follows 1 Select the appropriate SFR page using the SFRPAGE register 2 Use direct accessing mode to read or write the special function register MOV instruction The SFRPAGE register only needs to be changed in the case that the SFR to be accessed does not exist on the currently selected page See the SFR memory map
317. sing above Ox7F access the upper 128 bytes of data memory General Purpose Registers The lower 32 bytes of data memory locations 0 00 through Ox1F may be addressed as four banks of general purpose registers Each bank consists of eight byte wide registers designated RO through R7 Only one of these banks may be enabled at a time Two bits in the program status word PSW register RSO and RS1 select the active register bank This allows fast context switching when entering subroutines and interrupt service routines Indirect addressing modes use registers RO and R1 as index registers silabs com Smart Connected Energy friendly Rev 0 2 7 EFM8UB2 Reference Manual Memory Organization Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through 2 are also cessible as 128 individually addressable bits Each bit has a bit address from 0x00 to Ox7F Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07 Bit 7 of the byte at Ox2F has bit address Ox7F A bit access is distinguished from a full byte access by the type of instruction used bit source or destination operands as opposed to a byte source or destination The MCS 51 assembly language allows an alternate notation for bit addressing of the form XX B where XX is the byte address and B is the bit position within the byte For example the inst
318. ss and others are trademarks or registered trademarks of Silicon Laboratories Inc ARM CORTEX Cortex M3 and THUMB are trademarks or registered trademarks of ARM Holdings Keil is a registered trademark of ARM Limited All other products or brand names mentioned herein are trademarks of their respective holders Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 USA SILICON LABS
319. st is generated when the interrupt pending flag is set As soon as execution of the current instruction is complete the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine ISR Each ISR must end with an RETI instruction which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred If interrupts are not enabled the interrupt pending flag is ignored by the hard ware and program execution continues as normal The interrupt pending flag is set to logic 1 regardless of whether the interrupt is ena bled Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the IE and ElEn registers However interrupts must first be globally enabled by setting the EA bit to logic 1 before the individual interrupt enables are recognized Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt enable settings Some interrupt pending flags are automatically cleared by the hardware when the CPU vectors to the ISR or by other hardware condi tions However most are not cleared by the hardware and must be cleared by software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generated immediately and the CPU will re enter the ISR after t
320. st systems this parameter should not be adjusted and it is recommended that it be left at its default value By default if the SCL falling edge is detected after the falling edge of SDA i e one SYSCLK cycle or more the device will detect this as a START condition The SDD field is used to increase the amount of hold time that is required between SDA and SCL falling before a START is recognized An additional 2 4 or 8 SYSCLKs can be added to prevent false START detection in systems where the bus conditions warrant this SMBus Control Register SMBOCNO is used to control the interface and to provide status information The higher four bits of SMBOCNO MASTER TXMODE STA and STO form a status vector that can be used to jump to service routines MASTER indicates whether a device is the master or slave during the current transfer TXMODE indicates whether the device is transmitting or receiving data for the current byte STA and STO indicate that a START and or STOP has been detected or generated since the last SMBus interrupt STA and STO are also used to generate START and STOP conditions when operating as a master Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free STA is not cleared by hardware after the START is generated Writing a 1 to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle If STO and STA ar
321. structions which force a Soft ware Reset A global search on RSTSRC can quickly verify this PSWE Maintenance Reduce the number of places in code where the PSWE bit in register PSCTL is set to a 1 There should be exactly one routine in code that sets PSWE to a 1 to write flash bytes and one routine in code that sets PSWE and PSEE both to a 1 to erase flash pages Minimize the number of variable accesses while PSWE is set to a 1 Handle pointer address updates and loop variable maintenance outside the PSWE 1 PSWE 0 area Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been reset to 0 Any interrupts posted during the flash write or erase operation will be serviced in priority order after the flash operation has been completed and interrupts have been re enabled by software Make certain that the flash write and erase pointer variables are not located in XRAM See your compiler documentation for instruc tions regarding how to explicitly locate variables in different memory areas Add address bounds checking to the routines that write or erase flash memory to ensure that a routine called with an illegal address does not result in modification of the flash silabs com Smart Connected Energy friendly Rev 0 2 24 EFM8UB2 Reference Manual Flash Memory System Clock If operating from an external crystal based source be advised that crystal performance is susceptib
322. suspend mode This bit is cleared when firmware reads the CMINT register Value Name Description 0 NOT SET Resume interrupt inactive 1 SET Resume interrupt active 0 SUSINT 0 R Suspend Interrupt Flag When suspend detection is enabled bit SUSEN in register POWER this bit is set by hardware when suspend signaling is detected on the bus This bit is cleared when firmware reads the CMINT register Value Name Description 0 NOT SET Suspend interrupt inactive 1 SET Suspend interrupt active This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 200 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 17 IN1IE USBO IN Endpoint Interrupt Enable Bit 7 6 5 3 2 1 0 Name Reserved 2 Access R RW RW RW RW Reset 0x0 1 1 1 1 Indirect Address 0x07 Bit Name Reset Access Description 7 4 Reserved Must write reset value 3 IN3E 1 RW IN Endpoint 3 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 3 IN interrupts 1 ENABLED Enable Endpoint 3 IN interrupts 2 IN2bE 1 RW IN Endpoint 2 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 2 IN interrupts 1 ENABLED Enable Endpoint 2 IN interrupts 1 INTE 1 RW IN Endpoint 1 Interrupt Enable Value Name Description 0 DISABLED Disable Endpoint 1 IN interrupts
323. system clocks Table 14 3 Watchdog Timer Timeout Intervals System Clock Hz PCAOCPL4 Timeout Interval ms 24 500 000 255 32 1 24 500 000 128 16 2 24 500 000 32 4 1 3 062 500 255 257 3 062 500 128 129 5 3 062 500 32 33 1 32 000 255 24576 32 000 128 12384 32 000 32 3168 Note The values in this table assume SYSCLK 12 as the PCA clock source and a PCAOL value of 0x00 at the update time silabs com Smart Connected Energy friendly Rev 0 2 147 EFM8UB2 Reference Manual Programmable Counter Array 14 4 PCAO Control Registers 14 4 1 PCAOCNO PCA Control 0 Bit 7 6 5 4 3 2 1 0 Name CF CR Reserved CCF4 CCF3 CCF2 CCF1 CCFO Access RW RW R RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 SFR Page ALL SFR Address 0xD8 bit addressable Bit Name Reset Access Description 7 CF 0 RW PCA Counter Timer Overflow Flag Set by hardware when the PCA Counter Timer overflows from OxFFFF to 0x0000 When the Counter Timer Overflow CF interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automati cally cleared by hardware and must be cleared by firmware 6 CR 0 RW PCA Counter Timer Run Control This bit enables disables the PCA Counter Timer Value Name Description 0 STOP Stop the PCA Counter Timer 1 RUN Start the PCA Counter Timer running 5 Reserved
324. t to be correct When in Mode 2 Timer 1 operates identically to Timer O The overflow rate for Timer 0 in 8 bit auto reload mode is F F input Clock Finput Clock TIMERO 28 THO 256 THO Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TRO bit enables the timer when either GATEO in the TMOD register is logic 0 or when the input signal INTO is active as defined by bit INOPL in register ITO1CF Pre scaled Clock SYSCLK TFO Interrupt Flag INTO THO 8 bits Figure 19 2 TO Mode 2 Block Diagram silabs com Smart Connected Energy friendly Rev 0 2 252 EFM8UB2 Reference Manual Timers TimerO 1 2 Timer3 Timer4 and Timer5 Mode 3 Two 8 bit Counter Timers Timer 0 Only In Mode 3 Timer 0 is configured as two separate 8 bit counter timers held in TLO and THO The counter timer in TLO is controlled using the Timer 0 control status bits in TCON and TMOD TRO CTO GATEO and TFO TLO can use either the system clock or an external input signal as its timebase The THO register is restricted to a timer function sourced by the system clock or prescaled clock THO is enabled using the Timer 1 run control bit TR1 THO sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 inter rupt The overflow rate for Timer 0 Low 8 bit mode is F F input Clock Finput Clock TIMERO 28 TLO 256 TLO The ov
325. t value 5 0 AMXON 0x00 RW AMUXO Negative Input Selection Selects the negative input channel for ADCO For reserved bit combinations no input is selected silabs com Smart Connected Energy friendly Rev 0 2 125 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 4 11 REFOCN Voltage Reference Control Bit 7 6 4 3 2 1 0 REFBGS Reserved REGOVR REFSL TEMPE Reserved REFBE Access RW R RW RW RW RW RW Reset 0 0x0 0 0 0 0 0 SFR Page ALL SFR Address 0xD1 Bit Name Reset Access Description 7 REFBGS 0 RW Reference Buffer Gain Select This bit selects between 1x and 2x gain for the on chip voltage reference buffer Value Name Description 0 GAIN_2 The on chip voltage reference buffer gain is 2 1 GAIN_1 The on chip voltage reference buffer gain is 1 6 5 Reserved Must write reset value 4 REGOVR 0 RW Regulator Reference Override This bit overrides the REFSL bit and allows the internal regulator to be used as a reference source Value Name Description 0 REFSL The REFSL bit selects the voltage reference source 1 VREG Use the output of the internal regulator as the voltage reference source 3 REFSL 0 RW Voltage Reference Select This bit selects the ADC voltage reference Value Name Description 0 VREF Use the VREF pin as the voltage reference 1 VDD Use VDD as the voltage reference 2 TEMPE 0 RW Tempera
326. t write reset value 3 T5SPLIT 0 RW Timer 5 Split Mode Enable When this bit is set Timer 5 operates as two 8 bit timers with auto reload Value Name Description 0 16 BIT RELOAD Timer 5 operates in 16 bit auto reload mode 1 8 BIT RELOAD Timer 5 operates as two 8 bit auto reload timers 2 TR5 0 RW Timer 5 Run Control Timer 5 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR5H only is always enabled split mode 1 Reserved Must write reset value 0 T5XCLK 0 RW Timer 5 External Clock Select T5XCLK selects the external clock source for Timer 5 If Timer 5 is in 8 bit mode T5XCLK selects the external oscillator clock source for both timer bytes However the Timer 5 Clock Select bits T5MH and T5ML may still be used to select between the external clock and the system clock for either timer Value Name Description 0 SYSCLK DIV 12 Timer 5 clock is the system clock divided by 12 1 EXTOSC DIV 8 Timer 5 clock is the external oscillator divided by 8 synchronized with SYSCLK silabs com Smart Connected Energy friendly Rev 0 2 275 EFM8UB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 25 TMRSRLL Timer 5 Reload Low Byte Bit 7 6 5 4 3 2 1 0 TMRSRLL Access RW Reset 0 00 SFR Page OxF SFR Address 0xCA Bit Name Reset Access Description 7 0 TMRSRLL 0x00 RW Timer 5 Reload Low Byte When oper
327. tch es are reset to 1 in open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to an internal oscillator The Watchdog Timer is enabled and program execution begins at location 0x0000 Reset sources on the device include Power on reset External reset pin Comparator reset Software triggered reset Supply monitor reset monitors VDD supply Watchdog timer reset Missing clock detector reset Flash error reset USBreset 1 9 Debugging The EFM8UB2 devices include an on chip Silicon Labs 2 Wire C2 debug interface to allow flash programming and in system debug ging with the production part installed in the end application The C2 interface uses a clock signal C2CK and a bi directional C2 data signal C2D to transfer information between the device and a host system See the C2 Interface Specification for details on the C2 protocol 1 10 Bootloader All devices come pre programmed with a USB bootloader This bootloader resides in flash and can be erased if it is not needed silabs com Smart Connected Energy friendly Rev 0 2 6 EFM8UB2 Reference Manual Memory Organization 2 Memory Organization 2 1 Memory Organization The memory organization of the CIP 51 System Controller is similar
328. te TMRSL Timer 5 Low Byte Timer 5 High Byte 20 1 Introduction 20 2 Features 20 3 Functional Description 20 3 1 Baud Rate Generation 20 3 2 Data Format 20 3 3 Data Transfer 20 3 4 Multiprocessor Cueto 20 4 UARTO Control Registers 20 4 1 SCONO UARTO Serial Port Control 20 4 2 SBUFO UARTO Serial Port Data Buffer Universal Asynchronous Receiver Transmitter 1 UART1 21 1 Introduction 21 2 Features 21 3 Functional Description 21 3 1 Baud Rate Generation 21 3 2 Data Format 21 3 3 Basic Data Transfer 21 3 4 Multiprocessor Communications 21 4 UART1 Control Registers 21 4 1 SCON1 UART1 Serial Port Control 21 4 2 SMOD1 UART1 Mode 21 4 3 SBUF1 UART1 Serial Port Data Buffer 21 4 4 SBCON1 UART1 Baud Rate Generator Control 21 4 5 SBRLH1 UART1 Baud Rate Generator High Byte 21 4 6 SBRLL1 UART1 Baud Rate Generator Low Byte C2 Debug and Programming Interface 22 1 Introduction 22 2 Features 22 3 Pin Sharing 22 4 C2 Interface Registers 22 4 1 C2ADD C2 Address 22 4 2 C2DEVID C2 Device ID 22 4 3 C2REVID C2 Revision ID 272 273 273 273 274 275 276 276 276 277 278 278 278 279 279 279 280 280 281 281 282 283 283 283 284 284 284 284 285 286 286 288 289 290 290 291 292 292 292 292 293 293 293 293 304 22 4 4 C2FPCTL C2
329. terrupt pipe can be shut down or Halted by writing 1 to the SDSTL bit EINCSRL 4 While SDSTL 1 hardware will respond to all IN requests with a STALL condition Each time hardware generates a STALL condition an interrupt will be generated and the STSTL bit set to 1 The STSTL bit must be reset to 0 by firmware Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO If double buffering is enabled for the target endpoint it is possible for firmware to load two packets into the IN FIFO at a time In this case hardware will reset INPRDY to 0 immediately after firmware loads the first packet into the FIFO and sets INPRDY to 1 An interrupt will not be generated in this case an interrupt will only be generated when a data packet is transmitted When firmware writes 1 to the FCDT bit the data toggle for each IN packet will be toggled continuously regardless of the handshake received from the host This feature is typically used by Interrupt endpoints functioning as rate feedback communication for Isochronous endpoints When FCDT 0 the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet silabs com Smart Connected Energy friendly Rev 0 2 188 EFM8UB2 Reference Manual Universal Serial Bus USBO Operating Endpoints 1 3 as IN Isochronous Endpoints When the ISO bit is set to 1 the target endpoint operates Isochronous ISO mode Once an endpo
330. the ADCO start of conversion source All remaining bit combinations are reserved silabs com Smart Connected Energy friendly Value Name Description 0x0 ADBUSY ADCO conversion initiated on write of 1 to ADBUSY 0x1 TIMERO ADCO conversion initiated on overflow of Timer 0 0x2 TIMER2 ADCO conversion initiated on overflow of Timer 2 0x3 TIMER1 ADCO conversion initiated on overflow of Timer 1 0 4 CNVSTR ADCO conversion initiated on rising edge of CNVSTR 0 5 TIMER3 ADCO conversion initiated on overflow of Timer 3 0 6 TIMER4 ADCO conversion initiated on overflow of Timer 4 Rev 0 2 124 EFM8UB2 Reference Manual Analog to Digital Converter ADCO Reset Access Description 0x7 TIMER5 ADCO conversion initiated on overflow of Timer 5 12 4 9 AMUXO Positive Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Reserved AMXOP Access R RW Reset 0x0 0x00 SFR Page ALL SFR Address 0xBB Bit Name Reset Access Description 7 6 Reserved Must write reset value 5 0 AMXOP 0x00 RW AMUXO Positive Input Selection Selects the positive input channel for ADCO For reserved bit combinations no input is selected 12 4 10 AMXON AMUX0 Negative Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Reserved AMXON Access R RW Reset 0x0 0x00 SFR Page ALL SFR Address Bit Name Reset Access Description 7 6 Reserved Must write rese
331. the instruction that sets the IDLE bit the CPU may not wake from idle mode when a future interrupt occurs Therefore instructions that set the IDLE bit should be followed by an instruction that has two or more opcode bytes For example f xu OUS PCONO 0x01 set IDLE bit PCONO PCONO followed by a 3 cycle dummy instruction in assembly ORL PCONO 01h set IDLE bit MOV PCONO followed by a 3 cycle dumuy instruction If enabled the Watchdog Timer WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode This fea ture protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCONO register If this behavior is not desired the WDT may be disabled by software prior to entering the idle mode if the WDT was initially configured to allow this operation This provides the opportunity for additional power savings allowing the system to remain in the idle mode indefi nitely waiting for an external stimulus to wake up the system silabs com Smart Connected Energy friendly Rev 0 2 43 EFM8UB2 Reference Manual Power Management and Internal Regulators 7 4 Stop Mode In stop mode the CPU is halted and peripheral clocks are stopped Analog peripherals remain in their selected states Setting the STOP bit in the PCONO register causes the controller core to enter stop mode as soon as the instruction that sets the bit completes e
332. the module is set each time a match edge or up edge occurs The CF flag in PCAOCNO can be used to detect the overflow or down edge Important When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMnh bit to 0 writing to PCAOCPHn sets ECOMn to 1 14 3 9 Watchdog Timer Mode A programmable watchdog timer WDT function is available through the last PCA module module 4 The WDT is used to generate a reset if the time between writes to the WDT update register PCAOCPH4 exceed a specified limit The WDT can be configured and enabled disabled as needed by software With the WDTE bit set in the PCAOMD register the last module operates as a watchdog timer WDT The module 4 high byte is compared to the PCA counter high byte the module 4 low byte holds the offset to be used when WDT updates are performed The Watchdog Timer is enabled on reset Writes to some PCA registers are restricted while the Watch dog Timer is enabled The WDT will generate a reset shortly after code begins execution To avoid this reset the WDT should be ex plicitly disabled and optionally re configured and re enabled if it is used in the system silabs com Smart Connected Energy friendly Rev 0 2 145 EFM8UB2 Reference Manual Programmable Counter Array Watchdog Timer Operation While the WDT is enabled PCA counter is forced on Writes to PCAOL an
333. tile data stor age 2 3 Data Memory The RAM space on the chip includes both an internal RAM area which is accessed with MOV instructions and an on chip external RAM area which is accessed using MOVX instructions Total RAM varies based on the specific device The device memory has more details about the specific amount of RAM available in each area for the different device variants Internal RAM There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through OxFF The lower 128 bytes of data memo ry are used for general purpose registers and scratch pad memory Either direct or indirect addressing may be used to access the lower 128 bytes of data memory Locations 0 00 through Ox1F are addressable as four banks of general purpose registers each bank con sisting of eight byte wide registers The next 16 bytes locations 0x20 through Ox2F may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode The upper 128 bytes of data memory are accessible only by indirect addressing This region occupies the same address space as the Special Function Registers SFR but is physically separate from the SFR space The addressing mode used by an instruction when accessing locations above Ox7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs In structions that use direct addressing will access the SFR space Instructions using indirect addres
334. tine and must be cleared by software If both CAPPn and CAPNn bits are set to logic 1 then the state of the port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused the capture CCFn Interrupt Flag CAPPn PCAOCPLn PCAOCPHn CEXn CAPNn PCA Clock gt Figure 14 2 PCA Capture Mode Diagram Note The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware silabs com Smart Connected Energy friendly Rev 0 2 140 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 3 5 Software Timer Compare Mode In Software Timer mode the PCA counter timer value is compared to the module s 16 bit capture compare register PCAOCPHn and PCAOCPLn When a match occurs the Capture Compare Flag CCFn in PCAOCNO is set to logic 1 An interrupt request is generated if the CCFn interrupt for that module is enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and it must be cleared by software Setting the ECOMn and bits in the PCAOCPMn register enables Software Timer mode Note When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 PCAOCPLn PCAOCPHn MATn Match Enable ECOMn Co
335. tion mode is enabled Value Name Description 0 8 BIT 8 bit PWM selected 1 16_BIT 16 bit PWM selected 6 ECOM 0 RW Channel 1 Comparator Function Enable This bit enables the comparator function 5 CAPP 0 RW Channel 1 Capture Positive Function Enable This bit enables the positive edge capture capability 4 CAPN 0 RW Channel 1 Capture Negative Function Enable This bit enables the negative edge capture capability 3 MAT 0 RW Channel 1 Match Function Enable This bit enables the match function When enabled matches of the PCA counter with a module s capture compare register cause the CCF 1 bit in the PCAOMD register to be set to logic 1 2 TOG 0 RW Channel 1 Toggle Function Enable This bit enables the toggle function When enabled matches of the PCA counter with the capture compare register cause the logic level on the CEX1 pin to toggle If the PWM bit is also set to logic 1 the module operates in Frequency Output Mode 1 PWM 0 RW Channel 1 Pulse Width Modulation Mode Enable This bit enables the PWM function When enabled a pulse width modulated signal is output on the CEX1 pin 8 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel 1 Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCF1 interrupt Value Name Description 0 DISABLED Disable CCF1 interrupts 1 ENABLED
336. tion table for more information 10 2 Features The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability The CIP 51 includes the following features Fast efficient pipelined architecture Fully compatible with MCS 51 instruction set 0 to 50 MHz operating clock frequency 50 MIPS peak throughput with 50 MHz clock Extended interrupt handler Power management modes On chip debug logic Program and data memory security 10 3 Functional Description 10 3 1 Programming and Debugging Support In system programming of the flash program memory and communication with on chip debug support logic is accomplished via the Sili con Labs 2 Wire development interface C2 The on chip debug support logic facilitates full speed in circuit debugging allowing the setting of hardware breakpoints starting stop ping and single stepping through program execution including interrupt service routines examination of the program s call stack and reading writing the contents of registers and memory This method of on chip debugging is completely non intrusive requiring no RAM stack timers or other on chip resources The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs provides an integrated develop ment environment IDE including editor debugger and programmer The
337. to port I O when enabled 16 bit time base Programmable clock divisor and clock source selection Upto five independently configurable channels 8 or 16 bit PWM modes edge aligned operation Frequency output mode Capture on rising falling or any edge Compare function for arbitrary waveform generation Software timer internal compare mode Integrated watchdog timer Timers Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 and Timer 5 Several counter timers are included in the device two are 16 bit counter timers compatible with those found in the standard 8051 and the rest are 16 bit auto reload timers for timing peripherals or for general purpose use These timers can be used to measure time inter vals count external events and generate periodic interrupt requests Timer O and Timer 1 are nearly identical and have four primary modes of operation The other timers offer both 16 bit and split 8 bit timer functionality with auto reload and capture capabilities Timer 0 and Timer 1 include the following features Standard 8051 timers supporting backwards compatibility with firmware and hardware Clock sources include SYSCLK SYSCLK divided by 12 4 or 48 the External Clock divided by 8 or an external pin 8 bit auto reload counter timer mode 13 bit counter timer mode 16 bit counter timer mode Dual 8 bit counter timer mode Timer 0 Timer 2 Timer 3 Timer 4 and Timer 5 are 16 bit timers including th
338. to that of a standard 8051 There are two separate memory spaces program memory and data memory Program and data memory share the same address space but are accessed via different instruction types Program memory consists of a non volatile storage area that may be used for either program code or non volatile data storage The data memory consisting of internal and external data space is implemented as RAM and may be used only for data storage Program execution is not supported from the data memory space 2 2 Program Memory The CIP 51 core has a 64 KB program memory space The product family implements some of this program memory space as in sys tem re programmable flash memory Flash security is implemented by a user programmable location in the flash block and provides read write and erase protection All addresses not specified in the device memory map are reserved and may not be used for code or data storage MOVX Instruction and Program Memory The MOVX instruction in an 8051 device is typically used to access external data memory On the devices the MOVX instruction is normally used to read and write on chip XRAM but can be re configured to write and erase on chip flash memory space MOVC in structions are always used to read flash memory while MOVX write instructions are used to erase and write flash This flash access feature provides a mechanism for the product to update program code and use the program memory space for non vola
339. tor reset Software triggered reset Supply monitor reset monitors VDD supply Watchdog timer reset Missing clock detector reset Flash error reset USBreset silabs com Smart Connected Energy friendly Rev 0 2 61 EFM8UB2 Reference Manual Reset Sources and Power Supply Monitor 9 3 Functional Description 9 3 1 Device Reset Upon entering a reset state from any source the following events occur The processor core halts program execution Special Function Registers SFRs are initialized to their defined reset values External port pins are placed a known state Interrupts and timers are disabled SFRs are reset to the predefined reset values noted in the detailed register descriptions The contents of internal data memory are unaffected during a reset any previously stored data is preserved However since the stack pointer SFR is reset the stack is effective ly lost even though the data on the stack is not altered The port I O latches are reset to OxFF all logic ones open drain mode Weak pullups are enabled during and after the reset For Supply Monitor and power on resets the RSTb pin is driven low until the device exits the reset state Note During a power on event there may be a short delay before the POR circuitry fires and the RSTb pin is driven low During that time the RSTb pin will be weakly pulled to the supply pin On exit from the reset state the program counter
340. tput Mode 11 4 7 POSKIP Port 0 Skip 11 4 8 P1 Port 1 Pin Latch 11 4 9 P1MDIN Port 1 Input Mode 11 4 10 P1MDOUT Port 1 Output Mode 11 4 11 P1SKIP Port 1 Skip 11 4 12 P2 Port 2 Pin Latch 11 4 13 P2MDIN Port 2 Input Mode 11 4 14 P2MDOUT Port 2 Output Mode 11 4 15 P2SKIP Port 2 Skip 11 4 16 P3 Port 3 Pin Latch 11 4 17 P3MDIN Port 3 Input Mode 11 4 18 P3MDOUT Port 3 Output Mode 11 4 19 P3SKIP Port 3 Skip 11 4 20 P4 Port 4 Pin Latch 11 4 21 P4MDIN Port 4 Input Mode 11 4 22 PAMDOUT Port 4 Output Mode 11 5 INTO and INT1 Control Registers 11 5 1 ITO1CF INTO INT1 Configuration Analog to Digital Converter ADCO 12 1 Introduction 12 2 Features 12 3 Functional Description 12 3 1 Clocking 12 3 2 Voltage Reference Options 12 3 2 1 Internal Voltage Reference fox 12 3 2 2 Supply or LDO Voltage Reference 12 3 2 3 External Voltage Reference 12 3 3 Input Selection 12 3 3 1 Multiplexer Channel Selection 12 3 4 Initiating Conversions 12 3 5 Input Tracking 12 3 6 Output Formatting 12 3 7 Window Comparator 12 3 8 Temperature Sensor 12 3 8 1 Temperature Sensor Calibration 12 4 ADCO Control Registers i 12 4 1 ADCOCF ADCO Configuration 12 4 2 ADCOH ADCO Data Word High Byte 12 4 3 ADCOL ADCO Data Word Low Byte 12 4 4 ADCOGTH ADCO Greater Than High Byte 12 4 5 ADCOGTL ADCO Greater Than Low Byte 12 4 6 ADCOLTH ADCO Less Than High Byte 12 4 7 ADCOLTL A
341. ture Sensor Enable Enables Disables the internal temperature sensor Value Name Description 0 DISABLED Disable the internal Temperature Sensor 1 ENABLED Enable the internal Temperature Sensor 1 Reserved Must write reset value 0 REFBE 0 RW Internal Reference Buffer Enable Value Name Description 0 DISABLED Disable the internal reference buffer 1 ENABLED Enable the internal reference buffer The internal voltage reference is driven on the VREF pin silabs com Smart Connected Energy friendly Rev 0 2 126 EFM8UB2 Reference Manual Comparators and 1 13 Comparators 0 and 1 13 1 Introduction Analog comparators are used to compare the voltage of two analog inputs with a digital output indicating which input voltage is higher External input connections to device I O pins and internal connections are available through separate multiplexers on the positive and negative inputs Hysteresis response time and current consumption may be programmed to suit the specific needs of the application Positive Input Selection Programmable Hysteresis Port Pins CPnA asynchronous Internal LDO CPn synchronous SYSCLK p gt Port Pins GND Programmable Negative Input Response Time Selection Figure 13 1 Comparator Block Diagram 13 2 Features The comparator module includes the following features Up to 5 external positive inputs Up to 5 external negati
342. tures Asynchronous transmissions and receptions Dedicated baud rate generator supports baud rates up to SYSCLK 2 transmit or SYSCLK 8 receive 5 6 7 8 or 9 bit data Automatic start and stop generation Automatic parity generation and checking Three byte FIFO on receive silabs com Smart Connected Energy friendly Rev 0 2 283 EFM8UB2 Reference Manual Universal Asynchronous Receiver Transmitter 1 UART1 21 3 Functional Description 21 3 1 Baud Rate Generation The UART1 baud rate is generated by a dedicated 16 bit timer which runs from the controller s core clock SYSCLK and has prescaler options of 1 4 12 or 48 The timer and prescaler options combined allow for a wide selection of baud rates over many SYSCLK fre quencies The baud rate generator is configured using three registers SBCON1 SBRLH1 and SBRLL1 The SBCON1 register enables or disa bles the baud rate generator and selects the prescaler value for the timer The baud rate generator must be enabled for UART1 to function Registers SBRLH1 and SBRLL1 constitute a 16 bit reload value SBRL1 for the dedicated 16 bit timer The internal timer counts up from the reload value on every clock tick On timer overflows OxFFFF to 0x0000 the timer is reloaded For reliable UART receive operation it is typically recommended that the UART baud rate does not exceed SYSCLK 16 Figure 21 2 Baud Rate Generation 21 3 2 Data Format UART1 has
343. ure corners accurate to 0 25 when using USB clock recovery 80 kHz low frequency oscillator LFOSCO External RC C CMOS and high frequency crystal clock options EXTCLK for QFP48 packages External CMOS clock option EXTCLK for QFP32 and QFN32 packages Internal oscillator has clock divider with eight settings for flexible clock scaling 1 2 4 or 8 8 3 Functional Description 8 3 1 Clock Selection The CLKSEL register is used to select the clock source for the system SYSCLK The CLKSL field selects which oscillator source is used as the system clock while CLKDIV controls the programmable divider When an internal oscillator source is selected as the SYSCLK the external oscillator may still clock certain peripherals In these cases the external oscillator source is synchronized to the SYSCLK source The system clock may be switched on the fly between any of the oscillator sources so long as the selected clock source is enabled and has settled and CLKDIV may be changed at any time Note Some device families do place restrictions on the difference in operating frequency when switching clock sources Please see the CLKSEL register description for details 8 3 2 HFOSCO 48 MHz Internal Oscillator HFOSCO is a programmable internal high frequency oscillator that is factory calibrated to 48 MHz The oscillator is automatically ena bled when it is requested The oscillator period can be adjusted via the HFOOCAL register t
344. urpose port I O pins be used to select multiple slave devices in master mode SCK Phase Master or Slave SCK Polarity NSS Control XI NSS DX SYSCLK Clock Rate Generator Bus Control SCK MISO Shift Register MOSI TX Buffer RX Buffer SPIODAT Figure 17 1 SPI Block Diagram 17 2 Features The SPI module includes the following features Supports 3 or 4 wire operation in master or slave modes Supports external clock frequencies up to SYSCLK 2 in master mode and SYSCLK 10 in slave mode Support for four clock phase and polarity options 8 bit dedicated clock clock rate generator Support for multiple masters on the same data lines silabs com Smart Connected Energy friendly Rev 0 2 212 EFM8UB2 Reference Manual Serial Peripheral Interface SPIO 17 3 Functional Description 17 3 1 Signals The SPI interface consists of up to four signals MOSI MISO SCK and NSS Master Out Slave In MOSI The MOSI signal is the data output pin when configured as a master device and the data input pin when configured as a slave It is used to serially transfer data from the master to the slave Data is transferred on the MOSI pin most signifi cant bit first When configured as a master MOSI is driven from the internal shift register in both 3 and 4 wire mode Master In Slave Out MISO The MISO signal is the data input pin when configured as a master device
345. us divider options By default the clock to the USB module is turned off to save power Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator this allows the internal oscillator to meet the requirements for USB clock tolerance Clock Recovery should always be used any time the USB block is clocked from the internal HFOSC1 clock in full speed applications When operating the USB module as a low speed function with Clock Recovery software must write 1 to the CRLOW bit to enable low speed Clock Recovery Clock Recovery is typically not necessary in low speed mode Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network This mode is not required or recommended in typical USB environments silabs com Smart Connected Energy friendly Rev 0 2 55 EFM8UB2 Reference Manual Clocking and Oscillators 8 4 Clocking and Oscillator Control Registers 8 4 1 CLKSEL Clock Select Bit 7 6 5 4 3 2 1 0 Reserved USBCLK OUTCLK CLKSL Access R RW RW RW Reset 0 0x0 0 0x0 SFR Page ALL SFR Address 0xA9 Bit Name Reset Access Description 7 Reserved Must write reset value 6 4 USBCLK 0x0 RW USB Clock Source Select Bits Value Name Description 0x0 HFOSC USB clock USBCLK derived from the Internal High Frequency Oscillator 0 1 HFOSC_DIV_8 USB clock USBCLK derived from the Internal High F
346. ut pin TO increment the timer register Events with a frequency of up to one fourth the system clock frequency can be counted The input signal need not be periodic but it must be held at a given level for at least two full system clock cycles to ensure the level is properly sampled Clearing CT selects the clock defined by the TOM bit in register CKCONO When TOM is set Timer 0 is clocked by the system clock When is cleared Timer 0 is clocked by the source selected by the Clock Scale bits in CKCONO Setting the TRO bit enables the timer when either GATEO in the TMOD register is logic O or based on the input signal INTO The INOPL bit setting in ITO1TCF changes which state of INTO input starts the timer counting Setting GATEO to 1 allows the timer to be controlled by the external input signal INTO facilitating pulse width measurements Table 19 3 Timer 0 Run Control Options TRO GATEO INTO INOPL Counter Timer 0 X X X Disabled 1 0 X X Enabled 1 1 0 0 Disabled 1 1 0 1 Enabled 1 1 1 0 Enabled 1 1 1 1 Disabled Note 1 X Don t Care Setting TRO does not force the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as described above for TLO and THO Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0 The input signal IN
347. utput on the CEX3 pin 8 bit PWM is used if PWM16 is cleared to 0 16 bit mode is used if PWM16 is set to 1 If the TOG bit is also set the module operates in Frequency Output Mode 0 ECCF 0 RW Channel 3 Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCF3 interrupt Value Name Description 0 DISABLED Disable CCF3 interrupts 1 ENABLED Enable a Capture Compare Flag interrupt request when CCF3 is set silabs com Smart Connected Energy friendly Rev 0 2 157 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 4 15 PCAOCPL3 PCA Channel 3 Capture Module Low Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address 0xED Bit Name Reset Access Description 7 0 PCAOCPL3 0x00 RW PCA Channel 3 Capture Module Low Byte The PCAOCPL3 register holds the low byte LSB of the 16 bit capture module write to this register will clear the module s ECOM bit to a 0 14 4 16 PCAOCPH3 PCA Channel 3 Capture Module High Byte Bit 7 6 5 4 3 2 1 0 Access RW Reset 0x00 SFR Page ALL SFR Address OxEE Bit Name Reset Access Description 7 0 PCAOCPH 0x00 RW PCA Channel 3 Capture Module High Byte 3 The PCAOCPHG register holds the high byte MSB of the 16 bit capture module A write to this register will set the module s ECOM bit
348. value in pF and R the pull up resistor value p 1 23 x 10 Figure 8 6 RC Mode Oscillator Frequency For example if the frequency desired is 100 kHz let R 246 kO and C 50 pF ro 123 10 _ 1 23 x 109 246 50 Figure 8 7 RC Mode Oscillator Example 100 kHz Referencing the recommended XFCN setting for 100 kHz is 010 When the RC oscillator is first enabled the external oscillator valid detector allows firmware to determine when oscillation has stabi lized The recommended procedure for starting the RC oscillator is as follows 1 Configure XTAL2 for analog I O and disable the digital output drivers 2 Configure and enable the external oscillator 3 Poll for XCLKVLD 1 4 Switch the system clock to the external oscillator silabs com Smart Connected Energy friendly Rev 0 2 53 EFM8UB2 Reference Manual Clocking and Oscillators External Capacitor Example If a capacitor is used as the external oscillator the circuit should be configured as shown in The capacitor should be added to XTAL2 XTAL2 should be configured for analog I O with the digital output drivers disabled XTAL1 is not affected in C mode XTAL1 XTAL2 i Figure 8 8 External Capacitor Oscillator Configuration The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasit ic capacitance in the PCB layout The oscil
349. ve inputs Synchronous and asynchronous outputs can be routed to pins via crossbar Programmable hysteresis between 0 and 20 mV Programmable response time Interrupts generated on rising falling or both edges 13 3 Functional Description 13 3 1 Response Time and Supply Current Response time is the amount of time delay between a change at the comparator inputs and the comparator s reaction at the output The comparator response time may be configured in software via the CPMD field in the CMPnMD register Selecting a longer response time reduces the comparator supply current while shorter response times require more supply current silabs com Smart Connected Energy friendly Rev 0 2 127 EFM8UB2 Reference Manual Comparators and 1 13 3 2 Hysteresis The comparator hysteresis is software programmable via its Comparator Control register CMPnCN The user can program both the amount of hysteresis voltage referred to the input voltage and the positive and negative going symmetry of this hysteresis around the threshold voltage The comparator hysteresis is programmable using the CPHYN and CPHYP fields in the Comparator Control Register CMPnCN The amount of negative hysteresis voltage is determined by the settings of the CPHYN bits Settings of 20 10 or 5 mV nominal of nega tive hysteresis can be programmed or negative hysteresis can be disabled In a similar way the amount of positive hysteresis is dete
350. ved Access RW RW RW RW Reset 0 0x0 0 0x0 SFR Page ALL SFR Address 0x9E Bit Name Reset Access Description 7 Reserved Must write reset value 6 4 CMXN 0 0 RW Comparator Negative Input MUX Selection This field selects the negative input for the comparator 3 Reserved Must write reset value 2 0 0 0 RW Comparator Positive Input MUX Selection This field selects the positive input for the comparator silabs com Smart Connected Energy friendly Rev 0 2 136 EFM8UB2 Reference Manual Programmable Counter Array PCAO 14 Programmable Counter Array 0 14 1 Introduction The programmable counter array PCA provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter timers The PCA consists of a dedicated 16 bit counter timer and one 16 bit capture compare mod ule for each channel The counter timer is driven by a programmable timebase that has flexible external and internal clocking options Each capture compare module may be configured to operate independently in one of five modes Edge Triggered Capture Software Timer High Speed Output Frequency Output or Pulse Width Modulated PWM Output Each capture compare module has its own associated I O line CEXn which is routed through the crossbar to port I O when enabled SYSCLK SYSCLK 4 SYSCLK 12 PCN CON ET Control Interrupt
351. ved Must write reset value 12 4 2 ADCOH ADCO Data Word High Byte Bit 7 6 5 4 3 2 1 0 ADCOH Access RW Reset 0x00 SFR Page ALL SFR Address 0xBE Reset Access Description 7 0 ADCOH 0x00 RW Data Word High Byte When read this register returns the most significant byte of the 16 bit ADC data holding register ADCOH L formatted ac cording to the settings in ADLJST Any unused bits for right justified results will be zeroes silabs com Smart Connected Energy friendly Rev 0 2 121 EFM8UB2 Reference Manual Analog to Digital Converter ADCO 12 4 3 ADCOL ADCO Data Word Low Byte Bit 7 6 5 4 3 2 1 0 ADCOL Access RW Reset 0x00 SFR Page ALL SFR Address 0xBD Bit 7 0 Name Reset Access Description ADCOL 0x00 RW Data Word Low Byte When read this register returns the least significant byte of the 16 bit ADC data holding register ADCOH L formatted ac cording to the settings in ADLJST Any unused bits for left justified results will be zeroes 12 4 4 ADCOGTH ADCO Greater Than High Byte Bit 7 6 5 4 3 2 1 0 ADCOGTH Access RW Reset OxFF SFR Page ALL SFR Address 0xC4 Bit 7 0 Name Reset Access Description ADCOGTH OxFF RW Greater Than High Byte Most Significant Byte of the 16 bit Greater Than window compare register 12 4 5 ADCOGTL ADCO Greater Than Low Byte
352. ved Reserved 100001 ADCON 33 P4 2 Reserved Reserved 100010 ADCON 34 P4 7 Reserved Reserved 100011 111111 ADCON 35 ADCON 63 Reserved Reserved Reserved 12 3 4 Initiating Conversions A conversion can be initiated in many ways depending on the programmed state of the ADCM bitfield Conversions may be initiated by one of the following 1 Software triggered Writing a 1 to the ADBUSY bit initiates the conversion 2 Hardware triggered An automatic internal event such as a timer overflow initiates the conversion 3 External pin triggered A rising edge on the CNVSTR input signal initiates the conversion Writing a 1 to ADBUSY provides software control of ADCO whereby conversions are performed on demand All other trigger sources occur autonomous to code execution When the conversion is complete the ADC posts the result to its output register and sets the ADC interrupt flag ADINT ADINT may be used to trigger a system interrupts if enabled or polled by firmware During a conversion the ADBUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete However the ADBUSY bit should not be used to poll for ADC conversion completion The ADCO interrupt flag ADINT should be used instead of the ADBUSY bit Converted data is available in the ADCO data registers ADCOH ADCOL when the conversion is complete Note The CNVSTR pin is a multi function GPIO pin When the CNVSTR input is used as the ADC conve
353. when the low byte of Timer 4 overflows 4 Reserved Must write reset value 3 TASPLIT 0 RW Timer 4 Split Mode Enable When this bit is set Timer 4 operates as two 8 bit timers with auto reload Value Name Description 0 16 BIT RELOAD Timer 4 operates in 16 bit auto reload mode 1 8 BIT RELOAD Timer 4 operates as two 8 bit auto reload timers 2 4 0 RW Timer 4 Run Control Timer 4 is enabled by setting this bit to 1 In 8 bit mode this bit enables disables TMR4H only TMR4L is always enabled split mode 1 Reserved Must write reset value 0 TAXCLK 0 RW Timer 4 External Clock Select TAXCLK selects the external clock source for Timer 4 If Timer 4 is in 8 bit mode selects the external oscillator clock source for both timer bytes However the Timer 4 Clock Select bits T4MH and T4ML may still be used to select between the external clock and the system clock for either timer Value Name Description 0 SYSCLK DIV 12 Timer 4 clock is the system clock divided by 12 1 EXTOSC DIV 8 Timer 4 clock is the external oscillator divided by 8 synchronized with SYSCLK silabs com Smart Connected Energy friendly Rev 0 2 272 EFM8UB2 Reference Manual Timers TimerO Timer1 Timer2 Timer3 Timer4 and Timer5 19 4 20 TMR4RLL Timer 4 Reload Low Byte Bit 7 6 5 4 3 2 1 0 TMR4RLL Access RW Reset 0x00 SFR Page OxF SFR Address 0x92 Bit Name Reset Access Description 7
354. ws block writes to Flash memory from firmware Value Name Description 0 BLOCK WRITE DISA Each byte of a firmware flash write is written individually BLED 1 BLOCK WRITE ENA Flash bytes are written in groups of two BLED silabs com Smart Connected Energy friendly Rev 0 2 77 EFM8UB2 Reference Manual Port I O Crossbar and External Interrupts 11 Port I O Crossbar and External Interrupts 11 1 Introduction Digital and analog resources are externally available on the device s multi purpose pins Port pins P0 0 P3 7 be defined as gen eral purpose I O GPIO assigned to one of the internal digital resources through the crossbar or dedicated channels or assigned to an analog function Port pins P4 0 P4 7 can be used as GPIO Additionally the C2 Interface Data signal C2D is shared with P3 0 on some packages PO 0 x PO 1 2 x P0 3 P0 4 x P0 5 P0 6 x P0 7 x P1 0 P1 1 P1 2 P1 3 1 4 1 5 1 6 P1 7 x P2 0 4 P2 1 x P2 2 x P2 3 x P2 4 x P2 5 4 P2 6 b P2 7 pj P3 0 x P3 1 P3 2 x P3 3 P3 4 P3 5 x P3 6 x P3 7 4 P4 0 04 P4 1 P4 2 P4 3 P4 4 64 4 5 P4 6 04 P4 7 UARTO Priority Crossbar 4 Decoder SPIO 2 PO P1 P2 P SMBO 2 2 ADCOn CMP1 Out Po P1 P2 P4 3 PCA CEXn CMPO In P1 P2 P3 P4 1 PCA ECI CMP1 In PO P1 P2 P3 P4 1 Timer 0 INTO
355. x2 ENABLED_MODE2 Negative Hysteresis Hysteresis 2 0x3 ENABLED_MODE3 Negative Hysteresis Hysteresis 3 Maximum 13 5 2 CMP1MD Comparator 1 Mode Bit 7 6 5 4 3 2 1 0 Reserved CPRIE CPFIE Reserved CPMD Access R RW RW R RW Reset 0x0 0 0 0x0 0x2 SFR Page ALL SFR Address Ox9C Bit Name Reset Access Description 7 6 Reserved Must write reset value 5 CPRIE 0 RW Comparator Rising Edge Interrupt Enable Value Name Description 0 RISE INT DISABLED Comparator rising edge interrupt disabled 1 RISE INT ENABLED Comparator rising edge interrupt enabled 4 CPFIE 0 RW Comparator Falling Edge Interrupt Enable Value Name Description 0 FALL INT DISABLED Comparator falling edge interrupt disabled 1 FALL INT ENABLED Comparator falling edge interrupt enabled 3 2 Reserved Must write reset value 1 0 CPMD 0x2 RW Comparator Mode Select These bits affect the response time and power consumption of the comparator Value Name Description 0x0 MODEO Mode 0 Fastest Response Time Highest Power Consumption 0 1 MODE1 Mode 1 0x2 MODE2 Mode 2 0x3 MODE3 Mode 3 Slowest Response Time Lowest Power Consumption silabs com Smart Connected Energy friendly Rev 0 2 135 EFM8UB2 Reference Manual Comparators CMPO and 1 13 5 3 1 Comparator 1 Multiplexer Selection Bit 7 6 5 4 3 2 1 0 Reserved CMXN Reser
356. xecution Before entering stop mode the system clock must be sourced by HFOSCO In stop mode the CPU and internal clocks are stopped Analog peripherals may remain enabled but will not be provided a clock Each analog peripheral may be shut down individually by firmware prior to entering stop mode Stop mode can only be terminated by an internal or external reset On reset the device performs the normal reset sequence and begins program execution at address 0x0000 If enabled as a reset source the missing clock detector will cause an internal reset and thereby terminate the stop mode If this reset is undesirable in the system and the CPU is to be placed in stop mode for longer than the missing clock detector timeout the missing clock detector should be disabled in firmware prior to setting the STOP bit 7 5 Suspend Mode Suspend mode is entered by setting the SUSPEND bit while operating from the internal 24 5 MHz oscillator HFOSCO Upon entry into suspend mode the hardware halts the high frequency internal oscillator and goes into a low power state as soon as the instruction that sets the bit completes execution All internal registers and memory maintain their original data Suspend mode is terminated by any enabled wake or reset source When suspend mode is terminated the device will continue execu tion on the instruction following the one that set the SUSPEND bit If the wake event was configured to generate an interrupt the inter rupt wi
357. xternal Memory Interface In Non multiplexed mode the Data Bus and the Address Bus pins are not shared An example of a Non multiplexed Configuration is shown in Figure 15 4 Non Multiplexed Configuration Example on page 166 64 KBx8 A 15 0 Address Bus EMIF Optional D 7 0 Data Bus I O 7 0 os Figure 15 4 Non Multiplexed Configuration Example silabs com Smart Connected Energy friendly Rev 0 2 166 EFM8UB2 Reference Manual External Memory Interface EMIFO 15 3 5 Operating Modes The external data memory space can be configured in one of four operating modes based on the EMIF Mode bits in the EMIOCF regis ter These modes are as follows Internal Only Split Mode without Bank Select Split Mode with Bank Select External Only Timing diagrams for the different modes can be found in the Multiplexed Mode Section Split Mode without Split Mode with Bank Select Bank Select OxFFFF Internal Only External Only OxFFFF OxFFFF OxFFFF On Chip XRAM On Chip XRAM On Chip XRAM Off Chip Memory Off Chip Memory On Chip XRAM On Chip XRAM On Chip XRAM 0x0000 0x0000 0x0000 0x0000 Figure 15 5 EMIF Operating Modes Internal Only In Internal Only mode all instructions will target the internal XRAM space on the device Memory accesses to addresses beyond the populated space will wrap and will always target on chip XRAM As an ex
358. y Hardware resets the FLUSH bit to O when the flush is complete If data for the current packet has already been read from the FIFO the FLUSH bit should not be used to flush the packet Instead the FIFO should be read manually 3 DATERR 0 R Data Error Flag In Isochronous mode this bit is set by hardware if a received packet has a CRC or bit stuffing error It is cleared when firmware clears OPRDY This bit is only valid in Isochronous mode 2 OVRUN 0 RW Data Overrun Flag This bit is set by hardware when an incoming data packet cannot be loaded into the OUT Endpoint FIFO This bit is only valid in Isochronous mode and must be cleared by firmware Value Name Description 0 NOT SET No data overrun 1 SET A data packet was lost because of a full FIFO since this flag was last cleared 1 FIFOFUL 0 R OUT FIFO Full This bit indicates the contents of the OUT FIFO If double buffering is enabled DBIEN 1 the FIFO is full when the FIFO contains two packets If DBIEN 0 the FIFO is full when the FIFO contains one packet Value Name Description 0 NOT FULL OUT endpoint FIFO is not full 1 FULL OUT endpoint FIFO is full 0 OPRDY 0 RW OUT Packet Ready Hardware sets this bit to 1 and generates an interrupt when a data packet is available Firmware should clear this bit after each data packet is read from the OUT endpoint FIFO This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energ
359. y friendly Rev 0 2 209 EFM8UB2 Reference Manual Universal Serial Bus USBO 16 4 26 EOUTCSRH USBO OUT Endpoint Control High Bit 7 6 5 4 3 2 1 0 DBOEN ISO Reserved Access RW RW R Reset 0 0 0x00 Indirect Address 0x15 Bit Name Reset Access Description 7 DBOEN 0 RW Double Buffer Enable Value Name Description 0 DISABLED Disable double buffering for the selected OUT endpoint 1 ENABLED Enable double buffering for the selected OUT endpoint 6 ISO 0 RW Isochronous Transfer Enable This bit enables or disables Isochronous transfers on the current endpoint Value Name Description 0 DISABLED Endpoint configured for Bulk Interrupt transfers 1 ENABLED Endpoint configured for Isochronous transfers 5 0 Reserved Must write reset value This register is accessed indirectly using the USBOADR and USBODAT registers 16 4 27 EOUTCNTL USBO OUT Endpoint Count Low Bit 7 6 5 4 3 2 1 0 EOCL Access R Reset 0x00 Indirect Address 0x16 Bit Name Reset Access Description 7 0 EOCL 0x00 R OUT Endpoint Count Low EOCL holds the lower 8 bits of the 10 bit number of data bytes in the last received packet in the current OUT endpoint FIFO This number is only valid while OPRDY 1 This register is accessed indirectly using the USBOADR and USBODAT registers silabs com Smart Connected Energy friendly Rev 0 2 210
360. ycle can reset the device 2 Reserved Must write reset value silabs com Smart Connected Energy friendly REG1MD 0 RW VREG1 Voltage Regulator Mode This bit selects the Voltage Regulator mode for VREG1 When REG1MD is set to 1 the VREG1 voltage regulator operates in lower power mode This bit should not be set to 1 if the VREGO Voltage Regulator is disabled Rev 0 2 47 EFM8UB2 Reference Manual Power Management and Internal Regulators Bit Name Reset Access Description Value Name Description 0 NORMAL VREG1 Voltage Regulator in normal mode 1 LOW_POWER VREG1 Voltage Regulator in low power mode 0 Reserved Must write reset value silabs com Smart Connected Energy friendly Rev 0 2 48 EFM8UB2 Reference Manual Clocking and Oscillators 8 Clocking and Oscillators 8 1 Introduction The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources By default the system clock comes up running from the 48 MHz oscillator divided by 4 then divided by 8 1 5 MHz Clock Control Divider 48 MHz Oscillator l 1 2 4 8 2156701 SYSCLK To core and peripherals External Oscillator Input EXTCLK 80 kHz Oscillator Divider M delen 1 2 4 8 Figure 8 1 Clock Control Block Diagram 8 2 Features Provides clock to core and peripherals 48 MHz internal oscillator HFOSCO accurate to 1 5 over supply and temperat
361. ypical SMBus transaction silabs com Smart Connected Energy friendly Rev 0 2 225 EFM8UB2 Reference Manual System Management Bus 2 SMBO and 5 1 an SDA SLA6 1 SLA5 0 R W D7 D6 0 START Slave Address R W ACK Data Byte NACK STOP Figure 18 3 SMBus Transaction Transmitter vs Receiver On the SMBus communications interface a device is the transmitter when it is sending an address or data byte to another device on the bus A device is a receiver when an address or data byte is being sent to it from another device on the bus The transmitter con trols the SDA line during the address or data byte After each byte of address or data information is sent by the transmitter the receiver sends an ACK or NACK bit during the ACK phase of the transfer during which time the receiver controls the SDA line Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see e SCL High SMBus Free Timeout on page 226 In the event that two or more devices attempt to begin a transfer at the same time an arbitration scheme is employed to force one master to give up the bus The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW Since the bus is open drain the bus will be pulled LOW The master attempting the HIGH will d

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