CogniBlox Hardware Manual
Contents
1. The switch configuration allows for 3 differential pairs and 2 single ended wires or eight single ended wires The differential pairs can be LVDS They require that the switch between their lines is closed 2 differential 2 5V lines LVDS or else Lattice XP2 2 differential 2 5V lines LVDS or else 2 differential 2 5Vlines LVDS or else CogniBlox Hardware Manual The single ended wires can be used to connect DC SPI or other signals Lattice XP2 8single ended 3 3Vlines 1212 i Cardinal Connector All four cardinal connectors have the following pin assignment Pin Pin Name 1 ser defined 3 3V ser defined 3 3V ser defined 2 5V ser defined 2 5V ser defined 2 5V ser defined 2 5V ser defined 2 5V ser defined 2 5V co PD Mm a vo GIqI cy cq ay aqy cia ii Cardinal Switch The pin assignment of the four cardinal switches may defer slightly as described in the table below Pin Pin Name Pin Name Pin 1 3 3V 12C_SDA 2 3 3 3V 12C_SCL 4 5 SO so 6 7 S1 2 s1 8 9 S2 S2 10 11 No Connect No Connect 12 13 No Connect No Connect 14 15 No Connect No Connect 16 On the North switch SW2 pin 8 is reserved to define if the pull up resistors shall be enabled or not Pin 8 must be down for the bottom and top boards of a stack On the West switch SW4 pin 8 is reserv2. the CM1K chips sample a new command on the positive edge of the system clock and pull down their RDY line for the duration of its execution Upon completion the RDY line is pulled back up on the positive edge of the system clock A Write command DS RW_ 0 REG DATA must be stable on the positive edge of the system clock and released before the next positive edge of the system clock A Read command DS RW_ 1 REG must be stable on the positive edge of the system clock and released before the next positive edge of the system clock DATA is stable when the RDY control line is pulled high 4 D b Registers For more information about the CogniMem registers and programming examples refer to the CM1K hardware user s manual and the CogniMem technology Reference Guide Register Hex Description Def Access ault CM_NCR 0x00 Neuron Context 0 R W in SR mode CM_COMP 0x01 Component 0 W R W in SR mode CM_LCOMP 0x02 Last Component 0 W R W in SR mode CM_INDEXCOMP_ 0x03 Component Index 0 W CM_DIST 0x03 Distance OxFF R FF CM_CAT 0x04 Category OxFF R W FF CM_AIF 0x05 Active Influence Field 0x4 R W in SR mode 000 CM_MINIF 0x06 Minimum Influence Field 2 R W CM_MAXIF 0x07 Maximum Influence Field 0x4 R W 000 CM_NID OxOA Neuron identifier 0 R CM_GCR 0x0B Global Norm and Context 1 W CM_RESET CHAIN OxOC Point to the 1st neuron in SR mode W CM_NSR OxOD_ Network Status Register 0 R W
3. 0Mb s to UART FIFO IC It has the capability of being configured in a variety of industry standard serial or parallel interfaces It must be configured as a single channel synchronous 245 FIFO hardware interface mode FT245 and interfaces through a Virtual Com port or D2XX Direct driver CogniBlox Hardware Manual 99 20 2 C Connectivity and I Os 2 C a _ Power supply Asingle CogniBlox can be powered through its USB power supply otherwise you will need to use an external 24v power supply The 24v power supply is connected to a hot swap circuitry o In case of power shut down the power backup time lasts approximately 5 ms and is generous enough to allow saving the contents of the neurons to the MRAM provided that this feature is programmed in the firmware of the FPGA 1 5V Source Select J13 This jumper requires a jumper connector to be present in order for power to be delivered to the board A Jumper across 1 2 sources power to the card from the USB connector single board configuration only A jumper across 2 3 sources power from the on board 24V to 5V Regulator Pin Pin Name 1 VBUS 2 5V 3 VOUT ii 24V Source Connector J10 This header isa poke home connector for connecting the board to an external 24v power supply Insert strip wires into the bottom portion of the connector as described in the table below To release the wires you will need push a small wire in the upper holes of th
4. B PROGRAMMING TAE BOARD o ricis roren EErEE TEENE E EER AIE NE EET EER 3 4 B EXAMPLES OF APPLICATIONS YOU CAN PROGRAM sssessssssesssseresssessseesssresssseessstresssseessseessseeeesresssseee 6 4 B a Stack of CogniBlox for Data Mining cccccescescescesscesscnseceeceseeeseeeeaecaaecaeeeeceaecnaeenaeenaeees 6 4 B b CogniBlox for Video Analytics se tssisisstissenerssensicorssard nestins enen e ena Ee n KE 6 4 B c CogniBlox for Complex Recognition cccccccesseesseesseessecneeeeecacecaecsseeseeeeeeeaeecaaeseeeseeeeneesaes 7 4B d CogmBlox for Sensor FUSION cccsccssecssecesessseeseeseceeceeeceeeeeesaecsaecsaecueeaaecaeseeeeeeeesaeeeneenaes 7 C HARDWARE DESCRIPTION jc csssssccnssavstcnusncinnecnvevens cuvivdenasansuinesswnstvenseusdiuuscneusiuesessetuwsdsesiuesvonse 8 Wis OVERVIEW E T EN E E TE N E E R IE T ET 8 LCa Bank Of CMIKENDS ccna Riese sete ndag man ade eeeun EAE S amp 1 C b Field Programmable Gate Array cccccscceccesssesseceseceseeseeenseeseceseceseeeseeeaeeesseaeeeeeeaeeenaeensees 9 LGe Bank Of MRAM ssscistccesecsted cusses seued sseese cx vedvazadecedabc tuseiasebelavwecvies a a eiaa ia 9 1 C d FT DI USB chip isis ccscvisscectasiasoevibsccesendanteisasseados vihatiaacveid siecuisacdeeidea RTE E E EARTE 9 AC SCONNECTIVITY AND TOS oc dhte sca sted E evesisudd asain E TESA 10 2 Gidi gt Power SUPDIY viscussdceesivassveassadacsshsvcik vase vats caveials docats ba ices saves pede E TA 10 2Gb Spine CONNEC CION
5. CM_FORGET OxOF Clear the neuron registers the Minif W Maxif and GCR global registers Does NOT reset the NSR register CM_NCOUNT OxOF Return the number of committed neurons R CM_RSR Ox1C Recognition Status Register 0 R W CM_RTDIST Ox1D Real Time distance OxFF R FF CM_RTCAT OxlE Real Time category OxFF R FF CM_LEFT 0x11 Left position of the ROI 200 R W CM_TOP 0x12 Top position of the ROI 120 R W CM_NWIDTH 1 0x13 Width of the ROI 340 R W CM_NHEIGHT 1 0x14 Height of the ROI 220 R W CM_BWIDTH 1 0x15 Width of the inner block 20 R W CM_BHEIGHT 1 0x16 Height of the inner block 20 R W CM_ROIINIT Ox1F Reset the ROI to default W CogniBlox Hardware Manual 1717 E Examples of CogniBlox firmware architecture 1 E Combined vision and sound recognition In the following example a video recognition engine receives input from a camera on the North bus and interfaces to a chain of 3 CMIKs to the recognize the contents of the video frames The output is transferred to a decision rule shared with the Voice recognition engine Avoice recognition engine receives input from a microphone on the West bus and interfaces to a single CM1K to the recognize a voice The output is transferred to a decision rule shared with the Video recognition engine CM1K Video Reco _ Decision rule Voice Reco Power engine supply amp monitor Power low int
6. CogniBlox Hardware User s Manual Version 1 2 9 Revised 10 07 2013 COG NIMEN Technologies Inc Limitation of Liability CogniMem Technologies Inc CTI assumes no liability whatsoever and disclaims any express implied or statutory warranty relating to the product described in this manual and accompanying materials Product including but not limited to the implied warranty of merchantability fitness for a particular purpose or non infringement In no event shall CTI be liable for any direct indirect consequential punitive special or incidental damages including without limitation damages for loss of profits business interruption or loss of information arising out of the use or inability to use the Product even if CTI has been advised of the possibility of such damages CTI makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice This Product is not designed manufactured or intended by CTI for incorporation into products intended for use or resale in equipment in hazardous dangerous to life or potentially life threatening environments such as in the operation of nuclear facilities aircraft navigation or communication systems or direct life support machines in which the failure of products could lead directly to death personal injury or
7. J6 Pin Pin Name Pin Name Pin Number 1 24V 24V 2 3 CMB_SPO CMB_RDY 4 5 CMB_CSn CMB_CLK 6 7 CMB_BSY CMB_IDn 8 9 CMB_RO CMB_UNCn 10 11 CMB_RI CMB_DS 12 13 CMB_R2 CMB_RWn 14 15 CMB_R3 CMB_DCO 16 17 CMB_R4 CMB_RSTn 18 iv Spine connector South Bottom J8 Pin Pin Name Pin Name Pin Number 1 24V 24V 2 3 CMB_SPO CMB_RDY 4 5 CMB_CSn CMB_CLK 6 7 CMB_BSY CMB_IDn 8 9 CMB_RO CMB_UNCn 10 11 CMB_RI CMB_DS 12 13 CMB_R2 CMB_RWn 14 15 CMB_R3 CMB_DCI 16 17 CMB_R4 CMB_RSTn 18 CogniBlox Hardware Manual 1111 2 C c General purpose switch SW1 The switch SW1 allows defining the configuration and operation of the board through external switch positions provided that the firmware loaded in the FPGA takes these inputs into considerations Pin Pin Name Pin Number Pin Name 1 Ground 2 TBD 3 Ground 4 TBD 5 Ground 6 TBD 7 Down Single board 8 Down Master board Up Stackable board Up Slave board 9 Ground 10 TBD 11 Ground 12 TBD 13 Ground 14 TBD 15 Ground 16 TBD Cardinal connectors and switches 2 C d Four configurable cardinal connectors allow interfacing the board with sensors and other I O devices including other CogniBlox boards or stacks The connector is an 8 pin push in connector and its electrical properties are defined through an associated dip switch Connector Configuration Switch North Jl SW2 East J4 SW5 South J2 SW3 West J3 SW4
8. S sesiidesiessiiecvedercaseeiesscssencceadsrtee iiss eeniesectcuseseniovcducnaatawensseuseesieroelascsienieee 10 2 C c General purpose switch SW1 escccscsssecssscsseesecesceeseceseceseceeeeeneeeseesseceaeeseesaecsaeesaeenseeees 12 2 C d Cardinal connectors and SWitCheS cscccscccesseesseesseceseeseceseecsecescecaeceaeesaaeesaessaeeeaaeeeaes 12 2 C s JIAG ID ieri enr eE EE EEE R E E R AEE E EEE svete E 13 nA CN E E D E E E E E E N E A E E A 13 3 C DEFAULT SETTINGS SUMMARY cccsssssccecsssnsccecsssececcssaeeecesssaeececsesaaesesssaeeecesssaeeeeecsesaeeeseseaaeeeses 14 D FIRMWARE AT FACTORY DEFAULT sccsscssasnssstacedssassnesssusestunsessrcossviinsussinsadcuscvstesusevdersowavionss 15 LD ADDRESS MAPPING sccscsasacasveasecccsucadencdeseastdcnntacadcevonsboacechonsacacsuadencgouthdasdgundadandgnnusdede Qeebbangngentoans 15 2D USB COMMUNICATION PROTOCOL s i lt cvseseeccsenanacconnasacceadechunaaacconnaedccenaesccsstaad cobasccendasccowsaesccsvanaa cons 15 2 Did WHE protocol sesira enan a e ae aisle EAE E S 15 2D b Read Protocol oeno a E E EE E E TENES 15 BAD EXAMPLES snadisti aaraa AA aai EAN EANNAN RAA AAAS SAA ANAS AAP EANET A aa aa Eai iaar R ARNA 16 4D lt COGNIMEM CONTROLLER socsrciccs kiireen erri eena EA ETE EEEE E E EERE 16 4 D a Command and Control line cccsccesccesesseeensessetseeeneeeneeeseesaceesecsseeeseeeaesseeeeeeaeeeaeeeaaeenaees 16 AAD D REGISLOTS ccsssadcvcsnsbucsaceiuuscavcnedeateaniivea ceucau
9. e connector Pin Pin Name 1 24V 2 Ground 2 C b Spine connectors The spinal connectors enable the vertical stack ability of the CogniBlox modules and the expansion of the neural network by connecting the CM1K chips from multiple boards on a same parallel bus The top side connectors are 2 spinal spring loaded 18 pin connectors The bottom side connectors are simple pads mirroring the top connectors except for the daisy chain in DCI signal of J8 which becomes the daisy chain out DCO signal on J6 Warning If you probe the signals of the spinal connectors J6 and J8 DO NOT short pins 1 and 2 which are the 24v VCC lines CogniBlox Hardware Manual i Spine connector North Top J5 Pin Pin Name Pin Name Pin Number 1 CMB_D00 CMB_D08 2 3 CMB_D01 CMB_D09 4 5 CMB_D02 CMB_D10 6 7 CMB_D03 CMB_D11 8 9 CMB_D04 CMB_D12 10 11 CMB_D05 CMB_D13 12 13 CMB_D06 CMB_D14 14 15 CMB_D07 CMB_D15 16 17 Ground Ground 18 ii Spine connector North Bottom J7 Pin Pin Name Pin Name Pin Number 1 CMB_D00 CMB_D08 2 3 CMB_D01 CMB_D09 4 5 CMB_D02 CMB_D10 6 7 CMB_D03 CMB_D11 8 9 CMB_D04 CMB_D12 10 11 CMB_D05 CMB_D13 12 13 CMB_D06 CMB_D14 14 15 CMB_D07 CMB_D15 16 17 Ground Ground 18 iii Spine connector South Top
10. e through the following 32 bit address map Address Range Module Address 30 24 Functionality defined by registers Address 23 8 0x01000000 CogniMem Access to the CMIK neurons to learn and recognize 0x01 00001F 0x01 d01 vectors save and restore knowledge Also access to the recognition logic in bypass and video mode 0x 10000000 MRAM Not yet implemented 0x0100001F 0x10 d16 TBD More to come 2 D USB communication protocol The communication protocol programmed in the FPGA of the VIKU board is based on the following packet sequence 2 D a Write protocol Reserved Address 3 1 0 Data length 23 0 Data 0x00 Bit 31 1 Module 6 0 Register 24 0 Size of the input array Input array expressed in words 1 byte 1 byte 3 bytes 3 bytes Data length 2 bytes 2 D b Read protocol Reserved Address 3 1 0 Data length 23 0 Data 0x00 Bit 31 0 Module 6 0 Register 24 0 Size of the output array Output array expressed in words 1 byte 1 byte 3 bytes 3 bytes Data length 2 bytes CogniBlox Hardware Manual 1515 3 D Examples The following examples used dummy modules and registers numbers i Single Read Read the register 5 of the module 4 0x00 04 00 00 05 00 00 01 Data is returned into 2 bytes or a word ii Single Write Write the 16 bit value 0x33AA to the register 5 of the module 4 0x00 84 00 00 05 00 00 01 33 AA iii M
11. ear and the Connect button should be green if the board is properly detected The default module targets the CMIK chip Reading the register 6 must return the value 2 at factory settings For more testing refer to the technical brief CM1K_Getting_Started_Programmers pdf The list of the CMIK registers is supplied inthe paragraph Register Descriptions of the CM1K Hardware Manual Examples of Read Write sequences to learn and recognize a vector are described in the paragraph Programming Sequences of the CM1K Hardware manual Test Capacity automatically commits allthe neurons of a a9 CBX USB Test the four CMIK chips and reads their number back It should report the value 4096 at the end of the test Test Commit automatically loads a user defined number of neurons with random patterns The Loop Write and Loop Read functions execute a user defined number of read or write instructions and stop if any communication error occurs Programming the board The FPGA can be programmed using Lattice s Diamond software which is available as a download from the Lattice website for both Windows and Linux Once downloaded and installed it can be used with either a free license or a subscription license CogniBlox Hardware Manual 55 20 The default firmware programmed on the FPGA at factory settings implements a simple Register Transfer Level protocol to access the chain of the four CMIK chips It is described in
12. ed to define the boot configuration of the FPGA On the North switch SW2 pin 6 7 are reserved to enable the future programming of the FPGA via a USB connection without the need for a Lattice programming cable 2 C e JTAG J9 JTAG to program and debug the FPGA Pin Pin Name Pin Name Pin 1 JTAG_TDI VCC 3 3V 2 3 JTAG_TDO No Connect 4 5 JTAG_TCK No Connect 6 T JTAG_ TMS No Connect 8 9 JTAG_TRST Ground 10 2 Cf LEDs Four sets of three LEDS are placed along the four edges of the board Their functionality of defined by the firmware programmed on the board CogniBlox Hardware Manual 1313 3 C Default settings summary Single board configuration pin 7 of SW1 is down pin 87of SW1 is down pin 8 of SW2 is down Multiple boards configuration All boards gt pin 7 of SW1 is up master board gt pin 8 of SW1 down slave board gt pin 8 of SW1 up Iftop or bottom board of a stack gt pin 8 of SW2 down Ifin between board of a stack gt Pin 8 of the SW2 up CogniBlox Hardware Manual 1414 D Firmware at Factory Default At factory settings the board is programmed with a simple USB protocol to read and write data to registers or addresses of modules instantiated in the FPGA The only module instantiated at first is the controller of the chain of 4 CMIK chips residing on the board L D Address Mapping The default modules instantiated inthe board are accessibl
13. errupt CogniBlox Hardware Manual 1818 2 E Multi scale image recognition In the following example the same video signal received on the North bus is transmitted to three different Video Recognition engines which are each interfaced to their own CMIK chip These engines can be designed to recognize the video frames at different scales or with different feature extraction methods or with different regions of search etc The outputs of the three engines are transmitted to a decision rule engine which assembles them into a feature vector and uses a CMIK chip to classify this vector as a global response Ey Reco QA LJA Reco engine3 D engine2 rule Power supply amp CM1K monitor Power low interrupt CogniBlox Hardware Manual 1919 F Mechanical and Electrical Specifications Power supply 24v Power consumption 50 mA per board G Schematics Overview 3 3 Volts out 24 Volts in 2 5 Volts out POWER BLOCK LFXP2 40E SFN4841 UP connector MRAM data bus D 15 0 CogniBlox Hardware Manual Horizontal expansion links 11 bus LVDS pairs 2020
14. he person has authorized access to the appliance detection of its emotions based on its facial expression and tone of voice Expert in voice RE1 kn1 Expert in face expression RE2 kn2 Expert in fingerprint RE3 kn3 Expert in iris RE4 kn4 CogniBlox Hardware Manual 77 20 C Hardware Description LC Overview Four 8 pins push in connectors configurable as differential or single ended lines CM1K ESvmz CM1K Latti ce Spine bus 32 wires XP2 to stack boards DOWN connector FPGA 5V sustained 10 msec CM1K SUS HS USB USB 3 3V 1 2V 2 5V Configuration switch JTAG aa monitor Power low interrupt 1 C a Bank of CMIK chips 4CM1Kchips with 1024 neurons each The four chips can be configured to work independently from one another or to be daisy chained to build one or multiple networks with more than 1024 neurons Furthermore one of the network can also be daisy chained to additional CM1Ks residing on stacked CogniBlox boards through the spine connector The configuration of the neural networks is defined by the firmware loaded in the FPGA This firmware can be programmed to implement a single given configuration or to take advantage of the general purpose switch inputs to define multiple configurations CogniBlox Hardware Manual 88 20 i Examples of possible network configurations for the first board of a stack CM1K_1 CMIK 2 CM1K_3 CMIK 4 Sp
15. ine Description DCI DCO DCI DCO DCI DCO DCI DCO DCI Vcc Wirel Wirel Wire2 Wire2 Wire3 Wire3 N A 1 network of 4096 neurons 1 2 3 4 non expandable Vec Wirel Wirel Wire2 Wire2 Wire3 Wire3 Wire4 Wire4 1 network of 4096 neurons 1 2 3 4 expandable Vee N A Vec Wire2 Wire2 Wire3 Wire3 N A 1 network of 1024 neurons 1 and 1 network of 3072 neurons 2 3 4 Vec Wirel Vcc Wire2 Wire2 Wire3 Wire3 N A Wirel 1 network of 1024 neurons 1 expandable and 1 network of 3072 neurons 2 3 4 Vcc N A Vec Wire2 Wire2 Wire3 Wire3 Wire4 Wire4 1 network of 1024 neurons 1 and 1 network of 3072 neurons 2 3 4 expandable Vcc Wirel Wirel N A Vec Wire3 Wire3 N A 1 network of 2048 neurons 1 2 and 1 network of 2048 neurons 3 4 Vcc Wirel Wirel Wire2 Vcc Wire3 Wire3 N A Wire2 1 network of 2048 neurons 1 2 expandable and 1 network of 2048 neurons 3 4 Vcc Wirel Wirel N A Vec Wire3 Wire3 Wire4 Wire4 1 network of 2048 neurons 1 2 and 1 network of 2048 neurons 3 4 expandable 1 C b Field Programmable Gate Array Lattice XP2 FPGA with 40 000 logic elements Model LFXP2 40E BGA 484 balls Programmable through a JTAG connector USB connector or 2 SPI lines LEGG Two 2 Mbytes 2M xl6bits MRAM 35 ns access time Bank of MRAMs 1 C d FTDI USB chip The FT232H is a single channel USB 2 0 Hi Speed 48
16. ns AEEA A EEEE EE AEE 17 E EXAMPLES OF COGNIBLOX FIRMWARE ARCHITECTURE ssssssscsscsssscsseceesssssssosscceeeees 18 1 E COMBINED VISION AND SOUND RECOGNITION cccssceessseececsesceceesseeceeasececsesececseaseceseaaeceeaaeeeeeeaaes 18 2 E MULTISCALE IMAGE RECOGNITION cccssssccccssssececesscesessececessaeeecesaeeecsesaecesseeesssseeeesesaeeeseesaeeeses 19 F MECHANICAL AND ELECTRICAL SPECIFICATIONS ssssssccececsssscccscccesscssscsscccccesesssscoscssoee 20 G SCHEMATICS OVERVIEW sissuiwcsssncecssnsvssssssasatecsnssacossacscasnvacnsessssavedaasvouseusasanenseteseseauiguneses 20 CogniBlox Hardware Manual 3 20 CogniBlox Hardware Manual 4 20 LB 2 B 3 B Getting Started Configure a single board or a stack of boards Single board configuration pin 7 of SW1 is down pin 8 of SW1 is down pin 8 of SW2 is down Multiple boards configuration All boards gt pin 7 of SW1 is up master board gt pin 8 of SW1 down slave board gt pin 8 of SW1 up Iftop or bottom board of a stack gt pin 8 of SW2 down Ifin between board of a stack gt Pin 8 of the SW2 up Testing a single board or a stack of boards Connect the CogniBlox board to your PC through its USB connector and wait until the new device is detected Follow the instructions on screen The FTDI driver is supplied in the folder CBX USB Drivers Install the CogniBlox_Diagnostics program The following panel will app
17. severe physical or environmental damage High Risk Activities The inclusion of the Product as critical component in High Risk Activities implies that the manufacturer assumes all risk of such use and in doing so agrees to fully indemnify CTI for any damages resulting from such application Trademarks and Copyrights This manual is copyrighted and published by CogniMem Technologies Inc All rights reserved No parts of this work may be reproduced in any form or by any means graphic electronic or mechanical including photocopying recording taping or information storage and retrieval systems without the written permission of the publisher Products that are referred to inthis document may be either trademarks and or registered trademarks of the respective owners The publisher and the author make no claim to these trademarks Contact Information www cognimem com CogniBlox Hardware Manual 2 20 A Table of Contents A TARE OF CONTENTS soscccstsnssseceussatevectuscusessesvavssocmsuesscussvsaussdusdsnescssusceeavetsctedesssanuwssuuysswersunvades 3 B GETTING STARTED scvssscesanessnntisossnstsassnngwivaseanstsesseuninaseansesusobdsssevaseauicenavsnieds teasesnvabbansteaasbonee 5 1 B CONFIGURE A SINGLE BOARD OR A STACK OF BOARDS ssscccecessssccecessseecesseceeeessaaeeecsesaeeeeesseeeeeees 5 2 B TESTING A SINGLE BOARD OR A STACK OF BOARDS ssssccesessseceeseseeeesescecsesaecesesaececesaeceeeesaessesaeeeensaes 5 3
18. the next chapter 4 B Examples of applications you can program 4 B a Stack of CogniBlox for Data Mining Recognize and classify of vectors against large datasets or knowledge bases 4 B b CogniBlox for Video Analytics Process images N times faster by distributing the recognition to multiple CMIK chips Example The four quadrants of a high resolution image are recognized in parallel by four neural networks of 1024 neurons or more loaded with the same knowledge The latter can be simple and just intended to recognize edges or simple objects or it can be more complex and composed of neurons assigned to different contexts to build a decision based on multiple features The image is recognized in parallel at four different scales Expert at Scalel RE1 kn Expert at Scale2 RE2 kn Expert at Scale3 RE3 kn Expert at Scale4 RE4 kn The same knowledge is loaded in the four CM1Ks CogniBlox Hardware Manual 66 20 4 B c CogniBlox for Complex Recognition Build robust diagnostics using multiple recognition engine and hypothesis generation Example Expert in color RE1 kn1 Expert in texture RE2 kn2 Expert in shapes RE3 kn3 Expert in cell biology RE4 kn4 1 2 7 4 f Lafice Zo RE 3 4 B d CogniBlox for Sensor Fusion Multiple sensor inputs video sound accelerometer for composite recognition Example Robust recognition of a person based on its iris and fingerprint and if t
19. ultiple Read Read 8 consecutive byte values starting at 0x00 02 23 45 67 00 00 04 the address 0x234567 of the module 0x02 Data is returned into 8 bytes iv Multiple Write Write 4 consecutive byte values 9 8 7 6 starting at 0x00 82 23 45 67 00 00 02 09 08 07 the address 0x234567 of the module 0x02 4 D CogniMem controller The CogniMem controller is the module 0x01 It transmits and receives data to and from the chain of CMI1K chips residing on the board and possibly extending to the CM1K chips of additional boards stacked on top of this master board 4 D a DS RW_ REG DATA RDY ID UNC_ Command and control lines Data strobe line Read Write line default is Read with RW_ 1 5 bit register address 16 bit register data Ready control line mixing the ready output signal of all the neurons in the chain and indicating that the neurons are all ready to execute a new command Control line mixing the ready output signal of all the neurons in the chain and indicating that neurons have identified the last vector and that these neurons are allin agreement for its classification Control line mixing the ready output signal of all the neurons inthe chain and indicating that neurons have identified the last vector but that these neurons are in disagreement with its classification This line is an in out line because used as an input during the execution of certain Write register CogniBlox Hardware Manual 1616 All the neurons of
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