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80C186EB/80C188EB Microprocessor User`s Manual

1. Byte 2 Bytes 3 6 ASN 86 Instruction Format Hex Binary D1 1101 0001 mod 000 r m disp lo disp hi rol reg16 mem16 1 mod 001 r m disp lo disp hi ror reg16 mem16 1 D1 11010001 mod 010 r m disp lo disp hi rcl reg16 mem16 1 mod 011 r m disp lo disp hi rer reg16 mem16 1 mod 100 r m disp lo disp hi sal shl reg16 mem16 1 mod 101 r m disp lo disp hi shr reg16 mem16 1 mod 110 r m mod 111 r m disp lo disp hi sar reg16 mem16 1 D2 1101 0010 mod 000 r m disp lo disp hi rol reg8 mem8 CL mod 001 r m disp lo disp hi ror reg8 mem8 CL mod 010 r m disp lo disp hi rcl reg8 mem8 CL mod 011 r m disp lo disp hi rer reg8 mem8 CL mod 100 r m disp lo disp hi sal shl reg8 mem8 CL mod 101 r m disp lo disp hi shr reg8 mem8 CL mod 110 r m TG mod 111 r m disp lo disp hi sar reg8 mem8 CL D3 1101 0011 mod 000 r m disp lo disp hi rol reg16 mem16 CL mod 001 r m disp lo disp hi ror reg16 mem16 CL mod 010 r m disp lo disp hi rel reg16 mem16 CL mod 011 r m disp lo disp hi rer reg16 mem16 CL mod 100 r m disp lo disp hi sal shl reg16 mem16 CL mod 101 r m disp lo disp hi shr reg16 mem16 CL mod 110 r m EN mod 111 r m disp lo disp hi sar reg16 mem16 CL D4 11010100 0000 1010 aam D5 1101 0101 0000 1010 aad D6 1101 0110 D7 1101 0111 xlat source table D8 1101 1000 mod 000 r m disp lo disp hi esc opcode source D9 1101 1001 m
2. Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS Continued LEA Load EA to register 10001101 mod reg r m 6 LDS Load pointer to DS 11000101 mod reg r m mod 11 18 LES Load pointer to ES 11000100 mod reg r m mod 11 18 ENTER Build stack frame 11001000 data low data high E L 0 15 1 25 L gt 1 22 16 n 1 LEAVE Tear down stack frame 11001001 8 LAHF Load AH with flags 10011111 2 SAHF Store AH into flags 10011110 3 PUSHF Push flags 10011100 9 POPF Pop flags 10011101 8 ARITHMETIC INSTRUCTIONS ADD Add reg memory with register to either 000000dw mod reg r m 3 10 immediate to register memory 100000sw mod 000 r m data data if sw 01 4 16 immediate to accumulator 0000010w data data if w 1 3 4 1 ADC Add with carry reg memory with register to either 000100dw mod reg r m 3 10 immediate to register memory 100000sw mod 010 r m data data if sw 01 4 16 immediate to accumulator 0001010w data data if w 1 3 4 1 INC Increment register memory 1111111w mod 000 r m 3 15 register 01000 reg 3 AAA ASCII adjust for addition 00110111 8 DAA Decimal adjust for addition 00100111 4 NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the 8086 8088 instruction s
3. UII ylus d d d d d d d d axy 18H 9gu vau edu cau Lau 08H uondeosH pneg 8 A1283 0A Figure 10 2 RX Machine 10 3 SERIAL COMMUNICATIONS UNIT intel The RX machine can detect several error conditions that may occur during reception Parity errors A parity error flag is set when the parity of the received data is incorrect 2 Framing errors If a valid stop bit is not received when expected by the RX machine a framing error flag is set 3 Overrun errors If SxRBUF is not read before another reception completes the old data in SxRBUF is overwritten and an overrun error flag is set This indicates that data from an earlier reception has been lost The RX machine also recognizes two different break characters The shorter break character is M bit times where M is equal to the total number of bits start data stop in a frame The longer break character is 2M 3 bit times A break character results in at least one null all zero char acter with a framing error being received Other error flags could be set depending on the length of the break character and the mode of the serial port 10 1 1 2 TX Machine A block diagram of the TX machine is shown in Figure 10 3 The TX machine logic supports the following features parity generation even odd or none Clear to Send break character transmission
4. 2 20 2 5 Arithmetic Interpretation of 8 Bit Numbers eme 2 21 2 6 Bit Manipulation Instructions 2 21 2 7 String Instructions ee ERE E 2 22 2 8 String Instruction Register and Flag 2 23 2 9 Program Transfer Instructions ssesseeeeneenn eene 2 25 2 10 Interpretation of Conditional Transfers 2 26 2 11 Processor Control Instructions eesseeeseeeeeneeeneee nennen 2 27 2 12 Supported Data TYPES sieri ceteri tette ie tese ip Pr creto ited 2 37 3 1 Bus Cycle Types aii e AU aaa eet 3 12 3 2 Read Bus Cycle Types 4 iru ER ere EU Pi eT OR DO heise 3 20 3 3 Read Cycle Critical Timing Parameters seen 3 20 3 4 Wiite Bus Gycle Typ s ose itx 3 23 3 5 Write Cycle Critical Timing Parameters 3 25 3 6 HALET Bus Gycle Piti Stat s Ine b iei e Pe REESE 3 29 3 7 Signal Condition Entering HOLD seseeeeeeeneeenenneee nennen 3 40 4 1 Peripheral Control 4 3 5 1 Suggested Values for Inductor L1 in Third Overtone Oscillator Circuit 5 4 5 2 Summary of Power Management Modes sse 5 19 6 1 Chip Select Unit Registers
5. Type Description Integer A signed 8 or 16 bit binary numeric value signed byte or word All operations assume a 2 s complement representation The 80C187 numerics processor extension when added to an 80C186 Modular Core System directly supports signed 32 and 64 bit integers signed double words and quad words The 80C188 Modular Core does not support the 80C187 Ordinal An unsigned 8 or 16 bit binary numeric value unsigned byte or word BCD A byte unpacked representation of a single decimal digit 0 9 ASCII A byte representation of alphanumeric and control characters using the ASCII standard Packed BCD A byte packed representation of two decimal digits 0 9 One digit is stored in each nibble 4 bits of the byte String A contiguous sequence of bytes or words A string can contain from 1 byte to 64 Kbytes Pointer A 16 or 32 bit quantity A 16 bit pointer consists of a 16 bit offset component a 32 bit pointer consists of the combination of a 16 bit base component selector plus a 16 bit offset component Floating Point A signed 32 64 or 80 bit real number representation The 80C187 numerics processor extension when added to an 80C186 Modular Core System directly supports floating point operands The 80C188 Modular Core does not support the 80C187 2 37 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Signed Byte Sign Bit Signed Word Sign Bit Signed Double Word Sig
6. Name Description Operation CWD Convert Word to Doubleword if AF CWD AX 8000H r then DF Extends the sign of the word in register DX 0 IF AX throughout register DX Use to else OF produce a double length doubleword DX lt FFFFH PF dividend from a word prior to SF performing word division TF Instruction Operands ZF none DAA Decimal Adjust for Addition if AF v DAA AL and OFH gt 9 or AF 1 CF v i then DF Corrects the result of previously AL lt AL 6 IE adding two valid packed decimal AF lt 1 OF operands the destination operand if v must have been register AL Changes AL 9FH or CF 1 SF v the content of AL to a pair of valid then TF packed decimal digits AL lt AL 60H 7 Instruction Operands CF 1 none DAS Decimal Adjust for Subtraction if AF Y DAS AL and OFH gt 9 or AF 1 CF v then DF Corrects the result ofa previous AL lt AL 6 F subtraction of two valid packed AF 1 OF decimal operands the destination if v operand must have been specified as AL 9FH or CF 1 SF v register AL Changes the content of then TF AL 1o a pair of valid packed decimal AL lt AL 60H 7 digits CF 1 Instruction Operands none NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged afte
7. 10 29 10 4 Master Slave The select slave ROUtING ccccsccceeeseceeeseeeeeeeeeseneeensneeeeaes 10 30 10 5 Master Slave The slave 1 Routine 10 32 10 6 Master Slave The send slave command Routine 10 35 11 1 Port Programming Example sss nennen 11 12 12 1 Initialization Sequence for 80C187 Math 12 15 12 2 Floating Point Math Routine Using FSINCOS sseeeeeeee 12 16 xvi intel Introduction intel CHAPTER 1 INTRODUCTION The 8086 microprocessor was first introduced in 1978 and gained rapid support as the microcom puter engine of choice There are literally millions of 8086 8088 based systems in the world to day The amount of software written for the 8086 8088 is rivaled by no other architecture By the early 1980 s however it was clear that a replacement for the 8086 8088 was necessary An 8086 8088 system required dozens of support chips to implement even a moderately complex design Intel recognized the need to integrate commonly used system peripherals onto the same silicon die as the CPU In 1982 Intel addressed this need by introducing the 80186 80188 family of embedded microprocessors The original 80186 80188 integrated an enhanced 8086 8088 CPU with six commonly used system peripherals A parallel effort within Intel also gave
8. tr npe pei a eri totes 10 20 10 3 3 1 CLKOUT as Baud Timebase Clock 10 20 10 3 3 2 BCLK as Baud Timebase Clock ssseeeeeeeene 10 21 10 4 SERIAL COMMUNICATIONS UNIT 10 21 10 4 1 Channel 0 Interrupts eese nennen nnne nnne 10 21 10 4 2 Ch nnel t Interrupts x o textu Re Het pale ien 10 21 10 5 SERIAL PORT EXAMPLES ier eee ded Don el ARR Lc aon 10 23 10 5 1 Asynchronous Mode Example sse 10 23 10 5 2 Mode 0 Example iiini prre Tr tree catio Io 10 26 10 5 3 Master Slave Example sess enne nennen nnne 10 27 CHAPTER 11 INPUT OUTPUT PORTS Tha FUNCTIONAL OVERVIEW 11 1 TL Bidirectional Port iei eee editiert etie tiper Rr kee 11 1 11 1 2 eee ERO RERUM 11 3 115129 OUIDpUb PO uu eux DIPENDENTE 11 3 11 1 4 Open Drain Bidirectional Port sssssseeeeeneneeeeeenenen nennen 11 3 TAS Port Pin Organization a acid dne read Uwe eise 11 3 11 1 5 1 Port Organization i ici DRE E ERN EA AIRMAN 11 7 11 1 5 2 Port 2 Organization e ite 11 7 11 2 PROGRAMMING THE I O PORT UNIT sess enemies 11 7 11 2 1 Port Gontrol Register ueterem a e LER EAR RE RB Le edu ded 11 8 11 2 2 Port
9. NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 11 6 Port Direction Register PxDIR 11 2 3 Port Data Latch Register The Port Data Latch Register Figure 11 7 holds the value to be driven on an output or bidirec tional pin This value appears at the pin only if it is programmed as a port The Port Data Latch Register is read write Reading a Port Data Latch Register returns the value of the latch itself and not that of the associated port pin INPUT OUTPUT PORTS intel Register Name Port Data Latch Register Register Mnemonic PxLTCH P1LTCH P2LTCH Register Function Contains the data driven on pins programmed as output ports A1314 0A Bit Bit Name Reset Mnemonic State 7 0 Port Data FFH The data written to a PL bit appears on pins Latch 7 0 programmed as general purpose output ports NOTE Reserved register bits are shown with gray shading Reserved bits must be writ ten to a logic zero to ensure compatibility with future Intel products Figure 11 7 Port Data Latch Register PxLTCH 11 2 4 Port Pin State Register The Port Pin State Register Figure 11 8 is a read only register that is used to determine the state of a port pin When the Port Pin State Register is read the current state of the port pins is gated to the internal data
10. ssssseeeeneenneen nns 9 7 Timer 2 Control Register 1 ce ede Eee dee d eee 9 9 Timer Count Beglstels 3 32 Pee dt dre as etude eaa cie Re Fe Lee 9 10 Timer Maxcount Compare Registers 9 11 TxOUT Signal iecit ert rte Ere SD tee 9 15 Typical 10 Bit Asynchronous Data Frame 10 2 RA Machirie hti RUBORE PR RR EH ene io teinte 10 3 TX Machine tee dics Re rene pe ERR E m Reto E ee eere dene 10 5 Mode Waye O iiie itte ee POI RS ERR RE 10 6 Mode 3 Wavelform iecit etie vo E e Re 10 7 Mode 4 Wavelotim ier rete eite ERE 10 7 Mode O WavelotrIms enne ba ee a Pe GE ED he bete dic aa 10 8 Serial Receive Buffer Register 10 9 intel Figure 10 9 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 12 1 12 2 12 3 12 4 13 1 A 2 A 3 A 5 A 6 Serial Transmit Buffer Register SxTBUF Baud Rate Counter Register BxCNT Baud Rate Compare Register BxCMP Calculating the BxCMP Value for a Specific Baud Rate Serial Port Control Register SxCON Serial Port Status Register SxSTS CTS Recognition Sequence BCLK Synchronization Mode 0 BxCMP gt 2 Channel 0 Interrupts Channel
11. ayie Byte 2 Bytes 3 6 ASM 86 Instruction Format Hex Binary 53 0101 0011 push BX 54 0101 0100 push SP 55 0101 0101 push BP 56 0101 0110 push SI 57 0101 0111 push DI 58 0101 1000 pop AX 59 0101 1001 pop Cx 5A 0101 1010 pop DX 5B 0101 1011 pop BX 5C 0101 1100 pop SP 5D 0101 1101 pop BP 5E 0101 1110 pop SI 5F 0101 1111 pop DI 60 0110 0000 pusha 61 0110 000 popa 62 0110 0010 mod reg r m bound reg16 mem16 63 0110 001 64 0110 0100 65 0110 010 66 0110 0110 67 0110 011 68 0110 1000 data lo data hi push immed16 69 0110 1001 mod reg r m data lo data hi imul immed16 70 0 0000 P inc 8 jo short labe 71 0 0001 P inc 8 jno short labe 72 0 0010 P inc 8 jb jnae jc short label 73 0 0011 P inc 8 jnb jae jnc short label 74 0 0100 P inc 8 je jz short label 75 0 0101 P inc 8 jne jnz short label 76 0 0110 P inc 8 jbe jna short labe 77 0 0111 P inc 8 jnbe ja short labe 78 0 1000 P inc 8 js short labe 79 0 1001 P inc 8 jns short labe 7A 0 1010 IP inc 8 jp ipe short labe 7B 0 1011 IP inc 8 short labe 7C 0 1100 IP inc 8 jVinge short label 7D 0 1101 IP inc 8 jnl jge short label D 12 lel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued ee Byte 2 Bytes 3 6 ASM 86 Instruction Format Hex Binary 7E 0111 1110 IP inc 8 jle ing
12. U LE LE LISLE LE LL HOLD HLDA m ET AD15 0 fred 15 8 1916 RD EE LN CONTROL Valid n NOTE A19 16 and control signals remain floating until a valid cycle occur i e the BIU exists HALT or a refresh bus cycle is generated A1067 0A Figure 3 26 Returning to HALT After a HOLD HLDA Bus Exchange BUS INTERFACE UNIT intel cukor LJ LJ LJ LJ LJ LI LI LI 1 ALE 52 0 AD15 0 As 15 8 Address A19 16 1 X Addr A19 16 0 BHE H RFSH Note 2 NOTE 1 Previous bus cycle value 2 Only occurs for BHE on the first refresh bus cycle after entering HALT 3 BHE 1 for 16 bit device RFSH 0 for 8 bit device A1068 0A Figure 3 27 Returning to HALT After a Refresh Bus Cycle 3 5 6 Exiting HALT Any NMI or maskable interrupt forces the BIU to exit the HALT bus state in any power man agement mode The first bus operations to occur after exiting HALT are read cycles to reload the CS IP registers Figure 3 28 and Figure 3 29 show how the HALT bus state is exited when an NMI or INTn occurs 3 32 intel BUS INTERFACE UNIT avoir rE T LE gt 8 1 2 clocks to first vector fetch ALE _ _ _ S2 0 AD15 0 07 0 158 y BHE RFSH 1 o Mei is determined by PDTMR NMI pM 4 1 2 clocks min E NOTE Previous bus cycle address value A1069 0A
13. 6 5 6 2 Memory and I O Compare Addresses sssssseeeenenenen nennen 6 10 6 3 Example Adjustments for Overlapping 6 14 7 1 Identification of Refresh Bus Cycles sssseeeeeeeeneeen nennen 7 5 8 1 Default Interrupt ennemi 8 3 8 2 Fixed Interrupt Types er nde ineo rr RH sa deer et 8 9 8 3 Interrupt Control Unit Registers seseseeeeeeeenneneneeneeeen nennen 8 11 9 1 Timer 0 and 1 Clock Sources ssesssssss esee nennt neni 9 12 9 2 Titrier Pietriggering E teh EL REA TT 9 13 10 1 BxCMP Values for Typical Baud Rates and CPU Frequencies 10 13 11 1 Port 1 Multiplexing Options essseeeeeeeeeeeeeneneneeneen nennen nnne 11 7 11 2 Port 2 Multiplexing Options isni a earna eean isaba eaaa a aoea nnnm nennen enne 11 7 12 1 80C187 Data Transfer Instructions essen 12 3 12 2 80C187 Arithmetic Instructions eene 12 4 12 8 80C187 Comparison Instructions essseseeneeeeeenenneee nennen 12 5 12 4 80C187 Transcendental Instructions 12 5 12 5 80C187 Constant 12 6 12 6 80C187 Processor Control Instructions 12 6 12 7 80C187 I O Port Assignments essen nennen nns 12 10 C 1 Instr
14. unctio IREQ Interrupt This bit is set to indicate a pending interrupt Request VT4 0 Vector Type Contains the interrupt type of the highest priority pending interrupt NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 12 Poll Status Register 8 3 7 End of Interrupt EOI Register The End of Interrupt register Figure 8 13 issues an End of Interrupt EOI command to the In terrupt Control Unit which clears the In Service bit for the associated interrupt An interrupt han dler typically ends with an EOI command There are two types of EOI commands nonspecific and specific A nonspecific EOI simply clears the In Service bit of the highest priority interrupt To issue a nonspecific EOI command set the NSPEC bit Write 8000H to the EOI register A specific EOI clears a particular In Service bit To issue a specific EOI command clear the NSPEC bit and write the VT4 0 bits with the interrupt type of the interrupt whose In Service bit you wish to clear For example to clear the In Service bit for INT2 write 000EH to the EOI reg ister The timer interrupts share an In Service bit To clear the In Service bit for any timer inter rupt with a specific EOI write 0008H interrupt type 8 to the EOI register 8 21 INTERRUPT CONTROL UNIT intel Register Name End of Interrupt Register R
15. 12 7 12 4 4 Clocking the 80C187 dinies e eenid aaa a Ea aree argae aa DE eie neei 12 10 12 4 2 Processor Bus Cycles Accessing the 800187 12 10 12 4 9 System D sign TIps x oie pne DR CERERI Een ERR er 12 11 12 4 4 Exception Trapping sssi tte tie detect tette etur eee 12 13 CHAPTER 13 ONCE MODE 13 1 ENTERING LEAVING ONCE 13 1 APPENDIX 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A 1 80C186 INSTRUCTION SET ADDITIONS sese nennen nnne A 1 A 1 1 Data Transfer Instructions esseeeeeeeeeeee nnne nnne nnne nnne A 1 A 1 2 String Instructions eU dp De RR ERE ee t eg Ere nde Dos A 2 A 1 3 High Level Instr ctloris RRA 2 2 800186 INSTRUCTION SET A 8 A 2 1 Data Transfer Instructions ccccccccccccsececceececeeseeesesescesesececenensaaaeaesaececeeeeeeeeeeeeeeeees A 8 A 2 2 Arith metic INStruGtions UR UEM BEI INE A 9 A 2 3 Bit Manipulation Instructions seen A 9 A 2 3 1 ShiftInstr ctions oie ene b de ee E DU n A 9 A 2 3 2 Rotate Instructions 21 e nib e oeil ate east A 10 APPENDIX B INPUT SYNCHRONIZATION B 1 WHY SYNCHRONIZERS ARE B 1 B 2 AS
16. 2 46 CHAPTER 3 BUS INTERFACE UNIT 3 1 MULTIPLEXED ADDRESS AND DATA BUS seen 3 1 3 2 ADDRESS AND DATA BUS CONCEPTS sse nennen enn 3 1 3 2 1 16 Bit Data hot auum em telo E td ete qnc e ces 3 1 3 2 2 B Bit Data BUS oos En E e E E e e oue 3 5 3 3 MEMORY AND I O INTERFACES ssssssssseseeeeneeennee nennen nennen rennen ener 3 6 3 3 1 16 Bit Bus Memory I O Requirements sse 3 7 3 3 2 8 Bit Bus Memory and I O Requirements senes 3 7 3 4 BUS CYCLE recente due cr tee eode res ela ie ete eo ep dee eds 3 7 3 4 1 Address Status Phase nte e Be E et eee GENES ttal e IE 3 10 3 4 2 Data Phase eni RR eee eu een a e Em 3 13 9 4 9 Wait ate dete tired ila oed oe eicit t 3 13 9 44 Idle States nieto rtc rc EU ode ree t es 3 18 3 5 BUS GY GEES uec adve era afta ate es 3 20 3 5 1 Read Bus Cycles nh Ree eerte e eerta a ER eee ER DET RR 3 20 3 5 1 1 Refresh B s Cycl cene vase derent ede c Lec Pee rre osi ier etra eco 3 22 29 512 Wiite Bus Cycles nne een ar e ne ce se eee deen 3 22 3 5 3 Interrupt Acknowledge Bus Cycle sssssseseeeeeeeneenenenenneen nnn 3 25 3 5 8 1 System Design Considerations sene 3 27 3 5 4 HALT BUS Cycle uu it Ree De etn eed 3 28 3 5 5 Temporarily Exiting the HALT Bus State sssssseeee 3 30 3 5 6 TEXTING
17. NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 9 5 Timer 0 and Timer 1 Control Registers Continued intel TIMER COUNTER UNIT Register Name Timer 2 Control Register Register Mnemonic T2CON Register Function Defines Timer 2 operation M Bit Name Function 0 A1Z90 UA Bit Mnemonic EN Enable Set to enable the timer This bit can be written only when the INH bit is set Inhibit Set to enable writes to the EN bit Clear to ignore writes to the EN bit The INH bit is not stored it always reads as zero Interrupt Set to generate an interrupt request when the Count register equals a Maximum Count register Clear to disable interrupt requests Maximum This bit is set when the counter reaches a Count maximum count The MC bit must be cleared by writing to the Timer Control register This is not done automatically If MC is clear the counter has not reached a maximum count Continuous Set to cause the timer to run continuously Mode Clear to disable the counter clear the EN bit after each counting sequence NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 9 6 Timer 2 Control Register TIMER COUNTER UNIT intel Register Name Timer Count Regist
18. TF 0 SF interrupt procedure INTO addresses SP SP 2 TF the target interrupt procedure its type SP 1 SP lt CS 7 is 4 through the interrupt pointer at CS 12H location 10H it clears the TF and IF SP SP 2 flags and otherwise operates like INT SP 14SP lt IP INTO may be written following an IP 10H arithmetic or logical operation to activate an interrupt procedure if overflow occurs Instruction Operands none IRET Interrupt Return IP lt SP 1 SP AF Y IRET SP lt SP 2 CF Y CS SP 1 SP DF Y Transfers control back to the point of rs 3 s 580 IF v interruption by popping IP CS and the FLAGS lt SP 1 SP OF Y flags from the stack IRET thus affects SP SP 2 PF v all flags by restoring them to previously SF v saved values IRET is used to exit any interrupt procedure whether activated ZF by hardware or software Instruction Operands none JA Jump on Above if AF JNBE Jump on Not Below or Equal CF 0 or ZF 0 CF JA disp8 as JNBE disp8 IP lt IP disp8 sign ext to 16 bits x Transfers control to the target location PF if the tested condition CF 0 or SF ZF 0 is true TF Instruction Operands 2 JA short label JNBE short label NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unch
19. 10 T2Compare equ word ptr bp 12 push ax save registers used push dx push si push ds xor ax ax set interrupt vector mov ds ax mov si 4 timer_2_int mov word ptr ds si offset timer_2_interrupt_routine inc si inc si mov ds si cs pop ds mov ax hour set time mov hour al mov ax minute mov minute al mov ax second mov _ al mov _msec 0 mov dx T2CNT clear Count register xor ax ax out dx al mov dx T2CMPA Set maximum count value mov ax T2Compare See note in header above out dx al mov dx T2CON 7set up the control word mov ax OEOO01H enable counting out dx al generate interrupt on MC continuous counting TCUCON set up interrupt controller ax unmask highest priority interrupt al Example 9 1 Configuring a Real Time Clock Continued TIMER COUNTER UNIT intel sti enable interrupts pop si restore saved registers pop dx pop ax pop bp restore caller s bp ret Sset time endp timer 2 interrupt routine proc far push ax save registers used push dx cmp _msec 99 has 1 sec passed jae bump second if above or equal inc msec jmp Short reset int ctl bump second mov _msec 0 millisecond cmp _minute 59 minute passed jae bump_minute inc _second jmp short reset_int_ctl bump_minute mov _ 0 second cmp _minute 59 hour passed jae bump_hour inc _minute jmp short reset_int_ctl bump_hour mov _minute 0 reset mi
20. dest lt dest 1 affecting flags SF v complement of the number effectively TF reversing the sign of an integer If the ZE v operand is zero its sign is not changed Attempting to negate a byte containing 128 or a word containing 32 768 causes no change to the operand and sets OF Instruction Operands NEG reg NEG mem NOP No Operation None AF NOP CES DF Causes the CPU to do nothing IF Instruction Operands OF none PF SF TF ZF NOT Logical Not When Source Operand is a Byte AF NOT dest dest FFH dest et Inverts the bits forms the one s When Source Operand is a Word IF complement of the byte or word dest FFFFH dest OF operand PF Instruction Operands SF NOT reg TES NOT mem ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 31 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel Name Description Operation foe d OR Logical OR dest lt dest or src AF OR dest src CF 0 GE Y ene OF 0 DF Performs the logical inclusive or of IF the two operands bytes or words and OF v returns the result to the destination
21. operand bit the result is set if SE v either or both corresponding bits in the TF original operands are set otherwise ZF v the result bit is cleared Instruction Operands OR reg reg OR reg mem OR mem reg OR accum immed OR reg immed OR mem immed OUT Output dest lt src AF OUT port accumulator m Transfers byte word from the AL IF register or the AX register respec OF tively to an output port The port PF number may be specified either with SF an immediate byte constant allowing TF access to ports numbered 0 through ZF 255 or with a number previously placed in register DX allowing variable access by changing the value in DX to ports numbered from 0 through 65 535 Instruction Operands OUT immed AL OUT DX AX NOTE The three symbols used in the Flags Affected column are defined as follows C 32 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel Table C 4 Instruction Set Continued INSTRUCTION SET DESCRIPTIONS Name Description Operation OUTS Out String dst lt src AF OUTS port src string a E Performs block output from memory to IF an I O port The port address is placed OF in the DX register The memory PF address is placed in the SI
22. READY hold from clock high CLKOUT READY Alternatively in a Normally Ready system a wait state will be inserted when1 amp 2 are met 1 Tcs READY low to clock low 2 READY hold from clock low Failure to meet READY setup and hold can cause a device failure i e the bus hangs or operates inappropriately A1083 0A Figure 3 18 Normally Ready System Timings Conditions causing the BIU to become idle include the following The instruction prefetch queue is full An effective address calculation is in progress The bus cycle inherently requires idle states e g interrupt acknowledge locked opera tions Instruction execution forces idle states e g HLT WAIT 3 19 BUS INTERFACE UNIT intel An idle bus state may or may not drive the bus An idle bus state following a bus read cycle con tinues to float the bus An idle bus state following a bus write cycle continues to drive the bus The BIU drives no control strobes active in an idle state except to indicate the start of another bus cycle 3 5 BUS CYCLES There are four basic types of bus cycles read write interrupt acknowledge and halt Interrupt acknowledge and halt bus cycles define special bus operations and require separate discussions Read bus cycles include memory I O and instruction prefetch bus operations Write bus cycles include memory and I O bus operations All read and write bus cycles have the same basic form
23. The two levels of instruction sets address two requirements efficiency and simplicity Approxi mately 300 forms of machine level instructions make very efficient use of storage For example the machine instruction that increments a memory operand is three or four bytes long because the address of the operand must be encoded in the instruction Incrementing a register however re quires less information so the instruction can be shorter The 80C186 Core family has eight sin gle byte machine level instructions that increment different 16 bit registers The assembly level instructions simplify the programmer s view of the instruction set The pro grammer writes one form of an INC increment instruction and the assembler examines the op erand to determine which machine level instruction to generate The following paragraphs provide a functional description of the assembly level instructions 2 17 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel 2 2 1 1 Data Transfer Instructions The instruction set contains 14 data transfer instructions These instructions move single bytes and words between memory and registers They also move single bytes and words between the AL or AX register and I O ports Table 2 3 lists the four types of data transfer instructions and their functions Table 2 3 Data Transfer Instructions General Purpose MOV Move byte or word PUSH Push word onto stack POP Pop word off
24. double buffered operation A transmission begins by writing a byte to the Serial Transmit Buffer SxTBUF Register SxT BUF is a holding register for the transmit shift register The contents of SxTBUF are transferred to the transmit shift register as soon as it is empty If no transmission is in progress 1 the trans mit shift register is empty SxTBUF is copied immediately to the transmit shift register If parity is enabled the parity bits are calculated and appended to the transmit shift register during the transfer The start and stop bits are added when the data is transmitted The Transmit Interrupt bit TI is set at the beginning of the stop bit time Double buffering is a useful feature of the TX machine When the transmit shift register is empty the user can write two sequential bytes to SXTBUF The first byte is transmitted immediately and the second byte is held in SXTBUF until the first byte has been transmitted 10 4 SERIAL COMMUNICATIONS UNIT 2019 HUS g S19 ae 19 lig NA3 NJO Jaysibay wus pusueIL REJ pneg WOOD HUS XL 9160 04100 WIYS pue los isi uoneJeuet doig ueis un A1284 0A Figure 10 3 TX Machine 10 5 SERIAL COMMUNICATIONS UNIT intel The Transmit machine can be disabled by an external source by using the Clear to Send feature When the Clear to Send feature is enabled the TX machine will not transmit until the CTS pin
25. Figure 10 9 Serial Transmit Buffer Register SxTBUF 10 2 4 Baud Rates The baud rate generator is composed of a 15 bit counter register BxXCNT and a 15 bit compare register BXCMP BxCNT Figure 10 10 is a free running counter that is incremented by the baud timebase clock The baud timebase clock can be either the internal CPU clock or an external clock applied to the BCLK pin BxCMP Figure 10 11 is programmed by the user to determine the baud rate The most significant bit of BxCMP ICLK selects which source is used as the baud timebase clock BxCNT is incremented by the baud timebase clock and compared to BXCMP When BxCNT and BxCMP are equal the baud rate generator outputs a pulse and resets BxCNT This pulse train is the actual baud clock used by the RX and TX machines The baud clock is eight times the baud rate in the asynchronous modes because of the sampling requirements The baud clock equals the baud rate in the synchronous mode 10 10 intel SERIAL COMMUNICATIONS UNIT Register Name Baud Rate Counter Register Register Mnemonic BxCNT Register Function 15 bit baud rate counter value 15 A1275 0A Bit gt Bit Name Function Mnemonic BC14 0 Baud rate Reflects current value of the baud rate counter counter field NOTE Writing to this register while the serial port is transmitting causes indeterminate operation NOTE Reserved register bits are shown with gray shading Reserved bits
26. Figure 3 28 Exiting HALT Powerdown Mode 3 33 BUS INTERFACE UNIT intel lt gt Note 1 NMI INTx f ALE 52 0 li Valid AD15 0 AD7 0 ey Sl A15 8 Note 3 X Address 19 16 _f Notes N RESH NOTE 1 For NMI delay 4 1 2 clocks For INTx delay 7 1 2 clocks min 2 If previous bus cycle was a read bus will float If previous bus cycle was a write bus will drive data value 3 Previous bus cycle value 4 f previous bus cycle was a refresh cycle value will be 8H A19 1 otherwise value will be 0 A1070 0A Figure 3 29 Exiting HALT Active Idle Mode 3 6 SYSTEM DESIGN ALTERNATIVES Most system designs require no signals other than those already provided by the BIU However heavily loaded bus conditions slow memory or peripheral device performance and off board de vice interfaces may not be supported directly without modifying the BIU interface The following sections deal with topics to enhance or modify the operation of the BIU 3 34 intel BUS INTERFACE UNIT 3 6 1 Buffering the Data Bus The BIU generates two control signals DEN and DT R to control bidirectional buffers or trans ceivers The timing relationship of DEN and DT R is shown in Figure 3 30 The following con ditions require transceivers The capacitive load on the address data bus gets too large The current load on the address data bus exceeds device specifications
27. Figure 7 9 Refresh Address Register 7 7 8 Programming Example Example 7 1 contains sample code to initialize the Refresh Control Unit REFRESH CONTROL UNIT intel Smod186 name example_80C186_RCU_code FUNCTION This function initializes the DRAM Refresh Control Unit to refresh the DRAM starting at dram_addr at clock_time intervals SYNTAX extern void far config rcu int dram_addr int clock time INPUTS dram addr Base address of DRAM to refresh clock time DRAM refresh rate OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages RFBASE equ xxxxh Ssubstitute register offset equ xxxxh RFCON equ xxxxh Enable equ 8000h enable bit lib 80186 segment public code assume cs lib 80186 public config rcu Config red proc far push bp Save caller s bp mov bp sp get current top of stack clock time equ word ptr bpt6 get parameters off dram addr equ word ptr bpt8 the stack push save registers that push will be modified push push Example 7 1 Initializing the Refresh Control Unit intel REFRESH CONTROL UNIT RFBASE set upper 7 address bits dram addr al RFTIME set clock pre scaler clock time al Enable RCU 78 dummy cycles are required by DRAMs before actual use exercise ram mov word ptr di 0 loop exercise ram pop di restore saved registers pop dx ox pop ax pop bp restore caller s bp r
28. JNL 8 IP lt IP disp8 sign ext to 16 bits IF OF Transfers control to the target location PF If the condition tested SF OF or SF ZF 0 is true TF Instruction Operands ZF JGE short label JNL short label JMP Jump Unconditionally if AF JMP target Inter segment CF 1 then DF ransfers control to the target location CS SEG IF Instruction Operands IP lt dest OF JMP short label PPS JMP near label SF JMP far label TE JMP memptr ZF JMP regptr JNC Jump on Not Carry if AF JNC disp8 CF 0 CF Transfers control the target location men pE 1 n i IP lt IP disp8 sign ext to 16 bits IF if the tested condition CF 0 is true CEJ P Sig OF Instruction Operands JNC short label SF TF ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 23 INSTRUCTION SET DESCRIPTIONS intel Table C 4 Instruction Set Continued are Flags Name Description Operation Affected JNE Jump on Not Equal if AF JNZ Jump on Not Zero ZF 0 JNE disp8 then wt Verse JNZ disp8 IP lt IP disp8 sign ext to 16 bits IF OF Transfers control
29. Reset initializes the Instruction Pointer to 0000H The CS and IP values comprise a starting exe cution address of OFFFFOH see Logical Addresses on page 2 10 for a description of address formation 2 6 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 1 6 Flags The 80C186 Modular Core family has six status flags see Figure 2 5 that the Execution Unit posts as the result of arithmetic or logical operations Program branch instructions allow a pro gram to alter its execution depending on conditions flagged by a prior operation Different in structions affect the status flags differently generally reflecting the following states Ifthe Auxiliary Flag AF is set there has been a carry out from the low nibble into the high nibble or a borrow from the high nibble into the low nibble of an 8 bit quantity low order byte of a 16 bit quantity This flag is used by decimal arithmetic instructions Ifthe Carry Flag CF is set there has been a carry out of or a borrow into the high order bit of the instruction result 8 or 16 bit This flag is used by instructions that add or subtract multibyte numbers Rotate instructions can also isolate a bit in memory or a register by placing it in the Carry Flag If the Overflow Flag OF is set an arithmetic overflow has occurred A significant digit has been lost because the size of the result exceeded the capacity of its destination location An Interrupt On Overflow instruction is
30. The clock generation and distribution circuits provide uniform clock signals for the Execution Unit the Bus Interface Unit and all integrated peripherals The 80C186 Modular Core Family processors have additional logic that controls the clock signals to provide power management functions 5 1 CLOCK GENERATION The clock generation circuit Figure 5 1 includes a crystal oscillator a divide by two counter and reset circuitry See Power Management on page 5 10 for a discussion of power manage ment options Power Down Schmitt Trigger Idle Squares up CLKIN 01 Internal Phase Clocks Phase Drivers 2 To CLKOUT Internal Reset A1524 0A Figure 5 1 Clock Generator 5 1 1 Crystal Oscillator The internal oscillator is a parallel resonant Pierce oscillator a specific form of the common phase shift oscillator 5 1 CLOCK GENERATION AND POWER MANAGEMENT intel 5 1 1 1 Oscillator Operation A phase shift oscillator operates through positive feedback where a non inverted amplified ver sion of the input connects back to the input A 360 phase shift around the loop will sustain the feedback in the oscillator The on chip inverter provides a 180 phase shift The combination of the inverter s output impedance and the first load capacitor see Figure 5 2 provides another 90 phase shift At resonance the crystal becomes primarily resistive The combination of the crystal and the second load capacitor provides
31. and Twp values increase with the insertion of wait states The cal culated value however can be changed only by decreasing the clock rate 3 5 8 Interrupt Acknowledge Bus Cycle Interrupt expansion is accomplished by interfacing the Interrupt Control Unit with a peripheral device such as the 82C59A Programmable Interrupt Controller See Chapter 8 Interrupt Con trol Unit for more information The BIU controls the bus cycles required to fetch vector infor mation from the peripheral device then passes the information to the CPU These bus cycles collectively known as Interrupt Acknowledge bus cycles operate similarly to read bus cycles However instead of generating RD to enable the peripheral the INTA signal is used Figure 3 23 illustrates a typical Interrupt Acknowledge or INTA bus cycle An Interrupt Acknowledge bus cycle consists of two consecutive bus cycles LOCK is generated to indicate the sequential bus operation The second bus cycle strobes vector information only from the lower half of the bus D7 0 In a 16 bit bus system D15 13 contain cascade address in formation and D12 8 float 3 25 BUS INTERFACE UNIT c 2 o c be o lt NOTE Vector Type is read from 07 0 only A1064 0A Figure 3 23 Interrupt Acknowledge Bus Cycle 3 26 intel BUS INTERFACE UNIT Figure 3 24 shows a typical 82C59A interface example Bus ready must be provided to terminate both bu
32. Figure 10 7 Mode 0 Waveforms 10 8 intel SERIAL COMMUNICATIONS UNIT 10 2 PROGRAMMING This section describes how to program the serial port using the appropriate registers The Serial Receive Buffer Register SxRBUF is shown in Figure 10 8 and the Serial Transmit Buffer Reg ister SxTBUF is shown in Figure 10 9 These registers have the same functions in any serial port mode Register Name Serial Receive Buffer Register Register Mnemonic SxRBUF Register Function Received data bytes are stored in SxRBUF 15 R R IR R 7161514 1290 0 Bit Bit Nam Function Mnemonic Lome unctio RB7 0 Received Received data byte Data NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 10 8 Serial Receive Buffer Register SxRBUF 10 9 SERIAL COMMUNICATIONS UNIT intel Register Name Serial Transmit Buffer Register Register Mnemonic SxTBUF Register Function Bytes are written to SXTBUF to be transmitted 0 T T T T TIT T T B B B B 7161514 312110 1291 0 Function TB7 0 Transmit Data byte to be transmitted Data Field NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products
33. intel 80C186EB 80C188EB Microprocessor User s Manual February 1995 nformation in this document is provided solely to enable use of Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products ntel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein ntel retains the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation ntel Corporation and Intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Other brands and names are the property of their respective owners Additional copies of this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 INTEL CORPORATION 1995 intel CONTENTS CHAPTER 1 INTRODUCTION 1 1 HOW TO USE THIS MANUAL nanana e ieee rete E mete HE t de Rea 1 2 1 2 RELATED DOCUMENT
34. which can be in terrupted after each execution of the string primitive even if the REP prefix is combined with the LOCK prefix This prevents interrupts from being locked out during a block move or other re peated string operations However bus hold and refresh requests remain locked out until LOCK is removed either when the block operation completes or after an interrupt occurs 3 7 MULTI MASTER BUS SYSTEM DESIGNS The BIU supports protocols for transferring control of the local bus between itself and other de vices capable of acting as bus masters To support such a protocol the BIU uses a hold request input HOLD and a hold acknowledge output HLDA as bus transfer handshake signals To gain control of the bus a device asserts the HOLD input then waits until the HLDA output goes active before driving the bus After HLDA goes active the requesting device can take control of the local bus and remains in control of the bus until HOLD is removed 3 7 4 Entering Bus HOLD In responding to the hold request input the BIU floats the entire address and data bus and many of the control signals Figure 3 33 illustrates the timing sequence when acknowledging the hold request Table 3 7 lists the states of the BIU pins when HLDA is asserted All device pins not mentioned in Table 3 7 or shown in Figure 3 33 remain either active e g CLKOUT and T1OUT or inactive e g UCS and INTA Refer to the data sheet for specific details of pin func ti
35. 10 1 framing errors 10 4 hardware considerations 10 19 10 22 interrupts 10 22 master slave example 10 28 10 36 multiprocessor communications 10 14 overrun errors 10 4 overview 10 1 10 8 parity errors 10 4 programming 10 9 10 19 receiver 10 2 RX machine 10 2 stand alone communications 10 13 synchronous communications 10 8 10 19 example 10 27 timings 10 21 transmitter 10 4 TX machine 10 4 Serial Port Control Register SxCON 10 16 Serial Port Status Register SxSTS 10 17 10 18 Serial ports See Serial Communications Unit SCU Serial Receive Buffer Register SXRBUF 10 9 Serial Transmit Buffer Register SxTBUF 10 10 SHL instruction A 9 Short integer defined 12 7 Short real defined 12 7 intel SHR instruction A 9 SI register 2 1 2 5 2 13 2 22 2 23 2 30 2 32 2 34 Sign Flag SF 2 7 2 9 Single step trap Type 1 exception 2 43 Software code example 80C187 floating point routine 12 16 80C187 initialization 12 13 12 15 digital one shot 9 17 9 23 I O port configuration 11 12 ICU initialization 8 24 real time clock 9 17 9 19 SCU asynchronous mode 10 24 SCU master slave network 10 28 10 36 initialization code 10 30 10 32 select slave routine 10 31 10 32 send slave command routine 10 36 slave l routine 10 33 10 35 SCU synchronous mode 10 27 square wave generator 9 17 9 22 TCU configurations 9 17 9 23 data types 2 37 2 38 dynamic code relocation 2 13
36. 9 16 TxOUT signal 9 15 variable duty cycle output 9 14 9 15 Timer Maxcount Compare Registers TxCMPB 9 11 Timers See Timer Counter Unit TCU Watchdog timer Trap exceptions 2 43 Trap Flag TF 2 7 2 9 2 43 2 48 T state and bus cycles 3 9 and CLKOUT 3 8 defined 3 7 Index 7 INDEX W Wait states and bus cycles 3 13 and chip selects 6 11 6 14 and DRAM controllers 7 1 and PCB accesses 4 4 and READY input 3 13 Word integer defined 12 7 Write bus cycle 3 22 Z Zero Flag ZF 2 7 2 9 2 23 Index 8
37. Based Addressing csi ie dette e ee REI rk nte vend 2 31 Accessing a Structure with Based Addressing 2 32 Indexed ACCreSsing e cccesccceeseececeeeseeeseeeeeeseneceneeeesesecessneeeeseeeeeneseeseeseeeeeesentenesnees 2 33 Accessing an Array with Indexed Addressing see 2 33 Based Index Addressing etr retta d dot ege cu 2 34 Accessing a Stacked Array with Based Index 2 35 String Operarnd oet a ates aca ta esce ee tie amen 2 36 Port Addressing rere eet he een t ds 2 36 80C186 Modular Core Family Supported Data 2 38 Interrupt Control Unit cst eel teret Ln Eee HL be LR tL dene 2 39 Interrupt Vector Table reete Ix RE ERE 2 40 Interr pt Sequerice e Sache eter e ae a leis 2 42 Interrupt Response 2 46 Simultaneous NMI and Exception sessseeeeeeeeneeeeen nnne 2 47 Simultaneous NMI and Single Step Interrupts eeeeeeeeee 2 48 Simultaneous NMI Single Step and Maskable 2 49 Physical Data Bus Models ani ne eTa nens 3 2 16 Bit Data Bus Byte Transtar Siseron ei naai aariaa 3 3 16 Bit Data Bus Even Word Transfers seen 3 4 16 Bit Data Bu
38. CLI Clear Interrupt enable Flag IF lt 0 AF CLI Ces DF Zeroes the interrupt enable flag IF IF v When the interrupt enable flag is OF cleared the 8086 and 8088 do not PF recognize an external interrupt request SF that appears on the INTR line in other words maskable interrupts are ZF disabled A non maskable interrupt appearing on NMI line however is honored as is a software interrupt Instruction Operands none CMC Complement Carry Flag if AF CMC CF 0 CF v then DF Toggles complement carry flag CF to CF lt 1 IF its opposite state and affects no other else OF Instruction Operands SF none TE ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel fare Flags Name Description Operation Affected CMP Compare dest src AF Y CMP dest src EE Subtracts the source from the desti IF nation which be bytes or words OF v but does not return the result The PF operands are unchanged but the flags SF v are updated and can be tested by a TF subsequent conditional jump ZF instruction The
39. Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires servicing The CPU then stops executing the main task saves its state and transfers execution to the peripheral servicing code the interrupt handler At the end of the interrupt handler the CPU s original state is restored and execution continues at the point of interruption in the main task 8 1 INTERRUPT CONTROL UNIT intel Serial Serial Timer O Timer 1 Timer2 Receive Transmit INTO INT1 INT2 INT3 INT4 Interrupt Priority Resolver Vector To CPU Interrupt Request Generation Logic NOTE The three timers are multiplexed into a single input as are the two serial interrupts A1203 A0 Figure 8 1 Interrupt Control Unit Block Diagram 8 1 4 Generic Functions Several functions of the Interrupt Control Unit are common among most interrupt controllers This section describes how those generic functions are implemented in the Interrupt Control Unit 8 1 1 1 Interrupt Masking There are circumstances in which a programmer may need to disable an interrupt source tempo rarily for example while executing a time critical section of code or servicing a high priority task This temporary disabling is called interrupt masking All interrupts from the Interrupt Con trol Unit can be masked either globally or individually 8 2 intel INTERRUPT CONTROL UNIT The Interrupt Enable bit in the Processor Status Word globally enables o
40. NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 8 Interrupt Mask Register INTERRUPT CONTROL UNIT intel 8 3 4 Priority Mask Register The Priority Mask register Figure 8 9 contains a three level field that holds a priority value This register allows you to mask interrupts based on their priority levels Write a priority value to PM2 0 field to specify the lowest priority interrupt to be serviced This disables masks any interrupt source whose priority is lower than the PM2 0 value After reset the Priority Mask register is set to the lowest priority seven which enables all interrupts of any priority Register Name Priority Mask Register Register Mnemonic PRIMSK Register Function Masks lower priority interrupt sources A1216 A0 Bit s Bit Nam Function Mnemonic trame uneto PM2 0 Priority Defines a priority based interrupt mask Mask Interrupts whose priority is lower than this value are masked NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 9 Priority Mask Register 8 3 5 In Service Register The In Service register has a bit for each interrupt source The bits indicate which source s inter rupt handlers are currently executing The In Ser
41. Send short Wait 4 Cmd dx bx ax _slave_1l 1ib_80186 Example 10 5 Master Slave The slave_1 Routine Continued 10 34 intel SERIAL COMMUNICATIONS UNIT mod186 name example master send slave command ck ck ck KKK KKK ck ck ck ck ck ck koc ck KKK KKK KKK KKK KKK KK KKK KEK KKK KKK KKK KKK KKK KKK KKK ko kv Sk kc ko ko ko kokok send slave cmd FUNCTION This function transmits a slave command slave cmd over the serial network to a previously addressed slave SYNTAX extern void far send slave cmd int slave cmd OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages Example assumes PCB is in I O space te AND GRE RAR GRE SAAR ipu SS ERM d E TRA GAA SANE ANA GANG gen ax ree cce eee cde oe INPUTS Slave cmd command to send to addressed slave r EF substitute register offsets place of xxxxh SISTS equ xxxxh Serial Port 1 Status register S1CON equ xxxxh Serial Port 1 Control register S1TBUF equ xxxxh Serial Port 1 Transmit Buffer register lib 80186 segment public code assume cs lib_80186 public _send_slave_cmd Send slave cmd proc far push bp Save caller s bp mov bp sp get current top of stack get slave command off the stack Slave cmd equ word ptr bp 6 push ax Save registers that are modified push dx mov dx S1STS clear any pending excep
42. This is not done automati cally If MC is clear the counter has not reached a maximum count NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 9 5 Timer 0 and Timer 1 Control Registers TIMER COUNTER UNIT intel Register Name Timer 0 and 1 Control Registers Register Mnemonic TOCON T1CON Register Function Defines Timer 0 and 1 operation A1297 0A Bit 1 i nction Mnemonic Bit Name Functio RTG Retrigger This bit specifies the action caused by a low to high transition on the TMR INx input Set RTG to reset the count clear RTG to enable counting This bit is ignored with external clocking EXT 1 Prescaler Set to increment the timer when Timer 2 reaches its maximum count Clear to increment the timer at 1 4 CLKOUT This bit is ignored with external clocking EXT 1 External Set to use external clock clear to use internal clock Clock The RTG and P bits are ignored with external clocking EXT set Alternate This bit controls whether the timer runs in single or Compare dual maximum count mode see Figure 9 4 on page Register 9 6 Set to specify dual maximum count mode clear to specify single maximum count mode Continuous Set to cause the timer to run continuously Clear to Mode disable the counter clear the EN bit after each counting sequence
43. ax MaxCount CountDown ax not MaxCount dx al dx ax bp TIMER COUNTER UNIT get parameter off the stack save registers that will be modified Clear Timer 1 Counter set time before t shot to 0 set pulse time start Timer 1 read in T1CON max count occurred no then wait clear max count bit update T1CON restore saved registers restore caller s bp Example 9 3 Configuring a Digital One Shot Continued 9 23 TIMER COUNTER UNIT 9 24 intel 10 Serial Communications Unit intel CHAPTER 10 SERIAL COMMUNICATIONS UNIT 10 1 INTRODUCTION The Serial Communications Unit is composed of two identical serial ports or channels Each se rial port is independent of the other This chapter describes the operation of a single serial port The serial port implements several industry standard asynchronous communications protocols and it readily interfaces to many different processors over a standard serial interface Several pro cessors and systems can be connected to a common serial bus using a multiprocessor protocol The serial port also implements a simple synchronous protocol The synchronous protocol is most commonly used to expand the number of I O pins with shift registers Features Full duplex operation Programmable seven eight or nine data bits in asynchronous mode Independent baud rate generator Maximum baud rate of 1 16 the processor clock Double buffered transm
44. before the rising edge of CLKOUT and must remain valid Tcum after the same rising edge If these timing requirements are not met the input will not be recognized until the next clock edge intel TIMER COUNTER UNIT 9 3 2 Synchronization and Maximum Frequency All timer inputs are latched and synchronized with the CPU clock Because of the internal logic required to synchronize the external signals and the multiplexing of the counter element the Timer Counter Unit can operate only up to 1 4 of the CLKOUT frequency Clocking at greater fre quencies will result in missed clocks 9 3 2 1 Timer Counter Unit Application Examples The following examples are possible applications of the Timer Counter Unit They include a real time clock a square wave generator and a digital one shot 9 3 3 Real Time Clock Example 9 1 contains sample code to configure Timer 2 to generate an interrupt request every 10 milliseconds The CPU then increments memory based clock variables 9 3 4 Square Wave Generator A square wave generator can be useful to act as a system clock tick Example 9 2 illustrates how to configure Timer 1 to operate this way 9 3 5 Digital One Shot Example 9 3 configures Timer 1 to act as a digital one shot 9 17 TIMER COUNTER UNIT Smod186 name example FUNCTION OUTPUTS NOTE 80186 family timer code This function sets up the timer and interrupt contro
45. bit controls write accesses to the EN bit Timers 0 and 1 can be programmed to use their input pins as enable functions also If a timer is disabled the count register does not incre ment when the counter element services the timer The Enable bit can be altered by programming or the timers can be programmed to disable them selves at the end of a counting sequence with the Continuous CONT bit If the timer is not pro grammed for continuous operation the Enable bit automatically clears at the end of a counting sequence In single maximum count mode this occurs after Maxcount Compare A is reached In dual maximum count mode this occurs after Maxcount Compare B is reached Timers 0 and 1 only 9 15 TIMER COUNTER UNIT intel The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timer counting When using internal clocking the input pin can be programmed either to enable the tim er or to reset the timer count depending on the state of the Retrigger RTG bit in the control reg ister When used as an enable function the input pin either allows input high or prevents input low timer counting To ensure recognition of an input level it must be valid for four CPU clocks This is due to the counter element s time multiplexed servicing scheme for the timers 9 2 6 Timer Interrupts All timers can generate internal interrupt requests Although all three timers share a single inter rupt request to th
46. er the pin is used as an I O port or for a peripheral function 11 1 INPUT OUTPUT PORTS intel From Integrated Port Peripheral Peripheral Data Multiplexer Read Port Data latch x Output Driver Write Port Data Latch Read Port Pin State Read Port Direction Control Internal Data Bus F Bus Write Port Direction Read Port Direction Write Port Control Port Control Latch To Integrated Peripheral Peripheral Direction Control Figure 11 1 Simplified Logic Diagram of a Bidirectional Port Pin A1247 0A intel INPUT OUTPUT PORTS 11 1 2 Input Port Figure 11 3 shows the internal construction of an input port pin An internal connection perma nently disables the three state output driver The Port Pin register holds the current state synchro nized to the CPU clock of the input pin The Port Direction and Port Data bits are not used for an input only port pin they can be used for storage 11 1 3 Output Port Figure 11 3 shows the internal construction of an output port pin An internal connection perma nently enables the three state output driver The Port Control latch selects the source of data for the pin which can be either the on chip peripheral or the Port Data latch The Port Direction bit has no effect on an output only pin it can be used for storage 11 1 4 Open Drain Bidirectional Port Figure 11 4 shows the internal control logic for the open drain bidirectional port pin The logic is sl
47. is asserted The CTS pin is level sensitive Asserting the CTS pin before a pending transmission for at least 1 clock cycles ensures that the entire frame will be transmitted See CTS Pin Tim ings on page 10 18 for details The TX machine can also transmit a break character Setting the SBRK bit forces the TXD pin immediately low The TXD pin remains low until the user clears SBRK The TX machine will continue the transmission sequence even if SBRK is set Use caution when setting SBRK or char acters will be lost 10 1 1 3 Modes 1 3 and 4 The three asynchronous modes of the serial ports Modes 1 3 and 4 operate in approximately the same manner Mode is the 8 bit asynchronous communications mode Each frame consists of a Start bit eight data bits and a stop bit as shown in Figure 10 4 When parity is used the eighth data bit becomes the parity bit Both the RX and TX machines use this frame in Mode 1 with no exceptions Mode 3 is the 9 bit asynchronous communications mode see Figure 10 5 Mode 3 is the same as Mode 1 except that a frame contains nine data bits The ninth data bit becomes the parity bit when the parity feature is enabled When parity is disabled the ninth data bit is controlled by the user See Modes 2 and 3 for Multiprocessor Communications on page 10 14 Mode 3 can be used with Mode 2 for multiprocessor communications or alone for 8 data bits parity frames Mode 4 is the 7 bit asynchronous commun
48. the transfer is indeterminate This action requires that the appropriate bank defined by BHE or AO high be disabled to prevent destroying data 3 4 intel BUS INTERFACE UNIT A19 1 D15 8 BHE Low A19 1 D15 8 BHE High A1108 0A Figure 3 4 16 Bit Data Bus Odd Word Transfers 3 2 2 8 Bit Data Bus The memory address space on an 8 bit data bus is physically implemented as one bank of 1 Mbyte see Figure 3 1 on page 3 2 Address lines A19 0 select a specific byte within the bank Unlike transfers with a 16 bit bus byte and word transfers to even or odd addresses all transfer data over the same 8 bit bus Byte transfers to even or odd addresses transfer information in one bus cycle Word transfers to even or odd addresses transfer information in two bus cycles The BIU automatically converts the Word access into two consecutive byte accesses making the operation transparent to the program mer 3 5 BUS INTERFACE UNIT intel For word transfers the word address defines the first byte transferred The second byte transfer occurs from the word address plus one Figure 3 5 illustrates a word transfer on an 8 bit bus in terface First Bus Cycle Second Bus Cycle Oo p EE A1109 0A Figure 3 5 8 Bit Data Bus Word Transfers 3 8 MEMORY AND I O INTERFACES The CPU can interface with 8 and 16 bit memory and I O devices Memory devices exchange information with the CPU during memory read memory write
49. there is still a chance that the processor will successfully refresh the corresponding row of cells in the DRAM retaining the data 7 4 REFRESH ADDRESSES Figure 7 3 shows the physical address generated during a refresh bus cycle This figure applies to both the 8 bit and 16 bit data bus microprocessor versions Refresh address bits RA19 13 come from the Refresh Base Address Register See Refresh Base Address Register on page 7 7 From Refresh Base Address Register From Refresh Address Counter Fixed mi RA RA RA RA RA RA RA RA RA RA RA RA RA RA RA RA RA RA RA 1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 19 0 20 Bit Refresh Address A1266 0A Figure 7 3 Refresh Address Formation A linear feedback shift counter generates address bits RA12 1 and RAO is always one The counter does not count linearly from 0 through FFFH However the counting algorithm cycles uniquely through all possible 12 bit values It matters only that each row of DRAM memory cells is refreshed at a specific interval The order of the rows is unimportant Address bit AO is fixed at one during all refresh operations In applications based on a 16 bit data bus processor AO typically selects memory devices placed on the low even half of the bus Ap plications based on an 8 bit data bus processor typically use AO as a true address bit The DRAM controller must not route AO to row address pins on the DRAMs 74 intel REFRESH CONTROL
50. 0100 hlt F5 1 0101 cmc F6 1 0110 mod 000 r m disp lo disp hi data 8 test reg8 mem8 immed8 mod 001 r m mod 010 r m disp lo disp hi not reg8 mem8 mod 011 r m disp lo disp hi neg reg8 mem8 mod 100 r m disp lo disp hi mul reg8 mem8s mod 101 r m disp lo disp hi imul reg8 mem8s mod 110 r m disp lo disp hi div reg8 mem8 mod 111 r m disp lo disp hi idiv reg8 mem8 F7 1111 0111 mod 000 r m disp lo disp hi data lo data hi test reg16 mem16 immed16 mod 001 r m mod 010 r m disp lo disp hi not reg16 mem16 mod 011 r m disp lo disp hi neg reg16 mem16 mod 100 r m disp lo disp hi mul reg16 mem16 mod 101 r m disp lo disp hi imul reg16 mem16 mod 110 r m disp lo disp hi div reg16 mem16 mod 111 r m disp lo disp hi idiv reg16 mem16 D 18 intel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued Byte 2 Bytes 3 6 ASN 86 Instruction Format Hex Binary F8 1 1000 clc F9 1 1001 stc FA 1 1010 cli FB 1 1011 sti FC 1 1100 cld FD 1 1101 std FE 1 1110 mod 000 r m disp lo disp hi inc mem16 mod 001 r m disp lo disp hi dec mem16 mod 010 r m FE 11111110 mod 011 r m mod 100 r m mod 101 r m 25 110 mod 111 r m FF 1111 1111 mod 000 r m disp lo disp hi inc mem16 mod 001 r m disp lo disp hi dec mem16 mod 010
51. 1 Initialization Sequence Chip selects do not have to be initialized in any specific order However the following guidelines help prevent a system failure 1 Initialize local memory chip selects 2 Initialize local peripheral chip selects 3 Perform local diagnostics 4 Initialize off board memory and peripheral chip selects 5 Complete system diagnostics An unmasked interrupt or NMI must not occur until the interrupt vector addresses have been writ ten to memory Failure to prevent an interrupt from occurring during initialization will cause a system failure Use external logic to generate the chip select if interrupts cannot be masked prior to initialization 6 6 intel CHIP SELECT UNIT Register Name Chip Select Start Register Register Mnemonic UCSST LCSST GCSxST x 0 7 Register Function Defines chip select start address and number of bus wait states 1 Bit Mnemonic A1163 0A Bit Name Function CS9 0 Start Defines the starting base address for the chip Address select CS9 0 are compared with the A19 10 memory bus cycles or A15 6 I O bus cycles address bits An equal to or greater than result enables the chip select Wait State WS3 0 define the minimum number of wait Value states inserted into the bus cycle A zero value means no wait states Additional wait states can be inserted into the bus cycle using bus ready NOTE Reserved register bits are shown with gray shad
52. 111 r m data 8 sar reg16 mem16 immed8 C2 1100 0010 data lo data hi ret immed16 intrasegment C3 1100 0011 ret intrasegment C4 1100 0100 mod reg r m disp lo disp hi les reg16 mem16 C5 1100 0101 mod reg r m disp lo disp hi Ids reg16 mem16 C6 1100 0110 mod 000 r m disp lo disp hi data 8 mov mem8 immed8 mod 001 r m mod 010 r m mod 011 r m mod 100 r m mod 101 r m mod 110 r m C6 1100 0110 mod 111 r m C7 1100 0111 mod 000 r m disp lo disp hi data lo data hi mov mem16 immed16 mod 001 r m a mod 010 r m mod 011 r m mod 100 r m mod 101 r m mod 110 r m mod 111 r m C8 1100 1000 data lo data hi level enter immed16 immed8 C9 1100 1001 leave CA 1100 1010 data lo data hi ret immed16 intersegment CB 1100 1011 ret intersegment cc 1100 1100 int 3 cD 1100 1101 data 8 int immed8 CE 1100 1110 into CF 1100 1111 iret DO 1101 0000 mod 000 r m disp lo disp hi rol reg8 mem8 mod 001 r m disp lo disp hi ror reg8 mem8 mod 010 r m disp lo disp hi rel reg8 mem8 mod 011 r m disp lo disp hi rer reg8 mem8 mod 100 r m disp lo disp hi sal shl reg8 mem8s 1 mod 101 r m disp lo disp hi shr reg8 mem8 mod 110 r m m mod 111 r m disp lo disp hi sar reg8 mem8 D 16 In lel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued
53. 12 initializing 11 11 input only 11 3 open drain bidirectional 11 3 output only 11 3 overview 11 1 port 1 11 7 port 2 11 7 programming 11 7 11 12 registers 11 7 11 11 reset status 11 11 T O space 3 1 3 7 accessing 3 6 reserved locations 2 15 6 14 Idle mode 5 11 5 16 5 16 bus operation 5 13 control register 5 12 entering 5 11 5 13 exiting 5 14 5 15 exiting HALT bus cycle 3 34 initialization code 5 15 5 16 Idle states and bus cycles 3 18 Immediate operands 2 28 IMUL instruction A 9 Input output ports 11 1 Inputs asynchronous synchronizing B 1 INS instruction A 2 In Service register 8 5 8 7 8 18 8 19 Instruction Pointer IP 2 1 2 6 2 13 2 23 2 39 2 41 reset status 2 6 Instruction prefetch bus cycle See Bus cycles Instruction set 2 17 A 1 D 1 additions A 1 Index 3 INDEX arithmetic instructions 2 19 2 20 A 9 bit manipulation instructions 2 21 2 22 9 data transfer instructions 2 18 2 20 A 1 A 8 data types 2 37 2 38 enhancements A 8 high level instructions A 2 nesting A 2 processor control instructions 2 27 program transfer instructions 2 23 2 24 reentrant procedures A 2 rotate instructions A 10 shift instructions A 9 string instructions 2 22 2 23 A 2 INT instruction single byte See Breakpoint interrupt INTO instruction 2 44 INTA bus cycle See Bus cycles Integer defined 2 37 12 7 Interrupt Control registers 8 12 for external pins 8
54. 14 8 15 for internal sources 8 13 Interrupt Control Unit ICU 8 1 8 24 block diagram 8 2 cascade mode 8 7 initializing 8 23 8 24 interfacing with an 82C59A Programmable Interrupt Controller 3 25 3 27 operation with nesting 8 4 programming 8 11 registers 8 11 special fully nested mode 8 8 with cascade mode 8 8 without cascade mode 8 8 typical interrupt sequence 8 5 Interrupt Enable Flag IF 2 7 2 9 2 41 Interrupt Mask register 8 17 Interrupt Request register 8 16 Interrupt Status register 8 7 8 22 8 23 Interrupt Vector Table 2 39 2 40 Interrupt on overflow trap Type 4 exception 2 44 Interrupts 2 39 2 43 and CSU initialization 6 6 controlling priority 8 12 edge and level sensitive 8 10 and external 8259As 8 10 enabling cascade mode 8 12 Index 4 intel enabling special fully nested mode 8 12 latency 2 45 reducing 3 28 latency and response times 8 10 8 11 maskable 2 43 masking 8 2 8 12 8 17 priority based 8 18 multiplexed 8 7 nesting 8 4 NMI 2 42 nonmaskable 2 45 overview 8 1 priority 2 46 2 49 8 3 default 8 3 resolution 8 5 8 6 processing 2 39 2 42 reserved 2 39 response time 2 46 selecting edge or level triggering 8 12 software 2 45 timer interrupts 9 16 types 8 9 See also Exceptions Interrupt Control Unit INTn instruction 2 45 Invalid opcode trap Type 6 exception 2 44 IRET instruction 2 41 L LEAVE instruction A 7 Local bus 3 1 3 39
55. 8086 8088 instruction set See Appendix 806186 Instruction Set Additions and Extensions for details INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 2 Instruction Set Summary Continued Function Format Clocks Notes PROGRAM TRANSFER INSTRUCTIONS Continued RET Return from procedure within segment 000011 16 within segment adding immed to SP 000010 data low data high 18 intersegment 001011 22 intersegment adding immed to SP 001010 data low data high 25 JMP Unconditional jump short long 101011 disp low 14 direct within segment 101001 disp low disp high 14 reg memory indirect within segment 111111 mod 100 r m 26 indirect intersegment 111111 mod 101 r m mod 11 1147 direct intersegment 101010 segment offset 14 selector Iteration Control LOOP Loop CX times 11100010 disp 6 16 2 LOOPZ LOOPE Loop while zero equal 11100001 disp 5 6 2 LOOPNZ LOOPNE 11100000 disp 5 16 2 Loop while not zero not equal JCXZ Jump if CX zero 11100011 disp 6 16 2 Interrupts INT Interrupt Type specified 11001101 type 47 Type 3 11001100 45 INTO Interrupt on overflow 11001110 48 4 3 BOUND Detect value out of range 01100010 mod reg r m 33 35 IRET Interrupt return 11001111 28 NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock
56. A or Main via the appropriate BP in the display see Figure A 5 After Procedure B calls Procedure C ENTER creates the display for Procedure C The first word of the display points to the previous value of BP BPB The second word points to the value of BP for MAIN BPM The third word points to the value of BP for Procedure A BPA The fourth word points to the current BP BPC Because Procedure B and Procedure C have the same lexical nesting level Procedure C cannot access variables in Procedure B The only pointer to Procedure B in the display of Procedure C exists to allow the LEAVE instruction to collapse the Procedure C stack frame see Figure A 6 5 800186 INSTRUCTION SET ADDITIONS AND EXTENSIONS intel Display B Dynamic Storage B A1004 0A Figure A 5 Stack Frame for Procedure B at Level 3 Called from A A 6 intel 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Display C Dynamic Storage C A1005 0A Figure A 6 Stack Frame for Procedure C at Level 3 Called from B LEAVE LEAVE reverses the action of the most recent ENTER instruction It collapses the last stack frame created First LEAVE copies the current BP to the Stack Pointer releasing the stack space allocated to the current procedure Second LEAVE pops the old value of BP from the stack to return to the calling procedure s stack frame A RET instruction will remove arguments stacked by the calling procedure for use by the called procedu
57. BIU drives address data status and control information to define a bus cycle The start of a bus cycle presents the address of a memory or I O location and status information defining the type of bus cycle Read or write control signals follow the address and define the direction of data flow A read cycle requires data to flow from the selected memory or I O device to the BIU Ina write cycle the data flows from the BIU to the selected memory or I O device Upon termination of the bus cycle the BIU latches read data or removes write data 3 1 MULTIPLEXED ADDRESS AND DATA BUS The BIU has a combined address and data bus commonly referred to as a time multiplexed bus Time multiplexing address and data information makes the most efficient use of device package pins A system with address latching provided within the memory and I O devices can directly connect to the address data bus or local bus The local bus can be demultiplexed with a single set of address latches to provide non multiplexed address and data information to the system 3 2 ADDRESS AND DATA BUS CONCEPTS The programmer views the memory or I O address space as a sequence of bytes Memory space consists of 1 Mbyte while I O space consists of 64 Kbytes Any byte can contain an 8 bit data element and any two consecutive bytes can contain a 16 bit data element identified as a word The discussions in this section apply to both memory and I O bus cycles For brevity memory bus cyc
58. BREAK characters of two different lengths If a BREAK character longer than M bit times is detected the DBRKO bit in SxSTS is set If the BREAK character is longer than 2M 3 bit times DBRK1 in SxSTS is set M is equal to the total number of bits in a frame For example M is equal to 11 decimal in Mode 3 Register Name Serial Status Register Register Mnemonic SxSTS Register Function Indicates the status of the serial port 15 A1278 0A Bit i Function Mnemonic Bit Name unctio DBRK1 Detect Break 1 Set when a break longer than 2M 3 bits occurs DBRKO Detect Break 0 Set when a break longer than M bits occurs RB8 PE Received Contains the 9th received data bit in modes 2 Bit8 Parity and 3 PE is set when a parity error occurs PE Error is valid only when parity is enabled in Mode 1 20r 3 Receive RI is set when a character has been received Interrupt and placed in SxRBUF Note that RI need not be explicitly cleared to receive more characters Writing a one to this bit will not cause an interrupt Transmit Tl is set when a character has finished trans Interrupt mitting TI determines when one more character can be transmitted Writing a one to this bit will not cause an interrupt NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 10 14 Serial Port Status Register
59. DESCRIPTIONS Table C 4 Instruction Set Continued intel E Flags Name Description Operation Affected CBW Convert Byte to Word if AF CBW AL 80H CF then DF Extends the sign of the byte in register 0 IF AL throughout register AH Use to else OF produce a double length word lt dividend from a byte prior to SF performing byte division Instruction Operands ZF none CLC Clear Carry flag CF 0 AF CLC 2 d Zeroes the carry flag CF and affects IF no other flags Useful in conjunction OF with the rotate through carry left RCL PF and the rotate through carry right SF RCR instructions Instruction Operands 2 CLD Clear Direction flag DF 0 AF CLD ORS m DF Zeroes the direction flag DF causing IF the string instructions to auto OF increment the source index SI and or PF destination index DI registers SF Instruction Operands TF none zF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued Name Description Operation
60. HALT entente e tdi eet Ate tret a dr ced 3 32 3 6 SYSTEM DESIGN ALTERNATIVES esessssseeeeeeenenennneneeen rennen nene 3 34 3 6 1 Buttering the Data BUS ura te tee nce etr ase tine eet 3 35 3 6 2 Synchronizing Software and Hardware Events 3 37 3 6 3 Using a Locked BUS J tit oh tise teer RE ederet 3 38 3 7 MULTI MASTER BUS SYSTEM DESIGNS senem 3 39 3 7 1 Entering Bus HOLD eee nn hie nn e ets 3 39 3 7 1 1 HOLD Bus Cateney ote mr De eth ae edie cv iie eda 3 40 3 7 1 2 Refresh Operation During a BUS HOLD eee 3 41 94 2 Exiting HOLED a dde eee ele 3 43 3 8 BUS CYCGLE PRIORITIES ttt t tet nett 3 44 intel CHAPTER 4 PERIPHERAL CONTROL BLOCK 4 1 PERIPHERAL CONTROL REGISTERS seen 4 1 4 2 PCB REEOCATION REGISTER 2 reri teniente etm t eset te 4 1 4 3 RESERVED HOGATIONS RR RR MARRE 4 4 4 4 ACCESSING THE PERIPHERAL CONTROL BLOCK seen 4 4 4 4 1 B s Cycles 5 stmt qc mec eee LR et eb i o Peres 4 4 4 4 2 READY Signals and Wait States ssssssssssseeeeneeneeennenenn 4 4 4 4 3 cd e e e Pene n te Ded ia 4 5 4 4 3 1 Writing the PCB Relocation Register seesseeeenee 4 6 4 4 3 2 Accessing the Peripheral Control Registers 4 6 4 4 3 3 Acce
61. IF bytes or words replaces the OF v destination operand Both operands PF v may be signed or unsigned binary SF v numbers see AAA and DAA TE Instruction Operands ZF ADD reg reg ADD reg mem ADD mem reg ADD reg immed ADD mem immed ADD accum immed AND And Logical dest dest and src AF AND dest src CF 0 CF v OF 0 DF Performs the logical and of the two IF operands byte or word and returns OF v the result to the destination operand A PF v bit in the result is set if both corre SF v sponding bits of the original operands TF are set otherwise the bit is cleared ZF v Instruction Operands AND reg reg AND reg mem AND mem reg AND reg immed AND mem immed AND accum immed NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued EM A Flags Name Description Operation Affected BOUND Detect Value Out of Range if AF BOUND dest src n src or dest gt src 2 a en m Provides array bounds checking in SP SP 2 IF hardware The calculated array index SP 1 SP lt FLAGS OF is placed in one of the gener
62. If IF is clear maskable interrupts are ignored Trap Flag If TF is set the processor enters single step mode Sign Flag If SF is set the high order bit of the result of an operation is 1 indicating it is negative Zero Flag If ZF is set the result of an operation is zero Auxiliary Flag If AF is set there has been a carry from the low nibble to the high or a borrow from the high nibble to the low nibble of an 8 bit quantity Used in BCD operations PF Parity Flag If PF is set the result of an operation has even parity CF Carry Flag If CF is set there has been a carry out of or a borrow into the high order bit of the result of an instruction NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 2 5 Processor Status Word OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Fully Overlapped Partly Overlapped Logical Contiguous Segments Semen Sees Semet Physical Memory 10000H 20000H 30000H A1036 0A Figure 2 6 Segment Locations in Physical Memory The four segment registers point to four currently addressable segments see Figure 2 7 The currently addressable segments provide a work space consisting of 64 Kbytes for code a 64 Kbytes for stack and 128 Kbytes for data storage Programs access code and data in anot
63. Implementing a Power Management Scheme sese 5 19 CHAPTER 6 CHIP SELECT UNIT 6 1 COMMON METHODS FOR GENERATING 6 1 6 2 CHIP SELECT UNIT FEATURES AND BENEFITS eene 6 1 6 3 CHIP SELECT UNIT FUNCTIONAL OVERVIEW eeeeeeenenne ee 6 2 6 4 PROGRAMMING 1 ea er tee ue ete oper dae ts 6 5 6 4 1 Initialization Sequence 3 aan Rottend testo 6 6 6 4 2 Stat Address caede erg np eitis ene eem 6 10 6 59 Stop Addiess x uae epe REIP DRE RON 6 10 SUENE intel 6 4 4 Enabling and Disabling Chip Selects ccceeceeeeeeeseeeeeeeceeeeeeeeeaeeeaeeseeeeteaeeeneeeee 6 11 6 4 5 Wait State and Ready Control sessssssssseeeeneeeeeen enn 6 11 6 4 6 Overlapping Chip Selects sseseeseseseeeeeeeeeeeneen nennen nnne nnn 6 12 6 4 4 Memory or I O Bus Cycle Decoding esee 6 14 6 4 8 Programming Considerations sese 6 14 6 5 GHIP SELEGCTS AND BUS HOLD eicit ce tc terret cce ent eden 6 15 6 6 EXAMPLES cnp ge din DOE ERR EC HEEL Pe lie e ve DR Deo 6 15 6 6 1 Example 1 Typical System Configuration sene 6 15 6 6 2 Example 2 Detecting Attempts to Access Guarded Memory 6 20 CHAPTER 7 REFRESH CONTROL UNIT 7 1 THE ROLE OF THE REFRESH CONTROL UNIT esee 7 2 7 2 REFRESH CONTROL UNIT CAPABI
64. JE JZ Jump if equal zero JG JNLE Jump if greater not less nor equal JGE JNL Jump if greater or equal not less JL JNGE Jump if less not greater nor equal JLE JNG Jump if less or equal not greater JNC Jump if not carry JNE JNZ Jump if not equal not zero JNO Jump if not overflow JNP JPO Jump if not parity parity odd JNS Jump if not sign JO Jump if overflow JP JPE Jump if parity parity even JS Jump if sign Unconditional Transfers CALL Call procedure RET Return from procedure JMP Jump Iteration Control LOOP Loop LOOPE LOOPZ Loop if equal zero LOOPNE LOOPNZ Loop if not equal not zero JCXZ Jump if register CX 0 Interrupts INT Interrupt INTO Interrupt if overflow BOUND Interrupt if out of array bounds IRET Interrupt return OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 25 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Iteration control instructions can be used to regulate the repetition of software loops These in structions use the CX register as a counter Like the conditional transfers the iteration control in structions are self relative and can transfer only to targets that are within 128 to 127 bytes of themselves They are SHORT transfers The interrupt instructions allow programs and external hardware devices to activate interrupt ser vice routines The effect of a software interrupt is similar to that of a hardware initiated interrupt The processor cannot execute an interrupt acknowledge bus cycle if the inter
65. Latch A1505 0A Figure 11 2 Simplified Logic Diagram of an Input Port Pin intel INPUT OUTPUT PORTS From Integrated Peripheral Output Driver Read Port Permenantly Disabled Data latch 5 Pin Write Port Data Latch Read Port Pin State Read Port Direction Control Internal Data Bus F Bus Write Port Direction Read Port Direction Li Write Port Control Port Control Latch To Integrated Peripheral A1248 0A Figure 11 3 Simplified Logic Diagram of an Output Port Pin INPUT OUTPUT PORTS intel From Port Direction Latch Read Port Data Latch Internal Data Bus Port Data Latch e Write Port Data Latch E E Read Port Pin State From Port Control Latch A1249 0A Figure 11 4 Simplified Logic Diagram of an Open Drain Bidirectional Port 11 6 intel INPUT OUTPUT PORTS 11 1 5 1 Port 1 Organization Port 1 consists of eight output only port pins The Port 1 pins are multiplexed with the general purpose chip selects GCS7 0 Table 11 1 shows the multiplexing options for Port 1 Table 11 1 Port 1 Multiplexing Options Pin Name Peripheral Function Port Function P1 7 GCS7 GCS7 P1 7 P1 6 GCS6 GCS6 P1 6 P1 5 GCS5 GCS5 P1 5 P1 4 GCS4 GCS4 P1 4 P1 3 GCS3 GCS3 P1 3 P1 2 GCS2 GCS2 P1 2 P1 1 GCS1 GCS1 P1 1 P1 0 GCSO GCSO P1 0 11 1 5 2 Port 2 Organization Six of the Port 2 pins are multiplexed with serial channel functi
66. OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE intel Single step priority is a special case If an interrupt NMI or maskable occurs at the same instruc tion boundary as a single step the interrupt vector is taken first then is followed immediately by the single step vector However the single step service routine is executed before the interrupt service routine see Figure 2 29 If the single step service routine re enables single step by exe cuting the IRET the interrupt service routine will also be single stepped This can severely limit the real time response of the CPU to an interrupt To prevent the single step routine from executing before a maskable interrupt disable interrupts while single stepping an instruction then enable interrupts in the single step service routine The maskable interrupt is serviced from within the single step service routine and that interrupt ser vice routine is not single stepped To prevent single stepping before an NMI the single step ser vice routine must compare the return address on the stack to the NMI vector If they are the same return to the NMI service routine immediately without executing the single step service routine Instruction Trap Flag 1 Push PSW CS IP Fetch Divide Error Vector Trap Flag 0 Push PSW CS IP Fetch Single Step Vector Execute Single Step Service Routine Trap Flag A1032 0A Figure 2 29 Simultaneous NMI and Single Step Interrupts The most comp
67. Peripheral Control Registers Byte instructions should be used for the registers in the Peripheral Control Block of an 80C188 Modular Core family member This requires half the bus cycles of word operations Byte opera tions are valid only for even addressed writes to the Peripheral Control Block A word read e g IN AX DX must be performed to read a 16 bit Peripheral Control Block register when possible 4 4 3 3 Accessing Reserved Locations Unused locations are reserved If a write is made to these locations a bus cycle occurs but data is not stored If a subsequent read is made to the same location the value written is not read back If reserved registers are written for example during a block MOV instruction they must be cleared to 0H NOTE Failure to follow this guideline could result in incompatibilities with future 80C186 Modular Core family products 4 5 SETTING THE PCB BASE LOCATION Upon reset the PCB Relocation Register see Figure 4 1 on page 4 2 contains the value OOFFH which causes the Peripheral Control Block to be located at the top of I O space OFFOOH to OFFFFH Writing the PCB Relocation Register allows the user to change that location 4 6 intel PERIPHERAL CONTROL BLOCK As an example to relocate the Peripheral Control Block to the memory range 10000 100FFH the user would program the PCB Relocation Register with the value 1100H Since the Relocation Register is part of the Peripheral Control Block
68. RR NAN EE NRA EC ERE OSEE Wat RAM wah AA select_slave FUNCTION This function transmits a slave address _slave_addr over the serial network with data bit 9 set to one It then waits for the addressed slave to respond with its slave address If this address does not match the originally transmitted slave address or if there is no response within a set time the function will return false ax 0 Otherwise the function will return true ax lt gt 0 SYNTAX extern int far select slave int slave addr INPUTS Slave addr address of the slave on the network OUTPUTS True False NOTE Parameters are passed on the stack as required by high level languages Example assumes that PCB is located in I O space KKK ck ck ck ck ck ck kk Ck CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC x x A KK kx x KK substitute register offset in place of xxxxh P1CON equ xxxxh Port 1 Control register P2CON equ xxxxh Port 2 Control register S1CON equ xxxxh Serial Port 1 Control register S1STS equ xxxxh Serial Port Status register 1 S1TBUF equ xxxxh Serial Port 1 Transmit Buffer 1 SIRBUF equ xxxxh Serial Port Receive Buffer lib 80186 segment public code assume cs lib 80186 public Select slave Select slave proc far push bp Save caller s bp mov bp sp get current top of stack get slave address off the stack Slave addr equ word ptr bp 6 push cx save registers that will be push dx mod
69. SYNCHRONIZATION intel A synchronization failure can occur when the output of the first latch does not meet the setup and hold requirements of the input of the second latch The rate of failure is determined by the actual size of the sampling window of the data latch and by the amount of time between the strobe sig nals of the two latches As the sampling window gets smaller the number of times an asynchro nous transition occurs during the sampling window drops B 2 ASYNCHRONOUS PINS The 80C186EB 80C188EB inputs that use the two stage synchronization circuit are TOIN T1IN NMI TEST BUSY INT4 0 HOLD and all Port 2 input functions P2 5 BCLKO P2 2 BCLK1 and P2 4 CTST B 2 intel Instruction Set Descriptions APPENDIX C INSTRUCTION SET DESCRIPTIONS This appendix provides reference information for the 80C186 Modular Core family instruction set Tables C 1 through C 3 define the variables used in Table C 4 which lists the instructions with their descriptions and operations Table C 1 Instruction Format Variables Variable Description dest A register or memory location that may contain data operated on by the instruction and which receives is replaced by the result of the operation src A register memory location or immediate value that is used in the operation but is not altered by the instruction target A label to which control is to be transferred directly or a register or memory location whose
70. SxSTS 10 16 intel SERIAL COMMUNICATIONS UNIT Register Name Serial Status Register Register Mnemonic SxSTS Register Function Indicates the status of the serial port 15 A1278 0A Bit 2 i Function Mnemonic Bit Name unctio FE Framing Error FE is set when a framing error occurs A framing error occurs when a valid stop bit is not detected Transmitter TXE is set when both SxTBUF and the transmit Empty shift register are empty TXE determines when two consecutive bytes can be written to SxTBUF for transmission Accessing SxSTS does not clear TXE Overrun Error OE is set when an overrun error occurs An overrun error occurs when the character in SxRBUF is not read before another complete character is received SxRBUF always contains the most recent reception CTS Clear To Send CTS is the complement of the value on the CTF pin Accessing SxSTS does not clear CTS NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 10 14 Serial Port Status Register Continued When either BREAK character is detected an overrun error occurs OE is set SXRBUF will con tain at least one null character 10 17 SERIAL COMMUNICATIONS UNIT intel 10 2 3 Programming in Mode 0 Programming is much easier in Mode 0 than in the asynchronous modes Configuring SxCON Figure 10 13 on page 10
71. The default priorities are used Ihe example assumes that the register addresses have been properly defined code Segment assume cs code set int proc near push dx push ax mov ax 0110111B cascade mode priority seven mov dx IO0CON INTO control register out dx ax mov ax 01001101B unmask INT1 and INT3 mov dx IMASK out dx ax pop ax pop dx ret endp ends end Example 8 1 Initializing the Interrupt Control Unit 8 24 intel Timer Counter Unit intel CHAPTER 9 TIMER COUNTER UNIT The Timer Counter Unit can be used in many applications Some of these applications include a real time clock a square wave generator and a digital one shot All of these can be implemented in a system design A real time clock can be used to update time dependent memory variables A square wave generator can be used to provide a system clock tick for peripheral devices See Timer Counter Unit Application Examples on page 9 17 for code examples that configure the Timer Counter Unit for these applications 9 1 FUNCTIONAL OVERVIEW The Timer Counter Unit is composed of three independent 16 bit timers see Figure 9 1 The op eration of these timers is independent of the CPU The internal Timer Counter Unit can be mod eled as a single counter element time multiplexed to three register banks The register banks are dual ported between the counter element and the CPU During a given bus cycle the counter el ement
72. UNIT 7 5 REFRESH BUS CYCLES Refresh bus cycles look exactly like ordinary memory read bus cycles except for the control sig nals listed in Table 7 1 These signals can be ANDed in a DRAM controller to detect a refresh bus cycle The 16 bit bus processor drives both the BHE and AO pins high during refresh cycles The 8 bit bus version replaces the BHE pin with RFSH which has the same timings The 8 bit bus processor drives RFSH low and AO high during refresh cycles Table 7 1 Identification of Refresh Bus Cycles Data Bus Width BHE RFSH AO 16 Bit Device 1 1 8 Bit Device 0 1 7 6 GUIDELINES FOR DESIGNING DRAM CONTROLLERS The basic DRAM access method consists of four phases 1 The DRAM controller supplies a row address to the DRAMs 2 The DRAM controller asserts a Row Address Strobe RAS which latches the row address inside the DRAMs 3 The DRAM controller supplies a column address to the DRAMs 4 The DRAM controller asserts a Column Address Strobe CAS which latches the column address inside the DRAMs Most 80C186 Modular Core family DRAM interfaces use only this method Others are not dis cussed here The DRAM controller s purpose is to use the processor s address status and control lines to gen erate the multiplexed addresses and strobes These signals must be appropriate for three bus cycle types read write and refresh They must also meet specific pulse width setup and hold timing requ
73. accumulator 0010010w data data if w 1 3 4 1 OR Or reg memory and register to either 000010dw mod reg r m 3 10 immediate to register memory 1000000w mod 001 r m data data if w 1 4 10 immediate to accumulator 0000110w data data if w 1 3 4 1 XOR Exclusive or reg memory and register to either 001100dw mod reg r m 310 immediate to register memory 1000000w mod 110 r m data data if w 1 4 10 immediate to accumulator 0011010w data data if w 1 3 4 1 NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the 8086 8088 instruction set See Appendix A 80C 186 Instruction Set Additions and Extensions for details INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 2 Instruction Set Summary Continued Function Format Clocks Notes BIT MANIPULATION INSTRUCTIONS Continued TEST And function to flags no result register memory and register 1000010w mod reg r m 3 10 immediate data and register memory 1111011w mod 000 r m data data if w 1 4 10 immediate data and accumulator 1010100w data data if w 1 3 4 1 Shifts Rotates register memory by 1 1101000w mod TTT r m 2 15 register memory by CL 1101001w mod TTT r m 5 n 17 n register m
74. address bits are equal to or greater than the start address value causes the chip select to go active Table 6 2 defines the address bits that are compared with the start address value for memory and I O bus cycles It is not possible to have a chip select start on any arbitrary byte boundary A chip select config ured for memory accesses can start only on multiples of 1 Kbyte A chip select configured for I O accesses can start only on multiples of 64 bytes The equations below calculate the physical start address for a given start address value For memory accesses Start Value Decimal x 1024 Physical Start Address Decimal For I O accesses Start Value Decimal x 64 Physical Start Address Decimal Table 6 2 Memory and I O Compare Addresses Address Space Address Range Number of Bits Comparator Input Resolution Memory 1 Mbyte 20 A19 A10 1 Kbyte 64 Kbyte 16 A15 A6 64 Bytes 6 4 8 Stop Address The STOP register of each chip select defines its ending address The stop address value is com pared to the ten most significant address bits of the bus cycle A bus cycle whose ten most sig nificant bits of address are less than the stop address value causes the chip select to go active Table 6 2 defines the address bits that are compared with the stop address value for memory and I O bus cycles It is not possible to have a chip select end on any arbitrary byte boundary A chip select config ured for
75. approx imate download time for tagged files intel Overview of the 80C186 Family Architecture CHAPTER 2 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The 80C186 Modular Microprocessor Core shares a common base architecture with the 8086 8088 80186 80188 80286 Intel386 and Intel486 processors The 80C186 Modular Core maintains full object code compatibility with the 8086 8088 family of 16 bit microprocessors while adding hardware and software performance enhancements Most instructions require fewer clocks to execute on the 80C186 Modular Core because of hardware enhancements in the Bus Interface Unit and the Execution Unit Several additional instructions simplify programming and reduce code size see Appendix A 80C186 Instruction Set Additions and Extensions 2 1 ARCHITECTURAL OVERVIEW The 80C186 Modular Microprocessor Core incorporates two separate processing units an Exe cution Unit EU and a Bus Interface Unit BIU The Execution Unit is functionally identical among all family members The Bus Interface Unit is configured for a 16 bit external data bus for the 80C186 core and an 8 bit external data bus for the 80C188 core The two units interface via an instruction prefetch queue The Execution Unit executes instructions the Bus Interface Unit fetches instructions reads op erands and writes results Whenever the Execution Unit requires another opcode byte it takes the byte out of the prefetch queue The two u
76. be at an unknown point in its timing cycle when the timer to be prescaled is enabled This results in an unpredictable duration of the first timing cycle for the prescaled timer TIMER COUNTER UNIT intel 9 2 2 Clock Sources The 16 bit Timer Count register increments once for each timer event A timer event can be a low to high transition on a timer input pin Timers 0 and 1 a pulse generated every fourth CPU clock all timers or a timeout of Timer 2 Timers 0 and 1 Up to 65536 219 events can be count ed Timers 0 and 1 can be programmed to count low to high transitions on their input pins as timer events by setting the External EXT bit in their control registers Transitions on the external pin are synchronized to the CPU clock before being presented to the timer circuitry The timer counts transitions on this pin The input signal must go low then high to cause the timer to increment The maximum count rate for the timers is 1 4 the CPU clock rate measured at CLKOUT because the timers are serviced only once every four clocks All timers can use transitions of the CPU clock as timer events For internal clocking the timer increments every fourth CPU clock due to the counter element s time multiplexed servicing scheme Timer 2 can use only the internal clock as a timer event Timers 0 and 1 can also use Timer 2 reaching its maximum count as a timer event In this config uration Timer O or Timer 1 increments each time Timer 2
77. begin discharging With a long enough delay the processor is likely to lose its present state needing a reset to resume normal operation An 80C186 Modular Core microprocessor is fully static The CPU stores its current state in flip flops not capacitive nodes The clock signal to both the CPU core and the peripherals can stop without losing any internal information provided the design maintains power When the clock restarts the device will execute from its previous state When the processor is inactive for significant periods special power management hardware takes advantage of static operation to achieve major power savings 5 10 intel CLOCK GENERATION AND POWER MANAGEMENT There are two power management modes Idle and Powerdown Power management is a clock distribution function For this discussion Active mode is the condition of no programmed power management Active mode operation feeds the clock signal to the CPU core and all the integrated peripherals and power consumption reaches its maximum for the application The processor de faults to Active mode at reset 5 2 1 Idle Mode During Idle mode operation the clock signal is routed only to the integrated peripheral devices CLKOUT continues toggling The clocks to the CPU core Execution and Bus Interface Units freeze in a logic low state Idle mode reduces current consumption by about a third depending on the activity in the peripheral units 5 2 1 1 Entering Idle Mode
78. content is the address of the location to which control is to be transferred indirectly disp8 A label to which control is to be conditionally transferred must lie within 7128 to 127 bytes of the first byte of the next instruction accum Register AX for word transfers AL for bytes port An I O port number specified as an immediate value of 0 255 or register DX which contains port number in range 0 64K src string Name of a string in memory that is addressed by register SI used only to identify string as byte or word and specify segment override if any This string is used in the operation but is not altered dest string Name of string in memory that is addressed by register DI used only to identify string as byte or word This string receives is replaced by the result of the operation count Specifies number of bits to shift or rotate written as immediate value 1 or register CL interrupt type Immediate value of 0 255 identifying interrupt pointer number which contains the count in the range 0 255 optional pop value Number of bytes 0 64K ordinarily an even number to discard from the stack external opcode Immediate value 0 63 that is encoded in the instruction for use by an external processor C 1 INSTRUCTION SET DESCRIPTIONS intel Table C 2 Instruction Operands Operand Description reg An 8 or 16 bit general reg
79. cover the associated peripheral Accessing the Peripheral Con trol Block on page 4 4 discusses how the registers are accessed and outlines considerations for reading and writing them 4 2 RELOCATION REGISTER In addition to control registers for the integrated peripherals the Peripheral Control Block con tains the PCB Relocation Register Figure 4 1 The Relocation Register is located at a fixed off set within the Peripheral Control Block Table 4 1 If the Peripheral Control Block is moved the Relocation Register also moves The PCB Relocation Register allows the Peripheral Control Block to be relocated to any 256 byte boundary within memory or I O space The Memory I O bit MEM selects either memory space or I O space and the R19 8 bits specify the starting base address of the PCB The remaining bit Escape Trap ET controls access to the math coprocessor interface Setting the PCB Base Location on page 4 6 describes how to set the base location and outlines some restrictions on the Peripheral Control Block location 4 1 PERIPHERAL CONTROL BLOCK intel Register Name PCB Relocation Register Register Mnemonic RELREG Register Function Relocates the PCB within memory or I O space 0 A1263 0A Bit Bit Nam Function Mnemonic EName uneto ET Escape Trap The ET bit controls access to the math copro cessor If ET is set the CPU will trap resulting in a Type 7 interrupt when an ESC inst
80. implementation can take one of two approaches normally not ready or normally ready 3 13 BUS INTERFACE UNIT intel CLKOUT Valid Write Data gt ER Data NOTES 1 T Clock low to valid RD WR active Write data valid CLOV R T Clock low to status inactive CLOV Tous Data input valid to clock low TeLov Clock valid to RD WR inactive Data HOLD from clock low Output data HOLD from WR high TWHDx TRHAV Bus no longer floating from RD high A1103 0A Figure 3 12 Data Phase Signal Relationships 3 14 intel BUS INTERFACE UNIT euer eT Mes EL rne E fiis X Address X Valid Write Data A1040 0A BUS READY CLKOUT A1079 01 Figure 3 14 READY Pin Block Diagram 3 15 BUS INTERFACE UNIT intel A normally not ready system is one in which READY remains low at all times except to signal a ready condition For any bus cycle only the selected device drives the READY input high to complete the bus cycle The circuit shown in Figure 3 15 illustrates a simple circuit to generate a normally not ready signal Note that if no device is selected the bus remains not ready indef initely Systems with many slow devices that cannot operate at the maximum bus bandwidth usu ally implement a normally not ready signal The start of a bus cycle clears the wait state module and forces READY low After every rising edge of CLKOUT INPUTI
81. intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2 5 Arithmetic Interpretation of 8 Bit Numbers vox ameter Signed Unpacked Footed 07 00000111 7 7 7 7 89 10001001 137 119 invalid 89 C5 11000101 197 59 invalid invalid 2 2 1 3 Bit Manipulation Instructions There are three groups of instructions for manipulating bits within bytes and words These three groups are logical shifts and rotates Table 2 6 lists the bit manipulation instructions and their functions Table 2 6 Bit Manipulation Instructions Logicals NOT Not byte or word AND And byte or word OR Inclusive or byte or word XOR Exclusive or byte or word TEST Test byte or word Shifts SHL SAL Shift logical arithmetic left byte or word SHR Shift logical right byte or word SAR Shift arithmetic right byte or word Rotates ROL Rotate left byte or word ROR Rotate right byte or word RCL Rotate through carry left byte or word RCR Rotate through carry right byte or word Logical instructions include the Boolean operators NOT AND OR and exclusive OR XOR as well as a TEST instruction The TEST instruction sets the flags as a result of a Boolean AND op eration but does not alter either of its operands Individual bits in bytes and words can be shifted either arithmetically or logically Up to 32 shifts can be performed according to the value of the count operand coded in the instruction Th
82. iret ASYNC REC INT PROCendp ASYNC XMIT INT PROCproc near This procedure is entered whenever a transmission completes Typical code would be inserted here to transmit the next byte from a transmit buffer set up in memory Since the configuration of such a buffer is application dependent this section is omitted Now we must issue the end of interrupt command to the interrupt unit eoi xmit int mov EOI mov ax 8000h issue non specific EOI out ax iret ASYNC XMIT INT PROCendp code seg ends end Example 10 1 Asynchronous Mode 4 Example Continued 10 25 SERIAL COMMUNICATIONS UNIT intel 10 5 2 Mode 0 Example Example 10 2 shows a sample Mode 0 application mod186 name example SCU mode 0 ck ck ck ck ck ck ck ck ck ck ck ck ck KKK KKK ck ck ck KKK KKK ck cock KEK kc ck KKK KKK KKK KKK KKK ko ko ko ck ko ko kc ko KKK FUNCTION This function transmits the user s data user data serially over RXD1 TXD1 provides the transmit clock The transmission frequency is calculated as follows tran freq 0 5 CLKIN BAUDRATE 1 A 0 1 0 pulse on P1 0 indicates the end of transmission SYNTAX extern void far parallel serial char user data int tran freq INPUTS user data byte to send out serially tran freq baud rate compare value OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages KKK ck ck ck ck ck ck kk Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck Ck CC CC CC CC CC CC CC C CC C
83. its original selection row addressing preparing for the next DRAM access 7 6 intel REFRESH CONTROL UNIT 7 7 PROGRAMMING THE REFRESH CONTROL UNIT Given a specific processor operating frequency and information about the DRAMSs in the system the user can program the Refresh Control Unit registers 7 7 1 Calculating the Refresh Interval DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary and the maximum period to run the cycles The number of refresh cycles is the same as the num ber of rows You must compensate for bus latency the time it takes for the Refresh Control Unit to gain control of the bus This is typically 1 5 but if an external bus master will be ex tremely slow to release the bus increase the overhead percentage At standard operating frequen cies DRAM refresh bus overhead totals 2 3 of the total bus bandwidth Given this information and the CPU operating frequency use the formula in Figure 7 5 to deter mine the correct value for the RFTIME Register value Rperiop X Fepu RFTIME Register Value Rows Rows x Overhead Reeriop Maximum refresh period specified by DRAM manufacturer in us Fopy Operating frequency in MHz Rows Total number of rows to be refreshed Overhead Derating factor to compensate for missed refresh requests typically 1 5 Figure 7 5 Formula for Calculating Refresh Interval for RFTIME Register 7 7 2 Refresh Contro
84. m disp lo disp hi sbb reg8 mem8 reg8 19 0001 1001 mod reg r m disp lo disp hi sbb reg16 mem16 reg16 1A 0001 1010 mod reg r m disp lo disp hi sbb reg8 reg8 mem8 1B 0001 1011 mod reg r m disp lo disp hi sbb reg16 reg16 mem16 1C 0001 1100 data 8 sbb AL immed8 1D 0001 1101 data lo data hi sbb AX immed16 1E 0001 1110 push DS 1F 0001 1111 pop DS 20 0010 0000 mod reg r m disp lo disp hi and reg8 mem8 reg8 21 0010 0001 mod reg r m disp lo disp hi and reg16 mem16 reg16 22 0010 0010 mod reg r m disp lo disp hi and reg8 reg8 mem8 23 0010 0011 mod reg r m disp lo disp hi and reg16 reg16 mem16 24 00100100 data 8 and AL immed8 25 0010 0101 data lo data hi and AX immed16 26 0010 0110 ES segment override prefix 27 0010 0111 daa 28 0010 1000 mod reg r m disp lo disp hi sub reg8 mem8 reg8 29 0010 1001 mod reg r m disp lo disp hi sub reg16 mem16 reg16 2A 0010 1010 mod reg r m disp lo disp hi sub reg8 reg8 mem8 2B 0010 1011 mod reg r m disp lo disp hi sub reg16 reg16 mem16 2C 0010 1100 data 8 sub AL immed8 2D 0010 1101 data lo data hi sub AX immed16 D 10 intel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued ee Byte 2 Bytes 3 6 ASM 86 Instruction Format Hex Binary 2E 0010 1110 DS segment override prefix 2F 0010 1111 das 30 001
85. or REP prefixes Instruction Operands none NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 27 INSTRUCTION SET DESCRIPTIONS intel Table C 4 Instruction Set Continued E Flags Name Description Operation Affected LODS Load String Byte or Word When Source Operand is a Byte AF LODS src string AL lt src string E Transfers the byte or word string if IF element addressed by SI to register AL DF 0 OF or AX and updates SI to point to the then PF next element in the string This SI lt SI DELTA SF instruction is not ordinarily repeated else _ since the accumulator would be SI lt SI DELTA ZF overwritten by each repetition and When Source Operand is a Word only the last element would be lt src string retained if Instruction Operands DF 0 LODS src string then LODS repeat src string a lt 51 DELTA else SI SI DELTA LOOP Loop CX CX 1 AF LOOP disp8 if CX 0 Decrements CX by 1 and transfers then IF control to the target location if CX is IP lt IP disp8 sign ext to 16 bits OF not 0 otherwise the instruction PF following LOOP is executed SF Ins
86. peripheral registers 1 800186 INSTRUCTION SET ADDITIONS AND EXTENSIONS intel A 1 2 String Instructions INS source string port INS in string performs block input from an I O port to memory The port address is placed in the DX register The memory address is placed in the DI register This instruction uses the ES segment register which cannot be overridden After the data transfer takes place the pointer reg ister DI increments or decrements depending on the value of the Direction Flag DF The pointer register changes by one for byte transfers or by two for word transfers OUTS port destination string OUTS out string performs block output from memory to an I O port The port address is placed in the DX register The memory address is placed in the SI register This instruction uses the DS segment register but this may be changed with a segment override instruction After the data transfer takes place the pointer register SI increments or decrements depending on the value of the Direction Flag DF The pointer register changes by one for byte transfers or by two for word transfers A 1 3 High Level Instructions ENTER size level ENTER creates the stack frame required by most block structured high level languages The first parameter size specifies the number of bytes of dynamic storage to be allocated for the procedure being entered 16 bit value The second parameter level is the lexical nesting level of t
87. pop dx restore saved registers pop ax pop bp restore user s bp ret parallel serial endp lib 80186 ends end Example 10 2 Mode 0 Example Continued 10 5 3 Master Slave Example This section shows an example of a Mode 2 and 3 master slave network Figure 10 20 shows the proper connection of the master to the slaves The buffer is necessary to avoid contention on the receive line Alternatively an open collector buffer could be used and the port pin function could be deleted 10 27 SERIAL COMMUNICATIONS UNIT intel MASTER 186 Core Device Master Transmit Line TXD RXD Port Pin 186 Core 80C196 Device SLAVES A1273 0A Figure 10 20 Master Slave Example Example 10 3 demonstrates how to implement a master slave network in a typical system The remaining three examples show the routines used in the implementation Example 10 4 is a mas ter routine that addresses a slave and waits for it to respond Example 10 5 is a slave routine that responds to commands sent by the master Equation 10 6 is the master routine that sends com mands to the slave 10 28 intel SERIAL COMMUNICATIONS UNIT mod186 name example master slave ck ck ck ck ck KKK KKK ck ck ck KKK ck ck ck KKK KKK ck ck ck KKK KKK KKK KKK ck ck ck KKK ck ck KKK KK oko ck ko kc ko ko ko ko ko ko KKK FUNCTION This function demonstrates how to implement the three master slave routines slave 1 select slave and send slave command in a
88. processor master slave network This slave responds to two commands Flash the LEDs on the EVAL Board and Disconnect from the Network Other commands are easily added SYNTAX extern void far slave l void INPUTS None OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages The slave should be running this code before the master calls the slave Example assumes PCB is in I O space ockck ck ck ck ck ck ck ck kk Ck Ck Ck CC Ck Ck Ck CC CC CC C CC CC CC C CC CC CC CC CC CC CC CC CC x x x x X x kx x x X Substitute register offsets in place of xxxxh P1CON equ xxxx Port 1 Control register PILTCH equ Port 1 Latch register P2CON equ Xxxx Port 2 Control register S1CON equ xxxx Serial Port 1 Control register S1STS equ Serial Port 1 Status register S1TBUF equ XXXX Serial Port 1 Transmit Buffer SIRBUF equ XXXX Serial Port 1 Receive Buffer lib 80186 segment public code assume cs lib 80186 My Address equ Olh Slave 1 network address TriStateEna equ 08h Tri state buffer enable TriStateDis equ 00h Tri state buffer disable FlashLEDs equ Olh list of commands unit 1 responds to Disconnect equ Ofh public _51 1 _slave_l proc far push ax save registers that will be modified push bx push cx push dx Example 10 5 Master Slave The slave 1 Routine 10 32 intel SERIAL COMMUNICATIONS UNIT DisconnectMode dx STSTS clear any pending exception
89. r m disp lo disp hi call reg16 mem16 intrasegment mod 011 r m disp lo disp hi call mem16 intersegment mod 100 r m disp lo disp hi jmp reg16 mem16 intrasegment mod 101 r m disp lo disp hi jmp mem16 intersegment mod 110 r m disp lo disp hi push mem16 mod 111 r m INSTRUCTION SET OPCODES AND CLOCK CYCLES intel Table D 4 Mnemonic Encoding Matrix Left Half x0 x1 x2 x3 x4 x5 x6 x7 ADD ADD ADD ADD ADD ADD PUSH POP Ox b f r m w f r m b t r m w tr m b ia w ia ES ES ADC ADC ADC ADC ADC ADC PUSH POP 1x b f r m w f r m b t r m w t r m w i SS SS AND AND AND AND AND AND SEG DAA 2x b f r m w f r m b t r m w t r m w i ES XOR XOR XOR XOR XOR XOR SEG AAA 3x b f r m w f r m b t r m w tr m b i w i SS INC INC INC INC INC INC INC INC 4x AX CX DX BX SP BP SI DI PUSH PUSH PUSH PUSH PUSH PUSH PUSH PUSH 5x AX CX DX BX SP BP SI DI PUSHA POPA BOUND 6x w f r m JO JNO JB JNB JE JNE JBE JNBE 7X JNAE JAE JZ JNZ JNA JA JC JNC Immed Immed Immed Immed TEST TEST XCHG XcHG 8x b r m w r m b r m is r m b r m w r m b r m w r m NOP XCHG XCHG XCHG XCHG XCHG XCHG XCHG 9x XCHG AX CX DX BX SP BP SI DI MOV MOV MOV MOV MOVS MOVS CMPS CMPS Ax mAL m AX AL gt m AX gt m MOV MOV MOV MOV MOV MOV MOV MOV Bx i gt AL i2CL i2DL ioBL iAH i gt CH i2BH Shift Shift RET RET LES LDS MOV MOV Cx bi wi i SP b i
90. register SF This instruction uses the DS segment TF register but this may be changed with ZF a segment override instruction After the data transfer takes place the pointer register SI increments or decrements depending on the value of the direction flag DF The pointer register changes by 1 for byte transfers or 2 for word transfers Instruction Operands OUTS port src_string OUTS repeat port src_string POP Pop dest lt SP 1 SP AF POP dest SP lt SP 2 DF Transfers the word at the current top of IF stack pointed to by SP to the OF destination operand and then PF increments SP by two to point to the SF new top of stack _ Instruction Operands ZF POP reg POP seg reg CS illegal POP mem NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 33 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel Flags Name Description Operation Affected POPA Pop All 01 lt SP 1 SP AF POPA SP lt SP 2 CF SI lt SP 1 SP DF Pops all data pointer and index SP SP 2 IF registers off of the stack The SP value BP SP 1 SP OF p
91. repetitions can be termi nated by a variety of conditions Repeated operations can be interrupted and resumed Table 2 7 String Instructions REP Repeat REPE REPZ Repeat while equal zero REPNE REPNZ Repeat while not equal not zero MOVSB MOVSW Move byte string word string MOVS Move byte or word string INS Input byte or word string OUTS Output byte or word string CMPS Compare byte or word string SCAS Scan byte or word string LODS Load byte or word string STOS Store byte or word string String instructions operate similarly in many respects see Table 2 8 A string instruction can have a source operand a destination operand or both The hardware assumes that a source string resides in the current data segment A segment prefix can override this assumption A destination string must be in the current extra segment The assembler does not use the operand names to ad dress strings Instead the contents of the Source Index SI register are used as an offset to address the current element of the source string The contents of the Destination Index DI register are taken as the offset of the current destination string element These registers must be initialized to point to the source and destination strings before executing the string instructions The LDS LES and LEA instructions are useful in performing this function 2 22 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE String instructions au
92. required 2 required 2 required 2 required Be cautious when overlapping chip selects with different wait state or bus ready programming The following two conditions require special attention to ensure proper system operation 1 When all overlapping chip selects ignore bus ready but have different wait states verify that each chip select still works properly using the highest wait state value A system failure may result when too few or too many wait states occur in the bus cycle 2 If one or more of the overlapping chip selects requires bus ready verify that all chip selects that ignore bus ready still work properly using both the smallest wait state value and the longest possible bus cycle A system failure may result when too few or too many wait states occur in the bus cycle 6 4 7 Memory or I O Bus Cycle Decoding The Chip Select Unit decodes bus cycle status and address information to determine whether a chip select goes active The MEM control bit in the STOP register defines whether memory or T O address space is decoded Memory address space accesses consist of memory read memory write and instruction prefetch bus cycles I O address space accesses consist of I O read and I O write bus cycles Chip selects go active for bus cycles initiated by the CPU and Refresh Control Unit 6 4 8 Programming Considerations When programming chip selects active for I O bus cycles remember that eight bytes of I O are re
93. right shifts the destination operand right by an immediate val ue SAL has two operands The first destination is the effective address to be shifted The sec ond count is an immediate byte value representing the number of shifts to be made The CPU will AND count with 1FH before shifting to allow no more than 32 shifts The value of the orig inal sign bit shifts into the most significant bit to preserve the initial sign SHR destination count SHR immediate shift logical right is physically the same instruction as SAR immediate shift arithmetic right 9 800186 INSTRUCTION SET ADDITIONS AND EXTENSIONS intel A 2 3 2 Rotate Instructions ROL destination count ROL immediate rotate left rotates the destination byte or word left by an immediate value ROL has two operands The first destination is the effective address to be rotated The second count is an immediate byte value representing the number of rotations to be made The most significant bit of destination rotates into the least significant bit ROR destination count ROR immediate rotate right rotates the destination byte or word right by an immediate value ROR has two operands The first destination is the effective address to be rotated The second count is an immediate byte value representing the number of rotations to be made The least sig nificant bit of destination rotates into the most significant bit RCL destination count RCL immediate
94. rise to the 80286 microprocessor in 1982 The 80286 began the trend toward the very high performance Intel architecture that today includes the Intel386 Intel486 and Pentium microprocessors As technology advanced and turned toward small geometry CMOS processes it became clear that a new 80186 was needed In 1987 Intel announced the second generation of the 80186 family the 80C186 C188 The 80C186 family is pin compatible with the 80186 family while adding an enhanced feature set The high performance CHMOS III process allowed the 80C186 to run at twice the clock rate of the NMOS 80186 while consuming less than one fourth the power The 80186 family took another major step in 1990 with the introduction of the 80C186EB family The 80C186EB heralded many changes for the 80186 family First the enhanced 8086 8088 CPU was redesigned as a static stand alone module known as the 80C 186 Modular Core Second the 80186 family peripherals were also redesigned as static modules with standard interfaces The goal behind this redesign effort was to give Intel the capability to proliferate the 80186 family rapidly in order to provide solutions for an even wider range of customer applications The 80C186EB C188EB was the first product to use the new modular capability The 80C186EB C188EB includes a different peripheral set than the original 80186 family Power consumption was dramatically reduced as a direct result of the static design power manage
95. rotate through carry left rotates the destination byte or word left by an imme diate value RCL has two operands The first destination is the effective address to be rotated The second count is an immediate byte value representing the number of rotations to be made The Carry Flag CF rotates into the least significant bit of destination The most significant bit of destination rotates into the Carry Flag RCR destination count RCR immediate rotate through carry right rotates the destination byte or word right by an im mediate value RCR has two operands The first destination is the effective address to be rotated The second count is an immediate byte value representing the number of rotations to be made The Carry Flag CF rotates into the most significant bit of destination The least significant bit of destination rotates into the Carry Flag A 10 intel Input Synchronization APPENDIX B INPUT SYNCHRONIZATION Many input signals to an embedded processor are asynchronous Asynchronous signals do not re quire a specified setup or hold time to ensure the device does not incur a failure However asyn chronous setup and hold times are specified in the data sheet to ensure recognition Associated with each of these inputs is a synchronizing circuit see Figure B 1 that samples the asynchro nous signal and synchronizes it to the internal operating clock The output of the synchronizing circuit is then safely routed to th
96. segment register delay the servicing of interrupts until after the following instruction The delay allows a 32 bit load to the SS and SP without an interrupt occurring between the two loads 2 The CPU allows interrupts between repeated string instructions If multiple prefixes precede a string instruction and the instruction is interrupted only the one prefix preceding the string primitive is restored 3 The CPU can be interrupted during a WAIT instruction The CPU will return to the WAIT instruction 2 45 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel 2 3 4 Interrupt Response Time Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction in the service routine is executed Interrupt response time is less for interrupts or exceptions which supply their own vector type The maskable interrupt has a longer response time because the vector type must be supplied by the Interrupt Control Unit see Chapter 8 Interrupt Control Unit Figure 2 27 shows the events that dictate interrupt response time for the interrupts that supply their type Note that an on chip bus master such as the DRAM Refresh Unit can make use of idle bus cycles This can increase interrupt response time Clocks Idle Read IP Idle Read CS Idle Push Flags Idle Push CS Push IP HH OF First Instruction Fetch From Interrupt Routine Total 42 A1030 0A Figure 2 27 Interrupt Response Fac
97. stack PUSHA Push registers onto stack POPA Pop registers off stack XCHG Exchange byte or word XLAT Translate byte Input Output IN Input byte or word OUT Output byte or word Address Object and Stack Frame LEA Load effective address LDS Load pointer using DS LES Load pointer using ES ENTER Build stack frame LEAVE Tear down stack frame Flag Transfer LAHF Load AH register from flags SAHF Store AH register in flags PUSHF Push flags from stack POPF Pop flags off stack Data transfer instructions are categorized as general purpose input output address object and flag transfer The stack manipulation instructions used for transferring flag contents and instruc tions used for loading segment registers are also included in this group Figure 2 11 shows the flag storage formats The address object instructions manipulate the addresses of variables in stead of the values of the variables intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 5 BU OD i TS zUuAUPuc POPF 15 14131211109 8 7654321 0 U Undefined Value is indeterminate O Overflow Flag D Direction Flag Interrupt Enable Flag T Trap Flag S Sign Flag Z Zero Flag A Auxiliary Carry Flag P Parity Flag C Carry Flag A1014 0A Figure 2 11 Flag Storage Format 2 2 1 2 Arithmetic Instructions The arithmetic instructions see Table 2 4 operate on four types of numbers Uns
98. struction used in the past to test the presence of a coprocessor fails without the 80C187 If an application offers the 80C187 as an option problems can be prevented in one of three ways Remove all numerics ESC instructions including code that checks for the presence of the 80C187 Use a jumper or switch setting to indicate the presence of the 80C187 The program can interrogate the jumper or switch setting and branch away from numerics instructions when the 80C187 socket is empty Trick the microprocessor into predictable operation when the 80C187 socket is empty The fix is placing pull up or pull down resistors on certain data and handshaking lines so the CPU reads a recognizable Opcode Status Word This solution requires a detailed knowledge of the interface 12 10 intel MATH COPROCESSING Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I O bus cycles with respect to the processor s control pins See System Design Tips for information on integrating the 80C187 into the overall system 12 4 3 System Design Tips All 80C187 operations require that bus ready be asserted The simplest way to return the ready indication is through hardware connected to the processor s external ready pin If you program a chip select to cover the math coprocessor port addresses its ready programming is in force and can provide bus ready for coprocessor accesses The user must verify that there are no conflicts fro
99. temp AX lt 0 7FH 1 TF registers AL and AH the single length then type 0 interrupt is generated ZF quotient is returned in AL and the SP lt SP f single length remainder is returned in SP 1 5 lt FLAGS AH For byte integer division the IF lt 0 maximum positive quotient is 127 TF 0 7FH and the minimum negative SP lt SP 2 quotient is 127 81H SP 1 SP lt CS 5 lt 2 If the source operand is word it is SP lt SP divided into the double length dividend SP 1 SP lt IP in registers AX and DX the single IP lt 0 length quotient is returned in AX and else the single length remainder is returned AL lt temp AX in DX For word integer division the lt temp AX maximum positive quotient is 32 767 7FFFH and the minimum negative When Source Operand is a Word quotient is 32 767 8001H temp lt word src If the quotient is positive and exceeds if the maximum or is negative and is temp DX AX gt 0 and less than the minimum the quotient temp DX AX gt 7FFFH or and remainder are undefined and a temp lt 0 and type 0 interrupt is generated In temp DX AX lt 0 7FFFH 1 particular this occurs if division by Ois then type 0 interrupt is generated attempted Nonintegral quotients are SP lt SP truncated toward 0 to integers and SP 1XSP lt FLAGS the remainder ha
100. the CPU instruction queue Program transfer instructions operate on the IP and CS registers Changing the contents of these registers causes normal sequential operation to be altered When a program transfer occurs the queue no longer contains the correct instruction The Bus Interface Unit obtains the next instruction from memory using the new IP and CS values It then passes the instruction directly to the Execution Unit and begins refilling the queue from the new location The 80C186 Modular Core family offers four groups of program transfer instructions see Table 2 9 These are unconditional transfers conditional transfers iteration control instructions and in terrupt related instructions 2 23 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Unconditional transfer instructions can transfer control either to a target instruction within the current code segment intrasegment transfer or to a different code segment intersegment trans fer The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans fer FAR The transfer is made unconditionally when the instruction is executed CALL RET and JMP are all unconditional transfers CALL is used to transfer the program to a procedure A CALL can be NEAR or FAR A NEAR CALL stacks only the Instruction Pointer while a FAR CALL stacks both the Instruction Pointer and the Code Segment register The RET instruction uses the information pushed onto the stack to determ
101. the final 90 phase shift Above and below resonance the crystal is reactive and forces the oscillator back toward the crystal s nominal frequency 20 Inverter Output Z NOTE At resonance the crystal is essentially resistive Above resonance the crystal is inductive Below resonance the crystal is capacitive A1125 0A Figure 5 2 Ideal Operation of Pierce Oscillator Figure 5 3 shows the actual microprocessor crystal connections For low frequencies crystal ven dors offer fundamental mode crystals At higher frequencies a third overtone crystal is the only choice The external capacitors Cy at CLKIN and Cx at OSCOUT together with stray capaci tance form the load A third overtone crystal requires an additional inductor L and capacitor C to select the third overtone frequency and reject the fundamental frequency See Selecting Crys tals on page 5 5 for a more detailed discussion of crystal vibration modes 5 2 intel CLOCK GENERATION AND POWER MANAGEMENT Choose C and L component values in the third overtone crystal circuit to satisfy the following conditions The LC components form an equivalent series resonant circuit at a frequency below the fundamental frequency This criterion makes the circuit inductive at the fundamental frequency The inductive circuit cannot make the 90 phase shift and oscillations do not take place The LC components form an equivalent parallel resonant circuit at a frequen
102. the shared Interrupt Request bit is also cleared If other timer interrupts are pending the Interrupt Request bit remains set When the timer interrupt is acknowledged the shared In Service bit is set No other timer inter rupts can occur when the In Service bit is set If a second timer interrupt occurs while another timer interrupt is being serviced the second interrupt remains pending until the interrupt handler for the first interrupt finishes and clears the In Service bit This is true even if the second interrupt has a higher priority than the first 8 2 3 Cascading with External 8259As For applications that require more external interrupt pins than the number provided on the Inter rupt Control Unit external 8259A modules can be used to increase the number of external inter rupt pins The cascade mode of the Interrupt Control Unit supports the external 8259As The INT2 INTAO INT3 INTAT pins can serve either of two functions Outside cascade mode they serve as external interrupt inputs In cascade mode they serve as interrupt acknowledge out puts INTAO is the acknowledge for INTO and INTAT is the acknowledge for INT1 See Figure 8 2 The INTZ INTAO and INT3 INTAT pins are inputs after reset until the pins are confiugred as out puts The pullup resistors ensure that the INTA pins never float which would cause a spurious interrupt acknowledge to the 8259A The value of the resistors must be high enough to prevent excessi
103. thousands of clocks 3 Completion of Current Bus Cycle A bus hold request cannot be serviced until the current bus cycle completes A bus hold request will not separate bus cycles required to move odd aligned word data Also bus cycles with long wait states will delay the servicing of a bus hold request 4 Interrupt Acknowledge Bus Cycle A bus hold request is not serviced until after an INTA bus cycle has completed An INTA bus cycle drives LOCK active 5 Refresh Bus Cycles A bus hold request is not serviced until after the refresh bus cycle has completed Refresh bus cycles have a higher priority than hold bus requests 3 7 1 2 Refresh Operation During a Bus HOLD Under normal operating conditions once HLDA has been asserted it remains asserted until HOLD is removed However when a refresh bus request is generated the HLDA output is re moved driven low to signal the need for the BIU to regain control of the local bus The BIU does not gain control of the bus until HOLD is removed This procedure prevents the BIU from just arbitrarily regaining control of the bus Figure 3 34 shows the timing associated with the occurrence of a refresh request while HLDA is active Note that HLDA can be as short as one clock in duration This happens when a refresh request occurs just after HLDA is granted A refresh request has higher priority than a bus hold request therefore when the two occur simultaneously the refresh request occurs
104. to reads writes and DRAM refresh cycles The external DRAM controller generates the Row Address Strobe RAS Column Ad dress Strobe CAS and other DRAM control signals Pseudo static RAMs use dynamic memory cells but generate address strobes and refresh address es internally The address counters still need external timing pulses These pulses are easy to de rive from the processor s bus control signals Pseudo static RAMs do not need a full DRAM controller 7 2 REFRESH CONTROL UNIT CAPABILITIES A 12 bit address counter forms the refresh addresses supporting any dynamic memory devices with up to 12 rows of memory cells 12 refresh address bits This includes all practical DRAM sizes for the processor s 1 Mbyte address space 7 3 REFRESH CONTROL UNIT OPERATION Figure 7 2 illustrates Refresh Control Unit counting address generation and BIU bus cycle gen eration in flowchart form The nine bit down counter loads from the Refresh Interval Register on the falling edge of CLK OUT Once loaded it decrements every falling CLKOUT edge until it reaches one Then the down counter reloads and starts counting again simultaneously triggering a refresh request Once enabled the DRAM refresh process continues indefinitely until the user reprograms the Re fresh Control Unit a reset occurs or the processor enters Powerdown mode The refresh request remains active until the bus becomes available When the bus is free the BIU will run its d
105. 0000 mod reg r m disp lo disp hi add reg8 mem8 reg8 01 0000 0001 mod reg r m disp lo disp hi add reg16 mem16 reg16 02 0000 0010 mod reg r m disp lo disp hi add reg8 reg8 mem8 03 0000 0011 mod reg r m disp lo disp hi add reg16 reg16 mem16 04 00000100 data 8 add AL immed8 05 0000 0101 data lo data hi add AX immed16 06 0000 0110 push ES 07 0000 0111 pop ES 08 0000 0100 mod reg r m disp lo disp hi or reg8 mem8 reg8 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued aa Byte 2 Bytes 3 6 ASM 86 Instruction Format Hex Binary 09 0000 1001 mod reg r m disp lo disp hi or reg16 mem16 reg16 0A 0000 1010 mod reg r m disp lo disp hi or reg8 reg8 mem8 0B 0000 1011 mod reg r m disp lo disp hi or reg16 reg16 mem16 0C 0000 1100 data 8 or AL immed8 oD 0000 1101 data lo data hi or AX immed16 0E 0000 1110 push cs OF 0000 1111 10 0001 0000 mod reg r m disp lo disp hi adc reg8 mem8 reg8 11 0001 0001 mod reg r m disp lo disp hi adc reg16 mem16 reg16 12 0001 0010 mod reg r m disp lo disp hi adc reg8 reg8 mem8 13 0001 0011 mod reg r m disp lo disp hi adc reg16 reg16 mem16 14 00010100 data 8 adc AL immed8 15 0001 0101 data lo data hi adc AX immed16 16 0001 0110 push SS 17 0001 0111 pop SS 18 0001 1000 mod reg r
106. 1 0000 mod reg r m disp lo disp hi xor reg8 mem8 reg8 31 0011 0001 mod reg r m disp lo disp hi xor reg16 mem16 reg16 32 0011 0010 mod reg r m disp lo disp hi xor reg8 reg8 mem8 33 0011 0011 mod reg r m disp lo disp hi xor reg16 reg16 mem16 34 0011 0100 data 8 xor AL immed8 35 0011 0101 data lo data hi xor AX immed16 36 0011 0110 SS segment override prefix 37 0011 0111 aaa 38 0011 1000 mod reg r m disp lo disp hi xor reg8 mem8 reg8 39 0011 1001 mod reg r m disp lo disp hi xor reg16 mem16 reg16 3A 0011 1010 mod reg r m disp lo disp hi xor reg8 reg8 mem8 3B 0011 1011 mod reg r m disp lo disp hi xor reg16 reg16 mem16 3C 0011 1100 data 8 xor AL immed8 3D 0011 1101 data lo data hi xor AX immed16 3E 0011 1110 DS segment override prefix 3F 0011 1111 aas 40 0100 0000 inc AX 41 0100 0001 inc Cx 42 0100 0010 inc DX 43 0100 0011 inc BX 44 0100 0100 inc SP 45 0100 0101 inc BP 46 0100 0110 inc SI 47 0100 0111 inc DI 48 0100 1000 dec AX 49 0100 1001 dec Cx 4A 0100 1010 dec DX 4B 0100 1011 dec BX 4C 0100 1100 dec SP 4D 0100 1101 dec BP 4E 0100 1110 dec SI 4F 0100 1111 dec DI 50 0101 0000 push AX 51 0101 0001 push Cx 52 0101 0010 push DX D 11 INSTRUCTION SET OPCODES AND CLOCK CYCLES In Table D 3 Machine Instruction Decoding Guide Continued tel
107. 1 Interrupts Master Slave Example Simplified Logic Diagram of a Bidirectional Port Pin Simplified Logic Diagram of an Input Port Pin Simplified Logic Diagram of an Output Port Pin Simplified Logic Diagram of an Open Drain Bidirectional Port Port Control Register PXCON Port Direction Register PxDIR Port Data Latch Register PXLTCH Port Pin State Register PxPIN 80C187 Supported Data Types 80C186 Modular Core Family 80C187 System Configuration 80C187 Configuration with a Partially Buffered Bus 80C187 Exception Trapping via Processor Interrupt Pin Entering Leaving ONCE Mode Formal Definition of ENTER Variable Access in Nested Procedures Stack Frame for Main at Level 1 Stack Frame for Procedure A at Level 2 Stack Frame for Procedure B at Level 3 Called from A Stack Frame for Procedure C at Level 3 Called from B Input Synchronization Circuit CONTENTS xiii SUENE intel TABLES Table Page 1 1 Comparison of 80C186 Modular Core Family 1 2 1 2 Related Documents and Software eecccccesceeeneeeeeceeeeeeeeeeeeeseeseeeeeeeseaeeeeeeeeaeeeeeeeeae 1 3 2 1 Implicit Use of General Registers sssseeeeeeenen nennen 2 5 2 2 5 5 2 13 2 3 Data Transfer Instructions ttn epe tiri Re aana ea REDE dn aes 2 18 2 4 Arithmetic Instr Ctlons cene cene cce
108. 1 r m disp lo disp hi data 8 cmp reg8 mem8 immed8 83 1000 0011 mod 000 r m disp lo disp hi data SX add reg16 mem16 immed8 mod 001 r m mod 010 r m disp lo disp hi data SX adc reg16 mem16 immed8 mod 011 r m disp lo disp hi data SX sbb reg16 mem16 immed8 mod 100 r m mod 101 r m disp lo disp hi data SX sub reg16 mem16 immed8 mod 110 r m mod 111 r m disp lo disp hi data SX cmp reg16 mem16 immed8 84 1000 0100 mod reg r m disp lo disp hi test reg8 mem8 reg8 85 1000 0101 mod reg r m disp lo disp hi test reg16 mem16 reg16 86 1000 0110 mod reg r m disp lo disp hi xchg reg8 reg8 mem8 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued sa Byte 2 Bytes 3 6 ASN 86 Instruction Format Hex Binary 87 1000 0111 mod reg r m disp lo disp hi xchg reg16 reg16 mem16 88 1000 0100 mod reg r m disp lo disp hi mov reg8 mem8 reg8 89 1000 1001 mod reg r m disp lo disp hi mov reg16 mem16 reg16 8A 1000 1010 mod reg r m disp lo disp hi mov reg8 reg8 mem8 8B 1000 1011 mod reg r m disp lo disp hi mov reg16 reg16 mem16 8 1000 1100 mod OSR disp lo disp hi mov reg16 mem16 SEGREG mod 1 r m 8D 1000 1101 mod reg r m disp lo disp hi lea reg16 mem16 8E 1000 1110 mod OSR r m disp lo disp
109. 12 11 Long integer defined 12 7 Long real defined 12 7 Math coprocessing 12 1 hardware support 12 1 overview 12 1 Memory addressing 2 28 2 36 operands 2 28 reserved locations 2 15 Memory devices interfacing with 3 6 3 7 Memory segments 2 8 accessing 2 5 2 10 2 11 2 13 address base value 2 10 2 11 2 12 Effective Address EA 2 13 intel logical 2 10 2 12 offset value 2 10 2 13 overriding 2 11 2 13 physical 2 3 2 10 2 12 and dynamic code relocation 2 13 Memory space 3 1 3 6 N Normally not ready signal See READY Normally ready signal See READY Numerics coprocessor fault Type 16 exception 2 44 12 13 ONCE mode 13 1 One shot code example 9 17 9 23 Ordinal defined 2 37 Oscillator external and powerdown 5 19 selecting crystal 5 5 using canned 5 6 internal crystal 5 1 5 10 controlling gating to internal clocks 5 18 operation 5 2 5 3 selecting C and L components 5 3 5 6 OUTS instruction A 2 Overflow Flag OF 2 7 2 9 2 44 P Packed BCD defined 2 37 Packed decimal defined 12 7 Parity Flag PF 2 7 2 9 PCB Relocation Register 4 1 4 3 4 6 and math coprocessing 12 1 PDTMR pin 5 18 Peripheral Control Block PCB 4 1 accessing 4 4 and F Bus operation 4 5 base address 4 6 4 7 bus cycles 4 4 READY signals 4 4 reserved locations 4 6 wait states 4 4 Peripheral control registers 4 1 4 6 INDEX Pointer defined 2 37 Poll regi
110. 12 5 MHz which makes it convenient to feed the clock input from the microprocessor s CLKOUT pin Beyond 12 5 MHz the 80C187 must use a multiply by two clock input up to a maximum of 32 MHz The microprocessor and the math coprocessor have correct timing relationships even with operation at different frequencies 12 4 2 Processor Bus Cycles Accessing the 80C187 Data transfers between the microprocessor and the 80C187 occur through the dedicated 16 bit I O ports shown in Table 12 7 When the processor encounters a numerics opcode it first writes the opcode to the 80C187 The 80C187 decodes the instruction and passes elementary instruction information Opcode Status Word back to the processor Since the 80C187 is a slave processor the Modular Core processor performs all loads and stores to memory Including the overhead in the microprocessor s microcode each data transfer between memory and the 80C187 via the mi croprocessor takes at least 17 processor clocks Table 12 7 80C187 I O Port Assignments V O Address Read Definition Write Definition 00F8H Status Control Opcode OOFAH Data Data OOFCH Reserved CS IP DS EA OOFEH Opcode Status Reserved The microprocessor cannot process any numerics ESC opcodes alone If the CPU encounters a numerics opcode when the Escape Trap ET bit in the Relocation Register is a zero and the 80C187 is not present its operation is indeterminate Even the FINIT FNINIT initialization in
111. 14 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 1 10 Stack Implementation Stacks in the 80C186 Modular Core family reside in memory space They are located by the Stack Segment register SS and the Stack Pointer SP A system can have multiple stacks but only one stack is directly addressable at a time A stack can be up to 64 Kbytes long the maximum length of a segment Growing a stack segment beyond 64 Kbytes overwrites the beginning of the segment The SS register contains the base address of the current stack The top of the stack not the base address is the origination point of the stack The SP register contains an offset that points to the Top of Stack TOS Stacks are 16 bits wide Instructions operating on a stack add and remove stack elements one word at a time An element is pushed onto the stack see Figure 2 10 by first decrementing the SP register by 2 and then writing the data word An element is popped off the stack by copying it from the top of the stack and then incrementing the SP register by 2 The stack grows down in memory toward its base address Stack operations never move or erase elements on the stack The top of the stack changes only as a result of updating the stack pointer 2 1 11 Reserved Memory and 1 0 Space Two specific areas in memory and one area in I O space are reserved in the 80C186 Core family Locations OH through 3FFH in low memory are used for the Interrupt Vector Table Programs sho
112. 15 for Mode 0 requires only two steps 1 Program M2 0 with the correct combination for Mode 0 2 Ifthe Clear to Send feature is desired set the CEN bit The serial port is now configured for Mode 0 To transmit write a character to SXTBUF The TI and TXE bits reflect the status of SXTBUF and the transmit shift register Note that the SBRK bit is independent of serial port mode functions in Mode 0 Receptions in Mode 0 are controlled by software To begin a reception set the REN bit in Sx CON The RI bit must be zero or the reception will not begin Data begins shifting in on RXD as soon as REN is set The asynchronous error flags OE FE and PE and break flags DBRKO and DBRK1 are invalid in Mode 0 10 3 HARDWARE CONSIDERATIONS FOR THE SERIAL PORT There are several interface considerations when using the serial port 10 3 1 CTS Pin Timings When the Clear to Send feature is enabled transmissions will not begin until the CTS pin is as serted while a transmission is pending Figure 10 15 shows the recognition of a valid CTS The CTS pin is sampled by the rising edge of CLKOUT The CLKOUT high time synchronizes the CTS signal On the falling edge of CLKOUT the synchronized CTS signal is presented to the serial port CTS is an asynchronous signal The setup and hold times are given only to ensure rec ognition at a specific clock edge When CTS is asynchronously it should be asserted for at least 1 clock cycles to guarantee that t
113. 188 80C186XL C188XL Microprocessor User s Manual 272164 80C186EA 80C188EA Microprocessor User s Manual 270950 80C186EB 80C188EB Microprocessor User s Manual 270830 80C186EC 80C188EC Microprocessor User s Manual 272047 8086 8088 8087 80186 80188 Programmer s Pocket Reference Guide 231017 INTRODUCTION intel Table 1 2 Related Documents and Software Continued Document Software Title Patera 8086 8088 User s Manual Programmer s and Hardware Reference Manual 240487 ApBUILDER Software 272216 80C186EA Hypertext Manual 272275 80C186EB Hypertext Manual 272296 80C186EC Hypertext Manual 272298 80C186XL Hypertext Manual 272630 ZCON Z80 Code Converter Available on BBS 1 3 CUSTOMER SERVICE This section provides telephone numbers and describes various customer services Customer Support U S and Canada 800 628 8686 Customer Training U S and Canada 800 234 8806 Literature Fulfillment 800 548 4725 U S and Canada 44 0 793 431155 Europe FaxBack Service 800 628 2283 U S and Canada 44 0 793 496646 Europe 916 356 3105 worldwide Application Bulletin Board System 916 356 3600 worldwide up to 14 4 Kbaud line 916 356 7209 worldwide dedicated 2400 baud line 44 0 793 496340 Europe Intel provides 24 hour automated technical support through the use of our FaxBack service and our centralized Intel Application Bulletin Board System BBS The Fax
114. 2 14 interrupts 2 45 overview 2 17 See also Addressing modes Instruction set Square wave generator code example 9 17 9 22 SS register 2 1 2 5 2 6 2 13 2 15 2 30 2 45 Stack frame pointers A 2 Stack Pointer 2 1 2 5 2 13 2 15 2 45 Stack segment 2 5 Stacks 2 15 START registers CSU 6 5 6 7 6 11 STOP registers CSU 6 5 6 8 6 12 String instructions 2 22 2 23 and addressing modes 2 34 and memory mapped I O ports 2 36 operand locations 2 13 operands 2 36 Strings accessing 2 13 2 34 defined 2 37 Synchronizing asynchronous inputs B 1 INDEX T Temporary real defined 12 7 Terminology above vs greater 2 26 below vs less 2 26 device names 1 2 Timer Control Registers TxCON 9 7 9 8 Timer Count Registers TXCNT 9 10 Timer Counter Unit TCU 9 1 9 23 application examples 9 17 9 23 block diagram 9 2 clock sources 9 12 configuring a digital one shot 9 17 9 23 configuring a real time clock 9 17 9 19 configuring a square wave generator 9 17 9 22 counting sequence 9 12 9 13 dual maxcount mode 9 13 9 14 enabling and disabling counters 9 15 9 16 frequency maximum 9 17 initializing 9 11 input synchronization 9 17 interrupts 9 16 overview 9 1 9 6 programming 9 6 9 16 considerations 9 16 pulsed output 9 14 9 15 retriggering 9 13 9 14 setup and hold times 9 16 single maxcount mode 9 13 9 14 9 16 timer delay 9 1 timing 9 1 and BIU 9 1 considerations
115. 3 21 Read Only Device Interface 3 22 Typical Write Bus Cycle tr rere ree rere doce re Dane ve veo e ten 3 23 16 Bit Bus Read Write Device 3 24 Interrupt Acknowledge Bus Cycle ssssssesseeeeenee nennen 3 26 Typical 82659A Intetface ag et eb ede etie e o eee cepe tt 3 27 HALT Bus Cycle vss ie 2 rh c PD ii ge IC E EU des 3 30 Returning to HALT After a HOLD HLDA Bus Exchange 3 31 Returning to HALT After a Refresh Bus Cycle sse 3 32 Exiting HALT Powerdown Mode ennnenm emere nnne 3 33 Exiting HALT Active ldle Mode seeeenm en 3 34 DEN and DT R Timing Relationships m n 3 35 Buffered 5 5 aa a i tenent 3 36 Qualifying DEN with Chip Selects ceccececeseeceeeeeeeeeeeeeeeeeeeseaeeeeeeseaeeeneeeseeseaeeeneeee 3 37 Timing Sequence Entering HOLD sesesssseseeeeeeeeeenee nennen 3 40 Refresh Request During HOLD sese nennen neni 3 42 Batching Fb DA uie mte Sm os ined Cielo mite iced dao 3 43 Exiting HOL DH 3 44 PCB Relocation REJISter strna eite pa et erg s 4 2 Glock Generator once eee P Re Ue eet a 5 1 Ideal Operation of Pierce OSCIIlAtOr eee eeeeeeeeeeeeeeneeeee
116. 4 Square Wave Generator 9 17 9 3 5 Digital One ShOL 2 2 oh nee a e eee aedi teile 9 17 CHAPTER 10 SERIAL COMMUNICATIONS UNIT 1051 INTRODUGTIQN siot etta ha cte een eater toes 10 1 10 1 1 Asynchronous Communications eseseeeeeeeeenenen nennen 10 1 10 1 1 1 RX BERI UR RANA 10 2 10 1 1 2 TX EI 10 4 10 1 1 3 Modes 3 and 4 iunii der oer AERE 10 6 10 1 1 4 MOdG 2 ieu nete debut edt aliit teat eius 10 7 10 1 2 Synchronous Communications ssssseeeeeeeee nennen 10 8 10 2 PROGRAMMING iiti p eR edere Een e Eo erac aee eoe e Puede Pn 10 9 10 21 Baud Rates ien e pater RR ERI CER 10 10 vii Sane intel 10 2 2 Asynchronous Mode Programming esee 10 13 10 2 2 1 Modes 1 and 4 for Stand alone Serial Communications 10 13 10 2 2 2 Modes 2 and for Multiprocessor Communications 10 14 10 2 2 3 Sending and Receiving a Break Character 10 14 10 23 A tenni 10 18 10 5 HARDWARE CONSIDERATIONS FOR THE SERIAL 10 18 10 3 1 CTS PinTimings s s iso Ema nE ERE 10 18 10 32 BGEK PBinsTimlifhgs 2 tite E REGNARE 10 18 10 3 9 Mode 0 TIMINGS
117. 4 8 2 FUNCTIONAL OPERATION ect ad ie Ads ere eee t reote 8 4 8 2 1 Typical Interrupt Sequence essssssseseseseee eene nennt enne nnne 8 5 8 2 2 Priority Resolution sus i t rte ert es ine Aces eec bes 8 5 8 2 2 1 Priority Resolution Example senem 8 6 8 2 2 2 Interrupts That Share a Single Source esse 8 7 8 2 8 Cascading with External 8259As sss nnns 8 7 8 2 8 1 Special Fully Nested Mode esesessseeeeeeeenenenneeeneen nennen 8 8 8 2 4 Interrupt Acknowledge Sequence sese 8 9 9 2 5 Pollirig eet met tente adden ie hti ntis 8 9 vi intel dine 8 2 6 Edge and Level Triggering 8 10 8 2 7 Additional Latency and Response Time eee 8 10 8 3 PROGRAMMING THE INTERRUPT CONTROL UNIT eene 8 11 8 3 1 Interrupt Control Registers 8 12 8 3 2 Interrupt Request Register ceccscccessceeeeeeseeeeeneeneneceesesnseessenenesseeeeseeeeeeseneeesaces 8 16 8 3 3 Interrupt Mask Register 8 17 8 3 4 Priority Mask Register rne nnne 8 18 8 3 5 1 Registers icai p rete tte Rege nds nee 8 18 8 3 6 Poll and Poll Status Registers ssssseseenenene
118. 7 Warm Reset Waveform At the second falling CLKOUT edge after the internal clocks resynchronize the processor deas serts RESOUT Bus activity starts seven CLKOUT periods after recognition of RESIN in the log ic high state If an alternate bus master asserts HOLD during reset the processor immediately asserts HLDA and will not prefetch instructions 5 9 CLOCK GENERATION AND POWER MANAGEMENT intel CLKIN RESIN RESYNC Internal CLKOUT RESOUT NOTES 1 Setup of RESIN to falling CLKIN RESOUT goes active RESIN allowed to go inactive after minimum 4 CLKOUT cycles RESYNC pulse generated RESYNC pulse drives CLKOUT low resynchronizing the clock generator RESOUT goes inactive on the second falling CLKOUT edge following CLKOUT resynchronization A1117 0A Figure 5 8 Clock Synchronization at Reset 5 2 POWER MANAGEMENT Many VLSI devices available today use dynamic circuitry A dynamic circuit uses a capacitor usually parasitic gate or diffusion capacitance to store information The stored charge decays over time due to leakage currents in the silicon If the device does not use the stored information before it decays the state of the entire device may be lost Circuits must periodically refresh dy namic RAMs for example to ensure data retention Any microprocessor that has a minimum clock frequency has dynamic logic On a dynamic microprocessor if you stop or slow the clock the dynamic nodes within it
119. 7 0A Figure 3 6 Typical Bus Cycle TN Falling Rising CLKOUT Edge Edge 1 1 1 Phase 1 Phase 2 1 1 1 Low Phase High Phase A1111 0A Figure 3 7 T State Relation to CLKOUT Figure 3 8 shows the BIU state diagram Typically a bus cycle consists of four consecutive T states labeled T1 T2 T3 and T4 A TI idle state occurs when no bus cycle is pending Multiple T3 states occur to generate wait states The TW symbol represents a wait state The operation of a bus cycle can be separated into two phases Address Status Phase Data Phase 3 8 intel BUS INTERFACE UNIT The address status phase starts just before T1 and continues through T1 The data phase starts at T2 and continues through T4 Figure 3 9 illustrates the T state relationship of the two phases Bus Ready Request Pending HOLD Deasserted Halt Bus Cycle Bus Not Ready Bus Ready No Request Pending HOLD Deasserted Request Pending HOLD Deasserted RESIN Asserted HOLD Asserted 1538 01 Figure 3 8 BIU State Diagram 3 9 BUS INTERFACE UNIT intel T4 or TW CLKOUT Address Status Phase Bala hase A1113 0A Figure 3 9 T State and Bus Phases 3 4 1 Address Status Phase Figure 3 10 shows signal timing relationships for the address status phase of a bus cycle A bus cycle begins with the transition of ALE and 52 0 These signals transition during phase 2 of the T
120. 7C256 Note Ag and BHE are not used A1105 0A Figure 3 20 Read Only Device Interface 3 5 2 Write Bus Cycles Figure 3 21 illustrates a typical write bus cycle The bus cycle starts with the transition of ALE high and the generation of valid status bits S2 0 The bus cycle ends when WR transitions high inactive although data remains valid for one additional clock Table 3 4 lists the two types of write bus cycles 3 22 intel BUS INTERFACE UNIT CLKOUT so DV ALE NH xu ANS x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address Valid X A18 16 0 A19 Valid Status 1 1 A19 16 LN 15 8 AD15 0 AD7 0 WR A1085 0A Figure 3 21 Typical Write Bus Cycle Table 3 4 Write Bus Cycle Types Status Bits Bus Cycle Type 2 1 so 0 1 0 Write I O Initiated by executing IN OUT INS OUTS instructions A15 0 select the desired I O port A19 16 are driven to zero see Chapter 10 Direct Memory Access Unit 1 1 0 Write Memory Initiated by any of the Byte Word memory instructions A19 0 selects the desired byte or word memory location Figure 3 22 illustrates a typical 16 bit interface connection to a read write device Write bus cy cles have many parameters that must be evaluated in determining the compatibility of a memory or I O device Table 3 5 lists some critical write bus cycle parameters 3 23 BUS INTERFACE UNIT i
121. 8 7 10 8 1 8 3 8 4 8 5 8 6 8 8 8 9 8 10 8 11 8 12 8 13 8 14 9 1 9 3 9 4 9 6 9 7 9 9 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 xii FIGURES Page Using Chip Selects During HOLD 6 15 Typical Systems 6 16 Guarded Memory Detector sess eene nennen nens 6 20 Refresh Control Unit Block Diagranm ecceecceeceeeeeeeeeeeeeeeeeeeseeeeeeeseaeeseeeenaeeseeeeeeetias 7 1 Refresh Control Unit Operation Flow 7 3 Refresh Address Formattion ccscccessseeceeneeeeeneeeesneeesenneeeesaeeeseaeeseneeseseeeeeeeaeeersaeees 7 4 Suggested DRAM Control Signal Timing 7 6 Formula for Calculating Refresh Interval for RFTIME 7 7 Refresh Base Address Register sssssseeee ene 7 8 Refresh Clock Interval Register sssssseseeeneeeneneeeenen nennen 7 9 Refresh Control 7 10 Refresh Address Register crm inten ere precede ctore Tee 7 11 Regaining Bus Control to Run a DRAM Refresh Bus 7 14 Interrupt Control Unit Block Diagram eseeeeeeeneenenneeeneen nennen 8 2 Usi
122. 8 mov DL immed8 B3 1011 0011 data 8 mov BL immed8 B4 1011 0100 data 8 mov AH immed8 B5 1011 0101 data 8 mov CH immed8 B6 1011 0110 data 8 mov DH immed8 B7 1011 0111 data 8 mov BH immed8 B8 10 000 data lo data hi mov AX immed16 B9 10 001 data lo data hi mov CX immed16 BA 10 010 data lo data hi mov DX immed16 BB 10 011 data lo data hi mov BX immed16 BC 10 100 data lo data hi mov SP immed16 BD 10 101 data lo data hi mov BP immed16 BE 10 110 data lo data hi mov Sl immed16 BF 10 111 data lo data hi mov Dl immed16 co 1100 0000 mod 000 r m data 8 rol reg8 mem8 immed8 mod 001 r m data 8 ror reg8 mem8 immed8 mod 010 r m data 8 rcl reg8 mem8 immed8 mod 011 r m data 8 rer reg8 mem8 immed8 mod 100 r m data 8 shl sal reg8 mem8 immed8 mod 101 r m data 8 shr reg8 mem8 immed8 mod 110 r m mod 111 r m data 8 sar reg8 mem8 immed8 C1 1100 0001 mod 000 r m data 8 rol reg16 mem16 immed8 mod 001 r m data 8 ror reg16 mem16 immed8 mod 010 r m data 8 rcl reg16 mem16 immed8 mod 011 r m data 8 rer reg16 mem16 immed8 mod 100 r m data 8 shl sal reg16 mem16 immed8 mod 101 r m data 8 shr reg16 mem16 immed8 mod 110 r m INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued Byte 2 Bytes 3 6 ASN 86 Instruction Format Hex Binary mod
123. 87 name example 80C187 proc DESCRIPTION VARIABLES RESULTS NOTES convert convert code 12 16 i t T B T T H T assume cS data mov mov fld fld 5 r t x y e 5 P a d fsincos fmul fstp fmul fstp endp ends end S his code section uses the 80C187 FSINCOS transcendental instruction to convert the locus of a point from polar o Cartesian coordinates he variables consist of the radius r and the angle theta oth are expressed as 32 bit reals and 0 lt theta lt pi 4 he results of the computation are the coordinates x and y xpressed as 32 bit reals his routine is coded for Intel ASM86 It is not set up as an LL callable routine his code assumes that the 80C187 has already been initialized code ds data egment at 0100h dd X XXXX substitute real operand dd heta dd x xxxx substitute real operand dd nds egment at 0080h roc far x data S ax load radius heta load angle st cos st 1 sin kte S62 compute x Store to memory and pop compute y Store to memory and pop Example 12 2 Floating Point Math Routine Using FSINCOS intel 13 ONCE Mode intel CHAPTER 13 ONCE MODE ONCE pronounced Mode provides the ability to three state all output bidirectional or weakly held high low pins except OSCOUT To allow device
124. Additional Vo and Voy drive is required A memory or I O device cannot float its outputs in time to prevent bus contention even at reset T1 T2 T3 T4 T1 CLKOUT fs sl M Write Cycle Operation Read Cycle Operation A1094 A0 Figure 3 30 DEN and DT R Timing Relationships The circuit shown in Figure 3 31 illustrates how to use transceivers to buffer the address data bus The connection between the processor and the transceiver is known as the ocal bus A connection between the transceiver and other memory or I O devices is known as the buffered bus A fully buffered system has no devices attached to the local bus A partially buffered system has devices on both the local and buffered buses 3 35 BUS INTERFACE UNIT intel Processor Latch Address Bus Address Memory Transceiver Data or CS I O Device CPU Local Bus Buffered Bus A1095 0A Figure 3 31 Buffered AD Bus System In a fully buffered system DEN directly drives the transceiver output enable A partially buffered system requires that DEN be qualified with another signal to prevent the transceiver from going active for local bus accesses Figure 3 32 illustrates how to use chip selects to qualify DEN DT R always connects directly to the transceiver However an inverter may be required if the po larity of DT R does not match the transceiver DT R goes low 0 only for memory
125. B Writing an odd aligned word will give unexpected results For the 80C186 Modular Core use either OUT DX AX or OUT DX AL or MOV even PCB address word register For the 80C188 Modular Core using OUT DX AX will perform an unnecessary bus cycle and is not recommended Use either OUT DX AL or MOV even aligned byte PCB address byte register low byte Byte writes Always use even aligned byte writes to the PCB Even aligned byte writes will modify the entire word PCB location Do not perform unaligned byte writes to the PCB 4 5 PERIPHERAL CONTROL BLOCK intel 4 4 3 1 Writing the PCB Relocation Register Whenever mapping the Peripheral Control Block to another location the user should program the Relocation Register with a byte write 1 OUT DX AL Internally the Relocation Register is written with 16 bits of the AX register while externally the Bus Interface Unit runs a single 8 bit bus cycle If a word instruction i e OUT DX AX is used with an 80C188 Modular Core family member the Relocation Register is written on the first bus cycle The Bus Interface Unit then runs an unnecessary second bus cycle The address of the second bus cycle is no longer within the con trol block since the Peripheral Control Block was moved on the first cycle External READY must now be generated to complete the cycle For this reason we recommend byte operations for the Relocation Register 4 4 3 2 Accessing the
126. BCLK input signal has high and low times that are both at least 1 2 CLKOUT periods than synchronization to CLKOUT is not necessary How ever when the BCLK signal has a high or a low time of less than 1 2 CLKOUT periods meeting the setup and hold times to CLKOUT is necessary to avoid missing BCLK transitions The max imum input frequency to BCLK is one half the frequency of CLKOUT CPU operating frequen cy 10 3 3 Mode 0 Timings This section shows the timings of the TXD and RXD pins in Mode 0 In Mode 0 TXD never floats When not transmitting or receiving TXD is high RXD floats except when transmitting a character 10 3 3 1 CLKOUT as Baud Timebase Clock The behavior of the transmit receive clock on TXD is governed by the value of BxCMP When the BxCMP value is greater than or equal to two The TXD pin is low for two CLKOUT periods and is high for BxCMP 1 CLKOUT periods see Figure 10 17 cannot be equal to a one otherwise the serial port buffer registers SxRBUF will not receive the correct data Low For High For TXD 2 Clocks N 1 Clocks RXD BITO BIT 1 Figure 10 17 Mode 0 gt 2 A1282 A For transmissions the RXD pin changes on the next CLKOUT falling edge following a low to high transition on TXD Therefore the data on the RXD pin is guaranteed to be valid on the rising edges of TXD Use the rising edge of TXD to latch the value on RXD For receptions the incom ing serial data mu
127. Back service is a simple to use information system that lets you order technical documents by phone for immediate deliv ery to your fax machine The BBS is a centralized computer bulletin board system that provides updated application specific information about Intel products intel INTRODUCTION 1 3 1 How to Use Intel s FaxBack Service Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number see page 1 4 and respond to the system prompts After you select a document the system sends a copy to your fax machine Each document is assigned an order number and is listed in a subject catalog First time users should order the appropriate subject catalogs to get a complete listing of document order num bers The following catalogs and information packets are available 1 Microcontroller Flash and iPLD catalog Development tool catalog System catalog DVI and multimedia catalog BBS catalog Microprocessor and peripheral catalog Quality and reliability catalog 905 ER O ah Technical questionnaire 1 3 2 How to Use Intel s Application BBS The Application Bulletin Board System BBS provides centralized access to information soft ware drivers firmware upgrades and revised software Any user with a modem and computer can access the BBS Use the following modem settings e 14400 N 8 1 If your modem does not support 14 4K baud the system provides au
128. C C CC CC CC CC Cx x x x Kk x x KK B1CMP equ XXXXxH Channel Baud Rate Compare S1CON equ XXXXH Channel Control S1STS equ XXXXH Channel Status SITBUF equ XXXXH Channel Receive Buffer XXXX Substitute register offset Example assumes that all the port pins are configured correctly and PCB is located in I O space lib 80186 segment public code assume cs lib 80186 public parallel serial parallel serialproc far push bp Save caller s bp mov bp sp get current top of stack user data equ word ptr bp 6 get parameters off the stack tran freq equ word ptr bpt8 push ax save registers that push dx will be modifiled mov dx clear any pending exceptions Example 10 2 Mode 0 Example 10 26 intel SERIAL COMMUNICATIONS UNIT mov dx P1CON Get state of port 1 controls in ax dx and ax Ofeh make sure P1 0 is port out dx al mov mov ax tran freq or ax 8000h set internal clocking bit out dx ax Mode 0 1 million bps mov dx P2CON Jet Port 2 1 for TXD mov ax Offh out dx al mov dx SI1TBUF send user s data mov ax user_data out dx al mov dx S1CON Mode 0 No CTS Transmit ax out dx ax mov dx S1STS Check_4_TI in ax dx test ax 0020h check for TI bit JZ Check_4_TI mov P1LTCH pulse P1 0 ax out dx al not ax set P1 0 high out dx al not ax set P1 0 low out dx
129. CUCON SCU interrupt control in ax dx and ax 0007h clear mask bit to enable out dx ax Turn on the receiver mov dx S0CON in ax dx read SOCON or ax 0020 set REN bit REN 1 receiver enabled out dx ax write SOCON ret ASYNC CHANNEL SETUP endp Now the receiver is enabled and sampling of the RXD line begins Any write to SOTBUF will initiate a transmission Ihe next procedure is executed every time a reception is completed ASYNC REC INT PROC proc near mov dx SOSTS in ax dx get status info test al 10000000b test for parity error jnz parity error test al 00010000b test for framing error jnz framing error test al 00000100b test for overrun error jnz overrun error At this point we know the received data is OK Example 10 1 Asynchronous Mode 4 Example Continued 10 24 intel SERIAL COMMUNICATIONS UNIT mov dx SORBUF in ax dx read received data and ax O7fh strip off parity bit Code to store the data in a receive buffer would go here It has been omitted Since this is heavily application dependent jmp eoi rcv int parity error Code for parity error handling goes here jmp eoi rcv int framing error Code for framing error handling goes here jmp eoi rcv int overrun error Code for overrun error handling goes here jmp eoi rcv int Now we must issue the end of interrupt command to the interrupt unit eoi rcv int mov EOI mov ax 8000h issue non specific EOI out dx ax
130. Dir ction Register ieii nene e tegens 11 8 11 2 8 Port Data Latch Register 11 9 11 2 4 Port Pin State Register enne nennen nnne 11 10 11 2 5 Initializing the VO Ports 11 11 11 3 PROGRAMMING EXAMPLE eeseeeeeneeeeneennneen nennen nnne neret teneris 11 12 CHAPTER 12 MATH COPROCESSING 12 1 OVERVIEW OF MATH 5 12 1 12 2 AVAILABILITY OF MATH COPROCESSING seems 12 1 12 8 THE 80C187 MATH 12 2 12 3 1 80C187 Instruction Set He ede c a esee oe 12 2 12 3 1 1 Data Transfer Instructions 12 3 viii intel CONTENTS 12 3 1 2 Arithmetic Instr ctions 5 centes 12 3 12 3 1 3 Comparison Instructions essessseeeeeeeeeeeenene nennen nennen 12 5 12 3 1 4 Transcendental Instructions sess 12 5 12 3 1 5 Constant Instructions 12 6 12 3 1 6 Processor Control Instructions 12 6 12 3 2 80C187 Data Types iecit tette ioter i e des 12 7 12 4 MICROPROCESSOR AND COPROCESSOR
131. FSAVE FNSAVE Save state FENI FNENI Enable interrupts FRSTOR Restore state FLDCW Load control word FINCSTP Increment stack pointer FSTCW FNSTCW Store control word FDECSTP Decrement stack pointer FSTSW FNSTSW Store status word FFREE Free register FCLEX FNCLEX Clear exceptions FNOP No operation FSTENV FNSTENV Store environment FWAIT CPU wait intel MATH COPROCESSING 12 3 2 80C187 Data Types The microprocessor math coprocessor combination supports seven data types Word Integer A signed 16 bit numeric value All operations assume a 2 s complement representation Short Integer A signed 32 bit numeric value double word All operations assume a 2 s complement representation Long Integer A signed 64 bit numeric value quad word All operations assume a 2 s complement representation Packed Decimal A signed numeric value contained in an 80 bit BCD format Short Real A signed 32 bit floating point numeric value Long Real A signed 64 bit floating point numeric value Temporary Real A signed 80 bit floating point numeric value Temporary real is the native 80C187 format Figure 12 1 graphically represents these data types 12 4 MICROPROCESSOR AND COPROCESSOR OPERATION The 80C187 interfaces directly to the microprocessor as shown in Figure 12 2 and operates as an I O mapped slave peripheral device Hardware handshaking requires connections between the 80C187 and four special pi
132. Flag Causes string instructions to auto decrement the appropriate index register when set Clearing DF causes auto increment OF Interrupt enable Flag When set maskable interrupts will cause the CPU to transfer control to an interrupt vector specified location Overflow Flag Set if the signed result cannot be expressed within the number of bits in the destination operand cleared otherwise PF Parity Flag Set if low order 8 bits of result contain an even number of 1 bits cleared otherwise SF Sign Flag Set equal to high order bit of result 0 if positive 1 if negative TF ZF Single Step Flag Once set a single step interrupt occurs after the next instruction executes TF is cleared by the single step interrupt Zero Flag Set if result is zero cleared otherwise INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set intel ote Flags Name Description Operation Affected AAA ASCII Adjust for Addition if AF Y AL and OFH gt 9 or AF 1 CF v AAA then DF Changes the contents of register AL to AL lt AL 6 IF a valid unpacked decimal number the AH lt AH 1 OF high order half byte is zeroed AF lt 1 PF 2 Instruction Operands CF AF SF none AL lt AL and OFH TF ZF AAD ASCII Adjust for Division AL lt AH x OAH AL AF AAD AH 0 Modifies the numerator in AL b
133. IPHERAL CONTROL BLOCK 4 4 8 F Bus Operation The F Bus functions differently than the external data bus for byte and word accesses All write transfers on the F Bus occur as words regardless of how they are encoded For example the in struction OUT DX AL DX is even will write the entire AX register to the Peripheral Control Block register at location DX If DX were an odd location AL would be placed in DX and AH would be placed at DX 1 A word operation to an odd address would write DX and DX 1 with AL and AH respectively This differs from normal external bus operation where un aligned word writes modify DX and DX 1 In summary do not use odd aligned byte or word writes to the PCB Aligned word reads work normally Unaligned word reads work differently For example IN AX DX DX is odd will transfer DX into AL and DX 1 into AH Byte reads from even or odd addresses work normally but only a byte will be read For example IN AL DX will not transfer DX into AX only AL is modified No problems will arise if the following recommendations are adhered to Word reads Aligned word reads of the PCB work normally Access only even aligned words with IN AX DX or MOV word register even PCB address Byte reads Byte reads of the PCB work normally Beware of reading word wide PCB registers that may change value between successive reads e g timer count value Word writes Always write even aligned words to the PC
134. LC STC CLI STI CLS STD Grp2 Grp2 Fx b r m w r m NOTE Table D 5 defines abbreviations used in this matrix Shading indicates reserved opcodes D 21 INSTRUCTION SET OPCODES AND CLOCK CYCLES intel Table D 5 Abbreviations for Mnemonic Encoding Matrix Abbr Definition Abbr Definition Abbr Definition Abbr Definition b byte operation ia immediate to accumulator m memory t to CPU register d direct id indirect r m EA is second byte v variable f from CPU register is immediate byte sign extended si short intrasegment w word operation i immediate 1 long intersegment sr segment register z zero Byte 2 Immed Shift Grp1 Grp2 mod 000 r m ADD ROL TEST INC mod 001 r m OR ROR DEC mod 010 r m ADC RCL NOT CALL id mod 011 r m SBB RCR NEG CALL I id mod 100 r m AND SHL SAL MUL JMP id mod 101 r m SUB SHR IMUL JMP i id mod 110 r m XOR DIV PUSH mod 111 r m CMP SAR IDIV mod and r m determine the Effective Address EA calculation See Table D 1 for definitions D 22 intel Index intel 80C187 Math Coprocessor 12 2 12 8 accessing 12 10 12 11 arithmetic instructions 12 3 12 4 bus cycles 12 11 clocking 12 10 code examples 12 13 12 16 comparison instructions 12 5 constant instructions 12 6 data transfer instructions 12 3 data types 12 7 12 8 design considerations 12 10 12 11 example floating point routin
135. LITIES eene 7 2 7 3 REFRESH CONTROL UNIT 7 2 7 4 REFRESH ADDRESSES 2 intet t hmi tie eie bere bd ome 7 4 7 5 REFRESH BUS GYGEES tote PERI RE MM eme e PER 7 5 7 6 GUIDELINES FOR DESIGNING DRAM CONTROLLERS eee 7 5 7 7 PROGRAMMING THE REFRESH CONTROL UNIT eene 7 7 7 7 1 Calculating the Refresh Interval sese 7 7 7 7 2 Refresh Control Unit Registers eessesseeeeeeneeeeenennennenen nennen 7 7 7 7 2 1 Refresh Base Address Register sssssemem 7 7 7 7 2 2 Refresh Clock Interval Register c cesceeseeceeeeeeeeeeeeeseeeeeaeeenaeeeeeeseaeeseaeenaees 7 8 7 7 2 3 Refresh Control Register 7 9 7 7 2 4 Refresh Address Register 7 10 7 7 8 Programming Example penne 7 11 7 8 REFRESH OPERATION AND BUS 7 13 CHAPTER 8 INTERRUPT CONTROL UNIT 8 1 FUNCTIONAL OVERVIEW deste cecidere e deed 8 1 8 1 1 Generic FUNCIONS on nnt ace aerei dte diee Grade 8 2 8 1 1 1 Interrupt Masking e pte ceret te deb EE Rh Le cec 8 2 8 1 1 2 Interrupt Priority siu ipie ER Cor ne Re tr RE E ete thie re qe ib EG 8 3 8 1 1 3 Interrupt Nesting i rere er ee eka ree EO e ERE 8
136. LOCK All communication between integrated peripherals and the Modular CPU Core occurs over a spe cial bus called the F Bus which always carries 16 bit data The Peripheral Control Block like all integrated peripherals is always accessed 16 bits at a time 4 4 4 Bus Cycles The processor runs an external bus cycle for any memory or I O cycle accessing a location within the Peripheral Control Block Address data and control information is driven on the external pins as with an ordinary bus cycle Information returned by an external device is ignored even if the access does not correspond to the location of an integrated peripheral control register This is also true for the 80C188 Modular Core family except that word accesses made to integrated registers are performed in two bus cycles 4 4 2 READY Signals and Wait States The processor generates an internal READY signal whenever an integrated peripheral is access ed External READY is ignored READY is also generated if an access is made to a location with in the Peripheral Control Block that does not correspond to an integrated peripheral control register For accesses to timer control and counting registers the processor inserts one wait state This is required to properly multiplex processor and counter element accesses to the timer control registers For accesses to the remaining locations in the Peripheral Control Block the processor does not insert wait states 4 4 intel PER
137. Mode Figure 9 4 Timer Counter Unit Output Modes A1296 0A 9 2 PROGRAMMING THE TIMER COUNTER UNIT Each timer has three registers a Timer Control register Figure 9 5 and Figure 9 6 a Timer Count register Figure 9 7 and a Timer Maxcount Compare register Figure 9 8 Timers 0 and 1 also have access to an additional Maxcount Compare register The Timer Control register con trols timer operation The Timer Count register holds the current timer count value and the Max count Compare register holds the maximum timer count value 9 6 intel TIMER COUNTER UNIT Register Name Timer 0 and 1 Control Registers Register Mnemonic TOCON T1CON Register Function Defines Timer 0 and 1 operation A1297 0A Bit i Function Mnemonic Bit Name unctio EN Enable Set to enable the timer This bit can be written only when the INH bit is set Inhibit Set to enable writes to the EN bit Clear to ignore writes to the EN bit The TNH bit is not stored it always reads as zero Interrupt Set to generate an interrupt request when the Count register equals a Maximum Count register Clear to disable interrupt requests Register In Indicates which compare register is in use When set Use the current compare register is Maxcount Compare B when clear it is Maxcount Compare A Maximum This bit is set when the counter reaches a maximum Count count The MC bit must be cleared by writing to the Timer Control register
138. NS Conditional Transfers jump if JE JZ equal zero 01110100 disp 4 13 2 JL JNGE less not greater or equal 01111100 disp 4 13 2 JLE JNG less or equal not greater 01111110 disp 4 13 2 JB JNAE below not above or equal 01110010 disp 4 13 2 JC carry 01110010 disp 4 13 2 JBE JNA below or equal not above 01110110 disp 4 13 2 JP JPE parity parity even 01111010 disp 413 2 overflow 01110000 disp 413 2 JS sign 01111000 disp 4 13 2 JNE JNZ not equal not zero 01110101 disp 413 2 JNL JGE less greater equal 01111101 413 2 JNLE JG less or equal greater 0111111 disp 4A3 2 JNB JAE not below above or equal 0111001 disp 4 13 2 JNC not carry 01110011 disp 4 13 2 JNBE JA not below or equal above 0111011 disp 4 13 2 JNP JPO not parity parity odd 01111011 disp 4A3 2 JNO not overflow 01110001 disp 4 13 2 JNS not sign 0111100 disp 5 15 2 Unconditional Transfers CALL Call procedure direct within segment 11101000 disp low disp high 15 reg memory indirect within segment 11111111 mod 010 r m 13 19 indirect intersegment 11111111 mod 011 r m mod 11 38 direct intersegment 10011010 segment offset 23 selector NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the
139. OF Transfers control to the target location PF if the condition tested SF OF and SF ZF 0 is true TF Instruction Operands ZF JG short label JNLE short label JGE Jump on Greater Than or Equal if AF JNL Jump on Not Less Than SF OF JGE disp8 Wien PTS Non UNL disp8 lt IP disp8 sign ext to 16 bits IF OF Transfers control to the target location PF if the condition tested SF OF is true SF Instruction Operands TF JGE short label zF JNL short label NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 22 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued MEN Flags Name Description Operation Affected JL Jump on Less Than if AF JNGE Jump on Not Greater Than or Equal SF OF JL disp8 then c adn JNGE disp8 IP lt IP disp8 sign ext to 16 bits IF OF Transfers control to the target location PF if the condition tested SF OF is true SF Instruction Operands TF JL short label ZF JNGE short label JLE Jump on Less Than or Equal if AF JNG Jump on Not Greater Than SF OF or ZF 1 JGE disp8 er
140. OF Y the number of bits specified in the if PF count operand Bits equal to the count 3 SF v original high order sign bit are shifted then TF in on the left preserving the sign of the if ZF original value Note that SAR does not high order bit of dest produce th same result next to high order bit of dest dividend of an equivalent IDIV then instruction if the destination operand is OF 1 negative and 1 bits are shifted out For else example shifting 5 right by one bit OF 0 yields 3 while integer division 5 by 2 else yields 2 The difference in the instruc OF 0 tions is that IDIV truncates all numbers toward zero while SAR truncates positive numbers toward zero and negative numbers toward negative infinity Instruction Operands SAR reg n SAR mem n SAR reg CL SAR mem CL NOTE The three symbols used in the Flags Affected column are defined as follows C 40 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel Table C 4 Instruction Set Continued INSTRUCTION SET DESCRIPTIONS E A Flags Name Description Operation Affected SBB Subtract With Borrow if AF Y SBB dest src CF 1 CF Y Sub h f he dest then DF ubtracts t e source from tl e desti dest dest src 1 IF na
141. ON 58H P2DIR 98H GCS6ST D8H Reserved 1AH I1 CON 5AH P2PIN 9AH GCS6SP DAH Reserved 1CH I2CON 5CH P2CON 9CH GCS7ST DCH Reserved 1EH I3CON 5EH P2LTCH 9EH GCS7SP DEH Reserved 20H Reserved 60H BOCMP LCSST EOH Reserved 22H Reserved 62H BOCNT A2H LCSSP E2H Reserved 24H Reserved 64H SOCON A4H UCSST E4H Reserved 26H Reserved 66H SOSTS A6H UCSSP E6H Reserved 28H Reserved 68H SORBUF A8H RELREG E8H Reserved 2AH Reserved 6AH SOTBUF AAH Reserved EAH Reserved 2CH Reserved 6CH Reserved ACH Reserved ECH Reserved 2EH Reserved 6EH Reserved AEH Reserved EEH Reserved 30H TOCNT 70H B1CMP BOH RFBASE FOH Reserved 32H TOCMPA 72H B1CNT B2H RFTIME F2H Reserved 34H TOCMPB 74H S1CON B4H RFCON F4H Reserved 36H TOCON 76H S1STS B6H RFADDR F6H Reserved 38H TICNT 78H S1RBUF B8H PWRCON F8H Reserved 3AH T1CMPA 7AH S1TBUF BAH Reserved FAH Reserved 3CH T1CMPB 7CH Reserved BCH STEPID FCH Reserved 3EH T1CON 7EH Reserved BEH Reserved FEH Reserved PERIPHERAL CONTROL BLOCK intel 4 3 RESERVED LOCATIONS Many locations within the Peripheral Control Block are not assigned to any peripheral Unused locations are reserved Reading from these locations yields an undefined result If reserved reg isters are written for example during a block MOV instruction they must be set to OH NOTE Failure to follow this guideline could result in incompatibilities with future 80C186 Modular Core family products 4 4 ACCESSING THE PERIPHERAL CONTROL B
142. P SP first operand Figure A 1 Formal Definition of ENTER ENTER treats a reentrant procedure as a procedure calling another procedure at the same lexical level A reentrant procedure can address only its own variables and variables of higher level call ing procedures ENTER ensures this by copying only stack frame pointers from higher level pro cedures Block structured high level languages use lexical nesting levels to control access to variables of previously nested procedures For example assume for Figure A 2 that Procedure A calls Proce dure B which calls Procedure C which calls Procedure D Procedure C will have access to the variables of Main and Procedure A but not to those of Procedure B because Procedures C and B operate at the same lexical nesting level The following is a summary of the variable access for Figure A 2 1 Main has variables at fixed locations 2 Procedure A can access only the fixed variables of Main 3 Procedure B can access only the variables of Procedure A and Main Procedure B cannot access the variables of Procedure C or Procedure D 4 Procedure C can access only the variables of Procedure A and Main Procedure C cannot access the variables of Procedure B or Procedure D 5 Procedure D can access the variables of Procedure C Procedure A and Main Procedure D cannot access the variables of Procedure B A 3 800186 INSTRUCTION SET ADDITIONS AND EXTENSIONS intel Main Program Lexical Lev
143. RUCTION SET ADDITIONS AND EXTENSIONS A 2 2 Arithmetic Instructions IMUL destination source data IMUL integer immediate multiply signed allows a value to be multiplied by an immediate op erand IMUL requires three operands The first destination is the register where the result will be placed The second source is the effective address of the multiplier The source may be the same register as the destination another register or a memory location The third data is an im mediate value used as the multiplicand The data operand may be a byte or word If data is a byte it is sign extended to 16 bits Only the lower 16 bits of the result are saved The result must be placed in a general purpose register A 2 3 Bit Manipulation Instructions This section describes the eight enhanced bit manipulation instructions A 2 3 1 Shift Instructions SAL destination count SAL immediate shift arithmetic left shifts the destination operand left by an immediate value SAL has two operands The first destination is the effective address to be shifted The second count is an immediate byte value representing the number of shifts to be made The CPU will AND count with 1FH before shifting to allow no more than 32 shifts Zeros shift in on the right SHL destination count SHL immediate shift logical left is physically the same instruction as SAL immediate shift arithmetic left SAR destination count SAR immediate shift arithmetic
144. S fick Anes nee cadet 1 3 1 3 CUSTOMER SERVIGE a ei inv Ged wiv nee 1 4 1 3 1 How to Use Intel s FaxBack Service 1 5 1 3 2 How to Use Intel s Application BBS 1 5 1 3 3 How to Find the Latest ADBUILDER Files Hypertext Manuals and Data Sheets on the BBS cde diee deos 1 6 CHAPTER 2 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 1 ARCHITECTURAL OVERVIEW 2 enne 2 1 2 1 1 Execution deae 2 2 2 1 2 Bus Interface Unit 2 3 2 11 32 Generali Registers ite rudis 2 4 21 4 Segment Registers 2 5 2 1 5 Instructio POIlntet et tcd ert eet 2 6 2 1 6 Flags eer cbe t eiae re D ob eee ye EET ree eg ERE 2 7 2 1 7 Memory Segmentation nennen nennen eterne rnnt nnne 2 8 2 1 8 Logical Addresses eite hec eL Ie SUD 2 10 2 1 9 Dynamically Relocatable Code sese nnns 2 13 2 1 10 Stack Implementation a nnne nnne nnne nennen 2 15 2 1 11 Reserved Memory and I O Space sssssseeeneeneneen nennen 2 15 2 2 SOFTWARE OVERVIEW nete eren ect eerte Lev ee ei 2 17 2 2 1 Instruction Seb st ed erm ueneno 2 17 2 2 1 1 Data Tra
145. SP 1 SP AX DF Pushes all data pointer and index i i lt SP sae IF registers onto the stack The order in SP 1 5 lt CX OF which the registers are saved is AX SP P 2 PF CX DX BX SP BP SI and DI The SP 1 5 lt DX SF SP value pushed is the SP value SP 6 2 before the first register AX is pushed SP 1 5 lt BX ZF Instruction Operands SP i P 2 none SP 1 5 lt temp SP lt P 2 SP 1 SP lt BP SP lt P 2 SP 1 5 51 SP lt is P 2 SP 1 SP lt DI PUSHF Push Flags SP T P 2 AF PUSHF SP 1 SP Flags EE Decrements SP by two and then IF transfers all flags to the word at the top OF of stack pointed to by SP PF Instruction Operands SF none TF ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 35 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel fare Flags Name Description Operation Affected RCL Rotate Through Carry Left temp lt count AF RCL dest count do while temp 0 CF v tmpcf lt CF DF Rotates the bits in the byte or w
146. Setting the appropriate bit in the Power Control Register Figure 5 9 prepares for Idle mode The processor enters Idle mode when it executes the HLT halt instruction If the program arms both Idle mode and Powerdown mode by mistake the device halts but remains in Active mode See Chapter 3 Bus Interface Unit for detailed information on HALT bus cycles Figure 5 10 shows some internal and external waveforms during entry into Idle mode 5 11 CLOCK GENERATION AND POWER MANAGEMENT intel Register Name Power Control Register Register Mnemonic PWRCON Register Function Arms power management functions I Bit Name Function 0 o A1129 0A Bit Mnemonic IDLE Idle Mode Setting the IDLE bit forces the CPU to enter the Idle mode when the HLT instruction is executed The PWRDN bit must be cleared when setting the IDLE bit otherwise Idle mode is not armed Powerdown Setting the PWRDN bit forces the CPU to enter Mode the Powerdown mode when the next HLT instruction is executed The IDLE bit must be cleared when setting the PWRDN bit otherwise Powerdown mode is not armed NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 5 9 Power Control Register intel CLOCK GENERATION AND POWER MANAGEMENT Halt Cycle ee T4 or TI T1 TI TI TI CLKOUT I
147. Status 06H Poll 04H EOI 02H 8 3 1 Interrupt Control Registers Each interrupt source has its own Interrupt Control register The Interrupt Control register allows you to define the behavior of each interrupt source Figure 8 4 shows the registers for the timers and serial channel Figure 8 5 shows the registers for INT4 2 and Figure 8 6 shows the registers for INTO and INTI All Interrupt Control registers have a three bit field PM2 0 that defines the priority level for the interrupt source and a mask bit MSK that enables or disables the interrupt source The mask bit is the same as the one in the Interrupt Mask register Modifying a bit in either register also mod ifies that same bit in the other register The Interrupt Control registers for the external interrupt pins also have a bit LVL that selects level triggered or edge triggered mode for that interrupt See Edge and Level Triggering on page 8 10 The Interrupt Control registers for the cascadable external interrupt pins INTO and INT1 have two additional bits to support the external 8259As The CAS bit enables cascade mode and the SENM bit enables special fully nested mode 8 12 intel INTERRUPT CONTROL UNIT Register Name Interrupt Control Register internal sources Register Mnemonic TCUCON SCUCON Register Function Control register for the internal interrupt sources A1213 A0 Bit F Bit Name Function Mnemonic MSK Interrupt Cle
148. T DESCRIPTIONS Table C 4 Instruction Set Continued Name Description Operation Flags Affected REP REPE REPZ REPNE REPNZ Repeat Repeat While Equal Repeat While Zero Repeat While Not Equal Repeat While Not Zero Controls subsequent string instruction repetition The different mnemonics are provided to improve program clarity REP is used in conjunction with the MOVS Move String and STOS Store String instructions and is interpreted as repeat while not end of string CX not 0 REPE and REPZ operate identically and are physically the same prefix byte as REP These instructions are used with the CMPS Compare String and SCAS Scan String instructions and require ZF posted by these instruc tions to be set before initiating the next repetition REPNE and REPNZ are mnemonics for the same prefix byte These instructions function the same as REPE and REPZ except that the zero flag must be cleared or the repetition is terminated ZF does not need to be initialized before executing the repeated string instruction Instruction Operands none do while CX 0 service pending interrupts if any execute primitive string Operation in succeeding byte CX CX 1 if primitive operation is CMPB CMPW SCAB or SCAW and ZF 0 then exit from while loop AF CF DF IF OF PF SF TF ZF NOTE The three symbols used in the Flags Affected column are
149. Table 10 1 BxCMP Values for Typical Baud Rates and CPU Frequencies CPU Frequency Baud 25 MHz 20 MHz 16 MHz 8 MHz Rate BxCMP 96 BxCMP 96 BxCMP 96 BxCMP 96 Value Error Value Error Value Error Value Error 19 200 80A2H 0 14 8081H 0 16 8067H 0 16 8033H 0 16 9 600 8145H 0 14 8103H 0 16 80CFH 0 16 8067H 0 16 4 800 828AH 0 00 8208H 0 03 81A0H 0 08 80CFH 0 16 2 400 8515H 0 00 8411H 0 03 8340H 0 04 81A0H 0 08 1 200 8A2BH 0 00 8822H 0 01 8682H 0 02 8340H 0 04 NOTE A zero or one value for BXCMP is illegal and results in unpredictable operation Programming BxCMP during a transmission or reception causes indeterminate operation 10 2 2 Asynchronous Mode Programming The serial port operation is controlled by two registers The Serial Port Control SxCON Register controls the mode of operation of the serial port see Figure 10 13 The Serial Port Status SxSTS Register acts as the flags register reporting on errors and the state of the RX and TX machines see Figure 10 14 Depending on the serial port mode these registers can have differ ent functionality This section outlines how to use SxCON and SxSTS to obtain the desired op eration from the serial port 10 2 2 1 Modes 1 3 and 4 for Stand alone Serial Communications When using these modes for their respective seven eight or nine bit data modes operation is fair ly
150. The 80C186 Modular Core family instruction set differs from the original 8086 8088 instruction set in two ways First several instructions that were not available in the 8086 8088 instruction set have been added Second several 8086 8088 instructions have been enhanced for the 80C186 Modular Core family instruction set 1 80C186 INSTRUCTION SET ADDITIONS This section describes the seven instructions that were added to the base 8086 8088 instruction set to make the instruction set for the 80C186 Modular Core family These instructions did not exist in the 8086 8088 instruction set Data transfer instructions PUSHA POPA String instructions INS OUTS High level instructions ENTER LEAVE BOUND A 1 1 Data Transfer Instructions PUSHA POPA PUSHA push all and POPA pop all allow all general purpose registers to be stacked and un stacked The PUSHA instruction pushes all CPU registers except as noted below onto the stack The POPA instruction pops all registers pushed by PUSHA off of the stack The registers are pushed onto the stack in the following order AX CX DX BX SP BP SI DI The Stack Pointer SP value pushed is the Stack Pointer value before the AX register was pushed When POPA is executed the Stack Pointer value is popped but ignored Note that this instruction does not save segment registers CS DS SS ES the Instruction Pointer IP the Processor Status Word or any integrated
151. Unit I O Ports 16 Total 22 Total 1 1 HOW TO USE THIS MANUAL This manual uses phrases such as 80C186 Modular Core Family or 80C188 Modular Core as well as references to specific products such as 80C188EA Each phrase refers to a specific set of 80C186 family products The phrases and the products they refer to are as follows 80C186 Modular Core Family This phrase refers to any device that uses the modular 80C186 C188 CPU core architecture At this time these include the 80C186EA C188EA 80C186EB C188EB 80C186EC C188EC and 80C186XL C188XL 80C186 Modular Core Without the word family this phrase refers only to the 16 bit bus mem bers of the 80C186 Modular Core Family 80C188 Modular Core This phrase refers to the 8 bit bus products 80 188 A specific product reference refers only to the named device For example On the SOCI8SEC refers strictly to the 80C188EC and not to any other device intel INTRODUCTION Each chapter covers a specific section of the device beginning with the CPU core Each periph eral chapter includes programming examples intended to aid in your understanding of device op eration Please read the comments carefully as not all of the examples include all the code necessary for a specific application This user s guide is a supplement to the device data sheet Specific timing values are not dis cussed in this guide When designing a system always consult the most recent version of the de vice d
152. YNCHRONOUS PINS 5 52 nte SAR Retina atte els B 2 APPENDIX C INSTRUCTION SET DESCRIPTIONS APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLES INDEX SUENE intel Figure 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 FIGURES Page Simplified Functional Block Diagram of the 80C186 Family CPU 2 2 Physical Address Generation sssssseeeeneeee enne 2 3 GeneraliBegistets e eaae dee I E P SETS 2 4 Segment Registers ERE ONCE aed 2 6 Processor Status Word eee beer a POENI ERES 2 9 Segment Locations in Physical Memory seen 2 10 Currently Addressable Segments sese nennen 2 11 Logical and Physical Address seeenn menm 2 12 Dynamic Code senem nennen nnne rs 2 14 Stack Operation uie Beh nabh te bv diode ence te s 2 16 Flag Storage Format ionerne nure t e ev eeu de HEC EHE EUER ia 2 19 Memory Address Computation essesssseeseeeeeeenenen nennen nennt 2 29 Direct Addressing nena pb inen vereri ra re ERE ered nece 2 30 Register Indirect Addressing 2 31
153. a byte then it is then PF multiplied by register AL and the CF lt 0 SF 5 double length result is returned in AH else TF and AL If the source operand is a CF lt 1 ZF word then it is multiplied by register OF lt CF and the double length result is When Source Operand is a Word returned in registers DX and AX The DX AX c AX X src operands are treated as unsigned if binary numbers see AAM If the DX 0 upper half of the result AH for byte then Source DX for word source is non CF 0 zero CF and OF are set otherwise else they are cleared CF 1 Instruction Operands OF CF MUL reg MUL mem NOTE The three symbols used in the Flags Affected column are defined as follows C 30 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued EM Flags Name Description Operation Affected NEG Negate When Source Operand is a Byte AF NEG dest dest lt dest SE Y Subtracts the destination operand dest lt dest 1 affecting flags IF which may be a byte or a word from 0 When Source Operand is a Word OF v and returns the result to desti dest lt FFFFH dest PF v nation This Tome
154. active to clock high assumes Ready remains CHIS active between 1 amp 2 2 READY hold from clock low A1082 0A Figure 3 17 Normally Not Ready System Timing A valid not ready input can be generated as late as phase of T3 to insert wait states in a normally ready system A normally not ready system must run wait states if the not ready condition cannot be met in time Figure 3 18 illustrates the minimum and maximum timing necessary to insert wait states in a normally ready system Figure 3 18 also shows how to terminate a bus cycle with wait states in a normally ready system The BIU can execute an indefinite number of wait states However bus cycles with large numbers of wait states limit the performance of the CPU and the integrated peripherals CPU performance suffers because the instruction prefetch queue cannot be kept full Integrated peripheral perfor mance suffers because the maximum bus bandwidth decreases 3 4 4 Idle States Under most operating conditions the BIU executes consecutive back to back bus cycles How ever several conditions cause the BIU to become idle An idle condition occurs between bus cy cles see Figure 3 8 on page 3 9 and may last an indefinite period of time depending on the instruction sequence 3 18 intel BUS INTERFACE UNIT CLKOUT READY In a Normally Ready system a wait state will be inserted when 1 amp 2 are met 1 READY low to clock high 2
155. address of the target slave with the ninth bit set over the serial link 2 Allslaves receive the character and check whether that address is theirs 3 The target slave switches to Mode 3 all other slaves remain in Mode 2 4 The master and the target slave continue the communication with all ninth data bits equal to zero The other slave devices ignore the activity on the serial link 10 7 SERIAL COMMUNICATIONS UNIT intel 5 Atthe end of the communication the target slave switches back to Mode 2 and waits for another address The parity feature cannot be used when implementing multiprocessor communications with Modes 2 and 3 as the ninth data bit is a control bit and cannot be used as the parity bit 10 1 2 Synchronous Communications The synchronous mode Mode 0 is useful primarily with shift register based peripheral devices The device outputs a synchronizing clock on TXD and transmits and receives data on RXD in 8 bit frames Figure 10 7 The serial port always provides the synchronizing clock it can never receive a synchronous clock on TXD Communication in the synchronous mode is half duplex The RXD pin cannot transmit and receive data at the same time Because the serial port always acts as the master in Mode 0 all transmissions and receptions are controlled by the serial port In Mode 0 the parity functions and break character detection functions are not available Mode 0 Transmit Mode 0 Receive A1289 0A
156. al purpose IF 0 PF registers and the upper and lower 0 SF bounds of the array are placed in two SP SP 2 TF consecutive memory locations The SP 1 SP lt CS ZF contents of the register are compared CS 1EH with the memory location values and if SP SP 2 the register value is less than the first SP 1 SP lt IP location or greater than the second IP 1CH memory location a trap type 5 is generated Instruction Operands BOUND reg mem CALL Call Procedure if AF CALL procedure name ME EE A en Activates an out of line procedure SP lt SP IE e saving information on the stack to SP 1 S TA lt CS OF permit a RET return instruction in the CS SEG PF procedure to transfer control back to SP lt SP 2 SF the instruction following the CALL The SP 1 SP lt IP TF assembler generates a different type IP lt dest ZF of CALL instruction depending on whether the programmer has defined the procedure name as NEAR or FAR Instruction Operands CALL near proc CALL far proc CALL memptr16 CALL regptr16 CALL memptr32 NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 7 INSTRUCTION SET
157. aled by Timer 2 increments when Timer 2 reaches its maximum count value 9 1 TIMER COUNTER UNIT Transition Latch Transition Latch Synchronizer Synchronizer Timer 0 Registers Counter EM Element Registers Timer 2 Output Latch Registers Interrupt Clock Latch Output Latch Figure 9 1 Timer Counter Unit Block Diagram 9 2 TO Out T1 Out A1292 0A intel TIMER COUNTER UNIT Timer 0 Timer 1 Timer 2 Timer 0 Timer 1 Timer 2 Timer 0 ServicedServicedServiced Dead ServicedServicedServiced Dead Serviced NOTES TOIN resolution time setup time met TAIN resolution time setup time not met Modified count value written into Timer 0 count register TAIN resolution time count value written into Timer 1 count register TAIN resolution time A1293 0A Figure 9 2 Counter Element Multiplexing and Timer Input Synchronization TIMER COUNTER UNIT intel Timer Enabled EN 1 External Clocking EXT 1 Retrigger RTG 1 Lo to Hi Lo to Hi Timer Input transition on input transition on input at High Level pin since last pin since last service service Clear Count Prescaler On Register P 1 Did Timer 2 Reach Maxcount Increment Last Service Counter State Continued 1294 0 Figure 9 3 Timers 0 and 1 Flow Chart intel TIMER COUNTER UNIT Continued From A Alternating Maxcount Regs ALT 1 Counter Using Compare A Maxcou
158. and CPU can both access the register banks these accesses are synchronized The Timer Counter Unit is serviced over four clock periods one timer during each clock with an idle clock at the end see Figure 9 2 No connection exists between the counter element s se quencing through timer register banks and the Bus Interface Unit s sequencing through T states Timer operation and bus interface operation are asynchronous This time multiplexed scheme re sults in a delay of 212 to 6 CLKOUT periods from timer input to timer output Each timer keeps its own running count and has a user defined maximum count value Timers 0 and 1 can use one maximum count value single maximum count mode or two alternating max imum count values dual maximum count mode Timer 2 can use only one maximum count val ue The control register for each timer determines the counting mode to be used When a timer is serviced its present count value is incremented and compared to the maximum count for that tim er If these two values match the count value resets to zero The timers can be configured either to stop after a single cycle or to run continuously Timers 0 and 1 are functionally identical Figure 9 3 illustrates their operation Each has a latched synchronized input pin and a single output pin Each timer can be clocked internally or externally Internally the timer can either increment at 14 CLKOUT frequency or be prescaled by Timer 2 A timer that is presc
159. and I O read instruction prefetch and interrupt acknowledge bus cycles 3 36 intel BUS INTERFACE UNIT AD15 8 Ein D15 8 GCSO Buffered Data Bus AD7 0 D7 0 DT R T Buffer Local Data Bus A1096 01 Figure 3 32 Qualifying DEN with Chip Selects 3 6 2 Synchronizing Software and Hardware Events The execution sequence of a program and hardware events occurring within a system are often asynchronous to each other In some systems there may be a requirement to suspend program ex ecution until an event or events occurs then continue program execution One way to synchronize software execution with hardware events requires the use of interrupts Executing a HALT instruction suspends program execution until an unmasked interrupt occurs However there is a delay associated with servicing the interrupt before program execution can proceed Using the WAIT instruction removes the delay associated with servicing interrupts 3 37 BUS INTERFACE UNIT intel The WAIT instruction suspends program execution until one of two events occurs an interrupt is generated or the TEST input pin is sampled low Unlike interrupts the TEST input pin does not require that program execution be transferred to a new location i e an interrupt routine is not executed In processing the W AIT instruction program execution remains suspended as long as TEST remains high at least until an interrupt occurs When TEST is sampled low pro
160. and INPUT are shifted through the module and eventually drive READY high Assuming INPUTI and INPUT2 are valid prior to phase 2 of T2 no delay through the module causes one wait state Each additional clock delay through the module generates one additional wait state Two inputs are used to establish different wait state conditions Wait State Module CLKOUT A1080 0A Figure 3 15 Generating a Normally Not Ready Bus Signal A normally ready signal remains high at all times except when the selected device needs to signal a not ready condition For any bus cycle only the selected device drives the READY input low to delay the completion of the bus cycle The circuit shown in Figure 3 16 illustrates a simple cir cuit to generate a normally ready signal Note that if no device is selected the bus remains ready Systems that have few or no devices requiring wait states usually implement a normally ready signal The start of a bus cycle preloads a zero shifter and forces READY active high READY remains active if neither CST or CS2 goes low Should either CST or CS2 go low zeros are shifted out on every rising edge of CLKOUT causing READY to go inactive At the end of the shift pattern READY is forced active again Assuming CST and CS2 are active just prior to phase 2 of T2 shifting one zero through the module causes two wait states Each additional zero shifted through the module generates one wait state intel BUS INTERFACE UNIT Wai
161. and instruction fetch bus cycles I O peripheral devices exchange information with the CPU during memory read memory write I O read I O write and interrupt acknowledge bus cycles Memory mapped I O refers to periph eral devices that exchange information during memory cycles Memory mapped I O allows the full power of the instruction set to be used when communicating with peripheral devices I O read and I O write bus cycles use a separate I O address space Only IN and OUT instructions can access I O address space and information must be transferred between the peripheral device and the AX register The first 256 bytes 0 255 of I O space can be accessed directly by the I O instructions The entire 64 Kbyte I O address space can be accessed only indirectly through the DX register I O instructions always force address bits A19 16 to zero Interrupt acknowledge or INTA bus cycles access an I O device intended to increase interrupt input capability Valid address information is not generated as part of the INTA bus cycle and data is transferred only over the lower bank 16 bit device 3 6 intel BUS INTERFACE UNIT 3 3 1 16 Bit Bus Memory and I O Requirements A 16 bit bus has certain assumptions that must be met to operate properly Memory used to store instruction operands i e the program and immediate data must be 16 bits wide Instruction prefetch bus cycles require that both banks be used The lower bank contains the even b
162. anged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 20 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued MEN A Flags Name Description Operation Affected JAE Jump on Above or Equal if AF JNB Jump on Not Below CF 0 JAE disp8 then 2 JNB disp8 IP lt IP disp8 sign ext to 16 bits ae Transfers control to the target location PF if the tested condition CF 0 is true SF Instruction Operands TF JAE short label ZF JNB short label JB Jump on Below if AF JNAE Jump on Not Above or Equal CF 1 disp8 then DF JNAE disp8 IP lt IP disp8 sign ext to 16 bits SE Transfers control to the target location PF if the tested condition CF 1 is true SF Instruction Operands TF JB short label ZF JNAE short label JBE Jump on Below or Equal if AF JNA Jump on Not Above CF 1 or ZF 1 CF JBE disp8 then eo DE JNA disp8 IP lt IP disp8 sign ext to 16 bits a Transfers control to the target location PF if the tested condition C 1 or SF ZF 1 is true TF Instruction Operands ZF JBE short label JNA short label JC Jump on Carry if AF JC disp8 1 cF Transfers control to the target location men I n P IP lt IP disp8 sign ext to 16 b
163. ar to enable interrupts from this source Mask PM2 0 Priority 111 Defines the priority level for this source Level NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 4 Interrupt Control Register for Internal Sources INTERRUPT CONTROL UNIT intel Register Name Interrupt Control Register non cascadable pins Register Mnemonic I2CON I3CON I4CON Register Function Control register for the non cascadable external internal interrupt pins A1214 A0 Bit Function Mnemonic LVL Level trigger Selects the interrupt triggering mode 0 edge triggering 1 level triggering MSK Interrupt Clear to enable interrupts from this source Mask PM2 0 Priority 111 Defines the priority level for this source Level NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 5 Interrupt Control Register for Noncascadable External Pins intel INTERRUPT CONTROL UNIT Register Name Interrupt Control Register cascadable pins Register Mnemonic IOCON I1 CON Register Function Control register for the cascadable external interrupt pins A1215 A0 Bit Bit Name Function Mnemonic SFNM Special Set to enable special fully nested mode F
164. are a priority Within the assigned priority the receive interrupt has the higher relative priority Table 8 1 Default Interrupt Priorities Interrupt Name Relative Priority Timer 0 0 a Timer 1 0 b Timer 2 0 c Serial Channel 0 Receive 1 a Serial Channel 0 Transmit 1 b The priority of each source is programmable The Interrupt Control register enables the programmer to assign each source a priority that differs from the default The priority must still be between zero highest and seven lowest Interrupt sources can be programmed to share a priority The Interrupt Control Unit uses the default priorities see Table 8 1 within the shared priority level to determine which interrupt to service first For example assume that INTO and INTI are both programmed to priority seven Because INTO has the higher default priority it is serviced first 8 3 INTERRUPT CONTROL UNIT intel Interrupt sources can be masked on the basis of their priority The Priority Mask register masks all interrupts with priorities lower than its programmed value After reset the Priority Mask reg Ister contains priority seven which effectively enables all interrupts The programmer can then program the register with any valid priority level 8 1 1 3 Interrupt Nesting When entering an interrupt handler the CPU pushes the Processor Status Word onto the stack and clears the Interrupt Enable bit The processor enters all inter
165. at The following sections present timing equations containing symbols found in the data sheet The timing equations provide information necessary to start a worst case design analysis 3 5 1 Read Bus Cycles Figure 3 19 illustrates a typical read cycle Table 3 2 lists the three types of read bus cycles Table 3 2 Read Bus Cycle Types Status Bit Bus Cycle Type 2 S1 S0 0 0 1 Read I O Initiated by the Execution Unit or the Refresh Control Unit A19 16 are driven to zero see Chapter 10 Direct Memory Access Unit 1 0 0 Instruction Prefetch Initiated by the BIU Data read from the bus fills the prefetch queue 1 0 1 Read Memory Initiated by the Execution Unit or the Refresh Control Unit A19 0 select the desired byte or word memory location Figure 3 20 illustrates a typical 16 bit interface connection to a read only device interface The same example applies to an 8 bit bus system except that no devices connect to an upper bus Four parameters Table 3 3 must be evaluated when determining the compatibility of a memory or T O device Tap defines the delay through the address latch Table 3 3 Read Cycle Critical Timing Parameters Description Equation Toe Output enable RD low to data valid 2T Taova Tous Tacc Address valid to data valid 3T Taovo Tapttcn Teus Tor Chip enable UCS to data valid Terov2 Tous Tpr Out
166. ata sheet for up to date specifications 1 2 RELATED DOCUMENTS The following table lists documents and software that are useful in designing systems that incor porate the 80C186 Modular Core Family These documents are available through Intel Literature In the U S and Canada call 1 800 548 4725 to order In Europe and other international locations please contact your local Intel sales office or distributor NOTE If you will be transferring a design from the 80186 80188 or 80C186 80C188 to the 80C186XL 80C188XL refer to FaxBack Document No 2132 Table 1 2 Related Documents and Software Document Software Title Embedded Microprocessors includes 186 family data sheets 272396 186 Embedded Microprocessor Line Card 272079 80186 80188 High Integration 16 Bit Microprocessor Data Sheet 272430 80C186XL C188XL 20 12 16 Bit High Integration Embedded Microprocessor 272431 Data Sheet 80C186EA 80C188EA 20 12 and 80L186EA 80L1 88EA 13 8 low power 272432 versions 16 Bit High Integration Embedded Microprocessor Data Sheet 80C186EB 80C188EB 20 13 and 80L186EB 80L1 88EB 13 8 low power 272433 versions 16 Bit High Integration Embedded Microprocessor Data Sheet 80C186EC 80C188EC 20 13 and 80L186EC 80L188EC 13 8 low power 272434 versions 16 Bit High Integration Embedded Microprocessor Data Sheet 806187 80 Bit Math Coprocessor Data Sheet 270640 Low Voltage Embedded Design 272324 80C186 C
167. available that will generate an interrupt in this situation If the Sign Flag SF is set the high order bit of the result is a 1 Since negative binary numbers are represented in standard two s complement notation SF indicates the sign of the result 0 positive 1 negative Ifthe Parity Flag PF is set the result has even parity an even number of bits This flag can be used to check for data transmission errors Ifthe Zero Flag ZF is set the result of the operation is zero Additional control flags see Figure 2 5 can be set or cleared by programs to alter processor op erations Setting the Direction Flag DF causes string operations to auto decrement Strings are processed from high address to low address or right to left Clearing DF causes string operations to auto increment Strings are processed from low address to high address or left to right Setting the Interrupt Enable Flag IF allows the CPU to recognize maskable external or internal interrupt requests Clearing IF disables these interrupts The Interrupt Enable Flag has no effect on software interrupts or non maskable interrupts Setting the Trap Flag TF bit puts the processor into single step mode for debugging In this mode the CPU automatically generates an interrupt after each instruction This allows a program to be inspected instruction by instruction during execution The status and control flags are contained in a 16 bit Pro
168. before HLDA becomes active 3 41 BUS INTERFACE UNIT intel T CO M NOTES HLDA is deasserted signaling need to run refresh bus cycle External bus master terminates use of the bus HOLD deasserted Hold may be reasserted after one clock BIU runs refresh cycle A1098 0A Figure 3 34 Refresh Request During HOLD The device requesting a bus hold must be able to detect a HLDA pulse that is one clock in dura tion A bus lockup hang condition can result if the requesting device fails to detect the short HLDA pulse and continues to wait for HLDA to be asserted while the BIU waits for HOLD to be deasserted The circuit shown in Figure 3 35 can be used to latch HLDA 3 42 intel BUS INTERFACE UNIT Latched HLDA RESOUT HOLD A1310 0A Figure 3 35 Latching HLDA The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain the bus and execute a refresh bus cycle Should HOLD go active before the refresh bus cycle is complete the BIU will release the bus and generate HLDA 3 7 2 Exiting HOLD Figure 3 36 shows the timing associated with exiting the bus hold state Normally a bus operation e g an instruction prefetch occurs just after HOLD is released However if no bus cycle is pending when leaving a bus hold state the bus and associated control signals remain floating if the system is in normal operating mode For signal states associated with Idle a
169. between an NMI and an unmasked interrupt The core begins the inter rupt response six cycles after the core clock restarts when it fetches the NMI vector from location 00008H NMI does not clear the IDLE bit in the Power Control Register Resetting the microprocessor will return the device to Active mode Unlike interrupts a reset clears the Power Control Register Execution begins as it would following a warm reset see set and Clock Synchronization on page 5 6 5 2 1 4 Example Idle Mode Initialization Code Example 5 1 illustrates programming the Power Control Register and entering Idle mode upon HLT The interrupts from the serial port and timers are not masked Assume that the serial port connects to a keyboard controller At every keystroke the keyboard sends a data byte and the processor wakes up to service the interrupt After acting on the keystroke the core will go back into Idle mode The example excludes the actual keystroke processing 5 15 CLOCK GENERATION AND POWER MANAGEMENT intel mod186 name example 80C186 power management code FUNCTION This function reduces CPU power consumption SYNTAX extern void far power mgt int mode INPUTS mode 00 Active Mode 01 Powerdown Mode 02 Idle Mode 03 Active Mode OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages PWRCON equ xxxxH substitute PWRCON register offset lib 80C186 segment public code a
170. bus 11 10 intel INPUT OUTPUT PORTS Register Name Port Pin State Register Register Mnemonic PxPIN P1PIN P2PIN Register Function Reads the logic state at a port pin 15 0 P P 7 A1315 0A Bit Mnemonic Reset Bit Name State Function PP7 0 Port Pin XXXXH Reading the Port Pin State register returns the State 7 0 logic state present on the associated pin NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 11 8 Port Pin State Register PxPIN 11 2 5 Initializing the I O Ports The state of the I O ports following a reset is as follows Port 1 is configured for peripheral function general purpose chip selects GCS7 0 Port2 is configured for peripheral function The direction of each pin is the default direction for the peripheral function e g P2 1 TXD1 is an output P2 5 BCLKO is an input See Table 11 2 on page 11 7 for details There are no set rules for initializing the I O ports The Port Data Latch should be programmed before selecting a pin as an output port to prevent unknown Port Data Latch values from reaching the pins 11 11 INPUT OUTPUT PORTS intel 11 3 PROGRAMMING EXAMPLE Example 11 1 shows a typical ASM86 routine to configure the I O ports GCS7 through GCS4 are routed to the pins while P1 0 through P1 4 are used as output ports The bi
171. ce routine Each interrupt or exception is given a type number 0 through 255 corresponding to its position in the Interrupt Vector Table Note that in terrupt types 0 31 are reserved for Intel and should not be used by an application program 2 39 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Memory Table Vector Memory Table Vector Address Entry Definition Address Entry Definition SFE Type 255 T 13 INT1 src _ id T User Available Type 12 INTO Type 32 Type 9 11 Reserved Type 31 Type 8 Timer 0 Reserved Type 7 ESC Opcode Type 22 Type 6 Unused Opcode Type 21 Type 5 Array Serial 0 Trans Bounds Type 20 Type 4 Overflow Serial 0 Rec Type 19 Timer 2 Type 3 Breakpoint Type 18 Timer 1 Type 2 NMI Type 17 INT4 Type 1 Single Step Type 16 Numerics Type 0 Divide Error 80C186EB only Type 15 INT3 lt 2 Bytes gt Type 14 INT2 CS Code Segment Value IP Instruction Pointer Value A1010 01 Figure 2 25 Interrupt Vector Table When an interrupt is acknowledged a common event sequence Figure 2 26 allows the proces sor to execute the interrupt service routine 1 The processor saves a partial machine status by pushing the Processor Status Word onto the stack 2 40 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word This prevents maskable interrupts or single step exce
172. cessor Status Word see Figure 2 5 Re set initializes the Processor Status Word to OFOOOH 2 7 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel 2 1 7 Memory Segmentation Programs for the 80C186 Modular Core family view the 1 Mbyte memory space as a group of user defined segments A segment is a logical unit of memory that can be up to 64 Kbytes long Each segment is composed of contiguous memory locations Segments are independent and sep arately addressable Software assigns every segment a base address starting location in memory space All segments begin on 16 byte memory boundaries There are no other restrictions on seg ment locations Segments can be adjacent disjoint partially overlapped or fully overlapped see Figure 2 6 A physical memory location can be mapped into covered by one or more logical segments 2 8 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE Processor Status Word PSW FLAGS Posts CPU status information Register Name Register Mnemonic Register Function 15 0 5 7 C F F F A1035 0A Bit Mnemonic Bit Name Function OF Overflow Flag If OF is set an arithmetic overflow has occurred Direction Flag If DF is set string instructions are processed high address to low address If DF is clear strings are processed low address to high address Interrupt Enable Flag If IF is set the CPU recognizes maskable interrupt requests
173. column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 25 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel ae E Flags Name Description Operation Affected LDS Load Pointer Using DS dest EA AF LDS dest src 05 lt EA 2 Ed z Transfers a 32 bit pointer variable from IF R the source operand which must be a OF memory operand to the destination operand and register DS The offset SF word of the pointer is transferred to the TF destination operand which may be ZF any 16 bit general register The segment word of the pointer is transferred to register DS Instruction Operands LDS reg16 mem32 LEA Load Effective Address dest lt EA AF LEA dest src E 2 Transfers the offset of the source IF operand rather than its value to the OF destination operand PF Instruction Operands SF LEA reg16 mem16 TF ZF LEAVE Leave SP BP AF LEAVE lt SP 1 SP CF SP SP 2 DF Reverses the action of the most recent IF ENTER instruction Collapses the last stack frame created First LEAVE PF copies the current BP to the stack SF pointer releasing the stack space TF allocated to the current
174. comparison reflected in the flags is that of the destination to the source If a CMP instruction is followed by a JG jump if greater instruction for example the jump is taken if the destination operand is greater than the source operand Instruction Operands CMP reg reg CMP reg mem CMP mem reg CMP reg immed CMP mem immed CMP accum immed CMPS Compare String dest string src string AF v CMPS dest string src string if DF 0 Y Subtracts the destination byte or word then IF from the source byte or word The 91 SI DELTA OF v destination byte or word is addressed DI DI DELTA PF by the destination index DI register else SF v and the source byte or word is 91 SI DELTA TF addresses by the source index SI DI DI DELTA ZF register CMPS updates the flags to reflect the relationship of the destination element to the source element but does not alter either operand and updates SI and DI to point to the next string element Instruction Operands CMP dest string src string CMP repeat dest string src string NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued
175. cond read write cycle of an odd addressed word operation is inseparable from the first bus cycle The second read write cycle of an instruction with both load and store accesses e g XCHG can be separated from the first cycle by other bus cycles Successive bus cycles of string instructions e g MOVS can be separated by other bus cycles When a locked instruction begins its associated bus cycles become the highest priority and cannot be separated or preempted until completed 10 Bus cycles necessary to fill the prefetch queue 3 45 intel Peripheral Control Block intel CHAPTER 4 PERIPHERAL CONTROL BLOCK All integrated peripherals in the 80C186 Modular Core family are controlled by sets of registers within an integrated Peripheral Control Block PCB The peripheral control registers are physi cally located in the peripheral devices they control but they are addressed as a single block of registers The Peripheral Control Block encompasses 256 contiguous bytes and can be located on any 256 byte boundary of memory or I O space The PCB Relocation Register which is also lo cated within the Peripheral Control Block controls the location of the PCB 4 1 PERIPHERAL CONTROL REGISTERS Each of the integrated peripherals control and status registers is located at a fixed offset above the programmed base location of the Peripheral Control Block see Table 4 1 These registers are described in the chapters that
176. cs Numeric data values are non integral or vary over a wide range Algorithms produce very large or very small intermediate results Computations must be precise i e calculations must retain several significant digits Computations must be reliable without dependence on programmed algorithms Overall math performance exceeds that afforded by a general purpose processor and software alone For the 80C186 Modular Core family the 80C187 math coprocessor satisfies the need for pow erful mathematics The 80C187 can increase the math performance of the microprocessor system by 50 to 100 times 12 2 AVAILABILITY OF MATH COPROCESSING The 80C186 Modular Core supports the 80C187 with a hardware interface under microcode con trol However not all proliferations support the 80C187 Some package types have insufficient leads to support the required external handshaking requirements The 3 volt versions of the pro cessor do not specify math coprocessing because the 80C187 has only a 5 volt rating Please refer to the current data sheets for details The core has an Escape Trap ET bit in the PCB Relocation Register Figure 4 1 on page 4 2 to control the availability of math coprocessing If the ET bit is set an attempted numerics execution results in a Type 7 interrupt The 80C187 will not work with the 8 bit bus version of the processor because all 80C187 accesses must be 16 bit The 80C188 Modular Core automatically traps ESC numerics opc
177. ction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel Table C 4 Instruction Set Continued INSTRUCTION SET DESCRIPTIONS Name Description Operation HLT Halt None AF HLT DF Causes the CPU to enter the halt IF state The processor leaves the halt OF state upon activation of the RESET PF line upon receipt of a non maskable SF interrupt request on NMI or upon receipt of a maskable interrupt request ZF on INTR if interrupts are enabled Instruction Operands none NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 15 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel fare Flags Name Description Operation Affected IDIV Integer Divide When Source Operand is a Byte AF IDIV src temp lt byte src Performs a signed division of the if B accumulator and its extension by the temp AX 0 and OF source operand If the source operand temp AX gt 7FH or PF is a byte it is divided into the double temp AX 0 and SE length dividend assumed to be in
178. cy about halfway between the fundamental frequency and the third overtone frequency This criterion makes the circuit capacitive at the third overtone frequency necessary for oscil lation The two capacitors and inductor at OSCOUT plus some stray capacitance approximately equal the 20 pF load capacitor Cy used alone in the fundamental mode circuit a b c Fundamental Third Overtone Third Overtone Mode Mode Circuit Mode Circuit Equivalent Circuit OSCOUT 200 Li See text A1126 0A Figure 5 3 Crystal Connections to Microprocessor Choosing C as 200 pF at least 10 times the value of the load capacitor simplifies the circuit analysis At the series resonance the capacitance connected to L is 200 pF in series with 20 pF The equivalent capacitance is still about 20 pF and the equation in Figure 5 4 a yields the series resonant frequency To examine the parallel resonant frequency refer to Figure 5 3 c an equivalent circuit to Figure 5 3 b The capacitance connected to L is 200 pF in parallel with 20 pF The equivalent capaci tance is still about 200 pF within 10 and the equation in Figure 5 4 a now yields the parallel resonant frequency 5 3 CLOCK GENERATION AND POWER MANAGEMENT intel a Series or Parallel Resonant Frequency b Equivalent Capacitance 2 C O5 eq a C Eo Figure 5 4 Equations for Crystal Calculations The equation in Figure 5 4 b yields the eq
179. cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the 8086 8088 instruction set See Appendix A 80C 186 Instruction Set Additions and Extensions for details intel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 2 Instruction Set Summary Continued Function Format Clocks Notes PROCESSOR CONTROL INSTRUCTIONS CLC Clear carry 111 000 2 CMC Complement carry 11110101 2 STC Set carry 111 001 2 CLD Clear direction 111 00 2 STD Set direction 111 01 2 CLI Clear interrupt 111 010 2 STI Set interrupt 111 011 2 HLT Halt 11110100 2 WAIT Wait 100 011 6 4 LOCK Bus lock prefix 11110000 2 ESC Math coprocessor escape 110 MMM mod PPP r m 6 NOP No operation 10010000 3 SEGMENT OVERRIDE PREFIX cs 00101110 2 SS 00110110 2 DS 00111110 2 ES 00100110 2 NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the 8086 8088 instruction set See Appendix 80C 186 Instruction Set Additions and Extensions for details Table D 3 Machine Instruction Decoding Guide the Byte 2 Bytes 3 6 ASN 86 Instruction Format Hex Binary 00 0000
180. d The count does not reset to zero if its value is greater than the maximum count If the count value ex ceeds the Maxcount Compare value the timer counts to OFFFFH increments to zero then counts to the value in the Maxcount Compare register Upon reaching a maximum count value the Max imum Count MC bit in the Timer Control register sets The MC bit must be cleared by writing to the Timer Control register This is not done automatically The Timer Counter Unit can be configured to execute different counting sequences The timers can operate in single maximum count mode all timers or dual maximum count mode Timers 0 and 1 only They can also be programmed to run continuously in either of these modes The AI ternate ALT bit in the Timer Control register determines the counting modes used by Timers 0 and 1 All timers can use single maximum count mode where only Maxcount Compare A is used The timer will count to the value contained in Maxcount Compare A and reset to zero Timer 2 can operate only in this mode Timers 0 and 1 can also use dual maximum count mode In this mode Maxcount Compare A and Maxcount Compare B are both used The timer counts to the value contained in Maxcount Com pare A resets to zero counts to the value contained in Maxcount Compare B and resets to zero again The Register In Use RIU bit in the Timer Control register indicates which Maxcount Compare register is currently in use The timers can be program
181. d 000 r m data data if w 1 12 13 1 immediate to register 011w reg data data if w 1 3 4 1 memory to accumulator 010000w addr low addr high 9 accumulator to memory 010001w addr low addr high 8 register memory to segment register 0001110 mod 0 reg r m 2 9 segment register to register memory 0001100 mod 0 reg r m 2 11 PUSH Push memory 1111111 mod 110 r m 16 register 01010 reg 10 segment register 000reg110 3 immediate 011010s0 data data if s 0 10 POP Pop memory 10001111 mod 000 r m 20 register 01011 reg 10 segment register 000reg111 reg 01 8 PUSHA Push all 01100000 36 POPA Pop all 01100001 51 XCHG Exchange register memory with register 1000011w mod reg r m 4 17 register with accumulator 10010 reg 3 XLAT Translate byte to AL 11010111 11 IN Input from fixed port 1110010w port 10 variable port 1110110w 8 OUT Output from fixed port 1110010w port 9 variable port 1110110w 7 NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the 8086 8088 instruction set See Appendix A 80C 186 Instruction Set Additions and Extensions for details intel Table D 2 Instruction Set Summary Continued INSTRUCTION SET OPCODES AND CLOCK CYCLES
182. d Memory Detector 6 20 intel 7 Refresh Control Unit intel CHAPTER 7 REFRESH CONTROL UNIT The Refresh Control Unit RCU simplifies dynamic memory controller design with its integrat ed address and clock counters Figure 7 1 shows the relationship between the Bus Interface Unit and the Refresh Control Unit Integrating the Refresh Control Unit into the processor allows an external DRAM controller to use chip selects wait state logic and status lines V P 9 Down Counter Refresh Request Refresh Clock Interval Register BIU Interface CLR Refresh Acknowledge Refresh Control Register 12 Bit Address Counter Refresh Address Register 20 Bit Refresh Address A1264 01 Figure 7 1 Refresh Control Unit Block Diagram 7 1 REFRESH CONTROL UNIT intel 7 1 THE ROLE OF THE REFRESH CONTROL UNIT Like a DMA controller the Refresh Control Unit runs bus cycles independent of CPU execution Unlike a DMA controller however the Refresh Control Unit does not run bus cycle bursts nor does it transfer data The DRAM refresh process freshens individual DRAM rows in dummy read cycles while cycling through all necessary addresses The microprocessor interface to DRAMs is more complicated than other memory interfaces A complete DRAM controller requires circuitry beyond that provided by the processor even in the simplest configurations This circuitry must respond correctly
183. d is treated as an unsigned binary PF v number see AAA and DAA SF v Instruction Operands TF INC reg INS In String dest src AF INS dest string port 2 e Performs block input from an I O port IF to memory The port address is placed OF in the DX register The memory address is placed in the DI register SF This instruction uses the ES register which cannot be overridden After the 7 data transfer takes place the DI register increments or decrements depending on the value of the direction flag DF The DI register changes by 1 for byte transfers or 2 for word transfers Instruction Operands INS dest string port INS repeat dest string port NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued Name Description Operation Flags Affected INT Interrupt INT interrupt type Activates the interrupt procedure specified by the interrupt type operand Decrements the stack pointer by two pushes the flags onto the stack and clears the trap TF and interrupt enable IF flags to disable single step and maskable interrupts Th
184. defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 37 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel E E Flags Name Description Operation Affected RET Return IP lt SP 1 SP AF RET optional pop value S SP 2 E i Transfers control from a procedure inter segment TM back to the instruction following the then OF CALL that setae the procedure CS SP 1 SP PF The assemb er generates an intra SP SP 2 SF segment RET if the programmer has if TF defined the procedure near or an add immed8 to SP ZF intersegment RET if the procedure has then been defined as far RET pops the SP SP data word at the top of the stack pointed to by register SP into the instruction pointer and increments SP by two If RET is intersegment the word at the new top of stack is popped into the CS register and SP is again incremented by two If an optional pop value has been specified RET adds that value to SP Instruction Operands RET immed8 ROL Rotate Left temp lt count AF ROL dest count do while temp 0 CF v R he destination b d CF lt high order bit of dest DF yte Ta dest lt dest x 2 CF F eft by the number
185. dles asynchronous external events for example an NMI Exceptions result directly from the execution of an instruction usually an instruction fault The user can cause a software interrupt by executing an INTn instruction The CPU processes software in terrupts in the same way that it handles exceptions The 80C186 Modular Core responds to interrupts and exceptions in the same way for all devices within the 80C186 Modular Core family However devices within the family may have different Interrupt Control Units The Interrupt Control Unit handles all external interrupt sources and pre sents them to the 80C186 Modular Core via one maskable interrupt request see Figure 2 24 This discussion covers only those areas of interrupts and exceptions that are common to the 80C186 Modular Core family The Interrupt Control Unit is proliferation dependent see Chapter 8 Interrupt Control Unit for additional information Maskable Interrupt Request Interrupt External Control Interrupt Unit Sources Interrupt Acknowledge A1028 0A Figure 2 24 Interrupt Control Unit 2 3 1 Interrupt Exception Processing The 80C186 Modular Core can service up to 256 different interrupts and exceptions A 256 entry Interrupt Vector Table Figure 2 25 contains the pointers to interrupt service routines Each en try consists of four bytes which contain the Code Segment CS and Instruction Pointer IP of the first instruction in the interrupt servi
186. dress Register RFADDR 7 10 Refresh Base Address Register RFBASE 7 7 7 8 Refresh bus cycle See Bus cycles Refresh Clock Interval Register RFTIME 7 7 7 8 Refresh Control Register RFCON 7 9 7 10 Refresh Control Unit RCU 7 1 7 14 and bus hold protocol 7 13 7 14 and Powerdown mode 7 2 block diagram 7 1 bus latency 7 7 calculating refresh interval 7 7 control registers 7 7 7 10 initialization code 7 11 operation 7 2 overview 7 2 7 4 programming 7 7 7 12 relationship to BIU 7 1 Register operands 2 27 Registers 2 1 control 2 1 data 2 4 2 5 general 2 1 2 4 2 5 H amp L group 2 4 index 2 5 2 13 2 34 P amp I group 2 4 pointer 2 1 2 5 2 13 pointer and index 2 4 segment 2 1 2 5 2 11 2 12 status 2 1 Relocation Register See PCB Relocation Register Reset and bus hold protocol 5 6 and clock synchronization 5 6 5 10 cold 5 7 5 8 RC circuit for reset input 5 7 warm 5 7 5 9 ROL instruction A 10 ROR instruction A 10 Index 6 intel S SAL instruction A 9 SAR instruction A 9 Serial Communications Unit SCU asynchronous communications 10 1 10 8 10 13 10 18 example 10 24 10 28 mode 1 10 6 mode 2 10 7 mode 3 10 6 mode 4 10 6 baud rates 10 10 10 13 baud timebase clock 10 21 10 22 BCLK pin timings 10 19 10 21 break characters 10 4 10 15 channel 0 interrupts 10 22 channel 1 interrupts 10 22 CTS pin timings 10 19 examples 10 24 10 36 features
187. dress is ignored 5 The bus cycle is not accessing the Peripheral Control Block A memory address applies to memory read memory write and instruction prefetch bus cycles An I O address applies to I O read and I O write bus cycles Interrupt acknowledge and HALT bus cycles never activate a chip select regardless of the address generated After power on or system reset only the UCS chip select is initialized and active see Figure 6 4 6 4 intel CHIP SELECT UNIT Active For Processor Top 1 KByte NOTE 1 15 Wait states automatically inserted Bus READY must be provided A1162 0A Figure 6 4 UCS Reset Configuration 6 4 PROGRAMMING Two registers START and STOP determine the operating characteristics of each chip select The Peripheral Control Block defines the location of the Chip Select Unit registers Table 6 1 lists the registers and their associated programming names Table 6 1 Chip Select Unit Registers eee Chip Select Affected GCSOST GCSOSP GCS0 GCS1ST GCS1SP GCST GCS2ST GCS2SP GCS2 GCS3ST GCS3SP GCS3 GCS4ST GCS4SP GCS4 GCS5ST GCS5SP GCS5 GCS6ST GCS6SP GCS6 GCS7ST GCS7SP GCS7 UCSST UCSSP UCS LCSST LCSSP LCS 6 5 CHIP SELECT UNIT intel The START register Figure 6 5 defines the starting address and the wait state requirements The STOP register Figure 6 6 defines the ending address and the bus ready bus cycle and enable requirements 6 4
188. dular Core family memory space is 1 Mbyte in size and divided into logical seg ments of up to 64 Kbytes each The CPU has direct access to four segments at a time The segment registers contain the base addresses starting locations of these memory segments see Figure 2 4 The CS register points to the current code segment which contains instructions to be fetched The SS register points to the current stack segment which is used for all stack operations The DS register points to the current data segment which generally contains program variables The ES register points to the current extra segment which is typically used for data storage The CS register initializes to OFFFFH and the SS DS and ES registers initialize to 0000H Programs can access and manipulate the segment registers with several instructions OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE intel 15 0 CS Code Segment DS Data Segment SS Stack Segment ES Extra Segment Figure 2 4 Segment Registers 2 1 5 Instruction Pointer The Bus Interface Unit updates the 16 bit Instruction Pointer IP register so it contains the offset of the next instruction to be fetched Programs do not have direct access to the Instruction Pointer but it can change be saved or be restored as a result of program execution For example if the Instruction Pointer is saved on the stack it is first automatically adjusted to point to the next in struction to be executed
189. dy to fetch an instruction byte the Execution Unit waits for the Bus Interface Unit to fetch the instruction byte 21 2 Bus Interface Unit The 80C186 Modular Core and 80C188 Modular Core Bus Interface Units are functionally iden tical They are implemented differently to match the structure and performance characteristics of their respective system buses The Bus Interface Unit executes all external bus cycles This unit consists of the segment registers the Instruction Pointer the instruction code queue and several miscellaneous registers The Bus Interface Unit transfers data to and from the Execution Unit on the ALU data bus The Bus Interface Unit generates a 20 bit physical address in a dedicated adder The adder shifts a 16 bit segment value left 4 bits and then adds a 16 bit offset This offset is derived from com binations of the pointer registers the Instruction Pointer and immediate values see Figure 2 2 Any carry from this addition is ignored Segment Base Logical Address Offset To Memory A1500 0A Figure 2 2 Physical Address Generation 2 3 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel During periods when the Execution Unit is busy executing instructions the Bus Interface Unit sequentially prefetches instructions from memory As long as the prefetch queue is partially full the Execution Unit fetches instructions 2 1 3 General Registers The 80C186 Modular Core family CPU has eight 16 bit genera
190. e 1 1 1 Idle passive 3 12 intel BUS INTERFACE UNIT 3 4 2 Data Phase Figure 3 12 shows the timing relationships for the data phase of a bus cycle The only bus cycle type that does not have a data phase is a bus halt During the data phase the bus transfers infor mation between the internal units and the memory or peripheral device selected during the ad dress status phase Appropriate control signals become active to coordinate the transfer of data The data phase begins at phase 1 of T2 and continues until phase 2 of T4 or TI The length of the data phase varies depending on the number of wait states Wait states occur after T3 and before T4 or TI 3 4 3 Wait States Wait states extend the data phase of the bus cycle Memory and I O devices that cannot provide or accept data in the minimum four CPU clocks require wait states Figure 3 13 shows a typical bus cycle with wait states inserted The READY input and the Chip Select Unit control bus cycle wait states Only the READY input is described in this chapter See Chapter 6 Chip Select Unit for additional information Figure 3 14 shows a simplified block diagram of the READY input To avoid wait states READY must be active high within a specified setup time prior to phase 2 of T2 To insert wait states READY must be inactive low within a specified setup time to phase 2 of T2 or phase 1 of T3 Depending on the size and characteristics of the system ready
191. e 12 16 exceptions 12 13 I O port assignments 12 10 initialization example 12 13 12 16 instruction set 12 2 interface 12 7 12 13 and chip selects 6 14 12 11 and PCB location 4 7 exception trapping 12 13 generating READY 12 11 processor control instructions 12 6 testing for presence 12 10 transcendental instructions 12 5 8259A Programmable Interrupt Controllers 8 1 and special fully nested mode 8 8 cascading 8 7 8 8 interrupt type 8 9 priority structure 8 8 82C59A Programmable Interrupt Controller interfacing with 3 25 3 27 A Address and data bus 3 1 3 6 16 bit 3 1 3 5 considerations 3 7 8 bit 3 5 3 6 considerations 3 7 See also Bus cycles Data transfers Address bus See Address and data bus Address space See Memory space I O space Addressing modes 2 27 2 36 and string instructions 2 34 based 2 30 2 31 2 32 INDEX based index 2 34 2 35 direct 2 29 immediate operands 2 28 indexed 2 32 2 33 indirect 2 36 memory operands 2 28 register indirect 2 30 2 31 register operands 2 27 AH register 2 5 AL register 2 5 2 18 2 23 ApBUILDER files obtaining from BBS 1 6 Application BBS 1 5 Architecture CPU block diagram 2 2 device feature comparisons 1 2 family introduction 1 1 overview 1 1 2 1 Arithmetic instructions 2 19 2 20 interpretation of 8 bit numbers 2 20 Arithmetic Logic Unit ALU 2 1 Array bounds trap Type 5 exception 2 44 ASCII defined 2 37 Asynchronou
192. e CPU each has its own vector location and internal priority Timer 0 has the highest interrupt priority and Timer 2 has the lowest Timer Interrupts are enabled or disabled by the Interrupt INT bit in the Timer Control register If enabled an interrupt is generated every time a maximum count value is reached In dual max imum count mode an interrupt is generated each time the value in Maxcount Compare A or Max count Compare B is reached If the interrupt is disabled after a request has been generated but before a pending interrupt is serviced the interrupt request remains active the Interrupt Control ler latches the request If a timer generates a second interrupt request before the CPU services the first interrupt request the first request is lost 9 2 7 Programming Considerations Timer registers can be read or written whether the timer is operating or not Since processor ac cesses to timer registers are synchronized with counter element accesses a half modified count register will never be read When Timer 0 and Timer use an internal clock source the input pin must be high to enable counting 9 3 TIMING Certain timing considerations need to be made with the Timer Counter Unit These include input setup and hold times synchronization and operating frequency 9 3 1 Input Setup and Hold Timings To ensure recognition setup and hold times must be met with respect to CPU clock edges The timer input signal must be valid Tc
193. e SINTI output 10 4 1 Channel 0 Interrupts Figure 10 18 illustrates the channel 0 interrupt circuitry Channel 0 receptions assert an internal signal Receive Interrupt Request 0 This signal is routed both to the Interrupt Control Unit and to the SOSTS register where it sets the RI bit The RI bit has no effect on the internal interrupt request Writing to RI does not cause an interrupt and setting it does not prevent interrupts Channel 0 transmissions assert an internal signal Transmit Interrupt Request 0 Like the Receive Interrupt Request 0 signal this signal is routed to the Interrupt Control Unit and to the SOSTS register This signal sets the TI bit in SOSTS Like the RI bit TI has no effect on the in ternal interrupt request Writing to TI does not cause an interrupt and setting it does not prevent interrupts 10 4 2 Channel 1 Interrupts Figure 10 18 illustrates the channel 1 interrupt circuitry Channel 1 receptions assert an internal Receive Interrupt Request 1 signal and transmissions assert an internal Transmit Interrupt Request 1 signal Serial channel 1 is supported by the SINT1 output Each internal signal is routed to SISTS register where it sets the RI or TI bit The RI and TI bits are ORed into the SINTI signal so setting either bit asserts SINT1 Reading S1STS clears the RI and TI bits and deasserts SINTI This is the only method available for deasserting SINT1 10 21 SERIAL COMMUNICATIONS UNIT inte
194. e count can be specified as an immediate value or as a variable in the CL register This allows the shift count to be a supplied at execution time Arithmetic shifts can be used to multiply and divide bi nary numbers by powers of two Logical shifts can be used to isolate bits in bytes or words 2 21 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Individual bits in bytes and words can also be rotated The processor does not discard the bits ro tated out of an operand The bits circle back to the other end of the operand The number of bits to be rotated is taken from the count operand which can specify either an immediate value or the CL register The carry flag can act as an extension of the operand in two of the rotate instructions This allows a bit to be isolated in the Carry Flag CF and then tested by a JC jump if carry or JNC jump if not carry instruction 2 2 1 4 String Instructions Five basic string operations process strings of bytes or words one element byte or word at a time Strings of up to 64 Kbytes can be manipulated with these instructions Instructions are avail able to move compare or scan for a value as well as to move string elements to and from the accumulator Table 2 7 lists the string instructions These basic operations can be preceded by a one byte prefix that causes the instruction to be repeated by the hardware allowing long strings to be processed much faster than is possible with a software loop The
195. e flags are stored in the format used by the PUSHF instruction SP is decremented again by two and the CS register is pushed onto the stack The address of the interrupt pointer is calculated by multiplying interrupt type by four the second word of the interrupt pointer replaces CS SP again is decremented by two and IP is pushed onto the stack and is replaced by the first word of the interrupt pointer If interrupt type 3 the assembler generates a short 1 byte form of the instruction known as the breakpoint interrupt Instruction Operands INT immed8 SP 2 SP FLAGS T 80 T lt SP 2 e SP 2 SP 1 SP lt IP lt interrupt type x 4 AF CF DF IF v OF PF SF TF Y ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed INSTRUCTION SET DESCRIPTIONS intel Table C 4 Instruction Set Continued Name Description Operation foe d INTO Interrupt on Overflow if AF then DF Generates a software interrupt if the SP SP 2 IF overflow flag OF is set otherwise SP 1 SP FLAGS OF control proceeds to the following IF 0 instruction without activating
196. e interrupt capabilities be yond a single input It receives and processes maskable interrupts from multiple sources and pre sents them to the CPU through the maskable interrupt input Interrupts can originate from the on chip peripherals and from five external interrupt pins The Interrupt Control Unit synchronizes and prioritizes the interrupts and provides the interrupt type vector to the CPU See Figure 8 1 The Interrupt Control Unit has the following features Programmable priority of each interrupt source Individual masking of each interrupt source Nesting of interrupt sources Support for polled operation Support for cascading external 8259A modules to expand external interrupt sources 8 1 FUNCTIONAL OVERVIEW All microcomputer systems must communicate in some way with the external world A typical system might have a keyboard a disk drive and a communications port all requiring CPU atten tion at different times There are two distinct ways to process peripheral I O requests polling and interrupts Polling requires that the CPU check each peripheral device in the system periodically to see whether it requires servicing It would not be unusual to poll a low speed peripheral a serial port for instance thousands of times before it required servicing In most cases the use of polling has a detrimental effect on system throughput Any time used to check the peripherals is time spent away from the main processing tasks
197. e logic units Asynchronous Synchronized Input Output NOTES 1 First latch sample clock can be phase 1 or phase 2 depending on pin function 2 Second latch sample clock opposite phase of first latch sample clock e g if first latch is sampled with phase 1 the second latch is sampled with phase 2 A1007 0A Figure B 1 Input Synchronization Circuit B 1 WHY SYNCHRONIZERS ARE REQUIRED Every data latch requires a specific setup and hold time to operate properly The duration of the setup and hold time defines a window during which the device attempts to latch the data If the input makes a transition within this window the output may not attain a stable state The data sheet specifies a setup and hold window larger than is actually required However variations in device operation e g temperature voltage require that a larger window be specified to cover all conditions Should the input to the data latch make a transition during the sample and hold window the out put of the latch eventually attains a stable state This stable state must be attained before the sec ond stage of synchronization requires a valid input To synchronize an asynchronous signal the circuit in Figure B 1 samples the input into the first latch allows the output to stabilize then sam ples the stabilized value into a second latch With the asynchronous signal resolved in this way the input signal cannot cause an internal device failure B 1 INPUT
198. e used to access data in any other currently ad dressable segment 2 1 9 Dynamically Relocatable Code The segmented memory structure of the 80C186 Modular Core family allows creation of dynam ically relocatable position independent programs Dynamic relocation allows a multiprogram ming or multitasking system to make effective use of available memory The processor can write inactive programs to a disk and reallocate the space they occupied to other programs A disk res ident program can then be read back into available memory locations and restarted whenever it is needed If a program needs a large contiguous block of storage and the total amount is available only in non adjacent fragments other program segments can be compacted to free enough con tinuous space This process is illustrated in Figure 2 9 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Before After Relocation Relocation Code Segment Stack Segment I Data Segment Segment Stack Segment Data Segment Extra Extra Segment Segment A1039 0A Figure 2 9 Dynamic Code Relocation To be dynamically relocatable a program must not load or alter its segment registers and must not transfer directly to a location outside the current code segment All program offsets must be relative to the segment registers This allows the program to be moved anywhere in memory pro vided that the segment registers are updated to point to the new base addresses 2
199. ead For example assume a character is received with a parity error PE set and a subsequent error free character is received If the SxSTS register was not read be tween the two receptions the PE bit remains set 10 2 2 2 Modes 2 and 3 for Multiprocessor Communications Programming for multiprocessor communications is much the same as the stand alone operation The only added complexity is that the ninth data bit must be controlled and interpreted correctly The ninth data bit is set for transmissions by setting TB8 bit in SxCON TB8 is cleared after every transmission TB8 is not double buffered This is usually not a problem as very few bytes are actually transmitted with TB8 equal to one When writing TB8 make sure that the other bits in SxCON are written with their appropriate value In Modes 2 and 3 the state of the ninth data bit can be determined by the RB8 bit in SXSTS RB8 reflects the ninth bit for the character currently in SXRBUF Note that the RB8 bit shares func tionality with the PE bit in SxSTS When parity is enabled the PE bit has precedence over RB8 10 2 2 3 Sending and Receiving a Break Character The serial port can send as well as receive BREAK characters A BREAK character is a long string of zeros To send a BREAK character set the SBRK bit in SxCON SBRK drives the TXD pin immediately low regardless of the current serial port mode The user controls the length of the BREAK character in software by control
200. eeeeeeseeeeeeeseaeeseeeenaeeseeeeeeeteas 5 2 Crystal Connections to Microprocessor sssssesssseeeeeeneneenneen nennen 5 3 Equations for Crystal Calculations nennen 5 4 Simple RC Circuit for Powerup Reset nennen 5 7 Cold Reset Wavelfotim iem tette eo REP E RE RENTUR 5 8 Warm Reset Waveform uie cet tette cie upto pne o ld nears tere FR 5 9 Clock Synchronization at Reset enne 5 10 Power Control Register sese eene enne 5 12 Entering Idle Mode 5 Errem eter cds eed 5 13 HOLD HLDA During Idle Mode esee nnne nnns 5 14 Entering Powerdown Mode ssssseeeeeen eem nennen nennen 5 17 Powerdown Timer GI CU ccce be cio Er uc re eee 5 18 Common Chip Select Generation Methods sseeeeeneeee 6 2 Chip Select Block Diagram sees nnne enne 6 3 Chip Select Relative Timings 6 4 CS Reset Configuratiori eee ete 6 5 START Register Definition essent nnne nnne nnns 6 7 STOP Register 6 8 Wait State and Ready Control Functions sess 6 12 Overlapping Chip Selects ce ceccsesceeeeeceseeeseeesaeeseeeeeeeesseeceaeesaeesaeeeaeeseaeeseaeeeeeeaas 6 13 xi SUENE intel Figure 6 9 6 10 6 11 7 1 7 2 7 4 7 5 7 7 7
201. efore IF dividing two valid unpacked decimal OF operands so that the quotient PF F produced by the division will be a valid SF v unpacked decimal number AH must be zero for the subsequent DIV to ZF v produce the correct result The quotient is returned in AL and the remainder is returned in AH both high order half bytes are zeroed Instruction Operands none AAM ASCII Adjust for Multiply AH lt AL OAH AF AAM AL lt AL OAH SE Corrects the result of a previous multi IE plication of two valid unpacked b decimal operands A valid 2 digit OF 7 unpacked decimal number is derived PF from the content of AH and AL and is SF v returned to AH and AL The high order TF half bytes of the multiplied operands ZF must have been OH for AAM to produce a correct result Instruction Operands none NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued Name Description Operation AAS ASCII Adjust for Subtraction if AF Y AAS AL and OFH 9 or AF 2 1 CF v then DF Corrects the result of a previous AL lt AL 6 IF subtraction of two valid u
202. egister Mnemonic EOI Register Function Used to issue an EOI command A1210 A0 Bit f Bit Nam Function Mnemonic iframe unctio NSPEC Nonspecific Set to issue a nonspecific EOI EOI VT4 0 Interrupt 00000 Write with the interrupt type of the interrupt Type whose In Service bit is to be cleared NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 13 End of Interrupt Register 8 3 8 Interrupt Status Register The Interrupt Status register Figure 8 14 contains one bit for each interrupt that shares an inter rupt source and one bit for the nonmaskable interrupt NMI A bit is set to indicate a pending interrupt and is cleared when the interrupt request is acknowledged Any number of bits can be set at any one time 8 22 intel INTERRUPT CONTROL UNIT Register Name Interrupt Status Register Register Mnemonic INTSTS Register Function Indicates pending NMI or shared source interrupts 1 5 N M A1205 A0 Bit Bit Nam Function Mnemonic trame unctio NMI Non This bit is set to indicate a pending NMI maskable Interrupt STX Serial This bit is set to indicate a pending serial Transmit transmit interrupt SRX Serial This bit is set to indicate a pending serial Receive receive interrupt TMR2 0 Timer A bit is set to indicate a pending interrupt from t
203. egisters AL and AH TF 0 ZF The byte quotient is returned in AL SP SP 2 and the byte remainder is returned in SP 1 5 lt CS CS lt 2 If the source operand is a word it is SP lt SP 2 divided into the two word dividend in SP 1 SP IP registers AX and DX The word IP lt 0 quotient is returned in AX and the else word remainder is returned in DX AL lt temp AX If the quotient exceeds the capacity of AH lt temp AX its destination register FFH for byte When Source Operand is a Word source FFFFH for word source as temp lt word src when division by zero is attempted a if type 0 interrupt is generated and the temp DX AX FFFFH quotient and remainder are undefined then type 0 interrupt is generated Nonintegral quotients are truncated to SP lt SP integers SP 105 lt FLAGS Instruction Operands IF lt DIV reg TF o DIV mem SP SP SP 1 ee CS CS lt 2 SP lt SP SP 1 Pec IP IP lt 0 else lt temp DX AX DX lt temp DX AX NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 13 INSTRUCTION SET DESCRIPTIONS Table C 4 Instructi
204. el 1 Procedure A Lexical Level 2 Procedure B Lexical Level 3 Procedure C Lexical Level 3 Procedure D Lexical Level 4 A1001 0A Figure A 2 Variable Access in Nested Procedures The first ENTER executed in the Main Program allocates dynamic storage space for Main but no pointers are copied The only word in the display points to itself because no previous value exists to return to after LEAVE is executed see Figure A 3 Display Main Dynamic Storage Main BPM BP Value for MAIN A1002 0A Figure A 3 Stack Frame for Main at Level 1 After Main calls Procedure A ENTER creates a new display for Procedure A The first word points to the previous value of BP BPM The second word points to the current value of BP BPA BPM contains the base for dynamic storage in Main All dynamic variables for Main will be at a fixed offset from this value see Figure A 4 A 4 intel 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Display A Dynamic Storage A BPA BP Value for Procedure A A1003 0A Figure A 4 Stack Frame for Procedure A at Level 2 After Procedure A calls Procedure B ENTER creates the display for Procedure B The first word of the display points to the previous value of BP BPA The second word points to the value of BP for MAIN BPM The third word points to the BP for Procedure A BPA The last word points to the current BP BPB Procedure B can access variables in Procedure
205. emory by Count 1100000w modTTTr m count 5 n 17 n STRING MANIPULATION INSTRUCTIONS MOVS Move byte word 1010010w 14 INS Input byte word from DX port 0110110w 14 OUTS Output byte word to DX port 0110111w 14 CMPS Compare byte word 1010011w 22 SCAS Scan byte word 1010111w 15 STRING MANIPULATION INSTRUCTIONS Continued LODS Load byte word to AL AX 1010110w 12 STOS Store byte word from AL AX 1010101w 10 Repeated by count in CX MOVS Move byte word 11110010 1010010w 8 8n INS Input byte word from DX port 11110010 0110110w 8 8n OUTS Output byte word to DX port 11110010 0110111w 848n CMPS Compare byte word 11110012 1010011w 5422n SCAS Scan byte word 11110012 1010111w 5 15 LODS Load byte word to AL AX 11110010 0101001w 6 11n STOS Store byte word from AL AX 11110100 0101001w 6 9n NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the 8086 8088 instruction set See Appendix 80C 186 Instruction Set Additions and Extensions for details intel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 2 Instruction Set Summary Continued Function Format Clocks Notes PROGRAM TRANSFER INSTRUCTIO
206. ency Vendors furnish third or higher overtone crystals to avoid manufacturing very thin fragile quartz crystal elements At a given frequency an overtone crystal is thicker and more rugged than its fundamental mode counterpart Below 20 MHz most crystals are fundamental mode In the 20 to 32 MHz range you can purchase both modes You must know the vibration mode to know whether to add the LC circuit at OSCOUT Equivalent Series Resistance ESR ESR is proportional to crystal thickness inversely proportional to frequency A lower value gives a faster startup time but the specification is usually not important in microprocessor applications Shunt Capacitance A lower value reduces ESR but typical values such as 7 pF will work fine Drive Level Specifies the maximum power dissipation for which the manufacturer calibrated the crystal It is proportional to ESR frequency load and Disregard this specification unless you use a third overtone crystal whose ESR and frequency will be relatively high Several crystal manufacturers stock a standard microprocessor crystal line Specifying a microprocessor grade crystal should ensure that the rated drive level is a couple of milliwatts with 5 volt operation Temperature Range Specifies an operating range over which the frequency will not vary beyond a stated limit Specify the temperature range to match the microprocessor temperature range Tolerance The allowable fr
207. equency deviation at a particular calibration temperature usually 25 C Quartz crystals are more accurate than microprocessor applications call for do not pay for a tighter specification than you need Vendors quote frequency tolerance in percentage or parts per million ppm Standard microprocessor crystals typically have a frequency tolerance of 0 01 100 ppm If you use these crystals you can usually disregard all the other specifications these crystals are ideal for the 80C186 Modular Core family 5 5 CLOCK GENERATION AND POWER MANAGEMENT intel An important consideration when using crystals is that the oscillator start correctly over the volt age and temperature ranges expected in operation Observe oscillator startup in the laboratory Varying the load capacitors within about 50 can optimize startup characteristics versus sta bility In your experiments consider stray capacitance and scope loading effects For help in selecting external oscillator components for unusual circumstances count on the crys tal manufacturer as your best resource Using low cost ceramic resonators in place of crystals is possible if your application will tolerate less precise frequencies 5 1 2 Using an External Oscillator The microprocessor s on board clock oscillator allows the use of a relatively low cost crystal However the designer may also use a canned oscillator or other external frequency source Connect the external frequency inp
208. er Register Mnemonic TOCNT T1CNT T2CNT Register Function Contains the current timer count A1299 0A Bit i Function Mnemonic Bit Name unctio TC15 0 Timer Count Contains the current count of the associated Value timer Figure 9 7 Timer Count Registers 9 10 intel TIMER COUNTER UNIT Register Name Timer Maxcount Compare Register Register Mnemonic TOCMPA TOCMPB T1CMPA T1CMPB T2CMPA Register Function Contains timer maximum count value A1300 0A Bit Mnemonic Bit Name Function TC15 0 Timer Contains the maximum value a timer will count Compare to before resetting its Count register to zero Value Figure 9 8 Timer Maxcount Compare Registers 9 2 1 Initialization Sequence When initializing the Timer Counter Unit the following sequence is suggested 1 timer interrupts will be used program interrupt vectors into the Interrupt Vector Table 2 Clear the Timer Count register This must be done before the timer is enabled because the count register is undefined at reset Clearing the count register ensures that counting begins at zero 3 Write the desired maximum count value to the Timer Maxcount Compare register For dual maximum count mode write a value to both Maxcount Compare A and B 4 Program the Timer Control register to enable the timer When using Timer 2 to prescale another timer enable Timer 2 last If Timer 2 is enabled first it will
209. er vice routine clears the Trap Flag bit An IRET instruction in the interrupt service routine restores the Trap Flag bit to logic 1 and transfers control to the next instruction to be single stepped 2 43 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Breakpoint Interrupt Type 3 The Breakpoint Interrupt is a single byte version of the INT instruction It is commonly used by software debuggers to set breakpoints in RAM Because the instruction is only one byte long it can substitute for any instruction Interrupt on Overflow Type 4 The Interrupt on Overflow trap occurs if the Overflow Flag OF bit is set in the Processor Status Word and the INTO instruction is executed Interrupt on Overflow is a common method for han dling arithmetic overflows conditionally Array Bounds Check Type 5 An Array Bounds trap occurs when the array index is outside the array bounds during execution of the BOUND instruction see Appendix A 80C186 Instruction Set Additions and Exten sions Invalid Opcode Type 6 Execution of an undefined opcode causes an Invalid Opcode trap Escape Opcode Type 7 The Escape Opcode fault is used for floating point emulation With 80C186 Modular Core family members this fault is enabled by setting the Escape Trap ET bit in the Relocation Register see Chapter 4 Peripheral Control Block When a floating point instruction is executed with the Escape Trap bit set the Escape Opcode fa
210. er the first low to high transition on the input pin If another low to high transition occurs before the end of the timer cycle the timer count resets to zero and the timer cycle begins again In dual maximum count mode the Register In Use RIU bit does not clear when a low to high transition occurs For example if the timer retriggers while Maxcount Compare B is in use the timer resets to zero and counts to maximum count B before the RIU bit clears In dual maximum count mode the timer retriggering extends the use of the current Maxcount Compare register 9 2 4 Pulsed and Variable Duty Cycle Output Timers 0 and 1 each have an output pin that can perform two functions First the output can be a single pulse indicating the end of a timing cycle single maximum count mode Second the out put can be a level indicating the Maxcount Compare register currently in use dual maximum count mode The output occurs one clock after the counter element services the timer when the maximum count is reached see Figure 9 9 With external clocking the time between a transition on a timer input and the corresponding tran sition of the timer output varies from 21 to 6 clocks This delay occurs due to the time multi plexed servicing scheme of the Timer Counter Unit The exact timing depends on when the input occurs relative to the counter element s servicing of the timer Figure 9 2 on page 9 3 shows the two extremes in timer output delay Timer 0 demon
211. es could require circuit changes to accommodate the additional memory 6 2 CHIP SELECT UNIT FEATURES AND BENEFITS The Chip Select Unit overcomes limitations of the designs shown in Figure 6 1 and has the fol lowing features Ten chip select outputs Programmable start and stop addresses Memory or I O bus cycle decoder Programmable wait state generator Provision to disable a chip select Provision to override bus ready Figure 6 2 illustrates the logic blocks that generate a chip select Each chip select has a duplicate set of logic 6 1 CHIP SELECT UNIT intel 27C256 74AC138 Selects 896K to 1M Selects 768K to 896K Selects 128K to 256K Selects 0 to 128K Chip Selects Using Chip Selects Using Addresses Directly Simple Decoder A1168 0A Figure 6 1 Common Chip Select Generation Methods 6 3 CHIP SELECT UNIT FUNCTIONAL OVERVIEW The Chip Select Unit CSU decodes bus cycle address and status information and enables the appropriate chip select Figure 6 3 illustrates the timing of a chip select during a bus cycle Note that the chip select goes active in the same bus state as address goes active eliminating any delay through address latches and decoder circuits The Chip Select Unit activates a chip select for bus cycles initiated by the CPU or Refresh Control Unit Any of the ten chip selects can map into either memory or I O address space A memory mapped chip select can start and end on any 1 Kbyte addre
212. et config rcu endp lib 80186 ends end Example 7 1 Initializing the Refresh Control Unit Continued 7 8 REFRESH OPERATION AND BUS HOLD When another bus master controls the bus the processor keeps HLDA active as long as the HOLD input remains active If the Refresh Control Unit generates a refresh request during bus hold the processor drives the HLDA signal inactive indicating to the current bus master that it wishes to regain bus control see Figure 7 10 The BIU begins a refresh bus cycle only after the alternate master removes HOLD The user must design the system so that the processor can re gain bus control If the alternate master asserts HOLD after the processor starts the refresh cycle the CPU will relinquish control by asserting HLDA when the refresh cycle is complete 7 13 REFRESH CONTROL UNIT intel CLKOUT HLDA is deasserted signaling need to run DRAM refresh cycles less than ToLoy External bus master terminates use of the bus HOLD deasserted greater than Tc Hold may be reasserted after one clock Lines come out of float in order to run DRAM refresh cycle A1269 0A Figure 7 10 Regaining Bus Control to Run a DRAM Refresh Bus Cycle 7 14 intel Interrupt Control Unit intel CHAPTER 8 INTERRUPT CONTROL UNIT The 80C186 Modular Core has a single maskable interrupt input See Interrupts and Exception Handling on page 2 39 The Interrupt Control Unit ICU expands th
213. et See Appendix A 80C 186 Instruction Set Additions and Extensions for details INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 2 Instruction Set Summary Continued Function Format Clocks Notes ARITHMETIC INSTRUCTIONS Continued SUB Subtract reg memory with register to either 001010dw mod reg r m 3 10 immediate from register memory 100000sw mod 101 r m data data if sw 01 4 16 immediate from accumulator 0001110w data data if w 1 3 4 1 SBB Subtract with borrow reg memory with register to either 000110dw mod reg r m 3 10 immediate from register memory 100000sw mod 011 r m data data if sw 01 4 16 immediate from accumulator 0001110w data data if w 1 3 4 1 DEC Decrement register memory 1111111w mod 001 r m 3 15 register 01001 reg 3 NEG Change sign 1111011w mod reg r m 3 CMP Compare register memory with register 0011101w mod reg r m 3 10 register with register memory 0011100w mod reg r m 3 10 immediate with register memory 100000sw mod 111 r m data data if sw 01 3 10 immediate with accumulator 0011110w data data if w 1 3 4 1 AAS ASCIl adjust for subtraction 00111111 7 DAS Decimal adjust for subtraction 00101111 4 MUL multiply unsigned 1111011w mod 100 r m register byte 26 28 register word 35 37 memory byte 32 34 memory word 41 43 IMUL Integer multiply signed 1111011w mod 101 r m register b
214. et space time Clear Timer 1 Counter start Timer 1 Example 9 2 Configuring a Square Wave Generator 9 21 TIMER COUNTER UNIT intel pop dx restore saved registers pop bx pop ax pop bp restore caller s bp ret clock endp lib 80186 ends end Example 9 2 Configuring a Square Wave Generator Continued mod186 name example timerl 1 shot code FUNCTION This function generates an active low one shot pulse on Timer 1 output pin SYNTAX extern void far one shot int CMPB INPUTS CMPB This is the TICMPB value required to generate a pulse of a given pulse width This value is calculated from the formula below CMPB req pulse width f 4 OUTPUTS None NOTE Parameters are passed on the stack as required by high level languages equ xxxxH substitute register offsets equ xxxxH equ xxxxH T1CON equ xxxxH MaxCount equ 0020H lib 80186 segment public code assume cs lib 80186 public one shot one shot proc far push bp Save caller s bp mov bp sp get current top of stack Example 9 3 Configuring a Digital One Shot 9 22 _CMPB push push mov xor out mov mov out mov mov out mov mov out CountDown test jz and out pop pop pop ret one shot lib 80186 end equ word 6 ax dx dx LCNT ax ax dx 1 dx LCMPA ax dx 1 dx CMPB ax CMPB dx al dx T1CON ax C002H dx al in ax dx
215. external interrupt pin SER Serial This bit is set to indicate a pending interrupt Channel 0 from serial channel 0 either a receive or a Interrupt transmit interrupt TMR Timer This bit is set to indicate a pending interrupt Interrupt from one of the timers NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 7 Interrupt Request Register intel INTERRUPT CONTROL UNIT 8 3 3 Interrupt Mask Register The Interrupt Mask register Figure 8 8 contains a mask bit for each interrupt source This reg ister allows you to mask disable individual interrupts Set a mask bit to disable interrupts from the corresponding source The mask bit is the same as the one in the Interrupt Control register Modifying a bit in either register also modifies that same bit in the other register Register Name Interrupt Mask Register Register Mnemonic IMASK Register Function Masks individual interrupt sources A1207 A0 Bit Bit Nam Function Mnemonic Ename unctio INT3 0 INT4 External Set a bit to mask disable interrupt requests Interrupt from the corresponding external interrupt pin Mask Serial Set to mask disable interrupt requests from Channel 0 serial channel 0 Interrupt Mask Timer Set to mask disable interrupt requests from Interrupt the timers Mask
216. fic pin is set the 7 0 associated integrated peripheral controls both pin direction and pin data Clearing the PC bit makes the pin a general purpose l O port NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 11 5 Port Control Register PXCON 11 2 2 Port Direction Register The Port Direction Register Figure 11 6 controls the direction input or output for each pin pro grammed as a general purpose I O port The Port Direction bit has no effect on output only port pins These unused direction control bits can be used for bit storage The Port Direction Register is read write When read the register returns the value written to it previously Pins with their direction fixed return the value in this register not a value indicating their true direction The direction of a port pin assigned to a peripheral function is controlled by the peripheral the Port Direction value is ignored intel INPUT OUTPUT PORTS Register Name Port Direction Register Register Mnemonic PxDIR P1DIR P2DIR Register Function Controls the direction of pins programmed as ports Bit Mnemonic 0 A1313 0A Bit Name Function PD7 0 Port Setting the PD bit for a pin programmed as a Direction 7 0 general purpose I O port selects the pin as input Clearing the PD bit selects the pin as an output
217. g voltages and temper atures The oscillator starts up on the order of a couple of milliseconds After determining the os cillator startup time refer to PDTMR Pin Delay Calculation in the data sheet Multiply the startup time in seconds by the given constant to get the Cpp value Typical values are less than luF If the design uses an external oscillator instead of a crystal the external oscillator continues run ning during Powerdown mode Leave the PDTMR pin unconnected and the processor can exit Powerdown mode immediately 5 2 3 Implementing a Power Management Scheme Table 5 2 summarizes the power management options available to the user Overall power con sumption has two parts switching power dissipated by driving loads such as the address data bus and device power dissipated internally by the microprocessor whether or not it is connected to external devices A power management scheme should consider loading as well as the raw spec ifications in the processor s data sheet Table 5 2 Summary of Power Management Modes Mode Relative Typical User Chief Power Power Overhead Advantage Active Full 250 mW at 16 MHz Full speed operation Idle Low 175 mW at 16 MHz Low Peripherals are unaffected Powerdown Lowest 250 uW Low to Moderate Long battery life NOTE If an NMI or external maskable interrupt service routine is used to enter a power management mode the interrupt request signal should be deas
218. gister Function R C 8 Refresh Control Register RFCON Controls Refresh Unit operation A1311 0A Bit Mnemonic Bit Name Function REN Refresh Control Unit Enable Setting REN enables the Refresh Unit Clearing REN disables the Refresh Unit Refresh Counter These bits contain the present value of the down counter that triggers refresh requests The user cannot program these bits NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 7 8 Refresh Control Register 7 7 2 4 Refresh Address Register The Refresh Address Register Figure 7 9 contains address bits RA12 1 which will appear on the bus as A12 1 on the next refresh bus cycle Bit 0 is fixed as a one in the register and in all refresh addresses intel REFRESH CONTROL UNIT Register Name Refresh Address Register Register Mnemonic RFADDR Register Function Contains the generated refresh address bits 15 A1501 0A Bit E Function RA12 1 Refresh These bits comprise A12 1 of the refresh Address Bits address RAO Refresh Bit AO of the refresh address This bit is always 1 0 and is read only NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products
219. gister to get the type of the highest priority pending interrupt then calls the corresponding interrupt handler Reading the Poll register also acknowledges the interrupt This clears the Interrupt Request bit and sets the In Service bit for the interrupt The Poll Status register has the same format as the Poll register but reading the Poll Status register does not ac knowledge the interrupt 8 9 INTERRUPT CONTROL UNIT intel 8 2 6 Edge and Level Triggering The external interrupts INT4 0 can be programmed for either edge or level triggering see In terrupt Control Registers on page 8 12 Both types of triggering are active high An edge trig gered interrupt is generated by a zero to one transition on an external interrupt pin The pin must remain high until after the CPU acknowledges the interrupt then must go low to reset the edge detection circuitry See the current data sheet for timing requirements The edge detection cir cuitry must be reset to enable further interrupts to occur A level triggered interrupt is generated by a valid logic one on the external interrupt pin The pin must remain high until after the CPU acknowledges the interrupt Unlike edge triggered inter rupts level triggered interrupts will continue to occur if the pin remains high A level triggered external interrupt pin must go low before the EOI command to prevent another interrupt NOTE When external 8259As are cascaded into the Interrupt Cont
220. gram execution resumes The TEST input and WAIT instruction provide a mechanism to delay program execution until a hardware event occurs without having to absorb the delay associated with servicing an interrupt 3 6 3 Using a Locked Bus To address the problems of controlling accesses to shared resources the BIU provides a hardware LOCK output The execution of a LOCK prefix instruction activates the LOCK output LOCK goes active in phase 1 of T1 of the first bus cycle following execution of the LOCK prefix instruction It remains active until phase 1 of T1 of the first bus cycle following the execution of the instruction following the LOCK prefix To provide bus access control in multiprocessor sys tems the LOCK signal should be incorporated into the system bus arbitration logic residing in the CPU During normal multiprocessor system operation priority of the shared system bus is determined by the arbitration circuits on a cycle by cycle basis As each CPU requires a transfer over the sys tem bus it requests access to the bus via its resident bus arbitration logic When the CPU gains priority determined by the system bus arbitration scheme and any associated logic it takes con trol of the bus performs its bus cycle and either maintains bus control voluntarily releases the bus or is forced off the bus by the loss of priority The lock mechanism prevents the CPU from losing bus control either voluntarily or by force and guarantees
221. gue code to reduce arguments to a range accepted by the instruction Use epilogue code to adjust the result to the range of the original arguments The transcendentals operate on the top one or two stack elements and return their results to the stack Table 12 4 80C187 Transcendental Instructions FPTAN Partial tangent FPATAN Partial arctangent F2XM1 2x 1 FYL2X Y log X FYL2XP1 Y log X 1 FCOS Cosine FSIN Sine FSINCOS Sine and Cosine 12 5 MATH COPROCESSING intel 8 12 3 1 5 Constant Instructions Each constant instruction see Table 12 5 loads a commonly used constant onto the stack The values have full 80 bit precision and are accurate to about 19 decimal digits Since a temporary real constant occupies 10 memory bytes the constant instructions only 2 bytes long save mem ory space Table 12 5 80C187 Constant Instructions FLDZ Load 0 1 FLD1 Load 1 0 FLDPI Load FLDL2T Load log 10 FLDL2E Load log e FLDLG2 Load log 2 FLDLN2 Load log 2 12 3 1 6 Processor Control Instructions Computations do not use the processor control instructions these instructions are available for activities at the operating system level This group see Table 12 6 includes initialization excep tion handling and task switching instructions Table 12 6 80C187 Processor Control Instructions FINIT FNINIT Initialize processor FLDENV Load environment FDISI FNDISI Disable interrupts
222. hases If RESIN is sampled high while CLKOUT is low CLKOUT is already in phase 5 7 CLOCK GENERATION AND POWER MANAGEMENT intel Voc Ar Vec and CLKIN stable to valid CEAN pongas max a CLKOUT 4 AAPJYAYNY L N UCS LCS GC7 0 NPS TOOUT T1OUT TXD1 0 HLDA ALE SINT1 1 A114 l l l l l l 1 l 1 l l 1 l l l l l F l 1 l 1 AD15 0 S2 0 RD WR DEN4 DT R LOCK a Vec and CLKIN stable to RESET high to RESET high approximately first bus activity 32 CLKIN periods 7 CLKOUT periods NOTES 1 CLKOUT synchronization occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high solid line then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low dashed line the CLKOUT will not be affected A1134 0A Figure 5 6 Cold Reset Waveform 5 8 intel CLOCK GENERATION AND POWER MANAGEMENT CLKIN VAI DAD DDD DBR UCS LCS GCS7 0 ToT TOUT TXD1 0 NPS HLDA ALE i j a l 1 l 1 l 1 l l 1 l 1 9 l 1 1 C AD15 0 52 0 RD 1 l 1 l l 1 l WR DEN pre tt DT R RESIN UN E VA 2m RESOUT 1 a Minimum RESIN RESIN low time 4 CLKOUT high to periods first bus activity 7 CLKOUT periods A1133 0A Figure 5
223. he corresponding timer NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 14 Interrupt Status Register 8 3 9 Initializing the Interrupt Control Unit Follow these steps to initialize the Interrupt Control Unit 1 Determine which interrupt sources you want to use 2 Determine whether to use the default priority scheme or devise your own 8 23 INTERRUPT CONTROL UNIT intel 3 Program the Interrupt Control register for each interrupt source For external interrupt pins select edge or level triggering For INTO or INTI enable cascade mode special fully nested mode or both if you wish to use them If you are using a custom priority scheme program the priority level for each interrupt source 4 Program the Priority Mask with a priority mask level if you wish to mask interrupts based on priority The default is level seven which enables all interrupt levels 5 Setthe mask bit in the Interrupt Mask register for any interrupts that you wish to disable Example 8 1 shows sample code to initialize the Interrupt Control Unit mod186 name example 80C186 ICU initialization Ihis routine configures the interrupt controller to provide two cascaded interrupt inputs through an external 8259A connected to INTO and INTAO and two direct interrupt inputs connected to INT1 and INT3
224. he oscillator cold start guidelines see Reset and Clock Synchronization on page 5 6 The Powerdown timer circuit Figure 5 13 has a PDTMR pin Connecting this pin to an external capacitor gives the user control over the gating of the crystal oscillator to the internal clocks The strong P channel device is always on except during exit from Powerdown mode This pullup keeps the powerdown capacitor Cpp charged up to Cpp discharges slowly At the same time the circuit turns on the feedback inverter on the crystal oscillator and oscillation starts The Schmitt trigger connected to the PDTMR pin asserts the internal OSC_OK signal when the voltage at the pin drops below its switching threshold The OSC OK signal gates the crystal os cillator output to the internal clock circuitry One CLKOUT cycle runs before the internal clocks turn back on It takes two additional CLKOUT cycles for an NMI request to reach the CPU and another six clocks for the vector to be fetched Strong P Channel 0 Except when leaving Pullup Powerdown PDTMR Pin Weak N Channel C PE i Pulldown A1122 0A Figure 5 13 Powerdown Timer Circuit intel CLOCK GENERATION AND POWER MANAGEMENT The first step in determining the proper Cpp value is startup time characterization for the crystal oscillator circuit This step can be done with a storage oscilloscope if you compensate for scope probe loading effects Characterize startup over the full range of operatin
225. he pro cedure 8 bit value Note that the higher the lexical nesting level the lower the procedure is in the nesting hierarchy The lexical nesting level determines the number of pointers to higher level stack frames copied into the current stack frame This list of pointers is called the display The first word of the display points to the previous stack frame The display allows access to variables of higher level lower lexical nesting level procedures After ENTER creates a display for the current procedure it allocates dynamic storage space The Stack Pointer decrements by the number of bytes specified by size All PUSH and POP operations in the procedure use this value of the Stack Pointer as a base Two forms of ENTER exist non nested and nested A lexical nesting level of 0 specifies the non nested form In this situation BP is pushed then the Stack Pointer is copied to BP and decrement ed by the size of the frame If the lexical nesting level is greater than 0 the nested form is used Figure A 1 gives the formal definition of ENTER A 2 intel 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS The following listing gives the formal definition of the ENTER instruction for all cases LEVEL denotes the value of the second operand Push BP Set a temporary value FRAME PTR SP If LEVEL 0 then Repeat LEVEL 1 times BP BP 2 Push the word pointed to by BP End Repeat Push FRAME PTR End if BP FRAME PTR S
226. he signal is recognized CTS is not latched internally If CTS is asserted before a transmission starts the subsequent trans mission will not begin A write to SxTBUF arms the CTS sense circuitry 10 3 2 BCLK Pin Timings The BCLK pin can be configured as the input to the baud timebase clock The baud timebase clock increments the BxCNT register However the BCLK signal does not run directly into the baud timebase clock BCLK is first synchronized to the CPU clock Figure 10 16 The internal synchronization logic uses a low to high level transition on BCLK to generate the baud timebase clock that increments the BxCNT register The CPU recognizes a low to high transition by sam pling the BCLK pin low then high 10 18 intel SERIAL COMMUNICATIONS UNIT The CPU samples BCLK on the rising edge of CLKOUT The CLKOUT high time synchronizes the BCLK signal On the falling edge of CLKOUT the synchronized BCLK signal is presented to the baud timebase clock CTS Resolved During CLKOUT High Time CLKOUT CTS Internal 1279 0 Figure 10 15 CTS Recognition Sequence CLKOUT TCHIH gt TCHIH TCHIS lt lt TCHIS gt Increment BCNT Internal A1280 0A Figure 10 16 BCLK Synchronization 10 19 SERIAL COMMUNICATIONS UNIT intel BCLK is an asynchronous input However the pin does have setup and hold times which guar antee recognition at a specific CLKOUT If the
227. her seg ment by updating the segment register to point to the new segment 2 1 8 Logical Addresses It is useful to think of every memory location as having two kinds of addresses physical and log ical A physical address is a 20 bit value that identifies a unique byte location in the memory space Physical addresses range from to OFFFFFH All exchanges between the CPU and memory use physical addresses Programs deal with logical rather than physical addresses Program code can be developed with out prior knowledge of where the code will be located in memory A logical address consists of a segment base value and an offset value For any given memory location the segment base value locates the first byte of the segment The offset value represents the distance in bytes of the tar get location from the beginning of the segment Segment base and offset values are unsigned 16 bit quantities Many different logical addresses can map to the same physical location In Figure 2 8 physical memory location 2C3H is contained in two different overlapping segments one be ginning at 2BOH and the other at 2COH 2 10 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE FFFFFH A1037 0A Figure 2 7 Currently Addressable Segments The segment register is automatically selected according to the rules in Table 2 2 All information in one segment type generally shares the same logical attributes e g code or data This leads to programs
228. hi mov SEGREG reg16 mem16 mod 1 r m 8F 1000 1111 pop mem16 90 1001 0000 nop xchg AX AX 91 1001 0001 xchg AX CX 92 1001 0010 xchg AX DX 93 1001 0011 xchg AX BX 94 1001 0100 xchg AX SP 95 1001 0101 xchg 96 1001 0110 xchg AX SI 97 1001 0111 xchg AX DI 98 1001 1000 cbw 99 1001 1001 cwd 9A 1001 1010 disp lo disp hi seg lo seg hi call far proc 9B 1001 1011 wait 9C 1001 1100 pushf 9D 1001 1101 popf 9E 1001 1110 sahf 9F 1001 1111 lahf AO 10100000 addr lo addr hi mov AL mem8 A1 1010 0001 addr lo addr hi mov AX mem16 A2 1010 0010 addr lo addr hi mov mem8 AL 1010 0011 addr lo addr hi mov mem16 AL A4 1010 0100 movs dest str8 src str8 A5 1010 0101 movs dest str16 src str16 A6 1010 0110 cmps dest str8 src str8 A7 1010 0111 cmps dest str16 src str16 A8 1010 1000 data 8 test AL immed8 A9 1010 1001 data lo data hi test AX immed16 D 14 intel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 3 Machine Instruction Decoding Guide Continued RUE Byte 2 Bytes 3 6 ASM 86 Instruction Format Hex Binary AA 1010 1010 stos dest str8 AB 1010 1011 stos dest str16 AC 1010 1100 lods src str8 AD 1010 1101 lods src str16 AE 1010 1110 scas dest str8 AF 1010 1111 scas dest str16 1011 0000 data 8 mov AL immed8 B1 1011 0001 data 8 mov CL immed8 B2 1011 0010 data
229. ications mode Each frame consists of a start bit seven data bits and a stop bit as shown in Figure 10 6 Parity is not available in Mode 4 Both the RX and TX machines use this frame in Mode 4 with no exceptions E MO Su dg Ur up E cans eth Bie S9 cop 1041 1 1 1 1 1 1 1 1 1 1 TXD Stop RXD Bit 1 1285 0 Figure 10 4 Mode 1 Waveform intel SERIAL COMMUNICATIONS UNIT A1287 0A Figure 10 6 Mode 4 Waveform 10 1 1 4 2 Asynchronous Mode 2 is referred to as the address recognition mode Mode 2 is used together with Mode 3 for multiprocessor communications over a common serial link In Mode 2 the RX machine will not complete a reception unless the ninth data bit is a one Any character received with the ninth bit equal to zero is ignored No flags are set no interrupts occur and no data is transferred to SXRBUF In Mode 3 characters are received regardless of the state of the ninth data bit The following is brief example of using Modes 2 and 3 See Master Slave Example on page 10 27 for more information Assume one master serial port connects to multiple slave serial ports over a serial link The slaves are initially in Mode 2 and the master is always in Mode 3 The master communicates with one slave at a time The CPU overhead of the serial communications burdens only the master and the target slave device 1 The master transmits the
230. icitly along with the instruction mnemonic Still other instructions accept one explicit operand and one implicit operand usually the top stack element As with the basic non numerics instruction set there are two types of operands for coprocessor instructions source and destination Instruction execution does not alter a source operand Even when an instruction converts the source operand from one format to another for example real to integer the coprocessor performs the conversion in a work area to preserve the source operand A destination operand differs from a source operand because the 80C187 can alter the register when it receives the result of the operation For most destination operands the coprocessor usu ally replaces the destinations with results 12 2 intel MATH COPROCESSING 12 3 1 1 Data Transfer Instructions Data transfer instructions move operands between elements of the 80C187 register stack or be tween stack top and memory Instructions can convert any data type to temporary real and load it onto the stack in a single operation Conversely instructions can convert a temporary real oper and on the stack to any data type and store it to memory in a single operation Table 12 1 sum marizes the data transfer instructions Table 12 1 80C187 Data Transfer Instructions Real Transfers FLD Load real FST Store real FSTP Store real and pop FXCH Exchange registers Integer Transfers FILD Integer
231. ields both sine and cosine in one operation 12 18 MATH COPROCESSING intel 80C186 Modular Core ERROR CLK NPWR NPRD 80C187 NPS1 CKM PEREQ BUSY ERROR RESET A1256 01 Figure 12 4 80C187 Exception Trapping via Processor Interrupt Pin 12 14 intel MATH COPROCESSING mod186 name example 80C187 init FUNCTION This function initializes the 80C187 numerics coprocessor r SYNTAX extern unsigned char far 187_init void INPUTS None OUTPUTS unsigned char 0000h gt False gt coprocessor not initialized ffffh gt True gt coprocessor initialized NOTE Parameters are passed on the stack as required by high level languages lib 80186 segment public code assume cs lib 80186 public 187 init 187 initproc far push bp Save caller s bp mov bp sp get current top of stack cli disable maskable interrupts fninit init 80C187 processor fnstcw get current control word sti enable interrupts mov and mask off unwanted control bits cmp bits 11 je yes processor ok xor return false 80C187 not ok pop restore caller s bp ret and bp 2 Offfeh unmask possible exceptions fldcw bp 2 mov ax 0ffffh return true 80C187 ok pop bp restore caller s bp ret 187 initendp lib 80186ends end Example 12 1 Initialization Sequence for 80C187 Math Coprocessor 12 15 MATH COPROCESSING intel 8 mod186 modc1
232. ified mov dx Get state of port 1 controls in ax and ax make sure P1 0 3 is port out dx mov dx Set Port 2 1 for TXD1 P2 0 RXD1 mov ax out dx Example 10 4 Master Slave The select slave Routine 10 30 dx ax dx dx dx Slave dx al dx S dx ax COM xS dx S1STS Check 4 RI ex NoTimeOut ax ax SERIAL COMMUNICATIONS UNIT clear any pending exceptions prepare to send address d9 1 mode 3 select slave addr get slave address send it 7set REN enable receiver reset time out counter check to see if data is waiting decrement time out counter time out false then continue time out true set return value false 0 short SlaveExit NoTimeOut 1 ax dx ax 0040h Check 4 RI dx SIRBUF ax dx ax Offh _slave_ SlaveExit _select_slave lib 80186 test for RI bit keep checking till data received get slave response mask off unwanted bits addr did addressed slave respond ax 0 true else false invert state of ax to be consistent with false 0 and true non zero restore saved registers restore caller s bp Example 10 4 Master Slave The select slave Routine Continued 10 31 SERIAL COMMUNICATIONS UNIT intel mod186 name example slave 1 routine RAR scu eese eoru espere ens s icai a Slave 1 FUNCTION This function represents a slave unit connected to a multi
233. ightly different from that for the other port types When the open drain port pin is configured as an output clearing the Port Data latch turns on the N channel driver resulting in a hard zero being present at the pin A one value in the Port Data Latch shuts off the driver resulting in a high impedance input state at the pin The open drain pin can be floated directly by setting its Port Direction bit The open drain ports are not multiplexed with on board peripherals The port peripheral data multiplexer exists for open drain ports even though the pins are not shared with peripheral func tions The open drain port pin floats if the Port Control latch is programmed to select the non existent peripheral function 11 1 5 Port Pin Organization The port pins are organized as two functional groups Port 1 and Port 2 Port 1 consists of eight output only pins Port 2 has one bidirectional two output only three input only and two open drain bidirectional pins Most of the port pins are multiplexed with peripheral functions 11 3 INPUT OUTPUT PORTS intel 8 From Integrated Port Peripheral Peripheral Data Multiplexer Read Port Output Driver Data Latch E Permanently Disabled C T Write Port Data Latch Read Port Pin State Port Data Latch Read Port Direction Control Internal Data Bus F Bus Write Port Direction Read Port Direction Write Port Control To Integrated Peripheral Port Control
234. igned binary Signed binary integers Unsigned packed decimal Unsigned unpacked decimal 2 19 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Table 2 5 shows the interpretations of various bit patterns according to number type Binary num bers can be 8 or 16 bits long Decimal numbers are stored in bytes two digits per byte for packed decimal and one digit per byte for unpacked decimal The processor assumes that the operands in arithmetic instructions contain data that represents valid numbers for that instruction Invalid data may produce unpredictable results The Execution Unit analyzes the results of arithmetic instruc tions and adjusts status flags accordingly Table 2 4 Arithmetic Instructions Addition ADD Add byte or word ADC Add byte or word with carry INC Increment byte or word by 1 AAA ASCII adjust for addition DAA Decimal adjust for addition Subtraction SUB Subtract byte or word SBB Subtract byte or word with borrow DEC Decrement byte or word by 1 NEG Negate byte or word CMP Compare byte or word AAS ASCII adjust for subtraction DAS Decimal adjust for subtraction Multiplication MUL Multiply byte or word unsigned IMUL Integer multiply byte or word AAM ASCII adjust for multiplication Division DIV Divide byte or word unsigned IDIV Integer divide byte or word AAD ASCII adjust for division CBW Convert byte to word CWD Convert word to double word 2 20
235. ine where to return when the procedure finishes Note that the RET and CALL instruc tions must be the same type This can be a problem when the CALL and RET instructions are in separately assembled programs The JMP instruction does not push any information onto the stack A JMP instruction can be NEAR or FAR Conditional transfer instructions are jumps that may or may not transfer control depending on the state of the CPU flags when the instruction is executed Each conditional transfer instruction tests a different combination of flags for a condition see Table 2 10 If the condition is logically TRUE control is transferred to the target specified in the instruction If the condition is FALSE control passes to the instruction following the conditional jump All conditional jumps are SHORT The target must be in the current code segment within 128 to 127 bytes of the next instruction s first byte For example JMP 00H causes a jump to the first byte of the next instruc tion Jumps are made by adding the relative displacement of the target to the Instruction Pointer All conditional jumps are self relative and are appropriate for position independent routines 2 24 Table 2 9 Program Transfer Instructions Conditional Transfers JA JNBE Jump if above not below nor equal JAE JNB Jump if above or equal not below JB JNAE Jump if below not above nor equal JBE JNA Jump if below or equal not above JC Jump if carry
236. ing Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 6 5 START Register Definition CHIP SELECT UNIT intel Register Name Chip Select Stop Register Register Mnemonic UCSSP LCSSP GCSxSP x 0 7 Register Function Defines chip select stop address and other control functions A1164 0A Bit Mnemonic Bit Name Function CS9 0 Stop Defines the ending address for the chip select Address CS9 0 are compared with the A19 10 memory bus cycles or A15 6 I O bus cycles address bits A less than result enables the chip select CS9 0 are ignored if ISTOP is set Chip Select Disables the chip select when cleared Setting Enable CSEN enables the chip select Ignore Stop Setting this bit disables stop address checking Address which automatically sets the ending address at OFFFFFH memory or OFFFFH I O When ISTOP is cleared the stop address require ments must be met to enable the chip select NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products The reset state of CSEN and ISTOP is 1 for the UCSSP register Figure 6 6 STOP Register Definition intel CHIP SELECT UNIT Register Name Chip Select Stop Register Register Mnemonic UCSSP LCSSP GCSxSP x 0 7 Register Function Defines chip select stop address and other control fu
237. instruction Immediate data can be either 8 or 16 bits in length Immediate operands are available directly from the instruction queue and can be accessed quickly As with a register operand no bus cycles need to be run to get an imme diate operand Immediate operands can be only source operands and must have a constant value 2 2 2 2 Memory Addressing Modes Although the Execution Unit has direct access to register and immediate operands memory op erands must be transferred to and from the CPU over the bus When the Execution Unit needs to read or write a memory operand it must pass an offset value to the Bus Interface Unit The Bus Interface Unit adds the offset to the shifted contents of a segment register producing a 20 bit physical address One or more bus cycles are then run to access the operand The offset that the Execution Unit calculates for memory operand is called the operand s Effec tive Address EA This address is an unsigned 16 bit number that expresses the operand s dis tance in bytes from the beginning of the segment in which it resides The Execution Unit can calculate the effective address in several ways Information encoded in the second byte of the in struction tells the Execution Unit how to calculate the effective address of each memory operand A compiler or assembler derives this information from the instruction written by the programmer Assembly language programmers have access to all addressing modes The Exec
238. instruction processing until the ex ception is corrected The CPU handles software interrupts and exceptions in the same way The interrupt type for an exception is either predefined or supplied by the instruction Exceptions are classified as either faults or traps depending on when the exception is detected and whether the instruction that caused the exception can be restarted Faults are detected and ser viced before the faulting instruction can be executed The return address pushed onto the stack in the interrupt processing instruction points to the beginning of the faulting instruction This al lows the instruction to be restarted Traps are detected and serviced immediately after the instruc tion that caused the trap The return address pushed onto the stack during the interrupt processing points to the instruction following the trapping instruction Divide Error Type 0 A Divide Error trap is invoked when the quotient of an attempted division exceeds the maximum value of the destination A divide by zero is a common example Single Step Type 1 The Single Step trap occurs after the CPU executes one instruction with the Trap Flag TF bit set in the Processor Status Word This allows programs to execute one instruction at a time Inter rupts are not generated after prefix instructions e g REP after instructions that modify segment registers e g POP DS or after the WAIT instruction Vectoring to the single step interrupt s
239. into the Serial Receive Buffer SxRBUF Register From there the user can read the received data byte The RX machine samples the RXD pin looking for a logical low start bit signifying the begin ning of a reception Once the logical low has been detected the RX machine begins the receive process Each expected bit time is divided into eight samples by the 8X baud clock The RX ma chine takes the three middle samples and based on a two out of three majority determines the data bit value This oversampling is common for asynchronous serial ports and improves noise immunity This majority value is then shifted into the receive shift register Using this method the RX machine can tolerate incoming baud rates that differ from its own in ternal baud rates by 2 5 overspeed and 5 5 underspeed These limits exceed the CCITT ex tended signaling rate specifications A stop bit is expected by the RX machine after the proper number of data bits When the stop bit has been validated the data from the shift register is copied into SXRBUF and the Receive Inter rupt RI bit is set Note that the stop bit is actually validated right after its middle three samples are taken Therefore the data is moved into SxRBUF and the RI bit is set approximately in the middle of the stop bit time 10 2 SERIAL COMMUNICATIONS UNIT dd Lugd egu 20 jeubls jsonbay Y 91607 6 jouueyy JejsiDou HUS
240. inued MON Flags Name Description Operation Affected JO Jump on Overflow if AF JO disp8 1 CF T f Ito th then DF Transfers contro tot e target ocation IP lt IP disp8 sign ext to 16 bits IF if the tested condition OF 1 is true OF Instruction Operands short label SF TF ZF JP Jump on Parity if AF JPE Jump on Parity Equal PF 2 1 JP disp8 then DF JPE disp8 IP lt IP disp8 sign ext to 16 bits IF OF Transfers control to the target location PF if the tested condition PF 1 is true SF Instruction Format JP short label ZF JPE short label JS Jump on Sign if AF JS disp8 SF 1 CF Transfers control to the target location tren DES 1 y R lt IP disp8 sign ext to 16 bits IF if the tested condition SF 1 is true MPs Spa Sig OF Instruction Format JS short label SF TF ZF LAHF Load Register AH From Flags lt SF ZF X AF X PF X CF AF LAHF EE n Copies SF ZF AF PF and CF the IF 8080 8085 flags into bits 7 6 4 2 and OF 0 respectively of register AH The PF content of bits 5 3 and 1 are SF undefined LAHF is provided primarily TE for converting 8080 8085 assembly TEs language programs to run on an 8086 or 8088 Instruction Operands none NOTE The three symbols used in the Flags Affected
241. irements DRAM interface designs need special attention to transmission line effects since DRAMS represent significant loads on the bus DRAM controllers may be either clocked or unclocked An unclocked DRAM controller requires a tapped digital delay line to derive the proper timings Clocked DRAM controllers may use either discrete or programmable logic devices A state ma chine design is appropriate especially if the circuit must provide wait state control beyond that possible with the processor s Chip Select Unit Because of the microprocessor s four clock bus clocking some logic elements on each CLKOUT phase is advantageous see Figure 7 4 7 5 REFRESH CONTROL UNIT intel CLKOUT Muxed Address 52 0 NOTES 1 CAS is unnecessary for refresh cycles only 2 WE is necessary for write cycles only A1267 0A Figure 7 4 Suggested DRAM Control Signal Timing Relationships The cycle begins with presentation of the row address RAS should go active on the falling edge of T2 At the rising edge of T2 the address lines should switch to a column address CAS goes active on the falling edge of T3 Refresh cycles do not require CAS When CAS is present the dummy read cycle becomes a true read cycle the DRAM drives the bus and the DRAM row still gets refreshed Both RAS and CAS stay active during any wait states They go inactive on the falling edge of T4 At the rising edge of T4 the address multiplexer shifts to
242. ister reg16 An 16 bit general register Seg reg A segment register accum Register AX or AL immed A constant in the range 0O FFFFH immed8 A constant in the range 0 FFH mem An 8 or 16 bit memory location mem16 A 16 bit memory location mem32 A 32 bit memory location src table Name of 256 byte translate table src string Name of string addressed by register SI dest string Name of string addressed by register DI short label A label within the 128 to 127 bytes of the end of the instruction near label A label in current code segment far label A label in another code segment near proc A procedure in current code segment far proc A procedure in another code segment memptr16 A word containing the offset of the location in the current code segment to which control is to be transferred memptr32 A doubleword containing the offset and the segment base address of the location in another code segment to which control is to be transferred regptr16 A 16 bit general register containing the offset of the location in the current code segment to which control is to be transferred repeat A string instruction repeat prefix INSTRUCTION SET DESCRIPTIONS Table C 3 Flag Bit Functions Name Function AF Auxiliary Flag Set on carry from or borrow to the low order four bits of AL cleared otherwise CF Carry Flag Set on high order bit carry or borrow cleared otherwise DF Direction
243. it and receive Clear to Send feature for transmission Break character transmission and detection Programmable even odd or no parity Detects both framing and overrun errors Supports interrupt on transmit and receive 10 1 1 Asynchronous Communications Asynchronous communications protocols allow different devices to communicate without a com mon reference clock The devices communicate at a common baud rate or bits per second Data is transmitted and received in frames A frame is a sequence of bits shifted serially onto or off the communications line Each asynchronous frame consists of a start bit always a logic zero followed by the data bits and a terminating stop bit The serial port can transmit and receive seven eight or nine data bits The last data bit can optionally be replaced by an even or odd parity bit Figure 10 1 shows a typ ical 10 bit frame 10 1 SERIAL COMMUNICATIONS UNIT intel A1274 0A Figure 10 1 Typical 10 Bit Asynchronous Data Frame When discussing asynchronous communications it makes sense to talk about the receive ma chine RX machine and the transmit machine TX machine separately Each is completely in dependent Transmission and reception can occur simultaneously making the asynchronous modes full duplex 10 1 1 1 RX Machine The RX machine Figure 10 2 shifts the received serial data into the receive shift register When the reception has completed the data is then moved
244. it clears the corresponding bit in the Interrupt Request register and sets the corresponding bit in the In Service register The In Service register keeps track of which interrupt handlers are being processed At the end of an interrupt handler the programmer must issue an End of Interrupt EOI command to explicitly clear the In Service register bit If the bit remains set the Interrupt Control Unit cannot process any additional interrupts from that source 8 2 2 Priority Resolution The decision to assert the maskable interrupt request to the CPU is somewhat complicated The complexity is needed to support interrupt nesting First an interrupt occurs and the corre sponding Interrupt Request register bit is set The Interrupt Control Unit then asserts the maskable interrupt request to the CPU if the pending interrupt satisfies these requirements 1 its Interrupt Mask bit is cleared it is unmasked 2 its priority is higher than the value in the Priority Mask register 3 its In Service bit is cleared 4 its priority is equal to or greater than that of any interrupt whose In Service bit is set The In Service register keeps track of interrupt handler execution The Interrupt Control Unit uses this information to decide whether another interrupt source has sufficient priority to preempt an interrupt handler that is executing 8 5 INTERRUPT CONTROL UNIT intel 8 2 2 1 Priority Resolution Example This example illustrates priority resolu
245. it relocates to word 10000H plus its fixed offset NOTE Due to an internal condition external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block PCB is located at 0000H in I O space In this case wait states cannot be added to interrupt acknowledge bus cycles However you can add wait states to interrupt acknowledge cycles if the PCB is located at any other address 4 5 1 Considerations for the 80C187 Math Coprocessor Interface Systems using the 80C187 math coprocessor interface must not relocate the Peripheral Control Block to location 0000H in I O space The 80C187 interface uses I O locations OF8H through OFFH If the Peripheral Control Block resides in these locations the processor communicates with the Peripheral Control Block not the 80C187 interface circuitry NOTE If the PCB is located at 0000H in I O space and access to the math coprocessor interface is enabled the Escape Trap bit is clear a numerics ESC instruction causes indeterminate system operation Since the 8 bit bus version of the device does not support the 80C187 it automatically traps an ESC instruction to the Type 7 interrupt regardless of the state of the Escape Trap ET bit For details on the math coprocessor interface see Chapter 12 Math Coprocessing 4 7 PERIPHERAL CONTROL BLOCK 4 8 intel 5 Clock Generation Power Management CHAPTER 5 CLOCK GENERATION AND POWER MANAGEMENT
246. its IF if the tested condition CF 1 is true EE P Sig OF Instruction Operands JC short label SF TF ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 21 INSTRUCTION SET DESCRIPTIONS intel Table C 4 Instruction Set Continued E Flags Name Description Operation Affected JCXZ Jump if CX Zero if AF JCXZ disp8 CX 0 CF h then DF Transfers control to the target location IP lt IP disp8 sign ext to 16 bits IF if CX is 0 Useful at the beginning of a OF loop to bypass the loop if CX has a PF zero value i e to execute the loop SF zero times TE Instruction Operands 2 JCXZ short label JE Jump on Equal if AF JZ Jump on Zero ZF 1 CF JE disp8 then v MES JZ disp8 IP lt IP disp8 sign ext to 16 bits IF OF Transfers control to the target location PF if the condition tested ZF 1 is true SF Instruction Operands TF JE short label ZF JZ short label JG Jump on Greater Than if AF JNLE Jump on Not Less Than or Equal SF OF and ZF 0 JG disp8 TEM S Eins JNLE disp8 IP lt IP disp8 sign ext to 16 bits IF
247. ixed with then REPE or REPZ the operation is 01 lt 01 DELTA interpreted as scan while end of else string CX not 0 and string element 01 lt DI DELTA scan value ZF 1 This form may be used to scan for departure from a given value If SCAS is prefixed with REPNE or REPNZ the operation is interpreted as scan while not end of string CX not 0 and string element is not equal to scan value ZF 0 Instruction Operands SCAS dest string SCAS repeat dest string NOTE The three symbols used in the Flags Affected column are defined as follows C 42 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued MON A Flags Name Description Operation Affected SHR Shift Logical Right temp count AF Gre baa bit of dest OF ow order bit of des Shifts the bits in the destination ee dest ioe gest 2 operand byte or word to the right by temp lt temp 1 OF v the number of bits specified in the if PF v count operand Zeros are shifted in on count 1 SF v the left If the sign bit retains its original then TF value then OF is cleared if ZE Instruction Operands high order bit of dest SHR reg n next to high order bit of de
248. l Channel O0 Interrupt Request To SOSTS Transmit Interrupt Request 0 Receive Interrupt Request 0 A1270 A Figure 10 18 Channel 0 Interrupts Read S1STS Transmit Interrupt Request 1 Receive Interrupt Request 1 A1271 0A Figure 10 19 Channel 1 Interrupts 10 22 intel SERIAL COMMUNICATIONS UNIT 10 5 SERIAL PORT EXAMPLES This section contains examples that show ways to use the serial port NOTE The examples assume that the Peripheral Control Block is located in I O space 10 5 1 Asynchronous Mode Example Example 10 1 contains sample code to initialize Serial Port 0 for 9600 baud operation in asyn chronous Mode 4 mod186 name Scu async example This file contains an example of initialization code for the 80C186EB Serial Communications Unit The example has three procedures ASYNC CHANNEL SETUP sets up channel 0 as 9600 baud full duplex 7 data bits parity with CTS control ASYNC REC INT PROC is an interrupt handler for a reception The procedure 4 is nearly empty since the code to perform error checking and receive buffer handling is application dependent ASYNC_ XMIT_INT_PROC is an interrupt handler for a transmission This procedure too is nearly devoid of code A typical F application would test the TXE bit then copy data from the transmit buffer in memory to the SOTBUF register assume serial port registers have been correctly defined and the PCB i
249. l Unit Registers Three contiguous Peripheral Control Block registers operate the Refresh Control Unit the Re fresh Base Address Register Refresh Clock Interval Register and the Refresh Control Register A fourth register the Refresh Address Register permits examination of the refresh address bits generated by the Refresh Control Unit 7 7 2 1 Refresh Base Address Register The Refresh Base Address Register Figure 7 6 programs the base upper seven bits of the re fresh address Seven bit mapping places the refresh address at any 4 Kbyte boundary within the 1 Mbyte address space When the partial refresh address from the 12 bit address counter see Fig ure 7 1 and Refresh Control Unit Capabilities on page 7 2 passes FFFH the Refresh Control Unit does not increment the refresh base address Setting the base address ensures that the address driven during a refresh bus cycle activates the DRAM chip select 7 7 REFRESH CONTROL UNIT intel Register Name Refresh Base Address Register Register Mnemonic RFBASE Register Function Determines upper 7 bits of refresh address 15 0 A1008 0A Bit Mnemonic Reset State Function Bit Name RA19 13 Refresh 00H Uppermost address bits for DRAM refresh Base cycles NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 7 6 Refresh Base Add
250. l registers see Figure 2 3 The general registers are subdivided into two sets of four registers These sets are the data registers also called the H amp L group for high and low and the pointer and index registers also called the P amp I group Accumulator Stack Pointer Base Pointer Source Index Destination Index A1033 0A Figure 2 3 General Registers 2 4 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The data registers can be addressed by their upper or lower halves Each data register can be used interchangeably as a 16 bit register or two 8 bit registers The pointer registers are always access ed as 16 bit values The CPU can use data registers without constraint in most arithmetic and log ic operations Arithmetic and logic operations can also use the pointer and index registers Some instructions use certain registers implicitly see Table 2 1 allowing compact encoding Table 2 1 Implicit Use of General Registers Register Operations AX Word Multiply Word Divide Word I O AL Byte Multiply Byte Divide Byte I O Translate Decimal Arithmetic AH Byte Multiply Byte Divide BX Translate CX String Operations Loops CL Variable Shift and Rotate DX Word Multiply Word Divide Indirect I O SP Stack Operations SI String Operations DI String Operations The contents of the general purpose registers are undefined following a processor reset 2 1 4 Segment Registers The 80C186 Mo
251. les are used for examples and illustration 3 2 1 16 Bit Data Bus The memory address space on a 16 bit data bus is physically implemented by dividing the address space into two banks of up to 512 Kbytes each see Figure 3 1 One bank connects to the lower half of the data bus and contains even addressed bytes A020 The other bank connects to the upper half of the data bus and contains odd addressed bytes 0 1 Address lines A19 1 select a specific byte within each bank AO and Byte High Enable BHE determine whether one bank or both banks participate in the data transfer 3 1 BUS INTERFACE UNIT intel Physical Implementation Physical Implementation of the Address Space for of the Address Space for 8 Bit Systems 16 Bit Systems 512 KBytes 512 KBytes A19 1 D15 8 BHE A1100 0A Figure 3 1 Physical Data Bus Models Byte transfers to even addresses transfer information over the lower half of the data bus see Fig ure 3 2 AO low enables the lower bank while BHE high disables the upper bank The data value from the upper bank is ignored during a bus read cycle BHE high prevents a write operation from destroying data in the upper bank Byte transfers to odd addresses transfer information over the upper half of the data bus see Figure 3 2 BHE low enables the upper bank while AO high disables the lower bank The data value from the lower bank is ignored during a bus read cycle AO high prevents a write operation from destr
252. licated case is when an NMI a maskable interrupt a single step and another ex ception are pending on the same instruction boundary Figure 2 30 shows how this case is prior itized by the CPU Note that if the single step routine sets the Trap Flag TF bit before executing the IRET instruction the NMI routine will also be single stepped 2 48 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Enable Bit IE 1 Trap Flag TF 1 Timer Interrupt Push PSW CS IP Interrupt Enable Bit IE 0 Fetch Divide Error Vector Trap Flag TF 0 Push PSW CS Interrupt Enable Bit IE 0 Fetch NMI Vector Trap Flag TF 0 Push PSW CS IP Interrupt Enable Bit IE 0 Fetch Single Step Vector Trap Flag TF 0 Execute Single Step Service Routine IRET Interrupt Enable Bit IE 0 Trap Flag TF Interrupt Enable Bit IE 1 Trap Flag TF X Push PSW CS IP Interrupt Enable Bit IE 1 Fetch Single Step Vector Trap Flag TF X Execute Single Step Service Routine A1034 0A Figure 2 30 Simultaneous NMI Single Step and Maskable Interrupt 2 49 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE 2 50 intel Bus Interface Unit intel CHAPTER 3 BUS INTERFACE UNIT The Bus Interface Unit BIU generates bus cycles that prefetch instructions from memory pass data to and from the execution unit and pass data to and from the integrated peripheral units The
253. ling the length of time that SBRK remains set When writing SBRK make sure the other bits in SxCON retain their current states 10 14 intel SERIAL COMMUNICATIONS UNIT Register Name Serial Port Control Register Register Mnemonic SxCON Register Function Controls serial port operating modes A1277 0A Function Mnemonic SBRK Send Break Setting SBRK drives TXD low TXD remains low until SBRK is cleared TB8 Transmitted TB8 is the eighth data bit transmitted in modes 2 Bit 8 and CEN Clear to When CEN is set no transmissions will occur until Send Enable the CTS pin is asserted REN Receive Set to enable the receive machine Enable EVN Even Parity When parity is enabled EVN selects between even Select and odd parity Set for even clear for odd parity PEN Parity Setting PEN enables the parity generation checking Enable for all transmissions receptions M2 0 Serial Port Operating mode for the serial port channel Mode Field M2 1 MO Mode Synchronous ModeO 10 Bit Asynch Mode1 11 Bit Asynch Mode2 11 Bit Asynch Mode3 9 Bit Asynch Mode4 Reserved Reserved Reserved 4 OC0CO NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 10 13 Serial Port Control Register SxCON 10 15 SERIAL COMMUNICATIONS UNIT intel The serial port receives
254. ller to cause the timer to generate an interrupt every 10 milliseconds and to service interrupts to implement a real time clock Timer 2 is used in this example because no input or output signals are required extern void far set time hour minute second T2Compare hour hour to set time to minute minute to set time to Second second to set time to T2Compare T2CMPA value see note below None Parameters are passed on the stack as required by high level languages For a CLKOUT of 16Mhz f timer2 16Mhz 4 4Mhz 0 25us for T2CMPA T2CMPA 10ms 10ms 0 25us 10e 3 0 25e 6 40000 substitute register offsets T2CON T2CMPA T2CNT TCUCON EOI INTSTS timer 2 int data segment public hour minute Second msec data ends equ xxxxh Timer 2 Control register equ xxxxh Timer 2 Compare register equ xxxxh Timer 2 Counter register equ xxxxh Int Control register equ xxxxh End Of Interrupt register equ xxxxh Interrupt Status register equ 19 timer 2 vector type 19 public data hour minute second _msec db db db db 2 2 E Example 9 1 Configuring a Real Time Clock intel TIMER COUNTER UNIT lib 80186 segment public code assume cs lib 80186 ds data public set time _ time proc far push bp Save caller s bp mov bp sp get current top of stack hour equ word ptr bp 6 get parameters off stack minute equ word ptr bp 8 Second equ word
255. load FIST Integer store FISTP Integer store and pop Packed Decimal Transfers FBLD Packed decimal BCD load FBSTP Packed decimal BCD store and pop 12 3 1 2 Arithmetic Instructions The 80C187 s arithmetic instruction set includes many variations of add subtract multiply and divide operations and several other useful functions Examples include a simple absolute value and a square root instruction that executes faster than ordinary division Other arithmetic instruc tions perform exact modulo division round real numbers to integers and scale values by powers of two Table 12 2 summarizes the available operation and operand forms for basic arithmetic In addi tion to the four normal operations reversed instructions make subtraction and division sym metrical like addition and multiplication In summary the arithmetic instructions are highly flexible for these reasons the 80C187 uses register or memory operands the 80C187 can save results in a choice of registers 12 3 MATH COPROCESSING intel 8 Available data types include temporary real long real short real short integer and word integer The 80C187 performs automatic type conversion to temporary real Table 12 2 80C187 Arithmetic Instructions Addition Division FADD Add real FDIV Divide real FADDP Add real and pop FDIVP Divide real and pop FIADD Integer add FIDIV Integer divide Subtraction FDIVR Di
256. m other hardware connected to that chip select pin A chip select pin goes active on 80C187 accesses if you program it for a range including the math coprocessor I O ports The converse is not true a non 80C187 access cannot activate NCS nu merics coprocessor select regardless of programming In a buffered system it is customary to place the 80C187 on the local bus Since DTR and DEN function normally during 80C187 transfers you must qualify DEN with NCS see Figure 12 3 Otherwise contention between the 80C187 and the transceivers occurs on read cycles to the 80C187 The microprocessor s local bus is available to the integrated peripherals during numerics execu tion whenever the CPU is not communicating with the 80C187 The idle bus allows the processor to intersperse DRAM refresh cycles with accesses to the 80C187 The microprocessor s local bus is available to alternate bus masters during execution of numerics instructions when the CPU does not need it Bus cycles driven by alternate masters via the HOLD HLDA protocol can suspend coprocessor bus cycles for an indefinite period The programmer can lock 80C187 instructions The CPU asserts the LOCK pin for the entire du ration of a numerics instruction monopolizing the bus for a very long time 12 11 MATH COPROCESSING intel External Oscillator Buffer Buffer A1255 01 12 12 Figure 12 3 80C187 Configuration with a Partially Buffered Bus i
257. main unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued MEN Flags Name Description Operation Affected XLAT Translate AL lt AF XLAT translate table a E Replaces a byte in the AL register with IF a byte from a 256 byte user coded OF translation table Register BX is PF assumed to point to the beginning of SF the table The byte in AL is used as an TF index into the table and is replaced by ZF the byte at the offset in the table corre sponding to AL s binary value The first byte in the table has an offset of 0 For example if AL contains 5H and the sixth element of the translation table contains 33H then AL will contain 33H following the instruction XLAT is useful for translating characters from one code to another the classic example being ASCII to EBCDIC or the reverse Instruction Operands XLAT src table XOR Exclusive Or dest lt dest xor src AF XOR dest src CF lt 0 CF v OF 0 DF Performs the logical exclusive or of IF the two operands and returns the OF v result to the destination operand A bit PF in the result is set if the corresponding Sh SF v bits of the original operands contain TF opposite values one is set the
258. mation on refresh cycles during hold see Refresh Operation During a Bus HOLD on page 3 41 and Refresh Operation and Bus HOLD on page 7 13 5 2 1 3 Leaving Idle Mode Any unmasked interrupt or non maskable interrupt NMI will return the processor to Active mode Reset also returns the processor to Active mode but the device loses its prior state Any unmasked interrupt received by the core will return the processor to Active mode Interrupt requests pass through the Interrupt Control Unit with an interrupt resolution time for mask and priority level checking Then after 1 clocks the core clock begins toggling It takes an addi tional 6 CLKOUT cycles for the core to begin the interrupt vectoring sequence 5 14 intel CLOCK GENERATION AND POWER MANAGEMENT After execution of the IRET interrupt return instruction in the interrupt service routine the CS IP will point to the instruction following the HALT Interrupt execution does not modify the Power Control Register Unless the programmer intentionally reprograms the register after exit ing Idle mode the processor will re enter Idle mode at the next HLT instruction Like an unmasked interrupt an NMI will return the core to Active mode from Idle mode It takes two CLKOUT cycles to restart the core clock after an NMI occurs The NMI signal does not need the mask and priority checks that a maskable interrupt does This results in a considerable differ ence in clock restart time
259. mber byte writes DX GCSOST Set up GCSO MOV AX CSOST_VAL OUT DX L MOV AX CSOSP VAL MOV DX CSOSP OUT DX L Remember byte writes MOV DX CS2ST Set up GCS2 MOV AX CS2ST_VAL OUT DX L MOV DX CS2SP MOV AX CS2SP_VAL OUT DX L Remember byte writes Place remaining User Code here CODE ENDS POWER ON RESET CODE TO GET STARTED ASSUME CS POWER ON POWER ONSEGMENT AT OFFFFH MOV DX UCSST Point to UCS register MOV AX UCSST VAL Reprogram UCS for EPROM size OUT DX AL JMP FW START Jump to start of init code POWER ON ENDS Example 6 1 Initializing the Chip Select Unit Continued CHIP SELECT UNIT intel DATA SEGMENT DATA SEGMENT PUBLIC DATA DD 256 DUP Reserved for Interrupt Vectors Place additional memory variable here DW 500 DUP Stack allocation STACK TOP LABEL WORD DATA ENDS Program Ends END Example 6 1 Initializing the Chip Select Unit Continued 6 6 2 Example 2 Detecting Attempts to Access Guarded Memory A chip select is configured to set an interrupt when the bus accesses a physical address region that does not contain a valid memory or peripheral device Figure 6 11 illustrates how a simple circuit detects the errant bus cycle and generates an NMI System software then deals with the error The purpose of using the chip select is to generate a bus ready and prevent a bus hang condition Processor NMI GCS5 A1158 0A Figure 6 11 Guarde
260. med to run continuously in single maximum count and dual maximum count modes The Continuous CONT bit in the Timer Control register determines whether a timer is disabled after a single counting sequence 9 2 3 1 Retriggering The timer input pins affect timer counting in three ways see Table 9 2 The programming of the External EXT and Retrigger RTG bits in the Timer Control register determines how the input signals are used When the timers are clocked internally the RTG bit determines whether the in put pin enables timer counting or retriggers the current timing cycle When the EXT and RTG bits are clear the timer counts internal timer events In this mode the input is level sensitive not edge sensitive A low to high transition on the timer input is not re quired for operation The input pin acts as an external enable If the input is high the timer will count through its sequence provided the timer remains enabled 9 13 TIMER COUNTER UNIT intel Table 9 2 Timer Retriggering EXT RTG Timer Operation 0 0 Timer counts internal events if input pin remains high 0 1 Timer counts internal events count resets to zero on every low to high transition on the input pin 1 X Timer input acts as clock source When the EXT bit is clear and the RTG bit is set every low to high transition on the timer input pin causes the Count register to reset to zero After the timer is enabled counting begins only aft
261. memory accesses can end only on multiples of 1 Kbyte A chip select configured for I O accesses can end only on multiples of 64 bytes The equations below define the ending address for the chip select For memory accesses Stop Value Decimal x 1024 1 Physical Ending Address Decimal For I O accesses Stop Value Decimal x 64 12 Physical Ending Address Decimal 6 10 intel CHIP SELECT UNIT In the previous equations a stop value of 1023 03FFH results in a physical ending address of OFFBFFH memory or OFFBFH I O These addresses do not represent the top of the memory or I O address space To have a chip select enabled to the end of the physical address space the ISTOP control bit must be set The ISTOP control bit overrides the stop address comparator out put see Figure 6 2 on page 6 3 6 4 4 Enabling and Disabling Chip Selects The ability to enable or disable a chip select is important when multiple memory devices share or can share the same physical address space Examples of where two or more devices would occupy the same address space include shadowed memory bank switching and paging The STOP register holds the CSEN control bit which determines whether the chip select should go active A chip select never goes active if its CSEN control bit is cleared Chip selects can be disabled by programming the stop address value less than the start address value or by programming the start address value greater than
262. ment features and advanced CHMOS IV process The 80C186EB C188EB has found acceptance in a wide array of portable equipment ranging from cellular phones to personal organizers In 1991 the 80C186 Modular Core family was again extended with the introduction of three new products the 80C186XL the 80C186EA and the 80C186EC The 80C186XL C188XL is a high er performance lower power replacement for the 80C186 C188 The 80C186EA C188EA com bines the feature set of the 80C186 with new power management features for power critical applications The 80C186EC C188EC offers the highest level of integration of any of 80C186 Modular Core family products with 14 on chip peripherals see Table 1 1 INTRODUCTION intel The 80C186 Modular Core family is the direct result of ten years of Intel development It offers the designer the peace of mind of a well established architecture with the benefits of state of the art technology Table 1 1 Comparison of 80C186 Modular Core Family Products Feature 80C186XL 80C186EA 80C186EB 80C186EC Enhanced 8086 Instruction Set Low Power Static Modular CPU Power Save Clock Divide Mode Powerdown and Idle Modes 806187 Interface ONCE Mode Interrupt Control Unit 8259 Compatible Timer Counter Unit Chip Select Unit Enhanced Enhanced DMA Unit 2 Channel 2 Channel 4 Channel Serial Communications Unit Refresh Control Unit Enhanced Enhanced Watchdog Timer
263. must be written to a logic zero to ensure compatibility with future Intel products Figure 10 10 Baud Rate Counter Register BxCNT 10 11 SERIAL COMMUNICATIONS UNIT intel Register Name Baud Rate Compare Register Register Mnemonic BxCMP Register Function Determines baud rate for the serial port 0 B B B B B B RJ R 5 4 312110 15 1276 0 Bit i nction Mnemonic Bit Name Functio ICLK Internal Selects the input clock Clocking 0 BCLK is input to baud clock 1 CPU clock is input to baud clock Baud Rate Sets the compare value for the baud rate clock Compare Field Figure 10 11 Baud Rate Compare Register BxCMP The equations in Figure 10 12 show how to calculate the proper BxCMP value for a specific baud rate where CPU operating frequency CLKIN frequency Mode 0 Mode 1 4 F F If CPU clock is baud timebase clock Bxcmp 4 BxCMP CP U baudrate baudrate 8 If BCLK is baud timebase clock BOLK BxGMp BOLK_ baudrate baudrate x 8 Figure 10 12 Calculating the BxCMP Value for a Specific Baud Rate 10 12 intel SERIAL COMMUNICATIONS UNIT Due to internal synchronization requirements the maximum input frequency to BCLK is one half the CPU operating frequency See BCLK Pin Timings on page 10 18 for more information Ta ble 10 1 shows the correct BXCMP values for common baud rates
264. n Bit Signed Quad Word Sign Bit Binary Coded Decimal BCD Packed BCD Pointer Floating Point Sign Bit 7 0 Unsigned 7777777 LMSB L Magnitude l 0 1 Unsigned 15 Word LMSB L Magnitude JL Magnitude 1514 1 87 0 J LMSB LL Magnitude 4 87 3 2 1 0 31 2423 1615 87 0 LMSB gt 4 L Magnitude 0 7 21615 0 63 6 5 3 4847 43231 LMSB J Magnitude 3 7 0 0 BCD Digit BCD Digit 0 1 0 7 m 0 BCD Digit n 7 n 0 7 07 0 TEE ASCII Character 1 ASCII Character 0 ASCII Character n 7 mM 9 7 d 0 ope LLL pet IRURE Least Most Significant Digit Significant Digit 7 n ae Byte Word n 3 0 7 07 9 0 Byte Word 1 Byte Word 0 2 1 0 31 24 23 16 15 87 L Selecto E Offset 3 79 9 8 7 6 5 4 3 2 0 0 ee p m 1 L Exponent _L__________ Magnitude _________1 1 NOTE Directly supported if the system contains 800187 A1027 0B Figure 2 23 80C186 Modular Core Family Supported Data Types 2 38 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 3 INTERRUPTS AND EXCEPTION HANDLING Interrupts and exceptions alter program execution in response to an external event or an error condition An interrupt han
265. nary value 0101 is written to P1 0 through P1 3 The states of pins P2 6 and P2 7 are read and stored in the AL reg ister Smod186 name io_port_unit_example This file contains sample programming code for the 80C186EB I O Port Unit PCB EQUates in an include file include PCBMAP inc code seg segment public assume cs code seg IO UNIT EXAMPL proc near write 0101B to data latch for pins P1 3 through P1 0 mov dx Pl1LTCH mov al 0101b out dx al Gate data latch to output pins P1 3 to P1 0 are port pins mov dx P1CON mov 1 out dx al Read P2 6 and P2 7 We assume they have not been changed to output pins since reset mov dx P2PIN in al dx and al OCOh strip unused bits AL now holds the states of the P2 6 and P2 7 pins IO_UNIT_EXMPL endp code_seg ends end Example 11 1 I O Port Programming Example 11 12 intel 12 Math Coprocessing intel CHAPTER 12 MATH COPROCESSING The 80C186 Modular Core Family meets the need for a general purpose embedded microproces sor In most data control applications efficient data movement and control instructions are fore most and arithmetic performed on the data is simple However some applications do require more powerful arithmetic instructions and more complex data types than those provided by the 80C186 Modular Core 12 1 OVERVIEW OF MATH COPROCESSING Applications needing advanced mathematics capabilities have the following characteristi
266. nctions A1164 0A Bit Bit Name Function Mnemonic MEM Bus Cycle When MEM is set the chip select goes active Selector for memory bus cycles Clearing MEM activates the chip select for I O bus cycles MEM defines which address bits are used by the start and stop address comparators When MEM is cleared address bits A15 6 are routed to the comparators When MEM is set address bits A19 10 are routed to the comparators Bus Ready Setting RDY requires that bus ready be active Enable to complete a bus cycle Bus ready is ignored when RDY is cleared RDY must be set to extend wait states beyond the number determined by WS3 0 NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products The reset state of CSEN and ISTOP is 1 for the UCSSP register Figure 6 6 STOP Register Definition Continued The correct sequence to program a non enabled chip select is as follows If the chip select is al ready enabled either reverse the sequence or disable the chip select before reprogramming it 1 Program the START register 2 Program the STOP register CHIP SELECT UNIT intel 6 4 2 Start Address The START register of each chip select defines its starting base address The start address value is compared to the ten most significant address bits of the bus cycle A bus cycle whose ten most significant
267. nd Powerdown modes see Temporarily Exiting the HALT Bus State on page 3 30 3 43 BUS INTERFACE UNIT intel CLKOUT AD15 0 DEN RD WR BHE DT R S2 0 A19 16 HOLD recognition setup to clock low HOLD internally synchronized Clock low to HLDA low Clock high to signal active high or low Clock low to signal active high or low A1099 0A Figure 3 36 Exiting HOLD 3 8 BUS CYCLE PRIORITIES The BIU arbitrates requests for bus cycles from the Execution Unit the integrated peripherals e g Interrupt Control Unit and external bus masters 1 bus hold requests The list below summarizes the priorities for all bus cycle requests from highest to lowest 1 Instruction execution read write following a non pipelined effective address calculation 2 Refresh bus cycles 3 Bus hold request 4 Single step interrupt vectoring sequence 5 Non Maskable interrupt vectoring sequence 3 44 intel BUS INTERFACE UNIT u 9 Internal error e g divide error overflow interrupt vectoring sequence Hardware e g INTO interrupt vectoring sequence 80C187 Math Coprocessor error interrupt vectoring sequence General instruction execution This category includes read write operations following a pipelined effective address calculation vectoring sequences for software interrupts and numerics code execution The following points apply to sequences of related execution cycles The se
268. ng 2 35 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel oo 7 Destination EA A1025 0A Figure 2 21 String Operand 2 2 2 3 Port Addressing Any memory operand addressing modes can be used to access an I O port if the port is memory mapped String instructions can also be used to transfer data to memory mapped ports with an appropriate hardware interface Two addressing modes can be used to access ports located in the I O space see Figure 2 22 For direct I O port addressing the port number is an 8 bit immediate operand This allows fixed ac cess to ports numbered 0 to 255 Indirect I O port addressing is similar to register indirect address ing of memory operands The DX register contains the port number which can range from 0 to 65 535 Adjusting the contents of the DX register allows one instruction to access any port in the T O space A group of adjacent ports can be accessed using a simple software loop that adjusts the value of the DX register Port Address Port Address Direct Port Indirect Port Addressing Addressing A1026 0A Figure 2 22 I O Port Addressing 2 36 intel OVERVIEW OF THE 800186 FAMILY ARCHITECTURE 2 2 2 4 Data Types Used in the 80C186 Modular Core Family The 80C186 Modular Core family supports the data types described in Table 2 12 and illustrated in Figure 2 23 In general individual data elements must fit within defined segment limits Table 2 12 Supported Data Types
269. ng External 8259A Modules in Cascade 8 8 Interrupt Control Unit Latency and Response Time 8 11 Interrupt Control Register for Internal Sources essee 8 13 Interrupt Control Register for Noncascadable External 8 14 Interrupt Control Register for Cascadable Interrupt 8 15 Interrupt Request Register ssssssseeeeeneenen nennen 8 16 Interrupt Mask Registers 5 5 or pete tit rdi e Deo ep e ee dead 8 17 Priority Mask Register tee et cere e evi cta 8 18 In Service Register 4 ecole credet eene th He ed ete a esed reae 8 19 Poll Fegisters e RH ee aei 8 20 Poll Status Register eR RR ERR EGO OU HR REPERI 8 21 End of Interrupt 8 22 Interrupt Status Register e ee ceeeeeseeseneeeteeeeeeeeeeeeeaeeesaeeeaeecseeeeaeeeeaeesaeeeaeessaeenaeeseates 8 23 Timer Counter Unit Block Diagram ssssssesseeeeneeeenennee nennen 9 2 Counter Element Multiplexing and Timer Input Synchronization 9 3 Timers 0 and 1 Flow Chart init im Rb bd t EE uad etin 9 4 Timer Counter Unit Output Modes sssssesseeeeeeeeeneeenenennnee nennen 9 6 Timer 0 and Timer 1 Control Registers
270. ning of the segment Stack instructions always operate on the cur rent stack segment The Stack Pointer SP register contains the offset of the top of the stack from the base of the stack Most variables memory operands are assumed to reside in the current data segment but a program can instruct the Bus Interface Unit to override this assumption Often the offset of a memory variable is not directly available and must be calculated at execution time The addressing mode specified in the instruction determines how this offset is calculated see Ad dressing Modes on page 2 27 The result is called the operand s Effective Address EA Strings are addressed differently than other variables The source operand of a string instruction is assumed to lie in the current data segment However the program can use another currently addressable segment The operand s offset is taken from the Source Index SI register The des tination operand of a string instruction always resides in the current extra segment The destina tion s offset is taken from the Destination Index DI register The string instructions automatically adjust the SI and DI registers as they process the strings one byte or word at a time When an instruction designates the Base Pointer BP register as a base register the variable is assumed to reside in the current stack segment The BP register provides a convenient way to ac cess data on the stack The BP register can also b
271. nits can operate independently of one another and are able under most circumstances to overlap instruction fetches and execution The 80C186 Modular Core family has a 16 bit Arithmetic Logic Unit ALU The Arithmetic Logic Unit performs 8 bit or 16 bit arithmetic and logical operations It provides for data move ment between registers memory and I O space The 80C186 Modular Core family CPU allows for high speed data transfer from one area of memory to another using string move instructions and between an I O port and memory using block I O instructions The CPU also provides many conditional branch and control instructions The 80C186 Modular Core architecture features 14 basic registers grouped as general registers segment registers pointer registers and status and control registers The four 16 bit general pur pose registers AX BX CX and DX can be used as operands for most arithmetic operations as either 8 or 16 bit units The four 16 bit pointer registers SI DI BP and SP can be used in arith metic operations and in accessing memory based variables Four 16 bit segment registers CS DS SS and ES allow simple memory partitioning to aid modular programming The status and control registers consist of an Instruction Pointer IP and the Processor Status Word PSW reg ister which contains flag bits Figure 2 1 is a simplified CPU block diagram 2 1 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE intel General Registers In
272. nneeeeenen nnn 8 19 8 3 7 End of Interrupt EOI Register esesseseeeeeeeeneeeneenenennenn ne 8 21 8 3 8 Interrupt Status Register ssssssssssssseeeseeeeenee nennen neret 8 22 8 3 9 Initializing the Interrupt Control Unit sessseeeeeeennnennenennens 8 23 CHAPTER 9 TIMER COUNTER UNIT 9 1 FUNGTIONALE OVERVIEW tht a met ee E oe iniit 9 1 9 2 PROGRAMMING THE TIMER COUNTER 9 6 9 2 1 Initialization Sequence s ea recti bo i alata 9 11 9 2 2 Clock SO S e Hate A ete CR en oci db acd 9 12 9 2 3 Counting uec tr tli cse dre ea tore ec Pra unte ARR 9 12 9 2 3 1 Retriggerlng e Seem beret Lae 9 13 9 2 4 Pulsed and Variable Duty Cycle Output sseseeeeeneennnen 9 14 9 2 5 Enabling Disabling Counters sessseeeeeeneeeneenen nennen 9 15 9 2 6 jimerdnterrpts nh ente tei dh ter e eere ied 9 16 9 2 7 Programming Considerations ssssesseeeeeeeenene enne 9 16 9 3 TIMING iris freee acini needs See ere SI SMEs ius 9 16 9 3 1 Input Setup and Hold Timings 9 16 9 3 2 Synchronization and Maximum Frequency 9 17 9 3 2 1 Timer Counter Unit Application Examples 9 17 9 3 3 RealTime Clock etie ets c te c ptm iced 9 17 9 3
273. npacked AH lt AH 1 OF decimal operands the destination AF 1 operand must have been specified as AF SF register AL Changes the content of AL lt AL and OFH TF AL to a valid unpacked decimal ZF number the high order half byte is zeroed Instruction Operands none ADC Add with Carry if AF v ADC dest src CF 1 GE then DF Sums the operands which may be dest lt dest src 1 IF bytes or words adds one if CF is set Sise OF VY and replaces the destination operand dest lt dest src v with the result Both operands may be SF v signed or unsigned binary numbers TF see AAA and DAA Since ADC incor ZF v porates a carry from a previous operation it can be used to write routines to add numbers longer than 16 bits Instruction Operands ADC reg reg ADC reg mem ADC mem reg ADC reg immed ADC mem immed ADC accum immed NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 5 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel E Flags Name Description Operation Affected ADD Addition dest dest src AF Y ADD dest src EE d Sums two operands which may be
274. ns STC Set Carry flag CLC Clear Carry flag CMC Complement Carry flag STD Set Direction flag CLD Clear Direction flag STI Set Interrupt Enable flag CLI Clear Interrupt Enable flag External Synchronization HLT Halt until interrupt or reset WAIT Wait for TEST pin active ESC Escape to external processor LOCK Lock bus during next instruction No Operation NOP No operation 2 2 2 Addressing Modes The 80C186 Modular Core family members access instruction operands in several ways Oper ands can be contained either in registers in the instruction itself in memory or at I O ports Ad dresses of memory and I O port operands can be calculated in many ways These addressing modes greatly extend the flexibility and convenience of the instruction set The following para graphs briefly describe register and immediate modes of operand addressing A detailed descrip tion of the memory and I O addressing modes is also provided 2 2 2 1 Register and Immediate Operand Addressing Modes Usually the fastest most compact operand addressing forms specify only register operands This is because the register operand addresses are encoded in instructions in just a few bits and no bus cycles are run the operation occurs within the CPU Registers can serve as source operands des tination operands or both 2 27 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Immediate operands are constant data contained in an
275. ns on the processor NCS BUSY PEREQ and ERROR These pins are not available in some package types Refer to the data sheet for details 12 7 MATH COPROCESSING intel gt Increasing Significance Taie S Magnitude Two s Complement 0 Short Magnitude Two s Complement Integer 0 Long Two s Integer Magnitude Complement Packed Magnitude Decimal 72 Short Biased inniti Real Significand 23 Ww ja 0 Long Biased Lm Rea Signiicana CU EN 0 Temporary Biased we Eme Sena 9 64 63 NOTES S Sign bit 0 positive 1 negative da Decimal digit two per byte X Bits have no significance 80C187 ignores when loading zeros when storing A Position of implicit binary point Integer bit of significand stored in temporary real implicit in short and long real Exponent Bias normalized values Short Real 127 7FH Long Real 1023 8FFH Temporary Real 16383 FFFH A1257 0A Figure 12 1 80C187 Supported Data Types 12 8 intel MATH COPROCESSING Buffer 80C186 Modular Buffer A1255 01 Figure 12 2 80C186 Modular Core Family 80C187 System Configuration 12 9 MATH COPROCESSING intel 8 12 4 1 Clocking the 80C187 The microprocessor and math coprocessor operate asynchronously and their clock rates may dif fer The 80C187 has a CKM pin that determines whether it uses the input clock directly or divided by two Direct clocking works up to
276. nsfer Instructions sesesene em 2 18 2 2 1 2 Arithmetic Instructions cccesscceeseenceeseeeeeeseeeseeeeeeseeeeeesaeeaeesseneneseneeeseeness 2 19 2 2 1 3 Bit Manipulation Instructions e 2 21 2 2 1 4 StringAnstruetions 5 e ee a ER 2 22 2 2 1 5 Program Transfer Instructions eeeem e 2 23 2 2 1 6 Processor Control Instructions sseseeeeeeneenenenn 2 27 2 22 Addressing Modes iiie gue eet tp ione nhi 2 27 2 2 2 1 Register and Immediate Operand Addressing Modes 2 27 2 2 2 2 Memory Addressing 2 28 2 2 2 3 I O Port Addressing neve deg 2 36 2 2 2 4 Data Types Used in the 80C186 Modular Core Family 2 37 2 3 INTERRUPTS AND EXCEPTION 2 39 2 3 1 Interrupt Exception Processing 2 39 2 3 1 1 Non Maskable Interrupts seeeeeemeeem n 2 42 2 3 1 2 Maskable Interrupts 3o ott eria etn i e peines 2 43 2 3 1 3 Exceptions nien D 2 43 SUERTE intel 2 3 2 Software Interrupts nce eere et een LE ebd 2 45 2 3 3 Interrupt s eue ite it eerie ptt pe tix et cir ces da creare edv ge teet ie 2 45 2 3 4 Interrupt Response Time ntn enitn nnne nnne nne 2 46 2 3 5 Interrupt and Exception Priority
277. nt A RIU 0 Counter Counter Compare A Compare B Pulse TOUT Pin Set RIU Bit Clear RIU Bit Low For 1 Clock TOUT Pin Driven Low TOUT Pin Driven High Continuous Mode Continuous Mode CONT 1 CONT 1 Interrupt Bit Set Clear Enable Bit Clear Enable Bit Stop Counting Stop Counting Request Interrupt Clear Counter A1295 0A Figure 9 3 Timers 0 and 1 Flow Chart Continued TIMER COUNTER UNIT intel When configured for internal clocking the Timer Counter Unit uses the input pins either to en able timer counting or to retrigger the associated timer Externally a timer increments on low to high transitions on its input pin up to 14 CLKOUT frequency Timers 0 and 1 each have a single output pin Timer output can be either a single pulse indicating the end of a timing cycle or a variable duty cycle wave These two output options correspond to single maximum count mode and dual maximum count mode respectively Figure 9 4 Inter rupts can be generated at the end of every timing cycle Timer 2 has no input or output pins and can be operated only in single maximum count mode Figure 9 4 It can be used as a free running clock and as a prescaler to Timers 0 and 1 Timer 2 can be clocked only internally at 4 CLKOUT frequency Timer 2 can also generate interrupts at the end of every timing cycle Maxcount A Maxcount B M Dual Maximum Count Mode Maxcount A n ee Single Maximum Count
278. ntel Most memory and peripheral devices latch data on the rising edge of the write strobe Address chip select and data must be valid set up prior to the rising edge of WR Taw Tew and Tpw de fine the minimum data setup requirements The value calculated by their respective equations must be greater than the device requirements To increase the calculated value insert wait states A1106 0A Figure 3 22 16 Bit Bus Read Write Device Interface 3 24 intel BUS INTERFACE UNIT The minimum device data hold time from WR high is defined by Tpy The calculated value must be greater than the minimum device requirements however the value can be changed only by decreasing the clock rate Table 3 5 Write Cycle Critical Timing Parameters guid Description Equation Write cycle time 4T Taw Address valid to end of write strobe WR high Tapitcn Tow Chip enable LCS to end of write strobe WR high 3T Write recover time Twain Tow Data valid to write strobe WR high 2T Tou Data hold from write strobe WR high Twupx Twp Write pulse width and Twp define the minimum time maximum frequency a device can process write bus cy cles determines the minimum time from the end of the current write cycle to the start of the next write cycle All three parameters require that calculated values be greater than device re quirements The calculated
279. ntel MATH COPROCESSING 12 4 4 Exception Trapping The 80C187 detects six error conditions that can occur during instruction execution The 80C187 can apply default fix ups or signal exceptions to the microprocessor s ERROR pin The processor tests ERROR at the beginning of numerics instructions so it traps an exception on the next at tempted numerics instruction after it occurs When ERROR tests active the processor executes a Type 16 interrupt There is no automatic exception trapping on the last numerics instruction of a series If the last numerics instruction writes an invalid result to memory subsequent non numerics instructions can use that result as if it is valid further compounding the original error Insert the FNOP in struction at the end of the 80C187 routine to force an ERROR check If the program is written in a high level language it is impossible to insert FNOP In this case route the error signal through an inverter to an interrupt pin on the microprocessor see Figure 12 4 With this arrangement use a flip flop to latch BUSY upon assertion of ERROR The latch gets cleared during the excep tion handler routine Use an additional flip flop to latch PEREQ to maintain the correct hand shaking sequence with the microprocessor 12 5 Example Math Coprocessor Routines Example 12 1 shows the initialization sequence for the 80C187 Example 12 2 is an example of a floating point routine using the 80C187 The FSINCOS instruction y
280. nternal Peripheral Clock CPU Core Clock A1119 0A Figure 5 10 Entering Idle Mode 5 2 1 2 Bus Operation During Idle Mode DRAM refresh requests and HOLD requests temporarily turn on the core clocks If the processor needs to run a refresh cycle during Idle mode the internal core clock begins to toggle on the fall ing CLKOUT edge immediately after the down counter reaches zero After one idle T state the processor runs the refresh cycle As with all other bus cycles the BIU uses the ready wait state generation and chip select circuitry as necessary for refresh cycles during Idle mode There is one idle T state after T4 before the internal core clock shuts off again 5 13 CLOCK GENERATION AND POWER MANAGEMENT intel A HOLD request from an external bus master turns on the core clock as long as HOLD is active see Figure 5 11 The core clock restarts one CLKOUT cycle after the bus processor samples HOLD high The microprocessor asserts HLDA one cycle after the core clock starts The core clock turns off and the processor deasserts HLDA one cycle after the external bus master deas serts HOLD 1 Clock Core Processor Core Clock Delay Restart In Hold Shuts Off LS EA CLKOUT Internal Peripheral Clock Internal Core Clock HOLD HLDA A1120 0A Figure 5 11 HOLD HLDA During Idle Mode As in Active mode refresh requests will force the BIU to drop HLDA during bus hold For more infor
281. nute cmp _hour 12 have 12 hours passed jae reset_hour inc hour jmp reset int ctl reset hour mov hour 1 reset hour reset int ctl mov dx EOI mov ax 8000h non specific end of interrupt out dx al pop dx pop ax iret timer 2 interrupt routine endp lib 80186 ends end Example 9 1 Configuring a Real Time Clock Continued 9 20 Smod186 name FUNCTION SYNTAX INPUTS OUTPUTS NOTE T1CON 1ib_80186 assume public _clock push mov _space _mark push push push mov mov out mov mov out mov xor out mov mov out TIMER COUNTER UNIT example_timerl_square_wave_code This function generates a square wave of given frequency and duty cycle on Timer 1 output pin extern void far clock int mark int space mark This is the mark 1 time space This is the space 0 time The register compare value for a given time can be easily calculated from the formula below CompareValue req pulse width f 4 None Parameters are passed on the stack as required by high level Languages equ xxxxH substitute register offsets equ XXxxH equ XxXxxH equ XXxxxH segment public code cs lib 80186 clock proc far bp Save caller s bp bp sp get current top of stack equ word ptr bp 6 get parameters off the stack equ word ptr bpt8 ax save registers that will be bx modified dx dx set mark time s
282. od 001 r m disp lo disp hi esc opcode source DA 1101 1010 mod 010 r m disp lo disp hi esc opcode source DB 1101 1011 mod 011 r m disp lo disp hi esc opcode source DC 1101 1100 mod 100 r m disp lo disp hi esc opcode source DD 1101 1101 mod 101 r m disp lo disp hi esc opcode source DE 1101 1110 mod 110 r m disp lo disp hi esc opcode source DF 1101 1111 mod 111 r m disp lo disp hi esc opcode source EO 1110 0000 IP inc 8 loopne loopnz short label INSTRUCTION SET OPCODES AND CLOCK CYCLES In Table D 3 Machine Instruction Decoding Guide Continued lel Byte 2 Bytes 3 6 ASN 86 Instruction Format Hex Binary E1 1110 0001 IP inc 8 loope loopz short label E2 1110 0010 IP inc 8 loop short label 1110 0011 IP inc 8 jexz short label E4 1110 0100 data 8 in AL immed8 E5 1110 0101 data 8 in AX immed8 E6 1110 0110 data 8 out AL immed8 E7 1110 0111 data 8 out AX immed8 E8 1110 1000 IP inc lo IP inc hi call near proc E9 1110 1001 IP inc lo IP inc hi jmp near label EA 1110 1010 IP lo IP hi CS lo CS hi jmp far label EB 1110 1011 IP inc 8 jmp short label EC 1110 1100 in AL DX ED 1110 1101 in AX DX EE 1110 1110 out AL DX EF 1110 1111 out AX DX FO 1 0000 lock prefix F1 1 0001 F2 1 0010 repne repnz F3 1 0011 rep repe repz F4 1
283. odes to the Type 7 interrupt regardless of Relocation Register programming 12 1 MATH COPROCESSING intel 8 12 3 THE 80C187 MATH COPROCESSOR The 80C187 s high performance is due to its 80 bit internal architecture It contains three units a Floating Point Unit a Data Interface and Control Unit and a Bus Control Logic Unit The foun dation of the Floating Point Unit is an 8 element register file which can be used either as indi vidually addressable registers or as a register stack The register file allows storage of intermediate results in the 80 bit format The Floating Point Unit operates under supervision of the Data Interface and Control Unit The Bus Control Logic Unit maintains handshaking and communications with the host microprocessor The 80C187 has built in exception handling The 80C187 executes code written for the Intel387 DX and Intel387 SX math coprocessors The 80C187 conforms to ANSI IEEE Standard 754 1985 12 3 1 80C187 Instruction Set 80C187 instructions fall into six functional groups data transfer arithmetic comparison tran scendental constant and processor control Typical 80C187 instructions accept one or two oper ands and produce a single result Operands are usually located in memory or the 80C187 stack Some operands are predefined for example FSQRT always takes the square root of the number in the top stack element Other instructions allow or require the programmer to specify the oper and s expl
284. of bits specified in temp temp 1 OF v the count operand if PF Instruction Operands count 1 SF ROL reg n then TF ROL mem n if ZF ROL reg CL high order bit of dest z CF ROL mem CL then OF 1 else OF 0 else OF undefined NOTE The three symbols used in the Flags Affected column are defined as follows C 38 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued EM A Flags Name Description Operation Affected ROR Rotate Right temp count AF ROR dest count do while temp 0 CF v CF lt low order bit of dest DF Operates similar to ROL except that oe dee 12 IF the bits s e or word high order bit of dest lt CF OF v are rotated right instead of left temp lt temp 1 PF Instruction Operands if SF ROR reg count 1 TF ROR mem n then ZF ROR reg CL if ROR mem CL high order bit of dest next to high order bit of dest then OF 1 else OF 0 else OF undefined SAHF Store Register AH Into Flags SF ZF X AF X PF X CF lt AH AF SAHF Pr d Transfers bits 7 6 4 2 and 0 from IF register into SF ZF AF andCF OF respectively replacing whatever
285. of the lower half of the then result CF and OF are set otherwise CF 0 they are cleared When CF and OF are else set they indicate that AH or DX CF lt 1 contains significant digits of the result OF lt CF Instruction Operands IMUL reg IMUL mem IMUL immed IN Input Byte or Word When Source Operand is a Byte AF IN accum port AL lt port P n Transfers a byte or a word from an When Source Operand is a Word IF input port to the AL register or the AX AX lt port OF register respectively The port number PF may be specified either with an SF immediate byte constant allowing TF access to ports numbered 0 through ZF 255 or with a number previously placed in the DX register allowing variable access by changing the value in DX to ports numbered from 0 through 65 535 Instruction Operands IN AL immed8 IN AX DX NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 17 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel E Flags Name Description Operation Affected INC Increment dest dest 1 AF INC dest Ed z Adds one to the destination operand IF The operand may be byte or a word OF v an
286. of the same structure can be accessed by simply changing the base register 2 31 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Displacement High Address Vac Dept Status Vac Dept Low Address A1019 0A Figure 2 16 Accessing a Structure with Based Addressing With indexed addressing the effective address is calculated by summing a displacement and the contents of an index register SI or DI see Figure 2 17 Indexed addressing is often used to ac cess elements in an array see Figure 2 18 The displacement locates the beginning of the array and the value of the index register selects one element If the index register contains 0000H the processor selects the first element Since all array elements are the same length simple arithmetic on the register can select any element 2 32 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Mod R M Displacement A1020 0A Figure 2 17 Indexed Addressing High Address Low Address A1021 0A Figure 2 18 Accessing an Array with Indexed Addressing 2 33 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE intel Based index addressing generates an effective address that is the sum of a base register an index register and a displacement see Figure 2 19 The two address components can be determined at execution time making this a very flexible addressing mode A1022 0A Figure 2 19 Based Index Addressing Based index addressing provides a convenient
287. ols the accesses to SRAM memory space SRAM_SIZEEQ 32 Size in Kbytes SRAM_BASEEQ 0 Start address in Kbytes SRAM_WAITEQ 0 Wait states The LCS START and STOP register values are calculated using the above system constraints and the equations below LCSST_VALEQU SRAM_BASE SHL 6 OR SRAM_WAIT LCSSP_VALEQU SRAM_BASE OR SRAM_SIZE SHL 6 OR amp CSEN OR MEM A DRAM interface is selected by the GCS14 chip select The BASE value defines the starting address of the DRAM window The SIZE value along with the BASE value defines the ending address Zero wait state performance is assumed Refresh Control Unit uses DRAM BASE to properly configure refresh operation Example 6 1 Initializing the Chip Select Unit CHIP SELECT UNIT intel DRAM_BASEEQU Window start address in Kbytes DRAM SIZEEQU Window size in Kbytes DRAM WAITEQU Wait states change to match System The GCS14 START and STOP register values are calculated using the above syste constraints and the equations below GCS1ST VALEQU DRAM BASE SHL 6 OR DRAM WAIT GCS1SP VALEQU DRAM BASE OR DRAM SIZE SHL 6 OR amp CSEN OR MEM 1 O is selected using the GCS2 chip select Wait states assume operation at 16MHz The SIZE and BASE values must be modulo 64 bytes For this example the Floppy Disk Controller is connected to GCS2 and GCSO is connected to the DMA Controller IO SIZEEQU 64 Size in bytes IO_BASEEQU 256 Start addres
288. on Set Continued intel ae E Flags Name Description Operation Affected ENTER Procedure Entry SP SP 2 AF ENTER locals levels SP 1 SP lt BP Eae FP SP DF Executes the calling sequence for a if IF high level language It saves the level gt 0 OF current frame pointer in BP copies the then PF frame pointers from procedures below repeat level 1 times SF the current call to allow access to BP BP 2 local variables in these procedures SP SP 2 ZF and allocates space on the stack for SP 1 SP lt BP the local variables of the current end repeat procedure invocation SP lt SP 2 Instruction Operands SP 1 SP lt FP ENTER locals level end if BP FP SP SP locals ESC Escape if AF ESC mod z 11 CF then DF Provides a mechanism by which other data bus EA IF processors coprocessors may OF receive their instructions from the 8086 PF or 8088 instruction stream and make SF use of the 8086 or 8088 addressing TF modes The CPU 8086 or 8088 does ZF a no operation NOP for the ESC instruction other than to access a memory operand and place it on the bus Instruction Operands ESC immed mem ESC immed reg NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instru
289. on on HALT bus cycles Figure 5 12 shows the internal and external wave forms during entry into Powerdown mode CLKIN toggles only when external frequency input is used Halt Cycle CLKIN OSCOUT CLKOUT CPU Core Clock Internal Peripheral Clock A1121 0A Figure 5 12 Entering Powerdown Mode During the T2 phase of the HLT instruction the core generates a signal called Enter_Powerdown Enter_Powerdown immediately disables the internal CPU core and peripheral clocks The pro cessor disables the oscillator inverter during the next CLKOUT cycle If the design uses a crystal oscillator the oscillator stops immediately When CLKIN originates from an external frequency input EFT Powerdown isolates the signal on the CLKIN pin from the internal circuitry There fore the circuit may drive CLKIN during Powerdown mode although it will not clock the device 5 17 CLOCK GENERATION AND POWER MANAGEMENT intel 5 2 2 2 Leaving Powerdown Mode An NMI or reset returns the processor to Active mode If the device leaves Powerdown mode by an NMI a delay must follow the interrupt request to allow the crystal oscillator to stabilize before gating it to the internal phase clocks An external timing pin sets this delay as described below Leaving Powerdown by an NMI does not clear the PWRDN bit in the Power Control Register A reset also takes the processor out of Powerdown mode Since the oscillator is off the user should follow t
290. ons the other two provide open drain bidirectional port pin functions Table 11 2 shows the Port 2 multiplexing options Table 11 2 Port 2 Multiplexing Options Pin Name Peripheral Function Port Function P2 7 None P2 7 Open drain P2 6 None P2 6 Open drain P2 5 BCLKO BCLKO Input P2 5 P2 4 CTS1 CTS1 Input P2 4 P2 3 SINT1 SINT1 Output P2 3 P2 2 BCLK1 BCLK1 Input P2 2 P2 1 TXD1 TXD1 Output P2 1 P2 0 RXD1 RXD1 I O P2 0 11 2 PROGRAMMING THE I O PORT UNIT Each port is controlled by a set of four Peripheral Control Block registers the Port Control Reg ister PXCON the Port Direction Register PxDIR the Port Data Latch Register PXLTCH and the Port Pin State Register PxPIN INPUT OUTPUT PORTS intel 11 2 1 Port Control Register The Port Control Register Figure 11 5 selects the overall function for each port pin peripheral or port For I O ports the Port Control Register is used to assign the pin to either the associated on chip peripheral or to a general purpose I O port For output only ports the Port Control Reg ister selects the source of data for the pin either an on chip peripheral or the Port Data latch Register Name Port Control Register Register Mnemonic PxCON P1CON P2CON Register Function Selects port or peripheral function for a port pin 15 A1312 0A Bit Mnemonic Bit Name Function PC7 0 Port Control When the PC bit for a speci
291. ons during a bus hold 3 39 BUS INTERFACE UNIT intel m ZS CLKOUT AD15 0 DEN Float A19 16 RD WR __DT R S2 0 BHE LOCK HOLD input to clock low Clock high to output float Clock low to output float Clock low to HLDA high A1097 0A Figure 3 33 Timing Sequence Entering HOLD Table 3 7 Signal Condition Entering HOLD Signal HOLD Condition A19 16 S2 0 RD WR DT R BHE RFSH LOCK These signals float one half clock before HLDA is generated i e phase 2 AD15 0 16 bit AD7 0 8 bit A15 8 8 bit DEN These signals float during the same clock in which HLDA is generated i e phase 1 3 7 1 1 HOLD Bus Latency The duration between the time that the external device asserts HOLD and the time that the BIU asserts HLDA is known as bus latency In Figure 3 33 the two clock delay between HOLD and HLDA represents the shortest bus latency Normally this occurs only if the bus is idle or halted or if the bus hold request occurs just before the BIU begins another bus cycle 3 40 intel BUS INTERFACE UNIT The major factors that influence bus latency are listed below in order from longest delay to short est delay 1 Bus Not Ready As long as the bus remains not ready a bus hold request cannot be serviced 2 Locked Bus Cycle As long as LOCK remains asserted a bus hold request cannot be serviced Performing a locked move string operation can take several
292. operation with a crystal network OSCOUT does not three state ONCE Mode electrically isolates the device from the rest of the board logic This isolation allows a bed of nails tester to drive the device pins directly for more accurate and thorough testing An in circuit emulation probe uses ONCE Mode to isolate a surface mounted device from board log ic and essentially take over operation of the board without removing the soldered device from the board 13 1 ENTERING LEAVING ONCE MODE Forcing A19 ONCE low while RESIN is asserted low enables ONCE Mode see Figure 13 1 Maintaining A19 ONCE and RESIN low continues to keep ONCE Mode active Returning AT9 ONCE high exits ONCE Mode However it is possible to keep ONCE Mode always active by deasserting RESIN while keeping A19 ONCE low Removing RESIN latches ONCE Mode and allows A19 ONCE to be driven to any level A19 ONCE must remain low for at least one clock beyond the time RESIN is driven high Asserting RESIN exits ONCE Mode assuming A19 ONCE does not also remain low see Figure 13 1 RESIN A19 ONCE All output bidirectional weakly held pins except OSCOUT NOTES 1 Entering ONCE Mode 2 Latching ONCE Mode 3 Leaving ONCE Mode assuming 2 occurred A1260 0A Figure 13 1 Entering Leaving ONCE Mode 13 1 ONCE MODE 13 2 intel 0C186 Instruction Set Additions and Extensions APPENDIX A 800186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
293. opped is discarded SP SP 2 Instruction Operands lt SP 1 SP SF none SP e SP 2 TF DX lt SP 1 SP ZF SP SP 2 CX SP 1 SP SP SP 2 lt SP 1 SP SP lt SP 2 Pop Flags Flags lt SP 1 SP AE v POPF SP lt SP 2 BE f Transfers specific bits from the word at IF v the current top of stack pointed to by OF v register SP into the 8086 8088 flags Y replacing whatever values the flags SF v previously contained SP is then TF v incremented by two to point to the new ZF top of stack Instruction Operands none PUSH Push SP lt SP 2 AF PUSH src SP 1 SP src CF Decrements SP by two and then IF transfers a word from the source OF operand to the top of stack now PF pointed to by SP SF Instruction Operands TF PUSH reg PUSH seg reg CS legal PUSH mem NOTE The three symbols used in the Flags Affected column are defined as follows C 34 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued Name Description Operation PUSHA Push All temp lt SP AF PUSHA SP lt SP 2 GE
294. ord Cae bit of dest F destination operand to the left by the dest dest x 2 tmpcf OF v number of bits specified in the count temp lt temp 1 PF operand The carry flag CF is treated if SF as part of the destination operand count 1 TF that is its value is rotated into the low then ZF order bit of the destination and itself is if replaced by the high order bit of the high order bit of dest CF destination th en Instruction Operands OF 1 RCL reg n else RCL mem n OF 0 RCL reg CL else RCL mem CL OF undefined RCR Rotate Through Carry Right temp lt count AF RCR dest count do while temp 0 CF v tmpcf lt CF DF Operates exactly like RCL except that CF lt low order bit of dest IF the bits are rotated right instead of left dest lt dest 2 OF v Instruction Operands high order bit of dest lt tmpcf RCR reg n _ temp lt temp 1 SF RCR mem n if TF RCR reg CL count 1 ZF RCR mem CL then if high order bit of dest next to high order bit of dest then OF 1 else OF 0 else OF undefined NOTE The three symbols used in the Flags Affected column are defined as follows C 36 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed INSTRUCTION SE
295. otate instruction is executed r m EA Calculation mod Effect on EA Calculation 000 BX SI DISP 00 if r m 110 DISP 0 disp low and disp high are absent 00 BX DI DISP 00 if r m 110 EA disp high disp low 010 BP SI DISP 01 DISP disp low sign extended to 16 bits disp high is absent 01 BP DI DISP 10 DISP disp high disp low 100 51 DISP 11 r m is treated as a reg field 10 Dl DISP DISP follows the second byte of the instruction before any required data 110 BP T BOP if mog 00 Physical addresses of operands addressed by the BP register are computed disp high disp low if mod 00 using the SS segment register Physical addresses of destination operands of 11 BX DISP string primitives addressed by the DI register are computed using the ES seg ment register which cannot be overridden reg 16 bit w 1 8 bit w 0 TIT Instruction 000 AX AL 000 ROL 00 Cx CL 001 ROR 010 DX DL 010 RCL 01 BP BL 011 RCR 100 SP AH 100 SHL SAL 10 BP CH 101 SHR 110 SI DH 110 11 DI BH 111 SAR D 1 INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 2 Instruction Set Summary Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS MOV Move register to register memory 000100w mod reg r m 2 12 register memory to register 000101w mod reg r m 2 9 immediate to register memory 100011w mo
296. other ZF is cleared otherwise the result bit is cleared Instruction Operands XOR reg reg XOR reg mem XOR mem reg XOR accum immed XOR reg immed XOR mem immed NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 47 INSTRUCTION SET DESCRIPTIONS C 48 intel D Instruction Set Opcodes and Clock Cycles APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLES This appendix provides reference information for the 80C186 Modular Core family instruction set Table D 1 defines the variables used in Table D 2 which lists the instructions with their for mats and execution times Table D 3 is a guide for decoding machine instructions Table D 4 is a guide for encoding instruction mnemonics and Table D 5 defines Table D 4 abbreviations Table D 1 Operand Variables Variable Description mod mod and r m determine the Effective Address EA r m r m and mod determine the Effective Address EA reg reg represents a register MMM MMM and PPP are opcodes to the math coprocessor PPP PPP and MMM are opcodes to the math coprocessor TTT TTT defines which shift or r
297. owledges the pending interrupt just as if the CPU had started the interrupt vectoring sequence The Interrupt Control Unit updates the Interrupt Re quest In Service Poll and Poll Status registers as it does in the normal interrupt acknowledge sequence However the processor does not run an interrupt acknowledge sequence or fetch the vector from the vector table Instead software must read the interrupt type and execute the proper routine to service the pending interrupt Reading the Poll Status register Figure 8 12 will merely transmit the status of the polling bits without modifying any of the other Interrupt Controller registers Register Name Poll Register Register Mnemonic POLL Register Function Read to check for and acknowledge pending interrupts when polling A1208 A0 Bit Bit Nam Function Mnemonic trame unctio IREQ Interrupt This bit is set to indicate a pending interrupt Request VT4 0 Vector Type Contains the interrupt type of the highest priority pending interrupt NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 11 Poll Register 8 20 intel INTERRUPT CONTROL UNIT Register Name Poll Status Register Register Mnemonic POLLSTS Register Function Read to check for pending interrupts when polling A1209 A0 Bit Bit Nam Function Mnemonic
298. oying data in the lower bank To access even addressed 16 bit words two consecutive bytes with the least significant byte at an even address information is transferred over both halves of the data bus see Figure 3 3 A19 1 select the appropriate byte within each bank AO and BHE drive low to enable both banks simultaneously Odd addressed word accesses require the BIU to split the transfer into two byte operations see Figure 3 4 The first operation transfers data over the upper half of the bus while the second op eration transfers data over the lower half of the bus The BIU automatically executes the two byte sequence whenever an odd addressed word access is performed 3 2 A19 1 19 1 BUS INTERFACE UNIT D15 8 BHE High Odd Byte Transfer D15 8 BHE Low High A1104 0A Figure 3 2 16 Bit Data Bus Byte Transfers 3 3 BUS INTERFACE UNIT intel A19 1 D15 8 BHE Low A1107 0A Figure 3 3 16 Bit Data Bus Even Word Transfers During a byte read operation the BIU floats the entire 16 bit data bus even though the transfer occurs on only one half of the bus This action simplifies the decoding requirements for read only devices e g ROM EPROM Flash During the byte read an external device can drive both halves of the bus and the BIU automatically accesses the correct half During the byte write op eration the BIU drives both halves of the bus Information on the half of the bus not involved in
299. procedure ZF Second LEAVE pops the old value of BP from the stack to return to the calling procedure s stack frame A return RET instruction will remove arguments stacked by the calling procedure for use by the called procedure Instruction Operands none NOTE The three symbols used in the Flags Affected column are defined as follows C 26 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued Name Description Operation LES Load Pointer Using ES dest EA AF LES dest src ES lt EA 2 DF Transfers a 32 bit pointer variable from IF the source operand to the destination operand and register ES The offset PF word of the pointer is transferred to the SF destination operand The segment word of the pointer is transferred to ZF register ES Instruction Operands LES reg16 mem32 LOCK Lock the Bus none AF LOCK ae Causes the 8088 configured in IF maximum mode to assert its bus OF LOCK signal while the following PF instruction executes The instruction SF most useful in this context is an exchange register with memory ZF The LOCK prefix may be combined with the segment override and
300. ptions from interrupting the processor during the interrupt service routine 3 The current CS and IP are pushed onto the stack 4 The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt Vector Table and begins executing from that point The CPU is now executing the interrupt service routine The programmer must save usually by pushing onto the stack all registers used in the interrupt service routine otherwise their contents will be lost To allow nesting of maskable interrupts the programmer must set the Interrupt En able bit in the Processor Status Word When exiting an interrupt service routine the programmer must restore usually by popping off the stack the saved registers and execute an IRET instruction which performs the following steps 1 Loads the return CS and IP by popping them off the stack 2 Pops and restores the old Processor Status Word from the stack The CPU now executes from the point at which the interrupt or exception occurred 2 41 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel Interrupt Enable Bit Trap Flag Processor Status Word Code Segment Register Instruction Pointer Interrupt Vector Table A1029 0A Figure 2 26 Interrupt Sequence 2 3 1 1 Non Maskable Interrupts The Non Maskable Interrupt NMI is the highest priority interrupt It is usually reserved for a catastrophic event such as impending power failure An NMI cannot be preven
301. put disable RD high to output float 3 20 intel BUS INTERFACE UNIT Tacc and define the maximum data access requirements for the memory device These device parameters must be less than the value calculated in the equation column An equal to or greater than result indicates that wait states must be inserted into the bus cycle determines the maximum time the memory device can float its outputs before the next bus cycle begins A Tp value greater than the equation result indicates a buffer fight A buffer fight means two or more devices are driving the bus at the same time This can lead to short circuit conditions resulting in large current spikes and possible device damage Truax cannot lengthened other than by slowing the clock rate To resolve a buffer fight con dition choose a faster device or buffer the AD bus see Buffering the Data Bus on page 3 35 A19 16 RFSH A15 0 AD7 0 A1084 0A Figure 3 19 Typical Read Bus Cycle 3 21 BUS INTERFACE UNIT intel 3 5 1 1 Refresh Bus Cycles A refresh bus cycle operates similarly to a normal read bus cycle except for the following Fora 16 bit data bus address bit AO and BHE drive to a 1 high and the data value on the bus is ignored For an 8 bit data bus address bit AO drives to a 1 high and RFSH is driven active low The data value on the bus is ignored RFSH has the same bus timing as BHE 27C256 2
302. r a high to low transition The processor must remain in reset a minimum of 4 CLKOUT cycles after Vec and CLKOUT stabilize The hysteresis allows a simple RC circuit to drive the RESIN input see Figure 5 5 Typical applications can use about 100 mil liseconds as an RC time constant 5 6 intel CLOCK GENERATION AND POWER MANAGEMENT Reset may be either cold power up or warm Figure 5 6 illustrates a cold reset Assert the RES IN input during power supply and oscillator startup The processor s pins assume their reset pin states a maximum of 28 CLKIN periods after CLKIN and Vec stabilize Assert RESIN 4 addi tional CLKIN periods after the device pins assume their reset states Applying RESIN when the device is running constitutes a warm reset see Figure 5 7 In this case assert RESIN for at least 4 CLKOUT periods The device pins will assume their reset states on the second falling edge of CLKIN following the assertion of RESIN 100k typical RESET IN A1128 0A Figure 5 5 Simple RC Circuit for Powerup Reset The processor exits reset identically in both cases The rising RESIN edge generates an internal RESYNC pulse see Figure 5 8 resynchronizing the divide by two internal phase clock The clock generator samples RESIN on the falling CLKIN edge If RESIN is sampled high while CLKOUT is high the processor forces CLKOUT low for the next two CLKIN cycles The clock essentially skips a beat to synchronize the internal p
303. r disables the maskable interrupt request from the Interrupt Control Unit The programmer controls the Interrupt Enable bit with the STI set interrupt and CLI clear interrupt instructions Besides being globally enabled or disabled by the Interrupt Enable bit each interrupt source can be individually enabled or disabled The Interrupt Mask register has a single bit for each interrupt source The programming can selectively mask disable or unmask enable each interrupt source by setting or clearing the corresponding bit in the Interrupt Mask register 8 1 1 2 Interrupt Priority One critical function of the Interrupt Control Unit is to prioritize interrupt requests When multi ple interrupts are pending priority determines which interrupt request is serviced first In many systems an interrupt handler may itself be interrupted by another interrupt source This is known as interrupt nesting With interrupt nesting priority determines whether an interrupt source can preempt an interrupt handler that is currently executing Each interrupt source is assigned a priority between zero highest and seven lowest After reset the interrupts default to the priorities shown in Table 8 1 Because the timers share an interrupt source they also share a priority Within the assigned priority each has a relative priority Timer has the highest relative priority and Timer 2 has the lowest The serial channel 0 receive and transmit interrupts also sh
304. r inactive state Figure 3 3 lists the state of each pin after entering the HALT bus state Table 3 6 HALT Bus Cycle Pin States Pin State Pin s No Powerdown Powerdown or Idle Mode or Idle Mode AD15 0 AD7 0 for 8 bit Float Drive Zero A15 8 8 bit Drive Address Drive Zero A19 16 Drive 8H or Zero Drive Zero BHE 16 bit Drive Last Value Drive One RD WR DEN DT R RFSH 8 bit S2 0 Drive One Drive One 3 29 BUS INTERFACE UNIT intel T1 TI TI CLKOUT 52 0 011 AD15 0 AD7 0 Note A15 8 Note A19 16 v c RFSH 1 NOTE The AD15 0 AD7 0 bus can be floating driving a previous write data value or driving the next instruction prefetch address value For an 8 bit device A15 8 either drives the previous bus address value or the next instruction prefetch address value A1066 0A Figure 3 25 HALT Bus Cycle 3 5 5 Temporarily Exiting the HALT Bus State A refresh request or bus hold request causes the BIU to exit the HALT bus state temporarily This can occur only when in the Active or Idle power management mode The BIU returns to the HALT bus state after it completes the desired bus operation However the BIU does not execute another bus HALT cycle i e ALE and bus cycle status are not regenerated Figures 3 26 and 3 27 illustrate how the BIU temporarily exits and then returns to the HALT bus state 3 30 intel BUS INTERFACE UNIT
305. r m w i r m Shift Shift Shift Shift AAM AAD XLAT Dx b w b v LOOPNZ LOOPZ LOOP JCXZ IN IN OUT OUT Ex LOOPNE LOOPE LOCK REP REP HLT CMC Grp1 Grp1 Fx 2 b r m w r m NOTE Table D 5 defines abbreviations used in this matrix Shading indicates reserved opcodes D 20 intel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 4 Mnemonic Encoding Matrix Right Half x8 x9 xA xB xC xD xE xF OR OR OR OR OR OR PUSH Ox b f r m w f r m b t r m w t r m bii wi cs SBB SBB SBB SBB SBB SBB PUSH POP 1x b f r m w f r m b t r m w t r m w i DS DS SUB SUB SUB SUB SUB SUB SEG DAS 2x b f r m w f r m b t r m w t r m bii wi CS CMP CMP CMP CMP CMP CMP SEG AAS 3x b f r m w f r m b t r m w t r m w i DS DEC DEC DEC DEC DEC DEC DEC DEC 4x AX CX DX BX SP BP SI DI POP POP POP POP POP POP POP POP 5x AX CX DX BX SP BP SI DI PUSH IMUL PUSH IMUL INS INS OUTS OUTS 6x w i w i bii w i b w b w JS JNS JP JNP JL JNL JLE JNLE JPE JPO JNGE JGE JNG JG 7x MOV MOV MOV MOV MOV LEA MOV POP 8x b f r m w f r m b t r m w t r m sr f r m sr t r m r m CBW CWD CALL WAIT PUSHF POPF SAHF LAHF 9x L D TEST TEST STOS STOS LODS LODS SCAS SCAS Ax b ia w ia MOV MOV MOV MOV MOV MOV MOV MOV Bx i gt AX i gt CX i2DX i2BX iSP iBP 1 91 iDI ENTER LEAVE RET RET INT INT INTO IRET Cx V i SP l type 3 any ESC ESC ESC ESC ESC ESC ESC ESC Dx 0 1 2 3 4 5 6 7 CALL JMP JMP JMP IN IN OUT OUT Ex C
306. r the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 11 INSTRUCTION SET DESCRIPTIONS intel Table C 4 Instruction Set Continued E Flags Name Description Operation Affected DEC Decrement dest lt dest 1 AF DEC dest En a Subtracts one from the destination IF operand The operand may be a byte OF v or a word and is treated as an PF Y unsigned binary number see AAA and SF v DAA TF Instruction Operands ZF v DEC reg DEC mem NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued EM Flags Name Description Operation Affected DIV Divide When Source Operand is a Byte AF DIV src temp lt byte src d Performs an unsigned division of the if IF P accumulator and its extension by the temp AX gt OF source operand then type 0 interrupt is generated BE gt NS SP lt SP If the source operand is a byte it is SP 1 SP FLAGS SF divided into the two byte dividend IF 0 TF assumed to be in r
307. ransfers byte or a word from the IF source operand to the destination OF operand PF Instruction Operands MOV TF MOV accum mem ZF MOV reg reg MOV reg mem MOV mem reg MOV reg immed MOV mem immed MOV seg reg reg16 MOV seg reg mem16 MOV reg16 seg reg MOV mem16 seg reg NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 29 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel fare Flags Name Description Operation Affected MOVS Move String dest string lt src string AF MOVS dest string src string B zj Transfers a byte or a word from the IF source string addressed by Sl to the OF destination string addressed by DI PF and updates SI and DI to point to the SF next string element When used in TF conjunction with REP MOVS ZF performs a memory to memory block transfer Instruction Operands MOVS dest string src string MOVS repeat dest string src string MUL Multiply When Source Operand is a Byte AF MUL src lt AL x src ER Performs unsigned multiplication of if IF the source operand and the accumu AH OF v lator If the source is
308. re 7 800186 INSTRUCTION SET ADDITIONS AND EXTENSIONS intel BOUND register address BOUND verifies that the signed value in the specified register lies within specified limits If the value does not lie within the bounds an array bounds exception type 5 occurs BOUND is useful for checking array bounds before attempting to access an array element This prevents the pro gram from overwriting information outside the limits of the array BOUND has two operands The first register specifies the register being tested The second ad dress contains the effective relative address of the two signed boundary values The lower limit word is at this address and the upper limit word immediately follows The limit values cannot be register operands if they are an invalid opcode exception occurs A 2 80C186 INSTRUCTION SET ENHANCEMENTS This section describes ten instructions that were available with the 8086 8088 but have been en hanced for the 80C186 Modular Core family Data transfer instructions PUSH Arithmetic instructions IMUL Bit manipulation instructions shifts and rotates SAL SHL SAR SHR ROL ROR RCL RCR 21 Data Transfer Instructions PUSH data PUSH push immediate allows an immediate argument data to be pushed onto the stack The value can be either a byte or a word Byte values are sign extended to word size before being pushed A 8 intel 80C186 INST
309. reaches its maximum count See Table 9 1 for a summary of clock sources for Timers 0 and 1 Timer 2 must be initialized and running in order to increment values in other timer counters Table 9 1 Timer 0 and 1 Clock Sources EXT P Clock Source 0 0 Timer clocked internally at v4 CLKOUT frequency 0 1 Timer clocked internally prescaled by Timer 2 1 X Timer clocked externally at up to 4 CLKOUT frequency 9 2 3 Counting Modes All timers have a Timer Count register and a Maxcount Compare A register Timers 0 and 1 also have access to a second Maxcount Compare B register Whenever the contents of the Timer Count register equal the contents of the Maxcount Compare register the count register resets to zero The maximum count value will never be stored in the count register This is because the counter element increments compares and resets a timer in one clock cycle Therefore the max imum value is never written back to the count register The Maxcount Compare register can be written at any time during timer operation 9 12 intel TIMER COUNTER UNIT The timer counting from its initial count usually zero to its maximum count either Maxcount Compare A or B and resetting to zero defines one timing cycle A Maxcount Compare value of 0 implies a maximum count of 65536 a Maxcount Compare value of implies a maximum count of 1 etc Only equivalence between the Timer Count and Maxcount Compare registers is checke
310. ress Register 7 7 2 2 Refresh Clock Interval Register The Refresh Clock Interval Register Figure 7 7 defines the time between refresh requests The higher the value the longer the time between requests The down counter decrements every fall ing CLKOUT edge regardless of core activity When the counter reaches one the Refresh Con trol Unit generates a refresh request and the counter reloads the value from the register 7 8 intel REFRESH CONTROL UNIT Register Name Refresh Clock Interval Register Register Mnemonic RFTIME Register Function Sets refresh rate 15 R R C C 8 7 A1288 0A Reset State Bit Function Mnemonic unctio Bit Name RC8 0 Refresh Counter 000H Sets the desired clock count between refresh Reload Value cycles NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 7 7 Refresh Clock Interval Register 7 7 2 3 Refresh Control Register Figure 7 8 shows the Refresh Control Register The user may read or write the REN bit at any time to turn the Refresh Control Unit on or off The lower nine bits contain the current nine bit down counter value The user cannot program these bits Disabling the Refresh Control Unit clears both the counter and the corresponding counter bits in the control register REFRESH CONTROL UNIT Register Name Register Mnemonic Re
311. rol Unit INTO and INT1 must be programmed for level triggered interrupts 8 2 7 Additional Latency and Response Time The Interrupt Control Unit adds 5 clocks to the interrupt latency of the CPU Cascade mode adds 13 clocks to the interrupt response time because the CPU must run the interrupt acknowledge bus cycles See Figure 8 3 on page 8 11 and Figure 2 27 on page 2 46 intel INTERRUPT CONTROL UNIT Interrupt presented to control unit Interrupt presented to CPU Cascade Mode Only 5 if not cascade mode PUSH FLAGS IDLE PUSH CS PUSH IP 5 gt 4 2 4 5 4 3 4 4 4 3 4 4 5 First instruction fetch from interrupt routine A1212 A0 Figure 8 3 Interrupt Control Unit Latency and Response Time 8 3 PROGRAMMING THE INTERRUPT CONTROL UNIT Table 8 3 lists the Interrupt Control Unit registers with their Peripheral Control Block offset ad dresses The remainder of this section describes the functions of the registers Table 8 3 Interrupt Control Unit Registers Register Name Offset Address INT3 Control 1EH INT2 Control 1CH INT1 Control 1AH INTO Control 18H INT4 Control 16H Serial Control 14H Timer Control 12H Interrupt Status 10H Interrupt Request OEH 8 11 INTERRUPT CONTROL UNIT intel Table 8 3 Interrupt Control Unit Registers Continued Register Name Offset Address In Service 0CH Priority Mask OAH Interrupt Mask 08H Poll
312. ruction is executed NOTE The 8 bit bus version of the device automatically traps an ESC opcode to the Type 7 interrupt regardless of the state of the ET bit Memory I O The MEM bit specifies the PCB location Set MEM to locate the PCB in memory space or clear it to locate the PCB in I O space PCB Base R19 8 define the upper address bits of the PCB Address base address All lower bits are zero R19 16 are Upper Bits ignored when the PCB is mapped to I O space NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 4 1 PCB Relocation Register intel PERIPHERAL CONTROL BLOCK Table 4 1 Peripheral Control Block del Function aont Function diet Function pias Function 00H Reserved 40H T2CNT 80H GCSOST COH Reserved 02H EOI 42H T2CMPA 82H GCSOSP C2H Reserved 04H POLL 44H Reserved 84H GCS1ST C4H Reserved 06H POLLSTS 46H T2CON 86H GCS1SP C6H Reserved 08H IMASK 48H Reserved 88H GCS2ST C8H Reserved OAH PRIMSK 4AH Reserved 8AH GCS2SP CAH Reserved OCH INSERV 4CH Reserved 8CH GCS3ST CCH Reserved OEH REQST 4EH Reserved 8EH GCS3SP CEH Reserved 10H INSTS 50H P1DIR 90H GCS4ST DOH Reserved 12H TCUCON 52H P1PIN 92H GCS4SP D2H Reserved 14H SCUCON 54H P1CON 94H GCS5ST D4H Reserved 16H IACON 56H P1LTCH 96H GCS5SP D6H Reserved 18H IOC
313. rupt handlers with maskable in terrupts disabled Maskable interrupts remain disabled until either the IRET instruction restores the Interrupt Enable bit or the programmer explicitly enables interrupts Enabling maskable in terrupts within an interrupt handler allows interrupts to be nested Otherwise interrupts are pro cessed sequentially one interrupt handler must finish before another executes The simplest way to use the Interrupt Control Unit is without nesting The operation and servicing of all sources of maskable interrupts is straightforward However the application tradeoff is that an interrupt handler will finish executing even if a higher priority interrupt occurs This can add considerable latency to the higher priority interrupt In the simplest terms the Interrupt Control Unit asserts the maskable interrupt request to the CPU waits for the interrupt acknowledge then presents the interrupt type of the highest priority un masked interrupt to the CPU The CPU then executes the interrupt handler for that interrupt Be cause the interrupt handler never sets the Interrupt Enable bit it can never be interrupted The function of the Interrupt Control Unit is more complicated with interrupt nesting In this case an interrupt can occur during execution of an interrupt handler That is one interrupt can preempt another Two rules apply for interrupt nesting Aninterrupt source cannot preempt interrupts of higher priority An in
314. rupt originates in software or with an NMI Non Maskable Interrupt Table 2 10 Interpretation of Conditional Transfers Mnemonic Condition Tested Jump if JA JNBE CF or ZF 0 above not below nor equal JAE JNB CF 0 above or equal not below JB JNAE CF 1 below not above nor equal JBE JNA CF or ZF 1 below or equal not above JC CF 1 carry JE JZ ZF 1 equal zero JG JNLE SF xor OF or ZF 0 greater not less nor equal JGE JNL SF xor OF 0 greater or equal not less JL JNGE SF xor OF 1 less not greater nor equal JLE JNG SF xor OF or ZF 1 less or equal not greater JNC CF 0 not carry JNE JNZ ZF 0 not equal not zero JNO OF 0 not overflow JNP JPO PF 0 not parity parity odd JNS SF 0 not sign JO OF 1 overflow JP JPE PF 1 parity parity equal JS SF 1 sign NOTE The terms above and below refer to the relationship of two unsigned values greater and less refer to the relationship of two signed values 2 26 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 2 1 6 Processor Control Instructions Processor control instructions see Table 2 11 allow programs to control various CPU functions Seven of these instructions update flags four of them are used to synchronize the microprocessor with external events and the remaining instruction causes the CPU to do nothing Except for flag operations processor control instructions do not affect the flags Table 2 11 Processor Control Instructions Flag Operatio
315. ry addressing mode see Figure 2 13 No registers are in volved and the effective address is taken directly from the displacement of the instruction Pro grammers typically use direct addressing to access scalar variables With register indirect addressing the effective address of a memory operand can be taken directly from one of the base or index registers see Figure 2 14 One instruction can operate on various memory locations if the base or index register is updated accordingly Any 16 bit general register can be used for register indirect addressing with the JMP or CALL instructions In based addressing the effective address is the sum of a displacement value and the contents of the BX or BP register see Figure 2 15 Specifying the BP register as a base register directs the Bus Interface Unit to obtain the operand from the current stack segment unless a segment over ride prefix is present This makes based addressing with the BP register a convenient way to ac cess stack data Mod R M Displacement A1016 0A Figure 2 13 Direct Addressing 2 30 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE A1017 0A A1018 0A Figure 2 15 Based Addressing Based addressing provides a simple way to address data structures that may be located in different places in memory see Figure 2 16 A base register can be pointed at the structure Elements of the structure can then be addressed by their displacements Different copies
316. s ax dx dx P1CON get state of port 1 controls ax dx ax Of0h make sure P1 0 P1 3 is port dx ax dx P2CON set P2 1 for TXD1 P2 0for RXD1 ax Offh dx ax dx PILTCH make sure TXD latch is tristated ax TriStateDis dx ax set P1 7 to zero dx S1CON Select control register ax 0022h receive Mode 2 dx ax SelStatus dx S1STS Select status register Check 4 RI ax dx get status ax 0040h data waiting Check 4 RI no then keep checking dx S1SRUF yes then get data ax dx al My Address is slave 1 being addressed SelStatus no then ignore dx S1CON yes then switch to Mode 3 transmit ax 0003h Mode 3 dx ax dx PILTCH enable tristate buffer ax TriStateEna dx ax gate TXD onto master s RXD dx SITBUF echo My Address to the master ax My Address dx ax dx S1CON Switch to receive mode ax 0023h Mode 3 receive dx ax Wait 4 Cmd dx S1STS Select status register i ax dx get status ax 0040h command waiting Wait 4 Cmd no then keep checking dx SIRBUF yes then get command ax dx al Disconnect Disconnect command DisconnectMode yes then disconnect RXD from network Example 10 5 Master Slave The slave 1 Routine Continued 10 33 SERIAL COMMUNICATIONS UNIT intel al FlashLEDs Flash LEDs command Wait 4 Cmd no then ignore dx PILTCH yes then flash LEDs 10 times Cx 20 ax ax ax dx ax bx Offffh bx Dly1
317. s Odd Word Transfers senes 3 5 8 Bit Data Bus Word Transfers enne 3 6 Typical B s Gycle rer eee qud 3 8 T State Relation to CLKOUT sese ne nennen neret 3 8 BIU State DIagratm n RH OE ORE EDU daze Ee ERE E cA 3 9 T Statevand B us Phases 2 deae etenim a E A A 3 10 Address Status Phase Signal Relationships 3 11 Demultiplexing Address 3 12 Data Phase Signal Relationships ssseeeneeneeeee 3 14 Typical Bus Cycle with Wait States sessssssssseeeene eene 3 15 READY Pin Block Diagrarn tere eet oe Dent 3 15 intel deere Figure 3 15 3 16 3 17 3 18 3 19 3 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 3 28 3 29 3 30 3 31 3 32 3 33 3 34 3 35 3 36 4 1 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 10 5 11 5 12 5 13 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 FIGURES Page Generating a Normally Not Ready Bus 3 16 Generating a Normally Ready Bus Signal sees 3 17 Normally Not Ready System Timing essseeeeeeneneneneen 3 18 Normally Ready System Timings sssssseeeeeeeeneee nennen 3 19 Typical Read Bus Cycle xd Spe RR HERR ERR HRS
318. s SF v changed If a TEST instruction is followed by a JNZ jump if not zero JE instruction the jump will be taken if there are any corresponding one bits in both operands Instruction Operands TEST reg reg TEST reg mem TEST accum immed TEST reg immed TEST mem immed NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 45 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel E Flags Name Description Operation Affected WAIT Wait None AF WAIT B Causes the CPU to enter the wait state IF while its test line is not active OF Instruction Operands PF none SF TF ZF XCHG Exchange temp lt dest AF XCHG dest src dest lt src cF src lt temp DF Switches the contents of the source IF and destination operands bytes or OF words When used in conjunction with PF the LOCK prefix XCHG can test and SF Set a semaphore that controls access TF to a resource shared by multiple ZF processors Instruction Operands XCHG accum reg XCHG mem reg XCHG reg reg NOTE The three symbols used in the Flags Affected column are defined as follows C 46 the contents of the flag re
319. s cycles in the interrupt acknowledge sequence NOTE Due to an internal condition external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block PCB is located at 0000H in I O space In this case wait states cannot be added to interrupt acknowledge bus cycles However you can add wait states to interrupt acknowledge cycles if the PCB is located at any other address 3 5 3 1 System Design Considerations Although ALE is generated for both bus cycles the BIU does not drive valid address information Actually all address bits except A19 16 float during the time ALE becomes active on both 8 and 16 bit bus devices Address decoding circuitry must be disabled for Interrupt Acknowledge bus cycles to prevent erroneous operation Processor 82C59A A1065 0A Figure 3 24 Typical 82C59A Interface 3 27 BUS INTERFACE UNIT intel 3 5 4 HALT Bus Cycle Suspending the CPU reduces device power consumption and potentially reduces interrupt latency time The HLT instruction initiates two events 1 Suspends the Execution Unit 2 Instructs the BIU to execute a HALT bus cycle The Idle or Powerdown power management mode or the absence of both of them known as Ac tive Mode affects the operation of the bus HALT cycle The effects relating to BIU operation and the HALT bus cycle are described in this chapter Chapter 4 Clock Generation and Power Management discusses the concepts of Acti
320. s in bytes IO_WAITEQU 4 Wait states DMA_BASEEQU 512 Start address in bytes DMA WAITEQU 0 Wait states Size assumed to be 64 bytes The GCSO and GCS2 START and STOP register values are calculated using the above system contraints and the equations below GCS2ST VALEQU IO BASE 64 SHL 6 OR IO WAIT GCS2SP VALEQU IO BASE 64 OR IO SIZE 64 SHL 6 OR CSEN OR IO GCSOST VALEQU DMA BASE 64 SHL 6 OR DACK WAIT GCSOSP VALEQU DMA BASE 64 1 SHL 6 OR CSEN OR IO The following statements define the default assumptions for SEGMENT locations ASSUMECS CODE ASSUMEDS DATA ASSUMESS DATA ASSUMEES DATA CODE SEGMENT PUBLIC CODE ENTRY POINT ON POWER UP The power on or reset code does a jump here after the UCS register is programmed FW STARTLABEL FAR Forces far jump CLI Make sure interrupts are globally disabled Place register initialization code here Example 6 1 Initializing the Chip Select Unit Continued intel CHIP SELECT UNIT 7 SET UP CHIP SELECTS UCS EPROM Select LCS SRAM Select GCS1 DRAM Select GCS2 FLOPPY Select GCSO DMA Select MOV DX UCSSP Finish setting up UCS MOV AX UCSSP_VAL OUT DX AL Remember byte writes work MOV DX LCSST Set up LCS MOV AX CSST_VAL OUT DX L MOV DX CSSP MOV AX CSSP VAL OUT DX L Remember byte writes MOV DX CS1ST Set up GCS1 MOV AX CS1ST VAL OUT DX L MOV AX CS1SP VAL MOV DX CS1SP OUT DX L Reme
321. s inputs synchronizing B 2 Auxiliary Flag AF 2 7 2 9 AX register 2 1 2 5 2 18 2 23 3 6 Base Pointer BP See BP register Baud Rate Compare Register BxCMP 10 12 Baud Rate Counter Register BxCNT 10 11 BBS 1 5 BCD defined 2 37 Bit manipulation instructions 2 21 2 22 BOUND instruction 2 44 A 8 BP register 2 1 2 13 2 30 2 34 Breakpoint interrupt Type 3 exception 2 44 Bus cycles 3 20 3 45 address status phase 3 10 3 12 and 80C187 12 11 and CSU 6 14 and Idle mode 5 13 and PCB accesses 4 4 and Powerdown mode 5 16 Index 1 INDEX and T states 3 9 data phase 3 13 HALT cycle 3 28 3 34 and chip selects 6 4 HALT state exiting 3 30 3 34 idle states 3 18 instruction prefetch 3 20 interrupt acknowledge INTA cycles 3 6 3 25 3 26 8 9 and chip selects 6 4 operation 3 7 3 20 priorities 3 44 3 45 7 2 read cycles 3 20 3 21 refresh cycles 3 22 7 4 7 5 control signals 7 5 7 6 during HOLD 3 41 3 43 7 13 7 14 wait states 3 13 3 18 write cycles 3 22 3 25 See also Data transfers Bus hold protocol 3 39 3 44 and CLKOUT 5 6 and CSU 6 15 and Idle mode 5 14 and refresh cycles 3 41 3 43 7 13 7 14 and reset 5 9 latency 3 40 3 41 Bus Interface Unit BIU 2 1 2 3 2 11 3 1 3 45 and DRAM refresh requests 7 4 and TCU 9 1 buffering the data bus 3 35 3 37 modifying interface 3 34 3 37 3 37 relationship to RCU 7 1 synchronizing software and hardware e
322. s located in I O space BOCMP equ Oxxxx channel SOCON equ Oxxxx channel baud rate compare control SORBUF equ Oxxxx channel receive buffer SOTBUF equ Oxxxx channel transmit buffer RI TYPE equ receive is interrupt type 20 TI TYPE equ 21 transmit is interrupt type 21 EOI equ Off02h end of interrupt register SCUCON equ Off14h SCU interrupt control register 0 0 SOSTS equ Oxxxx channel 0 status 0 0 code seg segment public assume cs code_seg ASYNC CHANNEL SETUP proc near First set up the interrupt handler vectors ax ax mov ds ax need DS to point to interrupt vector table at Oh mov bx RI TYPE 4 mov ax offset ASYNC REC INT PROC mov bx ax mov ax seg ASYNC REC INT PROC mov bx 2 ax Example 10 1 Asynchronous Mode 4 Example 10 23 SERIAL COMMUNICATIONS UNIT intel mov bx TI TYPE 4 mov ax offset ASYNC XMIT INT PROC mov bx ax mov seg ASYNC XMIT INT PROC mov bx 2 ax Now set up channel 0 options mov ax 8067h for 9600 baud from 16MHz CPU clock mov dx BOCMP out dx ax Set baud rate mov ax 0059H CEN 1 CTS enabled REN 0 receiver not yet enabled EVN 1 even parity PEN 1 parity turned on MODE 1 10 bit frame mov dx S0CON out dx ax write to serial control register Clear any pending RI or TI just for safety mov dx S0STS in ax dx Cclear any old RI or TI Clear interrupt mask bit in interrupt unit to allow SCU interrupts mov dx S
323. s the same sign as IF 0 the dividend TF lt 0 SP lt SP Instruction Operands SP 1SP lt CS IDIV reg CS 2 IDIV mem SP lt SP SP 1 SP lt IP IP lt 0 else lt temp DX AX DX lt temp 96 DX AX NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued MON Flags Name Description Operation Affected IMUL Integer Multiply When Source Operand is a Byte AF IMUL src lt byte src x AL 5 Performs a signed multiplication of the IF 9 source operand and the accumulator AH sign extension of AL OF v If the source is a byte then it is then PF multiplied by register AL and the CF 0 SF double length result is returned in AH else IF and AL If the source is a word then it CF lt 1 ZF ioli OF CF is multiplied by register AX and the double length result is returned in When Source Operand is a Word registers DX and AX If the upper half DX AX lt word src AX of the result AH for byte source DX if for word source is not the sign DX sign extension of AX extension
324. scribe each port type The bidirectional port is described in detail as it is the basis for all of the other port types The descriptions for the unidirectional and open drain ports only highlight their specific differences from the common bidirectional module 11 1 1 Bidirectional Port Figure 11 1 shows a simplified schematic of a bidirectional port pin The overall function of a bidirectional port pin is controlled by the state of the Port Control Latch The output of the Port Control Latch selects the source of output data and the source of the control signal for the three state output driver When the port is programmed to act as a peripheral pin both the data for the pin and the directional control signal for the pin come from the associated integrated peripheral When a bidirectional port pin is programmed as an I O port all port parameters are under soft ware control The output of the Port Direction latch enables or disables the three state output driver when the pin is programmed as an I O port The three state output driver is enabled by clearing the Port Direction latch The data driven on an output port pin is held in the Port Data latch Setting the Port Direction latch disables the three state output driver making the pin an input The signal present on the device pin is routed through a synchronizer to a three state latch that connects to the internal data bus The state of the pin can be read at any time regardless of wheth
325. serted before entering the power management mode CLOCK GENERATION AND POWER MANAGEMENT 5 20 intel Chip Select Unit intel CHAPTER 6 CHIP SELECT UNIT Every system requires some form of component selection mechanism to enable the CPU to ac cess a specific memory or peripheral device The signal that selects the memory or peripheral de vice is referred to as a chip select Besides selecting a specific device each chip select can be used to control the number of wait states inserted into the bus cycle Devices that are too slow to keep up with the maximum bus bandwidth can use wait states to slow the bus down 6 1 COMMON METHODS FOR GENERATING CHIP SELECTS One method of generating chip selects uses latched address signals directly An example inter face is shown in Figure 6 1 A In the example an inverted A16 is connected to an SRAM device with an active low chip select Any bus cycle with an address between 10000H and 1FFFFH A16 1 enables the SRAM device Also note that any bus cycle with an address starting at 30000H 50000H 70000H and so on also selects the SRAM device Decoding more address bits solves the problem of a chip select being active over multiple address ranges In Figure 6 1 B a one of eight decoder is connected to the uppermost address bits Each decoded output is active for one eighth of the 1 Mbyte address space However each chip select has a fixed starting address and range Future system memory chang
326. served by Intel These eight bytes locations O0F8H through OOFFH control the interface to an 80C187 math coprocessor A chip select can overlap this reserved space provided there is no in tention of using the 80C187 However to avoid possible future compatibility issues Intel recom mendis that no chip select start at I O address location 00COH 6 14 intel CHIP SELECT UNIT The GCS chip select outputs are multiplexed with output port functions The register that controls the multiplexed outputs resides in the I O Port Unit See Table 11 1 on page 11 7 and Figure 11 5 on page 11 8 6 5 CHIP SELECTS AND BUS HOLD The Chip Select Unit decodes only internally generated address and bus state information An ex ternal bus master cannot make use of the Chip Select Unit During HLDA all chip selects remain inactive The circuit shown in Figure 6 9 allows an external bus master to access a device during bus HOLD CSU Chip Select oL Device select External Master Chip Select A1167 0A Figure 6 9 Using Chip Selects During HOLD 6 6 EXAMPLES The following sections provide examples of programming the Chip Select Unit to meet the needs of a particular application The examples do not go into hardware analysis or design issues 6 6 1 Example 1 Typical System Configuration Figure 6 10 illustrates a block diagram of a typical system design with a 128 Kbyte EPROM and a 32 Kbyte SRAM The peripherals are mapped to I O address
327. short label 7F 0111 1111 IP inc 8 jnle jg short label 80 1000 0000 mod 000 r m disp lo disp hi data 8 add reg8 mem8 immed8 mod 001 r m disp lo disp hi data 8 or reg8 mem8 immed8 mod 010 r m disp lo disp hi data 8 adc reg8 mem8 immed8 mod 011 r m disp lo disp hi data 8 sbb reg8 mem8 immed8 mod 100 r m disp lo disp hi data 8 and reg8 mem8 immed8 mod 101 r m disp lo disp hi data 8 sub reg8 mem8 immed8 mod 110 r m disp lo disp hi data 8 xor reg8 mem8 immed8 mod 111 r m disp lo disp hi data 8 cmp reg8 mem8 immed8 81 1000 0001 mod 000 r m disp lo disp hi data lo data hi add reg16 mem16 immed16 mod 001 r m disp lo disp hi data lo data hi or reg16 mem16 immed16 mod 010 r m disp lo disp hi data lo data hi adc reg16 mem16 immed16 mod 011 r m disp lo disp hi data lo data hi sbb reg16 mem16 immed16 mod 100 r m disp lo disp hi data lo data hi and reg16 mem16 immed16 81 1000 0001 mod 101 r m disp lo disp hi data lo data hi sub reg16 mem16 immed16 mod 110 r m disp lo disp hi data lo data hi xor reg16 mem16 immed16 mod 111 r m disp lo disp hi data lo data hi cmp reg16 mem16 immed16 82 1000 0010 mod 000 r m disp lo disp hi data 8 add reg8 mem8 immed8 mod 001 r m x mod 010 r m disp lo disp hi data 8 adc reg8 mem8 immed8 mod 011 r m disp lo disp hi data 8 sbb reg8 mem8 immed8 mod 100 r m mod 101 r m disp lo disp hi data 8 sub reg8 mem8 immed8 mod 110 r m mod 11
328. space Example 6 1 shows a pro gram template for initializing the Chip Select Unit 6 15 CHIP SELECT UNIT intel FAN a 1146 0 Figure 6 10 Typical System intel CHIP SELECT UNIT TITLE Chip Select Unit Initialization MOD186XREF NAME CSU EXAMPLE 1 External reference from this module include File declares Register Locations and names Module equates Configuration equates TRUE EQU OFFH FALSE EQU NOT TRUE READY EQU 0001H Bus ready control modifier CSEN EQU 0008H Chip Select enable modifier ISTOP EQU 0004H Stop address modifier MEM EQU 0002H Memory select modifier IO EQU 0000H I O select modifier Below is a list of the default system memory and I O environment These defaults configure the Chip Select Unit for proper system operation EPROM memory is located from 0E0000 to OFFFFF 128 Kbytes Wait states are calculated assuming 16MHz operation UCS4 controls the accesses to EPROM memory space EPROM SIZEEQU 128 Size in Kbytes EPROM BASEEQU 1024 EPROM SIZE Start address in Kbytes EPROM WAITEQU 1 Wait states The UCS START and STOP register values are calculated using the above system constraints and the equations below UCSST VALEQU EPROM BASE SHL 6 OR EPROM WAIT UCSSP VALEQU CSEN OR ISTOP OR MEM SRAM memory starts at OH and continues to 7FFFH 32 Kbytes Wait states are calculated assuming 16MHz operation LCS contr
329. ss location An I O mapped chip select can start and end on any 64 byte address location The chip selects typically associate with memory and peripheral devices as follows 6 2 Ignore Stop Address ISTOP Memory lO Selector MEM Internal Address Bus Address Shifter Value 2 Comparator CHIP SELECT UNIT Chip Select Enable CSEN Chip Select Peripheral Control Block Access Indicator A1160 0A Figure 6 2 Chip Select Block Diagram Mapped to the upper memory address space selects the BOOT memory device Mapped to the lower memory address space selects a static memory SRAM device that stores the interrupt vector table local stack local data and scratch EPROM or Flash memory types LCS pad data GCS7 0 Mapped to memory or I O address space selects additional SRAM memory DRAM memory local peripherals system bus etc 6 3 CHIP SELECT UNIT intel 1 1 1 1 1 1 1 1 Address Valid 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 l 1 1 1 1 1 1 1 1 i _ HC 1150 0 Figure 6 3 Chip Select Relative Timings A chip select goes active when it meets all of the following criteria 1 The chip select is enabled 2 The bus cycle status matches the programmed type memory or I O 3 The bus cycle address is equal to or greater than the start address value 4 The bus cycle address is less than the stop address value or the stop ad
330. ssing Reserved Locations ssseeeeenee 4 6 4 5 SETTING THE PCB BASE LOCATION nennen nnnm nennen 4 6 4 5 1 Considerations for the 80C187 Math Coprocessor Interface 4 7 CHAPTER 5 CLOCK GENERATION AND POWER MANAGEMENT 5 1 CLOCK GENERATION teret er cr nien deii olet eds 5 1 5 1 1 Grystal Oscillator teinte ie ties per In er 5 1 5 1 1 1 Oscillator OPSratiOn secus o cas coto reote rmt eee emeret tees 5 2 5 1 1 2 Selecting Crystals ae ae eere eicere ec c deme teed ee ae 5 5 5 1 2 Using an External Oscillatot 5 eet DR HIERO Ran 5 6 5 1 3 Output from the Clock Generator sssseeeeeeeeenneneneneneenn 5 6 5 1 4 Reset and Clock Synchronization sssssseeeeeeneeeeenen nenne 5 6 5 2 POWER MANAGEMBENT reete edente tede Pe evita edocs 5 10 5 2 1 Idle Mode bett ER Be ette dea b bn Gi 5 11 5 2 1 1 Entering Idle Mode esee nnnm niens 5 11 5 2 1 2 Bus Operation During Idle Mode sseeemn ene 5 13 5 2 1 3 Leaving Idle Mode select nennen nme 5 14 5 2 1 4 Example Idle Mode Initialization Code 5 15 5 2 2 Powerdowrn Mode omine tete Gn Da pause DE e 5 16 5 2 2 1 Entering Powerdown Mode seeeen meer 5 17 5 2 2 2 Leaving Powerdown Mode seem rennes 5 18 5 2 8
331. ssume cs lib 80C186 public power mgt power mgt proc far push bp Save caller s bp mov bp sp get current top of stack push ax save registers that will push dx be modified equ word 6 get parameter off the Stack mov dx PWRCON Select Power Control Reg mov ax mode get mode and ax 3 mask off unwanted bits out dx ax hlt enter mode pop dx restore saved registers pop ax pop bp restore caller s bp ret power mgt endp lib 80C186 ends end Example 5 1 Initializing the Power Management Unit for Idle or Powerdown Mode 5 2 2 Powerdown Mode Powerdown mode freezes the clock to the entire device core and peripherals and disables the crystal oscillator All internal devices registers state machines etc maintain their states as long as Voc is applied The BIU will not honor DRAM refresh and HOLD requests in Powerdown mode because the clocks for those functions are off CLKOUT freezes in a logic high state Cur rent consumption in Powerdown mode consists of just transistor leakage typically less than 100 microamps 5 16 intel CLOCK GENERATION AND POWER MANAGEMENT 5 2 2 1 Entering Powerdown Mode Powerdown mode is entered by executing the HLT instruction after setting the PWRDN bit in the Power Control Register see Figure 5 9 on page 5 12 The HALT cycle turns off both the core and peripheral clocks and disables the crystal oscillator See Chapter 3 Bus Interface Unit for detailed informati
332. st SHR mem n then SHR reg CL _ 1 SHR mem CL else OF 0 else OF undefined STC Set Carry Flag CF lt 1 AF STC CF Y Sets CF to 1 IF Instruction Operands OF none PE SF TF ZF STD Set Direction Flag DF lt 1 AF STD or Suet DF Sets DF to 1 causing the string instruc IF tions to auto decrement the SI and or OF DI index registers PF Instruction Operands SF none TF ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 43 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel Name Description Operation aoa d STI Set Interrupt enable Flag IF lt 1 AF STI p Sets IF to 1 enabling processor IF v recognition of maskable interrupt OF requests appearing on the INTR line PF Note however that a pending interrupt SF will not actually be recognized until the instruction following STI has executed ZF Instruction Operands none STOS Store Byte or Word String When Source Operand is a Byte AF STOS dest string DEST AL Be n Transfers a byte or word from register if IF AL or AX to the string element DF 0 OF addressed by DI and
333. st meet the setup and hold timings with respect to the rising edge of TXD These timings can be found in the AC timings section of the data sheet 10 20 intel SERIAL COMMUNICATIONS UNIT 10 3 3 2 BCLK as Baud Timebase Clock BCLK does not run directly into the baud timebase clock but is first synchronized to the CPU clock BCLK causes the baud timebase clock to increment but transitions on TXD and RXD for transmissions still occur relative to CLKOUT A low to high transition on BCLK increments BxCNT If BxCNT is equal to BXCMP TXD goes low approximately 4 CLKOUTS later will always remain low for two CLKOUT periods and then go high will go low again 4 2 CLKOUTs after BXCNT equals BxCMP Therefore the output frequency on TXD is roughly equal to the input frequency on BCLK multiplied by Bx CMP There will be some clock jitter as the output on TXD will always be some multiple of CLKOUTS This is due to the internal synchronization 10 4 SERIAL COMMUNICATIONS UNIT INTERRUPTS Serial communication is usually interrupt driven An interrupt needs to occur on each reception and on each transmission of a character The RI and TI flags in the SxSTS register Figure 10 14 on page 10 16 provide the interrupt mechanism for the serial ports The two serial ports or chan nels have different interrupt circuitry Serial channel 0 is directly supported by the integrated In terrupt Control Unit Serial channel 1 is supported by th
334. state just prior to T1 Either T4 or TI precedes T1 depending on the operation of the previous bus cycle see Figure 3 8 on page 3 9 ALE provides a strobe to latch physical address information Address is presented on the multi plexed address data bus during T1 see Figure 3 10 The falling edge of ALE occurs during the middle of T1 and provides a strobe to latch the address Figure 3 11 presents a typical circuit for latching addresses The status signals S2 0 define the type of bus cycle Table 3 1 S2 0 remain valid until phase 1 of T3 or the last TW when wait states occur The circuit shown in Figure 3 11 can also be used to extend S2 0 beyond the T3 or TW state intel BUS INTERFACE UNIT CLKOUT Clock high to ALE high S2 0 valid Clock low to address valid BHE valid Address valid to ALE low address setup to ALE Clock high to ALE low Clock low to address invalid address hold from clock low ALE low to address invalid address hold from ALE A1101 0A Figure 3 10 Address Status Phase Signal Relationships BUS INTERFACE UNIT intel Latched Signals From CPU Address Signals LA19 16 LS2 0 A1102 0A Figure 3 11 Demultiplexing Address Information Table 3 1 Bus Cycle Types Status Bit Operation S2 51 so 0 0 0 Interrupt Acknowledge 0 0 1 Read 0 1 0 Write 0 1 1 Halt 1 0 0 Instruction Prefetch 1 0 1 Memory Read 1 1 0 Memory Writ
335. ster 8 9 8 19 8 20 Poll Status register 8 9 8 19 8 20 8 21 Polling 8 1 8 9 POPA instruction 1 Port Control Register PXCON 11 8 Port Data Latch Register PXLTCH 11 10 Port Direction Register PXDIR 11 9 Port Pin State Register PXPIN 11 11 Power consumption reducing 3 28 5 19 Power Control Register 5 12 Power management 5 10 5 19 Power management modes and HALT bus cycles 3 28 3 30 3 32 compared 5 19 Powerdown mode 5 16 5 19 7 2 and bus cycles 5 16 control register 5 12 entering 5 17 exiting 5 18 5 19 exiting HALT bus cycle 3 33 initialization code 5 15 5 18 Priority Mask register 8 18 Processor control instructions 2 27 Processor Status Word PSW 2 1 2 7 2 41 bits defined 2 7 2 9 flag storage formats 2 19 reset status 2 7 Program transfer instructions 2 23 2 24 conditional transfers 2 24 2 26 interrupts 2 26 iteration control 2 25 unconditional transfers 2 24 Programming examples See Software PUSH instruction A 8 PUSHA instruction 1 R RCL instruction A 10 RCR instruction A 10 Read bus cycles See Bus cycles READY and chip selects 6 11 and normally not ready signal 3 16 3 18 and normally ready signal 3 16 3 17 and PCB accesses 4 4 and wait states 3 13 3 18 Index 5 INDEX block diagram 3 15 implementation approaches 3 13 timing concerns 3 17 Real defined 12 7 Real time clock code example 9 17 9 20 Refresh address 7 4 Refresh Ad
336. straightforward The serial port must be initialized correctly through SxCON then SxSTS needs to be interpreted To configure the serial port first program the baud rate through the BxCMP register then pro gram SxCON Figure 10 13 on page 10 15 as follows l Determine the values for M2 0 for the desired serial port mode 2 If parity is used enable it with the PEN bit Set the sense of parity even or odd with the EVN bit Note that parity is not available in Mode 4 seven bit data 10 13 SERIAL COMMUNICATIONS UNIT intel 3 Ifthe Clear to Send feature is used set the CEN bit to enable it 4 If receptions are desired set the REN bit to enable the RX machine Note the TX machine need not be explicitly enabled At this point you will be able to transmit and receive in the mode specified Now that the serial port is operating you must correctly interpret its status This is done by reading the SxSTS reg ister Figure 10 14 on page 10 16 and interpreting its contents Reading SxSTS clears all bits except the CTS and TXE bits SxSTS must first be saved in memory and then each bit can be interpreted individually The RI TI and TXE bits indicate the condition of the transmit and receive buffers RI and TI are also used with the Interrupt Control Unit for interrupt based communications The OE FE and PE bits indicate any errors when a character is received Once an error occurs the appropriate bit remains set until SxSTS is r
337. strates the best possible case where the input occurs immediately before the timer is serviced Timer 1 demonstrates the worst possible case where the input is latched but the setup time is not met and the input is not recognized until the counter element services the timer again In single maximum count mode the timer output pin goes low for one CPU clock period see Fig ure 9 4 on page 9 6 This occurs when the count value equals the Maxcount Compare A value If programmed to run continuously the timer generates periodic pulses 9 14 intel TIMER COUNTER UNIT Timer 0 Serviced Internal Count Value Maxcount 1 TxOUT Pin NOTE 1 1301 0 Figure 9 9 TxOUT Signal Timing In dual maximum count mode the timer output pin indicates which Maxcount Compare register is currently in use A low output indicates Maxcount Compare B and a high output indicates Maxcount Compare A see Figure 9 4 on page 9 6 If programmed to run continuously a repet itive waveform can be generated For example if Maxcount Compare A contains 10 Maxcount Compare B contains 20 and CLKOUT is 12 5 MHz the timer generates a 33 percent duty cycle waveform at 104 KHz The output pin always goes high at the end of the counting sequence even if the timer is not programmed to run continuously 9 2 5 Enabling Disabling Counters Each timer has an Enable EN bit in its Control register to allow or prevent timer counting The Inhibit INH
338. t State Module CLKOUT A1081 0A Figure 3 16 Generating a Normally Ready Bus Signal The READY input has two major timing concerns that can affect whether a normally ready or normally not ready signal may be required Two latches capture the state of the READY input see Figure 3 14 on page 3 15 The first latch captures READY on the phase 2 clock edge The second latch captures READY and the result of first latch on the phase 1 clock edge The follow ing items define the requirements of the READY input to meet ready or not ready bus conditions The bus is ready if both of these two conditions are true READY is active prior to the phase 2 clock edge and READY remains active after the phase 1 clock edge The bus is not ready if either of these two conditions is true READY is inactive prior to the phase 2 clock edge or READY is inactive prior to the phase 1 clock edge A normally not ready system must generate a valid READY input at phase 2 of T2 to prevent wait states If it cannot then running without wait states requires a normally ready system Figure 3 17 illustrates the timing necessary to prevent wait states in a normally not ready system Figure 3 17 also shows how to terminate a bus cycle with wait states in a normally not ready system 3 17 BUS INTERFACE UNIT intel CLKOUT READY In a Normally Not Ready system wait states will be inserted until both 1 amp 2 are met 1 T READY
339. t would be sent INT3 remains pending in the Interrupt Request register The INTO interrupt handler completes and sends an EOI command to clear the INTO bit in the In Service register INT3 is still pending and now meets all the priority criteria The Interrupt Control Unit asserts the interrupt request to the CPU and the process begins again intel INTERRUPT CONTROL UNIT 8 2 2 2 Interrupts That Share a Single Source Multiple interrupt requests can share a single interrupt input to the Interrupt Control Unit For example the three timers share a single input Although these interrupts share an input each has its own interrupt vector For example when a Timer 0 interrupt occurs the Timer 0 interrupt handler is executed This section uses the three timers as an example to describe how these in terrupts are prioritized and serviced The Interrupt Status register acts as a second level request register to process the timer interrupts It contains a bit for each timer interrupt When a timer interrupt occurs both the individual Inter rupt Status register bit and the shared Interrupt Request register bit are set From this point the interrupt is processed like any other interrupt source When the shared interrupt is acknowledged the timer interrupt with the highest priority see Ta ble 8 1 on page 8 3 at that time is serviced first and that timer s Interrupt Status bit is cleared If no other timer Interrupt Status bits are set
340. ta sheets obtaining from BBS 1 6 intel Data transfers 3 1 3 6 instructions 2 18 PCB considerations 4 5 PSW flag storage formats 2 19 See also Bus cycles Data types 2 37 2 38 DI register 2 1 2 5 2 13 2 22 2 23 2 30 2 32 2 34 Digital one shot code example 9 17 9 23 Direction Flag DF 2 7 2 9 2 23 Display defined A 2 Divide Error trap Type 0 exception 2 43 Documents related 1 3 DRAM controllers and wait state control 7 5 clocked 7 5 design guidelines 7 5 unclocked 7 5 See also Refresh Control Unit DS register 2 1 2 5 2 6 2 13 2 30 2 34 2 43 DX register 2 1 2 5 2 36 3 6 E Effective Address EA 2 13 calculation 2 28 Emulation mode 13 1 End of Interrupt EOI command 8 21 register 8 21 8 22 ENTER instruction A 2 ES register 2 1 2 5 2 6 2 13 2 30 2 34 Escape opcode fault Type 7 exception 2 44 12 1 Examples code See Software Exceptions 2 43 2 44 priority 2 46 2 49 Execution Unit EU 2 1 2 2 Extra segment 2 5 F Fault exceptions 2 43 FaxBack service 1 5 F Bus and PCB 4 5 operation 4 5 Flags See Processor Status Word PSW Floating Point defined 2 37 INDEX H HALT bus cycle See Bus cycles HOLD HLDA protocol See Bus hold protocol Hypertext manuals obtaining from BBS 1 6 devices interfacing with 3 6 3 7 memory mapped 3 6 ports 11 1 11 12 addressing 2 36 bidirectional 11 1 configuration example 11
341. ted or masked by software When the NMI input is asserted the interrupt processing sequence begins after ex ecution of the current instruction completes see Interrupt Latency on page 2 45 The CPU au tomatically generates a type 2 interrupt vector The NMI input is asynchronous Setup and hold times are given only to guarantee recognition on a specific clock edge To be recognized NMI must be asserted for at least one CLKOUT period and meet the correct setup and hold times NMI is edge triggered and level latched Multiple NMI requests cause multiple NMI service routines to be executed NMI can be nested in this man ner an infinite number of times 2 42 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 3 1 2 Maskable Interrupts Maskable interrupts are the most common way to service external hardware interrupts Software can globally enable or disable maskable interrupts This is done by setting or clearing the Inter rupt Enable bit in the Processor Status Word The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents them to the core via a single maskable interrupt input The Interrupt Control Unit provides the interrupt vector type to the 80C186 Modular Core The Interrupt Control Unit differs among members of the 80C186 Modular Core family see Chapter 8 Interrupt Control Unit for infor mation 2 3 1 3 Exceptions Exceptions occur when an unusual condition prevents further
342. ternal Communications Registers Temporary Registers C iud External Logic Bus Instruction Queue Control System Q Bus 8 Bits Execution Unit Bus Interface Unit EU BIU A1012 0A Figure 2 1 Simplified Functional Block Diagram of the 80C186 Family CPU 2 1 4 Execution Unit The Execution Unit executes all instructions provides data and addresses to the Bus Interface Unit and manipulates the general registers and the Processor Status Word The 16 bit ALU within the Execution Unit maintains the CPU status and control flags and manipulates the general reg isters and instruction operands All registers and data paths in the Execution Unit are 16 bits wide for fast internal transfers 2 2 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The Execution Unit does not connect directly to the system bus It obtains instructions from a queue maintained by the Bus Interface Unit When an instruction requires access to memory or a peripheral device the Execution Unit requests the Bus Interface Unit to read and write data Ad dresses manipulated by the Execution Unit are 16 bits wide The Bus Interface Unit however performs an address calculation that allows the Execution Unit to access the full megabyte of memory space To execute an instruction the Execution Unit must first fetch the object code byte from the in struction queue and then execute the instruction If the queue is empty when the Execution Unit is rea
343. terrupt source cannot preempt itself The interrupt handler must finish executing before the interrupt is serviced again Special Fully Nested Mode is an exception See Special Fully Nested Mode on page 8 8 8 2 FUNCTIONAL OPERATION This section covers the process in which the Interrupt Control Unit receives interrupts and asserts the maskable interrupt request to the CPU 8 4 intel INTERRUPT CONTROL UNIT 8 2 1 Typical Interrupt Sequence When the Interrupt Control Unit first detects an interrupt it sets the corresponding bit in the In terrupt Request register to indicate that the interrupt is pending The Interrupt Control Unit checks all pending interrupt sources If the interrupt is unmasked and meets the priority criteria see Pri ority Resolution on page 8 5 the Interrupt Control Unit asserts the maskable interrupt request to the CPU then waits for the interrupt acknowledge When the Interrupt Control Unit receives the interrupt acknowledge it passes the interrupt type to the CPU At that point the CPU begin the interrupt processing sequence See Interrupt Ex ception Processing on page 2 39 for details The Interrupt Control Unit always passes the vector that has the highest priority at the time the acknowledge is received If a higher priority interrupt occurs before the interrupt acknowledge the higher priority interrupt has precedence When it receives the interrupt acknowledge the Interrupt Control Un
344. than fifteen wait states must program RDY active A bus cycle with wait states automatically inserted cannot be shortened A bus cycle that ignores bus ready cannot be lengthened 6 4 6 Overlapping Chip Selects The Chip Select Unit activates all enabled chip selects programmed to cover the same physical address space This is true if any portion of the chip selects address ranges overlap i e chip selects ranges do not need to overlap completely to all go active There are various reasons for overlapping chip selects For example a system might have a need for overlapping a portion of read only memory with read write memory or copying data to two devices simultaneously If overlapping chip selects do not have identical wait state and bus ready programming the Chip Select Unit will adjust itself based on the criteria shown in Figure 6 8 6 12 intel CHIP SELECT UNIT Wait Wait Maximum Minimum WS3 0 WS3 0 Complete Bus Cycle A1166 0A Figure 6 8 Overlapping Chip Selects 6 13 intel Table 6 3 lists example wait state and bus ready requirements for overlapping chip selects and the resulting requirements for accesses to the overlapped region CHIP SELECT UNIT Table 6 3 Example Adjustments for Overlapping Chip Selects Chip Select X Chip Select Y Overlapped Region Access Wait States Bus Ready Wait States Bus Ready Wait States Bus Ready 3 ignored 9 ignored 9 ignored 5 required 0 ignored 0
345. that are shorter faster and better structured The Bus Interface Unit must obtain the logical address before generating the physical address The logical address of a memory location can come from different sources depending on the type of reference that is being made see Table 2 2 Segment registers always hold the segment base addresses The Bus Interface Unit determines which segment register contains the base address according to the type of memory reference made However the programmer can explicitly direct the Bus Interface Unit to use any currently addressable segment except for the destination operand of a string instruction In assembly lan guage this is done by preceding an instruction with a segment override prefix 2 11 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE intel Physical Address Logical Addresses Segment Base A1038 0A Figure 2 8 Logical and Physical Address 2 12 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2 2 Logical Address Sources Type of Memory Reference S Simon aoe S eom DI Offset Instruction Fetch CS NONE IP Stack Operation SS NONE SP Variable except following DS CS ES SS Effective Address String Source DS CS ES SS SI String Destination ES NONE DI BP Used as Base Register SS CS DS ES Effective Address Instructions are always fetched from the current code segment The IP register contains the in struction s offset from the begin
346. that the CPU can execute multiple bus cycles without intervention and possible corruption of the data by another CPU A classic use of the mechanism is the TEST and SET semaphore during which a CPU must read from a shared memory location and return data to the location without allowing another CPU to reference the same location during the test and set operations Another application of LOCK for multiprocessor systems consists of a locked block move which allows high speed message transfer from one CPU s message buffer to another During the locked instruction 1 while LOCK is active a bus hold or refresh request is recorded but is not ac knowledged until completion of the locked instruction However LOCK has no effect on inter rupts As an example a locked HALT instruction causes bus hold or refresh bus requests to be ignored but still allows the CPU to exit the HALT state on an interrupt 3 38 intel BUS INTERFACE UNIT In general prefix bytes such as LOCK are considered extensions of the instructions they pre cede Interrupts and refresh requests that occur during execution of the prefix are not acknowl edged until the instruction following the prefix completes except for instructions that are servicing interrupts during their execution such as HALT WAIT and repeated string primitives Note that multiple prefix bytes can precede an instruction Another example is a string primitive preceded by the repetition prefix REP
347. the stop address value However the ISTOP control bit cannot be set when chip selects are disabled in this manner 6 4 5 Bus Wait State and Ready Control Normally the bus ready input must be inactive at the appropriate time to insert wait states into the bus cycle The Chip Select Unit can ignore the state of the bus ready input to extend and com plete the bus cycle automatically Most memory and peripheral devices operate properly using fifteen or fewer wait states However accessing such devices as a dual port memory an expan sion bus interface a system bus interface or remote peripheral devices can require more than fif teen wait states to complete a bus cycle The START register holds a four bit value WS3 0 that defines the number of wait states to in sert into the bus cycle Figure 6 7 shows a simplified logic diagram of the wait state and ready control functions 6 11 CHIP SELECT UNIT intel BUS READY READY Control Bit Wait State Value WS3 0 A1165 0A Figure 6 7 Wait State and Ready Control Functions The STOP register defines the RDY control bit to extend bus cycles beyond fifteen wait states The RDY control bit determines whether the bus cycle should complete normally i e require bus ready or unconditionally i e ignore bus ready Chip selects connected to devices requiring fifteen wait states or fewer can program RDY inactive to automatically complete the bus cycle Devices that may require more
348. tion Assume these initial conditions The 1 10 8 6 the Interrupt Control Unit has been initialized no interrupts are pending no In Service bits are set the Interrupt Enable bit is set all interrupts are unmasked the default priority scheme is being used the Priority Mask register is set to the lowest priority seven example uses two external interrupt sources INTO and INT3 to describe the process A low to high transition on INTO sets its Interrupt Request bit The interrupt is now pending Because INTO is the only pending interrupt it meets all the priority criteria The Interrupt Control Unit asserts the interrupt request to the CPU and waits for an acknowledge The CPU acknowledges the interrupt The Interrupt Control Unit passes the interrupt type in this case type 12 to the CPU The Interrupt Control Unit clears the INTO bit in the Interrupt Request register and sets the INTO bit in the In Service register The CPU executes the interrupt processing sequence and begins executing the interrupt handler for INTO During execution of the INTO interrupt handler a low to high transition on INT3 sets its Interrupt Request bit The Interrupt Control Unit determines that INT3 has a lower priority than INTO which is currently executing INTO s In Service bit is set INT3 does not meet the priority criteria so no interrupt request is sent to the CPU If INT3were programmed with a higher priority than INTO the reques
349. tion subtracts one if CF is set and OF v returns the result to the destination dest dest src PF v operand Both operands may be bytes SF v or words Both operands may be TF signed or unsigned binary numbers ZE see AAS and DAS Instruction Operands SBB reg reg SBB reg mem SBB mem reg SBB accum immed SBB reg immed SBB mem immed NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed Y the flag is updated after the instruction is executed C 41 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel Name Description Operation Nina d SCAS Scan String When Source Operand is a Byte AF v SCAS dest string AL byte string v Subtracts the destination string if element byte or word addressed by DF 0 OF v DI from the content of AL byte string then PF or AX word string and updates the 01 lt 01 DELTA SE flags but does not alter the destination else string or the accumulator SCAS also 01 lt DI DELTA ZF updates DI to point to the next string When Source Operand is a Word element and AF CF OF PF SF and AX ea word string ZF to reflect the relationship of the if scan value in AL AX to the string DF 0 element If SCAS is pref
350. tions in ax dx mov dx S1CON prepare to send command mov ax 0003h Mode 3 out ax mov dx S1TBUF Select slave mov ax Slave get command to send to slave out dx al send it pop dx restore saved registers pop ax pop bx restore caller s bp ret _send_slave_cmdendp lib 80186 ends end Example 10 6 Master Slave The send slave command Routine 10 35 SERIAL COMMUNICATIONS UNIT 10 36 intel 1 Input Output Ports intel CHAPTER 11 INPUT OUTPUT PORTS Many applications do not require full use of all the on chip peripheral functions For example the Chip Select Unit provides a total of ten chip select lines only a large design would require all ten For smaller designs that require fewer than ten chip selects these pins would be wasted The input output ports give system designers the flexibility to replace the functions of unused pe ripheral pins with general purpose I O ports Many of the on chip peripheral pin functions are multiplexed with an I O port If a particular peripheral pin function is unnecessary in an applica tion that pin can be used for I O The 80C186EB 80C 188EB has four types of ports bidirection al input only output only and open drain bidirectional 11 1 FUNCTIONAL OVERVIEW All port pin types are derived from a common bidirectional port logic module Unidirectional and open drain ports are a subset of the bidirectional module The following sections de
351. to configuration support for 1200 through 14 4K baud modems To access the BBS just dial the telephone number see page 1 4 and respond to the system prompts During your first session the system asks you to register with the system operator by entering your name and location The system operator will then set up your access account within 24 hours At that time you can access the files on the BBS For a listing of files call the FaxBack service and order catalog 6 the BBS catalog INTRODUCTION intel If you encounter any difficulty accessing our high speed modem try our dedicated 2400 baud modem see page 1 4 Use the following modem settings e 2400 baud N 8 1 1 3 3 How to Find the Latest ApBUILDER Files Hypertext Manuals and Data Sheets on the BBS The latest ApBUILDER files and hypertext manuals and data sheets are available first from the BBS To access the files 1 Select F from the BBS Main menu 2 Select L from the Intel Apps Files menu 3 The BBS displays the list of all area levels and prompts for the area number 4 Select 25 to choose the ApBUILDER Hypertext area 5 Area level 25 has four sublevels 1 General 2 196 Files 3 186 Files and 4 8051 Files 6 Select 1 to find the latest ApBUILDER files or the number of the appropriate product family sublevel to find the hypertext manuals and data sheets 7 Enter the file number to tag the files you wish to download The BBS displays the
352. to the target location PF if the tested condition ZF 0 is true SF Instruction Operands JNE short label ZF JNZ short label JNO Jump on Not Overflow if AF JNO disp8 OF 0 CF Transfers control to the target location us 1 7 disp8 sign ext to 16 bits IF if the tested condition OF 0 is true UP Pes IR disp3 eld OF Instruction Operands JNO short label SF TF ZF JNS Jump on Not Sign if AF JNS disp8 SF 0 CF Transfers control to the target location hen nes 1 IP IP disp8 sign ext to 16 bits IF if the tested condition SF 0 is true lt IP dispsgelg OF Instruction Operands JNS short label SF TF ZF JNP Jump on Not Parity if AF JPO Jump on Parity Odd PF 20 JNO disp8 then NE ela JPO disp8 lt IP disp8 sign ext to 16 bits IF OF Transfers control to the target location PF if the tested condition PF 0 is true SF Instruction Operands TF JNO short label ZF JPO short label NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 24 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Cont
353. tomatically update the SI register the DI register or both before processing the next string element The Direction Flag DF determines whether the index registers are auto incremented DF 0 or auto decremented DF 1 The processor adjusts the DI SI or both registers by one for byte strings or by two for word strings If a repeat prefix is used the count register CX is decremented by one after each repetition of the string instruction The CX register must be initialized to the number of repetitions before the string instruction is executed If the CX register is 0 the string instruction is not executed and control goes to the following instruction Table 2 8 String Instruction Register and Flag Use SI Index offset for source string DI Index offset for destination string CX Repetition counter AL AX Scan value Destination for LODS Source for STOS DF Direction Flag 0 auto increment SI DI 1 auto decrement SI DI ZF Scan compare terminator 2 2 1 5 Program Transfer Instructions The contents of the Code Segment CS and Instruction Pointer IP registers determine the in struction execution sequence in the 80C186 Modular Core family The CS register contains the base address of the current code segment The Instruction Pointer register points to the memory location of the next instruction to be fetched In most operating conditions the next instruction will already have been fetched and will be waiting in
354. tors 2 3 5 Interrupt and Exception Priority Interrupts can be recognized only on valid instruction boundaries If an NMI and a maskable in terrupt are both recognized on the same instruction boundary NMI has precedence The maskable interrupt will not be recognized until the Interrupt Enable bit is set and it is the highest priority 2 46 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Only the single step exception can occur concurrently with another exception At most two ex ceptions can occur at the same instruction boundary and one of those exceptions must be the sin gle step Single step is a special case it is discussed on page 2 48 Ignoring single step for now only one exception can occur at any given instruction boundary An exception has priority over both NMI and the maskable interrupt However a pending NMI can interrupt the CPU at any valid instruction boundary Therefore NMI can interrupt an excep tion service routine If an exception and NMI occur simultaneously the exception vector is taken then is followed immediately by the NMI vector see Figure 2 28 While the exception has high er priority at the instruction boundary the NMI interrupt service routine is executed first Divide Error Push PSW CS IP Fetch Divide Error Vector Push PSW CS IP Fetch NMI Vector Execute NMI Service Routine Execute Divide Service Routine A1031 0A Figure 2 28 Simultaneous NMI and Exception 2 47
355. truction Operands TF LOOP short label ZF LOOPE Loop While Equal CX lt CX 1 AF LOOPZ Loop While Zero if CF Pree alspa UE IP disp8 si t to 16 bit 28 J isp8 sign ext to its Decrements CX by 1 and transfers amp disp8 sig control is to the target location if CX is SF not 0 and if ZF is set otherwise the TES next sequential instruction is executed ZF Instruction Operands LOOPE short label LOOPZ short label NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 28 intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued MON A Flags Name Description Operation Affected LOOPNE Loop While Not Equal CX CX 1 AF LOOPNZ Loop While Not Zero CF LOOPNE disp8 ZF 0 and CX 0 DF poe eens ge IP disp8 si t to 16 bit ee z lt isp8 sign ext to its Decrements CX by 1 and transfers Vest sig PF control to the target location if CX is SF not 0 and if ZF is clear otherwise the TF next sequential instruction is executed ZF Instruction Operands LOOPNE short label LOOPNZ short label MOV Move Byte or Word dest src AF MOV dest src EE T
356. tus register are not altered The CPU processes software interrupts and exceptions in the same way Software interrupts ex ceptions and traps cannot be masked 2 3 8 Interrupt Latency Interrupt latency is the amount of time it takes for the CPU to recognize the existence of an inter rupt The CPU generally recognizes interrupts only between instructions or on instruction bound aries Therefore the current instruction must finish executing before an interrupt can be recognized The worst case 80C186 instruction execution time is an integer divide instruction with segment override prefix The instruction takes 69 clocks assuming an 80C 186 Modular Core family mem ber and a zero wait state external bus The execution time for an 80C188 Modular Core family member may be longer depending on the queue This is one factor in determining interrupt latency In addition the following are also factors in determining maximum latency 1 The CPU does not recognize the Maskable Interrupt unless the Interrupt Enable bit is set 2 The CPU does not recognize interrupts during HOLD 3 Once communication is completely established with an 80C187 the CPU does not recognize interrupts until the numerics instruction is finished The CPU can recognize interrupts only on valid instruction boundaries A valid instruction boundary usually occurs when the current instruction finishes The following is a list of excep tions 1 MOVs and POPs referencing a
357. typical setup NOTE It is assumed that the network is set up as shown in Figure 10 20 that the slave unit is running the _ 1 1 code and that the PCB is located in I O space RAK AA AK EAA AE KAA GER OR UE ORO OEC LE SEO COE GEO ORE RAR eo ae eae LOR RR ese Slavel equ Olh address assigned to slave unit 1 Flash equ orth command to flash EVAL board LEDs Disc equ Ofh command to disconnect from network False equ 00h lib 80186 segment public code declare external routines extrn Select slave far extrn Send slave cmd far lib 80186 ends code segment public code assume cs code public main main proc near push Slavel get slave unit 1 address Send the address over the network call far ptr select slave add 2 adjust sp cmp ax false was slave 1 properly selected je SlaveExit no then exit push Flash yes then send Flash command call far ptr send slave cmd add sp 2 adjust sp insert a delay routine to allow completion of last command push Disc prepare to disconnect slave send it call far ptr send slave cmd add sp 2 adjust sp SlaveExit ret main endp code ends end main Example 10 3 Master Slave Implementing the Master Slave Routines 10 29 SERIAL COMMUNICATIONS UNIT intel mod186 name example master select slave ASA E RRR ES
358. uction Format Varlables tette tern C 1 xiv intel deere TABLES Table Page C 2 Instruction Operands a ce ate en a aad C 2 C 3 Flag Bit Functions c D ee a ee eee ee A see C 3 C 4 INStructiOn Set C C 4 D 1 Operand Variables nee eie der De e EP uie E ne eee D 1 D 2 Instruction Set ent pedestres D 2 D 3 Machine Instruction Decoding Guide senem D 9 D 4 Mnemonic Encoding Matrix Left Half D 20 D 5 Abbreviations for Mnemonic Encoding Matrix ee D 22 XV SUENE intel EXAMPLES Example Page 5 1 Initializing the Power Management Unit for Idle or Powerdown Mode 5 16 6 1 Initializing the Chip Select Unit essseeneeeeeneennen nennen 6 17 7 1 Initializing the Refresh Control Unit sseeeennennnenenne 7 12 8 1 Initializing the Interrupt Control Unit sseeeeenennennneeen 8 24 9 1 Configuring a Real Time Clock nennen 9 18 9 2 Configuring a Square Wave Generator essen 9 21 9 3 Configuring a Digital One Shot sessssseeeeeeeeeneeneennnee nnne 9 22 10 1 Asynchronous Mode 4 10 23 10 2 Mode O Example Bitte ct e OO RO ERR e iaeoe iie 10 26 10 3 Master Slave Implementing the Master Slave
359. uivalent capacitance C at the operation frequency The desired operation frequency is the third overtone frequency marked on the crystal Optimiz ing equations for the above three criteria yields Table 5 1 This table shows suggested standard inductor values for various processor frequencies The equivalent capacitance is about 15 pF Table 5 1 Suggested Values for Inductor L in Third Overtone Oscillator Circuit CLKOUT Third Overtone Crystal Inductor L Frequency MHz Frequency MHz Values pH 13 04 26 08 6 8 8 2 10 0 16 32 3 9 4 7 5 6 20 40 2 2 2 7 3 8 5 4 intel CLOCK GENERATION AND POWER MANAGEMENT 5 1 1 2 Selecting Crystals When specifying crystals consider these parameters Resonance and Load Capacitance Crystals carry a parallel or series resonance specifi cation The two types do not differ in construction just in test conditions and expected circuit application Parallel resonant crystals carry a test load specification with typical load capacitance values of 15 18 or 22 pF Series resonant crystals do not carry a load capacitance specification You may use a series resonant crystal with the microprocessor even though the circuit is parallel resonant However it will vibrate at a frequency slightly on the order of 0 1 higher than its calibration frequency Vibration Mode The vibration mode is either fundamental or third overtone Crystal thickness varies inversely with frequ
360. uld not be loaded here Locations OFFFFOH through OFFFFFH in high memory are used for system reset code because the processor begins execution at OFFFFOH Locations OF8H through OFFH in I O space are reserved for communication with other Intel hardware products and must not be used On the 80C186 core these addresses are used as I O ports for the 80C187 numerics processor extension 2 15 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel 2 16 Existing Stack PUSH AX x ir o Ra o E o e Not presently on stack Stack operation for code sequence PUSH AX POP AX POP BX A1013 0A Figure 2 10 Stack Operation intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 2 SOFTWARE OVERVIEW All 80C186 Modular Core family members execute the same instructions This includes all the 8086 8088 instructions plus several additions and enhancements see Appendix A 80C186 In struction Set Additions and Extensions The following sections describe the instructions by cat egory and provide a detailed discussion of the operand addressing modes Software for 80C186 core family systems need not be written in assembly language The proces sor provides direct hardware support for programs written in the many high level languages available The hardware addressing modes provide straightforward implementations of based variables arrays arrays of structures and other high level language data constructs A po
361. ully Nested Mode Cascade Set to enable cascade mode Mode Level trigger Selects the interrupt triggering mode 0 edge triggering 1 level triggering The LVL bit must be set when external 8259As are cascaded into the Interrupt Control Unit MSK Interrupt Clear to enable interrupts from this source Mask PM2 0 Priority 111 Defines the priority level for this source Level NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 6 Interrupt Control Register for Cascadable Interrupt Pins INTERRUPT CONTROL UNIT intel 8 3 2 Interrupt Request Register The Interrupt Request register Figure 8 7 has one bit for each interrupt source When a source requests an interrupt its Interrupt Request bit is set without regard to whether the interrupt is masked The Interrupt Request bit is cleared when the interrupt is acknowledged An external interrupt pin must remain asserted until its interrupt is acknowledged Otherwise the Interrupt Request bit will be cleared but the interrupt will not be serviced Register Name Interrupt Request Register Register Mnemonic REQST Register Function Stores pending interrupt requests A1206 A0 Bit Bit Nam Function Mnemonic uneto INT3 0 INT4 External A bit is set to indicate a pending interrupt from Interrupts the corresponding
362. ult occurs and the Escape Opcode service routine em ulates the floating point instruction If the Escape Trap bit is cleared the CPU sends the floating point instruction to an external 80C187 80C188 Modular Core Family members do not support the 80C187 interface and always generate the Escape Opcode Fault Numerics Coprocessor Fault Type 16 The Numerics Coprocessor fault is caused by an external 80C187 numerics coprocessor The 80C187 reports the exception by asserting the ERROR pin The 80C186 Modular Core checks the ERROR pin only when executing a numerics instruction A Numerics Coprocessor Fault in dicates that the previous numerics instruction caused the exception The 80C187 saves the ad dress of the floating point instruction that caused the exception The return address pushed onto the stack during the interrupt processing points to the numerics instruction that detected the ex ception This way the last numerics instruction can be restarted 2 44 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2 3 2 Software Interrupts A Software Interrupt is caused by executing an INTn instruction The n parameter corresponds to the specific interrupt type to be executed The interrupt type can be any number between 0 and 255 If the n parameter corresponds to an interrupt type associated with a hardware interrupt NMI Timers the vectors are fetched and the routine is executed but the corresponding bits in the Interrupt Sta
363. ummy read cycle Refresh bus requests have higher priority than most CPU bus cycles all DMA bus cycles and all interrupt vectoring sequences Refresh bus cycles also have a higher priority than the HOLD HLDA bus arbitration protocol see Refresh Operation and Bus HOLD on page 7 13 7 2 Refresh Control Unit Operation Load Counter From Refresh Clock Interval Register gt Decrement Counter Generated BIU Request Figure 7 2 Refresh Control Unit Operation Flow Chart REFRESH CONTROL UNIT BIU Refresh Bus Operation Refresh Request Acknowledged Execute Memory Read Increment Address Remove Executed Request Every Clock Continue A1265 0A The nine bit refresh clock counter does not wait until the BIU services the refresh request to con tinue counting This operation ensures that refresh requests occur at the correct interval Other wise the time between refresh requests would be a function of varying bus activity When the BIU services the refresh request it clears the request and increments the refresh address 7 3 REFRESH CONTROL UNIT intel The BIU does not queue DRAM refresh requests If the Refresh Control Unit generates another request before the BIU handles the present request the BIU loses the present request However the address associated with the request is not lost The refresh address changes only after the BIU runs a refresh bus cycle If a DRAM refresh cycle is excessively delayed
364. updates DI to then _ point to the next location in the string DI lt DI DELTA SF As a repeated operation else _ DI lt DI DELTA Instruction Operands 1 ZF When Source Operand is a Word STOS dest string STOS repeat dest string ER lt AX I DF 0 then DI lt DI DELTA else DI DI DELTA NOTE The three symbols used in the Flags Affected column are defined as follows C 44 the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed intel INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued Name Description Operation SUB Subtract dest dest src AF Y SUB dest src a d The source operand is subtracted from IF the destination operand and the result OF v replaces the destination operand The PF v operands may be bytes or words Both SF v operands may be signed or unsigned TF binary numbers see AAS and DAS 7 Instruction Operands SUB reg reg SUB reg mem SUB mem reg SUB accum immed SUB reg immed SUB mem immed TEST Test dest and src AF TEST dest src CF 0 GE Y OF 0 DF Performs the logical and of the two IF operands bytes or words updates OF v the flags but does not return the PF result i e neither operand i
365. upt Acknowledge Sequence During the interrupt acknowledge sequence the Interrupt Control Unit passes the interrupt type to the CPU The CPU then multiplies the interrupt type by four to derive the interrupt vector ad dress in the interrupt vector table Interrupt Exception Processing on page 2 39 describes the interrupt acknowledge sequence and Figure 2 25 on page 2 40 illustrates the interrupt vector ta ble The interrupt types for all sources are fixed and unalterable see Table 8 2 The Interrupt Control Unit passes these types to the CPU internally The first external indication of the interrupt ac knowledge sequence is the CPU fetch from the interrupt vector table In cascade mode the external 8259A supplies the interrupt type In this case the CPU runs an external interrupt acknowledge cycle to fetch the interrupt type from the 8259A see Interrupt Acknowledge Bus Cycle on page 3 25 Table 8 2 Fixed Interrupt Types Interrupt Name Interrupt Type Timer 0 8 Timer 1 18 Timer 2 19 Serial Channel 0 Receive 20 Serial Channel 0 Transmit 21 INT4 17 INTO 12 INT1 13 INT2 14 INT3 15 8 2 5 Polling In some applications it is desirable to poll the Interrupt Control Unit The CPU polls the Interrupt Control Unit for any pending interrupts and software can service interrupts whenever it is con venient The Poll and Poll Status registers support polling Software reads the Poll re
366. ut EFI signal directly to the oscillator CLKIN input Leave OSCOUT unconnected This oscillator input drives the internal divide by two counter directly generating the CPU clock signals The external frequency input can have practically any duty cy cle provided it meets the minimum high and low times stated in the data sheet Selecting an ex ternal clock oscillator is more straightforward than selecting a crystal 5 1 3 Output from the Clock Generator The crystal oscillator output drives a divide by two circuit generating a 5096 duty cycle clock for the processor s integrated components All processor timings refer to this clock available exter nally at the CLKOUT pin CLKOUT changes state on the high to low transition of the CLKIN signal even during reset and bus hold CLKOUT is also available during Idle mode but not dur ing Powerdown mode See Idle Mode on page 5 11 and Powerdown Mode on page 5 16 In a CMOS circuit significant current flows only during logic level transitions Since the micro processor consists mostly of clocked circuitry the clock distribution is the basis of power man agement 5 1 4 Reset and Clock Synchronization The clock generator provides a system reset signal RESOUT The RESIN input generates RE SOUT and the clock generator synchronizes it to the CLKOUT signal A Schmitt trigger in the RESIN input ensures that the switch point for a low to high transition is greater than the switch point fo
367. ution Unit calculates the Effective Address by summing a displacement the contents of a base register and the contents of an index register see Figure 2 12 Any combination of these can be present in a given instruction This allows a variety of memory addressing modes 2 28 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single Index Double Index Encoded in the Instruction Explicit in the Effective Instruction Address Assumed Unless Overridden by Prefix A1015 0A Figure 2 12 Memory Address Computation The displacement is an 8 or 16 bit number contained in the instruction The displacement gen erally is derived from the position of the operand s name a variable or label in the program The programmer can modify this value or explicitly specify the displacement 2 29 OVERVIEW OF THE 800186 FAMILY ARCHITECTURE intel The BX or BP register can be specified as the base register for an effective address calculation Similarly either the SI or the DI register can be specified as the index register The displacement value is a constant The contents of the base and index registers can change during execution This allows one instruction to access different memory locations depending upon the current values in the base or base and index registers The default base register for effective address calculations with the BP register is SS although DS or ES can be specified Direct addressing is the simplest memo
368. v values these flags previously had SF v Instruction Operands TF none ZF NOTE The three symbols used in the Flags Affected column are defined as follows the contents of the flag remain unchanged after the instruction is executed the contents of the flag is undefined after the instruction is executed v the flag is updated after the instruction is executed C 39 INSTRUCTION SET DESCRIPTIONS Table C 4 Instruction Set Continued intel Name Description Operation foe d SHL Shift Logical Left temp lt count AF SAL Shift Arithmetic Left do while temp 0 CF v SHL dest count CF lt high order bit of dest DF SAL dest count s lt gt emp lt temp Shifts the destination byte or word left by the number of bits specified in the count 1 SF v count operand Zeros are shifted in on then _ the right If the sign bit retains its if ZF Vv original value then OF is cleared high order bit of dest CE Instruction Operands then SHL reg n SAL reg n OF lt 1 SHL mem n SAL mem n else SHL CL SAL CL OF 0 SHL mem CL SAL mem CL else OF undefined SAR Shift Arithmetic Right temp lt count AF SAR dest count do while temp 0 CF v Tar EA CF lt low order bit of dest DF Shifts the bits in the destination dest dest 2 IF operand byte or word to the right by temp lt temp 1
369. ve Idle and Powerdown power management modes After executing a HALT bus cycle the BIU suspends operation until one of the following events occurs An interrupt is generated A bus HOLD is generated except when Powerdown mode is enabled Arefresh request is generated except when Powerdown mode is enabled Figure 3 25 shows the operation of a HALT bus cycle The address data bus either floats or drives during T1 depending on the next bus cycle to be executed by the BIU Under most instruction sequences the BIU floats the address data bus because the next operation would most likely be an instruction prefetch However if the HALT occurs just after a bus write operation the ad dress data bus drives either data or address information during T1 A19 16 continue to drive the previous bus cycle information under most instruction sequences otherwise they drive the next prefetch address The BIU always operates in the same way for any given instruction sequence The Chip Select Unit prevents a programmed chip select from going active during a HALT bus cycle However chip selects generated by external decoder circuits must be disabled for HALT bus cycles 3 28 intel BUS INTERFACE UNIT After several TI bus states all address data address status and bus control pins drive to a known state when Powerdown or Idle Mode is enabled The address data and address status bus pins force a low 0 state Bus control pins force thei
370. ve loading on the pins 8 7 INTERRUPT CONTROL UNIT intel 8259A or 82C59A INTA INTAO Interrupt Control Unit 8259A or 82C59A INTA A1211 A0 Figure 8 2 Using External 8259A Modules in Cascade Mode 8 2 3 1 Special Fully Nested Mode Special fully nested mode is an optional feature normally used with cascade mode It is applicable only to INTO and INTI In special fully nested mode an interrupt request is serviced even if its In Service bit is set In cascade mode an 8259A controls up to eight external interrupts that share a single interrupt input pin Special fully nested mode allows the 8259A s priority structure to be maintained For example assume that the CPU is servicing a low priority interrupt from the 8259A While the interrupt handler is executing the 8259A receives a higher priority interrupt from one of its sourc es The 8259A applies its own priority criteria to that interrupt and asserts its interrupt to the In terrupt Control Unit Special fully nested mode allows the higher priority interrupt to be serviced even though the In Service bit for that source is already set A higher priority interrupt has pre empted a lower priority interrupt and interrupt nesting is fully maintained Special fully nested mode can also be used without cascade mode In this case it allows a single external interrupt pin either INTO or to preempt itself 8 8 intel INTERRUPT CONTROL UNIT 8 2 4 Interr
371. vents 3 37 3 38 using a locked bus 3 38 3 39 using multiple bus masters 3 39 3 44 BX register 2 1 2 5 2 30 C Carry Flag CF 2 7 2 9 Chip Select Unit CSU 6 1 and HALT bus cycles 3 28 and READY 6 11 6 12 and wait states 6 11 6 12 block diagram 6 3 bus cycle decoding 6 14 examples 6 15 6 20 Index 2 features and benefits 6 1 functional overview 6 2 6 5 programming 6 5 6 15 registers 6 5 6 15 system diagram 6 16 See also Chip selects Chip selects activating 6 4 and 80C187 interface 6 14 12 11 and bus hold protocol 6 15 and DRAM controllers 7 1 and guarded memory locations 6 20 and reserved I O locations 6 14 enabling and disabling 6 11 initializing 6 6 6 15 methods for generating 6 1 multiplexed I O port pins 11 7 overlapping 6 12 6 14 programming considerations 6 14 start address 6 10 6 14 stop address 6 10 timing 6 4 CL register 2 5 2 21 2 22 CLKOUT and bus hold 5 6 and power management modes 5 6 and reset 5 6 Clock generator 5 6 5 10 and system reset 5 6 5 7 output 5 6 synchronizing CLKOUT and RESOUT 5 6 5 7 Clock sources TCU 9 12 Code programs See Software Code segment 2 5 Counters See Timer Counter Unit TCU CPU block diagram 2 2 Crystal See Oscillator CS register 2 1 2 5 2 6 2 13 2 23 2 39 2 41 Customer service 1 4 CX register 2 1 2 5 2 23 2 25 2 26 D Data 3 6 Data bus See Address and data bus Data segment 2 5 Da
372. vice bit is set when an interrupt is acknowl edged the interrupt handler must clear it with an End of Interrupt EOI command The Interrupt Control Unit uses the In Service register to support interrupt nesting Register Name Register Mnemonic Register Function INTERRUPT CONTROL UNIT In Service Register INSERV Indicates which interrupt handlers are in process A1204 A0 Bit Bit Nam Mnemonic Function INT3 0 INT4 External Interrupt In Service A bit is set to indicate that the corresponding external interrupt is being serviced Serial Channel 0 Interrupt In Service Timer Interrupt In Service This bit is set to indicate that a serial channel interrupt is being serviced This bit is set to indicate that a timer interrupt is being serviced NOTE Reserved register bits are shown with gray shading Reserved bits must be written to a logic zero to ensure compatibility with future Intel products Figure 8 10 In Service Register 8 3 6 Poll and Poll Status Registers The Poll and Poll Status registers allow you to poll the Interrupt Control Unit and service inter rupts through software You can read these registers to determine whether an interrupt is pending and if so the interrupt type The registers contain identical information but reading them pro duces different results INTERRUPT CONTROL UNIT intel Reading the Poll register Figure 8 11 ackn
373. vide real reversed FSUB Subtract real FDIVRP Divide real reversed and pop FSUBP Subtract real and pop FIDIVR Integer divide reversed FISUB Integer subtract Other Operations FSUBR Subtract real reversed FSQRT Square root FSUBRP Subtract real reversed and pop FSCALE Scale FISUBR Integer subtract reversed FPREM Partial remainder Multiplication FRNDINT Round to integer FMUL Multiply real FXTRACT Extract exponent and significand FMULP Multiply real and pop FABS Absolute value FIMUL Integer multiply FCHS Change sign FPREMI Partial remainder IEEE 12 4 intel MATH COPROCESSING 12 3 1 3 Comparison Instructions Each comparison instruction see Table 12 3 analyzes the stack top element often in relationship to another operand Then it reports the result in the Status Word condition code The basic oper ations are compare test compare with zero and examine report tag sign and normalization Table 12 3 80C187 Comparison Instructions FCOM Compare real FCOMP Compare real and pop FCOMPP Compare real and pop twice FICOM Integer compare FICOMP Integer compare and pop FTST Test FXAM Examine FUCOM Unordered compare FUCOMP Unordered compare and pop FUCOMPP Unordered compare and pop twice 12 3 1 4 Transcendental Instructions Transcendental instructions see Table 12 4 perform the core calculations for common trigono metric hyperbolic inverse hyperbolic logarithmic and exponential functions Use prolo
374. way for a procedure to address an array located on a stack see Figure 2 20 The BP register can contain the offset of a reference point on the stack This is typically the top of the stack after the procedure has saved registers and allocated local storage The offset of the beginning of the array from the reference point can be expressed by a displacement value The index register can be used to access individual array elements Arrays contained in structures and matrices two dimensional arrays can also be accessed with based indexed addressing String instructions do not use normal memory addressing modes to access operands Instead the index registers are used implicitly see Figure 2 21 When a string instruction executes the SI register must point to the first byte or word of the source string and the DI register must point to the first byte or word of the destination string In a repeated string operation the CPU will auto matically adjust the SI and DI registers to obtain subsequent bytes or words For string instruc tions the DS register is the default segment register for the SI register and the ES register is the default segment register for the DI register This allows string instructions to operate on data lo cated anywhere within the 1 Mbyte address space 2 34 intel OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE High Address s ow Address A1024 0A Figure 2 20 Accessing a Stacked Array with Based Index Addressi
375. werful set of memory to memory string operations allow efficient character data manipulation Finally routines with critical performance requirements can be written in assembly language and linked with high level code 2 2 4 Instruction Set The 80C186 Modular Core family instructions treat different types of operands uniformly Nearly every instruction can operate on either byte or word data Register memory and immediate op erands can be specified interchangeably in most instructions Immediate values are exceptions they must serve as source operands and not destination operands Memory variables can be ma nipulated added to subtracted from shifted compared without being moved into and out of reg isters This saves instructions registers and execution time in assembly language programs In high level languages where most variables are memory based compilers can produce faster and shorter object programs The 80C186 Modular Core family instruction set can be viewed as existing on two levels One is the assembly level and the other is the machine level To the assembly language programmer the 80C186 Modular Core family appears to have about 100 instructions One MOV data move in struction for example transfers a byte or a word from a register a memory location or an imme diate value to either a register or a memory location The 80C186 Modular Core family CPUs however recognize 28 different machine versions of the MOV instruction
376. yte 25 28 register word 34 37 memory byte 31 34 memory word 40 43 integer immediate multiply signed 01101051 mod reg data data if s 0 22 25 29 32 NOTES 1 Clock cycles are given for 8 bit 16 bit operations 2 Clock cycles are given for jump not taken jump taken 3 Clock cycles are given for interrupt taken interrupt not taken 4 If TEST 0 Shading indicates additions and enhancements to the 8086 8088 instruction set See Appendix 80C 186 Instruction Set Additions and Extensions for details D 4 intel INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D 2 Instruction Set Summary Continued Function Format Clocks Notes ARITHMETIC INSTRUCTIONS Continued AAM ASCII adjust for multiply 11010100 00001010 19 DIV Divide unsigned 1111011w mod 110 r m register byte 29 register word 38 memory byte 35 memory word 44 IDIV Integer divide signed 1111011w mod 111 r m register byte 29 register word 38 memory byte 35 memory word 44 AAD ASCII adjust for divide 11010101 00001010 15 CBW Convert byte to word 10011000 2 CWD Convert word to double word 10011001 4 BIT MANIPULATION INSTRUCTIONS NOT Invert register memory 1111011w mod 010 r m 3 AND And reg memory and register to either 001000dw mod reg r m 3 10 immediate to register memory 1000000w mod 100 r m data data if w 1 4 16 immediate to
377. ytes of code and the upper bank contains the odd bytes of code Memory used to store interrupt vectors and stack data must be 16 bits wide Memory address space between OH and 3FFH 1 Kbyte holds the starting location of an interrupt routine In re sponse to an interrupt the BIU fetches two consecutive even addressed words from this 1 Kbyte address space Stack pushes and pops always write or read even addressed word data 3 3 2 8 Bit Bus Memory and I O Requirements An 8 bit bus interface has no restrictions on implementing the memory or I O interfaces All transfers bytes and words occur over the single 8 bit bus Operations requiring word transfers automatically execute two consecutive byte transfers 3 4 BUS CYCLE OPERATION The BIU executes a bus cycle to transfer data between any of the integrated units and any external memory or I O devices see Figure 3 6 A bus cycle consists of a minimum of four CPU clocks known as T states A T state is bounded by one falling edge of CLKOUT to the next falling edge of CLKOUT see Figure 3 7 Phase 1 represents the low time of the T state and starts at the high to low transition of CLKOUT Phase 2 represents the high time of the T state and starts at the low to high transition of CLKOUT Address data and control signals generated by the BIU go active and inactive at different phases within a T state 3 7 BUS INTERFACE UNIT intel T CLKOUT SAT E V Valid Status _ y A150

80C186EB/80C188EB Microprocessor User`s Manual

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