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Ethernet PHY ASSP Singe Channel

1. Parameter te Conditions Min Typ Max Units Current 100 Extnernal 3 3V 70 mA B 1 5V consumption supplied 1 5 110 mA Internal 3 3V 180 mA kees 15V 0 mA 10B Extnernal 3 3V 120 mA 1 5V supplied 15V 70 mA Internal 3 3V 170 mA para 15V 0 mA Internal pull up Rstru 14 2 31 9 80 7 kQ strap resistor Internal pull down Rang 20 6 44 9 116 4 kQ strap resistor Input voltage low VDDIO 2 5V 0 0 7 V Input voltage VDDIO 2 5V 1 7 VDD V high Input voltage low VDDIO 3 3V 0 0 8 V Input voltage VDDIO 3 3V 2 0 VDD V high Output voltage Vol VDDIO 2 5V 0 1 V low lol OmA Output voltage Voh VDDIO 2 5V Vdd V high loh 0mA 0 1 Output voltage Vol VDDIO 3 3V 0 1 V low lol OmA Output voltage Voh VDDIO 3 3V Vdd V high loh 0mA 0 1 R19UH0082ED0201 RENESAS User Manual 105 8 2 4 100Base TX Differential Parameters on Secondary Side of Transformer Description Min Typ Max Units Notes 100M TX 95 1 05 V output high 100M TX mid 50 50 mV level 100M TX 95 1 05 V output low 10M TX output 2 2 2 8 V high Refer to ANSI X3 263 and IEEE802 3 standard for more information 8 2 5 100Base FX Output Characteristics Parameter Symbol Conditions Min Typ Max Units Output Voltage Low V 1 81 1 55 V Vol VDDIO Output Voltage High V 1 12 0 88 V Voh VDDIO R19UH0082ED020
2. Transmit Bit Name Description Mode Default 15 NEXT PAGE 1 next page exists RW 0 0 next page does not exist 14 RESERVED Write as 0 ignore on read RO 0 13 MESSAGE PAGE 1 message page RW 1 0 unformatted page 12 ACKNOWLEDGE2 0 cannot comply with message RW 0 1 will comply with message 11 TOGGLE 1 previous value equaled logic RO 0 zero 0 previous value equaled logic one 10 0 MESSAGE 11 bit code word to be RW 0x001 UNFORMATTED _ transmitted to link partner CODE 5 6 10 Register PHY 16 Silicon Revision Bit Name Description Mode Default 15 10 RESERVED Ignore on read RO 0 9 6 SILICON Four bit silicon revision identifier RO 0001 REVISION 5 0 RESERVED Ignore on read RO 0 2tENESAS 59 5 6 11 Register PHY 17 Mode Control Status Bit Name Description Mode Default 15 14 RESERVED Write as 0 ignore on read RW 0 13 EDPWRDOWN Enable the energy detect power down mode 0 energy detect power down is disabled 1 energy detect power down is enabled RW 0 12 RESERVED Write as 0 ignore on read RW 11 10 RESERVED Write as 0 ignore on read RW FARLOOP BACK Remote loopback enable All the received packets are sent back simultaneously in 100BASE TX FX only RW FASTEST Auto negotiation test mode 0 normal operation 1 activates test mode Note This bit can be used for
3. Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of ASSP in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products Patent for IEEE1588 A number of patents exist for systems related to IEEE1588 Renesas would request that customers ensure they comply with the relevant rights for these patents Renesas does not accept any responsibility for infringement of any patent rights by the customer R19UH0082ED0201 User Manual RENES How to Use This Manual Purpose and Target Readers R19UH0082ED0201 User Manual This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the PHY It is intended for users designing application systems incorporating the PHY A basic knowledge of electric circuits logical circuits and PHYs is necessary in order to use this manual The manual comprises an overview of the product descriptions of the PHY system control functions peripheral functions and electrical characteristics and usage notes Particular attention should be paid to the precautionary notes when using the manual These notes occur within the body of the
4. 0x1 This sets the pulse width to 8 ns Generally a smaller pulse may not be able to travel down a long cable and return as it is too weak a wider pulse may be too wide to measure a short cable as it is still transmitting when the reflection is already returning DIAG_SEL_LINE Set to 0 or 1 depending on which line pair should be measured 2tENESAS g R19UH0082ED0201 User Manual After writing to the register the result can be read immediately The results can be interpreted as ADC_MAX_VALUE The maximum measured value of the reflected wave This can be used to fine tune the value for the next ADC_TRIGGER value Typically the ADC_ Trigger should be set to half of the measured ADC_MAX_VALUE A value of 0 indicates that no reflection was detected DIAG_DONE Should be one otherwise the measurement has not been finished In this case the register needs to be read again However typically access through the SMI is so slow that the time between the write access to start the measurement and the read to read the results is much longer than the measurement DIAG_POL Indicates the polarity of the reflected wave If positive the end of the line was open if negative the end of the line has a shortcut DIAG_CNT This register contains the travel time for the signal in 8ns steps If there is no reflected wave the counter is at Ox1F If no cable is connected the value typically is 0x01 however if the CNT_WINDOW is larger than 0x01 this refl
5. 10 Only two buffer for timestamp left 11 Buffer is full immediate next read required or data will be lost 1 Rising edge triggered the RO event 0 Falling edge triggered the event GPIO number of the pin that RO triggered the event 00000 GPIOO 00001 GPIO1 00010 GPIO2 13 TIMESTAMP EDGE 12 8 TIMESTAMP_ GPIO 1 Timer overflow the event RO has not been processed on time and the timestamp may be broken 0 The timestamp is intact 1 An event was detected on RO the pin but could not be processed 0 All events were processed on time Rolling number for events on RO that pin 7 TIMER_ERROR 6 OVERRUN 5 0 TIMESTAMP_ NUMBER As it may not be required to read the complete timestamp since the first words usually do not change very often it is possible to get a direct access to the next timestamp In this case the INPUT_EVENT_DATA_BLOCK_READ register can be read which will always give access to the LSW of the next timestamp in memory To read a timestamp the INPUT_EVENT_DATA_BLOCK_READ is read first once and returns bits 15 0 of the next timestamp data Then the INPUT_EVENT_DATA_WORD_READ is read up to 5 times and reads out bits 31 16 bits 47 32 and so on To get bits 15 0 of the next timestamp the INPUT_EVENT_DATA_BLOCK_READ has to be read Thus it is not required to read the complete timestamp 2tENESAS a 7 5 6 INPUT_EVENT_DATA_BLOCK_READ Register
6. There are two ways timestamps can be transmitted between the nodes One way is called One Step In this mode the timestamp for transmit telegrams can be directly embedded in the telegram itself when it is transmitted However this approach increases the latency of the path through the PHY but it reduces required software overhead The other option is to use a Two Step approach In this mode the timestamp of the telegram is taken when it is transmitted and the timestamp is send in a follow up telegram This option requires more traffic and more software overhead but incurs a lower latency on the path Register access to PTP Many registers within the PTP block are 80 bits or 48 bits wide to control the whole width of the time representation To read or write these registers they need to be accessed 5 times 5 16 bit words 80 bits in a row Unless otherwise noted accesses are done with the least significant word bits 15 0 first 1588 Clock Control The clock handles the time which is to be synchronized between the different nodes To be adjusted it can be either directly set accelerated or decelerated and adjusted over a defined period The accessible clock is 80 bit wide with the upper 48 bits counting the seconds and the lower 32 bit counting the nanoseconds Thus the overflow is not at Oxffffffff but at Ox3b9acA00 1049 ns Internally the clock additionally handles additional 30 bits of sub nanosecond resolution to han
7. 1 errors 0 gt 0 errors will trigger 1 gt 1 triggers 2 gt 2 triggers 3 gt 4 triggers 4 gt 8 triggers 5 gt 16 triggers 6 gt 32 triggers 7 gt 64 errors triggers RW 23 10 7 BER_WINDOW Length of time for BER counter in 0 005 2 n ms 0 BER counter functions disabled 1 0 01 ms 2 0 02 ms 3 0 04 ms 14 81 92 ms 15 unlimited run window Writing a 0 resets the BER counter and restarts the time window RW 1 0 01 ms 23 6 0 BER_COUNT Counter for bit errors shows the amount of errors in the past time window Is updated every 100 us if BER_WINDOW 15 0x0 Example setting Typically the BER on a line should be in the range of 10exp 11 A significant increase of this number is an indication of a bad connection caused by some issue with the cable connectors or partner PHY 2tENESAS 44 Thus a typical setting could be as follows BER_CNT_LNK_EN 1 Enable Link Down in case of exhaustive bit errors BER_CNT_TRIG 2 This setting will set the maximum allowed amount of bit errors A smaller value may lead to link downs in case of single errors which may happen even on a good line BER_WINDOW 14 This will give the maximum time window In combination with a BER_CNT_TRIG of 2 three bit errors in this time window will put the link down After every 81 92ms the counter is reset so single bit errors are deleted As the logic will put the link down as so
8. Connect to GND via 12 4KQ resistor Pull Down 5k Q ATP Production test PoTxP POTXN 2 PORXP PORXN Media Interface a a E ME FL POLINKLED oer eme TI MDC moce LI moo Jo Jh hn Le mr pen eo O porxcik h mi ew PoRxD3 O Foz O Fos O Fos O Fos O PORXERR O POTXEN LI porxoo I Porxo 1 porxo2 porxos I XCLKO XCLK1 i PIO14 10 E o E Mu 50MHz RMII Mode POTXERR POCOLSD eror hr ooo eros hs o D EE DS Le hoo PL PL P IL Be BE er E Sou be GPios bo Pe Ee clock mode mE clock mode Eo a e eo bs i pos Bo food GPIO19 42 40 pe 2tENESAS 16 System Diagram The picture below shows the system diagram The PHY is connected to the MAC through a MII or RMII interface On the other side it is connected either to a CATS cable through some magnetics or to a fibre cable HW Prog Pins GP I O III II MII or RMII o Renesas Single Channel Industrial 10 100 Mbit Ethe rnet PHY Mic rocont roller 10BASE T or Netw orking ASSP or 100BASE TX or Sw itch ASIC FPGA SMI Interface 3 1 Device block diagram The device consists of two PHY s each connected to a PTP Framer block used to de encode the PTP frames and timestamp them a PTP timer block containing the PTP clock and a I O block for general configuration and I O handling The PTP support is only available on the PTP version 100BASE FX 1
9. Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free
10. These 33 pulses contain an acknowledge bit which is cleared at the start of the sequence Each partner starts to send FLP bursts and tries to receive them from the other with the acknowledge bit cleared After one partner has successfully received three identical FLP bursts it continues sending FLP bursts with the acknowledge bit set The other partner will wait until it has received this answer for three times After that both partners will send 6 8 FLP bursts with the acknowledge bit set to ensure that they have understood each other successfully After that both PHYs will resolve the information and decide on the optimum configuration Therefore it is required that at least 9 FLP bursts are sent to initiate a successful auto negotiation Thus a successful auto negotiation will last at least 72 ms up to 216 ms depending on the burst length if all transmissions are successful and the next page function is not used In case a pulse is distorted the process will start over again To improve the linkup time for two Renesas PHYs the nominal 16ms frame rate is reduced to allowed 8 ms and shortening the frame transmission time In this case two Renesas PHYs are able to negotiate within 72 ms without hurting the IEEE spec This core supports auto negotiation and implements the Base page defined by IEEE 802 3 It also supports the optional Next page function to get the remote fault number code R19UHO0082ED0201 2tENESAS User Manual 3
11. reading 0 PHY had no RX activity since last reading Cleared when read R LH 11 PHY_FD PHY runs on full duplex PHY runs not on fill duplex 10 PHY_LINK PHY has LINK PHY_100MB PHY runs on 100 MBit PHY runs not on 100 MBit PHY_10MB 1 0 1 0 PHY has no LINK 1 0 1 PHY runs on 10 MBit 0 PHY runs not on 10 MBit CA LED MODE Configure LED output see chapter 4 9 RW ACTIVE_LED _BLINK 1 Link LED blinks if activity is detected and ON if link is up 0 Link LED does not blink on activity When written this is set for the PHY number in PHY_ SELECT RW 2 0 PHY_ SELECT Select number of the PHY for which the other bits of this register will be read 000 Write to PHYO Others Reserved RW R19UH0082ED0201 User Manual 2tENESAS 21 4 7 interrupt Status register 7 20 To have a centralised register to get a summary of all possible interrupt sources an interrupt status register is placed at the top level in addition to the specific interrupt registers The bits in this register are only set if the corresponding interrupt is enabled in the interrupt source modules Bit Name Description Mode Reset 15 RESERVED R LH_ 0 14 CAP_TS_ST uPD60611 only R 0 ORED_INT The PTP capture unit stored an event 13 CAP_MEM_ uPD60611 only R 0 FULL_INT PTP capture buffer is full
12. 1011 Data B 11010 C 1100 Data C 11011 D 1101 Data D 11100 E 1110 Data E 11101 F 1111 Data F 11111 Undefined IDLE Used as inter stream fill code J 0101 Start of Stream Delimiter Part 1 of 2 11000 Always used in pairs with K K 0101 Start of Stream Delimiter Part 2 of 2 10001 Always used in pairs with J T Undefined Eracar meam Pentel Part 1 of 2 01101 Always used in pairs with R End of Stream Delimiter Part 2 of 2 00111 i ele Always used in pairs with T Transmit Error 00100 akii Used to force signaling errors 00000 V Undefined Invalid code 00001 V Undefined Invalid code 00010 V Undefined Invalid code 00011 V Undefined Invalid code 00101 V Undefined Invalid code 00110 V Undefined Invalid code 01000 V Undefined Invalid code 01100 V Undefined Invalid code 10000 V Undefined Invalid code 11001 V Undefined Invalid code R19UH0082ED0201 RENESAS User Manual 35 5 5 Functional Description 5 5 1 Collision detection When transmissions from two stations overlap the resulting contention is called a collision Collisions occur only in half duplex mode where a collision indicates that there is more than one station attempting to use the shared Physical medium 5 5 2 Carrier Sense detection Carrier Sense CRS is asserted by the core when either transmit or receive medium is non idle For the half duplex mode Carrier sense is asserted during transmission or reception For Full duplex mode Carrier sense is asserted dur
13. CLKS50MHZ ns CLK50MHZ frequency 50 MHz 1 External 50MHz clock input R19UH0082ED0201 User Manual 2tENESAS 100 8 1 6 2 RMII Transmit Timing CLKSOMHZ 1 P TXD 1 0 P TXEN Figure 8 RMII transmit timing Valid data T8 1 T82 Para meter Description Min Typ Max Units Notes T8 1 Transmit signals setup to rising edge of CLK50MHZ ns T8 2 Transmit signals hold to rising edge of CLKS50MHZ ns CLK50MHZ frequency 50 MHz 1 External 50MHz clock input R19UH0082ED0201 User Manual 2tENESAS 101 8 1 7 Sequence for turn on RESETB must be released after all external power is ready Crystal Clock UMA ALL External Power ei tror ess Figure 9 Reset timing User Manual Paramet Description Min Typ Max Units Notes er tpor Power on 4 ms Reset timing 102 8 2 DC Characteristics 8 2 1 Absolute Maximum Ratings R19UHO0082ED0201 Parameter Symbol Conditions Rating Units Analogue P1VDDMEDIA 0 5 to 2 0 V power supply POVDDMEDIA VDDAPLL voltage Digital Power VDD15 0 5 to 2 0 V Supply Voltage UO Voltage VDDIO 0 5 to 4 6 V Analog 3 3V VDDACB 0 5 to 4 6 V power supply Analog 3 3V REGAVDD 0 5 to 4 6 V power supply REGBVDD Analog 3 3V VDD33ESD 0 5 to 4 6 V pow
14. FEQ monitor Register Bit Name Description Mode Default 15 0 FEQ_ DELTA Minimum change of value compared to the reference value latched when the monitor is enabled which will trigger the FEQ interrupt and link down If the FEQ value differs by more than that value the link goes down if the BER_CNT_LNK_EN is 1 and the BER Monitor is enabled The interrupt is triggered if enabled FFFF will disable monitor and cause the reference value to be relatched continuously FFFE will not change the FEQ_ DELTA value but enable to read out the current reference value when FEQ_VAL is read instead of the current value Writing any other value will disable this mode W OxFFFF 15 0 FEQ_VAL If FEQ_DELTA FFFE Bit 17 2 of the reference value Else Bits 17 2 of the current FEQ2 coefficient RO 2tENESAS 64 R19UH0082ED0201 User Manual 5 6 19 Register PHY 25 Diagnosis Control Status Register Bit Name Description Mode Default 15 Reserved Write with 0 ignore on read RW 14 DIAG_INIT When set to 1 create one cycle pulse init TDR test RW self cleared 13 8 ADC_MAX_ VALUE Shows the signed maximum minimum value of the reflected wave After the TDR process has been started the PHY will send out a trigger pulse and wait for the reflected wave for 255 clock cycles of 8 ns After the time
15. POCOL Input for SD signal MII mode COL signal Else same as GPIOO 11 8 Reserved Write as 0 RW 1111 7 4 Reserved Write as 0 RW 1111 3 0 Reserved Write as 0 RW 1111 2tENESAS 27 R19UHO0082ED0201 4 10 LED configuration The device offers a very flexible configuration for the LED outputs Most of the GPIO can be assigned to one of four LED sources which may be driven by one of the signals in the following table Name Description LinkA_LED Link By setting bit ACTIVE_LED_BLINK in the LED_STATUS register this can be used to light when a link is established and to blink when there is activity on the line FD_LED This LED is turned on whenever the device is configured for Full Duplex in fix mode or after the Autonegotiation process is finished and has resolved into FD mode HD_LED Link is established in Half Duplex mode This LED is turned on after a link is actually established in HD mode It is not turned on when the device is configured in HD fix mode 100BT_LED Link is established in 100 BT mode 10BT_LED Link is established in 10 BT mode ACT_LED LED blinks when there is activity MUX_100BT 10BT Pin is shared for two LED signaling 100BT and 10 BT speed Active Low refers to 100BT MUX_LINKA FD Pin is shared for two LED signaling Link Activity and Full Duplex mode Active Low refers to LINKA MUX_LINKA HD Pin is shared for two LED signaling L
16. R W 0 ULL_INT_MA 9 Interrupt is enabled Sb 1 Interrupt is disabled 12 PTP_PERIO uPD60611 only RW 0 D_INT_MAS o Interrupt is enabled i 1 Interrupt is disabled 11 10 Reserved 9 TIMESTAMP uPD60611 only R W 0 _RXO_INT_M 0 Interrupt is enabled ASK 1 Interrupt is disabled 8 TIMESTAMP uPD60611 only RW 0 _TXO_INT_M 9 Interrupt is enabled ASK 1 Interrupt is disabled 7 4 Reserved RW 0 3 PHYO_LINK_ 0 Interrupt is enabled R W 0 DOWN_INT_ 4 Interrupt is disabled MASK 2 PHYO BER 0 Interrupt is enabled R W 0 OVER_INT_ 4 Interrupt is disabled MASK 1 PHYO _FEQ_ 0 Interrupt is enabled R W 0 NT_MASK 1 Interrupt is disabled 0 PHYO_GENE 0 Interrupt is enabled R W 0 RAL_INT_M 4 Interrupt is disabled ASK R19UH0082ED0201 RENESAS User Manual 23 4 9 GPIO The GPIO pins are highly configurable to adjust the device to the requirements of the application So for example if RMII is used the freed pins can be used for additional PTP debugging or LED signals The GPIO registers are located in the GLOBAL_CONFIG address range Each GPIO pin has a 4 bit configuration register assigned The register configuration is only used if the pin is not used for Ethernet handling So for example if MII is used many pins are used for MII In this case the GPIO configuration register is an input Most GPIO can be assigned to one of four LED signals 4 9 1 GPIO_CONFIG_0 Register 7 0 per sec
17. cycle times that can be achieved and the accuracy at which a system can be operated This has two implications one is the amount of latency which should be reduced as much as possible even more important is the jitter i e the latency should always stay the same 2tENESAS Sg Although the Renesas PHY has already a very short latency the PHY has a special mode that will reduce the latency even further This mode is called J only mode and is available on all devices of the PHY family A new telegram is initiated by two symbols J and K as shown in the picture below 010 MII Data Line Data 1010 IDLE 11010 1011 i 11111 111000 J 10001 K 10110410110 10110 10110 10110 aA E 1010 made heal adere 101 10110 10110 10110 10110 10110 10 Source Addr 6 Byte Data 46 1500 Byte FCS 4 Byte Length 2 Byte Preamble SFD Dest Addr 0 7 1 Byte 6 Byte Before data is sent it is transformed from a 4 bit notation at the MII to a 5 bit notation on the line to ensure that enough changes are available for the clock regeneration In addition the 5 bit coding allows for transmission of additional control symbols to indicate start of frame and end of frame So a start of frame is indicated by the symbol 11000 or J followed by a 10001 or K Standard devices conforming to the Ethernet standard must detect
18. enable the pulse generation by writing PULSE_GO with one and setting PULSE CONFIG to the required value For continuous pulse the start times are calculated by taking the previous start time adding the interval time comparing the result to the timer and generating the next pulse when the timer value exceeds the start time SINGLESHOT PULSE CONTINUOUS PULSE Pulse width Pulse width INTERVAL TIME gt lt gt START TIME gt START TIME There are four registers to control the pulse generators All registers are shadow registers which can be written first and are transferred to the pulse channel in PULSE_CHANNEL at the moment the PULSE_GO bit is written with 1 After writing the PULSE_CHANNEL register these registers are updated with the actual value for this channel and can be read 2tENESAS 89 7 6 1 Pulse Output Control Register 7 16 The Pulse Output Control register controls the pulse units All data written is stored for the channel selected in PULSE_CHANNEL Bit Name Description Mode Default 15 10 Reserved write as 0 ignore R W on read 9 LATCH_WIDTH Latch newly written data from WC 0 PULSE_WIDTH register and use for next pulse This bit is typically set after the PULSE_WIDTH register has been written and when the new values should be applied Until this is done the old value is used 8 LATCH_INTERVAL Latch newly written latch WC 0 interval
19. has elapsed the DIAG_DONE bit is set The ADC MAX_VALUE will indicate the maximum of the received wave if positive or the minimum if negative RO 13 8 ADC_Trigger Threshold for pulse detection should be 0 5V 00111 for cable length detection or 1 5V 01111 for no cable detection MSB should always be 0 WO DIAG_DONE Indicate that the counter has been stopped either by counter overrun or by a ADC trigger Cleared after reading RO DIAG_POL 0 Counter stopped by positive trigger level 1 Counter stopped by negative trigger level RO DIAG_SEL_LINE 1 perform diagnosis on TX line 0 perform diagnosis on RX line RW 4 0 PW_DIAG Pulse width for Diagnosis 0 Diagnosis turned off Other Pulse width value 8ns RW 2tENESAS 65 R19UH0082ED0201 User Manual 5 6 20 Register PHY 26 Diagnosis Counter Register Bit Name Description Mode Default 15 8 CNT_WINDOW Minimum time after which the counter stops Used to filter out any pulses or reflections generated from the local connector or similar sources One tick equals approx 0 8m RW 7 0 DIAGCNT Indicates the location of the received signal which exceeded the threshold When DIAG _INIT is set to 1 initiated by HW to 000000 1111111 indicates no reflection Any value different from zero indicates a valid measurement When n
20. offset latch 2 0 DRIFT_WRITE Value of pointer pointing to the RO 0 _POS CLOCK_DRIFT register If 0 next write goes to the least significant word off offset latch The CLOCK_READ register is used to read the actual value of the clock It must 7 3 2 CLOCK_READ Register 6 1 be accessed five consecutive times to read the complete data Any read to another register will reset the internal pointer and the next read will then again read the highest word All accesses are done with the most significant word first Bit Name Description Mode Default 79 0 CLOCK_READ Clock read register RO 0 R19UH0082ED0201 User Manual 2tENESAS 72 R19UH0082ED0201 User Manual 7 3 3 CLOCK_WRITE Register 6 2 This register can be used to set the clock to a value It must be written five consecutive times The data is latched into the clock when the S word is written All accesses are done with the most significant word first Bits Name Description Mode Default 79 0 CLOCK_WRITE Clock write register WO 7 3 4 CLOCK_OFFSET Register 6 3 This register is used to adjust the clock to a new value To avoid sudden jumps the offset is not added at once instead the OFFSET is added subtracted to the clock value after OFFSET_INTERVAL for OFFSET_COR_COUNT times Thus the clock is slowly adapted to the new value and jumps are avoided All values are la
21. simulation In this mode expanded time of S W reset becomes shorter too RW AUTOMDIX_EN AutoMDIX enable bit 1 Auto detect MDI MDIX mode 0 Manual set of MDI MDIX mode According to bit MDI mode Reg17 6 AutoMDIX is disabled in FX Mode RW Strap option MDI MODE MDI MDIX mode control status 1 MDIX mode 0 MDI mode When AutoMDIX_en 17 7 is disabled this bit is used for manual control of MDI MDIX mode If AUtoMDIX_en Bit 17 7 is enabled it shows the status and will not be written to RW RESERVED Write as 0 ignore on read RW RESERVED Write as 0 ignore on read RW FORCE GOOD LINK STATUS 1 Force 100BASE X link active 0 normal operation Note this bit should be set only testing RW R19UH0082ED0201 User Manual 2 ENESAS 60 1 ENERGYON Indicates whether energy is RO 0 detected on the line If no valid energy is detected within 256ms this bit goes to 0 0 RESERVED Write as 0 ignore on read RW 0 5 6 12 Register PHY 18 Special Modes Bit Name Description Mode Default 15 11 Reserved Write as 0 ignore on read RW 0 NASR 10 FX_MODE Enable 100BASE FX mode RW Strap 1 FX mode enable NASR option When PHYMODE should be set to 0011 or 0010 only 9 Reserved Write as 0 Ignore on read RW 0 8 5 PHYMODE PH
22. to rising edge of P TXCLK T4 3 P TXD valid to start of TX bit sai fi P TXCLK 25 MHz frequency P TXCLK duty 45 50 55 EI cycle R19UH0082ED0201 2tENESAS User Manual 8 1 5 10Base T Timings 8 1 5 1 10M MII Receive Timing P RXCLK P RXDJ3 0 P RXDV P RXERR Figure 5 10BT MII receive timing LI TL TI Para meter Description Min Typ Max Units Notes T5 1 Received signals output delay after rising edge of P RXCLK 100 300 ns P RXCLK frequency 2 5 MHz P RXCLK duty cycle 45 50 55 R19UH0082ED0201 User Manual 2tENESAS 98 8 1 5 2 10M MII Transmit Timing P TXCLK P TXD 3 0 P TXEN P TXERR Figure 6 10BT MII transmit timing T6 1 T6 2 Para meter Description Min Typ Max Units Notes T6 1 Transmit signals setup to falling edge of P TXCLK ns T6 2 Transmit signals hold to falling edge of P TXCLK 100 ns P TXCLK frequency 2 5 MHz P TXCLK duty cycle 45 50 55 R19UH0082ED0201 User Manual 2tENESAS 99 8 1 6 RMII 10 100Base TX Timings 8 1 6 1 RMII Receive Timing P RXD 1 0 P CRS_DV Figure 7 RMII receive timing CLKSOMHZ 1 L Para meter Description Min Typ Max Units Notes T7 1 Receive signals output delay after rising edge of
23. 001 Reserved 1010 Reserved 11 8 GPIO6 Same as GPIOO except RW MII 0110 POCRS in MII mode 0110 PLLREADY in RMII mode POCRS Indicates that PLL is operating RMII 0111 Clock signal with 1ms 0110 1000 Clock signal with 1us PLLREADY 1001 Reserved 1010 Reserved 7 4 GPIO5 Same as GPIOO except RW 1010 RMII 0111 Reserved 1111 MIl 1000 Reserved 1001 Reserved 1010 TXCLK 25 Mhz 3 0 GPIO4 Game as GPIOO RW 1101 Interrupt 2tENESAS 25 R19UHO0082ED0201 User Manual 4 9 3 GPIO_CONFIG_2 Register 7 2 Bit Name Description Mode Reset 15 12 GPIO11 MII mode RW 1111 POTXD2 RMII mode Same as GPIOO 11 8 GPIO10 MIl mode RW 1111 POTXD3 RMII mode Same as GPIOO 7 4 GPIO9 Game as GPIOO RW 0110 MII 1000 RMII 3 0 GPIO8 Mil mode always PORXD2 RW 1111 regardless of setting RMII mode Same as GPIOO except 0111 always 0 1000 always 1 1001 Reserved 1010 Reserved 4 9 4 GPIO_CONFIG_3 Register 7 3 Bit Name Description Mode Reset 15 12 Reserved Write as 0 11 8 GPIO14 Same as GPIOO except RW 0110 0110 PLLReady PLL operating and PLLREADY locked 7 4 Reserved Write as 0 RW 1111 3 0 Reserved Write as 0 RW 1111 2tENESAS 26 R19UH0082ED0201 User Manual 4 9 5 GPIO_CONFIG_4 Register 7 4 Bit Name Description Mode Reset 15 12 GPIO19 FXMode RW 0110
24. 01 10Mbps half duplex 101 10Mbps full duplex 010 100BASE TX half duplex 110 100BASE TX full duplex 1 RX_DV_J2T_ _ 0 rx_dvrises on JK delimiter RW 0 falls on TR delimiter 1 J ONLY _MODE rx_dv rises on J delimiter falls on T delimiter Do not use in RMII Mode 0 SCRAMBLE 1 disable data scrambling RW 0 DISABLE 0 enable data scrambling 2tENESAS 68 6 1 6 2 6 3 R19UH0082ED0201 User Manual External Components Clock The devices can be operated on an external 25 MHz clock in MII mode or an external 50 MHz clock in RMI mode In addition for MII mode it contains an internal oscillator which may generate the required 25 MHz clock using an external 25 MHz crystal connected to the pins XCLK1 and XCLKO Internal Regulator The device contains an internal voltage regulator which generates the internal 1 6 V for the core from the external 3 3V power supply It can be disabled by tying REGOFA and REGOFFD to 3 3V and connecting the pins mentioned below directly to a 1 6 V power supply Otherwise the REGOFFA and REGOFFD pins must be connected to GND Power Up Sequence In case the internal voltage regulator is not used and the 1 5V supply is supplied form an external source a special power up sequence is not required However the time of power supply rise and the point when both power supplies are stable must be within 100 ms 2tENESAS 69 7 1 R19UH008
25. 0201 User Manual 5 6 3 Register PHY 2 PHY Identifier Bit Name Description Mode Default 15 0 PHY ID Assign to the 3rd through 18th RO 0xb824 NUMBER bits of the Organizationally Unique Identifier OUI 5 6 4 Register PHY 3 PHY Identifier Bit Name Description Mode Default 15 10 PHY ID Assigned to the 19th through RO Ox0a NUMBER 24th bits of the OUI 9 4 MODEL Manufacturer s model number RO 0x1 NUMBER 3 0 REVISION Manufacturer s revision number RO 0x4 NUMBER 2tENESAS 55 R19UH0082ED0201 User Manual 5 6 5 Register PHY 4 Auto Negotiation Advertisement Bit Name Description Mode Default 15 NEXT PAGE 1 next page capable RW 0 0 no next page ability 14 RESERVED _ Write as 0 Ignore on read RO 0 13 REMOTE 1 remote fault detected RW 0 FAULT 0 no remote fault detected 12 RESERVED __ Write as 0 ignore on read RW 0 11 10 PAUSE 00 no PAUSE RW 00 OPERATION 94 asymmetric PAUSE toward link partner 10 Symmetric PAUSE 11 both symmetric PAUSE and asymmetric PAUSE toward local device 9 100BASE T4 1 100BASE T4 able RO 0 0 no 100BASE T4 ability This core does not support 100BASE T4 8 100BASE TX 1 100BASE TX full duplex able RW 1 FULL 0 no 100BASE Tx ability DUPLEX 7 100BASE TX 1 100BASE TX able RW 1 0 no 100BASE TX ability 6 10BASE T 1 10Mbps with full duplex RW 1 FULL 0 n
26. 0BASE T 100BASE TX R19UHO0082ED0201 RENESAS User Manual 17 Global Hardware Description The device consists of an Ethernet PHY with hardware support of IEEE1588 In addition it includes a control block which is used to control shared resources such as LED outputs interrupts and low power modes All are interfaced through a two wire bidirectional Serial Management Interface 4 1 Register Access All registers can be accessed through the MII SMI interface The SMI is a serial interface defined in IEEE802 3 for access to PHY registers The following picture shows a typical access using the SMI interface Write Cycle MDC i i i i i i sl i MDIO 3275 o T o TAXED EDEDED ROERE XOXO XEXEX Startofi oP Preamble i i PHY Address Register Address TUM Data Frame Code i Around MDC 7 ii MDIO BITS 0 12 1 10 KREXASKXADKATDXADKROXRIXROXRDXROX EXA DXX Preamble Startof OP PHY Address Register Address Tum Data i Frame Code i 7 Around The PHY address denotes the address of the PHY while the register address is the address of the register within the addr
27. 1 P pone 1 AUTOMDI X enabled CR 0 FX Mode for PHYO in this case the values of Autoneg Duplex Quick Autoneg PORXD3 1 PU PORXERR PORXDV are ignored for this PHY 1 PU 1 TX Mode for PHYO Configures the upper two bits N and M of the PHY addresses 00 device uses address 00xxx for SMI PORXDO 00 PD PORXD1 01 device uses address 01xxx for SMI 10 device uses address 10xxx for SMI 11 device uses address 11xxx for SMI R19UH0082ED0201 AS User Manual RENES 31 PHY 5 1 General Description The block diagram for each is shown below Xd ASVaool XL ASVao0l 1 3sv804 Xd ASVaool q Tid J A0SS0190 NY uonegobau oyny JouuoD Lo2puetut juaWaBeueY jenas IS Le e Jeu un Ip 1 ide Ee Bulposap JayaAuo0o ENEE Bulposap eyd OAY Aere E ee ZYN O IZAN Ga ep a avas n v y Jeu 13418991 gt Burpooap 1 3SY804 Jaysayouew We AW ra e J AUP au Ae Burpooua 1 3sv804 L 3svaol da seyoue WN ywusues J Aup au Jeueaugo0 Burposua Jeueaugo0 Burpooua La ra ra 1 aquen XL 3Sva001 via CN GON 0 ZYN Dies S agar 32 2tENESAS R19UHO0082ED0201 User Manual 5 2 5 3 5 4 R19UH0082ED0201 User Manual Clock Generator PLL The PLL is a 125 MHz PLL which generates the clock for the 125 MHz pa
28. 1 RENESAS User Manual 106 Physical dimensions 48 PIN PLASTIC LQFP FINE PITCH 7x7 detail of lead end UNIT mm ITEM DIMENSIONS D 7 00 0 20 E 7 00 0 20 HO 9 00 0 20 HE 9 00 0 20 A 1 60 MAX Al 0 10 0 05 A2 1 40 0 05 0 25 b 0 20 8 93 c 0 125 RK L 0 50 Lp Dennis L1 141 00 0 20 o ac 0 0 50 x 0 08 y 0 08 zD 0 75 nora a SC SEN Each lead centerline is located within 0 08 mm of its true position at maximum material condition 2010 Renesas Electronics Corporation All rights reserved R19UH0082ED0201 ztENESAS User Manual 107 R19UH0082ED0201 User Manual Revision history Date Revision Changes April 9 2013 24 Strap option register added minor changes Remove package other than LQFP48 March 19 2013 2 0 Electrical characteristic updated Register description updated Sept 03 2012 1 1 Updated GPIO Registers updated MII TX Timing May 31 2011 1 0 Initial release 2tENESAS 108 Industrial Ethernet P HY R19UH0082ED0201 2tENESAS User Manual 109
29. 12 PTP_PERIO uPD60611 only R 0 D_INT Pulse generator started new period 11 10 Reserved R 0 9 TIMESTAM uPD60611 only R 0 P_RXO_INT PHYO has received a telegram which caused a timestamp to be taken 8 TIMESTAM uPD60611 only R 0 P_TXO_INT PHYO has transmitted a telegram which caused a timestamp to be taken 7 4 Reserved R 0 3 PHYO_LINK PHYO has triggered a Link Down R 0 _DOWN_IN Interrupt 7 2 PHYO_BER_ PHYO has triggered a BER Interrupt R 0 OVER_INT 1 PHYO _FEQ_ PHYO has triggered a FEQ interrupt R 0 INT 0 PHYO_GEN PHYO has triggered one of its R 0 ERAL_INT internal interrupts except for Link Down BER and FEQ interrupts R19UHO0082ED0201 User Manual 2tENESAS 22 4 8 Interrupt Mask register 7 21 To have a centralised register to get a summary of all possible interrupt sources an interrupt mask register is placed at the top level in addition to the specific interrupt registers Note that this is just an additional option to mask all interrupts at a central register all Interrupts need to be enabled at their respective location within the PHY or PTP register set Therefore the mask register is be default enabled while the interrupt sources are by default disabled Bit Name Description Mode Reset 15 Reserved RW 0 14 CAP_TS_ST uPD60611 only RW 0 ORED_INT_ 9 Interrupt is enabled MAS 1 Interrupt is disabled 13 CAP_MEM_F uPD60611 only
30. 2ED0201 User Manual Support of IEEE1588 uPD60611 only Renesas Electronics Ethernet PHY uPD60611 supports the precision time protocol PTP according to IEEE1588 to support requirements towards higher precision and faster production The PHY supports IEEE1588 V1 and V2 including transparent clock mode and one step or two step mode Furthermore the PHY is able to timestamp incoming messages with a resolution of 1ns The following clock modes are supported e Ordinary clock e Boundary clock e Transparent clock The PHY can timestamp events on any of the GPIO pins Based on the internal synchronized clock it may generate up to three output signals which may generate single pulses or repetitive pulses with programmable pulse length It is also possible to output a Pulse Per Second PPS signal Resolution for the event timestamping unit and the pulse generation unit is 8ns Reception of a PTP message transmission of a PTP message an event on the event unit and the pulse generator can generate an interrupt IEEE1588 The basic purpose of IEEE1588 is to synchronize clocks in different nodes and have them run on the same time and frequency One clock in a node is selected as the master clock and all other clocks called slave clocks in the system are synchronized to this clock called master clock Special PTP telegrams are exchanged between the nodes to distribute the time value of the master clock To compensate the travel ti
31. 5 7 31 in the GLOBAL_CONFIG area is possible 0 Device is enabled 10 PULSE 0 Pulse Output logic is enabled RW 1 PWD 1 Pulse Output logic for GPIO is powered down 9 CAP_PWD 0 Capture logic is enabled RW 1 1 Capture logic for GPIO is powered down 8 PTP_PWD 0 PTP is enabled RW 1 1 PTP is powered down 10 1 Reserved RW 0 PHYOPWD 1 The analog and digital part of the RW 0 PHYO is powered down 0 PHYO is enabled R19UH0082ED0201 User Manual 2tENESAS 19 4 4 PHY Status Register 7 28 The following register shows the status of the PHYs Bit Name Description NES Reset 15 10 Reserved Write as 0 RW 0 9 Reserved Write as 0 R 0 8 PHYO LINK 0 PHY 0 has no link R 0 1 PHY 0 has link 7 2 Reserved Write as 0 RW 0 1 Reserved Write as 0 R 0 0 PHYO 1 PHY is powered up and able to R 0 SYSRST operate Reset not active 0 PHY is still powering up The SYSRST registers are set by the PHY after the PLL has been powered up and has stabilized They need to be 1 for the device to operate and to get access to all functions Otherwise the internal 125 MHz clock is not available 4 5 Strap option Register 7 27 The following register shows the strap option value latched after reset Bit Name Description Mode Reset 15 QUICK_AUT Autonegotiation strap setting RO Strap ONEG option 14 AUTO_NEG Quick Autonegot
32. 588 Clock Control asscscssicccccsccetecd sc tesisiecacteciatcesasleccnteccescnnazssisessaceccebacdesactazans 71 7 3 4 CLOCK_STATUS Register 6 0 c cccsseecesecesseeeesneeeeseeeseeeeessaesesneeeeeeeeseeesesnasensneeesenees 72 7 3 2 CLOCK_READ Register 6 1 sites cesctesciscees cectiecsedeects detec cisties des ieane lindas deletes science 72 7 3 3 CLOCK_WRITE Register 6 2 ccccssscecesseeceeeeseeeeeeeeeeeeeessaeeeeeesaeeeseseeeeenseaeeeeeeseneeenss 73 7 3 4 CLOCK_OFFSET Register 6 3 vsicvs sssecccsctescesctedives sesscestececessedsiees deities eiaiies delecessedaenss 73 7 3 5 CLOCK DRIFT Register 6 4 ticaccs sicecsecetecsntenseteaticerserendyecedetasesacdeataceieunnseattedvesedsendnerstucas 74 7 4 Frame Handling RE 74 UAT e TE We TE 75 ZZ Transparent Mode veciisciccccicdseecscdecciedovenstescscvecatanenecasceertietansancaaccerseesaveaneabtosieeetevnanseaotaneces 75 7 4 3 Timestamp Status Register 6 6 ccccceceseesseeeeeeeeeeeeeeeneeeeeeeeseeeeeaneeseeeeeseeseeaneneesees 76 7 4 4 Timestamp Configuration Register 6 7 cccceceseeeeeeeeeeeeeseeeeeeneeeeeeeeseeeeneneeeeeees 77 7 4 5 TIMESTAMP_LINE_EVENT Register 6 8 cc cccessssceeessecceeeesseeeeesseeeeeessaeeeeneneeeeenes 78 7 4 6 PTP_CONFIG Register 6 9 ccssscccessscceeesseeeeeeseeeeeeesneeeeeesnaeeeeeesaeeeensneeeeenssaeeeensneeeeeess 79 7 4 7 PHY DELAY TX Register 6 11 cccicscsccecscstecvescescceeescescveesessceietestovecves
33. 7 14 Bit Name Description Mode Default 15 0 TIMESTAMP__ Returns the least significant RO 0 READ_ BLOCK word bits 15 0 of the next timestamp 7 5 7 INPUT_CAPTURE_DATA_POINTER Register 7 13 Bit Name Description Mode Default 15 Reserved ignore on read RO 0 write as 0 14 8 FILLING LEVEL Amount of data sets in the RO 0 memory 0 Event memory is empty 64 Event memory is full 7 6 Reserved ignore on read RO 0 5 0 TIMESTAMP Value of the read pointer to RO 0 READ POS _BL the data sets event memory OCK 0 Next read will read from address 0 of timestamp memory 63 Next read will read from address 63 of timestamp memory R19UH0082ED0201 AS User Manual RENES 7 6 Pulse Generator Unit R19UH0082ED0201 User Manual The device has three pulse generator units which can generate pulses or events based on the PTP timer Each of them can run in two different modes single shot or continuous pulse generation A pulse is triggered when the START_TIME exceeds the time from the PTP timer Although the START_TIME has a resolution of 1 32 ns the exact output time may be up to 8 ns later as the output signal is running on the 125 MHz clock However internally the start time is calculated with 1 32 ns accuracy so the error does not add up To program a new pulse generation disable the current pulse generation for the respective channel write the values and re
34. 8 5 5 5 1 Improved Link Up time Quick Autonegotiation R19UH0082ED0201 User Manual In many applications a link up time of approx 2 seconds as required by IEEE 802 3 is too long To reduce the link up time the values of the BREAK_LINK_TIMER and the AUTONEG_WAIT_TIMER which are the main contributors to the long link up time can be configured to shorter values Thus the initial Link Up procedure can be significantly shortened Note that this process is only shortened if both PHYs are capable of using the shortened times If one PHY is not able to do this the normal link up times can be expected The BREAK_LINK_TIMER is required to assure that the partner PHY is definitely entering Link Down mode by disabling the transmission for the timer runlength However most PHY detect a missing link within a couple of us and are targeting lt 15us for industrial protocols so a timer length of gt 1250ms is not required in most cases So depending on the partner PHY the link up time can be reduced down to 80ms The AUTONEG _WAIT_TIMER is used if the auto negotiation state machine detects link signals when waiting for the FLP from the other PHY In this case it is assumed that the other PHY is running on either 10 MBit or 100 MBit fix mode The PHY will then wait for the duration of the AUTONEG_WAIT_TIMER to check if there are FLP or some other signals coming After the AUTONEG_WAIT_TIMER has expired and there were no other signals the link is established O
35. 9 INTO FEQ trigger RC 0 8 Reserved Ignore on read RC 0 7 INT7 1 ENERGYON generated RC 0 6 INT6 1 auto negotiation complete RC 0 5 INT5 1 remote fault TX Mode or RC 0 Far End Fault FX Mode detected 4 INT4 1 link down RC 0 3 INT3 1 auto negotiation Last Page RC 0 acknowledge 2 INT2 1 parallel detection fault RC 0 1 INT1 1 auto negotiation page RC 0 received 0 Reserved RO 0 5 6 24 Register PHY 30 Interrupt Enable Bit Name Description Mode Default 15 11_ Reserved Write as 0 Ignore on read RO 0 10 9 MASK BIT 1 interrupt source is enabled RW 0 0 interrupt source is masked 8 Reserved Write as 0 Ignore on read RO 0 7 1 Mask Bits 1 interrupt source is enabled RW 0 0 interrupt source is masked 0 Reserved Write as 0 Ignore on read RO 0 2tENESAS 67 R19UH0082ED0201 User Manual 5 6 25 Register PHY 31 PHY Special Control Status Bit Name Description Mode Default 15 14 Reserved Write as 0 ignore on read RW 0 13 Reserved Write as 0 ignore on read RW 0 12 AUTODONE Auto negotiation done indication RO 0 1 auto negotiation is done 0 auto negotiation is not done or disabled or not active 11 7 Reserved Write as 00000 Ignore on read RW 0 6 ENABLE 1 Enable 4B 5B RW 1 4B5B Encoding Decoding MAC MII MODE interface must be configured in 0 Bypass encoder decoder 5 Reserved Write as 0 ignore on Read RW 0 4 2 SPEED HCDSPEED value RO 000 INDICATION 0
36. Default 15 BER_LNK_OK Link quality indication indicates state of link monitor FSM 0 FSM is not in Good Link state 1 indicates FSM in Good Link state Will go up as soon as the counter is below the trigger level after start up Can be used to detect reliably link up after start up RO 0 14 BER_CNT_ LNK_EN 1 A trigger on the BER or on the FEQ monitor will cause a link down 0 A trigger on the BER FEQ will just cause the state machine to leave Good Link state RW 13 11 BER_CNT_TRIG Trigger level for BER Count to define link up down counter in 1 24 n 1 errors gt 0 errors will trigger gt 1 error will trigger gt 2 errors will trigger gt 4 errors will trigger gt 8 errors will trigger gt 16 errors will trigger gt 32 errors will trigger gt 64 errors will trigger NOOR Ga MM CH RW 10 7 BER_WINDOW Length of time for BER Counter in 0 005 2 n ms 0 BER Counter functions disabled 1 0 01 ms 2 0 02 ms 3 0 04 ms 14 81 92ms 15 unlimited run RW 1 0 01 ms 6 0 BER COUNT Counter for bit errors shows the amount of errors in the past time window or every 100 us if BER_WINDOW 15 Writing a 00 resets the BER counter and restarts the time window RO 0x0 R19UH0082ED0201 User Manual 2tENESAS 63 R19UH0082ED0201 User Manual 5 6 18 Register PHY 24
37. ED3 MUX FD HD Active Low refers to FD 0110 LEDO MUX LinkA FD Active Low refers to LinkA LED1 SD LED2 MUX 100BT 10BT Active Low refers to 100BT LED3 Activity 0111 LEDO Mux LinkA HD Mux frequency gt gt blink frequency Active Low refers to LinkA LED1 Activity LED2 10BT LED3 Mux 100BT HD Active Low refers to 100BT 1000 LEDO LinkA 2tENESAS 29 LED HD LED2 MUX 100BT 10BT _ Active Low refers to 100BT LED3 Activity 1001 LEDO MUX LinkA 100BT _ Active Low refers to LinkA LED SD LED2 100BT LED3 FD 1010 LEDO LinkA LED1 MUX SD Activity Active Low refers to SD LED2 MUX FD HD Active Low refers to FD LED3 MUX 100BT 10BT Active Low refers to 100BT 1011 LEDO LINKA LED MUX FD HD LED2 MUX 100BT 10BT Active Low refers to 100BT LED3 Activity 1100 LEDO Reserved 1111 LED1 Reserved LED2 Reserved LED3 Reserved 4 11 LED Mux To connect two LED to single pin a special logic is integrated which allows to control two LED on a single pin A schematic of this logic is shown below VDD 3 6V Data and oe controlled by LEDCTRL Normally the input pin of the device is tri stated so both LED are off By pulling the pin to either VDD or GND one of the two LED can be turned on In case both LED need to be turned the pin will toggle in a high frequency so both LED are on although they may be a little darker This mode is call
38. ES _TX is set 1 0 MODE_RX Set the PTP mode for RX RW 1 00 BC_PTP_V1 Boundary clock mode for PTP Version 1 telegrams For Sync and Delay_Req frames the timestamp is taken and stored in the timestamp buffer 01 BC_PTP_V2 Boundary clock mode for PTP Version 2 frames 10 TC_E2E_ PIP M Transparent clock end to end mode for PTP V2 telegrams 11 TC_P2P_PTP_V2 Transparent clock peer to peer mode for V2 telegrams For all other messages non PTP message no timestamp is taken unless the TS_ALL FRAMES _RxX is set The following table gives an overview on how the different telegram types are handled depending on the configuration An empty field means that nothing is done R19UH0082ED0201 AS User Manual RENES R19UHO0082ED0201 User Manual TX Path OC BC OC BC Ee v2 TCE2E TCP2P Frame type E2E P2P E2E P2P One One ele d One Two Step Step Step Step Step Step Copy TS Copy TS Add TS Add TS Sync Store TS to TS to TS Store TS to Cor to Cor field field field field FollowUp Add TS DelayReq Store TS Store TS Store TS Store TS to Cor field DelayResp Add TS PeerDelayReq Store TS Store TS to Cor Store TS field Add TS Add TS Add TS PeerDelayResp to TS Store TS to Cor to Cor field field field PeerDelayResp FollowUp RX Path OC BC OC BC vu ES Sg BC v2 v2 TCE2E TC P2P Fram
39. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics Rt uHo082E00201 Renesas CS User Manual The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communicat
40. Timestamp on both edges 7 6 IN_CAP_GPIO3 00 Disable event timestamping RW 0 for GPIO3 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges 5 4 Reserved Write as 0 RW 0 3 2 Reserved Write as 0 RW 0 1 0 IN_CAP_GPIOO 00 Disable event timestamping RW 0 for GPIOO 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges 7 5 3 Input Capture Pin Control register 7 9 The Input Capture Pin Control register is used to enable timestamping GPIO 8 to 15and is used to configure the edge on which it should trigger Bit Name Description Mode Default 15 14 Reserved Write as 0 RW 0 13 12 IN_CAP_GPIO14 00 Disable event timestamping RW 0 for GPIO14 User Manual 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges 11 10 Reserved Write as 0 RW 9 8 Reserved Write as 0 RW 7 6 IN_CAP_GPIO11 00 Disable event timestamping for GPIO11 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges RW 5 4 IN_CAP_GPIO10 00 Disable event timestamping for GPIO10 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges RW 3 2 IN_CAP_GPIO9 00 Disable event timestamping for GPIO9 01 Timestamp on rising edge 10 Timestamp on falling edge 11 T
41. Y mode of operation Is set RW Indirect according to strap pin setting NASR Strap after reset option 0000 4 3 PHY_ADD_DEV PHY address upper two bits RW Strap The PHY address is used to NASR option address the whole device and for the initialization of the Cipher Scrambler key 2 0 PHY _ADD_MOD PHY address lower three bits RW 000 The PHY address is used to NASR address the PHY and for the initialization of the Cipher Scrambler key 5 6 13 Register PHY 19 Elastic Buffer Status register Loopback Mode only Bit Name Description Mode Default 15 8 reserved Ignore on read RO H T_EL_BUF_OVF Transmitter elastic overflow RO LH 0 6 T_EL_BUF_UDF Transmitter elastic underflow RO LH 0 5 R_EL_BUF_OVF Receiver elastic overflow RO LH 0 4 R_EL_BUF_UDF Receiver elastic underflow RO LH 0 3 0 reserved Ignore on read RO R19UH0082ED0201 User Manual 2tENESAS 61 R19UH0082ED0201 User Manual 5 6 14 Register PHY 20 Reserved Bit Name Description Mode Default 15 0 Reserved Ignore on read RW 0 5 6 15 Register PHY 21 Reserved Bit Name Description Mode Default 15 0 Reserved Ignore on read RO 0 5 6 16 Register PHY 22 Reserved TSTREAD2 TSTWRT Bit Name Description Mode Default 15 0 Reserved Ignore on read RW 0 2tENESAS 62 5 6 17 Register PHY 23 BER Counter Bit Name Description Mode
42. ard LOM and network interface card NIC e Switches routers and repeaters with 10 100 Mbps capable ports e Mobile base stations e Test and measurement applications e Home servers broadband routers printers and IP phones e Telecom base stations e Real time networking R19UHO0082ED0201 2tENESAS User Manual 13 Pin Functions 2 1 Pinning Information DVOUT15 VDDIO POCRS RESETB TEST POCOLSD GNDAREF REGOFF AVOUT15 VDDA33REG VDDAPLL GNDAPLL R19UHO0082ED0201 User Manual 2 1 1 Pin Layout POTXERR L GPIO14 XCLK1 XCLKO C _VDDIO POTXCLK el POTXD3 POTXD2 POTXD1 el POTXDO Q O Z 3 POTXP C POTXN E POAGND 2tENESAS PORXP CL DORAN CT POAGND C VDDA15 C VDD33ESD EU VDD15 UH DOLINKLEDGH POTXEN vil 24 PORXER PORXDV PORXDO PORXD1 GNDIO VDDIO PORXD2 PORXD3 R PORXCLK INT MDIO MDC 14 R19UH0082ED0201 User Manual 2 1 2 Port Pins Im b rntier ESD enhancement POAGND 6 8 AnalogGNDforPHY 0 36 VDD15 GNDAPLL bn Analog GND for PLL VDDAIS p Analog 1 5V power supplyfor PHY MDDAPLL Analog 1 5V power supply for PLL VDDA33REG be ba power supply for voltage regulator 43 AnalogGND S O REGOFF 44 D GNDAREF M3 Regulator disable Hi Regulator Off Lo Regulator On Analog GND 2tENESAS 15 R19UH0082ED0201 User Manual Alternate Pin Comment EXTRES es Resistor EE
43. ayResp message 100 Delay Req message RO Undefined 175 96 TIMESTAMP Timestamp of the related event described in bits 95 0 Bits 175 128 seconds Pits 127 96 ns RO Undefined 95 16 SOURCEPORTIDENTITY sourcePortldentity extracted from the PTP telegram If TG ALL FRAMES _nnis set and a NonPTPFrame is received this field is empty RO Undefined 15 0 SEQUENCE_ID Rolling number assigned by sending port and extracted from telegram If TS_ALL_FRAMES is set and also normal non PTP telegrams are timestamped there may be no SEQUENCE _ID in the telegram thus the SEQUENCE _ID is generated internally starting with 0 RO Undefined To read a data set the timestamp memory register has to be accessed 12 times The least significant word is read first The TIMESTAMP_SELECT register must be written prior to each individual access to the timestamp memory register 2tENESAS 78 The PTP Config register is used to configure the framer unit The config register 7 4 6 PTP_CONFIG Register 6 9 for PHY 0 is located at address 6 9 Bit Name Description Mode Default 15 12 Reserved ignore on read write as 0 RW 11 TS ALL FRAMES_RX 1 Enable timestamping for all received telegrams The IPV4 and IPV6 filter bits are still used 0 Do not enable timestamping for all received telegrams RW 10 TS ALL FRAMES _TX 1 Enabl
44. cal variation of the FEQ2 value Example Typically the FEQ value will not change while the link is up except if the cable condition changes A value for FEQ_DELTA of 1000 is typically a good setting to detect cable condition changes reliably without being too sensitive The optimal value for the FEQ_DELTA depends on the quality of the cables and connectors used and should be optimized based on the requirements of the application To enable the FEQ monitor settings should be FEQ_DELTA 0x3E8 BER_CNT_LINK_EN 1 With these settings the FEQ monitor will sample the line condition after link up and will put the link down if these change Note that a bad line after link down is taken as a reference thus the software should check the value by reading FEQ_ VAL after link up and comparing this to a Known good value This should be determined after installation has been done Generally typical values can be taken from the picture above Interrupt 9 should also be enabled to inform the CPU about such an event R19UHO0082ED0201 2tENESAS User Manual 47 5 5 6 5 TDR Measurement Cable breaks can be localized using the built in TDR measurement logic This block sends out defined pulses and measures the time it takes for the reflected wave to travel forth and back Several configuration options allow to optimize the measurement to achieve down to 0 8m of accuracy The register to configure this is described below Bit Name Descripti
45. ch the next pulse is generated only for continuous pulse The shortest pulse interval value is 24 ns WO R19UH0082ED0201 User Manual 2tENESAS 92 Electrical Characteristics 8 1 AC Timing 8 1 1 Serial Management Interface SMI Timing MDC MDIO read EL T13 MDIO Valid data write Figure 1 SMI Timing Para Description Min Typ Max Units Notes meter NN MDC to MDIO 0 15 ns Data output delay from PHY T1 2 MDC to MDIO 10 ns setup 71 3 MDC to MDIO 10 ns hold MDC frequency 25 MHz User Manual 8 1 2 Reset Timing RESETB Strap pin latch 1 DR Device Ready Register access 2 Not available Available Figure 2 Reset Timing Para Description Min Typ Max Units Notes meter EN RESETB pulse 100 us width T2 2 Strap input 200 ns setup to RESETB rising T2 3 Strap input hold 400 ns after RESETB rising T2 4 Device Ready 600 us rising after RESETB rising T2 5 Register 5 ms access available after Device Ready rising 1 Strap options are latched Refer to 4 9 Strap Options 2 PHY register access through SMI is available T2 5 after Device Ready rising R19UH0082ED0201 AS User Manual RENES 8 1 3 Clock Timing R19UH0082ED0201 User Manual Para Description Min Typ Max Units Notes meter Reference 25 MHz MII
46. clock frequency 50 MHz RMII 25MHz 50 MHz selectable Clock 100 100 ppm frequency tolerance Duty cycle 40 50 60 Jitter tolerance 20 ps rms 1 1 Root Mean Square 2tENESAS 95 8 1 4 100Base TX Timings 8 1 4 1 100M MII Receive Timing P RXP N IDLE ENA 32V wi e Kay Kay Ki Ka D P RXCLK rd rd P RXD 3 0 P RXDV P RXERR Figure 3 100BT MII receive timing Para Description Min Typ Max Units Notes meter T3 1 Received signals output delay after 15 28 ns rising edge of P RXCLK 1 T3 2 Start of RX bit RX_DV_J2T to P RXDV 170 ns Register0 31 1 RX_DV_J2T 210 ns Register0 31 1 cleared P RXCLK 25 MHz frequency P RXCLK duty 45 50 55 cycle 1 Note that glitch may occur on output signals between min and max value of T3 1 after rising edge of P RXCLK However it is compliant with IEEE802 3 standard because the setup time at the input of MAC is 13ns Period 40ns max value gt 10ns and the hold time is 15ns min value gt 10ns R19UH0082ED0201 AS User Manual RENES 8 1 4 2 100M MII Transmit Timing P TXP N IDLE x J4 13 J2 J1 IX KXK Kl ln P TXCLK LT LS L P TXD 3 0 Valid data _ P TXEN ai 11 PIERR T41 Di T4 3 Figure 4 100BT MII Transmit Timing Para Description Min Typ Max Units Notes meter T4 1 Transmit 14 ns signals setup to rising edge of P TXCLK T4 2 Transmit 0 ns signals hold
47. data from the PULSE_INTERVAL register and use for next pulse This bit is set after the PULSE_INTERVAL register has been written and the new values should be applied Until this is done the old value is used 7 PULSE_GO Latch PULSE_STARTTIME WC 0 and use for next pulse This bit is usually set after the PULSE_STARTTIME register has been written and the new values should be applied To update the start time the pulsegen unit has to be stopped first 6 INT_EN Enable interrupt for this RW 0 channel An interrupt is triggered when the timer is larger than the current PULSE_STARTTIME continuously updated according to PULSE_INTERVAL 5 CHANNEL_INV Invert output of channel in 2 0 RW 0 4 3 PULSE Configuration for pulse RW 0 CONFIG 00 Off 01 Single shot 10 Continuous 11 Reserved 2 0 PULSE 000 Values in bits 9 3 and RW 0 CHANNEL respective shadow registers PULSE_STARTTIME PULSE_WIDTH and PULSE_INTERVAL will be written to channel 0 R19UHO0082ED0201 2tENESAS User Manual 90 R19UH0082ED0201 User Manual 001 Values in bits 9 3 and respective shadow registers will be written to channel 1 010 Values in bits 9 3 will be written to channel 2 7 6 2 PULSE_STARTTIME Register 7 17 The PULSE_STARTTIME register gives the start time for the next pulse For continuous pulses it is incremented with the PULSE_INTERVAL value after the pulse has been triggered T
48. dle drift correction As the clock of the device is running at 125 MHz the clock value is basically increased by 8ns with every clock cycle This 8ns value can be adjusted to speed up the clock or slow it down So although the clock is still incremented based on the 125 MHz clock it can be fine tuned so the value reflects the real time To access the clock the register has to be accessed five times with 16 bits each 2tENESAS 71 7 3 1 CLOCK_STATUS Register 6 0 The CLOCK_STATUS register is used to control the clock and the several registers used to access the PTP clock Bit Name Description Mode __ Default 15 reserved Write as 0 ignore on read RW 0 14 EN_OFFSET_ 1 Enable and start offset RW 0 CORR correction 0 Disable offset correction Automatically cleared after the offset correction is finished 13 OFFSET_RUN 1 offset correction in process RO 0 0 offset correction done 12 EN _DRIFT_C 1 enable drift correction RW 0 ORR 0 disable drift correction 11 9 CLOCK_READ Value of pointer pointing to the RO 0 _POS CLOCK_READ register If 0 next read is from least significant word of clock latch 8 6 CLOCK_WRIT Value of pointer pointing to the RO 0 E POS CLOCK_WRITE register If 0 next write goes to least significant word of clock latch 5 3 OFFSET_WRI Value of pointer pointing to the RO 0 TE_POS CLOCK_OFFSET register If 0 next write goes to the least significant word off
49. e any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics R19UH0082ED0201 AS User Manual RENES General Precautions in the Handling of ASSP Products The following usage notes are applicable to the series of these ASSP products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of ASSP Products and in the body of the manual differ from each other the description in the body of the manual takes precedence Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on The state of the product is undefined at the moment when power is supplied The states of
50. e timestamping for all transmitted telegrams The IPV4 and IPV6 filter bits are still used 0 Do not enable timestamping for all transmitted telegrams Only PTP telegrams are timestamped RW L2 1 Timestamp all Layer 2 PTP telegrams only for V2 messages 0 Do not timestamp layer 2 telegrams RW IPV4 1 Timestamp PTP frames containing IPV4 telegrams 0 Do not timestamp IPV4 telegrams RW IPV6 1 Timestamp PTP frames containing IPV6 telegrams only for V2 messages 0 Do not timestamp IPV6 telegrams RW ONE_STEP 1 Enable one step mode for the PHY In this mode the taken transmit timestamp is integrated in the frame on the fly and the CRC corrected In this mode the transmit timestamp is not stored in the timestamp memory 0 Select two step mode the transmit timestamp is not integrated in the outgoing frame RW 5 4 P2P_DELAY_ WRITE POS Current position of the PORT_DELAY_PHY register RO 3 2 MODE_TX Set the PTP mode for TX 00 BC_PTP_V1 Boundary clock mode for PTP V1 telegrams RW R19UH0082ED0201 User Manual 2tENESAS 79 01 BC_PTP_V2 Boundary clock mode for PTP V2 Telegrams 10 TC_E2E_ PIP M Transparent clock end to end mode for V2 telegrams 11 TC_P2P_PTP_V2 Transparent clock peer to peer mode for V2 Telegrams For all other messages non PTP messages no timestamp is taken unless the TS_ALL FRAM
51. e type One Two E2E P2P E2E P2P One One Step Step One Two Step Step Step Step Sub TS Sub TS from Cor from Cor Sync Store TS Store TS Store TS Store TS field Field Store TS Store TS FollowUp Sub TS DelayReq Store TS Store TS Store TS Store TS from Cor field DelayResp Sub TS Sub TS from Cor Sub TS PeerDelayReq from Cor Store TS field from Cor field field PeerDelayResp Sub TS Store TS Store TS from Cor Store TS field PeerDelayResp FollowUp 2 ENESAS 81 R19UH0082ED0201 User Manual 7 4 7 PHY_DELAY_TX Register 6 11 The PHY_DELAY_TX_PORT register is used to adjust the timestamp by the latency of the PHY s TX path This is by default set to 0 but may be corrected to also compensate for delays caused by the transformer PTP assumes that the line delay including the PHY latency in both directions is identical this may not be the case if PHYs from different vendors are used in a network In this case the PHY_DELAY_TX_PORT and PHY_DELAY_RX_PORT values should be set This value should be set to 40 Bit Name Description Mode Default 15 0 PHY_DELAY_ Value in ns by which RW 0 TX_PORT timestamps taken for the PHY on the TX side are corrected 7 4 8 PHY_DELAY_RX Register 6 12 The PORT_DELAY_RX_PORT register is used to adjust the timestamp by the latency of the PHYs RX path This is by default set to 0 but may be corrected to also c
52. e unit needs 4 clock cycles of 125 MHz to store an event thus the maximum frequency at which the input edges can be captured is lt 31 25 MHz If multiple events happen simultaneously they are stored in the order of the GPIO pin number i e GPIO1 is stored before GPIOZ2 If a new event happens before the event is stored the old event data is lost As the input capture unit is shared for all pins this frequency applies to all enabled pins together In any case the limiting factor for edges is the speed at which the data can be read through the SMI 2tENESAS 83 7 5 1 Input Event Control Register 7 12 The Input Event Control register is used to configure the input event unit Bit Name Description Mode Default 15 ALL_PTR_RES Reset all pointers WC 0 14 Reserved ignore on read write as 0 RW 0 13 READ_WORD_NEXT 1 Reading next word when accessing Read Register 0 No impact RW 12 OVRRUN_ANY_GPIO 0 No overrun on any GPIO 1 One of the edge detection unit got a pulse before it could handle the previous one This means that the frequency of pulses on the GPIO is too high RW 11 TIMEOUT_ANY_GPIO 0 No Timeout on any GPIO 1 An edge detection unit latched an event but it could not be stored timely This means that the frequency of all GPIO events together is too high RC 10 TIMESTAMP __ ENABLE 1 Enable time stamping unit 0 Disable
53. ecctvessececeeusecoseense 92 Electrical Characteristics e ereegegieeuegiegegeeieguegedz tegerggdeg u gg 93 81 AC ERR 93 8 1 1 Serial Management Interface SMI Timing sssssusssnnunnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnna 93 8 12 Reset TIMING EE 94 81 3 Clock TIMING BE 95 8 1 4 100Base TX TIMINGS ssssnssssnnunrunnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nanne nna 96 8 1 5 IC gp lu E 98 8 1 6 RMII 10 100Base TX A lu EE 100 8 1 7 SEQUENCE FOF tv E E 102 8 2 DC e E ENEE 103 8 2 1 Absolute Maximum RattingS ccccccceesseeeeeeeneeeeeeeeeeeeseeeeeeeeseeeeeeseeeeeeeaseeeeeeseseenenseeenes 103 8 2 2 Recommended Operating Conditions ccccccssseeeessseeeeeeeeeeeeneeeeeeeeesseeeeeeeeeeeeeseeees 104 8 2 3 DC Electrical Characteristics ccccceseesseeeeeceeeeeeeesseeneeseeeeeseeesneneeeeeeseseeesneneeeees 105 8 2 4 100Base TX Differential Parameters on Secondary Side of Transformer 106 8 2 5 100Base FX Output Characteristics ccccceeeeeceeeeeeeeeeeeeeeeeeeeeeeesneeeeeeeeseeeeeeneeeeeees 106 R19UH0082ED0201 RENESAS User Manual 10 Physical dimensions 2cccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeenenes Revision history R19UH0082ED0201 User Manual 2tENESAS 11 1 1 R19UH0082ED0201 User Manual General Description The extended single channel 10 100 Ethernet PHY uPD60610 and the uPD60611 are fully integrated Physical laye
54. eceived signal which exceeded the threshold When DIAG _INIT is set to 1 initiated by HW to 000000 1111111 indicates no reflection 7 0 DIAGCNT Any value different from zero RO 0 indicates a valid measurement When no cable is present the value will be 000001 assuming threshold is set to the correct value One counter tick equals approx 0 8 m Example Before using the TDR logic it must be assured that a PHY connected to the other side of the line is not transmitting any data As typically such measurement is only done if the cable is broken there should be no link anyway but it should be assured that the link is manually put down Note that there is no reflected wave on a working link as reflections only occur at locations where the cable is broken or at the end of an open line So the TDR measurement cannot be used to measure cable length of a connected cable On the other hand a missing refection is a sign of a good cable setup There is no way to force a partner PHY to turn off its transmission so this has to be done manually at the partner PHY The typical configuration for the start is CNT_WINDOW 1 This value should in any case be slightly higher than the PW_DIAG value A value of two will filter out any pulses that return sooner than 0 8 m from the PHY DIAG_INIT 1 This will start the pulse immediately ADC_Trigger 0x5 This sets the value for the trigger level to 0 5 V PW_DIAG
55. ecide how to continue 2tENESAS 45 5 5 6 4 Register PHY 24 FEQ Monitor Control Register Bit Name Description Mode Default 24 15 0 FEQ_ DELTA Minimum change of value compared to the reference value latched when the monitor is enabled after link up which will trigger the FEQ interrupt and link down If the FEQ value differs by more than FEQ_DELTA the link goes down if the BER_CNT_LNK_EN is 1 and the BER monitor is enabled The interrupt is triggered if enabled FEEF will disable monitor and cause the reference value to be re latched continuously FFFE will not change the FEO DELTA value but read out the current reference value when FEQ_ VAL is read instead of the current value Writing any other value will disable this mode OxFFFF 24 15 0 FEQ_VAL If FEQ_DELTA 7FFF FEQ reference value Else Current FEQ2 coefficient Undefined The following picture gives an example of the value of the FEQ coefficient depending on the line length in meters R19UH0082ED0201 User Manual Decimal value of FEQ 2 ENESAS 46 The following picture gives an example of the dependency of the FEQ coefficient on the resistance of the line The 0 Ohm resistance is the value for a 1 meter line for the other values a resistor has been added to the RX line Decimal value of FEQ cable of 1 meter O 10 22 47 220 Ohm The blue circles indicate the typi
56. ected wave will not trigger the counter and DIAG_CNT is set to 0x1F A DIAG_CNT of 0x1F can have a number of causes 1 The line is properly terminated In this case there will be no reflection 2 The cable is too long for the pulse width In this case PW_DIAG and CNT_WINDOW should be increased and the measurement restarted 3 The cable is too short for the selected CNT_WINDOW or even unconnected 4 ADC_TRIGGER is set too high 2tENESAS 50 R19UH0082ED0201 User Manual The following diagram shows the typical flow when doing the TDR measurement Initial Measurement No Increase PW DIAG and reflection CNT WINDOW found PW DIAG 0x1f Repeat Measurement Set ADC_TRIGGER to ADC_MAX_VALUE 2 Repeat Measurement Read Result in DIAG_POL and DIAG_CNT ADC_MAX_VALUE lt 8 The distance to the break or short is the result in DIAG_CNT 0 8m If no reflection can be found this can have the following reasons 1 The line is properly terminated In this case there will be no reflection 2 The distance to the line break or short cable is too short lt 0 8m or the cable is completely unconnected 5 5 7 Latency The latency is the amount of time it takes for data to pass through the PHY from the line interface to the MII and also from the MII to the line interface on the TX side For industrial real time applications a short latency is very important as it has a significant influence on the
57. ed MUX in the previous chapter R19UH0082ED0201 User Manual 2tENESAS 30 4 12 Strap Options The device offers several configurations which can be selected as strap options The related I Os have resistors of approx 40 KQ as pull up or pull down integrated which configure the device as described below To change this configuration an external resistor of maximum 5 KQ must be connected to this pin An external resistor supporting the internal resistor is also advisable in case the device is used in a very noisy environment The following table shows the possible configuration options and the related pins Unless otherwise noted all configuration options apply to both PHYs Pin Name Function Default value 0 Autoneg disabled 100BaseT 1 Autoneg enabled 100BaseT If Autoneg disabled 0 Half Duplex 1 Full Duplex PORXD2 If Autoneg enabled 1 PU 0 Parallel detect ends in half duplex mode 1 Forced Full Duplex in parallel detect 0 Disable Quick Autonegotiation If Autoneg enabled 1 Quick Autonegotiation shortest times PORXCLK If Autoneg disabled 1 PU 1 Special Isolate In this mode the PHYs will not set up a link unless programmed and enabled through the SMI 0 Configure RMII Interface 1 Configure MII Interface 0 Standard Mode JK required for Start of Frame detection POTXCLK 1 PU 1 Fast Mode Only J required for Start of Frame detection Do not use in RMII Mode 0 AUTOMDI X disabled
58. eeeeeseeeeeeseeeeeeeseeneeeesseeeeenseeneeenss 55 5 6 4 Register PHY 3 PHY Identifier cccccceesseeeeeeeeeeeeeeeeeeeeeseeeeeeeseeeeeeeseeeeeeesseeeeenseneeeenss 55 5 6 5 Register PHY A Auto Negotiation Advertisement cccccscccessseeeesseneeeesseneeeesseeeenes 56 5 6 6 Register PHY 5 Auto Negotiation Link Partner Ability Base Page c ssseee 57 5 6 7 Register PHY 5 Auto Negotiation Link Partner Ability Next Page ccsssseee 58 5 6 8 Register PHY 6 Auto Negotiation Expansion cccccscccesseeceesseneeeeseeneensseneeenseeeeenes 58 5 6 9 Register PHY 7 Auto Negotiation Next Page Transmit cccscccessseeeesseeeeeeeeereeeees 59 5 6 10 Register PHY 16 Silicon REVISION cseseeeceseseeeceseeeeeenseeneesnseeneeenseeneesnseeneeenneseenes 59 5 6 11 Register PHY 17 Mode Control Status cc cssescseseeeeeseseeeeeseeeesnseeneeseseeenenseenenes 60 5 6 12 Register PHY 18 Special Modes cccccsesseceseeeeeeeseeeeeeeseeeeeeeseseeesnseeneeenseeneeeneeeneees 61 5 6 13 Register PHY 19 Elastic Buffer Status register Loopback Mode onlly 61 5 6 14 Register PHY 20 Reserved cccciecccesecceceessnceceeescteceenseecresessterequsoeceersestecereseaeeaeeseeese 62 5 6 15 Register PHY 21 Reserved cceeccsesseeceseeeeeeeseeneeeeseeneeseseeeeeeesesneesesesneeensesneeenaeenaees 62 5 6 16 Register PHY 22 Reserved TSTREAD2 TSTWRT cssccssseeeeseeeseseeesseeeeeeeee
59. eeeeseeeeeeesseeeeseeseeeeenss 34 5 4 5 SB 4B Encoding DeCoding cescccceesenceeeeeeeeeeeeeeneeeeeeenseeeeeeneeeeseeneeeeseeneeeeseseeeeesseneeenss 34 5 5 Functional Dee 36 5 5 1 Collision detection secccivccsceniecccccsenecececrtesetenteectceeteecetsstnectoestnesecteteectonstnesctaernestoscreesedeereest 36 5 5 2 Carrier Sense detection ssssnsssennnnrnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn na 36 5 5 3 Auto Crossover MDI MDI X ssssnussnununnnnnnnnnnnnnnnnnnnnnnnnnnunnnnnnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnn na 36 5 54 AUto Polamitl E decetecsctecene ceceteesetecene dosed aesededenecdaseiavsttedene doceteesedederest 37 5 5 5 Autochegottatton cicccecccccceecccccneectccersectcceneecttceneecttcaneeetctaneectecernestiteneescecereestiuareectecereess 37 5 5 6 Bad Line recognition cc c2ccc ccsccecceecteccteecttecenecdcceteesttecenectenetnestcuseeecdeceneesttecenectocereestteceeesd 43 S57 EATON E 51 5 5 8 apen late is cas sasacssten ceccsxavsanaves dee eegene 52 5 6 PHY ROGUSCG FES crac c cc scccc ccc tecccccetcscccectectecccicctececteeceebenccseneebactuceaneesecesbecceecei lt 53 5 6 1 Register PHY D Basic Control ccccesccceeseeeeeeeeeeeeeeeeeeeeeseeeeeeeseeneeenseeeeeenseeneeensseeeeenss 53 5 6 2 Register PHY 1 Basic Control cccccscceeesseeeeeeeeeeeeeeeeneeeeseeneeeeseeeseeeseeneeeesseneeensseeeeenss 54 5 6 3 Register PHY 2 PHY Identifier cccccessseeeeeeeeeeeeeenee
60. enees 62 5 6 17 Register PHY 23 BER Counter eceecesesseeceseseeeeeseeneeseseeneeenseeneesesesneeenseeneesnsesneees 63 5 6 18 Register PHY 24 FEQ monitor Register csceccseseeceseseeeeeeeeeeeseseeneeeeeeeeeeneeenenen 64 5 6 19 Register PHY 25 Diagnosis Control Status Register ccccssseseeeeeeeeeeeeseeees 65 5 6 20 Register PHY 26 Diagnosis Counter Register cccsesseecseseeeeeseeeeeeeseseenenseeeees 66 5 6 21 Register PHY 27 Special Control Status Indications cccseecssseeeseseeeeseeeeees 66 5 6 22 Register PHY 28 Reserved WE 67 5 6 23 Register PHY 29 Interrupt Source FIAQGS ccseecceseseeeeeeeeeeeeeeeeneesesesneeseeeeneneneeeenes 67 5 6 24 Register PHY 30 Interrupt Enable cccceccesesseeceseeeeeeeeesneeseeeeneeseseseeeenseseeeeneesneees 67 5 6 25 Register PHY 31 PHY Special Control Status 0 cccccsesseeeseseeeeeseeeeeeeseeeeennesenes 68 External Components ccececeseeseeeeeeeeeeeeeeeeenaaeeeeensees 69 6 1 COG E 69 6 2 Internal Regulator secccccc ec cccccccc sete cc cctstcccescnteccesesteececeeteececesteccesesteeceseeteecescsbieees 69 6 3 Power Up E UE 69 Support of IEEE1588 UPD60611 ont 70 n ll aad E gt gt eee rere ere nee eee rete Perr rr rere etter Pere ert pr errr rr Pree Pern enrer ree Pere rrr eres rrreeer sper ry 70 R19UH0082ED0201 RENESAS User Manual 7 2 Register access to PUP wvcceccscecevececece ccc e SSES SEENEN EES 71 7 3 1
61. er supply Output Current POLINKLED GPIOOPOACTL 21 mA ED GPIO1 P1LINKLED GPIO2 P1ACTLED GPIO3 PO100BTLED GPIO4 P1100BTLED GPIO5 POTXERR GPIO9 POTXD3 GPIO10 POTXD2 GPIO11 P OTXCLK P1TXERR GPIO15 P1TXD3 GPIO16 P1TXD2 GPIO17 P1TXCLK MDIOOT XD1 Output Current POCRS POCRS_DV GPIO6 11 mA PORXD3 GPIO7 PORXD2 GPIO8 PORXD1 P ORXDO PORXCLK PORXERR PORXDV P1CRS P1CRS_DV GPIO12 P1RX D3 GPI013 P1RXD2 GPIO1 4 P1RXD1 P1RXDO0 P1RXC LK P1RXERR P1RXDV PO COL GPIO18 P1COL GPIO 19 Storage Tstg 65 to 150 C temperature 2tENESAS User Manual 8 2 2 Recommended Operating Conditions Parameter Symbol Conditions Rating Units Analogue power POVDDMEDIA 1 425 to V supply voltage VDDAPLL 1 575 Digital Power Supply VDD15 1 425 to V Voltage 1 575 I O Voltage VDDIO 2 25 to 2 75 V 3 0 to 3 6 Analog 3 3V power VDDACB V supply 3 0 to 3 6 Analog 3 3V power REGAVDD V 0 to 3 supply REGBVDD 3 0 to 3 6 Analog 3 3V power VDD33ESD V supply 3 0 to 3 6 Output Current GPIOO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO9 GPIO10 GPIO11 GPI015 GPIO16 GPI017 6 mA MDIO POTXCLK POTXEN POTXD1 POTXDO Output Current GPIO6 GPIO7 GPIO8 GP1012 GP1I013 GP1014 MDC PORXCLK 3 mA PORXERR PORXDV PORXD1 PORXDO Value for EXTRES EXTRES 12 441 kQ Operating ambient Ta C temperature eau tee R19UH0082ED0201 User Manual RENESAS 104 8 2 3 DC Electrical Characteristics
62. eserved Ignore on read write as 0 RW 0 29 0 DELTA_VAL Delta in fractions of ns by RW 0 which the increment value is corrected So bit 29 represents Ye ns bit 28 1 4 ns bit 27 1 8 ns etc ZA Frame Handling Unit The following picture shows the block diagram for the frame handling unit The incoming frame is time stamped as it arrives and the timestamp is then stored together with other frame related information in the timestamp SRAM When a frame is sent it is time stamped and the timestamp is stored together with the frame related information in the SRAM This data enables software to handle two step PTP When an event happens either due to transmission or reception of a PTP message an interrupt can be generated R19UH0082ED0201 AS User Manual RENES 74 MAC lt J Message type Correction field SourcePortID SequencelD Timestamp CRC Le PHY Transparent Clock Incoming frame y Switch Mode Timer P incoming Timestamp Latch Lower 34 Bits Timestamp SRAM Timestamp MACID SourcelD SequencelD veryy yyy lt a Controlbus1 to SMI Transparent Clock Switch Mode Lower 34 Bits Outgoing Timestamp Latch In onestep replace old timestamp Le Timer on the fly I MAC gt Message type Correction field SourcePortID SequencelD imestamp CRC gt PHY Outgoing frame with basic co
63. essed PHY The device uses the PHY addresses to support access to the PTP block and the Global Configuration registers The address table is as follows PHY Address Binary Ressource Comments NMO00 PHYO NMOO1 Reserved NMO010 Reserved NMO11 Reserved NM100 Reserved NM101 Reserved NM110 PTP LOBAL NFI NM111 n The values of the bits N and M can be configured as a strap option R19UH0082ED0201 2tENESAS User Manual 18 4 2 General SMI Control Register 7 31 The following register is used for configuration of the SMI Bit Name Description Mode Reset 1 Initiates a software reset of the complete device stays active until 15 SOFTRESET cleared by software Ww 0 0 Release Reset 14 SMI_SHORT 1 Enable short preamble support RW 0 _PREAMBLE 0 Short Preamble mode for SMI interface not enabled 13 RESET WC 0 12 4 Reserved Write as 0 RW 0 3 Reserved Write as 0 RW 0 2 Reserved Write as 0 RW 0 1 Reserved Write as 0 RW 0 PHYO 1 PHY 0 ignores the PHY address ice is bei itt 0 DISREGARD when the device is being written RW 0 ADDRESS 0 The PHY checks for the PHY Z address 4 3 Power Control Register 7 30 The following register is used for configuration of the power options Bit Name Description Lan Reset 15 14 Reserved RW 13 12 Reserved RW 11 STOP 1 Device is completely disabled RW 0 only access to registers 7 2
64. ext pages This core supports the optional next page function Next page exchange occurs after the base page has been exchanged Next page exchange consists of using the normal auto negotiation arbitration process to send next page messages Two message encodings are defined Message pages which contain predefined 11 bit codes and unformatted pages Next page transmission ends when both ends of a link segment set their next page bits to logic zero indicating that neither has anything additional to transmit It is possible for one device to have more pages to transmit than the other device Once a device has completed transmission of its next page information it shall transmit message pages with null message codes and the NP bit set to logic zero while its link partner continues to transmit valid next pages Auto negotiation capable devices shall recognize reception of message pages with null message codes as the end of its link partner s next page information The default value of the next page support is disable bit 15 of register 4 To enable next page support bit 15 of Register 4 should be set to 1 Auto negotiation should be restarted and the message code should be written to bit 10 0 of register 7 R19UH0082ED0201 AS User Manual RENES 41 5 5 5 5 Re negotiation When auto negotiation is enabled it is re started by one of the following events 1 Link status is down 2 Setting Auto Negotiation Restart bit to hig
65. featuring adaptive equalization and baseline wander correction e IEEE 802 3u auto negotiation and parallel detection e Full and half duplex operation e Supports automatic polarity detection and correction e Supports automatic MDI MDI X crossover e Supports IEEE1588 V1 and V2 uPD60611 only e Highly configurable I O configuration uPD60611 only e 2 5V and 3 3V MAC interface e Flexible MAC interface MII and RMII e Serial management port MDC MDIO 2tENESAS B D Supports user programmable interrupts e Enables software power up down and automatic power up down by energy detection e Single 3 3 V power supply with optional separated 1 5V e Operating temperature T ambient 40 to 85 C Tjunction from 40 to 125 C 1 2 Special product features e Low latency and low jitter for industrial networking D Fast link up option in auto negotiation e Fast link loss detection e Cable monitoring and error detection e Permanent cable quality tracking e Enhanced system testability such as bypass loopback and cable length measurement by TDR e 1 ns resolution timer for hardware support of IEEE1588 uPD60611 only e Timestamping function to timestamp incoming and outgoing telegrams and pin activity uPD60611 only e Output pins controllable by internal PTP clock uPD60611 only 1 3 Applications H Industrial networking such as Profinet Ethernet IP ClPsync ModbusTCP EtherCAT and Sercosilll H 10 100 Mbps LAN on motherbo
66. h Auto negotiation is started not re started when 1 H W reset 2 S W reset or 3 setting Auto Negotiation Enable from low to high 5 5 5 6 Parallel Detection The parallel detection function allows detection of link partners that support 100BASE TX and or 10BASE T but do not support auto negotiation or are set to fix mode The core is able to determine the speed of the link based on either 100M MLT 3 symbols or 10M Link Pulses If the core detects either mode it automatically reverts to the corresponding operating mode In this case the link is always half duplex as defined in the IEEE spec If a link is formed via parallel detection then reg 6 0 is cleared to indicate that the link partner is not capable of auto negotiation The controller has access to this information via the management interface If a fault occurs during parallel detection reg 6 4 is set reg 5 is used to store the link partner ability information which is coded in the received FLPs If the link partner is not auto negotiation capable then reg 5 is updated after completion of parallel detection to reflect the speed capability of the link partner Similar to the auto negotiation process the PHY waits for the Break_Link_Timer duration before starting parallel detection After reception of the first link signals the parallel detection process waits for another 500 ms to check if FLP bursts are received 5 5 5 7 Parallel Detection gt Speculative Full Duplex In
67. he updated value can be read after writing the PULSE_CHANNEL value Do not set the PULSE_STARTTIME to a value in the past This register has to be accessed five times with the most significant word first Word Name Description Mode Default 79 0 INITIAL_PULSE_ Initial start time for pulse WO 0 STARTTIME 79 32 Seconds 31 0 _Nanoseconds 2tENESAS 91 7 6 3 PULSE_WIDTH Register 7 18 This register has to be accessed three times in a row with the most significant word first Bit Name Description Mode Default 47 38 Reserved Write as 0 RW 0 34 5 PULSE_ Pulse high width nanoseconds RW 0 WIDTH_NS for single and continuous pulse The shortest pulse width value is 24 ns 4 0 PULSE_ Pulse high width fractions of RW 0 WIDTH_FNS nanoseconds for single and continuous pulse The shortest pulse width value is 24 ns 7 6 4 PULSE_INTERVAL Register 7 19 This register has to be accessed three times in a row with the most significant word first Bit Name Description Mode Default 47 35 Reserved Write as 0 WO 0 34 5 PULSE INTERVAL_NS Pulse interval nanoseconds after which the next pulse is generated only for continuous pulse The maximum value is 999 999 999ns or hex3B9AC9FF The shortest pulse interval value is 24 ns WO 0 4 0 PULSE INTERVAL_FNS Pulse interval fractions of nanoseconds after whi
68. iation strap setting RO Strap option 13 AUTO_MDIX Auto MDIX strap setting RO Strap option 12 FAST_JK Fast JK strap setting RO Strap option 11 DUPLEX Duplex strap setting RO Strap option 10 ADDR4 PHY address bit 4 strap setting RO Strap option 9 ADDR3 PHY address bit 3 strap setting RO Strap option 8 ETHERCAT MII timing strap setting RO Strap option 7 MII MII RMII strap setting RO Strap option 6 2 Reserved Reserved RO 0 1 PHY1 TX 100BASE TX 100BASE FX strap RO Strap setting for PHY1 option 0 PHYO TX 100BASE TX 100BASE FX strap RO Strap setting for PHYO option R19UH0082ED0201 User Manual 2tENESAS 20 4 6 PHY LED Status Register 7 24 The following register shows the status of the PHYs after power up To read the LED status for the PHYs first PHY SELECT must be written with the number of the required PHY and then the data for this PHY can be read from the register The ACTIVE_LED_BLINK bit can be used to control the LED outputs of the device If a GPIO is configured for link detection setting this register will cause the GPIO to blink while data transmission is ongoing Bit Name Description Mod e Reset 15 Reserved Write as 0 R 0 14 POSD Signal Detect signal is active R 0 13 PHY_TXACT 1 PHY had TX activity since last reading 0 PHY had no TX activity since last reading Cleared when read R LH 0 12 PHY_RXACT 1 PHY had RX activity since last
69. if buffer overruns oldest timestamp is lost RW 6 4 TIMESTAMP __ SELECT Address at which timestamp buffer is read for the following access to the TIMESTAMP_LINE_EVENT WORD register 001 Next read will get TX timestamp 000 Next read will get RX timestamp Others Undefined RW 3 1 Reserved ignore on read write as 0 RW TS_EN_PHYO 1 Enable timestamping for PHYO depending on setting in PTP_CONFIG_REGISTER 0 Disable timestamping for PHYO RW 2tENESAS 77 R19UH0082ED0201 User Manual 7 4 5 TIMESTAMP_LINE_EVENT Register 6 8 The TIMESTAMP_LINE_EVENT register gives access to the timestamp memory which stores the time stamps generated by the framer logic when a PTP frame was transmitted or received It stores transmit or receive timestamps separately for TX and RX frames The TIMESTAMP_SELECT bits in the TIMESTAMP_CONGIGURATION register define if the TX or the RX buffer is accessed The timestamp memory can hold up to four timestamps for RX and four timestamps for TX A read will always retrieve the oldest valid dataset A timestamp set is combined of the timestamp itself the source port identity and the sequence ID stored in a 192 bit wide register This is organized as shown below Bit Name Description Mode Default 191 176 MESSAGE_ID Message Type of the received message 001 PTP Sync message 010 PDelayReq message 011 PDel
70. imestamp on both edges RW 1 0 IN_CAP_GPIO8 00 Disable event timestamping for GPIO8 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges RW The Input Capture Pin Control register is used to enable timestamping GPIO 16 7 5 4 Input Capture Pin Control register 7 10 to 21 and is used to configure the edge on which it should trigger Bit Name Description Mode Default 15 14 Reserved Write as 0 RW 0 13 12 Reserved Write as 0 RW 0 11 10 Reserved Write as 0 RW 0 9 8 Reserved Write as 0 RW 0 7 6 IN_CAP_GPIO19 00 Disable event timestamping RW 0 for GPIO19 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges 5 4 Reserved Write as 0 RW 0 3 Reserved Write as 0 RW 0 1 0 Reserved Write as 0 RW 0 R19UH0082ED0201 RENESAS User Manual 86 R19UH0082ED0201 User Manual 7 5 5 INPUT_EVENT_DATA_READ_WORD Register 7 15 The INPUT_EVENT_DATA_READ _WORD register gives access to the stored timestamps To read the complete timestamp the register has to be accessed six times The least significant word is read first The location of the data is as follows Bit Name Description Mode 95 16 TIMESTAMP Timestamp of the related event described in bits 15 0 RO 15 14 BUFFER _ STATUS 00 Timestamp buffer is empty 01 Next timestamp is available RO
71. ing reception 5 5 3 Auto Crossover MDI MDI X The core automatically detects and corrects for the MDI MDI X crossover in the TX modes Auto Crossover is disabled in FX Mode If this function is disabled crossover may be corrected manually through the Serial management interface The status of the crossover function can be read in the status register The detection process is started whenever the PHY is turned on and Auto Crossover is activated As soon as the partner PHY is transmitting it will immediately do the adjustment 5 5 3 1 Auto Crossover when using 100BT Fix Mode In 100BT manual mode the transmitter transmits continuously idles on the TX line As the incoming echo from the transmitter path needs to be blocked there is no chance to listen on that line Therefore a special non standard implementation is done called 100BT idle burst mode The idle burst mode has two states a period of idle burst and a period of random silence mode to detect incoming signals on the TX line The time for the next transmission will be picked randomly The decision to do a switchover will be done based on the reception of two signals within a specific time period The PHY will transmit bursts of 1 us after a waiting time of 0 63 us In parallel it checks on both lines if a signal can be received If a valid signal is received on the RX line it will continue normal operation If a valid signal is received on the TX line it will wait for 500us and then
72. ink Activity and Half Duplex mode Active Low refers to LINKA MUX_LINKA Pin is shared for two LED signaling Link Activity and 400BT 100BT mode Active Low refers to LINKA MUX_LINKA Pin is shared for two LED signaling Link Activity and 10BT 10BT mode Active Low refers to LINKA SD Signal Detect Only used in FX mode 2tENESAS 28 R19UH0082ED0201 User Manual The setting in the LEDMODE register 24 7 4 configures the drivers for LEDO LED3 Mode LED Data input Comment output 0 LEDO LinkA Link with activity blink option depending on setting of ACTIVE_LED_ BLINK register LED1 FD LED2 MUX 100BT 10BT Active Low refers to 100BT LED3 Activity 0001 LEDO MUX LinkA FD Mux frequency gt gt blink frequency LED1 SD LED2 MUX 100BT 10BT Active Low refers to 100BT LED3 Activity 0010 LEDO MUX LinkA HD Mux frequency gt gt blink frequency LED1 SD LED2 MUX 100BT 10BT Active Low refers to 100BT LED3 Activity 0011 LEDO Mux LinkA 100BT Mux frequency gt gt blink frequency LED1 MUX 100BT FD Active Low refers to 100BT LED2 MUX ActTX ActRX Activity from PHY 128ms LED3 SD 0100 LEDO Mux LinkA 10 BT Mux frequency gt gt blink frequency Active Low refers to 100BT LED1 FD LED2 SD LED3 HD 0101 LEDO MUX LinkA SD Active Low refers to LinkA LED1 MUX 100BT 10BT Active Low refers to 100BT LED2 Activity L
73. internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable
74. ions equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use condi
75. me it is measured for the PTP telegrams Based on the master clock time value and the travel time of the telegram the slave clocks can be adjusted and synchronized To measure the travel time timestamps can be taken when telegrams leave the PHY or are received by the PHY The more precise these timestamps can be taken the more precise the calculation of the travel time and the better the synchronization of the clocks that can be achieved For the transmit telegrams the data is always sent at the clock edge of the 125 MHz clock and therefore the timestamping logic which is running at the same clock as the transmit logic has an optimum accuracy However receive telegrams can arrive at any time within the 125MHz 8ns clock period so the receive timestamping logic always has an error of up to 8ns depending on the actual arrival time of the data within the clock period To optimize the reception of the incoming data the receive DSP continuously shifts the time at which the data is sampled to the optimal time This is done by using one of 8 phases of the 125MHz clock coming out of the PLL Thus the selected phase of the PLL is a precise indicator for the exact sampling time at which the incoming data arrived at the PHY As each of these phases represents a 1ns timeslot it can be used to define the exact arrival time within the 8ns clock period This data is also stored together with the timestamp 2tENESAS ge 7 2 7 3 R19UH0082ED0201 User Manual
76. modern Ethernet systems it is not very likely that a 100 MBit fix mode PHY is actually using half duplex However if the IEEE 802 3 is fulfilled the PHY doing auto negotiation will revert to half duplex operation following the parallel detect operation Thus the result of the parallel detect mode may be one Fix mode configured PHY running at 100 MBit full duplex and the other Autonegotiation configured PHY running at 100 MBit half duplex Although communication is possible this will lead to a very high number of errors as the half duplex configured PHY will continuously detect collisions and interrupt its transmission when the full duplex PHY is transmitting and receiving simultaneously To avoid this situation the PHY can be configured to go into full duplex instead of half duplex in parallel detection mode by means of a strap option R19UH0082ED0201 AS User Manual RENES 42 5 5 6 Bad Line recognition The PHY features a number of functions to control and observe the line to be able to ensure a reliable connection 5 5 6 1 BER Monitor R19UH0082ED0201 User Manual The PHY can continuously measure the bit error rate BER on the line and trigger an interrupt or put the link down if a configurable threshold is reached Bit errors are detected by checking the received symbols against the list of allowed symbols There are two basic conditions for this check 1 IDLE situation When the PHY is in idle mode it should only receive IDLE symbol
77. n the other This handling can be enabled separately for each PHY and for transmit and receive The Transparent Clock function can only be used in one step mode In two step mode the Transparent Clock function is not required but can be handled by using one of the Ordinary Clock modes for time stamping and handling the protocol in software based on the FollowUp telegrams R19UHO0082ED0201 2tENESAS User Manual 75 R19UHO0082ED0201 7 4 2 1 End to End Transparent Clock For End to End Transparent clock the time a synch telegram takes to pass through the node is measured and either stored in the correction field of the telegram or the correction field of the FollowUp telegram The correction field at the slave then contains the time that the telegram spend in the different switches etc which act as a transparent clock The PTP stack can use this value to calculate the raw line delay and eliminate the jitter that comes from the varying residence times in the switches 7 4 2 2 Peer to Peer Transparent Clock For peer to peer transparent clock each node measures the delay to all surrounding nodes using the PdelayReq and Pdelay_Resp mechanism Thus all line delays in a network are known Each node through which a Synch message passes adds the own residence time plus the line delay of the incoming link to the correction field When this synch telegram arrives at the slave node it contains the complete line delay plus the residence times in its cor
78. negotiation protocol is a purely Physical layer activity and proceeds independently of the MAC controller Prior to the start of any kind of negotiation the PHY is required by the IEEE 802 3 Chapter 28 to wait the Break_Link_Timer time which is defined to be between 1200 ms and 1500 ms This time is defined to make sure both PHYs are reset and reach a defined status prior to starting the negotiation process For the auto negotiation function the two PHY communicate by sending FLP Fast link Pulse bursts for exchanging information with its link partner A FLP burst consists of 33 pulse positions The 17 odd numbered pulse positions contain a link pulse and represent clock information The 16 even numbered 2tENESAS Se pulse positions represent data information The data transmitted by an FLP burst is known as a Link Code Word These are fully defined in clause 28 of the IEEE 802 3 specification After the Break Link Timer has expired the link down status is achieved and if auto negotiation is enabled the PHY starts to send FLP bursts while trying to receive signals on its receive path If it detects signals according to 10BaseT 100BaseTX or 100BaseT standard it will wait for FLP bursts and check the received signals until the autoneg_wait_timer period of typically 5 00ms has expired and then switch to fix mode according to the received signal The following picture shows the FLP burst max 33 pulses _ 2m 16ms 8ms
79. ng or by setting the appropriate strap pins When auto negotiation is disabled the speed and duplex modes are decided by setting management interface registers or Parallel Detection 5 5 5 3 Priority Resolution There are four possible matches of the technology abilities In the order of priority these are 100M full duplex highest priority 100M half duplex 10M full duplex 10M half duplex Since two devices local device and remote device may have multiple abilities in common a prioritization scheme exists to ensure that the highest common denominator ability is chosen Full duplex solutions are always higher in priority than their half duplex counterparts 10BASE T is the lowest common denominator and therefore has the lowest priority If a link is formed via parallel detection then bit O in Register PHY 6 is cleared to indicate that the link partner is not capable of auto negotiation The controller has access to this information via the management interface If a fault occurs during parallel detection bit 4 of register PHY 6 is set Register PHY 5 is used to store the link partner ability information which is coded in the received FLPs If the link partner is not auto negotiation capable then register PHY 5 is updated after completion of parallel detection to reflect the speed capability of the link partner 5 5 5 4 Next Page Function Additional information exceeding that required by base page exchange is also sent via n
80. nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 23 SSC BE E EEA E E 24 4 9 1 GPIO_CONFIG_0 Register 78 24 4 9 2 GPIO_CONFIG_1 Register 71 25 4 9 3 lt GPIO CONFIG 2 Register 7 2 sissiessiisinsessarsenescecansssunstncasoetuaasnssnuentdannsnpacnantecbdianeeaneyiiann 26 4 9 4 GPIO_CONFIG_3 Register 7 3 sisc sstssassnctcacesassnntaashsacasunacecdapaicannesacastaniasasnanabisatanaaaianins 26 4 9 5 GPIO_CONFIG_4 Register 7 4 cs ss cecsssesseceseeesseceeceeeesnencescenesnesnonnaeeeenessonsaeoeens 27 410 LED c onfig rati nN E 28 SI LCEDMUX Qe Ee 30 412 Strap Options isisisi aa aa aa a aa ida a 31 PHN E 32 5 1 General Heer 32 5 2 Clock Generator E E 33 5 3 Analogue de WE 33 5 3 1 Adaptive Equalizing wii cciceccssnsnceacencreacvnnsnsnensentedshnnancenrsecttanynnmnceantnaned ss ensdanantncnkadencbangntnia 33 5 3 2 100Base TX Receiver ADC iiscicciccccscsscsctse ccccentsscentesetensesanstintceecesvensascentesescevenaantenttanseds 33 5 4 Digital Signal Handling useskCERkEEKESEKRGEKEEEKAEEKEEEKAEEKEEEKEERKEEEKREEKEEEKREEKEEEAEREKEEEKREE 33 BM WE 33 5 4 2 Baseline Wander Correction cc seeceeceeeeeeeeeeeeeee cece eeeeeseneeeeeeeeseeeseaneneeseeeseseeeeneesenees 33 R19UH0082ED0201 RENESAS User Manual 5 4 3 NRZI MLT 3 Encoding DeCOding cccccessseeeeeeeeeeeeeeeeeeeeseeneeeeseeneeenseeneeenseeeeeensenneeenss 34 5 4 4 Scrambler DeScramble e cccccccssececeeseneeeeseeeeeeeeeeeeeeeeeeeeeeseeeeeesseee
81. ntents 7 4 1 One step mode For one step PTP the timestamp is stored in the outgoing timestamp latch and is on the fly integrated in the timestamp field of the frame The CRC is corrected accordingly Note that for one step clock the latency is increased as the insertion of the time stamp in the frame requires some processing of the frame 7 4 2 Transparent Mode Transparent Clock is used to improve the accuracy of the time synchronization in long networks by eliminating the uncertainty it takes for synch frames to pass through switches Depending on the load of the switch the residence time of a synch telegram in the switch varies By measuring the time a synch frame stays in the switch and writing this value into the frame the accuracy is greatly improved as the slave clock can use this value to adjust its calculation of the master clock value To support Transparent Clock mode in hardware the PHY modifies the respective telegrams When a PTP synch telegram is received in transparent clock mode the lower 2 sec 32 ns bits of the timestamp value taken at reception are converted to ns and subtracted from the correction field When a PTP telegram is sent the transmit timestamp lower 2 sec 32 ns bits are converted to ns and added to the correction field Thus the correction field is incremented by the difference between transmit and reception and the correction field correctly updated even if a telegram is received on one PHY and transmitted o
82. nual Update etc Ethernet PHY Operating Precautions Abbreviation Full Form Register p n Register n at PHY address p Register p n b Bit b in register address n at PHY address p Register PHY n PHY stands for PHY address 0 or 1 so this would mean register n in any of the two PHYs can by PHY address 0 or PHY address 1 Abbreviation Full Form RW Readable or writeable SC Self Clearing RO Read Only W Write Only LH Latch High when the device sets the register it stays high until actively written to 0 even if the condition that set it disappears LL Latch Low the register stays low until actively written to 1 NASR Not affected by software reset WC Cleared by hardware after writing RC Cleared after reading by hardware 2tENESAS List of Abbreviations and Acronyms R19UH0082ED0201 User Manual Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter Autoneg Autonegotiation bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller FD Full Duplex Mode HD Half Duplex mode Hi Z High Impedance IEBus Inter Equipment Bus 1 0 Input Output LSB Least Significant Bit MSB Most Significant Bit NC Non Connect PLL Phase Locked Loop PU Pull Up PD Pull Down PWM Pulse Width Modula
83. o 10Mbps with full duplex DUPLEX ability 5 10BASE T 1 10Mbps able RW 1 0 no 10Mbps ability 4 0 SELECTOR 00001 IEEE Std 802 3 RW 00001 FIELD 2tENESAS 56 5 6 6 Register PHY 5 Auto Negotiation Link Partner Ability Base Page Bit Name Description Mode Default 15 NEXT PAGE 1 additional next page will RO 0 follow 0 last page 14 ACKNOWLEDGE 1 successfully received link RO 0 partner s link code word 0 not successfully received link partner s link code word 13 REMOTE FAULT 1 remote fault condition RO 0 0 no remote fault condition 12 11 RESERVED Ignore on read RO 0 10 PAUSE 1 pause operation is supported RO 0 OPERATION by remote MAC 0 pause operation is not supported by remote MAC 9 100BASE T4 1 100BASE T4 able RO 0 0 no 100BASE T4 ability 8 100BASE TX 1 100BASE TX with full duplex RO 0 FULL 0 no 100BASE TX full duplex DUPLEX ability 7 100BASE TX 1 100BASE TX able RO 0 0 no 100BASE TX ability 6 10BASE T FULL 1 10Mbps with full duplex RO 0 DUPLEX 0 no 10Mbps with full duplex ability 5 10BASE T 1 10Mbps able RO 0 0 no 10Mbps ability 4 0 SELECTOR 00001 IEEE Std 802 3 RO 00001 FIELD R19UH0082ED0201 RENESAS User Manual 5 6 7 Register PHY 5 Auto Negotiation Link Partner Ability Next Page Bit Name Descri
84. o cable is present the value will be 000001 assuming threshold is set to the correct value One counter tick equals approx 0 8 m RO 5 6 21 Register PHY 27 Special Control Status Indications Bit Name Description Mode Default 15 13 Reserved Write as O00 Ignore on read RW 0 12 SWRST_FAST SW reset counter testing 1 accelerates SW reset counter from 256us to 10 us for production testing RW 0 11 SQEOFF Disable the SQE test Heartbeat 1 SQE test is disabled 0 SQE test is enabled Set 1 when repeater mode RW NASR 10 6 Reserved Write as 0 ignore on read RW FEFIEN Far End fault indication enable 1 FEFI generation and detection are enabled This is the reset value if FXMODE is enabled by strap option 0 FEFI generation and detection are disabled RW Strap option XPOL Polarity state of the 1OBASE T 1 Reversed polarity 0 normal polarity RO 3 0 Reserved Ignore on read RO 1011 2tENESAS 66 R19UHO0082ED0201 User Manual 5 6 22 Register PHY 28 Reserved Do not write or read this register 5 6 23 Register PHY 29 Interrupt Source Flags Bit Name Description Mode Default 15 11 Reserved Ignore on Read 0 10 INT10 BER counter trigger RC 0
85. ompensate for delays caused by the transformer Typically this value should be 190 if Fast JK mode is used otherwise 230 Bit Name Description Mode Default 15 0 PHY_DELAY_ Value inns by which RW 0 RX_PORT timestamps taken for the PHY on the RX side are corrected 2tENESAS 82 7 5 Input Capture Unit R19UH0082ED0201 User Manual The input capture unit can be used to timestamp events on any of the GPIO pins The timestamps are stored in a special memory area which can be accessed through the SMI through dedicated registers The memory is configured as a FIFO structure timestamps are written in consecutive addresses To read out certain addresses can be selected Up to 64 timestamps can be stored Each GPIO has its own edge detection unit which can be configured to react on rising edge falling edge or both If an event happens the value of the timer is latched locally Each pin has its own counter to count the events that have happened The value of this counter is stored as rolling number together with the timestamp Thus it can be easily checked if an event has been missed if the rolling number value has gaps when the timestamp is read The input capture unit also stores the GPIO number at which the event occurred and the edge that triggered the event together with the timestamp data Each detection unit can store up to one event which needs to be stored before the next event occurs The input captur
86. on Mode Default 15 Reserved Write with 0 ignore on read RW 14 DIAG_INIT When set to 1 create one RW 0 cycle pulse init TDR test self cleared 13 8 ADC_MAX_ Shows the signed R VALUE maximum minimum value of the reflected wave After the TDR process has been started the PHY will send out a trigger pulse and wait for the reflected wave for 255 clock cycles of 8 ns After the time has elapsed the DIAG_DONE bit is set The ADC MAX_VALUE will indicate the maximum of the received wave if positive or the minimum if negative 13 8 ADC_Trigger Threshold for pulse detection W Oxf correlates to 1 5V 0 to OV MSB should always be 0 7 DIAG_DONE Indicate that the counter has R 0 been stopped either by counter overrun or by a ADC trigger Cleared after reading 6 DIAG_POL 0 Counter stopped by positive R 0 trigger level 1 Counter stopped by negative trigger level 5 DIAG_SEL_LINE 1 perform diagnosis on TX line RW 0 0 perform diagnosis on RX line 4 0 PW_DIAG Pulse width for Diagnosis RW 0 0 Diagnosis turned off Other Pulse width value 8ns R19UH0082ED0201 AS User Manual RENES R19UH0082ED0201 User Manual Bit Name Description Mode Default Minimum time after which the counter stops Used to filter out any pulses or reflections generated from the local connector or similar sources One tick equals approx 0 8m 15 8 CNT_WINDOW RW 0 Indicates the location of the r
87. on as three bit errors are detected this has no bad influence on the detection time for a line failure So in this case the value for the BER_ COUNTER_CONTROL register is 0x4700 This can be done at any time In addition Interrupt 10 in the Interrupt Mask register should be enabled to notify the CPU of such an event 5 5 6 3 FEQ Monitor R19UH0082ED0201 User Manual In order to optimize the reception of the incoming data the DSP continuously adapts its filters to the incoming signal To be able to monitor the line quality one of the DSP filter coefficients can be monitored and an interrupt or link down can be triggered if programmable limits are exceeded The FEQ2 coefficient changes as the DSP tries to readapt to match a changed line characteristic caused for example by a line break or increased resistance due to corrosion This change is done within 1 to 9us when the line condition changes depending on line length and cable quality So by using the FEQ monitor line changes can be safely detected within 9 us The FEQ2 value is latched at link up time By programming the FEQ2_DELTA field in register 24 the allowed deviation of this value can be set Whenever the FEQ2 is outside of this border due to changes in line condition an interrupt or link down is initiated Note that after a link down the FEQ2 value is relatched so then a link is established based on the then actual FEQ2 value In this case the application needs to take control and d
88. ond uPD60611 only 0010 Fixed 0 0011 GPIO is Output for PTP OUT1 Output of Pulse Out unit 1 uPD60611 only 0100 GPIO is Output for PTP OUT2 Output of Pulse Out unit 2 uPD60611 only 0101 GPIO is Output for PTP OUTO Output of Pulse Out unit 0 uPD60611 only uUPD60611 only 0110 GPIO is Output for PTP packet received on PHY 0 If PTP is disabled on this PHY the start of any telegram will activate the pin uPD60611 only 0111 GPIO is Output for LEDO 1000 GPIO is Output for LED1 1001 GPIO is Output for LED2 1010 GPIO is Output for LED3 1011 GPIO is Output for Start of a Frame on TX uPD60611 only 1100 GPIO is Output for Start of Frame on RX uPD60611 only 1101 GPIO is Output for INT Bit Pin Description Mode Reset 15 12 GPIO3 Same as GPIOO except RW 1111 0111 Clock signal with 1ms RXCLK 1000 Clock signal with 0 1ms 1001 Reserved 1010 RXCLK 11 8 Reserved Write as 0 RW 1000 7 4 Reserved Write as 0 RW 1010 3 0 GPIOO 0000 No change when written RW 0111 0001 GPIO is Output for PPS Pulse LEDO R19UH0082ED0201 User Manual 2tENESAS 24 R19UH0082ED0201 User Manual 1110 GPIO is Output for CHIP_SYNC uPD60611 only 1111 GPIO is Input 4 9 2 GPIO_CONFIG_1 Register 7 1 Bit Name Description Mode Reset 15 12 GPIO7 Mil mode always PORXD3 RW 1111 regardless of setting Input RMII mode Same as GPIOO except 0111 always 0 1000 always 1 1
89. ormly over the entire channel bandwidth The seed for the scrambler is generated from the PHY address ensuring that in multiple PHY applications each PHY will have its own scrambler sequence The descrambler descrambles the decoded NRZ ciphertext bit from the MLT 3 decoder The ciphertext bit stream is decoded by addition modulo 2 of a key stream to produce a plaintext bit stream During reception of IDLE symbols the descrambler synchronizes its descrambler key to the incoming stream Once synchronization is achieved the descrambler locks on this key and is able to descramble incoming data 5 4 5 5B 4B Encoding Decoding The data on the line is coded 4B 5B and decoded on the receive path The main purpose is to remove repeated values i e 0000 is replaced by 11110 to ensure there is a signal change after a certain period In addition it allows to find faulty transmissions and add some control data The following table shows the relationship between payload data and the 5B Interpretation R19UH0082ED0201 AS User Manual RENES 34 Bee codes Name MI TXD RXD Interpretation group 4 0 3 0 11110 0 0000 Data 0 01001 1 0001 Data 1 10100 2 0010 Data 2 10101 3 0011 Data 3 01010 4 0100 Data 4 01011 5 0101 Data 5 01110 6 0110 Data 6 01111 7 0111 Data 7 10010 8 1000 Data 8 10011 9 1001 Data 9 10110 A 1010 Data A 10111 B
90. ption Mode Default 15 NEXT PAGE 1 additional next page will RO 0 follow 0 last page 14 ACKNOWLEDGE 1 successfully received link RO 0 partner s link code word 0 not successfully received link partner s link code word 13 MESSAGE 0 unformatted page RO 0 PAGE 1 message page 12 ACKNOWLEDGE 0 cannot comply with message RO 0 2 1 will comply with message 11 TOGGLE 0 previous value of the RO 0 transmitted link code word equaled logic one 1 previous value of the transmitted link code word equaled logic zero 10 0 MESSAGE 11 bit code word received from RO All 0 UNFORMAT link partner TED CODE FIELD 5 6 8 Register PHY 6 Auto Negotiation Expansion Bit Name Description Mode Default 15 5 RESERVED Ignore on read RO 0 4 PARALLEL 1 fault has been detected RO LH 0 DETECTION 0 no fault has been detected FAULT 3 LINK 1 link partner is next page able RO 0 PARTNER 0 link partner is not next page NEXT PAGE able ABLE 2 NEXT PAGE 1 local device is next page able RO 1 ABLE 0 local device is not next page able 1 PAGE 1 anew page has been RO LH 0 RECEIVED received 0 a new page has not been received 0 LINK 1 link partner is auto RO 0 PARTNER negotiation able AUTO 0 link partner is not auto NEGOTIATION negotiation able ABLE R19UH0082ED0201 User Manual 2tENESAS 58 R19UH0082ED0201 User Manual 5 6 9 Register PHY 7 Auto Negotiation Next Page
91. r devices to connect to standard IEEE802 3 Ethernet networks This devices specifically focus on low latency and low jitter to support today s industrial Ethernet standards In addition it features hardware support for IEEE1588 V2 Renesas Electronics specific enhanced diagnosis features allow a permanent cable quality monitoring for easy maintenance in factory automation The PHY can connect to unshielded twisted pair UTP cable via external magnetics or to optical fiber via fiber PMD modules To the upper layer MAC it interfaces to an Ethernet MAC layer through the IEEE 802 3 Standard Media Independent Interface MII or reduced MII interface The uPD60611 includes hardware support for PTP according to IEEE1588 Version 1 and 2 To support this a 80 bit clock is included in the PHY based on this clock timestamps can be taken based on received and transmitted frames and based on events on external pins The resolution for timestamps of received and transmitted telegrams is down to 1 ns by using internal PHY data The device also supports one step and two step timestamp insertion and offers some special hardware support for transparent mode It further offers a special signal to share the internal clock with other Renesas PHYs which then run on the same PTP clock Overview of product features e Single channel PHY e Fully standard compliant with IEEE 802 3i 802 3u for 1OOBASE TX 100BASE FX and 10BASE T e Integrated PMD sub layer
92. r to change modes from 10BT to 100BT and vice versa Autoneg disabled will take approximately 2us Mode changes from HD to FD and vice versa is instantaneously 2tENESAS 53 5 6 2 Register PHY 1 Basic Control Bit Name Description Mode Default 15 100BASE_T4 1 100BASE T4 able RO 0 0 no 100BASE T4 ability 14 100BASE_TX_ 1 100BASE TX ability with full RO 1 FULL_DUPLEX duplex 0 no 100BASE TX full duplex ability 13 100BASE_TX_ 1 100BASE TX ability with half RO 1 HALF_DUPLEX duplex 0 no 100BASE TX half duplex ability 12 10MB_FULL_ 1 10Mb s ability with full RO 1 DUPLEX duplex 0 no 10M b s full duplex ability 11 10MB_HALF__ 1 10Mb s ability with half RO 1 DUPLEX duplex 0 no 10Mb s half duplex ability 10 6 RESERVED Ignore on read RO 0 5 AUTO 1 auto negotiation process RO 0 NEGOTIATION completed COMPLETE 0 auto negotiation process not completed 4 REMOTE 1 remote fault condition RO LH 0 FAULT detected 0 no remote fault condition detected 3 AUTO 1 able to perform auto RO 1 NEGOTIATION negotiation ABILITY 0 unable to perform auto negotiation 2 LINK STATUS 1 link is up ROLL O 0 link is down 1 JABBER 1 jabber condition detected RO LH O DETECT 0 no jabber condition detected 0 EXTENDED 1 extended register RO 1 CAPABILITY capabilities 0 basic register set capabilities only User Manual 54 R19UH0082ED
93. re instead of hardware R19UHO0082ED0201 2tENESAS User Manual 52 R19UHO0082ED0201 User Manual 5 6 PHY Register List The PHY registers can be accessed at PHY address 0 for PHY 0 or PHY address 1 for PHY 1 These registers control only the PHY they belong to Some of these registers are duplicated on the PHY address 7 registers to ease software handling 5 6 1 Register PHY O Basic Control Bit Name Description Mode Default 15 RESET 1 software reset RW SC 0 0 normal operation When setting this bit do not set other bits in this register 14 LOOPBACK 1 enable internal loopback RW 0 mode 0 disable internal loopback mode 13 SPEED_ 1 100 Mb s RW 1 SELECTION 0 10 Mb s This bit is ignored if auto negotiation is enabled 0 12 1 12 AUTO 1 Enable auto negotiation RW Strap NEGOTIATION_ process option ENABLE 0 Disable auto negotiation process 11 POWERDOWN 1 General Power down RW 0 0 normal operation 10 ISOLATE 1 Electrically isolate PHY from RW 0 MII 0 Normal operation 9 RESTART_ 1 restart auto negotiation RW SC 0 AUTONEGOTIATION process 0 normal operation 8 DUPLEX_MODE 1 Full duplex RW Strap 0 Half Duplex option This bit is ignored if auto negotiation is enabled 0 12 1 7 COLLISION_TEST 1 enable COL signal test RW 0 0 disable COL signal test 6 0 RESERVED Write as 0 ignore on Read RO 0 Writing to Reg 0 in orde
94. rection field except for the very last link The delay on the last link is known to the slave and thus the complete line delay is known Although this method is more complex than the End to End transparent clock it offers much faster reconfiguration in case of line breaks 7 4 3 Timestamp Status Register 6 6 The Timestamp Status register shows the status for each buffer Bit Name Description Mode Default 15 10 Reserved write as 0 ignore on RW read 9 BUF_EMPTY_ 1 Buffer not empty for TX buffer RO 0 TX_PHYO PHYO 0 Buffer empty for TX buffer PHYO 8 BUF_EMPTY_ 1 Buffer not empty for RX buffer RO 0 RX_PHYO PHYO 0 Buffer empty for RX buffer PHYO 7 2 Reserved write as 0 ignore on RW read 1 OVERFLOW 1 Buffer overflow for TX buffer RO 0 BUF_TX_PHY PHYO 0 0 No overflow Cleared when read 0 OVERFLOW 1 Buffer overflow for RX buffer RO 0 BUF_RX_PHY PHYO 0 0 No overflow Cleared when read 2tENESAS 76 R19UH0082ED0201 User Manual The Timestamp Configuration register is used to configure the framer unit and is 7 4 4 Timestamp Configuration Register 6 7 used to select which register of the timestamp memory is read Bit Name Description Mode Default 15 8 Reserved write as 0 ignore on read RW DISCARD_OLD EST_TIMESTA MP 0 Do not overwrite timestamp if buffer overruns newest timestamp is lost 1 Overwrite oldest timestamp
95. revert the setting exchange TX and RX Again after a time of 0 63us it will send a burst of 1 us and in parallel check if there is a signal on one of the lines This will continue until a valid signal is detected on the RX line The PHY will only do a crossover if it detects signals on the actual TX line On an open line it will not exchange the RX TX lines as it cannot receive any signals The duration of this process can be between lt 1 us if the signal is initially recognized correctly and approx 565us if the crossover has to be done R19UHO0082ED0201 2tENESAS User Manual 36 5 5 3 2 Auto Crossover when using Autoneg or 10BT Mode Since the auto negotiation s method of communication builds upon the link pulse mechanism employed by 10BASE T MAUs to detect the status of the link the energy detection upon FLPs bursts is the same as the NLPs The NLP is a pulse transmitted every 16 8 ms and its pulse width is 100ns Typical burst width is 2 ms After reset the PHY will check for the a signal on the incoming lines As it is in its Break_link_timer state it will not start transmission before this timer is expired If there is a signal detected in that period it will adjust the MDI X accordingly and continue If no signal is detected it will start transmitting the FL Pulses to establish a connection As the switchover is in general done during the duration of the Break_link_timer there is no additional time required for Auto Cro
96. rrection If the DC content of the signal is such that the low frequency components fall below the low frequency pole of the isolation transformer then the drop characteristics of the transformer will become significant and baseline wander BLW on the received signal will result To prevent corruption of the received data the DSP corrects for baseline wander 2tENESAS 3 5 4 3 NRZI MLT 3 Encoding Decoding MLT3 is a specific version of a NRZI coding using a trilevel code where a change in the logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit O Basically it uses the NRZI coding as input but the 1 is flipped to 1 every second time The main advantage is that it reduces the effective frequency on the cable to 1 4 or 125 8 MHz The decoder converts the MLT 3 data coming from the DSP to a NRZ data stream The conversion of data to NRZI MLT 3 encoded data is shown in the following picture Data 1 1 O 141 0 0 MLT 3 encoded data 0 This code is used on the Ethernet data lines in 100TX mode 5 4 4 Scrambler Descrambler To reduce EMI the data sent is scrambled before it goes on the line and descrambled in the receiver This reduces the emission of specific frequencies and spreads the emissions on a wider frequency band Scrambling the data helps eliminate large narrow band peaks for repeated data patterns and spreads the signal power more unif
97. rt It generates 32 output phases The DSP selects which of these phases is used to sample the incoming signal A single PLL is used for both PHYs Therefore a Power Down of a PHY will only power down the PLL if both PHYs are powered down Analogue Frontend The analogue frontend consists of two Programmable Gain Amplifiers a low pass filter and the ADC 5 3 1 Adaptive Equalizing The adaptive equalizer compensates for phase and amplitude distortion caused by the Physical channel consisting of magnetics connectors and CAT 5 cable The equalizer can restore the signal for any good quality CAT 5 cable 5 3 2 100Base TX Receiver ADC The Receiver ADC is part of the analog block It is clocked with a 125 MHz clock which can be selected by the DSP from one of 32 phases shift Digital Signal Handling The following chapters describe how the signal is handled in the digital part of the PHY 5 4 1 DSP The DSP is re shaping the received signal so it can be further processed The ADC is sampling the signal at an interval of 125 Mhz which is the sampling frequency of the signal However the frequency of the signal is significantly lower than that due to the MLT 3 coding Based on the received and decoded signal the DSP can measure the quality of the signal and either adjust its internal filters or adjust the sampling phase of the ADC One of the internal filters can be read and observed to observe the cable quality 5 4 2 Baseline Wander Co
98. s or the start of frame delimiter which is a J symbol All other symbols are indicating that a bit error has happened and are counted as error 2 Data transmission During data transmission there are 32 possible symbols of which only 19 are valid symbols The rest indicate a bit error and will be counted as such Note that the H symbol is also counted as an error symbol A pre condition of the BER mechanism operation is the lock of the descrambler it will try to adjust itself while receiving IDLE patterns and is considered locked if a reasonable number of IDLE patterns have been received and descrambled Unless the descrambler is locked the BER monitor is not operable and no data can be received 2tENESAS 43 5 5 6 2 Register PHY 23 BER Counter Control Register R19UH0082ED0201 User Manual Bit Name Description Mode Default 23 15 BER_LNK_OK Link quality indication indicates state of link monitor 0 Not in Good Link state 1 In Good Link state Will go up as soon as the counter is below the trigger level after start up Can be used to detect reliably link up after start up 0 23 14 BER_CNT_LNK_EN 1 A trigger on the BER or on the FEQ monitor will cause a link down 0 A trigger on the BER FEQ will just cause the state machine to leave Good Link state RW 23 13 11 BER_CNT_TRIG Trigger level for BER Count to define link up down Counter in 2 n
99. sceeestecevesstuecessseteceess 82 7 4 8 PHY _DELAY_RX Register 6 12 ccccccceesseceeeeseeceeeseeeeeeeseeeeeessaeeeseseeeeeeessaeeeenesaeeeenes 82 7 5 Input Capture Reese 83 7 5 1 Input Event Control Register 7 12 ss usssennnrennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nennen 84 7 5 2 Input Capture Pin Control register 7 8 eecceceeeeeeeeeeeeeeeeeeeeeeeeeaneeeeeeeeseneeeeneeeeeees 85 7 5 3 Input Capture Pin Control register 7 9 cc seeeeeceeeeeeeeeeeeeeeeeeeeeeeeeaneeeeeeeeseeseeeneeeeeees 85 7 5 4 Input Capture Pin Control register 7 10 c eceecceeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeseeseesneeeenes 86 7 5 5 INPUT_EVENT_DATA_READ_WORD Register 7 15 c cccessssceeesseceeeeeseeeeessseeeees 87 7 5 6 INPUT EVENT DATA BLOCK READ Register 7 14 c cccssscssseeeeseeeseeeeeseeeeeteeeeeeeees 88 7 5 7 INPUT_CAPTURE_DATA_POINTER Register 7 13 ccccscccssseeeseeeeeeeeseeeeesseeeeeeeeeeeees 88 7 6 Pulse Generator HE ege Sege SSES EES EE 89 7 6 1 Pulse Output Control Register 7 16 cccccssscessseceeeseeeeeeesseeeeeeseeeeeenseeeeeesseeeeeenseeneeenss 90 7 6 2 PULSE_STARTTIME Register 7 17 ccsssccccssssscssssseccesnsseceesnsseceesnseceesnseceesnssecenenss 91 7 6 3 PULSE_WIDTH Register 7 18 ccsssceceesseceeeeseeceeeeeeeeeeessaeeeeesnaeeeeeseaeeeensseeeeeneeaneeeess 92 7 64 PULSE_INTERVAL Register 7 19 c ccccsscccccissccccessscoteessecocecaseccteessidesveus
100. ssover in Autoneg Mode 5 5 3 3 Auto Crossover when connecting Autoneg and 100BT Mode R19UH0082ED0201 User Manual This is a situation in which one link partner A is in auto negotiation mode and the other partner F is set to 100 Mb s fix mode After power up the forced PHY F will start sending FLP while the other link partner A is in Transmit disable state So while PHY A will wait for its break_link_timer time 1200ms 1500ms the forced PHY F will turn itself off randomly for every time period of sample timer 62 2us to listen for a signal on its TX line It will not change its transmit line pair though unless it detects a contention PHY A adjusts its Autocrossover state as it received a signal during its break_link_timer expiration time When PHY A moves to ABILITY_DETECT mode and transmits FLP PHY F detects these pulses As PHY A has already adjusted its autocrossover mechanism correctly there is no need for PHY F to do SO 5 5 4 Auto Polarity The core automatically detects and corrects for polarity reversal in wiring in 10BASE T mode The result of polarity detection is indicated by the flag XPOL bit 4 in register 27 Polarity is checked at end of packets in 10BASE T 5 5 5 Auto Negotiation The objective of the auto negotiation function is to provide the means to exchange information between two devices that share a link segment and to automatically configure both devices to take maximum advantage of their abilities Auto
101. tched internally when the offset correction is stopped either when it is finished or if it is manually disabled and reenabled with the EN_OFFSET_CORR register bit Bit Name Description Mode Default 47 OFFSET_SIGN Sign WO 0 1 Subtract offset 0 Add offset 46 44 OFFSET Increase value in ns WO 0 43 Reserved Write as 0 WO 0 42 32 OFFSET_INTERVAL Interval in steps WO 0 0 No interval 1 No interval 2 add every 2 step 3 add every 3 step 31 30 Write as 0 WO 0 29 0 OFFSET _COR_COUNT Count how often the WO 0 step value is added 2tENESAS 73 7 3 5 CLOCK_DRIFT Register 6 4 This register contains a correction value which can be used to continuously correct the clock value to compensate for oscillator drift The value in the DELTA_VAL register is summed up every clock cycle 125MHz as soon as the sum has exceeded Ox3fffffff a value of 1 an additional ns is depending on the DELTA_SIGN bit added subtracted from the clock value This register is latched internally when the EN_DRIFT_CORR register bit is set The value for the DELTA_VAL register is calculated based on the following formula DELTA rat IT a 125 MHz 1 drift where drifi s slis correction value for clock use when DELTA _ SIGN 1 use when DELTA_ SIGN 0 Bit Name Description Mode Default 31 DELTA_SIGN Sign of the delta value RW 0 1 Clock is slowed down 0 Clock is speeded up 30 R
102. text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions Refer to the text of the manual for details The following documents apply to the uPD60610 60611 Group Make sure to refer to the latest versions of these documents The newest versions of the documents listed may be obtained from the Renesas Electronics Web site ei Description Document Title Document No ype Hardware specifications pin assignments memory maps peripheral function specifications User s manual User s electrical characteristics 1 qustrial Ethernet This User s manual manual for timing charts and Hardware operation description PHY R19UH0082ED0201 Note Refer to the Single PHY ASSP application notes for details on using peripheral functions Application Note industrial Ethernet Application design and wiring Single PHY PP g a ASSP Layout R19AN0014ED0101 Note Examples of schematics recommendation and board layout l and design rule Information on using and Application Note nati configuring special Industrial Ethernet oy functions and application PHY ASSP examples Programming R19AN0010ED0100 Guide Renesas Product specifications Customer R19TU0003ED0100 Technical updates on documents Notification 2tENESAS Notation of Numbers and Symbols Register Notation R19UH0082ED0201 User Ma
103. the leading J and K symbol of a telegram as start of frame before they can start to output data on the MII interface Thus two symbols have to be received before output can be started on the MII interface The Renesas PHY offers a special mode to only decode the leading J symbol and start receiving the data immediately The PHY will thus output data on the MII following the first J symbol without having to wait for the reception of the K symbol This reduces the roundtrip delay by 40ns This PHY family is thus able to support a roundtrip delay lt 200ns In the unlikely case that the J detection was due to a bit error and the next K symbol is not received the RX_ERR signal is asserted and reception resumed 5 5 8 Special Isolate In many applications it may be desirable to have a more flexible option to configure the PHY compared to strap options which need to be decided when the board is produced Usually a PHY will read the configuration from the strap pins and immediately after power up will try to connect This does not leave time for a controlling MAC to change the configuration before the communication and setup with the partner PHY has been started In special isolate mode the PHY will not connect to its partner PHY but stay quiet on the line until enabled in software Thus a controlling MAC has time to configure the PHY according to the application and the special configuration can be controlled by firmwa
104. therwise the process is restarted As the AUTONEG_WAIT_TIMER in this case slows down the Link Up process its value can also be configured The following picture gives a very simplified overview on the auto negotiation process with the related timers 2tENESAS 39 R19UH0082ED0201 User Manual Start of Process start break_link_timer 1200ms Sense RX TX and adjust MDI X Break link timer done 100BT signal Transmit FLP Listen to RX TX and adjust MDI X Start autoneg_wait_timer 500 ms 3 identical FLP detected Stop sending FLP Exchange FLP Burst Check Link signal for Parallel Detection Link Adjust settings speed Bad duplex accordingly Send 6 8 FLP with ACK set Autoneg_wait_timer expired Link ok Link_fail_inhibit Start link_fail_inhibit Timer expired timer 750ms Transmit IDLE Received correct signal Link Failure Link good The general behaviour can be configured with the external strap pins This can be used to use either the standard timing or the reduced timing with a Break_Link_Timer of 80ms and an Autoneg_wait_timer of 35ms The following table shows the values in ms that can be configured by the strap option Sale IEICE Strap Break_Link_Timer Autoneg_wait_timer Option Enabled 80 35 Disabled 1250 850 2tENESAS 40 5 5 5 2 Disabling Auto Negotiation Auto negotiation can be disabled by register setti
105. time stamping unit RW TS_ OVWR_EN 0 New timestamps can overwrite older ones when the buffer is full 1 New timestamps are not stored if memory has not been read out no overwrite and the buffer is full RW TS_RAM_ OVERFLOW 1 Timestamps were overwritten 0 Timestamps were not overwritten RO 7 6 Reserved ignore on read write as 0 RW 5 0 TIMESTAMP WRITE_POS Pointer to the timestamp for the next event 96 bit word pointer incremented by the event manager after writing RO R19UH0082ED0201 User Manual 2tENESAS 84 7 5 2 Input Capture Pin Control register 7 8 The Input Capture Pin Control register is used to enable timestamping for GPIO 0 to 7 and is used to configure the edge on which it should trigger Bit Name Description Mode Default 15 14 IN_CAP_GPIO7 00 Disable event timestamping RW 0 for GPIO7 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges 13 12 IN_CAP_GPIO6 00 Disable event timestamping RW 0 for GPIO6 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges 11 10 IN_CAP_GPIO5 00 Disable event timestamping RW 0 for GPIO5 01 Timestamp on rising edge 10 Timestamp on falling edge 11 Timestamp on both edges 9 8 IN_CAP_GPIO4 00 Disable event timestamping RW 0 for GPIO4 01 Timestamp on rising edge 10 Timestamp on falling edge 11
106. tion SFR Special Function Register VCO Voltage Controlled Oscillator PTP Precision Timer Protocol All trademarks and registered trademarks are the property of their respective owners 2tENESAS Table of Contents General Description sissciiisicouwscievincedinnwccactvineectesbanctewtues 12 1 1 Overview of product features KEEN EEn 12 LZ Special product feardeg 13 1 3 PNP d EN 13 Pin FUNCHONS a eegene 14 2 1 Pinning WOMEN AUN eegene 14 21i Pinay UE 14 KN EC HEN PONE ll E 15 System Diagrai RE 17 3 1 Device block diagram sssssssssunssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nenne 17 Global Hardware Description cccssesseeeeeeeeeeeeeeeeeees 18 4 1 Register PCCOSS aces acca aa ease acca mnanaa nnman a n 18 4 2 General SMI Control Register 7 31 ssssssnsnssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 19 4 3 Power Control Register 7 30 ssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 19 4 4 PHY Status Register 7 28 snnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 20 4 5 Strap option Register 7 27 ccccccccseseseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaeeeeeeeeeeeeeeeaaes 20 4 6 PHY LED Status Register 7 24 ssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 21 4 7 Interrupt Status register 7 20 ssssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 22 4 8 Interrupt Mask register 7 21 sssnsnnssnnn
107. tions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you hav
108. w N E SAS Industrial Ethernet PHY Single PHY ASSP uPD60610 uPD6061 1 All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Technology Corp website http Awww renesas com Renesas Electronics www renesas com Doc number R19UH0082ED0201 April 9 2013 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of

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