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MC68322UM MC68322 User`s Manual

1. ONAN a m IWAN ee RRNA RRNA ch PPS I vE 1 B Ey PSS N ES BI LIENS Nake REE ohj a Sm ae E 00 04 05 06 07 08 09 0 Figure 12 2 256 Possible Boolean Coded Graphic Operation Transfers The Boolean codes shown in Figure 12 2 are derived from the constants listed in Table 12 1 For example setting the Boolean code to EE causes the MC68322 to OR the source and destination operands thus producing a transparent combination of the two This combination illustrated in Figure 12 2 row EO column is calculated by logically OR ing the destination and source constants DESTINATION V SOURCE BOOLEAN CODE 10101010 V 11001100 11101110 For MES oduct to www freescale com Freescale Semiconductor supine A more complicated graphic oper
2. Cr paese romer e weca of m CECE HT NOTE Denotes That This Specification Only Applies To Register And DRAM Read Cycles During Core Cycles Read Data Propagates Directly From The Core To The ICE And Is Unaffected By The MC68322 CLK2 CLK1 4 HALT Figure A 8 ICE Reset AC Timing For On The Product Go to www freescale com Freescale Semiconductor Inc n Une so s s ss 5 5 A25 A1 i 26 27 2 FCO 100 105 RW D15 D0 DTACK CS7 CS0 u ET Figure A 9 ICE Read Cycle AC Timing For On This Product Go to www freescale com _ Freescale Semiconductor CLK2 CLK1 2 25 1 26 27 X geb eT Figure A 10 ICE Write Cycle AC Timing For On This Product Go to www freescale com Freescale Semiconductor Inc n vllis
3. 10 17 10 5 2 Rising Edge PVCCR Bit 11 10 17 10 5 3 Border Polarity High PVCCR Bit 5 0 10 17 Section 11 RISC Graphics Processor 11 1 PPP PS 11 2 11 1 1 RGP Start Register 11 2 11 1 2 Diagnostic Register 11 2 11 1 3 Interrupt Event Register 2 4 4 11 2 11 2 11 3 12 Graphic Operations 12 1 Types ob BI SDS 255 diis eee 12 1 12 2 12 2 12 3 Types of Graphic Operands 22 11 12 3 12 4 Boolean COGUBS x riore rrr e bo Pid ER bean ean bedside Pikes cn 12 3 12 5 Bit Block Transfers 12 5 12 6 Scanline Transfers sasir E E ER 12 5 12 6 1 Scanline Tables and Bit String Specifiers 12 6 12 6 2 Scanline Run Operation xar exc ecd 12 8 12 6 3 Executing During Banded Applications 12 9 12 6 4 Halftone Companion Tables 12 10 12 7 Scanline and Halftone Table Example
4. 4 3 4 5 Write Cycle FloWClart eran pa o er ade qat ot hee uda 4 4 4 6 Word and Byte Write Cycle Timing Diagram to Chip Selects 4 5 4 7 Word Write Cycle Timing Diagram to DRAM 4 6 4 8 Internal Interrupt Acknowledge Cycle 4 7 4 9 Interrupt Acknowledge Cycle Timing Diagram 4 7 4 10 Reset Operation Timing Diagram 2222 2 4 8 4 11 Bus Arbitration Timing Diagram 2 4 10 4 12 External Bus Master Read Cycle 4 11 4 13 External Bus Master Write Cycle 2 2 2 2 4 4 40 1222222 4 12 5 1 Software Interrupt Event Register 5 3 5 2 External Interrupt Registers 2 1 5 4 5 3 edet Se tate ea Msi A cues 5 6 5 4 Timer Interrupt Event Register 2 5 6 5 5 General Exception Processing Flowchart 5 7 5 6 General Form of an Exception Stack Frame 5 8 5 7 Module Soft Reset Register 2 22 222 5 14 F
5. DESTINATION BANDED BITMAP EOBPA BAND NUMBER BAND EOBPA 0 PAGE 180 PAGE B2T 0 B2T 1 Figure 13 23 Banded Bitmap Parameters For Mort 160322 On This Product Go to www freescale com Freescale Semiconductor Inc SET_BOOL_XXX Set Boolean Code PARAMETERS DESCRIPTION 0 0 SET_BOOL_D BOOL_D Destination only Boolean code 0x0D SET_BOOL_HD Opcode BOOL_HD Halftone Destination only Boolean code 0x0E SET_BOOL_SD BOOL_SD Source Destination only Boolean code 0x0F SET_BOOL_SHD Opcode BOOL_SHD Source Halftone Destination Boolean code Note A generalized algorithm for generating the Boolean code values is given in Section 12 Graphic Operations SET_BOOL_D graphic order specifies the Boolean code to be used all 1 transfer graphic orders that specify only the destination bitmap The SET BOOL HD graphic order specifies the Boolean code to be used by all 2 operand transfer graphic orders that specify a halftone bitmap as one of their operands The SET BOOL SD graphic order specifies the Boolean code to be used by all 2 operand transfer graphic orders that specify a source bitmap as one of their operands The SET BOOL SHD graphic order specifies the Boolean code to be used by all 3 operand transfer graphic orders that specify both a source and halftone bitmap as well as a destination bitmap as opera
6. so 2 w 5 5 go 65 67 FC2 1 68 A25 M MEE UDS LDS CU gt 78 8 AVEC IPL2 I IPLO Figure A 11 ICE Interrupt Acknowledge Cycle AC Timing Figure A 12 ICE Bus Arbitration AC Timing For On This Product Go to www freescale com Freescale Semiconductor wee cieolieevis er A 4 ICE PIN ASSIGNMENT The following figure illustrates the MC68322 ICE pin assignments and case drawing for the 208 PGA package A18 17 GND 16 R 01 19 03 21 GND 010 L 014 D12 K o EDTACK BG J BG H Voc G CS0 F CS3 E 6 62 800 GND RESET GND BUSY FAULT C TEST PD2 PD7 B PDO Vcc ACK A STROBE 68322 BOTTOM VIEW AUTOFD 2 INIT SELECT GND 9 1 GND 8 5 Vcc PERROR GND SELECTIN 2 2 For On The Product Go to www freescale com DLEN GND O CMD m FSYNC
7. NIC 5 5 CU PRINT LSYNC VIDEO Vcc EA RAS5 Oo RAS3 20 RAS1 GND WE Freescale Semiconductor APPENDIX B APPLICATIONS The MC68322 provides a wide variety of configuration possibilities The sample design described in this section demonstrates the detailed components required to design and build an MC68322 based laser printer This design demonstrates the typical configuration of printing systems for laser printers ink jet printers fax machines copiers and many other paper and nonpaper handling applications Also included in this section is a sample code stub to set up a memory map The following schematics describe the required connections for the MC68322 a 512K DRAM DRAM SIMM flash EPROM random control logic serial EEPROM in circuit emulation option parallel port and generic print engine interface B 1 CONFIGURING THE MC68322 The MC68322 requires up to two clock sources to properly clock the device Some designs take advantage of a single oscillator to clock the MC68322 For example if the video rate is 7 8MHz then a 31 2MHz source could be used to clock CLK2 and VCLK Several pull up resistors may be required to properly negate unused options on the MC68322 Figure B 1 illustrates the MC68322 connection For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor 5V
8. On The Product Go to www freescale com Freescale Semiconductor Inc PEI CLK2 A25 A1 57 50 RD 015 00 5 R W EC000 Core Read Cycle AC Timing One Wait State Access RSET 0 RACC 1 RHLD 1 Figure 14 7 Read Access 2 4 1 3 s s s s ss w w s 56 25 1 gt O gt CS7 CS0 RD 015 00 q o On AS RW EC000 Core Read Cycle AC Timing One Wait State Access RSET 1 RACC 0 RHLD 1 Figure 14 8 Read Access 4 2 1 3 For More ie ah Go to www freescale com Freescale Semiconductor Inc CR EW Qt so C N NAA AY AYA AAN 9 A25 A1 A EM C 97 50 gt On 9 015 00 mar EN 05 On AS RW 000 Core Read Cycle AC Timing One Wait State Access RSET 0 2 RHLD 0 Hold Time of 1 CLK2s The Chip Select Negates Before The RD Figure 14 9 Read Access 2 6 1 3 so s s s ss w w s 5 so st ENAN ANAS NAJN A25 A1 10 57 50 RD 9 01590 CL WAIT AS RW 000 Core Read Cycle Timing One Wait State Access RSET 1 RACC 1 RHLD 0 Hold Time of 1 CLK2s The Chip Select Negate
9. 7 1 2 4 Operational Example 7 2 DRAM Control Register 7 3 DRAM Timing Modes 7 4 DRAM ACCESSES Lob tee 7 4 1 DRAM Refresh Cycles 2 7 4 2 DRAM Read Cy Gloss aieo tete ren uendere 7 4 3 DRAM Write Cycles 2 7 4 4 DRAM Bus 7 4 5 DRAM Burst ACCESSES 7 5 lt Section 8 DMA Interface 8 1 DMA Configuration Registers 8 1 1 Transfer Address FieldS eese 8 1 2 Transfer Count Fields 8 1 3 Flush Request Fields 4 8 2 Control Register 8 3 Speed Register 222 2 2 4 42 14442 4400 8 4 Interrupt Event Registers 8 5 Initiating DMA Operation sese 8 6 DMA Transfers pd era e Pe o 8 6 1 PDMA Transfers ened eves ences 8 6 2 MC68322 Bus Read and Write Cycles 8 6 3 DRAM Bus Read and Write Cycles 8 7 DMA Transfer Termination
10. NIIS 11 1 5 5 There three registers that provide control of and receive status from the RGP the RGP start register the RGP diagnostic register and the RGP interrupt event register 11 1 1 Start Register The RGP starts by writing the address of a display list into the RGP start register RSR When the RSR is loaded the first graphic order is fetched The RSR in the MC68322 is double buffered thus allowing a second display list address to be loaded into the RSR prior to the completion of the first display list The second display list is automatically started as soon as the first one finishes 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 800 0000 HIGH WORD 00 802 LOW WORD ES 15 44 13 4 11 10 9 8 7 6 5 4 3 2 1 0 Figure 11 1 Start Register 11 1 2 RGP Diagnostic Register The RGP diagnostic register RDR contains the byte address of the graphic order opcode or operand being interpreted from the display list It is frozen when an error occurs and the RGP interrupt event register s RER bit is set Depending on the nature of the error the RDR can be frozen beyond the exact point in the display list wnere an RGP error occurs because of the prefetch characteristics of the RGP The RDR resumes functioning when a soft reset of the RGP occurs 15 14 4 12 11 10 9 8 7 6 5 4 3 2 1 0 00 804 0000 HIGH WORD 00 806 LOW WORD 15 14 13 12 11 10 9 8 7
11. 0 10 5 10 4 PVC Interrupt Event Register 2 1 1 10 6 MANUS Product Go to www freescale com Figure Page Number Title Number 10 5 Printer Communication Interrupt Event Register 10 8 10 6 PVC Video Interface State Diagram 10 10 10 7 Command Operation MC68322 Supplies CCLK 10 12 10 8 Command Operation Print Engine Supplies CCLK 10 13 10 9 Status Operation MC68322 Supplied CCLK 10 14 10 10 Status Operation Print Engine Supplied 10 14 2 f E 11 2 2 Diagnostic Register 22 2 24 2 2 4 4 4 11 2 11 3 Interrupt Event Register 2222244 2 2 1 29 41 00 11 2 12 1 Eight Common Graphic Operation Transfers 12 3 12 2 256 Possible Boolean Coded Graphic Operation Transfers 12 4 1253 Bit String Specifier 12 7 12 4 Scanline Run Operation oie bero aerei den cues cede teased itat ri etu 12 8 12 5 Illegal Bit String Specifier Use oot ei Nene ad ire o
12. Section 10 Print Engine Interface 10 1 Print Engine Interface Registers 10 1 1 Printer Communication Register 10 1 2 PVC Control Register 4 2 4 4 10 1 3 Printer Control Block Register Set 10 1 4 PVC Interrupt Event Register 10 1 5 Printer Communication Interrupt Event Register 10 2 Printer Communication Protocol 10 3 Print Engine Interface Operation 10 3 1 Synchronous Asynchronous PVC Operation 10 3 2 Command Operation 10 3 2 1 CCLK Supplied By MC68322 10 3 2 2 CCLK Supplied By Print Engine 10 3 3 Status A Rus 10 3 3 1 CCLK Supplied By 68322 10 3 3 2 CCLK Supplied By Print Engine 10 3 4 PLL Video Clock Divisor 4 244 4 4 22 10 4 Reset DC I 10 5 PVC Video Data Timing ERE noci nce For Mare Un This Product Go to www freescale com Freescale Semiconductor TABLE OF CONTENTS Continued Paragraph Page Number Title Number 10 5 1 1X Video Clock PVCCR Bit 0 0
13. supplying valid data 4 11 X system integration module 6 1 system interface signals 2 4 X dimension definition 1 9 X dimension definition 12 1 T XOFF defined 13 3 termination XON definition 13 4 bad address 8 10 core forced 8 10 Y normal 8 9 terminology E 1 Y dimension test register C 3 definition 1 9 thermal characteristics 14 1 Y dimension definition 12 1 TIER 5 5 timer count 5 6 interval 5 6 timer module 5 5 tracing 5 12 tracing 5 12 transfer bit block 12 5 scanline 12 5 transfer count field DMA described 8 3 transfer initiating 4 4 transferring data 4 1 U unbanded duplex operation during 13 7 unbanded bit map described 12 1 unbanded bitmap 12 1 unexpanded bit map described 12 1 unexpanded bitmap 12 1 unimplemented instruction exception 5 11 unimplemented insturction emulation 5 11 V vector numbers listed 5 8 table 5 8 vertical margin 10 5 video underrun interrupt event 10 7 W word operation 4 4 word sized read cycle support 4 10 word sized write cycle 4 11 For Mare Un This Product Go to www freescale com
14. W SL2F HD Halftone Destination Scanline Transfer to Frame PARAMETERS s DESCRIPTION Byte SL2F HD Opcode Byte Reserved Long Word Destination physical bit address Word Frame width in bits Word Halftone X remainder Word Halftone Y remainder Long Word Halftone physical address of the starting pixel 28 of 32 bits Companion halftone table physical byte address word aligned 28 of 32 bits Scanline table physical byte address word aligned The SL2F HD graphic order causes the MC68322 to render a scanline table image to a frame and apply a halftone bitmap in the process The destination and halftone pixels are combined as specified by the Boolean code last set by the SET BOOL HD graphic order The destination frame warp is taken from the graphic order s frame width FW parameter The SET HTBMAP graphic order must previously define the halftone bitmap dimensions Halftone tiled patterns are typically anchored to the page The rendering of a scanline table may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where it is positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the initial destination address given in the graphic order Remember that the initial destination address is not where the first pixel is drawn it is the point to which the first bit string specifier s displacem
15. CBSY CMD VIDEO PRINT ACK BUSY SELECT PERROR FAULT 451 Freescale Semiconductor J52 Us eee ere CONN40 CONN40 1 2 1 2 1 2 IRQ1 3 4 25 3 4 24 ICLK1 3 4 DLEN CS7 5 6 CS6 A23 5 6 22 IRESET 5 6 HALT CS5 7 8 CS4 A21 7 8 A20 IBG 7 8 BR CS3 9 10 CS2 M9 9 10 A18 ILDS 9 10 DTACK CS1 14 1 cso 17 1 12 16 IUDS 4 42 AVEC CLK2 13 WRL M5 13 14 14 13 14 WRU 15 16 RD M3 15 16 M2 IFC1 15 16 IPL1 WAIT 17 18 AS M1 17 418 10 2 17 18 IPL2 19 20 EDTACK 09 19 2 08 19 20 21 22 07 21 22 06 015 23 24 014 05 3 24 04 JUR D13 25 26 D12 A03 25 26 02 011 27 2 010 01 27 2 009 20 30 008 20 30 DREQ 007 301 32 006 CMD 31 2 STS D05 33 4 D04 CCLK 33 4 D03 35 36 D02 CBSY 35 36 SBSY D01 37 38 D00 e 37 38 PRINT 39 40 39 40 gt 453 2 J54 CONN40 1 2 3 4 LSYNC 10 VIDEO 5 6 VCLK 09 08 7 8 07 06 9 10 05 04 RAS5 11 12 RAS4 03 02 RAS3 13 14 RAS2 01 00 1 15 16 RASO WE 17 418 SELIN AUTOFD CAS1 19 20 CASO FAULT SELECT 2 2 INIT PERROR MD15 23 24 MD14 BUSY ACK MD13 25 26 MD12 PD6 MD11 27 28 MD10 PD5 PD4 MD09 29 30 MD08 PD3 PD2 MD07 31 2 MD06 PD1 PDO MD05 33 4 MD04 STROBE MD03 35 36 MD02 EMURST RESET MD01 37 38 MD00 7 39 40
16. HIGH BYTE LOW ENABLE OOFFF740 XXXXXXXX XXXXX000 INT BSY FLL TCR CMP OOFFF742 XXXXXXXX XXX00000 REG INTLEVEL 00 744 XXXXX000 PDMA ENABLE 00 750 XXXXX000 INT FLL TCR CMP ILA OOFFF752 XXXXXXXX XXX00000 REG INTLEVEL OOFFF754 XXXXX000 ENABLE OOFFF760 XXXXX000 00000000 PIER IVD CRD DRD IHL INH AFL AFH STL STH SNL SNH OOFFF762 000 00000000 INT LEVEL OOFFF764 XXXXXXXX XXXXX000 2 0 OOFFF770 XXXXXXXX 8 52 02 5 50 0 72 XXXX0000 EXIRO OOFFF774 XXXXXXXx XXXXX000 MODE2 MODEO O0FFF776 XXXXXXXX XXXX0000 SENO OOFFF 778 XXXXXX00 ENB3 ENB1 OOFFF780 XXXXXXXX XXXXXX00 STS3REQ3 STS1 REQ1 OOFFF782 XXXXXXXX 0000 EXIR1 INT LEVEL OOFFF784 XXXXXXXX XXXXX000 MODE3 MODE1 OOFFF786 XXXXXXXX XXXX0000 O0FFF 788 XXXXXXXX XXXXXX00 ENABLE 00 790 XXXXXXX0 00000000 SIER EIA CIA EVENT OOFFF792 XXXXXXX0 00000000 SET OO0FFF794 XXXXXXXX X0000000 MSRR GDR PDR RGP PVC O0FFF 7A0 XXXX0000 um 0000 HIGHWORD OOFFF800 00000000 00000000 LOWWORD ooFFF802 00000000 00000000 m 0000 HIGHWORD OOFFF804 00000000 00000000 LOWWORD 00 806 00000000 00000000 MMAR BASEADDRESS 00 900 XXXX0000 322MSK REV OOFFF902 00000000 000
17. SIZE BASE ADDRESS 27 18 OOFFFO60 XX000000 00000000 WHLD WSET RHLD RSET RACC OOFFF062 00000000 00000000 CSR7 SIZE BASE ADDRESS 27 18 00 070 XX000000 00000000 WHLD WSET WACC RHLD RSET RACC OOFFFO72 00000000 00000000 CSDTR WACC RHLD RSET RACC OOFFFO080 00000000 00000000 CSRR REC RECOVERY SELECT OOFFF082 XX000000 00000000 DRAMO RM SIZE BASE ADDRESS A27 A19 OOFFF100 XXXX0000 00000000 DRAM1 RM SIZE BASE ADDRESS A27 A19 00 110 XXXX0000 00000000 DRAM2 RM SIZE BASE ADDRESS A27 A19 00 120 XXXX0000 00000000 DRAM3 RM SIZE BASE ADDRESS A27 A19 OOFFF130 XXXX0000 00000000 DRAM4 RM SIZE BASE ADDRESS 27 19 OOFFF140 XXXX0000 00000000 DRAM5 RM SIZE BASE ADDRESS A27 A19 OOFFF150 XXXX0000 00000000 For Saat ER DMAA Product Go to www freescale com ansan Freescale Semiconductor Inc mvv y MME rv MISI Table C 1 Memory Mapped Register Set Continued Go to www freescale com MEMORY MAP VALUE AT RESET REG ADDRESS 34 15 14 13 12 11 10 978 7 6 5 4 3 2 0 HIGH BYTE LOW reise s REFRESH INTERVAL COUNT RIC 00 162 XXXXXX00 010000
18. On The Product Go to www freescale com Freescale Semiconductor Inc As an extreme illustration of these rules consider the arrival of an interrupt during the execution of a trap instruction while tracing is enabled First the trap exception is processed then the trace exception and finally the interrupt exception After the execution of the instruction is complete and before the start of the next instruction exception processing for a trace begins and a copy of the internal status register is made The transition to supervisor mode is made and the T bit of the internal status register is turned off thus disabling further tracing The vector number is generated to reference the trace exception vector and the current internal program counter and the copy of the internal status register are saved on the supervisor stack The saved value of the internal program counter is the address of the next instruction Instruction execution commences at the address contained in the trace exception vector 5 4 2 7 ADDRESS ERROR An address error exception occurs when the core attempts to access a word or long word operand or an instruction at an odd address The bus cycle is aborted and the core ceases current processing and begins exception processing Likewise if an address error occurs during the exception processing for an address error or reset the core is halted A common example of address error generati
19. ON oduct to www freescale com Freescale Semiconductor Inc ow MAT wires UNEXPANDED SOURCE BITMAP DESTINATION BANDED BITMAP lt DWB gt Su XMUL gt BOOL SD USED TO COMBINE FRAMES EXPANDED SOURCE BITMAP Figure 13 9 Expanded Source Destination bitBLT To Banded Bitmap 0 Page UNEXPANDED SOURCE BITMAP DESTINATION BANDED BITMAP SW BOOL_SD USED TO COMBINE FRAMES 5 gt DW8 gt XMUL EXPANDED SOURCE BITMAP Figure 13 10 Expanded Source Destination bitBLT To Banded Bitmap 180 Page For Mort 160322 Shon On This broduct Go to www freescale com Freescale Semiconductor MAT wires Z8 RR BLT2BB XHD Expanded Source Halftone Destination bitBLT to Banded Bitmap PARAMETERS s DESCRIPTION Byte BLT2BB XHD Opcode Byte Band number when graphic order is executed Long Word Destination logical bit address Word Destination frame width in bits Word Destination frame height in scanlines Long Word Unexpanded source physical bit address Word Unexpanded source frame warp in bits XOFF XMUL Two 4 bit Fields X offset and X multiplier in bits YOFF YMUL Two 4 bit Fields Y offset and Y multiplier in scanlines HXR Word Halftone X remainder HYR Word Halftone Y remainder HA Long Word Ha
20. 14 19 14 29 External Bus Master Bus Arbitration AC Timing 14 19 14 30 External Bus Master Multiple Cycle AC Timing 14 19 15 1 68322 160 Lead Plastic Quad Flat Pack 15 2 15 2 160 Pin QFP Package Dimensions 15 3 A 1 ICE Interface Block Blagraiti nadie een dci ge ie e tene ete estes A 5 A 2 68322 cnet te 6 A 3 68000 Emulator Connection 7 Ded 8 9 IGE Adaptor Board Pet tede 10 7 ICE Adaptor Board Silkscreen 11 Aco ICE Reset AC nana or em emet 12 A 9 ICE Read Cycle AC A 13 A 10 ICE Write Cycle AC Timing uoa a o A 14 A 11 ICE Interrupt Acknowledge Cycle AC Timing A 15 A 12 IGE Bus Arbitration Timing A 15 Bet 1 6689322 2 B 2 DRAM Connection Petre ud ea etant n eni uv ate x dos B 3 B 3 DRAM SIMM Conne
21. DETAIL C 0 20 0 008 O 0 50 0002 lt 0 20 0 008 H Wee DETAIL C DATUM A t PLANE 5 010 0 004 MILLIMETERS 0 08 0 003 0 0522 REF lt lt 20 1 325 0 0522 0 0043 Dimensioning and tolerancing per ANSI 14 5 1982 Controlling dimension millimeter Datum plane is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line Datums and D to be determined at datum plane Dimensions 5 and V to be determined at seating plane Dimensions A and B do not include mold protrusion Allowable protrusion is 0 25 010 per side Dimensions A and B do include mold mismatch and are determined at datum plane Dimension D does not include dambar protrusion Allowable dambar protrusion shall be 0 08 003 total in excess of the D dimension at maximum material condition Dambar cannot be located on the lower radius or the foot Figure 15 2 160 Pin QFP Package Dimensions For More MES 822 ae BM M 2b oduct Go to www freescale com Freescale Semiconductor APPENDIX A IN CIRCUIT EMULATION INTERFACE This section describes an in circ
22. On This Product Go to www freescale com Freescale Semiconductor Ing ad Annn 5 4 CORE EXCEPTION HANDLING Exception processing is the activity performed by the core in preparation to execute a special routine for any condition that causes an exception In particular exception processing does not include the execution of the routine itself It is the transition from the normal processing of a program to the processing required for any special internal or external condition that preempts normal processing External conditions that cause exceptions are interrupts from external devices address errors and resets Internal conditions that cause exceptions are instructions address errors and tracing For example the trap trapv chk rte and div instructions can generate exceptions as part of their normal execution In addition illegal instructions and privilege violations cause exceptions Exception processing uses an exception vector table and an exception stack frame Exception processing occurs in four functional steps However all individual bus cycles associated with exception processing vector acquisition and stacking are not guaranteed to occur in the order in which they are described in this section Figure 5 5 illustrates a general flowchart for the steps taken by the core during exception processing SAVE INTERNAL COPY OF SR 501 80 NUMBER SAVE CONTENTS TO STA
23. 22 IDTACK 23 IBR _ AS_ RW IAVEC IUDS iLDS IBG IRESET IHALT NC RP32 NC did 10KQ RES10 Iw 2 IFCO 008 1000 009 1001 L7 2 D10 ID02 D11 ID03 012 1004 013 1905 014 1006 2 U32 D15 Dor 22V10 10 S0 81 IDREN OTHRGB A24 25 Figure 3 MC68000 Emulator Connection For On The Product Go to www freescale com Freescale Semiconductor wee Ue nv nuvo J41 1 68322 PGA 23x23 For More FS 135 133 132 131 130 128 127 126 125 124 122 121 120 118 117 116 115 114 113 111 110 109 108 106 105 104 104 156 155 154 152 151 150 148 147 MAO MA1 MA2 MA3 MA4 MAS MA6 8 9 10 MD1 MD2 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 PDO PD1 PD2 PD3 PD4 PDS PD6 PD7 CLK2 RESET 23 19 _20 IRQO IRQ1 DREQ SBSY STS VCLK FSYNC LSYNC SELECTIN STROBE AUTOFD INIT 18 160 7T 82 80 89 85 137 157 139 142 J41 1 68322 PGA 23x23 Figure A 4 PGA Connector 322 3322 USER oduct to www freescale com 146 145 141 143 140 BG EDTACK EMURST CSO CS1 CS2 CS3 CS4 CS5 CS6 CS7 RD WRL WRU RASO RAS1 RAS2 RAS3 RAS4 RASS CASO 51
24. MD15 MDO Memory Data Bus This signal connects to 16 bit bidirectional three stateable memory data bus The memory data bus is used to transfer byte and word sized data to and from DRAM 55 50 Row Address Strobe These output signals provide row address strobes for external DRAM RASx asserts when a memory reference occurs that is internally decoded for the DRAM bank s CAS1 CASO Column Address Strobe These output signals provide the column address strobe timing for the external DRAM The 51 signal asserts when a byte write operation occurs to the upper memory data bus MD15 MD8 CASO asserts when a byte write operation occurs to the lower memory data bus MD7 MD0 However both CAS1 and CASO assert for byte sized read operations and word sized read and write operations WE Write Enable This output signal asserts when an external DRAM access write cycle is initiated providing the write control for external DRAM Table 2 3 DRAM Address Multiplexer ROW COLUMN MEMORY ADDRESS ADDRESS ADDRESS DRAM SIZE x16 BITS 4 Mbit 1 Mbit 256 Kbit Mbit 1 Mbit 256 Kbit 4 Le 1 Mbit 256 Kbit A03 MA2 4 Mbit 1 Mbit 256 Kbit MA3 4 Mbit 1 Mbit 256 Kbit 4 4 Mbit 1 Mbit 256 Kbit 5 4 Mbit 1 Mbit 256 Kbit MA6 4 Mbit 1 Mbit 256 Kbit A08 MA7 4 Mbit 1 Mbit 256 Kbit A09 MA8 4 Mbit 1 Mbit 256 Kbit For More MES 822 ae BM oduct to www
25. MAP wires BLT2UB XD Expanded Source Destination bitBLT to Unbanded Bitmap PARAMETERS sm DESCRIPTION 0x26 Byte BLT2UB XD 0x00 Byte Reserved DA Long Word Destination physical bit address FW Word Destination frame width in bits FH Word Destination frame height in scanlines SA Long Word Unexpanded source physical bit address SW Word Unexpanded source frame warp in bits XOFF XMUL Two 4 bit Fields X offset and X multiplier in bits YOFF YMUL Two 4 bit Fields Y offset and Y multiplier in scanlines The BLT2UB XD graphic order transfers a low resolution source frame to a destination unbanded bitmap Before being combined with the destination the source frame is scaled to match the resolution of the destination bitmap This results in an intermediate expanded source bitmap The pixels of the expanded source and destination bit maps are combined as specified by the Boolean code set in the last SET BOOL SD order The SET UBMAP graphic order must previously define the destination bitmap warp The DA parameter specifies the physical bit address of the area or transfer frame within the destination unbanded bitmap The entire transfer frame must be within the bounds of the banded bitmap DA must point to the upper left corner of the transfer frame The warp of the destination unbanded bitmap is set by the SET UBMAP graphic order which allows the bitmap to be packed or unpacked
26. eese 4 12 Section 5 Interrupt and Exception Handling Internal Inter pls ue bo in 5 1 Hardware Interrupts 5 3 9 qr tides teretes 5 2 S ftware Intertupils s entera desde eddie pem 5 3 External Interrupts deae ed c eben ttai re p 5 4 Timer MOC C uoi ieiuna utet rb Ende aar D and e be Rem rbi apad 5 6 Core Exception Handling 2 0 00 00011 5 7 Processing Specific Exceptions 5 10 Multiple EXxceplioriS xcix rt 5 13 Exception Bus Cycles 5 14 Module Soft Reset Register 21 1 2 1 1 2 5 14 Section 6 System Integration Module Chip Select Registers And Banks 6 1 Synchronous and AsynchronouS Chip Select Access Timing 6 4 For Mare Un This Product Go to www freescale com Freescale Semiconductor TABLE OF CONTENTS Continued Paragraph Number Title Section 7 DRAM Controller 7 1 DRAM Registers and Banks 7 1 1 Base Address and Size Fields 7 1 2 ROM MOHB 7 1 2 1 Functional Description odo eis haste teta peas 7 1 2 2 Timing EXSmple 2 Fest sete feti 7 1 2 3 Address Demultiplexing Circuit
27. 1 CSR2 OOFFF022 RHLD RSET RACC 00 030 BASE ADDRESS 27 18 CSR3 OOFFF032 RHLD RSET OOFFF040 BASE ADDRESS 27 18 CSR4 OOFFF042 RHLD RSET O0FFF050 BASE ADDRESS A27 A18 CSR5 OOFFF052 RHLD RSET RACC 00 060 ADDRESS 27 18 CSR6 OOFFF062 RHLD RSET RACC O0FFF070 BASE ADDRESS 27 18 CSR7 00 072 RHLD RSET RACC 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 RESERVED Figure 6 1 Chip Select Register CSR7 CSRO For 11093259 MANDA Product Go to www freescale com Freescale Semiconductor Wy Sturn The upper word of the memory mapped CSR contains the bit fields that control timing characteristics for read and write cycles on the chip select bank By manipulating these fields different timing are created for read and write cycles on a bank by bank basis WHLD Write Hold Time CSx hold time from trailing edge of WRU and WRL for write operations WSET Write Setup Time CSx setup time before leading edge of WRU and WRL for write operations WACC Write Access Time Indicates the duration of the WRU and WRL signals during write operations RHLD Read Hold Time CSx hold time from falling edge of RD for read operations RSET Read Setup Time CSx setup time before leading edge of RD for read operations RACC Read Access Time Indicates the duration of the RD signal during read operations The chip select active tim
28. 330 015 00 osc 40 RESET A25 A1 RD 47KQ WAIT 5V IRQO d WRL IRQ1 CS7 CS0 5V 47KQ e CHIP SELECT ze Zako PM EDTACK 4 BR USE 22 7692 MHz BG SBSY HET po MC68322 RAS5 RASO FSYNC LSYNC 4 50 CAS1 lt CBSY lt CMD 4 DRAM ADDR 10 0 DRAM DATA 1015 90 VIDEO PARALLEL PORT CONTROL PD7 PDO PARALLEL DATA Figure B 1 MC68322 Connection B 2 CONFIGURING THE DRAM AND DRAM SIMM The DRAM can be mounted directly onto the printed circuit board The following design demonstrates a 512K memory option which is a minimal memory configuration for the MC68322 However additional memory can be connected to the MC68322 s DRAM controller Figure B 2 illustrates the DRAM connection For More ie ash M product Go to www freescale com Freescale Semiconductor rpg gt 256 16 MD15 MDO Figure B 2 DRAM Connection DRAM SIMM modules may be added to provide more memory which is necessary in some designs The DRAM SIMM module does not have to be buffered However using buffers to isolate the main memory from a memory module can improve design reliability and prevent field failure s Due to the unknown nature of the SIMM modules inserted into the design isolation resistors are helpful to reduce undershoot and other electrical problems resulting from driving a large capacitive load Figure
29. 110 00 120 00 130 00 140 00 150 8 7 6 5 4 3 2 SIZE BASE ADDRESS A27 A19 ROM zn MODE SIZE BASE ADDRESS 27 19 ROM MODE SIZE BASE ADDRESS A27 A19 ROM _ SIZE BASE ADDRESS A27 A19 ROM SIZE BASE ADDRESS A27 A19 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED Figure 7 1 DRAM Register DRAM5 DRAMO For Mort d dora MANDA Product Go to www freescale com 1 15 14 13 12 40 9 _ SIZE BASE ADDRESS A27 A19 MODE A27 1 DRAMO DRAM1 DRAM2 DRAM3 DRAM4 DRAM5 Freescale Semiconductor Because each DRAM register contains a size field each DRAM bank be individually programmed for a different size or disabled entirely The available sizes are either 512K 2M or 8M depending on the size field s encoding There are no limitations in the ordering of bank sizes Table 7 1 lists the size field encodings and the equivalent DRAM bank sizes Table 7 1 DRAM Size Options ENCODING DRAM BANK ORGANIZATION Disabled No Size 256 Kbit x 16 512K base address field contained in each DRAM register allows the DRAM banks to be individually located at any location in the 256 byte memory map The DRAM register base address field contains bits 27 19 of the corresponding DRAM bank s starting address T
30. Ax ADD Dn lt ea gt ADDX Source Destination X Destination ADDX Dy Dx ADDX Ay Source A Destination Destination AND lt gt AND Dn lt ea gt ASL ASR Destination Shifted by count Destination ASd Dx Dy ASd lt data gt Dy ASd lt ea gt If condition true then PC d Bcc label BCHG bit number of Destination 2 BCHG Dn lt ea gt bit number of Destination bit number of Destination BCHG lt data gt lt ea gt BCLR bit number of Destination 2 BCLR Dn lt ea gt 0 lt bit number gt of Destination BCLR lt data gt lt ea gt BKPT Run breakpoint acknowledge cycle BKPT lt data gt TRAP as illegal instruction PC d BRA lt label gt BSET bit number of Destination 2 BSET Dn lt ea gt 1 lt bit number of Destination BSET lt data gt lt ea gt SP 4 SP PC SP PC d PC BSR label BTST bit number of Destination 2 BTST lt gt BTST 4 lt data gt lt ea gt C If Dn lt 0 or Dn gt Source then TRAP CHK lt ea gt Dn CMP Destination Source CMP lt ea gt Dn D CHK LR ination ion cc CMPA Destination Source CMPA lt ea gt An CMPI Destination Immediate Data CMPI lt data gt lt ea gt Destination Source CMPM Ay Ax DBcc If condition false then Dn 1 DBcc Dn lt label gt If Dn z 1thenPC d DIVS Destination Source Destination DIV
31. C51 C52 C53 C54 C55 C56 C57 C58 C59 C5A C5B L C5C OPAC DEC 0 1uF m Mea cso 1 PER noer 22UF Figure A 5 Test Points For On This Product Go to www freescale com Freescale Semiconductor nin ull ciolieevis nv nave 0 156 DIAMETER THRU 0 20 040 100 1 80 320 39 J53 1 6 40 6 20 x lt 6 10 40 O O e oG 6 5 1 4 09 MNPRTU 9 17 e e Ut7 1180179 6 OOO oo O90 oooolj o o dc oo 9 470 900 gt oo T o 0 6 ooooj ob O Q oo o ooooj ob 09 5144 43 D l Fg D 3 40 Fg 2 5 22 4 0 40 3 30 7_ lt 3290 SQUARE 00000000000000000000000 a 2 Ve J51 SIDES OF PCB TYPE 2 PLCS 60000000000000000000000000000000 64 PIN DIP 0 30 O O O 0 6 O O O O 6 6 O 6 O
32. DX mod HW DX gt 0 or HW DX mod HW mod HW DX lt 0 DY mod DY gt 0 or HH DY mod mod DY lt 0 HDA HDY x HW HDX For On The Product Go to www freescale com Freescale Semiconductor AF Where DX and DY are the signed X and Y dimension values used in the calculation of DZ HH is the target halftone bitmap height HW is the target halftone bitmap width HRL HDX HDY and HDA are all unsigned values and their values should satisfy the following boundary conditions 0 lt HRL lt HW 0 lt HDX lt HW 0 lt lt 0 lt HDA lt HZ Where HZ is the total number of bits in the halftone bitmap Any 32 or 48 bit bit string specifier with a corresponding halftone specifier must not have a horizontal displacement that extends beyond either side of the destination bitmap The halftoning operation does not track the Y dimension displacement caused by wrapping around the sides of a bitmap Of course the same is true for the run lengths since no horizontal clipping is performed at the left or right edges of the destination bitmap for any graphic order Unlike the scanline table the halftone table requires no 0000 terminators The parsing of the halftone table tracks that of the scanline table reading both tables in parallel For 32 and 48 bit specifiers the MC68322 reads a specifier from each table and for 1
33. Figure 13 29 Halftone Destination Scanline Transfer to Banded Bitmap 180 Page For Mort 12 5858 On This broduct Go to www freescale com _ Freescale Semiconductor Inc MAT wires wee SL2F D Destination Only Scanline Transfer to Frame PARAMETERS EM DESCRIPTION Byte SL2F_D Opcode Byte Reserved Long Word Destination physical bit address Word Frame width in bits 28 of 32 bits Scanline table physical byte address word aligned The SL2F D graphic order causes the MC68322 to render a scanline table image to a frame The destination is manipulated as specified by the Boolean code last set by the SET BOOL D graphic order The destination frame warp is taken from the graphic order s FW parameter SLTA points to the most significant byte of the first bit string specifier in the table not to the 0000 header and DA refers to the pixel to which the displacement of the first bit string specifier is added not necessarily the first bit of the run Since the scanline table s bit string specifiers must be placed at word boundaries SLTA must be word aligned Related Graphic Orders SET BOOL D SCANLINE DESTINATION TABLE FRAME pw gt BITSTRING SPECIFIERS DA FIRST BOOL_D APPLIED TO FRAME Figure 13 30 Destination Scanline Transfer to Frame For 12 5858 On This broduct Go to www freescale com Freescale Semiconductor Inc wpe
34. For zi MANUS Product Go to www freescale com Freescale Semiconductor LIST OF ILLUSTRATIONS Figure Page Number Title Number Tt MG68322 Block Diagrami cee 1 3 1 2 Graphics Unit Data Flow Diagram 1 5 129 16 Map Un sad mi d ddr epi de b i edd 1 7 1 4 256M ARAS NUR 1 7 1 5 Memory Map Address Register 1 7 Bitmap sea tesla nas ae i tbe eR 1 9 1 7 Unpacked And Packed Bitmaps 3 ect tiae teen cenae der po 1 9 1 8 Duplex Laser Printer Paper Pallio epo dor 1 11 1 9 Example of a Duplex Printing Operation 1 12 2 1 Functional Signal Groups eter aee al od o iq p nordique eee 2 1 2 2 1 1 Phase Relationship 2 2 442211 2 4 3 1 000 Core Programming 3 3 2 4 14 cans 4 2 4 2 External Timing Diagram to Chip Selects Banks 4 2 4 3 External Timing Diagram to Chip Select Banks 4 3 4 4 Word and Byte Read Cycle Timing Diagram to DRAM
35. INTERFACE CMDISTS a DACK INTERFACE R W EAK EXTERNAL BUS MASTER INTERFACE BG Figure 2 1 Functional Signal Groups For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor wry Rav Table 2 1 Signal Summary THREE THREE STATED SIGNAL NAME MNEMONIC INPUT OUTPUT ACTIVE STATE ow owmz e I wm T bus wawa X wa ___ ____ _______ _ ______ 20 Write Low f o f o f o a f e i ________ m Sv m pemen Sm ww MES 822 aa M V b roduct Go to www freescale com SIGNAL Status Data High Impedance Power Input Video Clock Video Processor Wait DRAM Write Enable Write Enable Lower Write Enable Upper Freescale Semiconductor Inc wry wvoviip uvg Tab
36. If the instruction specifies a word or long word operation the core writes both upper and lower bytes simultaneously When the instruction specifies a byte operation the core uses the internal AO to determine which byte to write and then issues the data strobe required for that byte A transfer is initiated by asserting the address strobe AS and providing a valid internal function code and address The address is decoded by each module Once a transfer is initiated the core uses the timing and wait state characteristics for the active interface to pace the internal core bus cycle Using the wait state information of the selected module the core waits the specified number of cycles transfers data and then terminates the cycle by asserting the internal signal to the core The core in turn then terminates the internal core bus cycle within two clocks 54 57 All transfers on the internal core bus require the minimum access time of four clock cycles Figure 4 5 illustrates the write cycle flowchart and Figure 4 6 illustrates the word and byte write cycle timing diagram to chip selects 000 CORE BUS INTERFACE UNIT ADDRESS THE DEVICE 1 PLACE ADDRESS ON A27 A0 2 ASSERT AS MC68322 BUS ONLY 4 ASSERT RIW INPUT THE DATA 1 DECODE ADDRESS 2 ASSERT CHIP SELECT MC68322 BUS ONLY 00 3 ASSERT WRU AND WRL DEPENDING ON UDS AND LDS MC68322 BUS ONLY 4 ASSERT MULTIPLEXED ADDRESS ON MA10 MA0 DRAM ONLY
37. PRINTERCOMMAND O0FFF500 XXXXXXXX 00000000 PCOMR PRINTERSTATUS O0FFF502 XXXXXXXX 00000000 CCLKDIVISOR OOFFF504 0000000 00000000 TIMERINTERVAL HIGHBYTE 00 600 00000000 TIMER TIMER INTERVAL LOWWORD OOFFF602 00000000 00000000 REG TIMER COUNT HIGHBYTE OOFFF604 XXXXXXXX 00000000 TIMER COUNT LOWWORD OOFFF606 00000000 00000000 ENABLE OOFFF700 XXXXXXXX XXX00000 PVCIR BSY PGE BUD VUD ILA OOFFF702 XXXXXXXX X0000000 INTLEVEL 00 704 XXXXX000 ENABLE OOFFF710 XXXXXXXX RIER RBY DLF RDN RER OOFFF712 XXXXXXXX XXXX0000 INTLEVEL 00 714 XXXXX000 ENABLE OOFFF720 XXXXXXXX PCIER STR OOFFF722 XXXXXXXX INTLEVEL 00 724 XXXXX000 INER 7 XXXXXXXO INT INT OOFFF732 XXXXXXXX XXXXXXXO REG INTLEVEL 00 734 XXXXX000 For On this Product Freescale Semiconductor Inc drin Table 1 Register Set Continued
38. The FW and FH parameters define the area of the destination bitmap on which the operation is performed FW is the frame width in bits and at a maximum equals the quantity W x XMUL 1 where W is the width of the unexpanded source bitmap FH is the frame height in scanlines and at a maximum equals the quantity H x YMUL 1 where is the height of the unexpanded source bitmap Specifying FW and FH as defined above causes the entire expanded source image to be combined with the destination bitmap Specifying an FW and or FH value less than the values defined by the above equations causes only a portion of the expanded source frame to be applied to the destination When used in combination with XOFF and YOFF clipping can be affected at any or all extents of the expanded source bitmap The SA parameter defines the unexpanded source bitmap bit address It must point to the upper left corner of the bitmap The warp of the bitmap is set by the SW operand This value is added to SA to locate the beginning of each successive scanline Note that the source warp set by the SET SBMAP graphic order has no effect on this graphic order For Mort ON oduct to www freescale com Freescale Semiconductor Inc v XOFF XMUL parameter is divided into two fields The least significant four bits contain the XMUL field which specifies the factor used to scale the unexpanded source bitma
39. banks described 7 1 location 7 1 reset values 7 10 burst access page boundary crossing 7 10 burst accesses 7 10 burst cycles 7 1 bus DMA control of 8 8 bus transfers DMA 8 8 devices operation speed 7 5 pre charge 7 10 DMA accesses 7 1 DRAM control TS field encodings 7 5 000 Core accesses 7 6 7 9 fast page mode 7 1 fast page mode burst accesses 7 10 nibble mode 7 1 ANS Product Go to www freescale com Freescale Semiconductor registers described 7 1 DRAM control 7 5 reset 7 10 static column 7 1 transfers DMA data latch during 8 6 WE RAS and CAS during DRAM read 7 7 DRAM bus see memory data and address bus DRAM controller accesses burst 7 10 bus arbitration 7 9 acesses 7 6 banks location 7 2 devices 7 1 power up 7 10 read cycle 7 7 registers reset values 7 10 registers and banks base address and size fields 7 1 ROM mode 7 2 registers and banks 7 1 timing mode 7 5 timing modes 7 5 write cycles 7 8 DRAM controller 7 1 DRAM interface signals 2 7 DRMCR 7 5 duplex operation bottom to top B2T parameter 13 6 destination address DA during 13 6 duplex printing explanation 1 11 E 000 Core DMA accesses 7 1 exceptions address error 5 12 illegal 5 11 privileged violations 5 11 tracing 5 12 unimplemented 5 11 exceptions see also exceptions flush request DMA 8 3 illegal memory address access 5 3 status register during exception processing 5
40. hopper During the second pass paper travels from the duplex hopper and under the drum and another image is placed on the page After fusing the page is placed in the output hopper with the second pass image facing up To properly orient the two images on the page the second pass data must be sent to the printer in right to left and bottom to top order so that a 180 image rotation will occur FIRST PASS SECOND PASS FIRST PIXEL FIRST PIXEL SCANNED SCANNED ONTO PAGE ONTO PAGE H DRUM LASER SCAN DIRECTION gt t PAPER MOTION PAST DRUM PAPER MOTION PAST DRUM Figure 1 9 Example of a Duplex Printing Operation LASER SCAN DIRECTION 3 gt 1 12 MC68322 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor SECTION 2 SIGNAL DESCRIPTIONS This section contains brief descriptions of the MC68322 input and output signals as illustrated in the figure below PD7 PDO lt AQ5 Ni gt ADDRESS BUS SELECTIN STROBE DI5 D gt DATA BUS PARALLELPORT INIT RD INTERFACE ACK STET WRU _ MC68322 BUS WRL INTERFACE SELECT WAT PERROR IRQ1 IRQO FAULT TEST Cu SYSTEM RESET INTERFACE PVC FSYNC HI Z INTERFACE LSYNC gt MEMORY ADDRESS BUS VIDEO MC68322 PRINT lt 15 gt MEMORY DATA BUS RAS5 RASO CCLK 1 PRINTER wey WE COMMUNICATION __SBSY
41. included prior to each transfer The SW parameter is typically set to a non zero value when it references a source which is not packed in memory This is a common occurrence in bitmapped fonts stored in font cartridges Each scanline of a character in a font begins on a word boundary 0 mod 2 byte address Related Graphic Orders BLT2BB SD BLT2F SD BLT2UB SD BLT2BB SHD BLT2F SHD BLT2UB SHD SOURCE BITMAP WARP WASTED SPACE SOURCE BITMAP WIDTH Figure 13 25 Unpacked Source Bitmap For Mort ON oduct to www freescale com __Freescale Semiconductor wires SET_UBMAP Set Unbanded Bitmap Parameters PARAMETERS DESCRIPTION 0x09 Byte SET UBMAP 0x00 Byte Reserved DWU Word Destination unbanded bitmap warp in bits The SET graphic order specifies the structure of an unbanded bitmap The warp of the bitmap is provided and is used in all subsequent graphic orders that operate on an unbanded bitmap Transfers to frames and banded bit maps are not affected by the DWU value Related Graphic Orders BLT2UB D BLT2UB SD BLT2UB SHD SL2UB D SL2UB HD For Mort RSE ON ANA oduct Go to www freescale com Freescale Semiconductor Inc W _ SL2BB D Destination Only Scanline Transfer to Banded Bitmap PARAMETERS s DESCRIPTION Byte SL2
42. size DESCRIPTION Byte SL2F_HD Opcode Byte Reserved LongWord Destination physical bit address Word Halftone X remainder Word Halftone Y remainder LongWord Halftone physical address of the starting pixel 28 of 32 bits Companion halftone table physical byte address word aligned 28 of 32 bits Scanline table physical byte address word aligned The SL2UB_HD graphic order causes the MC68322 to render a scanline table image to an unbanded bitmap and apply a halftone bitmap in the process The destination and halftone pixels are combined as specified by the Boolean code last set by the SET BOOL HD graphic order The SET UBMAP graphic order must previously define the destination unbanded bitmap warp and the SET HTBMAP graphic order must do the same for the halftone bitmap dimensions Halftone tiled patterns are typically anchored to the page Thus the rendering of a scanline table may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where it is positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the initial destination address given in the graphic order Remember that the initial destination address is not where the first pixel is drawn it is the point to which the first bit string specifier s displacement is added HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines
43. 1 0 RESERVED Figure 5 3 Timer Register 00 600 The timer interval field specifies the number of 1x clocks between timer interrupts The timer count field provides the current 1x clock count value in case more precise timing is required The interval field must be initialized before a timer interrupt event is enabled in the timer interrupt event register TIER which is illustrated in Figure 5 4 OOFFF730 OOFFF732 OOFFF734 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Figure 5 4 Timer Interrupt Event Register The timer interval and count fields in the timer register consist of a high byte and low word First the high byte should be loaded followed by the low word which is the natural order of an core long word write access Loading the low word causes the new interval to be loaded into the timer counter The count field counts down to zero generates an interrupt and then reloads from the interval field The value read from the count field reflects the current state of the timer counter The count field should be read twice to determine the actual timer count The timer count will decrement between the read of the high byte and the low word portions of the count field which can cause the high byte to decrement For example if the timer counts down from 300 to 2 between reads then the software may incorrectly read the upper byte as and the lower word as for a total of 3FF For
44. 12 13 12 8 BitBLT and Scanline Order Execution 12 14 12 9 Location and Address Constraints 12 15 Section 13 Graphic Orders 13 1 Types of Graphic Orders coxa cuo tete pO rdi tud 13 1 13 1 1 e dt eb Cotidie 13 1 13 1 2 Program Flow Control eite ec oett 13 3 13 1 3 Bit Block ec bep ei ruv ios iy 13 3 13 1 4 Expanded Bit Block Transfer 13 3 13 1 5 Transfer 13 4 13 2 Sequence of the Display List 4 2 2 2 13 5 13 3 Graphic Order Addresses Oups 13 5 13 3 1 Physical vs Logical Address 13 6 For Mon zi MANUS Product Go to www freescale com Number 13 3 2 13 4 13 5 15 1 15 2 15 3 Freescale Semiconductor TABLE OF CONTENTS Continued Page Title Number Duplex Addresses 2 2 424244 24 24 2 2 13 6 Band Number and Band Faults 13 7 Graphic Order Descriptions 13 8 Section 14 Electrical and Thermal Characteristics Maximum Ratings ud eec esaet t Sheet eee eee 14 1 Thermal Char
45. 12 3 Bit String Specifier Formats The ID field identifies the type of bit string specifier The bit string specifiers are designed to be recognizable no matter what direction the scanline table is read from memory This is required to properly handle scanline graphic orders in a duplex banding environment where 0 and 180 pages are possible Thus the ID fields in the 32 and 48 bit bit string specifiers are duplicated to allow parsing of the scanline table in either direction The RL field indicates the number of pixels to be drawn horizontally during the scanline run The displacement fields indicate the number of horizontal and vertical pixels to skip before drawing a scanline The DX field indicates the signed horizontal movement along the X dimension of the bitmap The DY field indicates the unsigned vertical movement along the Y dimension of the bitmap The DZ field is the signed aggregate displacement based on a calculation of the preferred X and Y movements along with the destination warp Thus the warp of the target bitmap must be known before building a scanline table containing 48 bit bit string specifiers This calculation is DZ DY x DW DX where DW is the unsigned warp of the target destination bitmap Note that DY is signed for this calculation Table 12 2 lists the definitions for each field of the three types of bit string specifiers For On The Product Go to www freescale com Freescale Semiconduct
46. 2 5 lariat ee ua enone 2 7 2 6 b e dde 2 8 2 7 Printer Communication Interface 2 8 2 8 Print Engine Video Controller Interface 2 8 2 9 Parallel Port Interface eot te Gra Sa dane oe i eae hee eat 2 9 For zi MANUS Product Go to www freescale com Number 3 1 3 3 6 1 6 2 Freescale Semiconductor Inc TABLE OF CONTENTS Continued Page Title Number Section 3 The Core Programming Model 22 5762 iota setts 3 1 Data Types Addressing Modes 3 3 Instruction Set Summlry e ene neh eee 3 4 Section 4 Bus Operation EGDOO Core Read erunt met etie iq 4 1 ECODO Core Write 4 4 Interrupt Acknowledge Bus Cycle 0 4 6 eee cas A M EOD Dr DO Ea 4 8 External Bus uc aeria ene m 4 9 MC68322 Bus Arbitration 4 9 External Bus Master Read Cycle 4 10 External Bus Master Write Cycle 4 11 Illegal Address Interrupt
47. 21 Output 4 4 CS 4 Output 5 5 CS 5 Output 6 6 CS 6 Output 7 7 CS 7 Output 8 8 RAS 4 Output 9 9 RAS 5 Output 10 10 WRU Output 11 11 DACK Output 12 12 AS Output 13 13 DTACK Output 13 14 BG Output Buzzer 13 BR Input Interrupt 14 DREQ Input Interrupt 15 For 11093259 MANDA Product Go to www freescale com Freescale Semiconductor mire i 0 2 STATE DURING RESET The output pins are in the normal deasserted state during reset and the first bus cycles except for A 21 25 AS RAS 4 5 Pins A 22 25 may be used as inputs on systems that require 4M or less of ROM by using the input pin mode as described below D 3 REGISTERS The new registers in the table below control the alternate pin function REGISTER ADDRESS BITS R W DESCRIPTION ALTPIN SEL OOFFF910 16 R W Select Alternate Function For Each Pin ALTPIN DIR OOFFF912 4 R W Direction Control For A 22 25 0 1 ALTPIN IN OOFFF914 4 R Input Status For A 22 25 ALTPIN OUT OOFFF916 15 R W Output Control For Output Bits The following bits have been added to the existing external interrupt registers DREQ EXIR2 bits were added to the EXIRO registers and BR EXIR3 bits were added to the EXIR1 registers The new bits are
48. 26 Parallel Port Interface AC Timing For More MES BM M to www freescale com Freescale Semiconductor CAI PWR WHI UV ILUV 14 4 8 External Bus Master Timing w e s CL A NOTE Denotes that AS and BR are asynchronous inputs and are synchronized internally by MC68322 They require no setup or hold time to be recognized for proper operation However to guarantee recognition of an input at a certain edge of CLK2 the input must satisfy the hold requirement 4 lt Figure 14 27 External Bus Master Read Cycle AC Timing For On The Product Go to www freescale com Freescale Semiconductor Inc _ l norn WEA gt lt gt G gt lt RW D15 D0 Figure 14 29 External Bus Master Bus Arbitration AC Timing Figure 14 30 External Bus Master Multiple Cycle AC Timing For On The Product Go to www freescale com Freescale
49. 3 NEGATE INTERNAL DTACK AND RD STROBE START NEXT CYCLE 4 NEGATE 10 0 RAS AND CAS DRAM ONLY ACQUIRE THE DATA 1 LATCH DATA 2 NEGATE AS Figure 4 1 Read Cycle Flowchart M MEM o wi RD WRU and WRL lt gt lt gt lt WORD READ WORD WRITE SLOW READ NOTE UDS LDS and DTACK are internal signals only Figure 4 2 External Timing Diagram to Chip Selects Banks For More ie 22 RER n Go to www freescale com Freescale Semiconductor sella Spiess gt lt gt lt gt WORD READ BYTE READ SLOW BYTE READ NOTE AO UDS LDS and DTACK are internal signals only Figure 4 3 External Timing Diagram to Chip Select Banks 50 52 54 56 50 Ng Ng RW NE BS E E NN S pc B EM M MA10 MAO Row X COLUMN X E M S NH NB MD15 MDO M EM EM EN ir NOTE 005 LDS and DTACK are internal signals only Figure 4 4 Word and Byte Read Cycle Timing Diagram to DRAM For More FS 8322 UBER oM roduct Go to www freescale com Freescale Semiconductor 4 2 000 CORE WRITE CYCLE During a write cycle the core sends data to memory DRAM or EPROM an internal register or a peripheral device writing bytes of data in all cases
50. 7 DRAM Timing Mode 0 Read Cycle ROM Mode 0 START WAIT WAIT READ DATA WAIT READ DATA TL MA10 MAO COLUMNCYCLE1 CYCLE 1 COLUMNCYCLE2 CYCLE 2 RASS RASO CAS1 CASO 015 00 DATA VALID DATA VALID WE SINGLE CYCLE FAST PAGE CYCLE Figure 7 8 DRAM Timing Mode 1 Read Cycle ROM Mode 0 For More MES M JA roduct Go to www freescale com Freescale Semiconductor Qt START WAIT READ DATA WAIT READ DATA READ DATA START 10 0 COLUMN COLUMN RAS5 RASO CAS1 CASO T SINGLE CYCLE FAST PAGE CYCLE FAST PAGE CYCLE Figure 7 9 DRAM Timing Mode 2 Read Cycle ROM Mode 0 7 4 3 DRAM Write Cycles A DRAM write cycle begins in the same manner as a DRAM read cycle except that data to be written is placed on the DRAM data bus MD15 MD0O WE is asserted at the beginning of the cycle CAS1 and CASO are asserted according to the internal LDS and UDS signals The cycle ends by negating the RASx CAS1 CAS2 and WE It is important to note that the MC68322 implements early write cycles which means that the assertion of CAS1 and CAS2 strobes data into DRAM Figures 7 10 to 7 12 illustrate the DRAM write cycle timings for each of the three timing modes START WAIT WAIT WAIT WRITEDATA WRITEDATA START cu MA10 MAO Emm 1 ROW X COLUM
51. 7 4 Address Demultiplexing Example 7 1 2 4 OPERATIONAL EXAMPLE A typical MC68322 based system might be a 16 MHz design that uses 70 5 DRAMs To achieve maximum system performance in this case select DRAM timing mode 2 This system might also include 120ns font ROMs that could be attached to one of the DRAM channels using a circuit such as the one illustrated above Such an arrangement would minimize system cost by reducing the overall DRAM requirements If the ROM mode was not used the system would need to be slowed to timing mode 0 to accommodate these font ROMs This slowdown would still produce a functional system but overall performance would be hindered because this setup would not fully utilize the available bandwidth in the DRAMs Instead timing mode 2 should be selected for this system and the ROM mode should be activated for the DRAM channel supporting the font ROMs These actions will optimize system performance as well as support the DRAM based font ROMs that help reduce system costs For On The Product Go to www freescale com Freescale Semiconductor WVU 7 2 DRAM CONTROL REGISTER The DRAM control register DRMCR contains two fields DRAM timing select TS and DRAM refresh interval RIC Figure 7 5 illustrates this register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OOFFF162 REFRESH INTERVAL COUNT RIC 15 14 13 1211 10 9
52. 8 7 1 Normal Termination aD PD pU DERE 8 7 2 Bad Address Termination 8 7 3 Core Forced Termination For Mon zi MANUS Product Go to www freescale com Page Number Freescale Semiconductor TABLE OF CONTENTS Continued Paragraph Number Title Section 9 Parallel Port Interface 9 1 PPI Registers eels 9 1 1 Parallel Port Interface Register 9 1 2 Parallel Port Control Register 9 1 3 PPI Interrupt Event Register 33802 9 2 Hardware Handshaking 9 2 1 Compatibility Handshaking 9 2 2 EGP Handshaklng e tecta t one 9 2 2 1 Command Byte Detection 9 2 2 2 RLE us 9 2 3 Disabling Hardware Handshaking 9 3 Software Controlled 9 4 Digital Filtering rte ua 9 5 Error GyGIGS 9 6 Parallel Port Data Bus Latching 9 7 PPI on Sat tates 9 8 PPI Data Transfer Rate 1 coe Per Eee od
53. AF 12 8 bitBLT AND SCANLINE ORDER EXECUTION Table 12 3 lists the bitBLT and scanline transfer timings based on an MC68322 system running at 20 MHz with DRAM running at 3 2 1 2 bus cycles Table 12 3 bitBLT and Scanline Execution Times OPERANDS ORDERS TIME MS bITBLT EXECUTION TIME 32 x 32 2 254 24 25 200 05 Solid fill bITBLT EXECUTION TIME 30 x 50 nou uy 25 25 TOU D D D D D Solid fill bITBLT EXECUTION TIME 100 x 100 0 E 200 Solid fill 0 SCANLINE EXECUTION TIME 30 x 50 70 05 195 90 For On This Product Go to www freescale com Freescale Semiconductor Graphic Operations 12 9 LOCATION AND ADDRESS CONSTRAINTS Display lists scanline tables and halftone tables must reside in DRAM space because the graphics unit cannot access chip select space The graphics unit can however fetch instructions from any of the MC68322 s six DRAM channels and from one channel to another if two channels define a continuous region of memory Keep in mind though that due to its internal prefetch queues the graphics unit must be able to read eight words beyond every display list scanline table and halftone table If this rule is broken an RGP error interrupt event could occur and cause the graphics unit to shut down The addressin
54. Byte BLT2F_SD Opcode Byte Reserved Long Word Destination physical bit address Word Frame width in bits Word Frame height in scanlines LongWord Source physical bit address The BLT2F_SD graphic order causes the MC68322 to bitBLT a source frame to a destination frame The source and destination pixels are combined as specified by the current BOOL_SD Boolean code The destination bitmap warp is taken to be the FW specified in the BLT2F_SD graphic order FW is also assumed to be the source frame warp unless a non zero source bitmap warp was previously defined by the SET_SBMAP graphic order in which case the latter is used The DA and SA parameters must point to the upper left corners of their respective frames Related Graphic Orders SET BOOL SD SET SBMAP SOURCE BITMAP DESTINATION FRAME BOOL SD USED TO COMBINE FRAMES Figure 13 14 Source Destination to Frame For Mort 166322 On This broduct Go to www freescale com Freescale Semiconductor Inc vwiuvis wits BLT2F SHD Source Halftone Destination bitBLT to Frame Byte BLT2F SHD Opcode Byte Reserved Long Word Destination physical bit address Word Frame width in bits Word Frame height in scanlines Long Word Source physical bit address Word Halftone X remainder Word Halftone Y remainder Long Word Halftone physical bit address of the starting pixel The BLT2F SHD graphi
55. DA must point to the upper left corner of the transfer frame when the B2T flag is clear and to the lower left corner of the transfer frame when B2T is set The warp of the destination banded bitmap is set by the SET BBMAP graphic order which allows the bitmap to be packed or unpacked When a band fault is detected the MC68322 rewrites the graphic order to update some of its parameters The BAND number is incremented or decremented when the B2T flag is set DA is repositioned to the starting pixel of the respective frame to be processed in the next band and FH is written back with the number of remaining scanlines in the destination frame Related Graphic Orders SET BOOL D SET BBMAP For Mort ON oduct to www freescale com Ereescale Semiconductor MAT DESTINATION BANDED BITMAP DWB BOOL_D APPLIED TO FRAME gt Figure 13 3 Destination bitBLT to Banded Bitmap 0 DESTINATION BANDED BITMAP FW lt EOBPA BOOL_D APPLIED TO FRAME lt gt DWB Figure 13 4 Destination bitBLT to Banded Bitmap 180 Page For Mort 160322 On This Product Go to www freescale com Freescale Semiconductor Inc vwiuvis Ji BLT2BB SD Source Destination bitBLT to Banded Bitmap PARAMETERS DESCRIPTION Byte BLT2BB SD Byte Band number when
56. DMA channel to stop in an indeterminate condition The RGP bit then returns the RGP to its idle state and the PVC bit returns the print engine video controller to its idle state The PVC bit can be used in the event that the PVC has an address error or if an underrun condition Occurs For On The Product Go to www freescale com Freescale Semiconductor SECTION 6 SYSTEM INTEGRATION MODULE The system integration module SIM provides the ROM PROM and peripheral chip selects It contains eight programmable chip select banks to decode the address and supply internal DTACK to the core after the appropriate number of wait states 6 1 CHIP SELECT REGISTERS AND BANKS The MC68322 contains eight noncontiguous memory mapped chip select registers CSR7 CSRO each corresponding to a variably sized chip select bank CSB7 CSBO in memory Each chip select register CSR indicates the corresponding chip select bank s location size and timing for read and write accesses such as data setup hold and recovery time Only the core or an external bus master can access the CSRs as word or long word sized registers Figure 6 1 illustrates the eight chip select registers 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 ADDRESS 27 18 CSRO 00 002 RHLD RSET RACC 00 010 ADDRESS 27 18 OOFFF012 RHLD RSET OOFFF020 BASE ADDRESS 27
57. Information Development team at 512 891 8593 Title of Manual QIN 69 24 20 107 Did the information this document appear to be organized a logical manner Was the level of writing appropriate for you as a user of this Freescale product Were the illustrations and graphics clear and easy to understand Some information such as signal summaries may have been duplicated in other sections for the purpose of making it easier for you to use Did you find it useful Did any of the technical information assume too much prerequisite knowledge If you answered yes to 5 do you need more task oriented information Were there enough example applications in the manual The Information Development team is considering the placement of documentation on CD ROM in the future Does your computer have a CD player What information should we add to the next version of this document 10 What information should we delete from the next version of this document 11 Was there technical information in this document that you have a question about Explain Thank you for your comments They will be used to improve this and other Freescale customer documentation Name Title Company Address City State Zip Country Email Address Phone Number For More Information On This Product Go to www freescale com Freescale Semiconductor TABLE OF CONTENTS Paragraph Page Number Title Number S
58. Semiconductor AF Both HDX and HRL are unsigned values but their values should satisfy the following boundary conditions 0 lt HRL lt HW 0 lt HDX lt HW The Y displacement found in the 32 bit bit string specifier DY field is automatically handled by the 68322 and has no corresponding field in the companion halftone specifier HRL is required for 180 pages since the graphics unit uses this offset to internally render scanline runs from left to right As illustrated in Figure 12 7 the corresponding halftone specifier for the 48 bit bit string specifier is 80 bits long and contains four fields halftone vertical movement HDY halftone horizontal movement HDX halftone run length HRL and halftone physical starting address HDA BYTE ADDRESS WORD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 5 HRL Run Length unsigned HDX X Dimension Displacement Horizontal unsigned HDY Y Dimension Displacement Vertical unsigned HDA Halftone Starting Address Displacement unsigned Figure 12 7 48 Bit Halftone Specifier Format The preferred horizontal and vertical displacements used in the original calculation of the bit string s DZ field are required to generate the parameters of the companion halftone specifier The four parameters for the 48 bit companion halftone specifier are defined as follows HRL RL mod HW HDX
59. Vit 9 5 ERROR CYCLES An example of an error cycle is when the user takes the printer off line a paper jam occurs or the printer runs out of paper When any of these or other events occur the printer runs an error cycle to alert the host of a change in the operational status of the printer An error cycle consists of asserting the BUSY signal and changing the states of SELECT PERROR and or FAULT to reflect the error condition This is done by manipulating the ERC bit in the PPCR which in turn triggers the PPI to set or clear bits in the PIER In compatibility mode the software sets ERC to notify the PPI when an error cycle occurs This causes the PPI to immediately set the BSY1 bit in the PIER After 1 us the software can set or clear the SEL PER or FLT bits in the PPIR to indicate the error condition After the error condition is cleared the software returns the SEL PRR and FLT to their normal negated state After 1 us the software clears ERC and the handshake logic concludes the cycle by generating an ACK pulse and clearing BSY1 If ERC is set and then STROBE is received from the host then the handshake logic performs the data transfer and data is still latched but no acknowledge is generated until ERC is cleared In other words the ERC bit prevents the handshake logic from generating an ACK pulse and clearing BSY1 Instead ACK1 and BSY1 remain set in the PPIR and the transfer cycle is extended As long as ERC
60. When B2T is clear YOFF is defined from the top edge of the source bitmap When B2T is set YOFF is defined from the bottom edge YOFF ranges from 0 YMUL If YOFF is zero no clipping occurs at the top or bottom extent but if it is non zero YOFF number of scanlines at the top or bottom edge of the expanded bitmap are skipped and the next scanline is the first one transferred to the destination bitmap Halftone tiled patterns are typically anchored to the page Thus a bitBLT may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where itis positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the upper left or lower left when the B2T flag is set corners of the source and destination frames HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the bottom edge or top edge when the B2T flag is set For Mort ON oduct to www freescale com Freescale Semiconductor wires HXR must be the following ranges 1 lt lt HW 1 lt lt HH where HW the width and height of the halftone bitmap respectively For example when the B2T flag is clear if the starting pixel in the halftone bitmap is determined to be at the upper le
61. When polling status bits in the PIER report the logic level at each parallel port input pin and control bits allow separate and direct control of each of the output pins The host inputs are always synchronized to the internally generated CLK1 signal to prevent metastable events from reaching the microprocessor This results in a maximum of one CLK1 period of delay before an external event appears in the PIER The SELECTIN INIT AUTOFD and STROBE signals can also be digitally filtered to improve noise immunity Digital filtering adds another CLK1 period of delay before level changes on these signals are indicated in the PIER 9 4 DIGITAL FILTERING The MC68322 contains digital filter circuitry on host control signal inputs SELECTIN STROBE AUTOFD and INIT to improve noise immunity and make the PPI more impervious to inductive switching noise Digital filtering can be enabled regardless of whether hardware handshaking is enabled or disabled When digital filtering is disabled the host control signals are synchronized to the internally generated CLK1 signal to prevent metastable events from reaching the internal logic of the MC68322 However the synchronization logic does not prevent glitches on the host control signals from reaching the PPPs internal logic and causing spurious events When digital filtering is enabled the host control signals are first synchronized and then passed through individual digital filters The digital filter samples
62. a data received interrupt event setting the DRD bit in the PIER DMA and interrupt operation is the same as described for compatibility handshaking mode Two additional interrupts events can be posted by the PPI when an ECP handshake mode is programmed command received and invalid termination setting the CRD and or IVD bits in the PIER CRD is posted when a command byte is received from the host and an IVD is posted when SELECTIN transitions illegally in the middle of a handshake sequence that is an invalid termination interrupt is posted if SELECTIN is low when STROBE is low or BUSY is high Such an event can be caused by the user changing a switch box ora parallel cable coming loose An invalid termination interrupt event should be treated as an immediate termination and the PPI should be returned to compatibility mode operation Figure 9 6 illustrates the ECP mode timing STROBE BUSY LATCH DATA READ DATA REQUEST INTERRUPT MAKE BUSY PULSE Figure 9 6 ECP Mode Timing Diagram 9 2 2 1 COMMAND BYTE DETECTION When ECP is enabled MODE 102 or 112 the PPI monitors the AUTOFD level that is latched into the PPIR s CMD bit to detect and intercept command bytes If CMD is clear the PPI interprets the data as a command byte and examines the most significant bit to interpret the byte If PD7 0 the command byte is a run length count and if itis 1 the command byte is a channel address The action taken with a channel add
63. address this state the PVC only responds to a PVC soft reset that is required to return the PVC to normal operation For On The Product Go to www freescale com Freescale Semiconductor nyny Gwe 10 1 5 Printer Communication Interrupt Event Register The printer communication interrupt event register PCIER indicates when a serial command has been sent or a serial status has been received OOFFF720 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED 00 722 00 724 Figure 10 5 Printer Communication Interrupt Event Register Note The PCIER is located in the interrupt register portion of the memory map and therefore is not necessarily located contiguously with the other print engine interface registers The command sent CMS bit indicates that the PCOMR s printer command field has been written and that the 8 bits of command data have been the print engine This interrupt event bit notifies the core that the command has been sent The status receive STR bit indicates that a status received interrupt event is active This occurs when the interface receives one byte of status data and the SBSY pin is deactivated STR is set when the SBSY pin is inactive to prevent a command operation from occurring before the print engine is ready to receive it 10 2 PRINTER COMMUNICATION PROTOCOL The print engine i
64. affected when rendering a page from bottom to top since scanline and halftone tables must be executed in reverse order when the B2T flag is set DA which normally gives the starting position for the scanline table must instead give the address of the pixel just beyond the last run in the scanline table The scanline table address which normally points to the most significant byte of the first bit string specifier in the table must instead point to the most significant byte of the last word In addition if a halftone is involved HA HXR and HYR must be provided with respect to the same pixel at the end of the image and halftone table address must point to the most significant byte of the last word in the halftone companion table Note in contrast to the order in which the print engine video controller reads an image 7 from memory When the B2T bit is set in the PCB control register the PVC reads memory in a bottom to top right to left order and in doing so produces an image that appears rotated 180 Unbanded and frame bitmap operations are always rendered in top to bottom order by the graphics unit independent of the value of the B2T flag Notice that for full page duplex applications page images can always be rendered top to bottom and then printed 0 or 180 when rotated by the PVC The B2T flag is important for banded duplex applications because it allows the bands to be rendered in the reverse order as needed for delivery to the
65. all cases If the instruction specifies a word or long word operation the core reads both upper and lower bytes simultaneously When the instruction specifies a byte operation the core uses the internal AO bit to determine which byte to read Once the data is received the core correctly positions the byte internally Figure 4 1 illustrates a word and byte sized read cycle flowchart Figure 4 2 illustrates the internal word read cycle timing diagram to chip selects Figure 4 3 illustrates the internal byte and word sized read cycle timing diagram to chip selects while Figure 4 4 illustrates the internal byte and word sized read cycle timing diagram to DRAM 7 Note AS asserts for 68322 chip select bus operations only For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor uil 000 BUS INTERFACE UNIT ADDRESS THE DEVICE 1 PLACE ADDRESS ON 27 0 2 ASSERT AS MC68322 BUS ONLY 4 ASSERT RIW INPUT THE DATA 1 DECODE ADDRESS 2 ASSERT CHIP SELECT MC68322 BUS ONLY 3 ASSERT RD MC68322 BUS ONLY 4 ASSERT MULTIPLEXED ADDRESS ON 10 0 DRAM ONLY 5 ASSERT RAS AND CAS DRAM ONLY 6 READ DATA FROM SOURCE 7 PLACE DATA ON INTERNAL 015 00 8 ASSERT INTERNAL DTACK 9 ASSERT WAIT TO STALL EXTERNAL MC68322 BUS ACCESS OPTIONAL TERMINATE THE CYCLE 1 REMOVE DATA FROM INTERNAL 015 00 _ 2 NEGATE RD MC68322 BUS ONLY
66. amount of toner used and the quality of the printed page when the SmartToner feature is enabled SLC and SRC SmartToner Left and Right Edge Control These fields are used to select which dot the halftone pattern is applied to on the left and right edges of a character If the halftone pattern starts and ends on the first dot then the character will appear more jagged than if it starts and ends on the second or third dot For example if the halftone pattern starts and ends on the second dot then the character will have a one dot wide border on the left and right sides with the halftone pattern applied in between Table 10 1 SLC and SRC Encodings ENCODING HALFTONE PATTERN PLE PLL Edge This bit is set to clock on both edges and clear to clock on rising edge only PLD PLL Divisor This field controls the PLL video clock prescaler PLD value of 00 01 10 or 11 causes the VCLK input to prescale by one two three or four before clocking the 8x PLL For On The Product Go to www freescale com Freescale Semiconductor wT VDP VIDEO Polarity Control Set if VIDEO is active high clear if active low BDP Border Polarity Control Set to drive low logic level in a nonprinting area clear to drive high PRP PRINT Polarity Control Set if PRINT is active high clear if active low FSP FSYNC Polarity Control Set if FSYNC is active high clear i
67. and right to left direction SME SmartToner Enable This bit is used to reduce the amount of toner the printer uses When it is enabled a halftone pattern is applied to the video data sent to the print engine The print image in memory is not affected The SME bit is double buffered and can be set or cleared for a specific page For On This Product Go to www freescale com Freescale Semiconductor Note It is not recommended that you change the SmartToner options in the 7 SLC SRC and SDN bits while printing a The page image bit address fields hold the starting address of the band image to be printed This address is a bit address and points to the first bit of data to be transmitted to the print engine Loading the page image bit address fields is also the stimulus that starts the PVC and initiates a print operation The values of all other PCB registers must be set before the page image bit address register is loaded 10 1 4 PVC Interrupt Event Register The PVC interrupt event register PVCIR contains five bits that indicate PVC interrupts events two that report normal events band begin and page end and three that report errors video under band under and PVC error A PVC error interrupt event results from an illegal address or out of range address If an error is detected by the PVC during the processing of the PCB register set i
68. and to the lower left corner of the transfer frame when B2T is set The warp of the destination banded bitmap is set by the SET_BBMAP graphic order which allows the bitmap to be packed or unpacked The FW and FH parameters define the area of the destination bitmap on which the operation is performed FW is the frame width in bits and at a maximum equals the quantity W x XMUL 1 where W is the width of the unexpanded source bitmap FH is the frame height in scanlines and at a maximum equals the quantity H x YMUL 1 where H is the height of the unexpanded source bitmap Specifying FW and FH as defined above causes the entire expanded source image to be combined with the destination bitmap Specifying an FW and or FH value less than the values defined by the above equations causes only a portion of the expanded source frame to be applied to the destination When used in combination with XOFF and YOFF clipping can be affected at any or all extents of the expanded source bitmap For Mort ON oduct to www freescale com __Freescale Semiconductor wires The SA parameter defines the unexpanded source bitmap bit address It must point to the upper left corner of the bitmap when the B2T flag is clear and to the lower left corner of the bitmap when the B2T flag is set The warp of the unexpanded bitmap is set by the SW parameter This value is added to SA to locate the beg
69. and two control scanline transfers to banded bit maps Each scanline graphic order specifies a pointer to a scanline table The graphics unit executes the whole scanline table before continuing to execute the rest of the graphic orders in the display list As with the bitBLT graphic orders the scanline graphic orders rely on certain parameters being previously set by initialization graphic orders For Mort farsi Shon On This Product Go to www freescale com Freescale Semiconductor uvv 13 2 SEQUENCE OF THE DISPLAY LIST The following is an example of a typical display list illustrating how the initialization graphic orders work with the bitBLT and scanline graphic orders SET_UBMAP Set parameters for rendering a full page into an unbanded bitmap SET_BOOL_D and BLT2UB_D Set the destination only Boolean code to draw in white and clear the entire page SET_SBMAP Set up for transfer from a font cartridge of a bit mapped font SET_BOOL_SD Draw the following characters in black BLT2UB_SD BLT2UB_SD and Place three characters on the page BLT2UB_SD SET_HTBMAP Identify a light gray repeating halftone pattern SET_BOOL_HD Identify a light gray repeating halftone pattern SL2UB HD Apply the halftone gray pattern during an upcoming transfer STOP Render an entire scanline table image in light gray 13 3 GRAPHIC ORDER ADDRESSES In the following graphic order descriptions operand lengths for a
70. as active low signals If this interface is not correct for the specific print engine the must be written to define a different interface If the PVCCR s VCS bit changes then the PVC will need to be soft reset During a PVC soft reset interrupt event no PVC registers are affected Any pending print operation is cleared and the next print operation is assumed to start at the beginning of a page Any pending interrupts remain pending A PVC reset interrupt event only occurs after the conclusion of the PVC s on going memory cycle 10 5 PVC VIDEO DATA TIMING The following timing diagram illustrates the relationship between the video data and the assertion of the LSYNC signal when the horizontal margin is set to zero LSYNC VIDEO N 5ns MIN 2ns MIN 20ns MAX There are many other variable associated with the behavior of the PVC The above timing diagram corresponds to a system configuration in the following manner For On This Product Go to www freescale com Freescale Semiconductor EIQ 10 5 1 1X Video Clock PVCCR Bit 0 0 If the PLL is used then video data will be clocked out by an effective video clock that is generated internal to the MC68322 Recognition of the LSYNC signal and the subsequent output of video data is relative to this internal clock since it is located outside the chip For applications that use an external ASIC to p
71. bit and long word 32 bit operations The second set of seven registers A0 A6 and the user stack pointer A7 USP can be used as software stack pointers and base address registers In addition the address registers can be used for word and long word operations However all 16 registers can be used as index registers The condition code register provides information on integer overflow zeros negatives carries and extends It is contained in the low order byte of the status register The supervisor mode provides access to two supplementary registers status register high order byte and supervisor stack pointer A7 SSP The status register has access to the condition codes but also includes the interrupt mask in the high order byte with eight levels of interrupts available It also indicates whether the core is in trace or supervisor mode For On This Product Go to www freescale com Freescale Semiconductor wus 3 2 DATA TYPES AND ADDRESSING MODES The core supports the basic data formats of the M68000 Family The instruction set supports operations on other data formats such as memory addresses The operand data formats supported by the core are the standard twos complement data formats defined in the M68000 Family architecture Registers memory or instructions themselves can contain integer unit operands The operand size for each instruction is either explicitly encoded in the instruct
72. code and is enabled with a size of 8M on power up The programmable parameters should provide setup and hold times for data to the core The read data is latched on the rising edge of the RD signal for any cycle with RHLD different than zero If RHLD is equal to zero the read data must be set up by the rising edge of the CSx signal that negates half of CLK1 before the RD signal On power up CSRO s WSET and RSET fields are also set to zero and the write and read ACC and HLD fields will be at their maximum Be aware that the software must program the chip select parameters for banks 7 1 before using them A chip select bank can be individually located anywhere in the 256M range of the memory map and can overlap with DRAM or other chip select banks In case of an address overlap all memory mapped registers have priority over chip select banks Likewise chip select banks have priority over DRAM banks and lower numbered chip select banks have priority over higher numbered chip select banks For example CSBO has a higher priority than CSB7 There two additional timing registers accessed by the core chip select DMA timing register and chip select recovery register Figure 6 2 illustrates these two registers 12 11 10 9 8 7 6 5 4 3 2 1 0 OOFFFO80 RHLD RSET RACC CSDTR 00 082 RESERVED 1 RECOVERY SELECT CSRR 10 9 8 7 6 5 4 3 2 1 0 em 6 2 DMA Timing and Recovery Registers The chip select DMA
73. control REGISTER ADDRESS DESCRIPTION BUZZER INT OOFFF608 Buzzer Interval BUZZER ENB OOFFF60A Buzzer Enable D 4 INPUT PIN MODE For A 22 25 to be programmed as input pins they must be three stated on power up to prevent the processor from driving them during the initial bus cycles which could cause bus contention on these lines To accommodate this condition A 22 25 will power up in a three state mode when a special state of the HI Z and TEST pins exists The normal functions for BR and DREQ will also be disabled in input pin mode ALTPIN SEL register bits 14 15 are set The table below shows the modes for these pins 1 2 5 FUNCTION 0 0 Three State All Outputs 0 1 Input Pin Mode A 22 25 Three Stated ALTPIN SEL Register Bits 0 3 14 15 1 1 0 Normal Mode A 22 25 Enabled ALTPIN SEL Register Bits 0 15 0 1 1 Special Test Mode Do Not Use D 5 BUZZER The BG output pin now has a buzzer control function which consists of an 8 bit interval control register a 1 bit enable register and a 16 bit free running counter The eight bits in the BUZZER INT register control the value to be loaded into the upper byte of the 16 bit counter after it reaches a count of zero The lower byte will always be loaded with FF The enable bit in the BUZZER ENB register causes the output from the BG pin to toggle every time the counter reaches zero The buzzer function driv
74. converted to a physical bit address by adding the PSUBL value set by the SET BBMAP graphic order The start of the transfer frame must be within the bounds of the banded bitmap but the end of the transfer frame may extend past the end of the bitmap DA must point to the upper left corner of the transfer frame when the B2T flag is clear and to the lower left corner of the transfer frame when B2T is set The warp of the destination banded bitmap is set by the SET BBMAP graphic order which allows the bitmap to be packed or unpacked The FW and FH parameters define the area of the destination bitmap on which the operation is performed FW is the frame width in bits and at a maximum equals the quantity W x XMUL 1 where W is the width of the unexpanded source bitmap FH is the frame height in scanlines and at a maximum equals the quantity H x YMUL 1 where is the height of the unexpanded source bitmap Specifying FW and FH as defined above causes the entire expanded source image to be combined with the destination bitmap Specifying an FW and or FH value less than the values defined by the above equations causes only a portion of the expanded source frame to be applied to the destination When used in combination with XOFF and YOFF clipping can be affected at any or all extents of the expanded source bitmap The SA parameter defines the unexpanded source bitmap bit address It must point to the upper left corner of the bitmap when the B2T flag i
75. displacements or scanline runs are required The larger formats allow any pixel in a bitmap to be reached with a single specifier Three bit string specifiers are supported 16 Bit Conditionally moves to the next scanline goes a short distance left or right from there and then draws a line that is a maximum of 63 bits long e 32 Bit Moves vertically up to three scanlines goes a large distance left or right from there and then draws a line that is a maximum of 4 095 bits long 48 Bit Moves a very large distance in both X and Y dimensions and then draws a line that is a maximum of 16 383 bits long All bit string specifiers are multiples of 16 bits and must always be located on word memory boundaries 0 mod 2 byte addresses Each bit string specifier consists of an ID field an unsigned run length RL field and a signed displacement DX DY or DZ field Figure 12 3 illustrates the three types of bit string specifier formats For On This Product Go to www freescale com Freescale Semiconductor AF BYTE ADDRESS OF WORD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 BIT SPECIFIER 0 32 BIT SPECIFIER 2 0 2 48 BIT SPECIFIER 4 NOTES RL Run Length unsigned DX X Dimension Displacement Horizontal signed DY Y Dimension Displacement Vertical unsigned DZ X and Y Dimension Displacement Horizontal and Vertical signed Figure
76. each scanline And again the VCLK source must be a free running clock On reset the print engine interface is programmed for synchronous operation If you want asynchronous operation with the PLL the PVCCR s VCS bit must be set After changing the VCS bit a PVC reset interrupt event must be posted by setting the PVC bit in the MSRR This will reset the video state machines to a known state The VCS bit should be changed only between pages when the video state machines are inactive 10 3 2 Command Operation Commands are sent to the print engine based on CCLK Writing another command to the PCOMR printer command field before one is finished should be avoided because it will corrupt the data The PCOMR should be properly programmed to choose between the command and status modes SBSY and STS which are used during status operations should not be asserted during a command operation 10 3 2 1 CCLK SUPPLIED BY MC68322 In this mode a write to the PCOMR s printer command field makes CBSY active CBSY completely brackets a command transmission by providing a setup and hold of one half CCLK period each This allows sufficient time for the print engine to detect the impending command byte and prepare its internal logic Setting the PCOMR s CRC bit allows the MC68322 to supply CCLK The value of the PCOMR s CCLK divisor field should be programmed to provide sufficient setup and hold time for the command data with respect to the rising edge of th
77. eto emt re tete 14 9 14 12 Wite ACCESS L2 1 9 le eua oco nd iru on 14 9 14 13 Wite Access 1 2 1 9 Lael aeneo EP NEU E te mds 14 10 14 14 Witte Access 4 41 23 Uno UOCE MERERI eg 14 10 14 15 DMA Read Cycle AC Timing 8840 14 11 14 16 DMA Write Cycle AC 14 11 14 17 DRAM Read Cycle AC 9 14 12 14 18 DRAM Write Cycle ues etico tee eee o en ipe ee een 14 12 14 19 DMA Request Acknowledge AC Timing 14 13 14 20 Print Engine Interface Input AC Timing 14 15 14 21 Print Engine Interface Output AC Timing 14 15 14 22 Video Clock AC Timing 88000 14 15 14 235 PVCAG TIMING eta e aM pee ee 14 16 14 24 Print Engine Interface AC Timing 2 14 16 14 25 Interrupt Interface AC Timing 2 1 eene 14 16 14 26 Parallel Port Interface AC Timing 2 4 14 17 For MANUS Product Go to www freescale com Freescale Semiconductor LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number 14 27 External Bus Master Read Cycle AC Timing 14 18 14 28 External Bus Master Write Cycle AC Timing
78. exception is being processed and the state of the core prior to the exception Figure 5 6 illustrates the general form of the exception stack frame SP STATUS REGISTER PROGRAM COUNTER Figure 5 6 General Form of an Exception Stack Frame The last step initiates execution of the exception routine The new internal program counter value is fetched from the exception vector The core then resumes instruction execution The instruction at the address in the exception vector is fetched and normal instruction decoding and execution is started The memory map for exception vectors is listed in Table 5 3 The vector table is 512 words long 1 024 bytes starting at address 0 decimal and proceeding through address 1 023 decimal The vector table provides 255 unique vectors some of which are reserved for trap and other system function vectors Of the 255 192 are reserved for user interrupt vectors However the first 64 entries are not protected so user interrupt vectors may overlap at the discretion of the systems designer Note All interrupt exceptions on the MC68322 are autovectored See Section 5 4 2 2 Interrupt Exceptions for more details For On The Product Go to www freescale com Freescale Semiconductor Ing and Exception Handling Table 5 3 Exception Vector Assignments FSET SP
79. executed for the next band Since the hardware automatically updates graphic orders that generate band faults graphic orders that span multiple bands execute without any software intervention Once a graphic order has been updated after a band fault the execution of the display list continues with the next graphic order in the list For On This Product Go to www freescale com Freescale Semiconductor SECTION 12 GRAPHIC OPERATIONS The MC68322 s graphics unit comprised of the print engine interface and the RISC graphics processor operates on a display list which is a collection of graphic orders A graphic order is a special instruction or command that directs the MC68322 to perform a discrete function such as setting internal environment registers or executing graphic operand transfers source to destination bit maps The MC68322 supports two types of transfers bit block and scanline 12 1 TYPES OF BITMAPS The basic element of a graphic operand is the bitmap As described in Section 1 Introduction a bitmap is a two dimensional array composed of scanlines each row in the array and pixels the junction of a scanline and column in the array The width of the bitmap X dimension is the number of pixels in the scanline and the height of the bitmap Y dimension is the number of scanlines Graphic orders use six types of bit maps Banded A banded bitmap has a warp associated with it that defines the X d
80. for responding to channel addresses If MODE is reprogrammed when decompression is occurring when the RLD bit is set the decompression continues unhindered to completion The RST bit can be set to immediately abort decompression DFE Digital Filtering Enable Setting this bit enables digital filtering on all four host control signal inputs SELECTIN STROBE AUTOFD and INIT RST Reset Setting this bit causes the handshake control and decompression logic to immediately terminate the current operation and return to idle RST clears the RLD and FLL bits The PPI state machine BUSY and ACK are negated If the PPIR s BSY2 2 bits are clear then BSY1 0 and 1 1 The software should set the MODE field to 00 to disable handshaking when setting RST to prevent the PPI state machine from starting again RST is a write only bit and setting it causes the reset Clearing RST has no effect This bit always reads as zero 9 1 3 PPI Interrupt Event Register The PPI interrupt event register PIER contains 11 bits that can be enabled and used to drive the parallel port using a software driver Eight of the eleven bits indicate when a rising or falling edge is seen on any of SELECTIN INIT AUTOFD or STROBE host inputs The remaining three bits indicate when a data or command byte is received or when an invalid termination event is detected Figure 9 4 illustrates the PIER OOFFF760 ENABLE qe ro we e
81. interrupt is generated if DMA channel attempts to access DRAM chip select bank using an out of range address This bit is set if the channel s configuration register GDTA GCSTA or PDTA fields do not access a valid address If this error occurs the DMA channel will halt all transfer operations and park in an error condition The DMA channel must then be reset using the soft reset registers GDR or PDR bits before starting a new operation The interrupt level field indicates the interrupt level If any of the events in the channel s interrupt event register occur an interrupt level indicated by this field is sent to the 000 core The interrupt levels range from seven to zero zero disables interrupts 8 5 INITIATING A DMA OPERATION The DMA channel is activated after programming the channel s configuration register and writing the transfer count field The software must ensure that a DMA channel is idle before writing the transfer count field Writing a zero value to the transfer count field is allowed but not recommended New values should not be written into the DMA registers during active transfers because undefined results will occur For transfers to the MC68322 bus from DRAM the GDMA immediately requests data from DRAM After receiving data from DRAM the GDMA begins monitoring the external DREQ input When the external DMA device requests data it is read out of the internal data latch and presented through the MC68322
82. located immediately adjacent to the bits already contained in those registers For example the EXIRO enable bit is bit 0 in the EXIRO ENB register and the EXIR2 enable bit is bit 1 Similarly the EXIRO status and request bits are bit 1 and 0 of the EXIRO EVENT register respectively and the EXIR2 status and request bits are bit 3 and 2 respectively EXIRO and EXIR2 will share the same interrupt level as EXIR1 and EXIR3 If BR or DREQ are to be used as simple inputs rather than interrupts the software should keep the interrupts disabled Users can check the input pin status by reading the status bit for the corresponding pin in the appropriate external interrupt event register Ina similar way the IRQO and IRQ1 pins have always been available as input pins REGISTER ADDRESS BITS R W DESCRIPTION EXIRO ENB OOFFF770 1 R W Interrupt EXIR2 Enable EXIRO EVENT OOFFF772 2 R W Interrupt EXIR2 Request And Status EXIRO MODE OOFFF776 2 R W Interrupt EXIR2 Mode EXIRO SEN OOFFF778 1 R W Interrupt EXIR2 Software Enable Bit EXIR1 ENB OOFFF780 1 R W Interrupt EXIR3 Enable EXIR1 EVENT OOFFF782 2 Interrupt EXIR3 Request And Status EXIR1 MODE OOFFF786 2 R W Interrupt EXIR3 Mode EXIR1 SEN OOFFF788 1 R W Interrupt EXIR3 Software Enable Bit For On The Product Go to www freescale com Freescale Semiconductor The registers in the following table have been added for buzzer
83. location priority 6 3 banks chip select registers 6 1 data transfers synchronous timing values 6 4 minimum value timings 6 2 registers chip select DMA timing register 6 3 chip select recovery 6 4 DMA access timing 8 8 location 6 3 registers at reset 6 3 size encodings 6 2 timing characteristics 6 2 clipping expanded bit maps 13 3 clocks command supplying 10 2 status supplying 10 2 video divisor operation 10 15 command byte detection 9 9 command bytes during ECP mode 9 3 commands to the print engine 10 11 communications modes 9 1 compatibility mode see handshaking core data types and addressing modes 3 3 DRAM write cycle 7 9 DRAMcortroller accesses and refresh cycle 7 6 instruction set summary 3 4 3 6 notational conventions 3 4 programming model 3 1 core read cycle 4 1 core write cycle 4 4 core 3 1 CSDTR 6 3 CSR 6 1 CSR see chip selects registers CSRR 6 4 Product Go to www freescale com Freescale Semiconductor D DA destination address defined 13 3 data bus 015 00 DMA transfers during 8 6 data bus 2 3 4 1 data formats 3 3 data latch DMA during DRAM transfers 8 6 status indication 8 5 data latching parallel port 9 13 data transfer rate 9 14 data transfers see also print engine videio controller PVC DMA termination indication of 8 5 data turnaround time 4 10 DDL 1 8 default interface 10 16 definitions E 1 destination operand type described 1
84. of four major blocks Graphic order parser Graphic order execution unit Writeback logic Band control registers The PVC contains a generic nonimpact printer communication interface which can be used with most of the printers currently on the market The communications interface is 8 bit synchronous full duplex and supports almost all laser and inkjet printers Internal interrupt events if enabled indicate that a serial command has been sent or serial status has been received This interface accesses a memory mapped register called the printer communication interface register which contains 8 bit command and status fields Using these fields the printer communication interface controls the CBSY and SBSY signals to provide a handshake that communicates between the PVC and the print engine In addition to this communication interface the PVC also provides for serialization of the bitmap image data through the video data output at a clock rate specified by the video clock input A digital phase locked loop is also provided for those printers that do not supply a video clock source The RGP interprets a list of special instructions called graphic orders a display list that the core or host application processor generates to render a banded bitmap page image After a page or band image is rendered by the RGP the PVC converts the bitmap image into a serial datastream and transfers the rendered page image through the video por
85. print engine For Mort ON oduct to www freescale com Freescale Semiconductor supine wi uvv HALFTONE BITMAP HALFTONE BITMAP SHOWN TILED SHOWN TILED HXR ra Cs eee SOURCE 21 SOURCE i FRAME 1 FRAME gt HXR 0 PAGE 180 PAGE TOP TO BOTTOM TOP TO BOTTOM Figure 13 2 Halftone Specification for bitBLT Operations 13 4 BAND NUMBER AND BAND FAULTS Each of the MC68322 graphic orders that operate on a banded bitmap contains a band number parameter The band number is used by the MC68322 to determine when to execute the graphic order Graphic orders whose band numbers match the current band being rendered are executed Otherwise the graphic order is skipped Band numbers always increase in value from the top band to the bottom band of the image regardless of the type of page 0 or 180 being rendered The band number for a graphic order must be determined by the software It must be the number of the band where the first scanline of a graphic order resides when rendering a 0 page or the number of the band where the last scanline of a graphics order resides when rendering a 180 page In banding applications bitBLT and scanline operations can extend beyond the bottom or top for 180 pages boundary of a band The MC68322 detects such band crossings or band faults during the course of the bitBLT or
86. remains set BUSY remains high and the software can manipulate status lines to indicate the error condition After the error condition is cleared the software returns the SEL PER and FLT bits in the PPIR to their normal negated state After 1 us the software clears ERC and the handshake logic concludes the cycle by generating an ACK pulse and clearing BSY1 If ERC is set when the handshake logic is in the middle of a transfer data is still latched but no acknowledge is generated until ERC is cleared In other words ERC prevents the handshake logic from generating ACK pulse and clearing BSY1 If ERC happens to be set near the end of the cycle after the handshake logic has begun to generate an ACK pulse the hardware continues to produce the ACK pulse as normal Setting ERC does not affect an ACK pulse that is already active but does prevent an ACK pulse that hasn t yet started as described above This behavior can result in two ACK pulses being generated while BUSY is high The first ACK is generated in response to STROBE and the second after ERC is cleared Figure 9 7 illustrates the timing diagram for an error cycle For On This Product Go to www freescale com Freescale Semiconductor Vit ERC SELECT PERR FAULT BUSY 656 1us DELAY 1us DELAY Figure 9 7 Error Cycle Timing Diagram 9 6 PARALLEL PORT DATA BUS LATCHING Latching
87. repetitively applied to data being transferred from a source bitmap to a destination bitmap thus causing a change in the appearance of the data 12 2 GRAPHIC OPERANDS Up to three operands are used when composing the print image source destination and halftone The source operand is typically located in a frame or unexpanded bitmap the destination operand in a banded or unbanded bitmap and the halftone operand in a halftone bitmap These operands are represented by a specific 1 byte constant value which is listed in Table 12 1 Table 12 1 Graphic Operation Data Operand Constant Values CONSTANTS BINARY CODING Zero 00000000 One 11111111 Destination 10101010 Source 11001100 Halftone 11110000 These five constant values can be combined using Boolean arithmetic computations to yield a 1 byte Boolean code that corresponds to a specific transfer effect See Section 12 4 Boolean Codes for more information For On The Product Go to www freescale com Freescale Semiconductor AF erus R2 12 3 TYPES OF GRAPHIC OPERANDS Graphic orders specify which graphic operands to transfer and there are three types All graphic orders of the form XXXX D such as SET BOOL D define 1 operand transfers that specify only the destination bitmap All graphic orders of the form XXXX SD or XXXX HD such as BLT2F SD or SL2UB HD define 2 operand transfers that specify the dest
88. scanline operation When a band fault occurs the operation is prematurely terminated and the MC68322 accesses the display list to update the graphic order s parameters including its band number bitmap and scanline table addresses and frame bitmap heights The graphic order parameters are written back into the display list to begin the operation following the point of the band fault at the top or bottom for 180 pages of the next band The MC68322 automatically adjusts the band number when the graphic order spans multiple bands When a band fault occurs the band number is incremented or decremented depending on the setting of the B2T flag If the B2T flag is clear the band number is incremented when an operation crosses a band boundary If the B2T flag is set the band number is decremented For 166322 On This broduct Go to www freescale com Freescale Semiconductor MAT wires Band faults only occur during graphic orders that operate on banded bit maps In the descriptions that follow parameters updated by the MC68322 as the result of a band fault are marked with asterisks In some cases however certain parameters will not be updated Specifically this affects source and halftone parameters If the Boolean code for a two or three operand graphic order describes a function that does not require a source and or halftone operand then no bitmap is accessed and no parameters will be updated if
89. techniques This design implementation provides a technically superior and more cost effective system solution The specialized display list banding techniques executed by the RGP enable system memory requirements to be significantly reduced The use of software memory reduction techniques alone an approach taken by conventional controllers lack the power needed to handle complex pages causing the controller to fall back to lower resolution or reduced page throughput The MC68322 optimizes overall system performance by integrating an 000 core and PVC using a unique dual bus architecture This architecture eliminates bus contention between processing units and modules creating a true parallel processing environment The additional bandwidth allows each processing unit to operate at peak performance Working in conjunction with an on chip programmable bursting DRAM controller the processing units are capable of achieving outstanding throughput These dedicated processing units enable the MC68322 to produce 600 dpi images using substantially less memory than conventional controllers The MC68322 extends these benefits to low cost 4 8 ppm printers The MC68322 significantly reduces component count board space power consumption and their inherent costs while yielding higher reliability and shorter design time It also provides support for toner conservation thus enabling the print controller to conserve toner when printing in draft mo
90. the host input on the rising edge of CLK1 and passes a logic level change through but only if the host signal is sampled at the same logic level for a second consecutive clock Digital filtering protects internal logic from glitches as wide as one CLK1 period Such internal logic includes the hardware handshake control logic the PPCR and the parallel port interrupt controller Synchronization plus digital filtering adds two CLK1 periods of delay before a level change on one of the host signals appears in the PPCR and three CLK1 periods of delay before an output responds to an input before BUSY responds to STROBE Likewise synchronization and digital filtering of STROBE affect the point at which PD7 PDO and AUTOFD are latched into the PPIR Without digital filtering PD7 PDO and AUTOFD are sampled on the second rising edge of CLK1 after STROBE is first sampled low With digital filtering PD7 PDO and AUTOFD are sampled on the third rising edge of CLK1 after STROBE is first sampled low Digital filtering can be disabled to avoid the one clock penalty that it adds to recognizing input signals This is an option in specialized applications that have a high bandwidth requirement and the ability to guarantee signal integrity between the host and the printer Otherwise it is highly recommended that digital filtering be enabled For On This Product Go to www freescale com Freescale Semiconductor
91. thus indicating that the core has accessed a memory location that is not mapped to a register chip select or DRAM The interrupt is cleared by writing a 1 to the CIA bit position The core will never have a bus error condition The EIA bit is set if the external bus master accesses a memory location that is not mapped to a register chip select or DRAM This interrupt generates a level 7 interrupt to the core The interrupt is cleared by writing a 1 to the EIA bit position 5 2 EXTERNAL INTERRUPTS The MC68322 provides up to four pins for external interrupts IRQ3 IRQO IRQ1 and IRQO are dedicated interrupt pins IRQ3 and IRQ2 are multiplexed pins and must be programmed to be used as interrupt pins Refer to Appendix D Alternate Pin Functions for more details These inputs can be individually programmed for active polarity and either level or edge sensitivity External interrupts are asynchronous to the MC68322 and are synchronized inside the MC68322 for proper operation Two registers control each source of external interrupt external interrupt 0 2 and 1 3 registers EXIRO 2 EXIR1 3 Figure 5 2 illustrates these registers EXTERNAL INTERRUPT _ REGISTER 0 2 EXTERNAL REGISTER 1 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED Figure 5 2 External Interrupt Registers EXIRO 2 EXIR1 3 For More MES ah BM V b roduct Go to www freescale com Freescale Semiconductor Ing IIO aii EN
92. unit manages the bus arbitration signals so that the core alternates cycles between GDMA and the external master Systems having several devices that become bus master require external circuitry to assign priorities to the devices So when two or more external devices try to become bus master at the same time the one having the highest priority is the bus master first These external devices must assert the bus arbitration signals in the following sequence 1 An external device asserts the bus request BR signal This can be a wire ORed signal although it need not be constructed from open collector devices that informs the MC68322 that an external device requires control of the bus 2 The MC68322 three states 25 1 015 00 AS and Then it asserts the bus grant BG signal to indicate the bus is available 3 The external device controls the bus cycle by driving the control signals and the MC68322 asserts EDTACK to denote the end of each external bus master cycle BR can be issued at any time during a bus cycle or between cycles BG is asserted when the bus is available When the requesting device receives BG and more than one external device can be bus master the requesting device should begin whatever arbitration is required The external device asserts and maintains BR during the entire bus cycle or cycles for which it is bus master The following conditions must be met for an external device to assume mastership of the bus th
93. up can be achieved in the ECP forward mode The hardware handshaking can also be completely disabled for the software to directly control the parallel port interface signals and support new protocols Control and data signals provide a glueless interface to the parallel port 1 3 INTERNAL MEMORY MAP The MC68322 uses memory mapped registers that occupy 4K of memory space With these registers the hardware configuration and timing can be set the status information can be read and the PVC RGP DMA and PPI interfaces can be controlled All registers can be written and read except for a few read only and write only registers that are noted For more information about each register see its corresponding module s section Appendix C Memory Mapped Register Summary discusses all the registers and their location in memory during power up Register operations are implemented within one MC68322 bus cycle for both read and write operations and are completed without asserting any wait states The registers should only be read and or written as 16 bit words All register addresses are on word boundaries The MC68322 powers up with a 16M memory map with the registers occupying the upper 4K of the 16M of memory space They are located at address range through OxOOFFFFFF The MC68322 memory map for a 16M memory space is illustrated in Figure 1 3 1 6 MC68322 USER S MANUAL For More Information On This Product Go to www freescale c
94. use the PIER and PPIR to read and control the logic levels on all parallel port pins 9 2 1 Compatibility Handshaking Compatibility mode hardware handshaking is enabled by setting the PPCR s MODE 01 When this mode of handshaking is enabled the PPI automatically generates BUSY when the leading edge of STROBE from the host is received and latches the logic levels on PD7 PDO AUTOFD into the PPIR The PPI then waits for STROBE to negate and the PPIR s DATA field to be read After both of these events occur the PPI asserts ACK for the duration specified in the PPIR s ACKW field and then negates ACK and BUSY to conclude the data transfer When data is latched into the PPIR s DATA field the PPI generates two interrupt events a parallel port DMA PDMA request and a core interrupt request The software can alternate between and interrupt based data transfers The request remains active until the data is read by either the PDMA channel or core in response to the interrupt event If the PDMA has been enabled it responds to the request by reading the PPIR s DATA field and writing the data to DRAM When the PDMA channel reads the DATA field ACK is pulsed BUSY is negated and the PDMA request is cleared The PIER s ENABLE field can be programmed to interrupt the core when parallel port data is received If enabled the PIER s bit when set will generate a data received interrupt event When the core rea
95. usual exception processing The saved value of the internal program counter is the address of the instruction that would have been executed had the interrupt not been taken The appropriate interrupt vector is fetched and loaded into the internal program counter and normal instruction execution commences in the interrupt handling routine For On This Product Go to www freescale com Freescale Semiconductor and Exception Handling 5 4 2 3 INSTRUCTION TRAPS Traps are exceptions caused by instructions and they occur when the core recognizes an abnormal condition during instruction execution or when an instruction is executed that normally traps during execution Exception processing for traps is straightforward The internal status register is copied the supervisor mode is entered and tracing is turned off The vector number is internally generated but as the trap instruction part of the vector number comes from the instruction itself The internal program counter and the copy of the internal status register are saved on the supervisor stack The saved value of the internal program counter is the address of the instruction following the instruction that generated the trap Finally instruction execution commences at the address in the exception vector Some instructions are used specifically to generate traps The trap instruction always forces an exception and is useful for implementing system calls for user programs Th
96. 00 0000 PDMADRAMTRANSFERADDRESS HIGHWORD OOFFF200 00000000 00000000 PDMADRAM TRANSFER ADDRESS LOW WORD OOFFF202 00000000 00000000 PDMATRANSFER COUNT 204 000000 00000000 FR OOFFF206 XXXXXXXX XXXXXXXO 0000 GDMA DRAM TRANSFER ADDRESS HIGHWORD OOFFF210 00000000 00000000 GDMA DRAM TRANSFER ADDRESS LOWWORD 00 212 00000000 00000000 oe 0000 CHIP SELECT TRANSFER ADDRESS HIGH WORD 00 214 00000000 00000000 REG GDMACHIP SELECTTRANSFER ADDRESS LOWWORD OOFFF216 00000000 0000000X GDMATRANSFER COUNT 218 000000 00000000 FR 00 21 XXXXXXXO GDMCR DS 00 21 XXX00000 PPCR FLLIRLD ABT PDE ERC MODE preE RST OOFFF300 XXXXXXX0 00000000 INT AFD STR sin 857 ACK peg err OOFFF302 XXXXX000 01101000 PPIR CMD DATA O0FFF304 XXXXXXX0 00000000 ACKPULSEWIDTH ACKW O0FFF306 XXXXXXXX 00000000 PRT OOFFF400 XXXXXXXX XXXXXXXO SDN SLC SRC PLE PLD VDP BDP PRP FSP LSP VCP VCS OOFFF402 0000000 00000000 VERTICALMARGIN OOFFF404 00000000 00000000 HORIZONTAL MARGIN 406 00000000 00000000 PCB PAGE IMAGE HEIGHT 00 408 00000000 00000000 REG PAGE IMAGE WIDTH OOFFF40A 00000000 00000000 SET SME B2T BND OOFFF40C XXXXXXXX XXXXX000 0 PAGE IMAGE BIT ADDRESS HIGHWORD OOFFF410 00000000 00000000 PAGE IMAGE BIT ADDRESS LOWWORD OOFFF412 00000000 00000000
97. 00000 DMASP 5 0 00 904 00000000 00000000 RGPBUSACTIVITY OOFFFAOO 00000000 00000000 TEST IPL OOFFFA02 XXXXXXXX XXXXX000 TMR PCOM RGP PVC 4 00000000 00000000 SFT 6 XXX00000 00000000 C 1 MC68322 MASK REGISTER The MC68322 mask 322MSK register reflects the revision number of the MC68322 chip C 2 TEST REGISTER The test register contains fields that should not be read or written RGP Bus Activity This field indicates the current bus activity while the RGP is processing a display list For More FS 322 3322 USER uM oduct Go to www freescale com Semiconductor Inc WIV y EM DMA DMA Test When this bit is set with WAIT asserted a DRAM cycle will be delayed This bit is used for testing the DMA cycles IPL IPL Test When this bit is set the IPLx signals output on MA2 MAQ This bit is used with the test registers interrupt set fields PDMA GDMA TMR PCOM etc to test the interrupt logic in the MC68322 MD Mode Test When this bit is set with WAIT asserted the MC68322 goes into test mode Set Interrupt The test register contains 10 fields collectively called the set interrupt fields which allow the capability to set interrupt events for each module Writing a 1 to a bit will set the corresponding bit in that module s interrupt event register Writing a z
98. 08 PIN PGA ICEN coi Bron HIZ Figure A 1 ICE Interface Block Diagram For More FS 8322 UBER 5 Ph roduct Go to www freescale com Freescale Semiconductor nin ull cieolieevis er A 3 ICE ADAPTOR BOARD SCHEMATICS MC68322l A A CLK2 RESET 2702 BR A R W ROO 10KQ 45V R21 RW 270 DREQ 270 SBSY STS FSYNC SYNC SELECTIN STROBE AUTOFD INIT U21 68322 20 0 1 010 C10 LDS 683221 gH Jaz C TEST68K L1 J2 J3 D3 C3 P13 5V 5 IHALT 1KQ IRESET Figure A 2 MC68322 PGA Pinout 322 For More 65 ash BM M product Go to www freescale com N17 U16 P14 P16 R16 BG EDTACK C80 651 652 CS3 C94 55 CS6 CS7 RD WRL WRU RASO RAST RAS2 RAS3 RAS4 RAS5 CASO CAS1 WE DACK CCLK CBSY CMD VIDEO PRINT BUSY SELECT PERROR FAULT Freescale Semiconductor ni ee Une ciolieevis er U33 034 031 74ALS244 74ALS244 MC68000 64 DIP DO M D1 2 02 03 M D4 5 05 A6 D6 07 08 9 09 10 1010 11 1011 12 1012 13 035 036 1013 14 1014 15 1015 16 45V 17 18 19 20 10KQ
99. 1 phase lock loop control of video clock 10 3 phase locked loop 10 1 PIER 9 6 pins alternate functions D 1 pixel definition 12 1 PLL video clock divisor 10 15 PLL 10 1 PPCR 9 4 PPIR 9 2 prescaler setting resolution 10 15 print engine band image starting address 10 6 clocks supplying cammand and status 10 2 command operation end of operation 10 11 interface operation described 10 9 reset operation 10 11 synchronous operation 10 10 transmitting data 10 2 video clock divisor operation 10 15 video rate supplied 10 2 print engine interface operation command 10 11 PLL video clock divisor 10 15 status 10 13 operation 10 9 printer communication protocol 10 8 PVC on reset 10 15 registers printer communication interrupt event 10 8 printer communication 10 2 printer control block register set 10 5 PVC control 10 3 PVC interrupt event 10 6 registers 10 2 synchronous asynchronous PVC operation 10 10 Product Go to www freescale com Freescale Semiconductor mavan print engine interface 10 1 print engine video controller data transfer complete 10 9 soft reset 10 16 print engine video controller PVC soft reset 10 7 starting 10 9 print engine video controller interface signals 2 8 print engine video controller 10 1 printer communication interface signals 2 8 printer communication protocol 10 8 printer control block new print operation indication 10 6 printer language
100. 12 10 halftoning definition 1 10 handshaking compatability error cycles 9 12 ECP enabling with RLE 9 9 enabling without RLE 9 9 operation 9 9 with RLE 9 10 without RLE 9 10 hardware disabling 9 10 resetting controller 9 14 software controlled 9 11 handshaking modes compatability enabling 9 8 operation 9 8 PDMA during 9 8 ECP command bytes during 9 3 types 9 8 hardware handshaking 9 7 horizontal margin see page margins HTTA see halfton table address HXR halftone X remainder defined 13 3 HYR halftone Y remainder defined 13 4 ANS Product Go to www freescale com Freescale Semiconductor ICE interface signals 1 ICE A 1 illegal address DMA access to 8 6 illegal address interrupt 4 12 illegal and unimplemented instructions 5 10 illegal instruction exception 5 11 in circuit emulation interface adaptor board design A 4 adaptor board schematics A 6 pin assignment A 16 signals A 1 in circuit emulation interface A 1 initialization graphic orders 13 1 instruction set summary 3 4 3 6 instructions illegal and unimplemented 5 11 privileged listed 5 11 privileged 5 11 tracing 5 12 unimplemented emulation 5 11 interrupt acknowledge bus cycle 4 6 interrupt events command sent 10 11 RGP error 12 15 interrupt handling 5 1 interrupt generating 4 6 interrupts DTACK during illegal memory address access 5 3 error during RGP operation 11 3 events band u
101. 18 O 57 415 WAIT 1 14 121 2 15 WRL M5 120 00 IRQO 6 WRU A16 11g MD1 IRQ1 AEN A17 117 2 57 RASO 18 116 9 51 20 161 O RAS3 MD6 EMURST o 92 RASA A22 111 MD7 161 55 23 110 MD8 iod 50 24 109 MD9 ad CAS1 A25 Jog 010 WE 106 MIDI DREQ 73 528 105 DO 104 MD13 mE 79 CCLK D1 MD14 82 O 104 5 5 a 83 CBSY D2 MD15 STS 80 CBS D3 d 81 CMD D4 VCLK 89 87 05 156 85 q 84 VIDEO D6 155 ien LSYNC 86 d FRINT D7 154 312 146 08 152 145 BUSY 09 151 SELECTIN d PD4 157 SELECT D10 150 STROBE q 143 PD5 139 011 148 140 FAULT 012 147 INIT 142 013 PD7 014 015 Figure 8 MC68322 ICE Interface For More FS 8322 UBER oM Ph roduct Go to www freescale com Freescale Semiconductor B 7 CONFIGURING THE PARALLEL PORT The MC68322 provides a direct connection with no external buffers or latches to virtually all standard computer parallel ports available The MC68322 can support 2M sec and higher data rates when the internal DMA is utilized Additionally the parallel port supports the IEEE 1284 interface Figure B 9 demonstrates the interface to a parallel port connector External resistors are needed in many implementations to avoid ringing RF noise and a powered do
102. 2 2 but when the ROM mode is selected the access time becomes 5 3 3 3 for that particular channel This timing relaxation in the ROM mode allows ROMs which typically have longer access times than to operate effectively on one or more of the DRAM channels For On This Product Go to www freescale com Freescale Semiconductor WVU VWI At the same time the other channels the normal mode will run at full speed thereby achieving maximum use of the available bandwidth in the DRAMs and maximizing system performance In addition to extending the accesses one CLK1 of idle time is inserted at the end of the entire access to the channel when in the ROM mode This idle clock allows the data bus to return to a state of high impedance because ROMs can drive the data bus for an extended period of time after an access 7 1 2 2 TIMING EXAMPLE Figures 7 2 and 7 3 illustrate the difference between the DRAM accesses when in normal mode and ROM mode This example is for DRAM timing mode 1 but similar behavior is exhibited in timing modes 0 and 2 CLK2 MA10 0 X ROW COLUMN X COLUMN ROW COLUMN RAS5 0 Mr CASTO X MD15 0 DATA DATA SINGLE CYCLE FAST CYCLE pe lt a gt INIT
103. 2 2 destination address duplex operation 13 6 digital filtering 9 11 direct memory access DMA DMA accesses 7 1 display list banded defined 11 3 errors during execution 11 4 example format 13 5 display lists address convention 12 15 DMA active channel indication 8 5 arbitration 8 8 chip select bank access timing 8 8 DRAM bus transfers 8 8 error condition 8 6 external device request 8 4 flush request described 8 3 flush requst during operation 8 6 GDMA read cycle termination 8 7 GDMA configuration registers described 8 2 GDMA write cycle 8 7 illegal address interrupt 8 6 MC68322 bus cycles CSx during 8 4 PDMA during compatibilty mode 9 8 PDMA configuration registers described 8 2 soft reset register 5 14 transfers For Mol oderat ion DMA initiated 8 6 DREQ and DACK during 8 7 size 8 6 interface channel status indication 8 5 channels 8 1 data latch DRAM transfers 8 6 data latch status indication 8 5 DRAM bus control 8 8 error condition 8 10 GDMA CSx during read cycle 8 7 handshaking 8 7 read cycle request 8 7 initiating an operation 8 6 invalid address accessing 8 6 MC68322 address bus incrementing 8 2 operation 8 1 reallocating resource 8 6 transfer count field 8 3 transfers count 8 3 direction programmed 8 4 flush request 8 3 termination indication 8 5 width programmed 8 4 DMA interface signals 2 8 interface 8 1 DMASP 8 4 DRAM bank size 7 1
104. 3 13 Destination bitBLT to Frame 00000000 13 23 13 14 Source Destination bitBLT to Frame 13 24 13 15 Source Halftone Destination bitBLT to Frame 13 26 13 16 Expanded Source Destination bitBLT To Frame 13 28 13 17 Expanded Source Halftone Destination bitBLT To Frame 13 31 13 18 Destination bitBLT to Unbanded Bitmap 13 32 Freescale Semiconductor Inc LIST OF ILLUSTRATIONS Continued For More informatio ion 5 BANAL Product Go to www freescale com Freescale Semiconductor LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number 13 19 Source Destination bitBLT to Unbanded Bitmap 13 33 13 20 Source Halftone Destination bitBLT to Unbanded Bitmap 13 35 13 21 Expanded Source Destination bitBLT To Unbanded Bitmap 13 37 13 22 Expanded Source Halftone Destination bitBLT to Unbanded Bitmap 13 40 13 23 Banded Bitmap Parameters 13 44 13 24 Halftone Bitmap tans 13 46 13 25 Unpacked Source Bitmap 13 47 13 26 Destination Scanline Transfer to
105. 5 ASSERT CS1 AND CS0 DEPENDING ON UDS AND LDS DRAM ONLY 6 ASSERT RAS DRAM ONLY 7 WRITE DATA FROM DESTINATION 8 RECEIVE DATA ON INTERNAL D15 D0 9 ASSERT INTERNAL DTACK 10 ASSERT WAIT TO STALL EXTERNAL 68322 BUS ACCESS OPTIONAL ACQUIRE THE DATA 1 REMOVE DATA FROM INTERNAL D15 D0 2 NEGATE AS 3 SET R W TO READ TERMINATE THE CYCLE 2 NEGATE INTERNAL DTACK 2 NEGATE WRU AND WRL MC68322 BUS ONLY 3 NEGATE 10 0 WE RAS AND CAS DRAM ONLY START NEXT CYCLE Figure 4 5 Write Cycle Flowchart For More ie ash M product Go to www freescale com Freescale Semiconductor oi 50 52 54 56 50 52 54 56 50 52 54 56 ot m NM M 3 m m m i A0 EP m s m M UDS LDS R W Sag 015 08 B NM ww mm lt WORD WRITE gt lt ODD BYTE WRITE gt lt EVEN BYTE WRITE gt NOTE 0 UDS LDS and DTACK are internal signals only Figure 4 6 Word and Byte Write Cycle Timing Diagram to Chip Selects When the core initiates a DRAM write cycle the data is latched in an internal write buffer and a zero wait state is generated to the core The data from the write buffer is written to DRAM through the graphics bus as soon as the bus is available Subsequent write cycles to DRAM
106. 5 7 test C 3 timer interrupt event 5 5 timer 5 5 rendering direction programmed 10 5 RESET asserting 9 14 reset exeption 5 9 reset instruction executing 4 8 reset operation PVC during 10 11 PVC 10 15 reset operation 4 8 resolution 10 15 resolution 10 1 RGP 10 9 11 1 RICSC graphics processor RGP burst cycles 7 1 RIER 11 2 RISC graphics processor DMA accesses 7 1 errors during display list execution 11 4 operation 11 3 registers RGP diagnostic 11 2 RGP interrupt event 11 2 RGP start 11 2 registers 11 2 soft reset register 5 14 RISC graphics processor 11 1 ROM mode 7 2 Product Go to www freescale com Freescale Semiconductor RSR 11 2 run length decompression resetting logic 9 14 decompression 9 10 run length encoding command received interrupt 9 7 5 13 scanline table address convention 12 15 table address STLA during duplex operation 13 6 scanline and halftone table example 12 13 scanline graphic orders 13 4 scanline order execution 12 14 scanline table 12 6 scanline definition 12 1 Scource operand type described 12 2 SET BBMAP 13 47 SET BOOL D 13 50 SET HTBMAP 13 51 SET SBMAP 13 53 SET UBMAP 13 54 signal descriptions 2 1 signal summary 2 2 signals ACK during compatibility mode transfer 9 8 software control of 9 4 AUTOFD during compatibility mode transfer 9 8 bus arbitration 4 9 bus control 4 1 BUSY software cont
107. 6 5 4 3 2 4 0 Figure 11 2 RGP Diagnostic Register 11 1 3 RGP Interrupt Event Register interrupt event register RIER processes and controls interrupts from the to the core 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OOFFF714 LEVEL 15 4 13 12 1 10 9 8 7 6 5 4 3 2 1 0 RESERVED Figure 11 3 RGP Interrupt Event Register For The Product Go to www freescale com Freescale Semiconductor Inc waynes RDN bits are set by to indicate one interrupt event to the core each event bit has a corresponding bit in the enable field The RBY bit indicates that the RGP is executing a display list and the DLF bit indicates that a second display list is queued The RGP sets the RBY bit when the RSR is loaded and clears the RBY bit when it encounters a STOP graphic order If a second display list start address is loaded before a STOP graphic order is encountered the RGP keeps RBY set as the second display list starts Since the RSR is double buffered the DLF bit is set only after a second display list address is loaded If a second display list address was loaded and RGP reaches the end of the current display list it clears the DLF bit Keeps RBY set and starts reading the second display list DLF is cleared as soon as a STOP graphic order opcode for the current display list is encountered If the RSR is loaded when DLF is
108. 6 bit specifiers only the scanline table is read The halftone specifiers like their bit string counterparts must be located on word aligned boundaries and consequently the halftone table address pointer specified in the scanline graphic order must be word aligned 0 mod 2 byte address For On The Product Go to www freescale com Freescale Semiconductor supine 12 7 SCANLINE AND HALFTONE TABLE EXAMPLE Figure 12 8 illustrates an example scanline table its corresponding halftone table and the resulting image Notice that the halftone table contains only two specifiers since the scanline table is mostly composed of 16 bit bit string specifiers and that the halftone table is not terminated with 0000 null specifiers but the scanline table is SCANLINE TABLE a oo DX 30 NULL BSS 1 BSS 2 E BSS 3 BSS 4 55 5 855 6 02 4292601 1789 2400 999 RL 500 NULL NOTES COMPANION HALF TONE TABLE HDX 2 0 HTS 2 HTS 6 4 HDX 1 5 41 5 8 1 8 HALFTONE BIT MAP HH 8 HTS Halftone Specifier BSS Bit String Specifier DESTINATION BIT MAP DW 2400 999 1789 lt Figure 12 8 Scanline and Halftone Table Example For More 6 raa SER ion ae oduct Go to www freescale com Freescale Semiconductor
109. 60 6 562 ADDR7 EQU 70 TIMING7 EQU 572 RECOVERY EQU 82 DRAMO EQU 100 DRAM1 EQU 110 DRAM2 EQU 120 DRAM3 EQU 130 DRAM4 EQU 140 DRAM5 EQU 150 DRAM EQU 160 DRAM REF EQU 162 SECTION code XDEF start XREF main start move l 50 5 Clear 5 move l 0 a6 Clear frame pointer move w 2700 sr Set up status register lea BASE322 a0 Set a0 to base address of 68322 move w 0c18 ADDRO a0 Set 50 to 0x600000 0x6fffff move w 0003 TIMINGO a0 move w 51010 1 a0 Set CS1 to 0x400000 0x5fffff move w 0003 TIMINGI1 a0 move w 1008 ADDR2 a0 Set CS2 to 0x200000 0x3fffff move w 0003 TIMING2 a0 0c38 ADDR6 a0 Set CS6 to 0xe00000 0xefffff move w 3434 TIMING6 a0 move w 0c3c ADDR7 a0 Set CS7 to 0 00000 move 3434 TIMING7 a0 move w 1540 RECOVERY a0 Set recovery for back to back access move w 50200 DRAMO a0 DRAMO 0x0 0x80000 move 50000 DRAM1 a0 Disabled move w 040c DRAM2 a0 DRAM2 0x600000 Ox7fffff move w 0410 DRAM3 a0 DRAM3 0x800000 Ox9fffff W 0414 DRAM4 a0 DRAMA 0xa00000 Oxbfffff move w 0418 DRAM5 a0 DRAM5 0xc00000 Oxdfffff move w 0000 DRAM CTRL a0 move w 0020 DRAM REF a0 bra main Jump to Main end For On This Product Go to www freescale com APPENDIX MEMORY MAPPED REGISTER SUMMARY Freescale Semicond
110. 7 electrical characteristics 14 1 enhanced capabilities mode 9 1 error condition For RS display list execution during 11 4 DMA transfers 8 10 RGP operation during 11 3 error condition DMA during 8 6 error cycles 9 12 exception handling 5 1 exception processing stack frame during 5 8 status register during 5 7 exception vector number 5 7 exceptions address error 5 12 bus cycles 5 13 causes 5 11 how processing occurs 5 6 illegal 5 11 illegal and unimplemented instructions 5 10 multiple 5 13 multiple 5 13 operation 5 6 priority 5 13 privilege violations 5 11 processing specific 5 9 tracing 5 12 types instruction traps 5 10 interrupt 5 10 reset 5 9 types 5 9 unimplemented 5 11 exceptions 5 6 EXIRO ENB D 2 EXIRO EVENT D 2 EXIRO MODE D 2 EXIRO SEN D 2 EXIR1 ENB D 2 EXIR1 EVENT D 2 EXIR1 MODE D 2 EXIR1 SEN D 2 expanded bit block graphic orders 13 3 expanded bitmap 12 1 expanded bitmaps clipping 13 3 external bus master illegal memory address access 5 3 external bus master read cycle 4 10 external bus master signals 2 6 external bus master write cycle 4 11 external bus master 4 9 Product Go to www freescale com Freescale Semiconductor F fast page mode 7 1 features core 3 1 MC68322 1 2 FH frame height defined 13 4 flush request DMA during operation 8 6 flush request DMA 8 3 frame bit map described 12 2 frame bitmap 12 2 FW frame wi
111. 8 7 6 5 4 3 2 1 0 RESERVED Figure 7 5 DRAM Control Register The TS field is used to select one of three DRAM timing modes The timing mode selected applies to all banks All DRAM devices connected to the MC68322 must operate at the same speed because the DRAM controller does not support independently programmable bank speeds The exception to this is the ability to slow down individual DRAM banks by setting the ROM mode bit in the corresponding DRAM register See Section 7 1 2 ROM Mode for details The RIC field provides the refresh time interval in CLK1s The CAS and RAS timing parameters for refresh are hardcoded and cannot be programmed However the RIC field can be changed at any time and the new value will take effect when the next terminal count is reached and a refresh cycle begins Then the new RIC field value is loaded into the refresh counter 7 3 DRAM TIMING MODES Three DRAM timing modes provide wait state profiles optimized for various DRAM speeds at system frequencies of 16 20 and 25MHz These timing modes are not fixed to any specific system clock frequency and can therefore be used regardless of system clock frequency as long as the DRAM device timing is satisfied The DRAM controller automatically bursts for both read and write bus cycles Table 7 2 lists the timing modes their associated DRAM control register TS field encodings and the recommended system speeds Table 7 2 DRAM Timing Modes TS FIELD MODE WAIT ST
112. ACE ASSIGNMENT 0 000 5 Reset Initial Interrupt Stack Pointer 2 1 004 5 Reset Initial Program Counter 2 2 008 50 Not Applicable 3 00 50 Address Error 4 010 50 Illegal Instruction 5 014 50 Integer Divide Zero 6 018 50 CHK Instruction 7 01 50 Instruction 8 020 50 Privilege Violation 9 024 50 10 028 SD Line 1010 Emulator Unimplemented A Line Opcode 11 02C SD Line 1111 Emulator Unimplemented F Line Opcode 121 030 Unassigned Reserved 131 034 Unassigned Reserved 14 038 50 Format Error 15 03C SD Not Applicable 16 231 040 05 Unassigned Reserved 24 060 SD Not Applicable 25 064 50 Level 1 Interrupt Autovector 26 068 50 Level 2 Interrupt Autovector 27 06C 0 Level 3 Interrupt Autovector 28 070 50 Level 4 Interrupt Autovector 29 074 SD Level 5 Interrupt Autovector 30 078 SD Level 6 Interrupt Autovector 31 07C SD Level 7 Interrupt Autovector 32 47 080 0 50 TRAP 40 15 Instruction Vectors 48 631 0C0 0FC Unassigned Reserved 64 255 100 0 User Defined Vectors NOTES 1 Vector Numbers 12 13 16 23 And 48 63 Are Reserved For Future Enhancements By Freescale No User Peripheral Devices Should Be Assigned These Numbers 2 Reset Vector 0 RRequires Four Words Unlike The Other Vectors Which Only Require Two Words And Is Located In The Supervisor Program Space 3 TRAP n Uses Vector Number 32 n 4 SP Denotes Supervisor Program Space And SD Denotes Supervisor Data Spac
113. AM Timing Mode 1 Write Cycle 7 9 7 12 DRAM Timing Mode 2 Write Cycle 44 0211 7 9 8 1 Configuration Registers 8 2 8 2 Control Register e cere Rees 8 3 8 3 DMA Speed Register tee octo pu iler pedis ae bres 8 4 8 4 DMA Interrupt Event Registers 8 5 8 5 MC68322 Bus Read Or Write Cycle 8 8 8 6 Byte Sized DRAM Write Transfer 8 9 8 7 Word Sized DMA DRAM Write Transfer 2 8 9 9 1 Parallel Port Interface Controller Block Diagram 9 1 9 2 Parallel Port Interface Register 22 2224 4 2 4 9 2 9 3 Parallel Port Control Register da oe De ie ed edit 9 4 9 4 PPI Interrupt Event Register 221 24 44 21 9 6 9 5 Compatibility Mode Timing Diagram 9 8 9 6 EGPMode Timing Diagram 9 9 9 7 Error Cycle Timing Diagram tutte ee 9 13 9 8 Parallel Port Data Latch Timing Diagram 9 13 10 1 Printer Communication Register 10 2 10 2 PVC Control Register cuc sic cuite gto md tete eode tique 10 3 10 3 Printer Control Block Register Set
114. ANA oduct Go to www freescale com MAP SET Set Banded Bitmap Parameters PARAMETERS DESCRIPTION Byte SET_BBMAP Opcode Byte Reserved Byte Current band number 1 of 8 bits Bottom to top duplex direction Word Destination banded bitmap warp in bits Long Word Signed difference between the physical and logical address spaces bits Long Word End of band physical bit address The SET_BBMAP graphic order specifies the structure of a banded bitmap The current band number render direction and warp are provided in addition to a signed value for mapping logical addresses to physical addresses and a physical address indicating the end of the band buffer These parameters are used in all subsequent graphic orders that only operate on a banded bitmap They do not however affect transfers to frames or unbanded bit maps SET_BBMAP graphic order specifies a current band number to be rendered from the remainder of the display list The current band number is used in comparison against the band numbers found in subsequent bitBLT and scanline graphic orders that operate on the banded bitmap The result of each band number comparison determines whether a graphic order is executed during the current pass of the display list Note that a banded display list is executed several times One pass for each band of the page The B2T parameter contains a 1 bit
115. ATE PROFILE ENCODING RECOMMENDED SYSTEM SPEED Timing Mode 0 3 3 3 5 25 2 with 80ns 5 2 2 2 writes Timing Mode 1 2 2 2 reads 01 20MHz with 100ns or 25MHz with 70ns 4 2 2 2 writes Timing Mode 2 2 1 2 Wi Mm 80ns 20MHz with 60ns or 25MHz 3 2 2 2 writes with 5 Not Used Not Used For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor wvu 7 4 55 5 When the PVC one the DMAs core accesses DRAM the MC68322 begins DRAM read or write cycle to one of the DRAM banks The software must assure that eight or more refresh cycles described below have occurred before any access to the DRAM is performed This is a requirement of the DRAM devices rather than the MC68322 7 4 1 DRAM Refresh Cycles DRAM refresh is accomplished through the use of CAS before RAS refresh cycles with the refresh interval fully programmable In CAS before RAS refresh cycles the DRAM provides its own refresh address thus eliminating the need to generate an external refresh address The refresh cycle timing is fixed and satisfies the timing requirements for the highest system clock speeds During the refresh cycle WE is always driven high to prevent enabling of the test mode feature found in some DRAM devices All refresh cycles are transparent in that they take place between DRAM accesses without forcing t
116. B 3 illustrates the DRAM SIMM connection For On This Product Go to www freescale com Freescale Semiconductor 220 SIM72 52 DR RAS2 RAS3 DR RAS3 V V DR_RAS4 222 5 V DR RAS5 220 caso VV DR CASO 220 1 DR CAS DQ9 220 0010 A00 0011 220 0912 AW DR_A01 3 74ALS244 220 0914 l DR_A02 DQ15 0016 DR A03 DQ17 DQ18 DR A04 DR A05 DR A06 DR A07 DR A08 DR A09 DR A10 DR WE Figure B 3 DRAM SIMM Connection B 3 CONFIGURING THE FLASH EPROM The flash EPROM in this design demonstrates the methodology used to connect a typical PROM ROM or EPROM interface Different EPROM devices can be used with minimal or no changes required This design demonstrates four banks of flash memory connected to the MC68322 which provides 4M of main memory to support the core with instruction memory built in fonts and permanent data structures Figure B 4 illustrates the flash EPROM connection For On This Product Go to www freescale com Freescale Semiconductor 2 10 1 WOHd33 Usel4 t g 4 070460 070460 070362 070366 lt lt For More f
117. B HD Scanline To Banded bitmap Halftone Destination For Mort ON oduct to www freescale com Freescale Semiconductor MAT 13 1 2 Program Flow Control Program flow control graphic orders control the execution order for the display list JUMP allows the execution to change to a different point in the display list During banding it is common to build a display list along with several headers These headers contain a graphic order to set the parameters for the current band and a JUMP graphic order to move execution to the main body of the display list The STOP graphic order signals the end of the display list and normally results in an interrupt to the core 13 1 3 Bit Block Transfer Bit block transfer bitBLT graphic orders specify a rectangular bitmap transfer There are nine different bitBLT graphic orders that provide the nine combinations of destination bitmap and operand type Three of these control bitBLTs to frames three control bitBLTs to unbanded bit maps and three control bitBLTs to banded bit maps These graphic orders rely on certain parameters being previously set by initialization graphic orders 13 1 4 Expanded Bit Block Transfer There are six expanded bitBLT graphic orders that are used to manipulate and transfer low resolution bitmap images Two of these control expanded bitBLTs to frames two control expanded bitBLTs to unbanded bit
118. B SHD Opcode Byte Band number when graphic order is executed Long Word Destination logical bit address Word Frame width in bits Word Frame height in scanlines Long Word Source physical bit address Word Halftone X remainder Word Halftone Y remainder LongWord Halftone physical bit address of the starting pixel Note Denotes A Parameter That The MC68322 Updates When The Frame Crosses A Band Boundary The BLT2BB SHD graphic order causes the MC68322 to bitBLT a source frame to a destination banded bitmap and apply a halftone bitmap in the process The source halftone and destination pixels are combined as specified by the current BOOL SHD Boolean code The destination bitmap parameters must have been previously defined by the SET BBMAP graphic order The source frame warp is assumed to be the FW specified in the BLT2BB SHD graphic order unless a non zero source bitmap warp was previously defined by the SET SBMAP graphic order in which case the latter is used The halftone bitmap dimensions must have been previously defined by the SET HTBMAP graphic order During the processing of halftones wrapping occurs at the edges of the bitmap and this results in horizontal and vertical replication tiling of the bitmap to cover the entire bitBLT frame area Halftone tiled patterns are typically anchored to the page Thus a bitBLT may need to take on the halftone pattern starting at various points in the halftone bitmap depending o
119. BB D Opcode Byte Band number when graphic order is executed Long Word Destination logical bit address 28 of 32 bits Scanline table physical byte address word aligned Note Denotes A Parameter That The MC68322 Updates When The Frame Crosses A Band Boundary The SL2BB D graphic order causes the MC68322 to render a scanline table image to a banded bitmap The destination is manipulated as specified by the Boolean code last set by the SET BOOL D graphic order The SET BBMAP graphic order must previously define the destination banded bitmap parameters When the B2T flag is clear SLTA points to the most significant byte of the first bit string specifier in the table and DA refers to the pixel to which the displacement of the first bit string specifier is added not necessarily the first bit of the first run When the B2T flag is set SLTA points to the most significant byte of the last word of the final bit string specifier in the table and DA refers to the pixel that lies just past the end of the final bit string specifier run In neither case does SLTA point to the 0000 scanline table terminators Since the scanline table s bit string specifiers must be placed at word boundaries SLTA must be word aligned When a band fault is detected the MC68322 rewrites the scanline graphic order to update its parameters The BAND number is incremented or decremented when the B2T flag is set DA is written back corresponding to the pixel follow
120. BSY and STS are not sampled during command operations A CBSY setup half CCLK period B CMD sampled by the print engine Recovery cycle half CCLK period Figure 10 7 Command Operation MC68322 Supplies CCLK 10 3 2 2 CCLK SUPPLIED BY PRINT ENGINE In this mode the print engine interface expects eight rising edge transitions of CCLK from the print engine Because CCLK is asynchronous to CLK1 itis synchronized inside the MC68322 As a result the period of this signal can be no less than four CLK1 periods When a command operation is initiated CBS Y transitions to an active state and stays active until all command bits are transferred and hold time the value in the PCOMR s CCLK divisor field for the last command bit is satisfied Command data is transferred on CMD STS which remains in high impedance until the first falling edge of CCLK The command bit changes three CLK1 periods after every falling edge of the CCLK At the end of the transmission CMD STS is brought high for one CLK1 period and then returns to the high impedance state When CBSY transitions to an inactive state indicating the end of the command operation the PCIER s CMS bit is set to notify the core that the command has been sent thus causing a command sent interrupt event to occur The software should not try to write another command until this interrupt is received SBSY and STS which are used during status operations should not be as
121. Banded Bitmap 0 Page 13 50 13 27 Destination Scanline Transfer to Banded Bitmap 180 13 50 13 28 Halftone Destination Scanline Transfer to Banded Bitmap 0 Page 13 53 13 29 Halftone Destination Scanline Transfer to Banded Bitmap 180 Page 13 53 13 30 Destination Scanline Transfer to Frame 13 54 13 31 Halftone Destination Scanline Transfer to Frame 13 56 13 32 Destination Scanline Transfer to Unbanded Bitmap 13 57 13 33 Halftone Destination Scanline Transfer to Unbanded Bitmap 13 59 Glock AC 14 3 14 2 Reset AC TIMING ua aeter teni a 14 3 14 3 Read Access 2 2 1 9 14 5 14 4 Read Access 24 3 ee rat ere eed eee 14 5 14 5 Read Access 42 dq 14 6 14 6 Read Access 2 2 9 9 eus 14 6 14 7 Read Access 24 123 nee eee Re eed 14 7 1458 ACCESS ended 14 7 14 9 Read Access 2 6 1 35 eet pe deg va tnra tess 14 8 14 10 Read Access 44 13 9 14 8 14 11 Read A cess 6 2 51 3 4
122. Bx External Interrupt Enable External interrupts are enabled when set and disabled when cleared This bit affects the interrupt to the core but not the interrupt event in the STSx or REQx fields STSx External Interrupt Status This bit reflects the status of the corresponding IRQ signal after it is synchronized with CLK1 REQx External Interrupt Request This bit is set when an external interrupt event occurs To remove the interrupt the core should write 1 to the REQx bit If this bit and the ENBx bit are set an interrupt is posted Interrupt Level Register This field is used to set the interrupt level A level 7 is the highest priority and level 1 is the lowest priority Level 0 indicates that the interrupt is disabled MODEx External Interrupt Mode This field controls the external interrupt polarity and whether it is level sensitive or edge sensitive Table 5 2 lists the MODEx field encodings Table 5 2 External Interrupt Polarity ENCODING DESCRIPTION 0 Active Low Level Active High Level Falling Edge Transition Rising Edge Transition SENx External Interrupt Software Enable This bit is only used when the external interrupt is level sensitive is only set by the software and only cleared by the hardware It allows the software to control a level sensitive interrupt without using the ENBx bit The software cannot clear but it is set by the software and cleared by the hardware when a le
123. CK FRAME SEE NOTE EXECUTE EXCEPTION HANDLER OTHERWISE BEGIN INSTRUCTION EXECUTION EXIT NOTE These blocks vary for reset and interrupt exceptions Figure 5 5 General Exception Processing Flowchart For More ie ash M product Go to www freescale com Freescale Semiconductor During the first step the core makes internal copy of the internal status register SR except during the reset exception which does not make a copy of the internal status register Then the core changes to the supervisor mode by setting the S bit and inhibits tracing of the exception routine by clearing the T bit in the SR For the reset and interrupt exceptions the core also updates the interrupt priority mask in the internal status register During the second step the core determines the vector number for the exception and internal logic provides the vector number for all exceptions This vector number is used in the last step to calculate the address of the exception vector Please note that throughout this section vector numbers are given in decimal notation The third step is to save the current core contents for all exceptions other than the reset exception which does not stack information The core creates an exception stack frame on the active supervisor stack and fills it with information appropriate for the type of exception Other information can also be stacked depending on which
124. CP with RLE MODE 11 is enabled and data decompression is in progress INL INIT Low This bit is set when a high to low transition on INIT is reported in the PPIR INH INIT High This bit is set when a low to high transition on INIT is reported in the PPIR AFL AUTOFD Low This bit is set when a high to low transition on AUTOFD is reported in the PPIR AFH AUTOFD High This bit is set when a low to high transition on AUTOFD is reported in the PPIR STL STROBE Low This bit is set when a high to low transition on STROBE is reported in the PPIR STH STROBE High This bit is set when a low to high transition on STROBE is reported in the PPIR SNL SELECTIN Low This bit is set when a high to low transition on SELECTIN is reported in the PPIR SNH SELECTIN High This bit is set when a low to high transition on SELECTIN is reported in the PPIR For On This Product Go to www freescale com Freescale Semiconductor Vit Ew 9 2 HARDWARE HANDSHAKING The PPI supports three hardware handshaking modes for forward data transfers that are enabled and disabled by the software One mode supports forward data transfers during compatibility mode and the other two modes support forward data transfers during ECP mode Only one of the three modes can be enabled at a time or all modes can be disabled When disabled the software must assume full responsibility for handshaking and
125. ECTION 5 INTERRUPT AND EXCEPTION HANDLING The MC68322 supports two types of interrupts internal and external These interrupts are posted to the core through an internal interrupt controller which uses an exception processing routine to handle the interrupt The core s internal status register contains a 3 bit interrupt priority mask that ranges from level 0 to 7 level 7 being the highest mask level Interrupts are inhibited for all priority levels less than or equal to the current mask level Priority level 7 is a special case Level 7 interrupts cannot be inhibited by the interrupt priority mask thus providing a nonmaskable interrupt capability Level 7 interrupts can be generated in two ways First an interrupt is generated each time the interrupt event level changes from a level below level 7 Second a level 7 interrupt occurs if the interrupt request level is a 7 and the core priority mask is dropped from level 7 to a lower level by the execution of an instruction 5 1 INTERNAL INTERRUPTS The MC68322 modules function simultaneously and independently of the core At the completion of a module s operation the module is capable of posting an internal interrupt to the core through an internal interrupt controller For example the printer video controller PVC could post a page end interrupt to signal the core that it has finished rendering a page The controller ranks the interrupt based on a module s programmed interrupt p
126. F Figure 14 24 Print Engine Interface AC Timing 14 4 6 Interrupt Timing CHARACTERISTIC UNIT a NOTE IRQ1 IRQO asynchronous inputs and are synchronized internally by the MC68322 They require no setup hold time to be recognized for proper operation However to guarantee recognition of an input at a certain edge of CLK2 the input must satisfy the hold requirement IRQ0 IRQ1 Figure 14 25 Interrupt Interface AC Timing For Mors On This Product Go to www freescale com Freescale Semiconductor Me CR EE WEE WUT ILUV 14 4 7 Parallel Port Interface Timing CHARACTERISTIC UNIT PD7 PD0 ACK BUSY SELECT PERROR FAULT Output Valid from CLK2 PD7 PDO High Impedance from CLK2 PD7 PDO SELECTIN STROBE AUTOFD INIT Asynchronous Input Hold after CLK2 NOTE Denotes that 7 SELECTIN STROBE AUTOFD INIT are asynchronous inputs and are synchronized internally by the MC68322 They require no setup or hold time to be recognized for proper operation However to guarantee recognition of an input at a certain edge of CLK2 the input must satisfy the hold requirement SELECTIN STROBE AUTOFD INIT amp PD7 PDO INPUT ACK BUSY SELECT PERROR amp FAULT PD7 PDO0 OUTPUT Figure 14
127. Fe n n LEVEL RESERVED Figure 9 4 PPI Interrupt Event Register The following bits describe each of the parallel port interrupt events that can be posted by the PPI The first eight interrupt events signal level changes that occur at the host control signal input pins Note that these events are detected after the host inputs are synchronized optionally digitally filtered and recorded in the PPIR For On The Product Go to www freescale com Freescale Semiconductor Vit IVD Invalid Transition This bit is set when SELECTIN transitions from high to low in the middle of an ECP forward data transfer handshake sequence The invalid transition interrupt is posted if SELECTIN is low when STROBE is low or BUSY is high This event can be posted only when ECP is enabled CRD Command Received This bit is set when a command byte is latched into the PPIR s DATA field If ECP without RLE MODE 10 is enabled then a command received interrupt is posted when a run length or channel address is received If ECP with RLE MODE 11 is enabled then a command received interrupt is posted when a channel address is received This event can only be posted when ECP is enabled DRD Data Received This bit is set when data is latched into the PPIR s DATA field which occurs on every high to low transition of STROBE when the PPCR s PDE bit is clear This interrupt is also set if E
128. Freescale Semiconductor MC68322 Integrated Printer Processor User s Manual 1997 Motorola Inc All Rights Reserved Freescale Semiconductor Inc 2004 All rights reserved So freescale semiconductor Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com I
129. HXR and HYR must both be set to one The HA parameter defines a physical bit address within the halftone bitmap and must point to the upper left corner of the transfer frame HA must be consistent with HXR and HYR Related Graphic Orders SET BOOL SHD SET UBMAP SET HTBMAP For Mort ON oduct to www freescale com Freescale Semiconductor Inc MAT wives UNEXPANDED HALFTONE BITMAP SOURCE BITMAP 5 SW EXPANDED DESTINATION UNBANDED SOURCE BITMAP BITMAP XMUL DWU YMUL BOOL_SHD USED TO COMBINE FRAMES Figure 13 22 Expanded Source Halftone Destination bitBLT to Unbanded Bitmap For Mort 160322 On This Product Go to www freescale com Freescale Semiconductor MAT wires vu JUMP Jump to Graphic Order PARAMETERS DESCRIPTION 0x01 Byte JUMP Opcode 0x00 Byte Reserved GOA 28 of 32 bits Graphic order physical byte address The JUMP graphic order indicates a new byte address where the display list continues The MC68322 updates its internal display list pointer with the address following the graphic order and resumes execution at this address when it encounters the JUMP graphic order GOA must be a word aligned address with the least significant bit equal to zero If the first bit is equal to one the RGP forces it to zero For Mort RSE ON
130. IAL ACCESS NEXT ACCESS E Figure 7 2 DRAM Timing Mode 1 Read Cycle ROM Mode 0 10 0 ROW COLUMN COLUMN RAS5 0 PET CAS1 0 N MD15 0 DATA gt 22 DATA GE SINGLE CYCLE FAST PAGE CYCLE INITIAL ACCESS IDLE NEXT Figure 7 3 DRAM Timing Mode 1 Read Cycle ROM Mode 1 Note The IDLE state shown here will also occur at the end of a refresh cycle whenever the ROM mode is selected for at least one of the DRAM channels For MES ah BM M 2b oduct Go to www freescale com Freescale Semiconductor 7 1 2 3 ADDRESS DEMULTIPLEXING CIRCUIT The MC68322 multiplexes the addresses on the DRAM bus as required by standard DRAM devices To connect ROM to one of the DRAM channels a simple address demultiplexing circuit must be used The following circuit provides an example of how to implement this logic in a system 2 MBYTE DRAM gt ROM CIRCUIT RAS5 CE1 TO SECOND ROM gt 512K X 16 OPTIONAL CEO 74F00 LATCH LMA 9 MA 9 0 LMA 8 0 MD 15 0 68322 74415821 MAGO ROM 512K X 16 THE CIRCUIT FOR THE 74F00 SHOULD BE AS FOLLOWS SIGNALS ROM ADDRESS PINS MA 9 A 18 LATCH LMA 8 0 A 17 9 8 0 A 8 0 RAS5 Ej Figure
131. It is used to exchange command and status information between the print engine and the MC68322 The direction of this pin is programmable and engine dependent STS Status This input signal is used by the print engine to supply data to the MC68322 Data sent through this signal is synchronous with the CCLK 2 8 PRINT ENGINE VIDEO CONTROLLER INTERFACE The print engine video controller PVC interface consists of five signals designed to interface directly to most laser print engines and input output polarities are programmable The following signals are used to transfer data from the MC68322 to the print engine PIN NAME DESCRIPTION VCLK Video Shift Clock This input signal is a free running clock that is used to drive the video transfer The print engine or an onboard oscillator can supply VCLK FSYNC Frame Synchronize This input only signal indicates frame synchronization The print engine asserts the FSYNC signal to begin a page The active polarity of this signal is programmable LSYNC Line Synchronize This input signal indicates that the print engine is ready to accept data for the next scanline The active polarity of this signal is programmable PRINT Print Request This output signal indicates that the MC68322 is ready to begin printing The assertion of this signal initiates the printing process The active polarity of this pin is programmable VIDEO Video Data This output signal provides the serial video d
132. LU W lt ea gt Dn 16 16 32 MES 822 ae BM oduct to www freescale com Freescale Semiconductor wun Table 3 4 Instruction Set Summary Continued OPCODE OPERATION SYNTAX NOT Destination Destination OR lt gt ROL ROR Destination Rotated by count Destination ROd Dx Dy ROd lt data gt Dy ROd lt ea gt ROXL Destination Rotated with X by count Destination ROXd Dx Dy ROXR ROXd lt data gt Dy ROXd lt ea gt RTE If supervisor state then SP SR SP 2 5 4 SP restore state and deallocate stack according to SP else TRAP RTR SP 5 2 SP 5 4 SP SBCD Destination 107 Source 107 X Destination SBCD Dx Dy SBCD Ax Ay If condition true then 15 Destination else 05 Destination STOP If supervisor state then Immediate Data SR STOP else TRAP STOP 4 data SUB lt gt SUBI Destination Immediate Data Destination SUBX Destination Source X Destination SUBX Dx Dy SUBX Ax Ay SWAP Register 31 16 Register 15 0 SWAP Dn TAS Destination Tested Condition Codes 1 bit 7 of Destination TRAP 1 S bitofSR SSP 4 55 SSP SSP 2 SSP TRAP lt vector gt SR SSP Vector Address TRAPV If V then TRAP TRAPV P D UNLK An SP SP 5 4 5 An 1 Does Not Reset External Devices Or Internal Registers Has No Effect Any MC68322 M
133. MA controller for graphics unit operations Bus Interface Unit Dual bus architecture allows separate buses to function independently Distributed processing optimizes system performance Write buffer for 000 core enhances performance System Integration Module Eight Programmable Chip Selects 256K to 256M of address space Independently programmable timing parameters for each bank Qj Integrated system timer DRAM System Integration Module Supports 512K 2M and 8M DRAM bank sizes Directly controls up to 6 banks of DRAM supports up to 48M of DRAM Programmable transparent refresh of DRAM banks 9 Bursting DRAM interface General Purpose DMA Controller Module Provides high speed downloads to and from DRAM IEEE 1284 Parallel Port Controller Module DMA controller supports 2M sec bidirectional communication transfers 16 20 or 25 MHz Operation 160 Pin Plastic Quad Flat Packaging MC68322 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction 1 2 PROCESSORS AND MODULES To improve total system throughput and reduce part count board size and cost of system implementation the M68300 Family integrates intelligent peripheral modules with typical glue logic on chip The MC68322 consists of two processor units the 000 core and and six modules that assist them the PVC bus interface unit system integration m
134. MANDA Product Go to www freescale com _ Freescale Semiconductor Table 1 ICE Interface Signal Summary Continued INPUT ACTIVE ICE Interrupt Priority Level IPL2 1 Output A 1 1 ICE Signal Descriptions CLK1 INTERNAL CLOCK Output This signal is used for a 1x clock that is a buffered version of the clock to the 68 00 core processor Typically this signal is connected directly to the MC68000 ICE clock pin A27 1 A26 INTERNAL ADDRESS Input These signals are address bits that expand the addressing capability of the MC68ECOO0 core They are used by the internal system integration module internal registers and DRAM accesses For the most part these signals will not be used and should be pulled low UDS I LDS INTERNAL UPPER AND LOWER DATA STROBE Input These active low input signals control the flow of data on the data bus as specified in Table A 2 When R W is high the processor reads from the data bus as indicated and when it is low the processor writes to the data bus Typically these signals are connected directly to the MC68000 ICE Table A 2 Data Strobe Control of Data Bus 005 LDS D15 D8 07 00 High High No Valid Data No Valid Data Valid Data Bits Read 15 8 Valid Data Bits Read 7 0 No Valid Data Valid Data Bits Read 7 0 Valid Data Bits Read 15 8 No Valid Data Valid Data Bits Write 15 8 Valid Data Bi
135. MUL field which specifies the factor used to scale the unexpanded source bitmap in the Y dimension YMUL can equal any value from 0 15 which represents a scaling factor of 1 16 The YOFF field occupies the four most significant bits and indicates the number of scanlines to be clipped at the top or bottom edge of the expanded source bitmap depending on the value of the B2T flag When B2T is clear YOFF is defined from the top edge of the source bitmap When B2T is set YOFF is defined from the bottom edge YOFF ranges from 0 YMUL If YOFF is zero no clipping occurs at the top or bottom extent but if it is non zero YOFF number of scanlines at the top or bottom edge of the expanded bitmap are skipped and the next scanline is the first line transferred to the destination bitmap A band fault is detected when the transfer frame extends past the end of the destination bitmap which is defined by the EOBPA operand in the SET BBMAP graphic order When a band fault is detected the MC68322 rewrites the graphic order to update its operands The BAND number is incremented or decremented when the B2T flag is set DA and SA are repositioned to the starting pixel of the respective frame to be processed in the next band and YOFF is updated according to the current position in the expanded source bitmap Lastly FH is written back with the number of scanlines in the frame to be transferred Related Graphic Orders SET BOOL SD SET BBMAP For Mort
136. N CYCLE1 X COLUMNCYCLE2 RAS5 RASO 1 7 015 00 DATA VALID DATA VALID WE SINGLE CYCLE FAST PAGE CYCLE Figure 7 10 DRAM Timing Mode 0 Write Cycle For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor WVU 5 WRITE DATA WAIT WRITE DATA START ROW COLUMNCYCLE 1 COLUMNCYCLE2 RAS5 RASO CAS1 CASO 015 00 DATA VALID DATA VALID SINGLE CYCLE FAST CYCLE Figure 7 11 DRAM Timing Mode 1 Write Cycle START WAIT WRITE DATA WAIT WRITE DATA START 10 ROW COLUMN CYCLE 1 COLUMN CYCLE2 X RAS5 RASO 1 015 00 DATAVALID DATA VALID WE SINGLE CYCLE FAST PAGE CYCLE i E J amp Figure 7 12 DRAM Timing Mode 2 Write Cycle When a DRAM write cycle is initiated by the core the data is latched into a buffer and an early internal DTACK is generated to the core Subsequent write cycles to DRAM are delayed if the write buffer is full The write buffer allows the core to execute the next instruction s while waiting for the word to be written to DRAM thus increasing the MC68322 s performance 7 4 4 DRAM Bus Arbitration Arbitration for the DRAM bus is performed with strict priorities If the bus is busy the core will be delayed a maxi
137. NDED XMUL SOURCE BITMAP BITMAP DWU gt YMUL BOOL_SD USED TO COMBINE FRAMES Figure 13 21 Expanded Source Destination bitBLT To Unbanded Bitmap For 12 5858 On This broduct Go to www freescale com Freescale Semiconductor Inc MAP wires BLT2UB_XHD Expanded Source Halftone Destination bitBLT to Unbanded Bitmap PARAMETERS DESCRIPTION Byte BLT2UB_XHD Opcode Byte Reserved LongWord Destination physical bit address Word Destination frame width in bits Word Destination frame height in scanlines LongWord Unexpanded source physical bit address Word Unexpanded source frame warp in bits XOFF XMUL Two 4 bit Fields X offset and X multiplier in bits YOFF YMUL Two 4 bit Fields Y offset and Y multiplier in scanlines HXR Word Halftone X remainder HYR Word Halftone Y remainder HA LongWord Halftone physical bit address of the starting pixel The BLT2UB_XHD graphic order transfers a low resolution source frame to a destination unbanded bitmap and applies a halftone bitmap in the process Before being combined with the destination the source frame is scaled to match the resolution of the destination bitmap This results in an intermediate expanded source bitmap The pixels of the expanded source halftone and destination bit maps are combined as specified by the Boolean value set in the last SET_BOOL_SHD order The SET_UBMAP gr
138. O O O O O 000 NOTES 1 Component side is shown 2 Dimensions are in inches unless otherwise specified 3 Tolerances Hole location and diameter 0 010 4 Connectors J51 J53 J54 and J55 are located on the component side of the PCB 5 Connector J41 is located on the solder side of the PCB Figure A 6 ICE Adaptor Board For On This Product Go to www freescale com Freescale Semiconductor ni ee Ue ciolieevis er 454 GND GND GND GND GND 10 GND 9 MA8 SBY CBY NC CCK MA5 MA4 STS CMD MA3 MA2 DRQ DAK 0 A1 NC NC A2 A3 SIN AFD A4 A5 RT MC68322 PGA 46 INI PER A8 A9 BSY ACK A10 A11 PD7 PD6 A12 A13 PD5 PD4 A14 A15 PD3 PD2 A16 A17 PD1 PDO 18 19 5 NC A20 A21 ERST RST A22 A23 GND GND A24 A25 GND GND GND GND J52 J55 GND GND CK1 DLE TU 1 05 033 034 UDS AVC 0 FC2 2 lt W1 JUMPER IN GND GND 74 573 74ALS573 ICE DISABLED JUMPER OUT RP32 U35 U36 ICE ENABLED R31 R23 RP31 MC68322 ICE 031 MC68HC000 16P 3080 94 006 08 gt SILK1 Figure 7 ICE Adaptor Board Silkscreen R27 R28 For On This Product Go to www freescale com Freescale Semiconductor nin ull cieolieevis nv nave A 3 1 In Circuit Emulation Interface wes wur
139. OP SBSY STS PCLK CBSY PRINT RESERVED CPRDY VIDEO CMD CCLK RESERVED PRFD E T 20K Q 2 74714 9 8 LL CPRDY gt gt 74714 2 150K Q PRED pRED ZA 0 001pF AUXILIARY POWER CONIM 45V 5V 5V LED8 FP LED9 Figure B 10 Print Engine Interface For More FS 8322 UBER oM roduct Go to www freescale com Freescale Semiconductor 9 MC68322 MEMORY INITIALIZATION EXAMPLE The following code example sets up memory map illustrated in Figure B 11 0 0 DRAM BANK 0 0x80000 UNUSED 0x600000 CHIP SELECT BANK 0 See Note 0x700000 DRAM BANK 2 See Note 0x800000 DRAM BANK 3 0xA00000 DRAM BANK 4 0xC00000 DRAM BANK 5 0xE00000 SERIAL DEVICE CHIP SELECT BANK 6 0 00000 NOTE chip select banks have priority over the DRAM banks Figure B 11 Initialized Memory Map From Code Example For More fnformation On This Product Go to www freescale com Freescale Semiconductor rAMpMgUVuuvimm B 10 MC68322 INTERNAL REGISTERS SAMPLE CODE BASE322 EQU S00fff000 ADDRO EQU 50 TIMINGO EQU 2 ADDR1 EQU 10 512 ADDR2 EQU 20 TIMING2 EQU 22 ADDR3 EQU 30 532 ADDR4 EQU 40 TIMING4 EQU 42 ADDR5 EQU 50 5 552 ADDR6 EQU 5
140. PER DIRECTION DIRECTION OUTPUT HOPPER HOPPER Figure 1 8 Duplex Laser Printer Paper Path Since the image is placed on both sides of the page in duplex printing image orientation is important When the page is turned to read either side both images must appear right side up To achieve the correct image orientation the physical characteristics of the print engine and the format of the printed page must be taken into consideration For example it is important to know how the page is turned over to expose both sides to the drum inside the print engine as well as how the page is going to be bound in the completed document Images printed on the opposite side of a page may have to be rotated 180 Understandably these types of pages are called 180 pages They require pixel data to be transmitted from the page image bitmap starting at the bottom right corner and then continuing from right to left bottom to top Pages that do not require this type of rotation are called 0 pages they are transmitted starting at the top left corner and then continuing from left to right top to bottom In banding applications 180 pages require special attention Since the page image is transmitted to the print engine in bottom to top order bands must be generated in this order too The MC68322 directly supports 180 page rendering and printing as required by duplex banding applications The RGP and graphic order instruc
141. Page For 12 5858 On This broduct Go to www freescale com __Freescale Semiconductor MAP wires BLT2BB XD Expanded Source Destination bitBLT to Banded Bitmap PARAMETERS sm DESCRIPTION 0x36 Byte BLT2BB XD Opcode BAND Byte Band number when graphic order is executed DA Long Word Destination logical bit address FW Word Destination frame width in bits FH Word Destination frame height in scanlines SA Long Word Unexpanded source physical bit address SW Word Unexpanded source frame warp in bits XOFF XMUL Two 4 bit Fields X offset and X multiplier in bits YOFF YMUL Two 4 bit Fields Y offset and Y multiplier in scanlines Note Denotes A Parameter That The MC68322 Updates When The Frame Crosses A Band Boundary The BLT2BB_XD graphic order transfers a low resolution source frame to a destination banded bitmap Before being combined with the destination the source frame is scaled to match the resolution of the destination bitmap which results in an intermediate expanded source bitmap The pixels of the expanded source and destination bit maps are combined as specified by the Boolean code set in the last SET BOOL SD order The destination bitmap parameters must have been previously defined by the SET BBMAP graphic order DA specifies the logical bit address of the area or transfer frame that begins in the destination banded bitmap The logical bit address is
142. RS DESCRIPTION 0x00 Byte STOP Opcode 0x00 Byte Reserved The STOP graphic order indicates the end of a display list The MC68322 RGP halts execution and generates an RGP done interrupt event when the STOP graphic order is encountered For Mort RSE ON ANA oduct Go to www freescale com Freescale Semiconductor SECTION 14 ELECTRICAL AND THERMAL CHARACTERISTICS This section contains information on the maximum rating and thermal characteristics for the MC68322 which is subject to change For the most recent specifications contact a Freescale sales office 14 1 MAXIMUM RATINGS CHARACTERISTIC SYMBOL VALUE UNIT This ia 5 D iid against damage due to high static voltages Supply Voltage 12 0 310 7 0 or electrical fields However it is advised that normal precautions be taken to avoid Input Voltage 4 2 VOR application of any voltages higher than Maximum Operating Junction Temperature maximum rated voltages to this m 5 S high impedance circuit Reliability of Minimum operating Ambien Temperature 9090 operation is enhanced if unused inputs Storage Temperature Range 55 to 150 n to S voltage level e g either NOTES 1 Permanent damage can occur if maximum ratings are exceeded Exposure to voltages or currents in excess of recommended values affects device reliability Device modules may not operate normally while being exposed to electrical extremes 2 Althoug
143. S W ea Dn32 16 16 169 DIVU Destination Source Destination DIVU W lt ea gt Dn32 16 16r 16q For On This Product Go to www freescale com Freescale Semiconductor wus Table 3 4 Instruction Set Summary Continued Source Destination Destination EORI Immediate Data Destination Destination EXG EXG Dx Dy EXG Ax Ay EXG Dx Ay EXG Ay Dx Destination Sign Extended Destination EXT WDn extend byte to word EXT LDn extend word to long word ILLEGAL SSP 4 89 SSP ILLEGAL SSP 2 SSP SR Illegal Instruction Vector Address Destination Address lt gt SP 4 SP a lt ea gt Destination Address LINK SP 4 SP LINK An lt displacement gt SP An SP dy SP LSL LSR Destination Shifted by count Destination LSd Dx Dy LSd lt data gt Dy LSd lt ea gt MOVE to SR If supervisor state then Source SR else TRAP MOVE lt a gt SR lt ea gt SR MOVE USP If supervisor state then USP US else TRAP LI USP An MOVE An USP MOVEM Registers Destination MOVEM lt list gt lt ea gt Source Registers MOVEM ea list MOVEP Source Destination MOVEP 4 d Immediate Data Destination Data Destination lt data gt Dn MULS pee __________ x Destination Destination MULS W lt ea gt Dn 16 16 MULU Source x Destination Destination MU
144. SARY This section provides the definitions to some of the key terms used in this document address demunging Reversal of a munge operation on an address This has the effect of restoring the original address address munging Address modification in a way that the low order three bits of the address are exclusive OR ed with a three bit value that depends on the length of the operand refer to the PowerPC Microprocessor Family The Programming Environments MPGFPE AD atomic cycle If multiple bus transactions by a bus master occur in a sequence where the master retains ownership of the bus during the duration of the sequence thus preventing other master s from transferring in the middle of the sequence the sequence is considered atomic autobaud The process of determining a serial data rate by timing the width of a single bit big endian An ordering of the bytes within a word where the least significant byte is at the highest address and vice versa For example a 32 bit wide data bus with big endian the least significant byte is located on data bus bits 24 31 and the most significant byte is on bits 0 7 blockage The interval from the time an instruction begins execution until its execution unit is available for a subsequent instruction AND has 1 clock latency and 1 clock blockage boundedly undefined Results of a given not defined instruction are boundedly undefined if they could have been achieved by executin
145. SER S MANUAL 1 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction In addition to width and height dimensions an unpacked bitmap also possesses an attribute known as the bitmap warp which is the distance between the beginning of each consecutive scanline The bitmap warp is the value used to obtain Y dimension movement within the bitmap For example to move from one pixel to a pixel in the same column but in the next lower scanline simply add the bitmap warp to the current position in memory A packed bitmap also has a bitmap warp that is equal to the width of the bitmap 1 4 3 Banding Banding is a process in which the page to be printed is constructed in a series of partial page images or bands To better accommodate banding the MC68322 allows the page image to be represented in an intermediate form In this intermediate form the page image is represented by a series of graphic orders which are collectively called a display list and are maintained in memory The PDL or PCL emulator firmware running on the core generates the display list before the print engine begins the actual printing process The RGP executes the graphic orders in the display list to build the bitmapped image in bands as the print engine is started Generally band n 1 is being constructed while band n is being output to the print engine 1 4 4 Halftoning Halftoning involves applying a pattern or
146. Semiconductor SECTION 15 ORDERING INFORMATION AND MECHANICAL DATA This section contains MC68322 ordering information pin assignments and package dimensions 15 1 ORDERING INFORMATION The following table provides ordering information pertaining to the MC68322 package types frequencies temperatures and Freescale order numbers PACKAGE TYPE FREQUENCY TEMPERATURE ORDER NUMBER 160 Pin QFP 25 MHz 0 to 70 C MC68322FT25 FT Suffix 20 MHz MC68322FT20 16 667 MHz MC68322FT16 15 2 PIN ASSIGNMENT The following illustrates the MC68322 pin assignments for the 160 PQFP package For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor PEE ANM EU MDO 10 MA9 MA8 MA7 6 5 GND MA4 2 MA1 Vcc SELECTIN GND AUTOFD FAULT SELECT INIT PERROR Voc BUSY ACK PD7 PD6 GND PD5 x 68322 VIEW UU UU UU UU E p 5 o lolo gt 6 Io IO IO 5 g Figure 15 1 MC68322 160 Lead Plastic Quad Flat Pack PQFP For On The Product Go to www freescale com O Jo 5 In 81 Freescale Semiconductor Inc NO ER 15 3 MECHANICAL DATA 121 160 DETAIL A ca DETAIL A
147. T 2 gt SET TIME 3 3 gt ACC TIME 4 HLD 0 gt HLD TIME NOTE There is one CLK1 of synchronization delay on WAIT Figure 6 5 Special Asynchronous Read or Write Timing Diagram For More MES M V b roduct Go to www freescale com Freescale Semiconductor SECTION 7 DRAM CONTROLLER The MC68322 supports fast page mode DRAM devices However nibble mode and static column DRAM devices are not supported The MC68322 directly supports up to six banks of DRAM with bank sizes of 256Kbits x 16 1Mbit x 16 and 4Mbits x 16 All DRAM sizes a fixed data width of one word of 16 bits Each of the six banks can support 512K to 8M The RISC graphics processor printer video controller PVC DMAs and 000 core can all make accesses through the DRAM controller The RGP and PVC use burst cycle accesses to maximize DRAM bus bandwidth while the core does not burst to or from DRAM All burst cycles from these modules occur within 256 word DRAM page boundaries Core write accesses to the DRAM controller use data pipelining that allows for a reduction of internal bus arbitration delays 7 1 DRAM REGISTERS AND BANKS 7 1 1 Base Address and Size Fields Each of the six DRAM banks correspond to an internal DRAM register These six DRAM registers DRAM5 DRAMO word sized and indicate the DRAM bank s size location Figure 7 1 illustrates these registers 00 100 00
148. TO COMBINE FRAMES EOBPA lt oy EXPANDED SOURCE BITMAP Figure 13 11 Expanded Source Halftone Destination bitBLT To Banded Bitmap 0 Page mn SW EXPANDED DESTINATION SOURCE BITMAP BANDED BITMAP lt FW gt BOOL_SHD USED TO COMBINE FRAMES DWB Figure 13 12 Expanded Source Halftone Destination bitBLT To Banded Bitmap 180 Page For 12 5858 On This broduct Go to www freescale com Freescale Semiconductor BLT2F D Destination Only bitBLT to Frame PARAMETERS s DESCRIPTION Byte 2 D Opcode Byte Reserved LongWord Destination physical bit address Word Frame width in bits Word Frame height in scanlines The BLT2F D graphic order causes the MC68322 to modify a destination frame bitmap The destination pixels are manipulated as specified by the current BOOL D Boolean code The destination bitmap warp is taken to be the FW specified in the BLT2F D graphic order The destination physical bit address DA must point to the upper left corner of the frame Related Graphic Orders SET BOOL D DESTINATION FRAME BOOL D APPLIED TO FRAME FW Figure 13 13 Destination bitBLT to Frame For Mort farsi Shon On This Product Go to www freescale com Freescale Semiconductor wives BLT2F SD Source Destination bitBLT to Frame PARAMETERS DESCRIPTION
149. UTOFD was latched high and if clear AUTOFD was latched low This is a read only bit so writing CMD has no effect For On The Product Go to www freescale com Freescale Semiconductor Vit This field is 8 bit read write field When read DATA provides the latched logic levels on the parallel port data bus when STROBE last transitioned from high to low with the PPCR s PDE clear When written the value defines the logic levels to be driven by the MC68322 when PD7 PDO is enabled by setting the PDE bit The most significant bit of the DATA field corresponds to PD7 and the least significant bit to PDO The CMD DATA fields latch the logic levels on the parallel port data bus PD7 PDO and AUTOFD pins which is used to indicate command bytes during ECP mode forward data transfers The CMD and DATA fields should not be read while the PDMA channel is enabled doing so clears the PDMA request INT INIT Status Read only Indicates the level read on INIT after synchronization and optional digital filtering AFD AUTOFD Status Read only Indicates the level read on AUTOFD after synchronization and optional digital filtering STR STROBE Status Read only Indicates the level read on STROBE after synchronization and optional digital filtering SIN SELECTIN Status Read only Indicates the level read on SELECTIN after synchronization and optional digita
150. WORD CONFIGURATION OOFFF216 GDMA CHIP SELECT TRANSFER ADDRESS LOW WORD REGISTERS OOFFF218 1 GDMA TRANSFER COUNT 00 200 RESERVED Figure 8 1 Configuration Registers 8 1 1 Transfer Address Fields The PDMA configuration register contains the PDMA DRAM transfer address field The configuration register contains two transfer address fields GDMA DRAM transfer address GDTA and GDMA chip select transfer address GCSTA These fields define the base address for the beginning of the transfer and they cannot be written while the BSY bit in the active channel s interrupt event register is set The transfer address fields support the entire 256M address range of the MC68322 The GDTA field increments during a DMA transfer For word sized data transfers using the GDMA channel the transfer address is incremented after every word is transferred When receiving byte sized data the data is packed into words prior to accessing DRAM and the address is incremented after every full word is transferred to DRAM Likewise for sending byte sized data a word access to DRAM is made the address in incremented and the data is sent unpacked as bytes to the MC68322 bus All byte sized data packing is organized as big endian data The MC68322 bus address used for the GDMA channel is fixed and not incremented The transfer address for the MC68322 bus is used to access one of eight possib
151. a band fault occurs 13 5 GRAPHIC ORDER DESCRIPTIONS Table 13 2 contains the graphic orders sorted by opcode value with the page number they appear on Table 13 2 Graphic Orders Sorted by Opcode OPCODE GRAPHIC ORDER PAGE OPCODE GRAPHIC ORDER PAGE For Mort ON oduct to www freescale com Freescale Semiconductor Inc wy BLT2BB D Destination Only bitBLT to Banded Bitmap PARAMETERS s DESCRIPTION Byte BLT2BB D Opcode Byte Band number when graphic order is executed Long Word Destination logical bit address Word Frame width in bits Word Frame height in scanlines Note Denotes A Parameter That The MC68322 Updates When The Frame Crosses A Band Boundary The BLT2BB D graphic order causes the MC68322 to modify a frame of a destination banded bitmap The destination pixels are manipulated as specified by the current BOOL D Boolean code The destination bitmap parameters must have been previously defined by the SET BBMAP graphic order DA specifies the logical bit address of the area or transfer frame that starts in the destination banded bitmap The logical bit address is converted to a physical bit address by adding the PSUBL value set by the SET BBMAP graphic order The start of the transfer frame must be within the bounds of the banded bitmap but the end of the transfer frame may extend past the end of the bitmap
152. a write cycle On the other hand it acts as an output when one of the following conditions occur When data is sent to an device When an external bus master is reading data During an interrupt acknowledge cycle the data bus is not used For More fnformation On This Product Go to www freescale com Freescale Semiconductor RV II UNI IZ 2 3 SYSTEM INTERFACE 2 3 1 Reset RESET The RESET signal is an input only signal that causes a total system reset thus resetting the processor and external devices This is different than a reset caused by the reset instruction which does not reset external devices or internal registers In effect the internal state of the processor is not affected Regardless using the reset instruction on the MC68322 is not recommended 2 3 2 System Clock To develop the internal clocks needed by the 68322 2 is internally buffered The MC68322 divides the system clock CLK2 frequency by two to generate CLK1 signal that is used internally by the core and most modules The input frequency of the CLK2 signal is twice the system frequency CLK2 can be slowed or stopped to reduce device and system power consumption However CLK2 is necessary to refresh DRAM and complete removal of the CLK2 signal can cause a loss of data in DRAM The internal CLK1 signal functions continuously through reset The phase relationship between CLK1 and CLK2 is determined by the t
153. abled If the MODE field is reprogrammed during decompression decompression continues and RLD remains set until the operation is complete RLD is also cleared when RST is issued ABT Abort This bit causes the PPI to use SELECTIN to detect when the host suddenly aborts a reverse transfer and returns to compatibility mode If ABT is set a low level on SELECTIN causes the PDE bit to be cleared and the PD7 PDO output drivers to be three stated In fact if ABT is set and SELECTIN is low setting the PDE bit has no effect This protection logic as with all internal PPI logic operates on a synchronized and optionally digitally filtered SELECTIN that is latched into the PPIR For On The Product Go to www freescale com Freescale Semiconductor Vit PDE Parallel Port Data Bus Output Enable This bit performs two functions controls the state of the three state output buffers and qualifies the latching of data from the output drivers into the PPIR s DATA field When clear PDE disables the PD7 PDO output buffers and allows data to be latched into the DATA field on every high to low transition of STROBE When set PDE enables the PD7 PDO output buffers preventing data from being latched into the DATA field In this state the DATA field is unaffected by transitions on STROBE Setting the ABT bit affects the operation of PDE If the ABT bit is set SELECTIN must remain high to all
154. acteristics GM tied akon 14 1 DG Electrical Specifications e recie ford 14 2 AC Electrical Specifications dictata nd 14 3 Clock and Reset Timing 222 2 1 441 14 3 MC68322 Bus Timing e 14 4 BRAM TIMING eme reb modd min brides 14 12 ID NIA TITRE 14 13 Print Engine Interface Timing 200000 14 14 interrupt oe tede Dir 14 16 Parallel Port Interface Timing 14 17 External Bus Master Timing 14 18 Section 15 Ordering Information and Mechanical Data Ordering Information ascii oa acto qid dd Poi opted 15 1 PIM ASSIQDETOD 15 1 Mechanical Data 15 3 In Circuit Emulation Interface ICE Interface Signals condici etu tme A 1 ICE Signal Descriptions 00 212 A 2 ICE Adaptor Board Design 1 0011 A 4 ICE Adaptor Board Schematics A 6 In Circuit Emulation Interface 2 A 12 ICE Pin Assignment 16 For Mare Un This Product Go to www freescale com Freescale Semiconductor TABLE OF CONTENTS Continued Pa
155. all the data has been transferred the destination counter decrements to zero a flush request is posted or an error occurs The GDMA supports bidirectional byte and word sized data transfers between external DMA devices such as I O and DRAM The GDMA transfers to or from a single address on the MC68322 bus while automatically incrementing the address on the memory address bus 10 This provides a high speed method of transferring data to or from a peripheral or DRAM The PDMA operates like the GDMA except that all transfers occur between the parallel port interface and DRAM In addition it is designed to support only byte sized data transfers For 11093259 MANDA Product Go to www freescale com Freescale Semiconductor 8 1 CONFIGURATION REGISTERS The interface provides two internal memory mapped configuration register sets called PDMA and GDMA These registers configure each DMA channel and provide programmability for transfer address and count Figure 8 1 illustrates the DMA interface registers 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0000 PDMA DRAM TRANSFER ADDRESS HIGH WORD OOFFF202 PDMA DRAM TRANSFER ADDRESS LOW WORD CONFIGURATION OOFFF204 Ie PDMA TRANSFER COUNT REGISTERS 00 210 0000 DRAM TRANSFER ADDRESS HIGH WORD OOFFF212 GDMA DRAM TRANSFER ADDRESS LOW WORD OOFFF214 0000 GDMA CHIP SELECT TRANSFER ADDRESS HIGH
156. am counter is the address of the first word of the instruction causing the privilege violation Finally instruction execution commences at the address in the privilege violation exception vector 5 4 2 6 TRACING To aid in program development the core includes a facility to allow tracing after each instruction When tracing is enabled an exception is forced after the execution of each instruction Thus a debugging program can monitor the execution of the program under test The trace facility is controlled by the T bit in the supervisor portion of the internal status register If the T bit is cleared tracing is disabled and instruction execution proceeds from instruction to instruction as normal If the T bit is set on at the beginning of an instruction s execution a trace exception is generated after the completion of the instruction If the instruction is not executed because an interrupt is taken or because the instruction is illegal or privileged the trace exception does not occur The trace exception also does not occur if the instruction is aborted by a reset bus error or address error exception If the instruction is executed and an interrupt is pending on completion the trace exception is processed before the interrupt exception During the execution of the instruction if an exception is forced by that instruction the exception processing for the instruction exception occurs before that of the trace exception For
157. and handshakes with the printer to transmit the video data The memory subsystem contains a data fetch controller an 8 word deep FIFO and many counters It interfaces to the core through a set of memory mapped registers called the printer control block The video subsystem s task is to interface with the print engine and serialize and transmit video data It contains a video interface controller a 16 bit shift register a phase locked loop PLL clock circuit and some counters The PLL video clock divisor divides the VCLK input by 32 24 16 12 8 or 4 to produce the dot clock for the PVC This is accomplished internally by using a prescaler and by using either the rising edge or both edges of the clock for the PLL This feature allows for direct support of multiple resolutions using a single external oscillator For example the PVC can transmit 300 x 300 600 x 300 600 x 600 or 1200 x 600 resolution page images using the same VCLK input frequency For 11093259 MANDA Product Go to www freescale com Freescale Semiconductor WEI The print engine interface is capable of sending and receiving information to and from a print engine which is done at the same time as all other operations within the MC68322 This transmission and reception of information is synchronous either to the clock supplied by the interface or to the clock supplied by the print engine For transmitting video data the PVC
158. anlines to be clipped at the top edge of the expanded source bitmap YOFF ranges from 0 YMUL If YOFF is zero no clipping occurs at the top or bottom extent but if it is non zero YOFF number of scanlines at the top edge of the expanded bitmap are skipped and the next scanline is the first one transferred to the destination bitmap Related Graphic Orders SET BOOL SD UNEXPANDED SOURCE BITMAP SW EXPANDED ymuL SOURCE BITMAP TN lt gt D YMUL BOOL_SD USED TO COMBINE FRAMES 46 gt FW Figure 13 16 Expanded Source Destination bitBLT To Frame For 12 5858 On This broduct Go to www freescale com Freescale Semiconductor Inc IARE ANI S BLT2F_XHD Expanded Source Halftone Destination bitBLT to Banded Bitmap PARAMETERS DESCRIPTION Byte BLT2F_XHD Opcode Byte Reserved Long Word Destination physical bit address Word Destination frame width in bits Word Destination frame height in scanlines Long Word Unexpanded source physical bit address Word Unexpanded source frame warp in bits XOFF XMUL Two 4 bit Fields X offset and X multiplier in bits YOFF YMUL Two 4 bit Fields Y offset and Y multiplier in scanlines HXR Word Halftone X remainder HYR Word Halftone Y remainder HA Long Word Halftone physical bit address of the starting pixel The BLT2F_XHD graphic order transfers a low resolution source frame to a des
159. aphic order must previously define the destination bitmap warp and the SET_HTBMAP graphic order must do the same for the halftone bitmap dimensions During the processing of halftones wrapping occurs at the edges of the bitmap and this results in horizontal and vertical replication tiling of the bitmap to cover the entire destination frame area The DA parameter specifies the physical bit address of the area or transfer frame within the destination unbanded bitmap The entire transfer frame must be within the bounds of the banded bitmap DA must point to the upper left corner of the transfer frame The warp of the destination unbanded bitmap is set by the SET UBMAP graphic order which allows the bitmap to be packed or unpacked The FW and FH parameters define the area of the destination bitmap on which the operation is performed FW is the frame width in bits and at a maximum equals the quantity W x XMUL 1 where W is the width of the unexpanded source bitmap FH is the frame height in scanlines and at a maximum equals the quantity H x YMUL 1 where is the height of the unexpanded source bitmap Specifying FW and FH as defined above causes the entire expanded source image to be combined with the destination bitmap Specifying an FW and or FH value less than the values defined by the above equations causes only a portion of the expanded source frame to be applied to the destination When used in combination with XOFF and YOFF clipping can be a
160. are held off if the write buffer is full The write buffer allows the core to execute the next instructions while waiting for data to be written to DRAM thus increasing the processor s performance Figure 4 7 illustrates the word and byte write cycle timing diagram to DRAM For On This Product Go to www freescale com Freescale Semiconductor walle 50 52 54 56 50 52 54 on UDS MA10 MA0 ROW RAS5 RAS0 MD15 MD0 WRITE DATA WE NOTE UDS and DTACK are internal signals only Figure 4 7 Word Write Cycle Timing Diagram to DRAM 4 3 INTERRUPT ACKNOWLEDGE BUS CYCLE Whenever an interrupt is generated by one of the modules on the MC68322 or when an external interrupt arrives a bit will be set in the corresponding interrupt event register and the internal IPLX signals will be asserted according to the level programmed for that module In response to these active internal IPLx signals the core transparently initiates an interrupt acknowledge cycle During this cycle the core sets all internal function code signals 2 high displays the interrupt level on internal 1 drives 23 4 and the internal AO high and initiates a read cycle All MC68322 interrupts are autovectored During the interrupt acknowledge bus cycle with AS detected an internal AVEC signal is asserted to the core as an indication that the interrupt is an automatic vector i
161. at way during operation A 2 ICE ADAPTOR BOARD DESIGN In a typical system the logic board contains an MC68322 and a PGA connector around the 160 pin QFP MC68322 The PGA connects directly to all the signals of the MC68322 The user plugs the ICE interface into this PGA connector which asserts the HI Z input pin on the MC68322 on the logic board thereby forcing it to three state With the MC68322 three stated the MC68322 ICE on the ICE interface has control of all the signals on the logic board The MC68322 ICE takes the place of the MC68322 in the system when the ICE interface is installed Normally the ICEN input pin on the MC68322 ICE is connected to ground which disables the internal core and uses an MC68000 ICE for the processor For diagnostic purposes if ICEN is connected high on the ICE module then the internal core is used When an MC68000 ICE is used 1 27 1 26 to the MC68322 ICE are tied to ground An MC68000 ICE can only access the lower 64M of memory but an MC68020 ICE can be used instead If an MC68020 ICE is used then 27 26 are driven by the MC68020 ICE which can access the entire 256M of memory Figure A 1 illustrates the connection between the ICE interface and the logic board For On This Product Go to www freescale com Freescale Semiconductor Inc ww neis ICE MODULE LOGIC BOARD PGA CONNECTOR MC68000 ICE CONNECTOR 64 PIN DIP MC68322 ICE 2
162. ata to the printer The default polarity is low for active video and high for inactive video The VIDEO output driver can sink and source 24 mA The active polarity of this signal is programmable For On This Product Go to www freescale com Freescale Semiconductor wry weoviivuvins 2 9 PARALLEL PORT INTERFACE The MC68322 has 17 pins dedicated to parallel port communications These pins are designed to interface to an IEEE 1284 compatible or compliant host and meet all electrical driver receiver requirements for Level 2 compliance All inputs are TTL compatible and received with Schmitt triggers with over 200 mV of hysteresis All outputs are symmetrical and can sink and source 16 mA at 0 4 and 3 0 V respectively This provides a direct connection through series resistors between the MC68322 and the parallel port connector thus no external buffering or latching logic is required The following signal descriptions are for compatibility mode operation only Control signals carry different meanings when other IEEE 1284 modes are used When other modes are discussed the IEEE 1284 signal name is provided in parentheses following the MC68322 pin name Applications that do not require a parallel port can use these pins as general purpose individually controllable pins PIN NAME DESCRIPTION PD7 PDO Parallel Port Data Bus This 8 bit bidirectional three stateable b
163. ata transfer is complete When EDTACKis recognized during a read cycle the external bus master latches the data and terminates the bus cycle When EDTACKis recognized during a write cycle the bus cycle is terminated Bus Request This active low input is ORed with all other devices that can be bus masters This active low input signal informs the core that another device is ready to be the bus master Bus Grant This active low output indicates to all other potential bus masters that the MC68322 bus is available BG will assert after the assertion of BR but only after all bus cycles have terminated Chip Select These signals are output only and can be programmed to provide from 256K to 64M decode These signals continue to function as they are programmed when an alternate bus master has control of the MC68322 bus Read This signal is an output only strobe that is asserted during a read operation on the MC68322 bus A read cycle can be initiated by the core internal DMA or external bus master The read strobe remains negated during an MC68322 bus write cycle WRU Upper Write Strobe This strobe is an output only signal that is asserted during a write operation on the MC68322 bus A write cycle can be initiated by the core internal DMA or external bus master The upper write strobe asserts during all word write operations and during byte write operations to the upper portion of the data bus D15 D8 WRU remains negated dur
164. ate Data Addressing Immediate DATA Next Word s Quick Immediate Inherent Data Implied Addressing Implied Register EA SR USP SSP For More MGG Dana RER 2b oduct Go to www Freescale Semiconductor 3 3 INSTRUCTION SET SUMMARY Table 3 3 lists the notational conventions used throughout this manual and Table 3 4 summarizes the core instruction set by opcode In the syntax descriptions the left operand is the source operand and the right operand is the destination operand Table 3 3 Notational Conventions lt gt sign extended All bits of the upper portion are made equal to the high order bit of the lower portion lt operand gt lt operand gt shifted The source operand is shifted by the number of count by lt count gt lt gt rotated The source operand is rotated by the number of count by lt count gt bit number of lt operand gt Selects a single bit of the operand OTHER OPERATIONS RAP 1 T S bit of SR SSP 4 SSP PC SSP SSP 2 SSP SR 55 Vector Address Enter the stopped state waiting for interrupts operand 40 The operand is BCD operations are performed in decimal If condition Test the condition If true the operations after then are performed If the condition is false and the optional else then operations clause is present the operations after else are performed If the conditi
165. ation bitBLT to Unbanded Bitmap For 12 5858 On This broduct Go to www freescale com __Freescale Semiconductor MAT wires BLT2UB SHD Source Halftone Destination bitBLT to Unbanded Bitmap PARAMETERS ELM DESCRIPTION Byte BLT2UB SHD Opcode Byte Reserved Long Word Destination physical bit address Word Frame width in bits Word Frame height in scanlines Long Word Source physical bit address Word Halftone X remainder Word Halftone Y remainder Long Word Halftone physical bit address of the starting pixel The BLT2UB SHD graphic order causes the MC68322 to bitBLT a source frame to a destination unbanded bitmap and apply a halftone bitmap in the process The source halftone and destination pixels are combined as specified by the current value in the BOOL SHD Boolean code register The SET graphic order must be previously define the destination bitmap warp The source frame warp is assumed to be the FW specified in the BLT2UB SHD graphic order unless a non zero source bitmap warp was previously defined by the SET SBMAP graphic order in which case the latter is used The SET HTBMAP graphic order must previously define the halftone bitmap dimensions During the processing of halftones wrapping occurs at the edges of the bitmap and results in horizontal and vertical replication tiling of the bitmap to cover the entire bitBLT frame area Halftone tiled patte
166. ation transfer is calculated in the same way For example the Boolean code for a semi transparent source transfer onto the destination bitmap involving halftoning sometimes used by PostScript is determined as follows NOT SOURCE A DESTINATION SOURCE A HALFTONE BOOLEAN CODE 11001100 A 10101010 11001100 11110000 11100010 E216 Take caution when calculating a Boolean code to ensure only operand values that are contained in the graphic operation transfer are used For example the halftone value should not be used when specifying the Boolean code for a transfer involving a source destination graphic order If this constraint is violated the MC68322 treats the extra parameter s as zero Thus if the Boolean code for dest source A halftone V dest is used to specify a transfer involving a source destination graphic order the MC68322 treats the halftone parameter as zero The resulting operation becomes dest source A 0 V dest or simply dest dest 12 5 BLOCK TRANSFERS A bit block transfer bitBLT is an operation that combines up to three rectangular bit maps source halftone and destination in some Boolean combination and places the result in the original destination bitmap An expanded bitBLT operation is similar to a standard bitBLT operation except that each pixel of the source bitmap is replicated in one or both dimensions by scaling factors from 1 to 16 An expanded bitBLT graphic order reads a
167. be properly recognized by the MC68322 This value results in read and write access times of three CLK1s which is the minimum required for a proper asynchronous access Once RACC and WACC are satisfied the MC68322 samples WAIT If WAIT is active at the end of the access time the access is stalled After WAIT becomes inactive and a two CLK1 recovery from WAIT RHLD and WHLD are satisfied If WAIT becomes inactive and RHLD and WHLD are zero an internal DTACK is generated to the core and the cycle is terminated Figures 6 4 and 6 5 illustrate normal and special asynchronous read or write timing For On This Product Go to www freescale com Freescale Semiconductor jowi yews 52 54 W W W W W W W W S6 015 00 READ i SET TIME K gt lt WAIT ACC TIME i CHIP SELECT TIME ADDEDWAITTIME HLDTIME 2 gt lt gt 4 gt gt st 1 gt 2 3 gt ACC TIME 4 HLD 2 gt HLD TIME 1 1 There is CLK1 of synchronization delay WAIT 2 Chip select bank recovery starts Figure 6 4 Asynchronous Read or Write Timing Diagram W W W W W 5657 SET TIME ACC TIME E Pt gt lt ADDED REC WAIT TIME lt HP SELECT TIME SE
168. bits in the PPIR to handshake with the host MODE can be reprogrammed at any time but if a compatibility mode cycle is currently in progress it completes as normal However MODE should only be changed from compatibility mode handshaking when BUSY is high This ensures that no parallel port activity is taking place when reconfiguring the 10 Enable ECP mode hardware handshaking without RLE support during forward data transfers In this mode the responds to a high to low transition on STROBE and automatically sets and clears the BSY1 bit in the PPIR to handshake with the host Reception of both run length counts and channel addresses causes the PIER s CRD bit to be set The software is responsible for responding to channel addresses and performing data decompression MODE For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor Vit Ew can be reprogrammed at any time but if an ECP cycle is currently in progress it completes as normal 11 Enable ECP mode hardware handshaking with RLE support during forward data transfers The PPI performs the same ECP mode handshaking as above except RLE decompression is enabled RLE decompression enables the PPI to detect and intercept run length counts and to automatically perform data decompression However during this mode only channel addresses cause the PIER s CRD bit to be set The software is responsible
169. bly halt activity to supply correct data swap Four byte lanes reversing lane 0 to lane 3 lane 1 to lane 2 lane 2 to lane 1 and lane 3 to lane 0 tablewalk An index value is used to identify an entry point in a tree structure that is traversed until a pointer is found The system walks through a table of pointers to it s end transaction A bus transaction consists of an address transfer address phase and data transfers data phase time division multiplex TDM Any serial channel that is divided into channels separated by time watchpoint An event that is reported but does not change the timing of the machine word word consists of 4 bytes or 32 bits writethrough Continuous updates as they occur of external memory so that cache and memory maintain coherency at all times MC68322 USER S MANUAL E 5 For More Information On This Product Go to www freescale com Freescale Semiconductor INDEX Numerics 0 pages bottom to top B2T parameter 13 6 scanline run 12 7 12 8 0 pages definition 1 11 180 pages band fault during 11 4 bottom to top B2T parameter 13 6 definition 1 11 scanline run 12 7 12 8 322MSK C 3 A accessing memory 4 9 address bit defined 13 5 byte defined 13 5 address boundary DRAM registers 7 2 address bus 2 3 4 1 address constraints 12 15 address error exception 5 12 address error 5 12 address physical vs logical 13 6 address
170. bus to complete the data transfer This process continues until all data is transferred an address error occurs or the transfer is terminated by the core through a flush request For data transfers to DRAM from the MC68322 bus the GDMA begins monitoring the external DREQ input When data is available from the external DMA device the MC68322 bus cycle starts and the data is loaded into the internal data latch Once the internal data latch is loaded with source data the GDMA requests a DRAM cycle and when granted writes the data to memory This process continues until all data is transferred an address error occurs or the transfer is terminated by the core through a flush request During an active DMA transfer the system software can decide to reallocate the DMA resource to another device By issuing a flush request the current DMA operation will be terminated When the CMP bit in the interrupt event register is set new values for the DMA channel registers can be written and the channel restarted 8 6 DMA TRANSFERS Because both DMA channels operate a demand basis all DMA initiated transfers through either the PDMA or GDMA channels use a data request and acknowledge type handshake The GDMA supports both word and byte sized transfers For word sized transfers the external DMA device must connect to 015 00 and for byte sized transfers the device must connect to 07 00 WRU and WRL signals are both asserted during an MC68322 wor
171. c order causes the MC68322 to bitBLT a source frame to a destination frame and apply a halftone bitmap in the process The source halftone and destination pixels are combined as specified by the current BOOL SHD Boolean code The destination bitmap warp is taken to be the FW specified the BLT2F SHD graphic order FW is also assumed to be the source frame warp unless a non zero source bitmap warp was previously defined by the SET SBMAP graphic order in which case the latter is used The SET HTBMAP graphic order must previously define the halftone bitmap dimensions During the processing of halftones wrapping occurs at the edges of the bitmap and results in horizontal and vertical replication tiling of the bitmap to cover the entire bitBLT frame area Halftone tiled patterns are typically anchored to the page A bitBLT may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where it is positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the upper left corners of the source and destination frames HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the bottom edge HXR and HYR must be in the following ranges 1 lt HXR x HW and 1 x HYR x HH where HW and HH are the width and height of the halftone bitmap respectively For example if the starting pixel in
172. c order operands may also require adjusting including the destination address DA halftone address HA and halftone X remainder HXR Clipping in the Y dimension is controlled in a similar way with the two graphic order operand values YOFF and FH YOFF is an offset in scanlines from the top edge of the expanded bitmap or bottom edge when rendering in bottom to top order and FH is the transfer frame height Together YOFF and FH provide scanline granular control of clipping at the top and bottom extents of the expanded bitmap When clipping other graphic order operands may also require adjusting including the DA HA and the halftone Y remainder HYR For Mort ON oduct to www freescale com Freescale Semiconductor MAT wires UNEXPANDED EXPANDED DESTINATION SOURCE BITMAP XMUL SOURCE BITMAP BITMAP SAA lt HEH YMUL e gt DW Figure 13 1 Controlling Left and Right Clipping of Expanded Bit Maps 13 1 5 Scanline Transfer Scanline graphic orders differ from bitBLT graphic orders in that the individual scanline runs describe the transfer and can effectively generate a nonrectangular and unconnected destination area There are six different scanline graphic orders that provide the six combinations of destination bit maps and operand types Two of these control scanline transfers to frames two control scanline transfers to unbanded bit maps
173. can run synchronously from a 1x video rate from the print engine If the print engine does not supply a video clock the PVC can phase lock to a print engine s synchronization signal and generate an internal video rate to use during transmission The phase locked loop circuitry runs off of a clock from an external oscillator 10 1 PRINT ENGINE INTERFACE REGISTERS The print engine interface contains several registers that control the engine interface protocol signals and interrupts These registers include the printer communication register the PVC control register the printer control block register set the PVC interrupt event register and the printer communication interrupt event register 10 1 1 Printer Communication Register The printer communication register PCOMR contains several bits and fields that control the status of data transfers to or from the print engine 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Figure 10 1 Printer Communication Register The core uses the printer command field write only to send an 8 bit command to the print engine and the printer status field read only receives an 8 bit serial command The 12 bit CCLK divisor field determines the period of the clock supplied to the print engine CCLK period CLK1 period x CCLK Divisor 1 x 16 At 16MHz this provides a range of 1us to 4 1ms per CCLK period The PCOMR has three bits that determine th
174. ce and destination _SD and source halftone and destination _SHD They are all used to load the four Boolean code registers that will govern the bitBLT or scanline transfer graphic order to be executed The RGP has four internal registers that contain the Boolean code used during operand transfers BOOL_D BOOL_SD BOOL_HD and BOOL_SHD The register BOOL_D is loaded using the SET_BOOL_D graphic order and holds the Boolean code used during destination only bitBLTs and scanline transfers BOOL_SD and BOOL_HD are loaded using the SET BOOL SD and SET BOOL HD graphic orders BOOL_SD holds the Boolean codes used during source destination bitBLTs For Mon zi MANUS Product Go to www freescale com Freescale Semiconductor wires BOOL HD holds the Boolean code used during halftone destination scanline transfers BOOL_SHD contains the Boolean code used during source halftone destination bitBLTs bitBLTs can use BOOL_D BOOL_SD or BOOL_SHD Boolean codes and scanline transfers can use BOOL_D or BOOL_HD Table 13 1 Graphic Order Organization TYPE GRAPHIC ORDER DESCRIPTION Initialization SET_BBMAP Set Banded Destination Bitmap Parameters SET_UBMAP Set Unbanded Destination Bitmap Parameters SET_SBMAP Set Source Bitmap Parameters SET_HTBMAP Set Halftone Bitmap Parameters SET_BOOL_D Set Boolean Operator For Destination Only Transfers SET_BOOL_HD Set Boolean Operator For Halftone Destination Tran
175. concepts is key to understanding how the MC68322 works These concepts include understanding printer languages bitmaps banding halftoning and duplex printing 1 4 1 Printer Languages There are three basic types of printer languages 1 1 8 Printer Control Language PCL A term coined by Hewlett Packard when LaserJet printers were first introduced It embodies a relatively simple set of escape sequences reminiscent of ANSI 3 64 Of the common printer languages PCL is considered moderately complex Page Description Languages PDL Actual programming languages The major players are Adobe s PostScript and Microsoft s Truelmage and they resemble other languages like BASIC FORTRAN and C except that PDLs are interpreted rather than compiled The instructions for how the page is to be formed are described in lexical verbs such as FINDFONT and MOVETO This means that the parsing and interpretation of these languages must be done in the printer engine itself Generally PDLs describe one page at a time and each page is a separate PDL program Also PDLs are considered highly complex Document Description Languages DDL Similar to PDLs in that they programming languages with lexical verbs The difference between DDLs and PDLs is that DDLs generally describe an entire document consisting of multiple pages This increases the storage requirements of a printer in that the entire document must be parsed and interpreted before any p
176. ction B 4 B 4 Flash EEPROM Connection 1 of 2 22 22 2 1 5 5 ote eoo aspe eb RR osa Unt bebe ERI EU IRE CR c orit pides B 7 B 6 Front Panel Buffers and Latches B 8 B 7 4 Kbit Serial EEPROM B 8 B 8 68 3221 gt seh teed ics eee at tu e 9 B 9 Parallel Port Connector Interface B 10 10 Print Engine Interface potuto teruel nios B 11 B 11 Initialized Memory Map From Code Example B 12 For More informatio ion 5 BANAL Product Go to www freescale com Freescale Semiconductor LIST OF TABLES Table Page Number Title Number 21 5 lt SUMMA aco sui ence 2 2 2 2 and TEST Combinations 2 5 2 3 DRAM Address Multiplexer enne 2 7 3 1 Processor Data Formats 3 3 3 2 Effective Addressing Modes 22 22 2 3 3 Su 3 4 3 4 Instruction Set Summary 3 6 5 1 Hardware Interrupt Events 22 2048111 5 2 5 2 External Interrupt Polarity errare een uei eati tbe ine bienes 5 5 5 3 Exception Vector Ass
177. ctor SECTION 10 PRINT ENGINE INTERFACE The MC68322 uses an 8 bit half duplex synchronous serial protocol to communicate with the print engine This print engine interface contains an integrated print engine video controller PVC as well as control logic for the 8 bit serial communication channel compatible with many print engines The print engine interface is one of the two components of the graphics unit the other being the RISC graphics processor The PVC can drive virtually all laser printers currently on the market It automatically retrieves video data from DRAM using burst cycles and manages all parameters associated with the video image This type of print engine video interface eliminates all the software overhead associated with the transfer of the bitmap image to the print engine The software starts the transfer and waits for the end of page or band interrupt event which allows the core to start processing the next page The PVC also saves a significant amount of hardware cost Static RAMs and FIFOs are unnecessary since the bitmap image is transferred directly from DRAM serialized and then transmitted to the print engine The PVC uses an efficient page mode access to DRAM to fill its internal eight word queue FIFO The PVC is divided into two subsystems Amemory subsystem that performs direct memory accesses to DRAM to obtain video data from a page or band bitmap A video subsystem that serializes the data
178. d sized bus write cycle but only WRL is asserted during byte sized writes For On This Product Go to www freescale com Freescale Semiconductor IU Support for byte sized transfers is handled automatically by the DMA interface through data packing and it requires no external logic Byte sized data received from the core or PPI are packed into words prior to requesting a DRAM access Data sent to the core as bytes are read in as words from DRAM and unpacked to bytes for transfer All data transfers to and from memory are in big endian format thus assuring compatibility with the processor s data organization in memory 8 6 1 PDMA Transfers Handshaking for the PDMA channel is transparent and handled internally between the PPI and the PDMA channel A typical transfer cycle for the PPI is described in Section 9 Parallel Port Interface 8 6 2 GDMA MC68322 Bus Read and Write Cycles GDMA handshaking uses the DREQ and DACK signals DREQ is an input signal that has a programmable level or edge sensitivity with polarity control The default configuration is active low level DACK is an output signal that is used by the external DMA device to acknowledge that a GDMA cycle is in progress The polarity for the DACK output is fixed to provide an active low output A GDMA cycle is requested when DREQ is asserted by the external DMA device such as PROM or I O After the DMA interface interna
179. d sometimes ISYNC half word A half word consists of 2 bytes or 16 bits instruction done Execution finished and results written back instruction execution time All the time between taken and done instruction fetch Reading the instruction data received from the instruction memory I Cache Flash instruction issue Driving valid instruction bits inside the core instruction retire The instruction and all preceding instructions in the program finished execution with no errors Retired instructions are said to be architecturally executed instruction stream A sequence of operands to be executed by the CPU instruction taken All resources to perform the instruction are ready and the core begins executing it For On This Product Go to www freescale com Freescale Semiconductor internal bus The bus connecting the CPU and SIU interrupt The act of changing the machine state register and other parts of the machine state in response to an exception latency The interval from the time an instruction begins execution until it produces a result that is available for use by a subsequent instruction little endian Byte ordering that assigns the lowest address to the lowest order 8 bits of the scalar master A device on the bus that requests bus ownership and initiates the bus cycles memory controller A functional logic section of the It s primary function is to provide the contr
180. ddresses are sometimes given as a pair of numbers For example 28 of 32 This indicates that the address in this case a byte address occupies the least significant 28 bits of the long word operand and that the MC68322 controls the four most significant bits For more information on address constraints for graphic orders scanline tables and bit maps see Section 12 Graphic Operations Some graphic orders specify address parameters that must be aligned to byte or word boundaries When a byte address is required to be aligned on a word boundary its least significant bit should be zero The MC68322 forces the bit to be zero internally There are two combinations of address granularity and alignment used by MC68322 graphic orders In the descriptions of graphic orders and definitions of their parameters the following two phrases are used Bit address A 32 bit bitmap address that points to any bit location in memory and specifies bitmap locations and pixels Byte address word aligned A 28 bit word aligned address that points to any word location in DRAM space It is used for referencing graphic order instructions scanline tables and halftone companion tables For Mort ON oduct to www freescale com Freescale Semiconductor wires 13 3 1 Physical vs Logical Address For graphic orders that render images to frames or unbanded bit maps the address parameters are interp
181. de The MC68322 also provides the perfect printing environment for users of complex page description languages such as PCL and PostScript and less scaleable graphics imaging models such as Windows Printing System and QuickDraw Complete code compatibility with the M68000 Family gives the designer access to a broad base of established real time kernels operating systems languages applications and development tools many of which are optimized for embedded processing and printing applications MC68322 USER S MANUAL 1 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction 1 1 FEATURES The following list summarizes the main features of the MC68322 1 2 Static 000 Core Processor Complete code compatibility with M68000 Family 0 Glueless interface to peripherals 256M address range Graphics Unit Memory reduction techniques Run length encoded scan line tables 9 RISC graphics processor Processes multi operation graphics orders from display list Requires significantly less bitmap image memory due to hardware banding capability Dedicated graphics bus allows up to 8 ppm performance at 600 dpi resolution Print engine video controller Converts bitmap image to serial datastream and feeds print engine Generic programmable nonimpact printer communications interface Toner conservation technique Dedicated high performance D
182. ds the PPIR s DATA field ACK is pulsed BUSY is negated and the request is cleared The PPI functions without using the but the system throughput will be dramatically impacted Therefore using the PDMA is strongly recommended Figure 9 5 illustrates the compatibility mode timing STROBE BUSY ACK LATCH DATA READ DATA REQUEST INTERRUPT MAKE ACK PULSE Figure 9 5 Compatibility Mode Timing Diagram For On This Product Go to www freescale com Freescale Semiconductor Vit 9 2 2 ECP Handshaking The PPI supports two ECP hardware handshaking modes for forward data transfers one with run length encoding and one without ECP hardware handshaking is enabled by setting the MODE field in the PPCR to 102 while ECP hardware handshaking with RLE is enabled by setting MODE 112 The basic operation of these two handshake modes is identical When either mode is enabled the PPI automatically responds to STROBE by latching the logic levels on PD7 PDO and AUTOFD in the PPIR s DATA field When the PPIR s DATA field is read the PPI drives BUSY high waits for STROBE to go high and then drives BUSY low to conclude the cycle Since no ACK pulse is generated the pulse width duration specified in the PPIR s ACKW field is not used Like compatibility handshake mode data is latched at the leading edge of STROBE thus causing a PDMA request and the posting of
183. dth defined 13 3 G general purpose DMA see DMA GDMA 8 2 GDMCR 8 3 glossary E 1 graphic operations bit block and scanline order execution 12 14 bit block transfer 12 5 bitmap types 12 1 Boolean codes 12 3 graphic operands types 12 3 graphic operands 12 2 location and address constraints 12 15 scanline and halftone table example 12 13 scanline transfer executing during banded applications 12 9 halftone companion tables 12 10 run operation 12 8 scanline transfer 12 5 graphic operations 12 1 graphic order interrupted 11 4 graphic orders address alignment 13 5 addresses 13 5 band number and fault 13 7 bitBLT during duplex 13 6 defined 11 1 descriptions 13 8 display list sequence 13 5 duplex operation 13 6 example display list format 13 5 execution unit 11 1 operand types 12 2 parser 11 1 scanline during duplex 13 6 types bit block transfer 13 3 expanded bit block transfer 13 3 For Mol oderat ion initialization 13 1 program flow control 13 3 scanline transfer 13 4 types 13 1 graphic orders 13 1 graphics unit shut down 12 15 H HA halftone address defined 13 3 halftone 32 bit specifier 12 10 48 bit specifier described 12 11 bit map type described 12 2 operand type described 12 2 specifier boundary conditions 12 12 table address convention 12 15 table address HTTA during duplex operation 13 6 halftone bitmap 12 2 halftone companion table
184. e CLK1s for read operations is derived from these fields through the calculation active read time RSET RHLD 17 The chip select active time in CLK1s for write operations is derived from the calculation active write time WSET WACC WHLD 11 There are two guidelines that the software must follow when programming these timing parameters The minimum allowed value for active read time and active write time is 21 The minimum allowed value for WSET 1 which produces a write setup time of 2 The CSR s size field contains the chip select bank s size and should have a defined programmed value Because each CSR has its own size field each chip select bank can be a different size or completely removed from the memory map This bit field allows a maximum bank size of 64M Table 6 1 lists the encodings for the size field For On This Product Go to www freescale com Freescale Semiconductor Inc 3 Table 6 1 Size Field Encoding 16M CSR s base address field contains the chip select bank s address and allows each bank to be programmed anywhere in the 256M range of the memory map The bits in the base address field correspond to bits 27 18 of the chip select bank s starting address At reset CSR7 CSR1 are disabled The base address of CSRO is set to zero so the core can fetch the reset vector CSRO should be connected to ROMs containing the startup
185. e For On This Product Go to www freescale com Freescale Semiconductor Inc 5 4 1 Processing Specific Exceptions The exceptions are classified according to their sources and each type is processed differently There are three types of exceptions reset interrupt and instruction traps 5 4 2 1 RESET EXCEPTION The reset exception corresponds to the highest exception level The processing of the reset exception is performed for system initiation and recovery from catastrophic failure Any processing in progress at the time of the reset is aborted and cannot be recovered The core is forced into the supervisor state and the trace state is forced off The interrupt priority mask is set at level 7 The vector number is internally generated to reference the reset exception vector at location 0 in the supervisor program space Because no assumptions can be made about the validity of register contents in particular the SSP neither the internal program counter nor the internal status register are saved The address in the first two words of the reset exception vector is fetched as the initial SSP and the address in the last two words is fetched as the initial internal program counter Finally instruction execution is started at the address in the internal program counter The initial internal program counter should point to the power up restart code The MC68322 does support the reset instruction but the inst
186. e data bus when RD is negated When the hold time is satisfied then the MC68322 drives the data bus with the data and EDTACK is asserted The hold time provides a data turnaround time starting from the time the chip select device drives the data to the time the MC68322 drives the data Read data is valid while EDTACK is asserted When the external bus master receives EDTACK it is free to negate AS and to stop driving the address bus Only word sized read cycles are supported Figure 4 12 illustrates a read cycle from the external bus master For More MES 822 ae BM 2b to www freescale com Freescale Semiconductor M eee eer 25 1 015 00 EDTACK A B C D E F G H I NOTES A Master requests bus by asserting BR MC68322 grants bus by asserting BG Master drives 25 1 Master asserts AS 68322 drives 015 00 and asserts EDTACK F Master negates AS and stops driving 25 1 MC68322 stops driving 015 00 and negates EDTACK Master negates BR _ MC68322 negates BG UJ Figure 4 12 External Bus Master Read Cycle 4 5 3 External Bus Master Write Cycle When the external bus master writes to DRAM chip selects or internal registers it asserts EDTACK when the write cycle to the device is complete The write data on the data bus goes directly to the device being written Once the external bus master receives EDTACK it is free to negate AS and
187. e the current operational mode of the GDMA channel This is not recommended When read by the core the register reflects the current programmed bit fields Figure 8 2 illustrates the GDMA control register 15 14 13 12 11 40 9 8 7 6 5 4 3 2 4 0 00FFF21C RESERVED fos Figure 8 2 GDMA Control Register For On This Product Go to www freescale com Freescale Semiconductor The DM field is used to select how the channel recognizes an external DMA device request Table 8 1 lists the field encodings and available options Table 8 1 DM Field Encoding ENCODING DREQ REQUEST OPTION Active Low Level Active High Level Falling Edge Transition Rising Edge Transition Setting the DS bit causes the MC68322 bus interface signal CSx to be asserted during a DMA generated MC68322 bus cycle If cleared CSx will not be asserted during the cycle When the W bit is set the GDMA channel performs byte sized transfers but word sized transfers when cleared When the D bit is set the GDMA channel transfers data from DRAM to an external DMA device and when cleared the GDMA channel transfers the data from an external DMA device to DRAM 8 3 DMA SPEED REGISTER The SPD bit in the DMA speed DMASP register controls the maximum time that the GDMA waits between accesses to DRAM When set GDMA waits a maximum of 29 DRAM bus cycles plus six CLK1 periods for DRAM refr
188. e CCLK Command data is transferred on CMD STS which remains in high impedance until the CBSY setup time is satisfied CMD STS is then brought active for one CLK1 period and each bit is driven on the falling edge of CCLK The print engine should sample the command data on the rising edge of CCLK At the end of the transmission CMD STS is brought high for one CLK1 period and then returns to the high impedance state When CBSY transitions to an inactive state indicating the end of the command operation the PCIER s CMS bit is set to notify the core that the command has been sent thus causing a command sent interrupt event to occur The software should not try to write another command until this interrupt is received For On This Product Go to www freescale com Freescale Semiconductor recovery cycle is then initiated during which no command or status operations are performed If a subsequent command operation is initiated during this time it will be latched and started after the recovery If SBSY becomes active indicating a status operation then it must remain active until the end of the recovery which has the duration of one half CCLK period Figure 10 7 illustrates the timing diagram for a command operation when the core supplies CCLK sc 4 s e 10 aa COXDCOCOCOCOCOCO des les NOTES S
189. e designs being ported to the MC68322 can be tested rapidly This is accomplished by providing signals in a 208 pin grid array PGA package that are not available the 160 quad flat pack package MC68322 USER S MANUAL 1 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction 1 2 2 Graphics Unit The graphics unit performs all graphics functions required by complex PDLs such as bit block transfer bitBLT A bitBLT is a CPU intensive function of logically bits from one memory location to another The graphics unit acts as a dedicated hardware execution engine to perform the bitBLT function with virtually no intervention from the core bitBLT operations are performed very fast by the graphics unit supporting one two and three operand bitBLT operations to yield 256 logical bitBLT operation combinations The graphics unit contains two independent processing units that can function in parallel with the core a RISC graphics processor RGP and a print engine video controller PVC Both processing units perform burst read and write accesses to DRAM through the DRAM controller The RGP is a high performance bit image processor optimized for the 16 bit DRAM controller on the MC68322 It achieves performance levels that enable the MC68322 to be used effectively in banding applications or in other high speed high density bitmapped graphics products The RGP is comprised
190. e expanded graphic order increases the resolution of the unexpanded bitmap to match the resolution of the destination bitmap being used in a transfer Since the RGP expands the unexpanded bit maps during the transfer expanded bit maps never actually exist in memory For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor AF Frame A frame bitmap is two dimensional array of pixels that is generally a subset of some larger bitmap array the width and warp are identical For example a frame bitmap could describe the bounding box of a character To better illustrate this difference suppose a rectangle is transferred to a bitmap both the warp of the bitmap and the width of the rectangle being transferred must be specified When transferring a rectangle to a frame bitmap the warp is the width of the rectangle being transferred Operations that involve transferring pixels to frame bit maps are particularly useful when a small rectangle of a larger image must be saved for future reference The frame bitmap is the smallest possible storage means for the rectangle because the scanlines are packed in memory The end of one scanline and the beginning of the next have no unused bits between them Halftone A halftone bitmap is a special type of bitmap because it is automatically replicated in both the horizontal and vertical directions It is intended to hold a pattern that is
191. e run length is loaded into the counter FLL is set again when the data byte is received and cleared when the run length counter reaches zero and the last data byte is decompressed 9 2 3 Disabling Hardware Handshaking When hardware handshaking is disabled MODE 00 the software is responsible for controlling the However the PPIR s DATA field continues to latch parallel port data on the leading edge of STROBE even with all hardware handshaking disabled Also host control signal inputs are always synchronized to CLK1 to prevent metastable events from reaching the internal logic of the MC68322 This does not include PD7 PDO since they guaranteed to be stable when STROBE is low For On This Product Go to www freescale com Freescale Semiconductor Vit 9 3 SOFTWARE CONTROLLED HANDSHAKING By clearing the PPCR s MODE field the software controls all parallel port operations including negotiation and termination phases as well as reverse data transfers The software can also respond to parallel port inputs by way of polling or interrupts This gives the software the flexibility to adapt to new and revised protocols The software controls BUSY and ACK with the BSY2 and 2 bits in the PPIR Normally the PPI state machine should be idle when using BSY2 and ACK2 The software can issue a reset by setting the RST bit in the PPCR to force the PPI state machine to idle
192. e trapv and chk instructions force an exception if the user program detects a run time error which can be an arithmetic overflow or a subscript out of bounds A signed divide divs or unsigned divide divu instruction forces an exception if a division operation is attempted with a divisor of zero 5 4 2 4 ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS An illegal instruction refers to any of the word bit patterns that do not match the bit pattern of the first word of a legal core instruction If such an instruction is fetched an illegal instruction exception occurs Freescale reserves the right to define instructions using the opcodes of any of the illegal instructions Three bit patterns always force an illegal instruction trap on all M68000 Family compatible microprocessors These patterns 4AFA 4AFB and 4AFC Two of the patterns 4AFA and 4AFB are reserved for Freescale system products The third pattern 4 is reserved for customer use as the take illegal instruction trap illegal instruction Word patterns with bits 15 12 equaling 1010 or 1111 are distinguished as unimplemented instructions and separate exception vectors are assigned to these patterns to permit efficient emulation Opcodes beginning with bit patterns equaling 1111 F line are implemented in the MC68020 as coprocessor instructions These separate vectors allow the operating system to emulate unimplemented instructions in the software Exception p
193. e various modes of operation the CMD STS bidirectional CSB bit the SCLK source SRC bit and the CCLK source CRC bit The CSB bit indicates whether CMD STS is bidirectional CSB 1 or output only CSB 0 The values programmed in the SRC and CRC bits determine whether the MC68322 SRC CRC 1 or the print engine SRC CRC 0 have supplied status or command clocks respectively For On The Product Go to www freescale com Freescale Semiconductor mnywe 10 1 2 PVC Control Register The PVC control register PVCCR contains bits that control the polarity of all MC68322 inputs and outputs used by the PVC The PVCCR should be written after an MC68322 reset and before a print operation begins 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 aS a Trpo 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 RESERVED Figure 10 2 PVC Control Register 00 400 00 402 While the is active the polarity of input signals should not be altered The responds to a polarity change if it occurs while the PVC is waiting for a transition but this should be avoided The PVCCR also contains the video clock source control bits the PLL video clock divisor control and the SmartToner control bits SDN SmartToner Density This field selects one of four halftone patterns where 00 7 density 01 1 4 density 10 1 density and 11 1 density This will affect the
194. ection 1 Introduction 1 1 costoso Ee sexe S Lucae n E 1 2 1 2 Processors and Modules ee ea End 1 3 1 2 1 The ECDOD Core tta deste ote re e ien edet ess 1 3 1 2 2 Graphics scd oii eG D Ap tob roto den 1 4 1 2 3 Bus Intertace diete pte e ee Shee eee 1 5 1 2 4 System Integration Module 1 5 1 2 5 eec 1 6 1 2 6 Interface 1 6 1 2 7 Parallel Port 1 6 1 3 Internal Memory Map 1 6 1 4 Understanding the 68322 224 1 8 1 4 1 Printer Languages 1 8 1 4 2 ati 1 9 1 4 3 Banding 1 10 1 4 4 Halftoning C 1 10 1 4 5 Duplex Printing 1 11 Section 2 Signal Descriptions 2 1 Address BUS 2 3 2 2 A T E 2 3 2 3 System Interface 2 4 2 3 1 Reset RESET 2 4 2 3 2 System Clock e poto o esaet tot de pre na ideis 2 4 2 3 3 High Impedance Mode crecer ener eren netten 2 5 24 External Bus Master Interface 2 6
195. ed in the section detailing the corresponding module Table 5 1 Hardware Interrupt Events POSTING MODULE INTERRUPT EVENTS PVC Illegal DRAM Address Video Underrun Band Underrun Page End Band Begin Error Done Printer Communication Command Sent Status Received GDMA Illegal Address DMA Complete Terminal Count Reached PDMA Illegal Address DMA Complete Terminal Count Reached SELECTIN High SELECTIN Low STROBE High STROBE Low AUTOFD High AUTOFD Low INIT High INIT Low Data Received ECP Command Received Invalid Termination A module s interrupt event register contains three basic parts interrupt enable field interrupt event bit fields and interrupt level field When an enable bit is set it allows the interrupt event to cause an interrupt When clear the interrupt is masked An interrupt event bit reflects the status of an interrupt event regardless of the masking in the enable field To determine the source of the interrupt the software reads these bits and applies the mask in the enable field The interrupt event bits are cleared with the software by writing a 1 to the bit positions to be cleared in the module s interrupt event register For More FS 8322 UBER oM roduct Go to www freescale com Freescale Semiconductor Ing interrupt level field reflects the interrupt priority level for that module Level 7 is the highest priority level 1 is the lowest and lev
196. egotiation reverse data transfers and termination cycles must be carried out by the software Please note that IEEE 1284 EPP communications mode is not supported The PPI contains an interface controller that consists of a data receive and transmit latch run length encoding decompression logic input conditioning logic and edge detector logic The RLE decompression is accomplished through a smart state machine and additional control logic The PPI has input conditioning logic to filter the incoming control signals Figure 9 1 illustrates the PPI controller block diagram PD7 PDO PARALLEL PORT DATA BUS DECOMPRESSION LOGIC FAULT DIGITAL SELECT STROBE FILTER Hd STATE CONTROL AUTOFD EDGE REGISTERS PERROR DETECTION INIT 3 CONTROL BUSY REGISTERS ACK Figure 9 1 Parallel Port Interface Controller Block Diagram For d dora ion ROMANY Product Go to www freescale com Freescale Semiconductor t Vit Ew 9 1 REGISTERS There three memory mapped registers that control the PPI PPI interface register PPI control register e PPI interrupt event register 9 1 1 Parallel Port Interface Register The parallel port interface register PPIR is a read write register that contains two 8 bit fields one that controls the ACK pulse width and another that contains the latched parallel data transmitted from the host
197. el 0 indicates that no interrupt is requested If an event occurs and causes the same level of interrupt as is currently being serviced at the same time an interrupt of that level is being cleared the interrupt level will become active again after two clocks The interrupt level to the core could change if the priority level of an active interrupt is changed To avoid potential problems priority levels should be changed only while the corresponding interrupt is masked Some interrupt event registers have status bits in addition to the interrupt bits These status bits cannot cause an interrupt to the core However the software can read them at any time to obtain more information about the module s status 5 1 2 Software Interrupts There are seven independent software interrupts that can be set and cleared under software control each corresponding to levels 7 through 1 Software can read the software interrupt event register for status information or write to it to clear or set an interrupt Like the basic format for each module s interrupt event registers described above the software interrupt event register contains an enable field several software status fields and the software interrupt event bits Figure 5 1 illustrates the software interrupt event register OOFFF790 ENABLE OOFFF794 RESERVED Figure 5 1 Software Interrupt Event Register Software interrupts set by writing to the bits of the sof
198. ent is added HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the bottom edge HXR and HYR must be in the following ranges 1 x HXR x HW and 1 x HYR x HH where HW and HH are the width and height of the halftone bitmap respectively For example if the starting pixel in the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH HTTA and SLTA point to the most significant byte of the first specifier in their respective tables and DA HXR HYR and HA refer to the pixel to which the displacement of the first bit string specifier is added not necessarily the first bit of the first run Since both the scanline table and companion halftone table s specifiers must be placed at word boundaries HTTA and SLTA must be word aligned Related Graphic Orders SET BOOL HD SET HTBMAP For Mort ON oduct to www freescale com _Freescale Semiconductor Inc wires DESTINATION TABLE HALFTONE TABLE BANDED BITMAP SLTA HALFTONE SPECIFIERS DAA FIRST DISPLACEMENT BITSTRING SPECIFIERS BOOL_HD USED TO COMBINE FRAMES HALFTONE BITMAP a x SS Figure 13 31 Halftone Destination Scanline Transfer to Frame For Mort farsi Shon On This Product Go to www freescale com Freescale Se
199. er and the new scanline is beyond the end of the current band The MC68322 does not check horizontal and vertical boundaries while processing the bit string specifier s run For On This Product Go to www freescale com Freescale Semiconductor AF 12 6 4 Halftone Companion Tables A halftone bitmap is automatically replicated in both the X dimensions For scanline graphic orders the task is complex since each scanline run describes an individual area on which to be operated For example on 0 pages after the displacement required by the bit string specifier has been applied the proper location in the halftone bitmap must be calculated For the 16 bit bit string specifier this task is relatively straightforward and can be carried out with a minimum number of cycles For the 32 and 48 bit specifiers the task is considerably more complex because of the much larger displacement values associated with them The task can be accomplished but at a significant cost in overhead cycles To reduce the penalty for the larger bit string specifier formats a halftone companion table is employed This eliminates virtually all overhead cycles in return for only slightly higher memory storage requirements within typical scanline tables The halftone companion table contains a list of corresponding halftone specifiers similar in composition to bit string specifiers for each 32 and 48 bit bit st
200. ero to a bit has no effect These fields are write only For On This Product Go to www freescale com Freescale Semiconductor APPENDIX D ALTERNATE PIN FUNCTIONS This section describes the MC68322 alternate pin functions available in Mask Set G59B In small systems where many of the pins are not used these pins may be individually programmed as general purpose inputs and outputs thereby providing as many as four I O pins 12 output pins and two interrupt input pins D 1 PINS The following 18 pins have alternate functions Each of these pins powers up with their normal function Software written for previous revisions of the MC68322 will operate identically on Mask Set G59B provided users write zeroes to all unused register bits To alternately define these pins the software may program the ALTPIN SEL register to assign an alternate function to each pin The following table shows the pins and pin type when the ALTPIN SEL register bit is set Note that three of the alternate bus master output signals share a register bit Table D 1 ALTPIN SEL Bit Descriptions PIN TYPE 00 910 00 912 00 914 00 916 ALTPIN SEL 1 ALTPIN SEL ALTPIN DIR ALTPIN IN ALTPIN OUT REGISTER REGISTER BIT REGISTER REGISTER BIT A 22 Input Output 0 0 0 A 23 Input Output 1 1 1 1 A 24 Input Output 2 2 2 2 A 25 Input Output 3 3 3 3 A
201. es physical logical translation 13 48 addresses duplex 13 6 addresses graphic orders 13 5 addressing modes 3 3 ALTPIN DIR D 2 ALTPIN IN D 2 ALTPIN OUT D 2 ALTPIN SEL D 1 applications configuring a generic print engine interface B 11 configuring the DRAM and DRAM SIMM B 2 configuring the flash EPROM B 4 configuring the in circuit emulation B 9 configuring the parallel port B 10 configuring the random control logic B 7 configuring the serial EEPROM B 8 MC68322 internal registers sample code B 13 memory map initialization example B 12 applications B 1 asynchronous operation 10 10 band bit map type described 12 1 buffer reuse 10 7 display list defined 11 3 fault 11 4 number paramenter 13 7 underrun interrupt event 10 7 band buffer 10 9 band faults 13 8 band image starting address 10 6 band numbers 13 7 banded duplex operation 13 7 banded bitmap 12 1 banding definition 1 10 bit address definition 13 5 bit block order execution 12 14 bit block transfer expanded operation 12 5 bit block transfer graphic orders 13 3 bit block transfers 12 5 bit map expanded described 12 1 bit maps expanded clipping 13 3 bit string specifiers 12 6 bitBLT rendering direction 10 5 bitBLT 12 5 bit granular control of clipping 13 3 bitmap banded 12 1 definition 1 9 expanded 12 1 frame 12 2 halftone 12 2 unbanded 12 1 unexpanded 12 1 bitmap types 12 1 block diagrams parallel port i
202. es a buzzer on the board or front panel On products that need this feature the buzzer control function saves a 555 chip with its resistors and capacitors 0 6 IN CIRCUIT EMULATION If the alternate pin function is to be used in a system then an in circuit emulator ICE cannot be used for system development This feature of the G59B Mask Set is not available in an ICE version If the alternate pin function will not be used in the system then the original ICE version of the MC68322 can be used with an in circuit emulator For On This Product Go to www freescale com Freescale Semiconductor mica D 7 OPERATION EXAMPLE If the alternate pin functions are not used or if none of them be used as inputs then HI Z should be connected to Vec and TEST pin 159 of the PQFP package should be connected to ground If some of the input pins will be used then the input pin mode should be selected by connecting HI Z to ground and TEST to This connection powers up the A 22 25 pins to function as input pins and disables the normal BR and DREQ input pin functions software loads the ALTPIN OUT register with the initial values loads the ALTPIN DIR register to control the configuration of the A 22 25 pins and loads the ALTPIN SEL register to control the pin configurations For On This Product Go to www freescale com Freescale Semiconductor APPENDIX E GLOS
203. esh This is used for low memory bandwidth devices such as serial ports When DMASP is clear waits a maximum of 17 DRAM bus cycles plus six CLK1 periods for DRAM refresh This setting is used for high memory bandwidth applications GDMA latency occurs when the core RISC graphics processor print engine video controller or an external bus master uses the DRAM bus The minimum latency is zero If the DRAM bus is idle when the GDMA makes a request its DRAM bus cycle starts immediately Figure 8 3 illustrates DMASP which indicates the speed of the DMA throughput 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 00 904 RESERVED SPD Figure 8 3 DMA Speed Register For On The Product Go to www freescale com Freescale Semiconductor wmm 1725 8 4 DMA INTERRUPT EVENT REGISTERS The DMA interface provides two memory mapped interrupt event registers for each DMA channel These registers provide real time and interrupt status to the core Figure 8 4 illustrates the two DMA interrupt registers OOFFF740 ENABLE GDMA INTERRUPT INTERRUPT OOFFF750 ENABLE 21 EVENT REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Figure 8 4 DMA Interrupt Event Registers Note The DMA interrupt registers are located in the interrupt register portion of the memory map and are therefore not necessarily located contiguously with the other DMA registers Interrupt events for either channe
204. evel on FAULT Note The FLT SEL PER and BSY2 bits are arranged to correspond to their use as 7 parallel port data lines during nibble mode reverse data transfers When hardware handshaking is enabled BUSY and ACK are controlled by the PPI state machine When hardware handshaking is disabled and the PPI state machine is idle BUSY and ACK can be controlled by the software using the BSY2 and 2 bits 9 1 2 Parallel Port Control Register The parallel port control register PPCR is a read write register containing nine bits that configure the operation of the PPI Figure 9 3 illustrates the PPCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 9 3 Parallel Port Control Register FLL Full This bit is a read only status bit that indicates when parallel port data from the host is latched in the DATA field of the PPIR FLL is cleared when the PPIR s DATA field is read When handshaking and DMA are enabled FLL is set and then cleared as data is latched and read during forward data transfers The FLL bit is also cleared when the RST bit is set RLD Run Length Decompression This bit is a read only status bit that indicates when run length decompression is taking place during ECP forward data transfers RLD is set when a run length count is received and loaded into the internal counter and cleared when the last of the decompressed data is read from the PPIR s DATA field This bit can only be set when ECP with RLE MODE 11 is en
205. f active low LSP LSYNC Polarity Control Set if LSYNC is active high clear if active low VCP VCLK Polarity Control Set if rising edge is to be used clear if falling edge is to be used VCS VCLK Source Clear if VCLK input is 1x clock set if VCLK input is an external oscillator driving the 8x PLL PRT PRINT This bit controls the level of the MC68322 s PRINT output pin When the PRT bit is set PRINT is asserted but when it is clear PRINT is negated The active level of PRINT is determined by the PRP bit In nonprinting applications or for applications that do not require a PRINT interface signal the PRINT output pin can be used as a general purpose output For On The Product Go to www freescale com Freescale Semiconductor RPI QI 10 1 3 Printer Control Block Register Set The printer control block PCB register set is a group of six registers that define a print operation for the PVC to execute The PCB values define the dimensions and location of the band image page margins and band control data Loading the page image bit address portion of the PCB is the stimulus that starts the PVC and begins a print operation The entire PCB register set is doubled buffered which allows two print operations to be loaded at a time Basically when the first operation finishes the second operation immediately begins executing This is especially useful in bandi
206. ffected at any or all extents of the expanded source bitmap For Mort ON oduct to www freescale com Freescale Semiconductor MAT wires The SA parameter defines the unexpanded source bitmap bit address It must point to the upper left corner of the bitmap The warp of the bitmap is set by the SW operand This value is added to SA to locate the beginning of each successive scanline Note that the source warp set by the SET_SBMAP graphic order has no effect on this graphic order The XOFF XMUL parameter is divided into two fields The least significant four bits contain the XMUL field which specifies the factor used to scale the unexpanded source bitmap in the X dimension XMUL must equal a specific value from 0 15 which represents a scaling factor of 1 16 Only certain scaling factors are supported as defined in Table 13 3 Values other than those listed are ignored and no X scaling is performed The XOFF field occupies the four most significant bits and indicates the number of bits to be clipped at the left edge of the expanded source bitmap XOFF ranges from 0 XMUL If XOFF is zero no clipping occurs at the left extent but if itis non zero XOFF number of bits in the left edge of the expanded bitmap are skipped and the next bit is the first one transferred to the destination bitmap The YOFF YMUL parameter is also divided into two fields The least sign
207. fines the width of a video dot The active edge of VCLK is programmed by setting the PVCCR s VCP bit A synchronous print engine interface must source VCLK at a frequency that equals the expected video dot rate and supply an LSYNC signal that meets the setup and hold requirements of the MC68322 relative to the VCLK source However VCLK must be a free running clock For Mors On This Product Go to www freescale com Freescale Semiconductor QI The PVC is programmed for asynchronous operation by setting the PVCCR s VCS bit This causes the PVC to use the VCLK as a clock source and to enable the internal PLL circuitry The VCLK input is either 4 8 12 16 24 or 32 times the frequency of the video data rate the print engine requires The PLL circuit continuously generates internal 1 clock to drive the video subsystem When a print operation is active and LSYNC arrives the PLL adjusts the frequency of the internal 1x clock in synchronization with LSYNC s arrival The PLL guarantees that each scanline starts at the same point on the page with a maximum offset of an eighth of a dot The PLL always takes a 1 dot clock delay to synchronize with LSYNC Depending on the PLL prescaler value selected this will be a fixed time in the range of 4 to 32 VCLK periods A horizontal margin of zero dots is allowed Asynchronous interfaces need only provide an LSYNC signal that accurately identifies the start of
208. flag to indicate render direction When the least significant bit of the B2T byte is set all subsequent bitBLT and scanline transfers to banded bit maps are rendered in bottom to top order In other words bitBLTs begin at the bottom most scanline of each frame and proceed towards the top of the frame Scanline line tables are read starting with the last bit string specifier and executed in reverse order When the B2T flag is set the MC68322 expects all starting pixel addresses and table addresses to point to the bottom or end of their respective operands instead of the top Graphic orders that operate on frames or unbanded bit maps are unaffected by the B2T flag and are always rendered in a forward direction By rendering in a reverse direction the bands of a 180 page can be created in opposite order and transmitted to the print engine to print the back side of duplex pages The DWB parameter specifies the destination warp of the banded bitmap Note that if the banded bitmap is destined to be printed by the print engine video controller the bitmap must adhere to page image requirements In part the warp of the bitmap must equal to 0 mod 16 and the bitmap must not contain any pad words For Mort ON oduct to www freescale com Freescale Semiconductor Inc wiuvis The value of PSUBL is used to translate the logical destination addresses found subsequent banded graphic orders into physical memor
209. for the core s s ss 5 so s CLK2 A25 A1 CO AT may em 57 50 RD 3 27 CL WAIT MC 6 s 22 Eo o EC000 Core Read Cycle AC Timing Zero Wait State Access RSET 0 RACC 0 RHLD 1 Figure 14 3 Read Access 2 2 1 3 st s s s se 5 so s s s EN 9 25 1 O CS7 CS0 is RD 2 9o AS RW EC000 Core Read Cycle AC Timing Zero Wait State Access RSET 0 RACC 1 RHLD 0 Hold Time of 1 CLK2s The Chip Select Negates Before The RD Figure 14 4 Read Access 2 4 1 3 For More ie ah Go to www freescale com Freescale Semiconductor UNM NV WHA UVLO IOVS s s2 s A25 A1 so s s s ss 5 oo bo RR ale gt CS7 CS0 E RD Te 015 00 ql D c WAIT 5 RW 000 Core Read Cycle AC Timing Zero Wait State Access RSET 1 RACC 0 RHLD 0 Hold Time of 1 CLK2s The Chip Select Negates Before The RD Figure 14 5 Read Access 4 2 1 3 CLK2 25 1 57 50 RD 015 00 5 RW 000 Core Read Cycle AC Timing One Wait State Access RSET 0 RACC 0 RHLD 2 Figure 14 6 Read Access 2 2 3 3 For
210. freescale com Freescale Semiconductor 2 6 DMA INTERFACE The following signals control the DMA interface They are used to transfer data from the MC68322 bus to DRAM or vice versa DREQ Data Request This input signal whose polarity is programmable is asserted by a peripheral device to request a transfer between the internal core bus and DRAM The assertion of the DREQ signal starts a DMA operation DACK Data Acknowledge This active low output signal indicates that a DMA transfer is complete 2 7 PRINTER COMMUNICATION INTERFACE The following signals communicate with the print engine Due to various interfaces with different print engines some signals may not be needed PIN NAME DESCRIPTION CBSY Command Busy This output only signal indicates that a command byte is being sent to the print engine SBSY Status Busy This input only signal indicates that a status is ready to be received from the print engine CCLK Command Clock This bidirectional signal is used to clock command and status data between the MC68322 and the print engine It is not a free running clock and remains inactive until CBSY or SBSY is asserted The print engine or the MC68322 can supply CCLK The direction of this pin is programmable and engine dependent CMD STS Command Status This bidirectional signal is provided because some print engines require command and status on the same line
211. ft HXR must be set to HW and HYR to HH If instead a 180 page is rendered and the B2T flag is set HXR must still be set to HW but HYR must be set to one The HA parameter defines a physical bit address within the halftone bitmap HA must point to the upper left corner of the transfer frame when the B2T flag is clear and to the lower left corner of the frame when the B2T flag is set Also HA must be consistent with HXR and HYR A band fault is detected when the transfer frame extends past the end of the destination bitmap which is defined by the EOBPA operand in the SET_BBMAP graphic order When a band fault is detected the MC68322 rewrites the graphic order to update its operands The BAND number is incremented or decremented when the B2T flag is set DA SA and HA are repositioned to the starting pixel of the respective frame to be processed in the next band and YOFF is updated according to the current position in the expanded source bitmap Lastly FH and HYR are written back with the number of remaining scanlines in their respective frames to be transferred Related Graphic Orders SET BOOL SHD SET BBMAP SET HTBMAP For Mort RSE ON ANA oduct Go to www freescale com Freescale Semiconductor Inc MAT wires UNEXPANDED SOURCE BITMAP HALFTONE BITMAP HW SAm lt gt SW ut DESTINATION BANDED BITMAP lt DWB zi lt 2 1 BOOL_SHD USED
212. g an arbitrary sequence of defined instructions in valid form starting in the state the machine was before the attempt was made to execute the given instruction For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor breakpoint An event that forces the machine to branch into a breakpoint exception routine bubble A number inside a circle that is used to identify specific terms in AC timing diagrams burst A bus transfer that has more than one piece of data associated with it burst length The number of data associated with a burst cycle For example a burst length of four has four data pieces four beats associated with it bus park Keeps the bus granted to a bus master although it has completed the bus cycle This allows the same master to make the next transfer without having to rearbitrate for the bus copyback Updates to external memory are delayed until forced by the user program or a transfer of bus control to an external master At the time of forced update or relinquishment of the bus all changes to the cache are written to external memory Until that time cache and external memory are not coherent critical data first This feature allows the data transferred during the burst cycle to be organized where the word or data needed first is the first one to transfer within the burst data block The order of transferring can be sequential and usually wraps back to the w
213. g conventions discussed in previous sections also apply to graphic order address parameters All address fields are 32 bits wide Address parameters that reference bit maps specify bit addresses while all others require conventional byte addresses The RGP requires all display lists scanline tables and companion halftone tables to start on word aligned addresses Since all graphic orders bit string specifiers and halftone specifiers are an even number of bytes in length this guarantees that all successive orders and specifiers begin at word aligned addresses as well This requirement also guarantees that all word and long word operands and field values are aligned on word boundaries This is important for the core which can access word and long word data only on word boundaries These rules do not apply to the actual bitmap data which has no alignment requirements The RGP internally stores all addresses in 32 bit registers and performs all address calculations using 32 bit arithmetic When the RGP makes an access to DRAM for bitmap data the bitmap address must first be converted to a byte address to accommodate the fetch This conversion is done first by stripping off the low order four bits these bits select a bit within the word and then shifting the address to the right by three bits This produces a word aligned byte address that is used for a 16 bit DRAM fetch of the bitmap data MC68322 USER S MANUAL 12 15 For More Information On Th
214. generates an RGP done interrupt event the software should adjust the display list to reflect the next band information and then restart the RGP The quantity size and location of band buffers is determined by the core s software These band parameters can be dynamically altered to suit a particular application or page complexity The band numbers are under software control to allow for nonsequential band processing applications like duplex printing Depending on the length of the display lists and interrupt latency one or both display lists can complete and generate an RGP done interrupt event before any interrupt is even serviced To determine whether one or both display lists has executed the software must first clear the RIER s RDN bit then reread it to examine the current setting If the RIER s RBY bit is set and a RGP done interrupt is being serviced then one display list has finished and the second display list is currently being executed If the RBY bit is clear both display lists have finished and the RGP is sitting idle For On The Product Go to www freescale com Freescale Semiconductor Inc detect certain errors during the execution of a display list including an out of range display list start address out of range graphic order operand addresses and illegal graphic order opcodes When the RGP detects one of these errors it i
215. graphic order is executed Long Word Destination logical bit address Word Frame width in bits Word Frame height in scanlines Long Word Source physical bit address Note Denotes A Parameter That The MC68322 Updates When The Frame Crosses A Band Boundary The BLT2BB SD graphic order causes the MC68322 to bitBLT a source frame to a destination banded bitmap The source and destination pixels are combined as specified by the current BOOL SD Boolean code The destination bitmap parameters must have been previously defined by the SET BBMAP graphic order The source frame warp is assumed to be the FW specified in the BLT2BB SD graphic order unless a non zero source bitmap warp was previously defined by the SET SBMAP graphic order in which case the latter is used DA specifies the logical bit address of the area or transfer frame that starts in the destination banded bitmap The logical bit address is converted to a physical bit address by adding the PSUBL value set by the SET BBMAP graphic order The start of the transfer frame must be within the bounds of the banded bitmap but the end of the transfer frame may extend past the end of the bitmap DA must point to the upper left corner of the transfer frame when the B2T flag is clear and to the lower left corner of the transfer frame when B2T is set The warp of the destination banded bitmap is set by the SET BBMAP graphic order which allows the bitmap to be packed or unpacked The source ph
216. graphics bus 1 2 4 System Integration Module The system integration module SIM provides the ROM PROM and peripheral chip selects It contains eight chip select banks that can be programmed to decode addresses and supply internal DTACK termination These eight chip select banks are individually programmable for an address range of 256K to 64M They can be located anywhere within the 256M memory map and be either contiguous or disjointed as required by the operating environment Also each chip select bank can be independently Size or disabled The chip selects for each bank can be set up to provide a wide range of timing parameters such as setup access hold and recovery times for both read and write bus cycles The MC68322 s SIM provides internal bus cycle auto acknowledge and the asynchronous WAIT signal allows external devices to insert additional wait states as needed The SIM also allows SRAM to be added to the MC68322 bus for system stack space temporary data storage or as a buffer for peripheral data MC68322 USER S MANUAL 1 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction 1 2 5 DRAM Controller The MC68322 provides a fully integrated bursting DRAM controller containing six DRAM banks of varying programmable sizes and locations They can be located contiguously or disjointedly as required by the operating environment The DRAM controller multip
217. gt lt lt Figure 14 1 Clock AC Timing CLK2 RESET Figure 14 2 RESET AC Timing For On The Product Go to www freescale com Freescale Semiconductor Inc MeV GR 14 4 2 MC68322 Bus Timing Dw pews O EE pT NOTE WAIT is an asynchronous input and is synchronized internally by MC68322 It requires no setup hold time in order to be recognized for proper operation However to guarantee recognition of the input at certain edge of CLK2 WAITmust satisfy the hold requirement The timing diagrams that follow illustrate core reads and writes Figures 14 3 through 14 5 illustrate combinations of chip select parameters that produce zero wait state reads on the 000 bus Figures 14 6 through 14 9 illustrate combinations of chip select parameters that produce one wait state reads on the 000 bus Figure 14 11 illustrates the only combination of chip select parameters that produce zero wait state writes on the 000 bus Figures 14 12 through 14 14 illustrate combinations of chip select parameters that produce one wait state writes on the 000 bus The access times for each timing diagram are shown in parentheses in CLK2s T
218. h sections of the device contain circuitry to protect against damage from high static voltages or electrical elds take normal precautions to Thermal Characteristics 14 2 THERMAL CHARACTERISTICS CHARACTERISTIC SYMBOL VALUE RATING Thermal Resistance Junction to Case PGA Package For 11093259 MANDA Product Go to www freescale com Freescale Semiconductor UNM FEWER WHA UVEITIS 14 3 DC ELECTRICAL SPECIFICATIONS CHARACTERISTICS SYMBOL UNIT 1 Three State and Open Drain Leakage Current Output High Voltage Rated Maximum 4 75 V Vy Output Low Voltage I E Rated Maximum Yw 7 2 Current Drain TA 70 C 5 25V f 16 667 MHz Input Capacitance CN pF All Input Only Pins 10 All VO Pins 20 Output Drive Derating Factor a 8 mA Output Pins WE WRU WRL 015 00 CS7 CS0 25 1 PRINT MD15 MDO 10 DTACK CLK1 DTACK BG AS CBSY CCLK and CMD STS 16 mA Output Pins SELECT RAS5 RASO PERROR PD7 PDO FAULT 51 CASO BUSY and 24 mA Output Pin VIDEO ICE Bond Out Option 4 mA Output Pins DLEN IPL2 I IPLO HALT BR and AVEC NOTES 1 Notincluding internal pull up 2 Currents listed are with no loading 3 Theoutput drive derating factor applie
219. halftone screen to a data transfer to modify its appearance Halftone screens are used to produce shades of gray ina monochrome printing environment such as printing presses dot matrix printers or laser printers Halftone screens are commonly seen in newspapers because that is where photographs with levels of gray are represented with a medium that only allows black and white Halftone screens are repetitive in both the X and Y dimensions of a bitmap array For example to perform shading a 10101010 pattern might be applied to the even scanlines and a 01010101 pattern to the odd scanlines 1 10 MC68322 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction 1 4 5 Duplex Printing The MC68322 supports duplex printing applications Duplex printing is the operation of placing an image on both sides of a page before it leaves the printer In a duplex laser printer paper travels out of the input hopper and under a drum to receive a toner image The paper then travels through a fuser to set the toner onto the first side of the paper and into an internal duplex hopper Next the paper moves out of the duplex hopper and under the drum again to receive the second toner image this time on the reverse side of the paper Finally once the second image has been fused the paper is placed in the output hopper DOUBLE SIDED PAPER PATH DUPLEX HOPPER om al INTERNAL PA
220. he 16 bit data bus and internal 32 bit address bus The core has the following features Eight 32 bit address registers Eight 32 bit data registers 4G direct addressing range Fifty six instructions Operations on five data types Memory mapped input output Fourteen addressing modes 3 1 PROGRAMMING MODEL The 000 core programming model is separated into two modes of access user supervisor The user mode provides the execution environment for a majority of the application programs The supervisor mode allows some additional instructions and privileges that the operating system and other system software use The M68000 Family Programmer s Reference Manual can be another source for programming model information For 11093259 MANDA Product Go to www freescale com Freescale Semiconductor wun USER PROGRAMMING MODEL 0 r DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER SUPERVISOR PROGRAMMING MODEL 31 0 22 ATISSP SUPERVISOR STACK POINTER SR STATUS REGISTER NOTE CCR is also illustrated in the user programming model Figure 3 1 000 Core Programming Model As illustrated in Figure 3 1 the user mode provides access to sixteen 32 bit general purpose registers a 32 bit program counter and an 8 bit condition code register The first eight registers 00 07 are used as data registers for byte 8 bit word 16
221. he last specifier s X and displacements put it The displacements specified by DX DY for 16 and 32 bit bit string specifiers and DZ for 48 bit bit string specifiers are applied before executing the scanline run for a 0 page and after executing it for a 180 page Figure 12 4 illustrates a scanline run using the values in the bit string specifier fields Notice that destination address A is the initial address for 0 pages as well as the final address for 180 pages in turn address is the final address for 0 pages and the initial address for 180 pages DESTINATION ADDRESS A DISPLACEMENT DY AN INE B DESTINATION SCANLINE RUN gt ADDRESS DX RL Figure 12 4 Scanline Run Operation For On This Product Go to www freescale com Freescale Semiconductor AF erus R2 When rendering to banded bit maps of 0 pages or to frame and unbanded bit maps the displacement is added to the current destination address before the scanline is drawn The scanline run is then completed in a left to right direction When rendering to banded bit maps of 180 pages the run length is first subtracted from the current destination address and that address is saved Then the scanline run is carried out in a left to right direction and the displacement is subtracted from the saved destination address 12 6 3 Executing Dur
222. he microprocessor to halt execution If the core accesses a chip select bank or chip select register a DRAM refresh cycle can occur simultaneously However if the core accesses DRAM during a refresh operation it is delayed until the refresh cycle completes When the refresh cycle occurs the RGP and PVC will also be delayed Figure 7 6 illustrates a DRAM refresh cycle START 2 Wem 015 00 We REFRESH CYCLE Figure 7 6 DRAM Refresh Cycle For On The Product Go to www freescale com Freescale Semiconductor 7 4 2 DRAM Read Cycles The timing mode selected during setup determines the sequence of events that join to form a DRAM read cycle WE remains negated during these events The events in timing order are The row address is placed on the memory address bus 10 The address selects one of the RAS signals which is then asserted The column address is placed on the memory address bus 10 The CAS1 and CASO are asserted Data is read RASx 51 and CASO are negated Figures 7 7 to 7 9 illustrate the DRAM read cycle timings for each of the three timing modes START WAIT WAIT WAIT READ DATA WAIT WAIT READ DATA START miomo Row RASS RASO CAST CASO i 016 00 brava SINGLE CYCLE FAST PAGE CYCLE gt Figure 7
223. he numbers within the parentheses are defined as follows Setup Access Hold Recover The Setup value indicates the number of CLK2s between the assertion of the chip select and RD WRU or WRL The Access value indicates the number of CLK2s that the RD WRU or WRL signal will remain asserted The Hold value indicates the number of CLK2s between the negation of RD WRU or WRL and chip select Note that some of the access times are flagged with an asterisk because the access has a hold time of 1 CLK2s This situation occurs whenever the hold value in one of the chip select registers is set to zero In this case the chip select actually negates one CLK2 before the RD WRU or WRL This is important because for reads in such cases the data must be set up to the negation of the chip select rather than the negation of the RD signal The Recover value indicates the number of CLK2s between the negation and reassertion of the chip select chip select high time These timing diagrams are all shown without extra recovery clocks so the recovery time for each of the cycles will be 3 CLK2s For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor Inc To calculate the total cycle time add the values in the parentheses For example Figure 1 3 shows an access time of 2 2 1 3 The total cycle time for this setup will be 8 CLK2s or 4 CLK1s which is a zero wait state access
224. hese DRAM banks can be contiguous to or disjointed from each other as required by the operating environment Even though the DRAM bank can be any size the starting address must be unique non overlapping and located on an address boundary equal to its size For example an 8M DRAM bank must be on an 8M address boundary DRAM address space can however overlap with other registers ROM or I O space In case of an overlap DRAM has the lowest priority 7 1 2 ROM Mode MC68322 DRAM controller ROM mode is available in the G59B Mask Set The ROM mode of operation causes the selected DRAM channel to run with extended cycle times while the remainder of the channels operate at full speed This will place font ROMs on one of the DRAM channels with only an external latch required to demultiplex the address signals By placing the font ROMs on one of the DRAM channels the MC68322 RGP will have direct access to font data which eliminates the need for a font cache thus reducing overall system DRAM requirements ROM mode is selected for a particular DRAM channel by setting the ROM mode bit in the corresponding DRAM register see Figure 7 1 for details 7 1 2 1 FUNCTIONAL DESCRIPTION When the ROM mode is selected for one of the DRAM channels the accesses to that channel are extended Each initial and burst access is extended by CLK1 period two CLK2 periods For example in timing mode 1 the normal DRAM access time in CLK1s would be 4 2
225. hronized internally by the MC68322 It requires no setup or hold time to be recognized for proper operation However to guarantee recognition of the input at a certain edge of CLK2 DREQ must satisfy the hold requirement CLK2 u 4 er Figure 14 19 Request Acknowledge Timing DREQ For More MES BM M V b oduct Go to www freescale com Freescale Semiconductor MWR CPI WHA UVLO IOVS 14 4 5 Print Engine Interface Timing a CELK Period Period C eiue pe Frequency of Operation 1x Mode T PLL Mode VCLK Period 1x Mode PLL Mode 36 37 VCLK Pulse Width 1x Mode PLL Mode 38 39 Rise and Fall Times 1x Mode PLL Mode FSYNC LSYNC Asynchronous Input Hold after VCLK 34 1x Mode FSYNC only PLL Mode 4 S LSYNC Setup before VCLK 59 EA SYNC Hold after VCLK 56 FSYNC LSYNC Pulse Width 6 1 PRINT Valid from CLK2 1 Applies only when CCLK is configured as an input 2 CCLK and CMD STS when gured as inputs and SBSY and STS are asynchronous inputs and are synchronized internally by the MC68322 They require no setup or hold time in order to be recognized for proper operation However to guarantee recognition of an input at a certain edge of CLK2 the input must satisfy the hold requirement 3 FSYNC in 1
226. ideo subsystem is started which is also started when the page image bit address register is written PFL is cleared Next the video interface controller begins waiting for FSYNC and once it arrives a page band begin interrupt event is posted and the controller waits for the leading active edge of LSYNC Then after LSYNC arrives the vertical margin count is decremented and the controller again waits for LSYNC When the vertical margin decrements to zero the next LSYNC causes the horizontal margin count to be decremented for each internal video clock until it reaches zero At this time the first bit of video data is transmitted Video data is loaded from the memory subsystem s FIFO into a 16 bit shift register On each active edge VCLK data is shifted out When the last data bit is shifted out the shift register is reloaded As the video subsystem shifts out video data and empties the FIFO the memory subsystem makes additional memory fetches The FIFO is filled until the page image height and width values decrement to zero at which time BSY is cleared and the memory subsystem returns to idle Every internal video clock decrements the page width counter When the page width counter reaches zero the page height counter is decremented if it is not zero the video interface controller returns again to wait for LSYNC When the page width and page height reach zero the transmission completes and the video interface controller p
227. ificant four bits contain the YMUL field which specifies the factor used to scale the unexpanded source bitmap in the Y dimension YMUL can equal any value from 0 15 which represents a scaling factor of 1 16 The YOFF field occupies the four most significant bits and indicates the number of scanlines to be clipped at the top edge of the expanded source bitmap YOFF ranges from 0 YMUL If YOFF is zero no clipping occurs at the top or bottom extent but if itis non zero YOFF number of scanlines at the top edge of the expanded bitmap are skipped and the next scanline is the first one transferred to the destination bitmap Halftone tiled patterns are typically anchored to the page Thus a bitBLT may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where itis positioned on the page The halftone parameters HYR and HA define the precise halftone pixel that corresponds to the upper left corners of the source and destination frames HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the bottom edge HXR and HYR must be in the following ranges 1 lt HXR x HW and 1 x HYR x HH where HW and HH are the width and height of the halftone bitmap respectively For example if the starting pixel in the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH to start at the lower right
228. igh Impedance Mode The high impedance mode HI Z and TEST pins can be used to place the MC68322 into a three state mode that allows an in circuit emulator to be used Table 2 2 shows all combinations of the HI Z and TEST pins See Appendix D Alternate Pin Functions for more information on the proper use of the input pin mode Table 2 2 7 and TEST Combinations HI Z TEST FUNCTION 0 0 Three State All Outputs 0 1 Input Pin Mode A 22 25 Three Stated 1 0 Normal Mode A 22 25 Enabled 1 1 Special Test Mode Do Not Use For On The Product Go to www freescale com Freescale Semiconductor 2 4 EXTERNAL BUS MASTER INTERFACE The following signals control the MC68322 bus operation PIN NAME AS DESCRIPTION Address Strobe The active low AS signal indicates a valid address on the address bus ASis an output when the core or internal DMA initiates an access on the MC68322 bus and an input when an external bus master controls the MC68322 bus Read Write This signal defines data bus transfer as a read active high write cycle active low R Wis an output when the core or internal DMA initiates an access on the MC68322 bus and an input when an external bus master has control of the MC68322 bus External Bus Master Data Transfer Acknowledge This output signal is sent to an external bus master to indicate that the d
229. igh to low transitions of CCLK so that the status can be sampled on every rising edge The CCLK period must be at least four CLK1s for proper sampling of each status bit After all eight bits of the status are sampled the print engine interface enters a recovery cycle The recovery time is one half CCLK period as programmed in the PCOMR s CCLK divisor field When the status operation is complete the PCIER s STR bit is set thus indicating that the PCOMR s printer status field is full If enabled this bit causes an interrupt event SBSY is an asynchronous signal to the print engine interface and is internally synchronized to CLK1 The print engine should not assert the signal at any time during a command operation or recovery cycle Once SBSY has been asserted it must remain that way until the status operation is initiated Figure 10 10 illustrates the timing diagram for a status operation when the print engine supplies CCLK 1C 2C 3C 4C 5 6 7 8 9C 10C NOTE CBSY CMD STS are high impedance STS is sampled by 000 core B Recovery cycle half CCLK period Any pending command is acknowledged after the recovery Figure 10 10 Status Operation Print Engine Supplied CCLK For On The Product Go to www freescale com Freescale Semiconductor mnywe 10 3 4 PLL Video Clock Divisor The 8x PLL circuitry can clock on either the risi
230. ignments 2 end eee wien rain 5 9 5 4 Exception Grouping and Priority code rer Ree voce npe de exe geo cete E Rue d 5 13 B 1 Size Field Encoding secte ee O demam EO NU A E 6 3 6 2 Synchronous Timing Values teca be meat t eo eei cent 6 4 7 14 DRAM Size ODpLOFIS 2 1 Leni eet aki 7 2 fe2 DRAM Timing Modes pede bettie genteel Ga Re oil 7 5 Clie BDM Field 8 4 SEC ANG SIG EMCOGINGS te ocid i 10 3 10 2 PLL Video Clock Divisor 22 Sar s rt 10 15 12 1 Graphic Operation Data Operand Constant Values 12 2 12 2 Bit String Specifier Field Definitions 2 44 242242404 4 12 8 12 3 bitBLT and Scanline Execution Times 4 24 12 14 13 1 Graphic Order Organization oiii crine roro eRe 13 2 13 2 Graphic Orders Sorted by 13 8 13 3 Supported Scaling Factors 13 17 For Mon zi MANUS Product Go to www freescale com Freescale Semiconductor LIST OF TABLES Continued Table Page Number Title Number 1 ICE Interface Signal Summary 1 2 Data Strobe Control of Data Bu
231. imension and a logical coordinate that defines the Y dimension When specifying a banded bitmap in a transfer of data the transfer of data is checked against the Y boundary of the bitmap If the data falls beyond the Y boundary a band fault occurs and the transfer of data for the current graphic order is prematurely terminated Unbanded An unbanded bitmap also has a warp associated with it that only defines the X dimension However there is no logical coordinate associated with its Y dimension The significance of this is that no boundary checks are made for unbanded bit maps When specifying an unbanded bitmap in a transfer of data it is assumed that the bitmap is of sufficient size to complete the transfer Unexpanded An unexpanded bitmap is a two dimensional array of pixels that represents a low resolution image Typically an unexpanded bitmap describes a bitmap image that is created at 75 100 150 200 or 300 dpi In contrast all other bit maps have an implied resolution that matches the print engine resolution which can be 300 600 or 1200 dpi Unexpanded bit maps can be positioned anywhere in memory packed or unpacked and they do not need to be aligned to word boundaries Also an unexpanded bitmap is always used as a source bitmap by expanded graphic orders Expanded An expanded bitmap is a conceptual term that describes the outcome of processing an unexpanded source bitmap during the execution of an expanded graphic order Th
232. ination bitmap and either the source or halftone bitmap the halftone applied to the destination All graphic orders of the form XXXX SHD such as BLT2BB SHD define 3 operand transfers that specify the destination bitmap source bitmap and halftone bitmap the halftone applied to the source and destination 12 4 BOOLEAN CODES The preferred result of a graphic operand transfer must be specified by means of the 1 byte Boolean code that directs the MC68322 to logically combine the given source destination and or halftone operands during the graphic operation Figure 12 1 illustrates eight common Boolean coded graphic operation transfers and all 256 Boolean coded graphic operation transfer combinations are represented in Figure 12 2 They involve all possible logical combinations between the true and inverted versions of the three operands D DESTINATION SOURCE HT HALFTONE BIT MAP BIT MAP BIT MAP CLEAR OPAQUE TRANSPARENT FULLY TRANSPARENT D 4 0 04 5 D 4 5 0 D 4 SAHT D CLEAR TO BLACK CLEAR TO PATTERN OPAQUE TRANSFER SEMI TRANSPARENT D 1 D 4 HT D 4 SAHT D 4 SAHT ISAD Figure 12 1 Eight Common Graphic Operation Transfers For On This Product Go to www freescale com Freescale Semiconductor supine DESTINATION SOURCE HALFTONE BIT MAP BIT MAP BIT MAP 00 03 04 co 0A 00 0 OF
233. ing Banded Applications When executing a scanline table for a banded bitmap the MC68322 performs boundary checking to detect a band fault before executing each bit string specifier A band fault occurs when the destination bitmap is a banded bitmap and the scanline frame extends below the end of the band A band fault will cause the scanline transfer to terminate prematurely The remainder of the display list is processed in the event of a band fault but the execution of the scanline table resumes when the display list is rerun to render the next band of the page image The MC68322 does not however check for a band fault while processing the scanline run lengths During banding applications there are two ways to use bit string specifiers that can cause unwanted destruction of data The destruction occurs when the bit string specifier causes processing to occur outside of the banded bitmap One way is when a bit string specifier contains a signed offset that references a previous band see Figure 12 5 The MC68322 checks only the lower boundary of the banded bitmap so the violation goes undetected Normally the MC68322 would process the bit string specifier s run length at a memory location that is not contained within the target bitmap PREVIOUS BAND CURRENT BAND NEXT BAND Figure 12 5 Illegal Bit String Specifier Use Another way is when a bit string specifier contains a run length that wraps from one scanline to anoth
234. ing a read and a lower byte write cycle a Lower Write Strobe This strobe is an output only signal that asserts during a write operation on the MC68322 bus A write cycle can be initiated by the core internal DMA or external bus master The lower write strobe asserts during all word write operations and during byte write operations to the lower portion of the data bus D7 D0 WRL remains negated during a read and an upper byte write cycle Wait This input only signal that extends MC68322 bus cycle beyond the programmed values Be aware that WAIT can only prolong bus cycles for chip select banks 2 ge 2 External Interrupt Request These input only signals have programmable assertion levels and used to connect external interrupting devices to the MC68322 These two signals are sent through the internal interrupt controller before posting an interrupt to the core For On The Product Go to www freescale com Freescale Semiconductor wry wvoviip uvg 2 5 DRAM INTERFACE The following signals control the DRAM bus operation PIN NAME DESCRIPTION 10 0 Memory Address Bus These 11 output only signals connect to the internally multiplexed DRAM address bus They directly drive the memory address bus to a DRAM array The low order address signals change to provide bursting capability See Table 2 3 for a list of DRAM address multiplexing values
235. ing the last run rendered or when the B2T flag is set the pixel preceding the next bit string specifier s run and SLTA points to the next specifier to be executed when the rest of the scanline table is rendered to the next band The contents of the scanline table is left unchanged after a band fault Related Graphic Orders SET BOOL D SET BBMAP For Mort ON oduct to www freescale com Freescale Semiconductor Inc MAT wires SCANLINE TABLE DESTINATION BANDED BITMAP SLTA EN DWB i lt BITSTRING SPECIFIERS DISPLACEMENT BOOL_D APPLIED TO FRAME Figure 13 26 Destination Scanline Transfer to Banded Bitmap 0 Page SCANLINE TABLE DESTINATION BANDED BITMAP BOOL_D APPLIED TO FRAME BITSTRING SPECIFIERS lt DWB SLTA Figure 13 27 Destination Scanline Transfer to Banded Bitmap 180 Page For 160322 ation On This broduct Go to www freescale com Freescale Semiconductor Inc uv EORR SL2BB_HD Halftone Destination Scanline Transfer to Banded Bitmap PARAMETERS DESCRIPTION Byte SL2BB HD Opcode Byte Band number when graphic order is executed Long Word Destination logical bit address Word Halftone X remainder Word Halftone Y remainder Long Word Halftone physical address of the starting pixel 28 of 32 bits Companion halftone table
236. inning of each successive scanline Notice that the source warp set by the SET_SBMAP graphic order has no effect on this graphic order The XOFF XMUL operand is divided into two fields The least significant four bits contain the XMUL field which specifies the factor used to scale the unexpanded source bitmap in the X dimension XMUL must equal a specific value from 0 15 which represents a scaling factor of 1 16 Only certain scaling factors are supported as defined in Table 13 3 Values other that those listed are ignored and no X scaling is performed The XOFF field occupies the four most significant bits and indicates the number of bits to be clipped at the left edge of the expanded source bitmap XOFF ranges from 0 XMUL If XOFF is zero no clipping occurs at the left extent but if itis non zero XOFF number of bits in the left edge of the expanded bitmap are skipped and the next bit is the first bit transferred to the destination bitmap The YOFF YMUL operand is also divided into two fields The least significant four bits contain the YMUL field which specifies the factor used to scale the unexpanded source bitmap in the Y dimension YMUL can equal any value from 0 15 which represents scaling factor of 1 16 The YOFF field occupies the four most significant bits in the YOFF YMUL operand YOFF indicates the number of scanlines to be clipped at the top or bottom edge of the expanded source bitmap depending on the value of the B2T flag
237. ion or implicitly defined by the instruction operation Table 3 1 lists the data formats for the core Refer to the M68000 Family Programmer s Reference Manual for details on data format organization in registers and memory Table 3 1 Processor Data Formats OPERAND DATA FORMAT Binary Coded Decimal BCD Word Integer 16 Bits Long Word Integer 32 Bits The core also supports the basic addressing modes of the M68000 Family The register indirect addressing modes support postincrement predecrement offset and index capabilities The program counter relative mode also supports indexing and offsetting Table 3 2 lists a summary of the data addressing modes for the core Refer to the M68000 Family Programmer s Reference Manual for details on the core s effective addressing modes Table 3 2 Effective Addressing Modes ADDRESSING MODES SYNTAX Register Direct Addressing Data Register Direct EA Dn Address Register Direct EA An Absolute Data Addressing Absolute Short Next Word Absolute Long Ned Two Words Program Counter Relative Addressing Relative With Offset 446 Relative With Index and Offset ae PC 48 Register Indirect Addressing Register Indirect EA An Postincrement Register Indirect Predecrement Register Indirect An N EA An Register Indirect With Offset E Indexed Register Indirect With Offset 98 Immedi
238. ion transfer count This value is required to determine the amount of data remaining to be transferred when a DMA channel is shut down using flush request To assure an accurate value after issuing a flush request the transfer count should be read only after receiving a DMA complete interrupt event This ensures that all data was transferred and is reflected in the count value 8 1 3 Flush Request FR Fields Each DMA channel contains a write only control field FR that allows the core real time control over an active DMA transfer A read by the core results in a value of zero The FR bit when set during an active transfer shuts down the transfer and then returns the DMA channel to a condition ready for a new operation For transfers to DRAM the FR bit instructs the channel to disable reading source data and to finish transferring any data left in the internal data latch to DRAM For transfers from DRAM the FR bit instructs the DMA channel to disable reading source data and to discard any data left in the internal data latch that was read from DRAM When completed a DMA complete interrupt is posted and the DMA channel controllers return to the idle state 8 2 GDMA CONTROL REGISTER The GDMA control register GDMCR is used to configure the transfer direction transfer data width and DREQ input mode as well as enable CSx during MC68322 bus cycles This register is not double buffered and writing a new value during an active transfer will chang
239. is Product Go to www freescale com Freescale Semiconductor SECTION 13 GRAPHIC ORDERS This section describes the MC68322 graphic orders and lists them in alphabetical order For each graphic order a functional description opcode parameter format and definitions of its parameters are provided Graphic orders specify one or more graphic operands as indicated in the mnemonic by the last few characters See Section 12 Graphic Operations for more information 13 1 TYPES OF GRAPHIC ORDERS The five types of graphic orders consist of the following Initialization Program flow control Bit block transfer Expanded bit block transfer Scanline transfers The initialization bit block transfer and expanded bit block transfer graphic orders are processed as a stream of instructions from the display list The scanline graphic orders include a pointer to a scanline table that is a compressed run length encoding of an image such as a font character 13 1 1 Initialization Initialization graphic orders those whose mnemonics begin with SET define bitmap parameters and Boolean codes to be used during transfers The SET_BMAP graphic orders are defined for four bitmap types banded unbanded source and halftone They are used to load bitmap parameters into internal registers The four SET BOOL graphic orders are defined for each type of Boolean operation destination only _D halftone and destination _HD sour
240. is enabled only when the PPCR s PDE bit is clear Latching occurs based on every high to low transition of STROBE regardless of the handshaking mode being enabled or disabled STROBE like all PPI control inputs is synchronized and optionally digitally filtered before it is used internally by the PPI This affects the point at which parallel port data is latched The 9 bit data input to the latch is not synchronized or digitally filtered Figure 9 8 illustrates the timing diagram for parallel port data bus latching CLK1 DATA 5 BUSY DATALATCHED DATA LATCHED IF DFE 0 IF DFE 1 Figure 9 8 Parallel Port Data Latch Timing Diagram For On The Product Go to www freescale com Freescale Semiconductor t Vit Ew 9 7 ON RESET The assertion of RESET causes all PPI registers and register fields to be cleared to zero with one exception The BSY2 bit in the PPIR is set and remains that way until the software explicitly clears it This is intended to delay the host long enough for the software to initialize the PPI The RST bit in the PPCR resets the PPI state machine which includes the hardware handshake controller and run length decompression logic Normally when RST is set MODE is set to 002 to prevent the state machine from starting again RST immediately causes the handshake controller and the run length decompres
241. is generated as soon as data is available from the DMA source Figures 8 6 and 8 7 illustrate byte and word sized DMA write transfers across both MC68322 and DRAM buses In these figures the transfer count register is set to two For More ie ash M product Go to www freescale com Freescale Semiconductor 125 LOAD TRANSFER COUNT BUSY FULL CYCLE ACTIVE MC68322 BUS MC68322 BUS DRAM DMA REQUEST INTERRUPT Figure 8 6 Byte Sized DMA DRAM Write Transfer LOAD TRANSFER COUNT BUSY FULL MC68322 BUS DRAM MC68322 BUS REQUEST Figure 8 7 Word Sized DMA DRAM Write Transfer 8 7 DMA TRANSFER TERMINATION A DMA transfer can terminate when one of the three following conditions occur normal termination bad address or an core forced termination 8 7 1 Normal Termination Normal termination is the normal conclusion of a DMA transfer and it occurs when the source and destination transfer counters have decremented to zero and no address value errors have occurred When the DMA transfer completes the CMP and TCR bits in the channel s interrupt event register are set and an interrupt is posted to the core if enabled For On This Product Go to www freescale com Freescale Semiconductor ww 8 7 2 Bad Address Termination If at some p
242. l can be individually enabled or disabled by programming each bit of the enable field Setting each bit enables its respective event and clearing it masks the event If an event is enabled an interrupt is sent to the core The following are GDMA and PDMA interrupt events and their bit field descriptions BSY Busy This bit is set when the DMA channel s transfer count field is written indicating that the channel is active and that the core should not write to the channel s configuration registers This bit is cleared when the final transfer has completed and the channel remains idle and is ready to accept new register values FLL Full This bit is set when byte or word sized data is held in the DMA data latch and is cleared when the transfer operation is complete The combination of the BSY and FLL bits indicate real time status TCR and CMP Terminal Count Reached and Complete The TCR bit indicates when a DMA transfer is completed under normal termination the number of transfer operations equals the value programmed the channel s configuration register transfer count field When the TCR bit is set the DMA channel is finished with its transfer The CMP bit is then set indicating that the DMA registers are ready to be written for the next DMA transfer For On This Product Go to www freescale com Freescale Semiconductor Address An illegal address
243. l filtering 1 Status Read only Indicates the level driven on ACK This bit is the ACK2 bit NOR ed with ACK from the PPI state machine This bit is set on reset BSY1 BUSY Status Read only Indicates the level driven on BUSY This bit is the BSY2 bit OR ed with BUSY from the PPI state machine This bit is set on reset ACK2 ACK Control 2 forces a low level to be driven on ACK This is generally done when hardware handshaking is disabled and the PPI state machine is idle The ACK2 bit is NOR ed with ACK from the PPI state machine before driving ACK If ACK2 is set then the ACK pin is forced low and the 1 bit is cleared BSY2 BUSY Control BSY2 forces a high level to be driven on BUSY This is generally done when hardware handshaking is disabled and the PPI state machine is idle The BSY2 bit is OR ed with BUSY from the PPI state machine before driving BUSY If BSY2 is set then BUSY is forced high and the BSY1 bit is set BSY2 is set on reset PER PERROR Control Setting this bit drives a high level and clearing it drives a low level on PERROR For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor Vit Ew SEL SELECT Control Bit Setting this bit drives a high level and clearing it drives a low level on SELECT FLT FAULT Control Bit Setting this bit drives a high level and clearing it drives a low l
244. l in the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH to start at the lower right HXR and HYR must be set to one The HA parameter defines a physical bit address within the halftone bitmap and must point to the upper left corner of the transfer frame HA must be consistent with HXR and HYR Related Graphic Orders SET BOOL SHD SET HTBMAP For Mort ON oduct to www freescale com YMUL Freescale Semiconductor UNEXPANDED HALFTONE BITMAP SOURCE BITMAP 5 SW EXPANDED XMUL SOURCE BITMAP lt DESTINATION FRAME DA E BOOL_SHD USED TO COMBINE FRAMES lt gt FW Figure 13 17 Expanded Source Halftone Destination bitBLT To Frame For Mort 160322 On This Product Go to www freescale com MAT __Freescale Semiconductor BLT2UB D Destination Only bitBLT to Unbanded Bitmap PARAMETERS sm DESCRIPTION Byte Byte Long Word Word BLT2UB D Opcode Reserved Destination physical bit address Frame width in bits Word Frame height in scanlines The BLT2UB D graphic order causes the MC68322 to modify the frame of a destination unbanded bitmap The destination pixels are manipulated as specified by the current BOOL D Boolean code The SET graphic order must previously define the destination bitma
245. le 2 1 Signal Summary Continued THREE STATED MNEMONIC INPUT OUTPUT ACTIVE STATE EAE NN 25 lom IEEE TIED n ee STS 2 Voc IDEO WE WRL WRU Low Low wo ww w om ww NOTE Becomes An Input BG Which Effectively Three States The Signal 7 Note Assertion and negation used to specify forcing signal to a particular state 2 1 ADDRESS BUS Assertion and assert refer to a signal that is active or true Negation and negate refer to a signal that is inactive or false These terms are used independent of the voltage level high or low that they represent This 25 bit bidirectional three state bus is capable of directly addressing 64M of data The address bus acts as an output when the core or general purpose DMA is accessing the chip select banks and it acts as an input when the device is in an external bus master mode In the external bus master mode the address bus is sent to the MC68322 s internal decode circuits 2 2 DATA BUS This 16 bit bidirectional three state bus is the general purpose data path It acts as an input when one of the following conditions occur When data from ROM PROM or I O is required in the form of data or instructions When an external bus master performs
246. le chip select banks The GDMA chip select transfer address appears on the output address pins of the MC68322 bus interface 25 1 It is assumed the device that is connected to the banks on the MC68322 bus used for the DMA handles any addressing issues internally For On The Product Go to www freescale com Freescale Semiconductor Uw 8 1 2 Transfer Count Fields Each DMA configuration register provides a 14 bit programmable transfer count field thus allowing for a maximum 16 Kbyte or 16 Kword transfers The transfer count is in words if the selected DMA channel is programmed to perform word sized transfers Similarly the transfer count is in bytes if the DMA channel is programmed to perform byte sized transfers Writing this register activates the DMA channel so that all other configuration register fields must be initialized before writing the transfer count field When activated the transfer count value is loaded into an internal counter and decremented after each destination transfer The transfer count field is not double buffered so writing a new value during an active transfer will not start the next DMA operation at the conclusion of the current operation However if a new value is written to the transfer count field during an active transfer the new value is ignored During an active transfer reading the transfer count field will reflect the current value of the destinat
247. led and the DRMCR refresh interval count RIC is set to a minimum value for the most frequent refresh rate Software must load the RIC field with the proper value during initialization but before it enables any DRAM bank the DRAM register for a bank must be programmed with a valid starting address For On The Product Go to www freescale com Freescale Semiconductor SECTION 8 DMA INTERFACE The MC68322 DMA interface provides support for high speed data transfers between external sources and DRAM The DMA interface contains two channels the parallel port DMA PDMA and the general purpose DMA GDMA Both of these channels are single ended and operate independently from each other with the single restriction that DRAM can only be accessed one channel at a time Each DMA channel contains control state machines a 16 bit data latch data steering multiplexers and counters for addresses and transferred data Each channel is interfaced and activated through a corresponding register Once they are activated the data steering multiplexers are configured based on direction and data width and the source controller begins requesting data When source data is available the source control state machine latches the data and signals the destination control state machine to start the destination operation Destination transfer requests begin immediately after the first source data is received DMA transfers continue until
248. lexes addresses to provide up to 8M of DRAM address space per bank The timing parameters for each DRAM bank are preprogrammed to provide a 3 4 or 5 clock access from industry standard fast page mode 5 On reset all DRAM banks are disabled Additionally the DRAM controller provides a separate 16 bit DRAM data path and a write enable signal for a glueless DRAM interface DRAM refresh cycles are carried out with CAS before RAS refresh cycles The DRAM refresh rate is fully programmable and the controller performs refreshes from system reset until it is initialized 1 2 6 DMA Interface The DMA interface contains two DMA controllers a single ended general purpose DMA GDMA and a dedicated parallel port interface DMA PDMA controller The DMA interface can be programmed to transfer data from a high speed I O peripheral to DRAM with minimal intervention from the core 1 2 7 Parallel Port Interface MC68322 contains a direct IEEE 1284 Level 2 compliant bidirectional 8 bit PPI The PPI supports four IEEE 1284 communications modes compatibility Centronics nibble byte and enhanced capabilities port ECP It also fully supports all variants of these modes including device ID requests and run length encoded data compression The PPI contains specialized hardware to provide automatic handshaking during forward data transfers When hardware handshaking is used in conjunction with the PDMA transfer rates as high as 2M sec and
249. lftone physical bit address of the starting pixel Note Denotes A Parameter That The MC68322 Updates When The Frame Crosses A Band Boundary The BLT2BB_XHD graphic order transfers a low resolution source frame to a destination banded bitmap and applies a halftone bitmap in the process Before being combined with the destination the source frame is scaled to match the resolution of the destination bitmap This results in an intermediate expanded source bitmap The pixels of the expanded source halftone and destination bit maps are combined as specified by the Boolean code set in the last SET_BOOL_SHD order The destination bitmap parameters must have been previously defined by the SET_BBMAP graphic order and the halftone bitmap dimensions by the SET_HTBMAP graphic order During the processing of halftones wrapping occurs at the edges of the bitmap This results in horizontal and vertical replication tiling of the bitmap to cover the entire destination frame area The DA parameter specifies the logical bit address of the area or transfer frame that starts in the destination banded bitmap The logical bit address is converted to a physical bit address by adding the PSUBL value in the SET_BBMAP graphic order The start of the transfer frame must be within the bounds of the banded bitmap but the end of the transfer frame may extend past the end of the bitmap DA must point to the upper left corner of the transfer frame when the B2T flag is clear
250. lly synchronizes DREQ it arbitrates for the MC68322 bus and when granted asserts DACK After DACK is asserted the internal bus interface unit BIU performs the GDMA cycle defined by the GDMA configuration register After the cycle completes DACK is negated and the DMA cycle terminates During a GDMA bus cycle CSx can be disabled This option supports external DMA devices that require CSx to be inactive during a DMA operation The DS bit in the GDMA configuration register controls the operation of CSx during a DMA generated MC68322 bus cycle MC68322 bus write cycle occurs when the channel is configured to transfer from DRAM to an external DMA device A word sized GDMA write cycle asserts the WRU and WRL signals and a byte sized GDMA write cycle asserts WRL and negates WRU Figure 8 5 illustrates the typical timing for a fast DMA read or write cycle The bus cycle timing shown is obtained using minimum values for all timing parameters For On The Product Go to www freescale com Freescale Semiconductor ww OL ed MC68322 REQUEST REQUEST BUS REQ START WAIT WAIT DATA RECOVERY lt gt i i DREQ uid aoe mi WE CS7 CS0 RD or WRU and WRL D15 D0 DATA VALID MC68322 DMA REQUEST BUS REQ MC68322 BUS CYCLE NOTES 1 This diagram illustrates DREQ programmed as an active low input DREQ is an asynchronous input and is s
251. locate the beginning of each successive scanline Note that the source warp set by the SET SBMAP graphic order has no effect on this graphic order The XOFF XMUL operand is divided into two fields The least significant four bits contain the XMUL field which specifies the factor used to scale the unexpanded source bitmap in the X dimension XMUL must equal a specific value from 0 15 which represents a scaling factor of 1 16 Only certain scaling factors are supported as defined in Table 13 3 Values other than those listed are ignored and no X scaling is performed For Mort ON oduct to www freescale com _ Freescale Semiconductor Inc supine wires The XOFF field occupies the four most significant bits and indicates the number of bits to be clipped at the left edge of the expanded source bitmap XOFF ranges from 0O XMUL If XOFF is zero no clipping occurs at the left extent but if itis non zero XOFF number of bits in the left edge of the expanded bitmap are skipped and the next bit is the first one transferred to the destination bitmap The YOFF YMUL parameter is also divided into two fields The least significant four bits contain the YMUL field which specifies the factor used to scale the unexpanded source bitmap in the Y dimension YMUL can equal any value from 0 15 which represents a scaling factor of 1 16 The YOFF field occupies the four most significant bits and indicates the number of sc
252. m edge or top edge when the B2T flag is set HXR must be the following ranges 1 x HXR x HW and 1 lt HYR HH where HW and HH are the width and height of the halftone bitmap respectively For example when the B2T flag is clear if the starting pixel in the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH if instead a 180 page is being rendered and the B2T flag is set HXR must still be set to HW but HYR must be set to one For Mort ON oduct to www freescale com _ Freescale Semiconductor Inc MAT wives W When the B2T flag is clear SLTA HTTA point to the most significant byte of the first specifier in their respective tables and DA HXR HYR and HA refer to the pixel to which the displacement of the first bit string specifier is added not necessarily the first bit of the first run When the B2T flag is set SLTA and HTTA point to the most significant byte of the last word of the final specifier in their respective tables and DA HXR HYR and HA refer to the pixel just past the end of the final bit string specifier run In neither case does SLTA point to the 0000 scanline table terminators Since both the scanline table and companion halftone table s bit string specifiers must be placed at word boundaries HTTA and SLTA must be word aligned When a band fault is detected the MC68322 re
253. maps and two control expanded bitBLTs to banded bit maps These graphic orders rely on certain parameters being previously set by initialization graphic orders Expanded bitBLT graphic orders are particularly useful in applications that regularly receive low resolution bitmap images Note that the warp of the unexpanded bitmap is included as an operand of each expanded bitBLT graphic order Expanded bitBLT graphic orders can read unexpanded bit maps that are 75 x 75 100 x 100 150 x 150 200 x 200 and 300 x 300 dpi and expand the images in both the X and Y dimensions during the transfer to match any combination of 300 600 or 1200 dpi This is accomplished by specifying two expansion factors in the graphic order one for the X dimension and one for the Y dimension An expansion factor of 1 2 3 4 6 8 12 or 16 can be specified in the X dimension and any value from 1 to 16 in the Y dimension This allows a single step expansion to printer resolutions of 300 600 and 1200 dpi The expanded bitBLT graphic orders support clipping of expanded bit maps in both the X and Y dimensions Clipping in the X dimension is controlled by two graphic order operand values XOFF and FW as illustrated in Figure 13 1 XOFF is an offset in bits from the left edge of the expanded bitmap and FW is the transfer frame width Together XOFF and FW provide bit granular control of clipping at the left and right extremes of the expanded bitmap When clipping other graphi
254. me when the B2T flag is clear and to the lower left corner of the transfer frame when B2T is set The warp of the destination banded bitmap is set by the SET_BBMAP graphic order which allows the bitmap to be packed or unpacked The SA must point to the upper left corner of the source frame when the B2T flag is clear and to the lower left corner of the source frame when the B2T flag is set When a band fault is detected the MC68322 rewrites the graphic order to update some of its parameters The BAND number is incremented or decremented when the B2T flag is set DA SA and HA are repositioned to the starting pixel of the respective frame to be processed in the next band Lastly FH and HYR are written back with the number of remaining scanlines in their respective frames to be transferred Related Graphic Orders SET BOOL SHD SET BBMAP SET HTBMAP SET SBMAP For Mort RSE ON ANA oduct Go to www freescale com Freescale Semiconductor Inc _ ET SOURCE BITMAP SW lt DESTINATION BANDED BITMAP DWB gt lt BOOL_SHD USED TO COMBINE FRAMES HALFTONE BITMAP mM Figure 13 7 Source Halftone Destination bitBLT to Banded Bitmap 0 Page 3 SOURCE BITMAP lt lt DESTINATION BANDED BITMAP BOOL_SHD USED TO COMBINE FRAMES sk lt gt HALFTONE BITMAP Figure 13 8 Source Halftone Destination bitBLT to Banded Bitmap 180
255. miconductor Inc apne SL2UB D Destination Only Scanline Transfer to Unbanded Bitmap PARAMETERS s DESCRIPTION Byte SL2F D opcode Byte Reserved Long Word Destination physical bit address 28 of 32 bits Scanline table physical byte address word aligned The SL2UB D graphic order causes the MC68322 to render a scanline table image to an unbanded bitmap The destination is manipulated as specified by the SET BOOL D graphic order The SET graphic order must previously define the destination unbanded bitmap warp SLTA points to the most significant byte of the first bit string specifier in the table not to the 0000 header and DA refers to the pixel to which the displacement of the first bit string specifier is added not necessarily the first bit of the run Since the scanline table s bit string specifiers must be placed at word boundaries SLTA must be word aligned Related Graphic Orders SET BOOL D SET UBMAP SCANLINE DESTINATION TABLE UNBANDED BITMAP SLTA lt DW PT DA oe DISPLACEMENT BITSTRING SPECIFIERS BOOL_D APPLIED i ______ Figure 13 32 Destination Scanline Transfer to Unbanded Bitmap For 12 5858 On This broduct Go to www freescale com _ Freescale Semiconductor Inc MAP wires SL2UB_HD Halftone Destination Scanline Transfer to Unbanded Bitmap PARAMETERS
256. mmed timing values are satisfied the system integration module generates an internal to the core and terminates the 68322 bus cycle Table 6 2 lists the core s synchronous access timing values for the chip selects and Figure 6 3 illustrates a synchronous read or write access Table 6 2 Synchronous Timing Values PARAMETER MIN VALUES MAX VALUE NAME CSR FIELD FORMULA CLK1 CLK1 Read Setup RSET RSET Time RSET 1 Write Setup WSET WSET Time WSET 1 Read Access RACC Time RACC 1 Write Access WACC WACC Time WACC 1 Read Hold RHLD RHLD Time RHLD 1 Write Hold WHLD WHLD Time WHLD 1 NOTE The Value WSET 0 Produces A WSET Time 2 For On The Product Go to www freescale com Freescale Semiconductor Inc RE 0 52 54 X X X X S6 INTERNAL CLK1 CSx RD or WRU and WRL 015 00 READ 1 y SET TIME ACC TIME 2 gt 3 1 gt 2 2 gt HLD TIME 11 REC 2 gt REC TIME 35 5 1 Recovery starts here no access to CSx will start until recovery is satisfied 2 Delayed 000 core access starts here 3 WATT is inactive Figure 6 3 Synchronous Read or Write Timing Diagram In asynchronous mode read and write access timings WACC and RACC must be programmed to be at least two so that WAIT will
257. mmediately stops processing the current display list and sets the RIER s RER bit When RER is set the RDR determines the graphic order that generated the error However the RGP must be reset by an RGP soft reset to return it to normal operation A write to the RGP bit in the soft reset register initiates an RGP soft reset operation See Section 5 Interrupt and Exception Handling for more information On an RGP soft reset the RGP registers are initialized as follows RSR is purged RIER s DLF and RBY bits are cleared RDR is cleared to all zeros pun ac cm Internal Boolean code registers that hold the Boolean values defined by the SET BOOL graphic orders are cleared to all zeros If the RSR is loaded between the time an RGP error is detected and the time the soft reset is issued the address stored in the RSR is lost Additionally if RDR information is needed the RDR must be read before an RGP soft reset is executed Due to the prefetching characteristics of the RGP and depending on the type of error the address returned by the RDR may be slightly beyond the source of the error When a graphic order is interrupted due to a band fault all parameters necessary to resume the data transfer at the point where the band fault occurred are written back into the display list In addition the graphic order s band number is incremented or decremented for 180 pages and written back into the display list to ensure that the graphic order is
258. mum of 13 internal accesses before it has access to DRAM For On This Product Go to www freescale com Freescale Semiconductor 7 4 5 DRAM Burst Accesses Burst accesses are carried out by using the fast page mode operation of the DRAM Fast page mode is used for all multi word burst cycles In fast page mode the cycle is carried out as described for read and write cycles except that only CAS1 and CAS2 are negated while RASx remains asserted After the defined interval defined by the memory access timing register the column address is incremented and the CAS signals reassert initiating another memory cycle The DRAM controller interface will not burst across a 256 word address page boundary If a burst access tries to cross a 256 word page the cycle will terminate and a new one will begin 7 5 POWER UP SEQUENCE Once RESET is negated the DRAM controller automatically performs DRAM refresh cycles To guarantee proper DRAM operation after a power up sequence or extended low frequency or static operation some DRAMs require an 8 cycle precharge To meet this requirement the system should set the DRAM controller to the correct values and then perform eight reads from DRAM thus disregarding the data On reset the DRAM registers and the DRMCR s TS field are set to zero Setting the TS field to zero selects the most conservative timing mode All DRAM banks are disab
259. n unexpanded source bitmap directly from memory and expands it to match the resolution of the destination bitmap Then it is combined with the destination and or halftone bitmap to complete the transfer For normal or expanded bitBLT operations if the destination bitmap is a banded bitmap the transfer terminates prematurely if the transfer frame extends below the bottom of the band This is considered a band fault The remainder of the display list is processed in the event of a band fault but the transfer operation that caused the band fault will resume when the display list is rerun to render the next band of the page image 12 6 SCANLINE TRANSFERS Scanline transfers are used to operate on nonrectangular regions of bit maps In their simplest form they are used to fill arbitrary polygons and draw vectors A scanline transfer involves operating on a specified set of scanline runs on one or more bit maps The set of scanline runs is defined by a scanline table which contains a series of bit string specifiers Each bit string specifier is a compressed run length encoding of a scanline run The compressed format of scanline tables not only saves memory but also improves performance since fewer memory fetches must be performed For On This Product Go to www freescale com Freescale Semiconductor AF Scanline operations arise quite often from two sources The first occurs from outline fon
260. n where itis being positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the upper left or lower left when the B2T flag is set corners of the source and destination frames HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the bottom edge or top edge when the B2T flag is set HXR and HYR must be in the following ranges 1 x HXR x HW and 1 x HYR x HH where HW and HH are the width and height of the halftone bitmap respectively For example when the B2T flag is clear if the starting pixel in the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH If instead a 180 page is being rendered and the B2T flag is set HXR must still be set to HW but HYR must be set to one For Mort ON oduct to www freescale com __Freescale Semiconductor MAT wires DA specifies the logical bit address of the area or transfer frame that begins the destination banded bitmap The logical bit address is converted to a physical bit address by adding the PSUBL value set by the SET_BBMAP graphic order The start of the transfer frame must be within the bounds of the banded bitmap but the end of the transfer frame may extend past the end of the bitmap DA must point to the upper left corner of the transfer fra
261. nderrun 10 7 command recieve 9 7 command sent status 10 8 data received 9 7 DMA illegal address 8 6 000 Core request 9 8 illegal address PVC 10 7 page end 10 7 page band begin 10 7 PDMA request 9 8 RGP busy 11 3 RGP error 11 4 status receive 10 8 video underrun 10 7 external 5 4 externally initiated 5 4 hardware 5 1 illegal memory address access 5 3 internal 5 1 IRQx during external interrupts 5 4 priority level external 5 4 For registers external described 5 4 software event described 5 3 software clearing 5 3 setting priority level 5 3 software 5 3 interrupts 5 1 J JUMP 13 46 L languages printer 1 8 latching 9 13 location constraints 12 15 mask register C 3 mastership assuming 4 9 MC68322 alternate pin functions D 1 applications B 1 bus arbitration 4 9 bus operation 4 1 configuration B 1 core 3 1 interface 8 1 DRAM controller 7 1 electrical and thermal characteristics 14 1 explanation 1 8 features 1 2 graphic operations 12 1 graphic orders 13 1 in circuit emulation interface A 1 interrupt and exception handling 5 1 introduction 1 1 memory mapped register summary C 1 parallel port interface 9 1 print engine interface 10 1 RISC graphics processor 11 1 signal descriptions 2 1 system integration module 6 1 MC68322 bus cycles CSx during DMA generated 8 4 DMA incrementing address 8 2 DMA read and write cycles 8 7 MC68322 reset diffe
262. nds Related Graphic Orders FOR SET BOOL D FOR SET BOOL HD FOR SET BOOL SD FOR SET BOOL SHD BLT2BB D SL2BB HD BLT2BB SD BLT2BB SHD BLT2F D SL2F HD BLT2F SD BLT2F SHD BLT2UB D SL2UB HD BLT2UB SD BLT2UB SHD SL2BB D BLT2BB XD BLT2BB XHD SL2F D BLT2F XD BLT2F XHD SL2UB D BLT2UB XD BLT2UB XHD For Mort ON oduct to www freescale com __Freescale Semiconductor supine wires weet SET_HTBMAP Set Halftone Bitmap Parameters PARAMETERS DESCRIPTION Byte SET_HTBMAP Opcode Byte Reserved Long Word Halftone bitmap total size in bits Word Halftone bitmap width in bits Word Halftone bitmap height in scanlines The SET_HTBMAP graphic order specifies the structure of a halftone bitmap This graphic order specifies the width HW height HH and total size in bits HZ of the halftone bitmap These parameters are used in all subsequent graphic orders that operate with halftones and they are dimensional only meaning that no physical base address is given in the parameters Instead each subsequent graphic order operating with the halftone defines its own physical starting address in the bitmap in addition to positional parameters Both HW and HH must be in the range 1 65 535 inclusive zero values are illegal HZ is always equal to the product of HW and HH The halftone bitmap must be packed The width of the bitmap can be any value from 1 65 535 bits A halftone bitmap narr
263. next bit is the first one transferred to the destination bitmap The YOFF YMUL parameter is also divided into two fields The least significant four bits contain the YMUL field which specifies the factor used to scale the unexpanded source bitmap in the Y dimension YMUL can equal any value from 0 15 which represents a scaling factor of 1 16 The YOFF field occupies the four most significant bits and indicates the number of scanlines to be clipped at the top edge of the expanded source bitmap YOFF ranges from 0 YMUL If YOFF is zero no clipping occurs at the top or bottom extent but if it is non zero YOFF number of scanlines at the top edge of the expanded bitmap are skipped and the next scanline is the first one transferred to the destination bitmap Halftone tiled patterns are typically anchored to the page A bitBLT may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where it is positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the upper left corners of the source and destination frames HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the bottom edge HXR and HYR must be in the following ranges 1 lt HXR x HW and 1 x HYR lt HH where HW and HH are the width and height of the halftone bitmap respectively For example if the starting pixe
264. nformation On This Product Go to www freescale com Freescale Semiconductor Apprvauuirg 070460 z 10 2 Woudaa user t g IS lt lt lt k OTN CO LO lt 8 1 9 9 vb 6 6 0 Q e Lo C lt lt lt lt lt lt lt lt N N X lt 070366 070460 070460 For More fnformation On This Product Go to www freescale com Freescale Semiconductor Inc Applications B 4 CONFIGURING THE RANDOM CONTROL LOGIC The MC68322 requires a minimal amount of external control logic but should have a reliable reset circuit to sense power up low voltage and push button resets This sample design includes a Texas Instruments device TL7705A to supply a reliable reset and Figure B 5 illustrates reset circuit usage Other devices from Freescale and Dallas Semiconductor have suitable reset circuits for MC68322 resistor capacitor reset circuit is not recommended for reliable power up and low voltage resets 5V 5V TL7705A emt m SENSE RESET RESET m RESIN RESET N C il Figure B 5 Reset Circuit Other random logic such as external latches or buffers may be required to interface with the print engine This sam
265. nformation in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the fail
266. ng applications 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0 OOFFF40C RESERVED BND memes ew OOFFF410 ER PAGE IMAGE BIT ADDRESS HIGH WORD OOFFF412 PAGE IMAGE BIT ADDRESS LOW WORD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 404 Figure 10 3 Printer Control Block Register Set The PCB s vertical and horizontal margin registers position the page image on the printed page The vertical margin value specifies the number of scanlines that are skipped before the first scanline of page image data and the horizontal margin value defines the number of internal video clocks that are skipped before the first bit is transmitted at the start of each scanline The PCB s page image height and width registers describe the limits of the page image as itis to be read from memory and transmitted to the print engine The page image height is measured in scanlines but the page image width is in bits The PCB also contains three 1 bit fields that control the execution of a print operation on a band by band basis BND Band This bit is used during banding applications to indicate when the current band image is to be followed by another band on a page It is set for all bands but cleared for the last band in a sequence or when only one band appears on a page B2T Bottom to Top This bit is set to indicate the render direction When B2T is clear it indicates a top to bottom and left to right direction When set it indicates a bottom to top
267. ng edge or both edges of its clock This is controlled by the PVCCR s PLE bit If the PLL clocks on the rising edge it divides its input clock by eight to produce a dot clock This dot clock will have no more than 1 5 dot jitter If the PLL clocks on both edges it divides its input clock by four to produce a dot clock When PLD 00 or 10 and PLE 01 the dot clock has no more than dot jitter When the duty cycle of the is less than 50 the amount of jitter will increase when using both clock edges The duty cycle does not adversely affect the jitter of the dot clock when using the rising edge only mode PLD and PLE have an effect only when the PVCCR s VCS bit selects the PLL clock After changing the PLD or PLE bits a PVC soft reset must be posted The PLD and PLE bits should only be changed between pages when the video state machine is inactive Table 10 2 lists all values of PLD PLE and the resulting dot clock Table 10 2 PLL Video Clock Divisor PLD PLE PRESCALE CLOCK ENCODING ENCODING VALUE CLOCK EDGE DOT CLOCK JITTER Rising VCLK Dot Both VCLK Dot Rising VCLK 16 Dot 1 Both 8 I Dot 2 0 3 Rising VCLK 24 Dot 1 12 I Dot 3 0 4 Rising VCLK 32 Dot 1 16 ls Dot NOTE ClockJitter When PLLDIV 0 And PLL EDGE 1 Is Dependent On VCLK Input Clock Symmetry In some cases there are multiple configurations that produce the same effective do
268. ns B 6 CONFIGURING THE IN CIRCUIT EMULATION The MC68322 provides an ICE option which is included here The ICE connection is a simple pin grid array to an ICE board available from Freescale The ICE option can be implemented in the prototype stages of designing a printing system and can remain available through production as a method of testing debugging and field service See Appendix A In Circuit Emulation Interface for ICE board specifications To provide an ICE option the HI Z signal should be connected to a pull up resistor and not directly to Vec The ICE PGA pattern should be placed on the PCB and typically the MC68322 can be placed inside the cut out section of the PGA All signals from the MC68322 160 pin quad flat pack QFP must be connected to the ICE PGA connector The special version of the MC68322 along with the ICE board allow a standard MC68000 DIP format emulator to be used This type of interface allows existing emulators to be reused with virtually no additional investment Figure B 8 illustrates the MC68322 ICE interface 1 68322 PGA 23x23 1 68322 PGA 23x23 135 1 133 CLK2 13 22 132 _ MA RESET 128 4 EDTACK 131 q 159 _ TEST 11 5 130 SET CSO AG 128 _ MA5 0 5 51 AT 127 M 25 o CS2 A8 2 MAT BR d OF CS3 AQ 125 AS 19 4 OF CS4 A10 124 _ R W 20 OF 55 11 122 MA10 0 5 CS6 A12 TNT
269. nterface controller 9 1 For information On This Product Go to www freescale com Freescale Semiconductor mavan BLT2BB_D 13 9 BLT2BB_SD 13 11 BLT2BB_SHD 13 13 BLT2BB_XD 13 17 BLT2BB_XHD 13 22 BLT2F_D 13 27 BLT2F_SD 13 28 BLT2F_SHD 13 29 BLT2F_XD 13 31 BLT2F_XHD 13 33 BLT2UB_D 13 36 BLT2UB_SD 13 37 BLT2UB_SHD 13 38 BLT2UB_XD 13 40 BLT2UB_XHD 13 43 Boolean code calculating example 12 4 specifying a graphic operatin transfer 12 3 Boolean codes 12 3 Boolean logic unit 11 1 bottom to top 2 definition 13 6 BR asserting 4 10 burst accesses DRAM 7 10 burst cycles DRAM access 7 1 bus 4 1 address 2 3 data 2 3 bus arbitration DRAM 7 9 signals asserting 4 9 bus arbitration 4 9 bus cycle exception 5 13 bus cycles DRAM read cycles 7 7 DRAM write cycles 7 8 bus interface unit GDMA read cycles performing 8 7 bus mastership exchanging 4 9 bus operation core read cycle 4 1 core write cycle 4 4 external bus master 4 9 interrupt acknowledge bus cycle 4 6 reset 4 8 bus operation 4 1 BUZZER ENB D 3 BUZZER INT D 3 byte address defined 13 5 byte operation 4 1 4 4 For ME RS CCLK supplied 68322 10 11 10 13 CCLK supplied by print engine 10 12 10 14 channel address command received interrupt 9 7 chip select recovery value 6 4 chip select DMA timing register 6 3 chip selects active read and write times 6 2 banks DMA access timing 8 8
270. nterface uses the CBSY and SBSY pins to indicate the direction of data transfer and it uses the CCLK pin to pace data transmissions It does not employ handshaking but it asserts the CBSY and SBSY pins before the actual data transmission so there is sufficient time for the logic to prepare for the subsequent data CCLK remains inactive until either the CBSY or SBSY pin is asserted and then goes through eight periods one per data bit During a command transfer to the print engine the MC68322 shifts a bit on each CCLK falling edge and expects the print engine to sample the datastream on each rising edge Similarly for a status transfer from the print engine the MC68322 samples the datastream on each rising edge and expects the print engine to shift a bit on each falling edge For On This Product Go to www freescale com Freescale Semiconductor QI 10 3 PRINT ENGINE INTERFACE OPERATION Page images are generally rendered by the RISC graphics processor RGP into an area of memory known as the band buffer After a page image is rendered the PVC is programmed to transmit the contents of the band buffer to the print engine The PVC starts by loading the PCB register set with the dimension and location of the page image Once the page image bit address register is written the memory subsystem sets the PVCCR s PFL and BSY bits and begins to fetch data from memory to fill its FIFO After the v
271. nterrupt AVEC is negated when AS goes inactive The internal IPL2 IPLO signals remain asserted until the core clears the interrupt event by clearing the appropriate bit in the module s interrupt event register The IPLx signals can however change from one level to another before they are serviced if a different level interrupt is generated As part of the interrupt handling routine the interrupt sources of that level should be cleared Figure 4 8 illustrates the internal interrupt acknowledge timing diagram and Figure 4 9 illustrates the interrupt acknowledge cycle timing diagram For On The Product Go to www freescale com Freescale Semiconductor eee 2 NOTE These signals are internal signals only Figure 4 8 Internal Interrupt Acknowledge Cycle 50 52 54 56 57 52 54 56 50 52 W 55 56 c 1 005 and LDS w LAST BUS CYCLE OF INSTRUCTION AUTO STACK AND I READ OR WRITE gt lt __ vector cycle gt VECTOR FETCH NOTE AO UDS LDS AVEC and DTACK are internal signals only Figure 4 9 Interrupt Acknowledge Cycle Timing Diagram For More information On This Product Go to www freescale com Freescale Semiconductor WS deamon 4 4 RESET OPERATION RESET is externally asse
272. odule DRAM system integration module DMA controller and parallel port interface Figure 1 1 illustrates the MC68322 block diagram PARALLEL PORT IEEE 1284 GRAPHICS UNIT PARALLEL PORT EC000 CORE SYSTEM INTEGRATION es BUS GRAPHICS BUS MODULE SIM INTERFACE UNIT EC000 BUS RISC GRAPHICS PROCESSOR RGP PRINT ENGINE VIDEO CONTROLLER PVC DRAM CONTROL IN CIRCUIT EMULATION OPTIONAL PERIPHERAL OPTIONAL PRINT ENGINE Figure 1 1 MC68322 Block Diagram 1 2 1 The 000 Core The MC68322 contains a static low power 16 bit microprocessor 000 core which performs general purpose computing and exception handling and display list rendering The core has a 16 bit data path that is upward compatible with 32 bit machines It also has a 32 bit internal architecture with internal 32 bit data and address registers and an extended address range The address range is 28 bits for internal register decoding of chip selects and DRAM controller functions This address range allows for full code compatibility with existing M68000 Family based designs and future upward compatibility to higher performance designs The core is register and memory map compatible with the industry standard MC68000 MC68bECO000 and MC68HCO000 processors The MC68322 is designed to support in circuit emulation with existing emulators so that new hardware and softwar
273. odules 2 d lIs Direction L For On The Product Go to www freescale com Freescale Semiconductor SECTION 4 BUS OPERATION The MC68322 bus consists of the address data buses 25 0 and D15 D0 respectively These are separate parallel buses that transfer data using an asynchronous protocol The graphics bus consists of the MC68322 s DRAM address and data buses 10 and MD15 MDO respectively which are separate parallel buses on which data is transferred to and from DRAM using an asynchronous protocol This section describes control signals and bus operation during data transfers on the MC68322 bus and graphics bus It also describes arbitration of the bus and external bus mastership Except during external bus mastership the 000 core directs the MC68322 bus graphics bus using the following the CSx RD WRU WRL R W RAS5 RASO CAS1 CASO 10 and WE control signals to transfer data These control signals indicate the bus cycle beginning and type as well as the address space and size of the transfer They control all transfers to and from the core including Internal registers read or write ROM read DRAM read or write read or write 4 1 EC000 CORE READ CYCLE During a read cycle the core receives data from memory DRAM EPROM an internal register or a peripheral device reading either one or two bytes of data in
274. of a band fault The graphic order execution unit is a collection of state machines that control all aspects of the graphic operations including calculation of effective addresses rectangular pixel array widths in words barrel shifter rotation offsets left right mask values and halftone positioning The band registers hold the graphic order operands and values that are required for internal use The arithmetic logic unit performs all internal calculations including addition subtraction increment by one decrement by one and comparison It is also used to calculate and modify effective addresses for source destination and halftone bit maps The pixel data files along with internal barrel shifters hold source halftone and destination data and it constantly adjusts so that all the data is uniformly aligned These data files operate independently from the remainder of the RGP requesting new data at the same time existing data is processed through the barrel shifters or Boolean logic unit for subsequent writing to memory The Boolean logic unit carries out all combinations of 1 2 and 3 operand Boolean operations combining source halftone and destination data together in one of 256 possible combinations Left and right masking is used to preserve the original destination data at the left and right edges of the destination bitmap For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor Inc
275. oint during the DMA transfer an address supplied by the DMA to the DRAM or MC68322 bus interfaces is incorrect not mapped to a valid bank an address fault occurs The DMA transfer terminates the ILA bit in the channel s interrupt event register is set and an interrupt is posted to the core if enabled As a result of this bad address error the DMA channel will park in an error condition The DMA channel must then be reset using one of soft reset registers DMA bits before a new operation can be initiated A write to either the GDR or PDR bits in the soft reset register will initiate a DMA soft reset operation See Section 5 Interrupt and Exception Handling for more information During the reset condition only the DMA channel control logic is affected Initial register values are not cleared 8 7 3 Core Forced Termination If during DMA transfer the core sets the FR bit in the channel s configuration register the DMA controller will terminate any ongoing transfer for that channel If the DMA channel is receiving data from the MC68322 bus or the PPI any data remaining in the internal data latch is written to DRAM If the DMA channel is sending data to the MC68322 bus any data remaining in the data latch is discarded When the data transfers are complete the channel shuts down sets the CMP bit in the channel s interrupt event register and returns to the idle state Depending on the value remaining in the transfer counters it is possible to se
276. ols for the external bus memories and I O devices no operation NOP An instruction whose sole function is to increment the Program Counter but which affects no changes to any registers or memory pace control Controls the rate of the data flow between the master and slave The burst mechanisms allow this to be controlled by the slave and is useful in slowing down the data transfer rate Slave delay can be used in place of pace control It means the data pace can be slowed down by the slave pipeline The act of initiating a bus cycle while another bus cycle is in progress Thus the bus can have multiple bus cycles pending at a time scan chain The peripheral buffers of a device linked in JTAG test mode that are addressed in a shift register fashion scoreboard A register tracking system that ensures that values are not pulled from a register before they are updated by a previous instruction sequential instruction Any instruction that is not a flow control instruction and not ISYNC For The Product Go to www freescale com Freescale Semiconductor Glossary slave A device that responds to the master s address A slave receives data on a write cycle and gives data to the master on a read cycle snoop The act of monitoring external bus activity by alternate bus masters By snooping these external accesses a CPU can identify accesses to memory locations that contain dirty data and possi
277. om Freescale Semiconductor Introduction 01000000 OOFFFFFF INTERNAL REGISTERS 00 000 OOFFEFFF ROM AND I O BANKS 0 7 DRAM BANKS 0 5 00000000 Figure 1 3 16M Memory Map After power up the MC68322 can be configured for the full 256M address space and the registers can be moved to start at a higher address The MC68322 memory map for a 256M memory space is illustrated in Figure 1 4 FFFFFFFF 10000000 OFFFFFFF INTERNAL REGISTERS ROM AND I O BANKS 0 7 DRAM BANKS 0 5 00000000 Figure 1 4 256M Memory Map The memory map address register contains bits 27 24 of the register set s base address and is illustrated in Figure 1 5 This register is used to relocate the memory mapped registers within the memory map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 1 5 Memory Map Address Register DRAM ROM or I O can be programmed individually to reside anywhere in the memory map The address space for registers ROM or I O chip selects and DRAM can overlap In case of an address overlap registers have the highest priority then chip selects and finally the DRAM Only the device with the highest priority responds to the access MC68322 USER S MANUAL 1 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction 1 4 UNDERSTANDING THE MC68322 Familiarity with some of the basic printer operation
278. on is false and else is omitted the else operations instruction performs no operation Refer to the Bcc instruction description as an example For On This Product Go to www freescale com Freescale Semiconductor Inc The Core Table 3 3 Notational Conventions Continued C DATA FORMAT AND TYPE lt fmt gt Operand Data Format Byte B Word W Long L SUBFIELDS AND QUALIFIERS lt xxx gt or lt data gt Immediate data following the instruction word s SINGLE AND DOUBLE OPERAND OPERATIONS Identifies an indirect address in a register Identifies an indirect address in memory Displacement Value n Bits Wide example d 5 16 bit displacement REGISTER NAMES Condition Code Register lower byte of status register Program Counter Status Register 22221222000 REGISTER CODES Carry Bit in CCR Condition Codes from CCR Negative Bit in CCR Undefined Reserved for Freescale Use Overflow Bit in CCR Extend Bit in CCR Zero Bitin CCR STACK POINTERS Active Stack Pointer SSP Supervisor Master or Interrupt Stack Pointer User Stack Pointer For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor Table 3 4 Instruction Set Summary OPCODE OPERATION SYNTAX ABCD Source 10 Destination 10 X Destination ABCD Dy Dx ABCD Ay
279. on is when the stack pointer is pointing at an odd address 5 4 2 Multiple Exceptions When multiple exceptions occur simultaneously they are processed according to a fixed priority Table 5 4 lists the exceptions grouped by characteristics with group 0 having the highest priority Within group 0 reset has the highest priority followed by an address error Within group 1 trace has priority over external interrupts which takes priority over illegal instruction and privilege violation Since only one instruction can be executed at a time no priority relationship applies within group 2 Table 5 4 Exception Grouping and Priority GROUP EXCEPTION PROCESSING ope m Reset and Address Error Exception Processing Begins Within Two Clock Cycles Trace Interrupt Illegal and Privilege Exception Processing Begins Before The Next Instruction trap trapv chk and div Exception Processing Is Started By Normal Instruction Execution The priority relationship between two exceptions determines which one is taken or taken first if the conditions for both arise simultaneously In another example if an interrupt event occurs during the execution of an instruction while the T bit in the internal status register is asserted the trace exception has priority and is processed first However before instruction execution resumes the interrupt exception is processed As a general rule the lower the priority of an exception the sooner the handler ro
280. or supine Table 12 2 Bit String Specifier Field Definitions BITSTRING TYPE FIELD DEFINITION 0 to 63 pixels DX 127 to 128 pixels 32 bit DY Zero to three scanlines 0 to 4 095 pixels 8 191 to 8 192 pixels 48 bit RL 0 to 16 383 pixels DZ 536 870 991 to 536 870 992 pixels A 16 bit null termination bit string specifier of 0000 1 placed before the beginning and after the end of every scanline table This is a real specifier that specifies no movement of the base pointer and a run of zero pixels Note that the null terminators can be shared between scanline tables placed adjacent in memory In other words the ending point 0000 of one scanline table serves as the starting point 0000 for the next scanline table The dual termination of the scanline tables is required for duplex banding applications where the MC68322 reads the scanline table in both forward and reverse directions to render 0 and 180 pages 12 6 2 Scanline Run Operation When a scanline graphic order begins the current destination address is established by the initial address specified in the graphic order The MC68322 maintains a current destination address value and updates it after each bit string specifier is executed For 0 pages after a scanline run occurs the current destination address points to the pixel immediately following the last pixel in the run For 180 pages the current destination address points where t
281. or Mon zi MANUS Product Go to www freescale com Freescale Semiconductor LIST OF ILLUSTRATIONS Continued Figure Page Number Title Number 6 1 Chip Select Register 0 0 0000 6 1 6 2 Chip Select DMA Timing and Recovery Registers 6 3 6 3 Synchronous Read or Write Timing Diagram 6 5 6 4 Asynchronous Read or Write Timing Diagram 6 6 6 5 Special Asynchronous Read or Write Timing Diagram 6 6 7 1 DRAM Register 5 7 1 7 2 DRAM Timing Mode 1 Read Cycle ROM Mode 0 7 3 7 3 DRAM Timing Mode 1 Read Cycle ROM Mode 1 7 3 7 4 Address Demultiplexing Example 7 4 1 5 DRAM Control Register ee pb ER a qid a o ecu dq 7 5 6 DRAM Refresh Cycle eene guion fts Cs 7 6 7 7 DRAM Timing Mode 0 Read Cycle ROM Mode 0 7 7 7 8 DRAM Timing Mode 1 Read Cycle ROM Mode 0 7 7 7 9 DRAM Timing Mode 2 Read Cycle ROM Mode 0 7 8 7 10 DRAM Timing Mode 0 Write 0 7 8 7 11 DR
282. ord or data zero For example 1 2 3 for a sequence of four data with data 1 as the critical data datastream A sequence of information to be processed by the CPU early termination Some burst protocols specify the burst length at the beginning of the transfer Early termination allows the burst to be terminated before all data beats are transferred exception An error unusual condition or external signal that can set a status bit It may or may not cause an interrupt depending on whether or not the corresponding interrupt is enabled For On This Product Go to www freescale com Freescale Semiconductor ANZ ADU y execution serialization Instruction issue is halted until all instructions that are currently in progress complete execution all internal pipeline stages and instruction buffers have emptied and all outstanding memory transactions are completed execution stream The combination of instructions and data on which the CPU operates fetch serialization Instruction fetch is halted until all instructions currently in the processor have completed execution all issued instructions as well as the prefetched instructions waiting to be issued The machine after fetch serialization is said to be completely synchronized fixed transaction A bus transaction that combines the address and data phase of the bus cycle into a single event flow control instruction One of B BR BCR BCC RFI SC an
283. ost process the video data use the 1X clock mode 10 5 2 VCLK Rising Edge PVCCR Bit 1 11 If VCP 0 the specifications shown above are relative to the falling edge of VCLK 10 5 3 Border Polarity High PVCCR Bit 5 0 This bit controls the state of the video out signal in the margin area of the page If this bit is set the video signal is driven low when the video data is not being driven out of the part For On The Product Go to www freescale com Freescale Semiconductor SECTION 11 RISC GRAPHICS PROCESSOR The RISC graphics processor RGP is one of the two components of the graphics unit the other being the print engine interface The RGP executes a display list of graphic orders a special list of instructions to render a page image This section describes the following RGP functional blocks and how they operate Graphic order parser Graphic order execution unit Band registers Arithmetic logic unit Pixel data files Boolean logic unit The graphic order parser is responsible for reading the display list and determining opcode type and if a banded opcode the appropriate band to process the graphic order It is also responsible for aligning and transferring the operands into the band registers interpreting aligning and transferring scanline table bit string specifiers into the band registers as well as writing back any modified operands in the event
284. osts a page end interrupt event and returns to idle If the BND bit was set in the PCB s band control register the controller returns instead to end of band idle and waits for another page address to load before resuming execution A state diagram for the video interface controller machine is illustrated in Figure 10 6 For On The Product Go to www freescale com Freescale Semiconductor IQ ISTART PW 0 amp PH 0 IFSYNC amp IBAND ISTART LSYNC amp VM 0 LSYNC amp VM 0 amp gt 0 HM gt 0 PRINT VERTICAL MARGIN ILSYNC NOTES FSYNC FSYNC Asserted HM Horizontal Margin Register Value LSYNC Leading Edge of LSYNC Detected PH Page Image Height Register Value PM Page Image Width Register Value START Load of Page Image Bit Address Register VM Vertical Margin Register Value Figure 10 6 PVC Video Interface State Diagram 10 3 1 Synchronous Asynchronous PVC Operation The PVC interfaces with print engines that provide either an asynchronous or synchronous interface A print engine interface is considered synchronous if it supplies a video clock and a synchronous control signal If a print engine supplies no clock the interface is considered asynchronous The PVC is programmed for synchronous operation by clearing the PVCCR s VCS bit This causes the PVC to use VCLK as a 1x clock source to clock video data The VCLK period de
285. ow PDE to be set or remain set If the ABT bit is set and SELECTIN goes low PDE is cleared and setting PDE will have no effect ERC Error Cycle The ERC bit is used to execute an error cycle when in compatibility mode MODE 01 When set ERC sets the 5 1 bit in the PPIR which immediately causes the MC68322 to drive BUSY high If ERC is set when a compatibility mode handshake sequence is in progress BSY1 remains set beyond the end of the cycle The ERC bit does not affect an ACK pulse that is already active but does prevent an ACK pulse if it is about to be generated While ERC is set the software can set or clear the PPIR s SEL PER and FLT bits When ERC is cleared the PPI generates an ACK pulse and negates BUSY to automatically conclude the error cycle When the MODE bit is set to any value except 01 setting ERC has no effect Setting MODE 01 when ERC is already set causes the handshake controller to immediately begin an error cycle as described above MODE This 2 bit field selects and enables a hardware handshaking mode for forward data transfers The following paragraphs describe the functions for encoding the MODE field 00 Disable all hardware handshaking so that handshaking can be performed by the software 01 Enable compatibility mode hardware handshaking during forward data transfers In this mode the PPI responds to a high to low transition on STROBE and automatically sets and clears the BSY 1 and 1
286. ower than 32 bits should be replicated to at least 32 bits to minimize the cost of replicating the halftone pattern across wide areas This type of replication is not necessary in the Y dimension The MC68322 contains specialized caching hardware to achieve the greatest performance with 32 and 64 bit wide word aligned halftones Related Graphic Orders BLT2BB SHD BLT2F SHD BLT2UB SHD BLT2BB XHD BLT2F XHD BLT2UB XHD SL2BB HD SL2F HD SL2UB HD HALFTONE BITMAP HZ HW x HH HH gt HW Figure 13 24 Halftone Bitmap Parameters For Mort forsrination On This Product Go to www freescale com Freescale Semiconductor iip m vwiuvis dL SET_SBMAP Set Source Bitmap Parameters PARAMETERS DESCRIPTION Ox0A Byte SET_SBMAP Opcode 0x00 Byte Reserved SW Word Source bitmap warp in bits The SET SBMAP graphic order specifies the structure of a source bitmap The warp of the bitmap is provided and if non zero is used in all subsequent bitBLT graphic orders that specify a source bitmap If the source bitmap warp is set to zero the width of the destination frame specified by a subsequent bitBLT graphic order is assumed to be the warp of the source bitmap This feature is particularly useful when a series of bitBLT operations are performed from a font or collection of source frames where each frame has a different width By setting the source warp to zero the SET SBMAP graphic order does not need to be
287. p in the X dimension XMUL must equal a specific value from 0 15 which represents a scaling factor of 1 16 Only certain scaling factors are supported as defined in Table 13 3 Values other than those listed are ignored and no X scaling is performed The XOFF field occupies the four most significant bits and indicates the number of bits to be clipped at the left edge of the expanded source bitmap XOFF ranges from 0 XMUL If XOFF is zero no clipping occurs at the left extent but if itis non zero XOFF number of bits in the left edge of the expanded bitmap are skipped and the next bit is the first one transferred to the destination bitmap The YOFF YMUL parameter is also divided into two fields The least significant four bits contain the YMUL field which specifies the factor used to scale the unexpanded source bitmap in the Y dimension YMUL can equal any value from 0 15 which represents a scaling factor of 1 16 The YOFF field occupies the four most significant bits and indicates the number of scanlines to be clipped at the top edge of the expanded source bitmap YOFF ranges from 0 YMUL If YOFF is zero no clipping occurs at the top or bottom extent but if itis non zero YOFF number of scanlines at the top edge of the expanded bitmap are skipped and the next scanline is the first one transferred to the destination bitmap Related Graphic Orders SET BOOL SD SET UBMAP UNEXPANDED SOURCE BITMAP SW EXPANDED DESTINATION UNBA
288. p warp The DA parameter must always point to the upper left corner of the frame Related Graphic Orders SET BOOL D SET UBMAP DESTINATION UNBANDED BITMAP BOOL D APPLIED TO FRAME Figure 13 18 Destination bitBLT to Unbanded Bitmap For Mort 12 5858 On This Product Go to www freescale com Freescale Semiconductor Inc vwiuvis Jin BLT2UB SD Source Destination bitBLT to Unbanded Bitmap PARAMETERS DESCRIPTION Byte BLT2UB_SD Opcode Byte Reserved Long Word Destination physical bit address Word Frame width in bits Word Frame height in scanlines LongWord Source physical bit address The BLT2UB_SD graphic order causes the MC68322 to bitBLT a source frame to a destination unbanded bitmap The source and destination pixels are combined as specified by the current value in the BOOL_SD Boolean code register The SET_UBMAP graphic order must previously define the destination bitmap warp source frame warp is assumed to be the FW specified in the BLT2UB_SD graphic order unless a non zero source bitmap warp was previously defined by the SET_SBMAP graphic order in which case the latter is used The DA and SA parameters must point to the upper left corners of their respective frames Related Graphic Orders SET_BOOL_SD SET_SBMAP SET_UBMAP SOURCE BITMAP DESTINATION UNBANDED BITMAP DWU BOOL_SD USED TO COMBINE FRAMES Figure 13 19 Source Destin
289. physical byte address word aligned 28 of 32 bits Scanline table physical byte address word aligned Note Denotes A Parameter That The MC68322 Updates When The Frame Crosses A Band Boundary The SL2BB HD graphic order causes the MC68322 to render a scanline table image to a banded bitmap and apply a halftone bitmap in the process The destination and halftone pixels are combined as specified by the Boolean code last set by the SET BOOL HD graphic order The SET BBMAP graphic order must previously define the destination banded bitmap parameters and the SET HTBMAP graphic order must do the same for the halftone bitmap dimensions Halftone tiled patterns are typically anchored to the page The rendering of a scanline table may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where it is positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the initial destination address given in the graphic order Remember that the initial destination address is not where the first pixel is drawn when the B2T flag is clear it is the point to which the first bit string specifier s displacement is added and when the B2T flag is set the point immediately to the right of the last bit string specifier s run HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the botto
290. ple design has two latches to interface with the front panel and serial EEPROM Two buffers are used to filter and clean up the incoming signals from the print engine Figure B 6 illustrates the front panel buffers and latches For On The Product Go to www freescale com Freescale Semiconductor CONTROLLER REGISTERS CONTROLLER STATUS REGISTERS 74ALS259 ODD BYTES 74ALS541 0078000F 0078000D 0078000B PRFD 00780009 FP RST 00780007 FP LED9 00780005 FP LEDWR 00780003 FP VFDCS 00780001 CS6 WL 73 1 TAALS32 74ALS259 EVEN BYTES 0078000E 0078000C CPRDY 0078000A FP BUZZEN 00780008 FP sWRD 00780006 00780004 Pwrp 00780002 EP PCLK 00780000 EE_CK TAALS32 CS6 WRU RESET Figure B 6 Front Panel Buffers and Latches B 5 CONFIGURING THE SERIAL EEPROM Often a serial EEPROM is used to store field programmable or default information such as page count printer name Ethernet address and resolution This interface uses four signals from the random logic interface The serial interface utilizes the latches and buffers that are shared with the front panel interface Figure B 7 illustrates the serial EEPROM connection PIN 8 5 PIN 5 GND Figure B 7 4 Kbit Serial EEPROM Connection For On This Product Go to www freescale com Freescale Semiconductor Inc Applicatio
291. ppear in each section The easiest way to start using this manual is to use the index to find the topic you re interested in SUPPLEMENTAL DOCUMENTATION There are two manuals available from Freescale that will enable you to have a more well rounded reference source for the MC68322 To order them see the back cover of this manual for the Freescale Literature Distribution Center contact information or click here to go to the LDC website The M68000 Family Programmer s Reference Manual M68000PM AD provides instructions and detailed information on the 000 core and other devices The MC68322 Integrated Printer Processor Product Brief MC68322P D provides a brief description of the MC68322 s capabilities GIVE US YOUR OPINION We are constantly trying to make our documentation easier to access and use so please give us your feedback You can either print out and send us the form on the following page or fill out the survey on the web at http www mot com SPS ADC site docs survey html You can also visit the Freescale Imaging and Storage Division website at http Awww mot com isd for information about applications errata and other products This manual 15 also available in PDF format at that site MC68322 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor FREESCALE IMAGING AND STORAGE DIVISION CUSTOMER DOCUMENTATION SURVEY Fill out this form and fax it to the ISD
292. q RU pi qe Rete 12 9 12 6 32 Bit Halftone Specifier 12 10 12 7 48 Bit Halftone Specifier Format 12 11 12 8 Scanline and Halftone Table Example 12 13 13 1 Controlling Left and Right Clipping of Expanded Bit Maps 13 4 13 2 Halftone Specification for bitBLT Operations 13 7 13 3 Destination bitBLT to Banded 0 Page 13 10 13 4 Destination bitBLT to Banded Bitmap 180 Page 13 10 13 5 Source Destination bitBLT to Banded Bitmap 0 Page 13 12 13 6 Source Destination bitBLT to Banded Bitmap 180 Page 13 12 13 7 Source Halftone Destination bitBLT to Banded 0 Page 13 15 13 8 Source Halftone Destination bitBLT to Banded Bitmap 180 13 15 13 9 Expanded Source Destination bitBLT To Banded Bitmap 0 Page 13 18 13 10 Expanded Source Destination bitBLT To Banded Bitmap 180 Page 13 18 13 11 Expanded Source Halftone Destination bitBLT To Banded Bitmap OF Mc Eccc 13 22 13 12 Expanded Source Halftone Destination bitBLT Banded Bitmap 190 Pagea ir eique e tta prae oh Pbi d Pu SU RED laa 13 22 1
293. r the status register nor any of the internal registers are affected by a reset instruction execution Also the RESET signal will not assert during the execution of a reset instruction However using the reset instruction on the MC68322 is not recommended For On The Product Go to www freescale com Freescale Semiconductor TP en 4 5 EXTERNAL BUS MASTER The design of the MC68322 bus allows only one bus master at a given time The core can be disabled as the bus master so that DMA or an external device can have full access to MC68322 resources This provides a significant improvement in performance and takes full advantage of the high integration in the MC68322 The design also provides the external bus master with access to DRAM chip selects or register memory resources in the lower 64M of memory However the external bus master cannot access memory above this 64M boundary A handshake between the MC68322 and the external bus master achieves the exchange of bus mastership When the MC68322 is in external bus master mode the external bus master drives many of the signals into the MC68322 The external bus master is limited in that it is unable to detect generated interrupts can perform only word sized operations and cannot perform read modify write cycles 4 5 1 MC68322 Bus Arbitration Bus arbitration is the protocol by which an external device or DMA becomes the MC68322 bus master The bus interface
294. ragraph Page Number Title Number Appendix B Applications B 1 Configuring The 68322 t dde eae uidet e sede dus B 1 B 2 Configuring The DRAM and DRAM SIMM B 2 B 3 Configuring The Flash EPROM getreten enano B 4 B 4 Configuring The Random Control B 7 B 5 Configuring The Serial EEPROM ctt oett toe B 8 B 6 Configuring The In Circuit Emulation 2000012 B 9 B 7 Configuring The Parallel Port B 10 B 8 Configuring The Generic Print Engine Interface B 11 B 9 MC68322 Memory Initialization Example B 12 B 10 MC68322 Internal Registers Sample Code B 13 Appendix C Memory Mapped Register Summary C 1 MC68322 Mask Register C 3 C 2 Test Register C 3 Appendix D Alternate Pin Functions D 1 o EE D 1 D 2 State D ring Reset D 2 D 3 ede a D 2 D 4 APUI Pim MOGG 0 3 0 5 m tesa D 3 D 6 1 D 3 D 7 Operation EXample s s sd 0 4 Appendix Glossary Index
295. railing edge of RESET Figure 2 2 illustrates the internal timing of the MC68322 in which RESET is doubly synchronized and the trailing edge is used to synchronize CLK1 CLK1 SYNCED Figure 2 2 CLK1 Phase Relationship For On This Product Go to www freescale com Freescale Semiconductor wvoviip uvg CLK1 can be generated with external logic as illustrated in the following equations This logic runs off CLK2 takes system reset in as RESETIN and generates CLK1 and RESET as outputs rstix RESETINx Sync reset input internal use Reset to 68322 rst2x RESETx Delayed reset internal use CLK1 Toggle RESETx amp rst2x Sync at trailing edge of RESET Where Inverted Logical AND Logical OR Registered Output Combination Non Registered Output Line Termination Comment XE Qo This external logic works a similar manner as the logic used inside the 68322 external CLK1 runs continuously even during reset and only its phase is adjusted based on the trailing edge of the RESETIN input The asynchronous RESETIN input is synchronized to avoid metastability problems and a synchronous RESET output signal is produced to reset the MC68322 and ensure that it generates its internal CLK1 in phase with its external CLK1 2 3 3 H
296. rences during 10 16 mechanicals 15 1 Product Go to www freescale com Freescale Semiconductor memory addresses 3 3 memory data bus DRAM write cycles 7 8 memory mapped registers C 1 modes of operation exception processing described 5 6 module soft reset register MSRR described 5 14 module soft reset register 5 14 MSRR 5 14 multiple exceptions 5 13 N nibble mode 7 1 notational conventions 3 4 O operands types of graphic order 12 2 operation bus 4 1 ordering information 15 1 buffer reuse 10 7 height of image 10 5 image dimension and location 10 9 height values counted down 10 9 width values counted down 10 9 width 10 5 page boundary DRAM burst access 7 10 parallel interface port signals 2 9 parallel port control signals 9 8 digital filtering operation 9 11 error cycles see error cycles hardware handshaking see handshaking parallel port interface block diagram 9 1 data latching operation 9 13 data transfer rate 9 14 digital filtering 9 11 error cycles 9 12 hardware handshaking disabling 9 10 ECP 9 8 hardware handshaking 9 7 interrupt events 9 6 PDMA 9 8 PDMA see also DMA For Mol oderat ion miava registers 9 2 RESET 9 14 software controlled handshaking 9 11 parallel port interface 9 1 PCB 10 5 PCIER 10 8 PCL 1 8 PCOMR 10 2 PDL 1 8 parallel port DMA see DMA PDMA 8 2 performance improving 4 9 phase 10
297. ress or run length count depends on which ECP handshaking mode is selected For On This Product Go to www freescale com Freescale Semiconductor Vit If ECP without RLE is enabled 10 a channel address and run length count always generates command received interrupt event The does not perform decompression BUSY remains low until the PPIR s DATA field is read by the core No data received interrupt event is posted and request is generated for the command byte If ECP with RLE is enabled MODE 11 and a channel address is received a command received interrupt event is posted BUSY remains low until the PPIR s DATA field is read by the core If the detects a run length count RLE decompression will occur on the next data byte that is received No command or data received interrupt events are posted and no PDMA request is generated for the run length command byte 9 2 2 2 RLE DECOMPRESSION When ECP with RLE handshaking is enabled run length counts are detected and automatically loaded into an internal counter The PPI then sets the PPCR s RLD bit A run length count of zero is interpreted as a replication factor of one and a run length count of 127 is interpreted as a factor of 128 BUSY is driven high when the run length value is loaded into the counter and lowered when STROBE returns high The PPI then waits for the next data b
298. reted as physical addresses and the MC68322 uses them to access memory directly In the case of banded bit maps where only a portion of the physical page s image may be present in memory address parameters are interpreted as logical addresses The MC68322 must translate logical addresses to physical space before graphic order execution begins Translation information is provided to the MC68322 at the same time the banded bitmap dimensions are defined the SET BBMAP order Physical addresses are translated back to logical addresses when a band fault occurs so an updated logical address parameter can be written back to the graphic order 13 3 2 Duplex Addresses Based on the value of the bottom to top B2T parameter in the SET BBMAP graphic order bitBLTs and scanline transfers can be rendered in a top to bottom direction for a 0 page or in a bottom to top direction for a 180 page When bit block transferring to a banded bitmap with the B2T flag set the definition of certain graphic order parameters change Namely the frame bitmap address parameters DA SA and HA must be provided so they are pointing to the bottom left corners of their respective frames instead of the upper left and the HYR halftone parameter must provide the number of scanlines remaining to reach the top of the bitmap instead of the bottom Figure 13 2 uses the halftone bitmap parameters to illustrate this requirement The parameters of scanline operations are also
299. ring specifier in the scanline table There is no corresponding halftone specifier for 16 bit bit specifiers because they are halftoned without assistance The halftone specifiers use displacements instead of absolute values This minimizes the number of halftone tables to one per halftone pattern for each halftoned character Thus if a character is halftoned only one halftone table must be constructed regardless of the number of times the character is used The same halftone table for a particular character can be used with different halftone patterns if the dimensions of each halftone bitmap are identical Each field of a halftone specifier corresponds to a similar field in the 32 or 48 bit bit string specifier As illustrated in Figure 12 6 the 32 bit halftone specifier contains two fields a halftone horizontal movement HDX and a halftone run length HRL HDX corresponds to the 32 bit bit string specifier s DX field and HRL corresponds to the RL field BYTE ADDRESS OF WORD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDX 2 HRL NOTES HRL Halftone Run Length unsigned HDX X Dimension Displacement Horizontal unsigned Figure 12 6 32 Bit Halftone Specifier Format HDX and HRL are defined as follows where HW is equal to the warp of the target halftone bitmap HDX DX mod HW DX gt 0 V HW DX mod HW mod HW DX lt 0 HRL RL mod HW For On The Product Go to www freescale com Freescale
300. rinting can begin Like PDLs DDLs are considered highly complex MC68322 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction 1 4 2 Bitmap A bitmap is a two dimensional array of memory bits A scanline is one row in the array There is no special term for each column of the array The junction point of a scanline and a column is a pixel The bitmap width called the X dimension is the number of pixels in each scanline The bitmap height called the Y dimension is the number of scanlines in the bitmap array Figure 1 6 illustrates these terms COLUMN 72222 B PIXEL 7 SCANLINE BIT MAP HEIGHT DIMENSION Figure 1 6 Bitmap Structure A bitmap can be stored in memory as either packed or unpacked as illustrated in Figure 1 7 Packed bitmaps occupy less memory than unpacked bitmaps In an unpacked bitmap each scanline begins on a byte or word boundary In a packed bitmap scanlines follow one another without regard to byte or word boundaries The MC68322 supports both packed and unpacked bitmap structures WARP X DIMENSION 7 WARP X DIMENSION gt gt ZZZA UNPACKED BIT MAP PACKED BIT MAP 30 BYTES 1 BYTES WASTED 23 BYTES d BYTE WASTED Figure 1 7 Unpacked And Packed Bitmaps MC68322 U
301. riority level and then posts the interrupt event to the core This type of internal interrupt event is called a hardware interrupt because it is initiated by one of the MC68322 modules The MC68322 supports another type of interrupt event called a software interrupt This type of interrupt is initiated by the software by programming some internal registers on the MC68322 Once the software has initiated such an event the interrupt will be posted to the core in exactly the same way as a hardware interrupt event The advantage that these MC68322 hardware interrupts provide over the typical 68000 Family software exceptions is that these software interrupts can be set at a lower priority level than the current interrupt event and thus be delayed until the core runs at a lower priority level This causes the software interrupt to be serviced sometime between the current interrupt and the next noninterrupt operation See Section 5 4 2 3 Instruction Traps for more information For Mort d dora MANDA Product Go to www freescale com Freescale Semiconductor 5 1 1 Hardware Interrupts There are 31 hardware interrupt events that can be posted from a module to the core The interrupt events are grouped together by module and listed in Table 5 1 Each module has a corresponding interrupt level register which is used to set the needed interrupt level for the module Each module s interrupt event register is individually describ
302. rns are typically anchored to the page Thus a bitBLT may need to take on the halftone pattern starting at various points in the halftone bitmap depending on where itis positioned on the page The halftone parameters HXR HYR and HA define the precise halftone pixel that corresponds to the upper left corners of the source and destination frames HXR specifies the number of pixels remaining to the right edge of the bitmap and HYR defines the number of scanlines remaining to the bottom edge HXR and HYR must be in the following ranges 1 x HXR x HW and 1 x HYR x HH where HW and HH are the width and height of the halftone bitmap respectively For example if the starting pixel in the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH to start at the lower right HXR and HYR must both be set to one The DA SA and HA parameters must point to the upper left corners of their respective frames Related Graphic Orders SET BOOL SHD SET HTBMAP SET SBMAP SET UBMAP For Mort ON oduct to www freescale com Freescale Semiconductor Inc ARTE UR SOURCE BITMAP SW Ix DESTINATION UNBANDED BITMAP lt DWU gt BOOL_SHD USED FW 5 Figure 13 20 Source Halftone Destination bitBLT to Unbanded Bitmap For Mort 160322 On This Product Go to www freescale com __Freescale Semiconductor
303. rocessing for illegal instructions is similar to that for traps After the instruction is fetched and decoding is attempted the core determines that execution of an illegal instruction is being attempted and starts exception processing The exception stack frame is then pushed on the supervisor stack and the illegal instruction vector is fetched For On The Product Go to www freescale com Freescale Semiconductor Inc 5 4 2 5 PRIVILEGE VIOLATIONS provide system security various instructions are privileged An attempt to execute one of the privileged instructions while in the user mode causes an exception The privileged instructions are as follows and immediate to sr move usp eor immediate to sr or immediate to sr move to sr reset move from sr rte e movec stop e moves Exception processing for privilege violations is nearly identical to that for illegal instructions The core starts exception processing once the instruction is fetched decoded and the core determines that a privilege violation is being attempted The internal status register is copied the supervisor mode is entered and tracing is turned off The vector number is generated to reference the privilege violation vector and the current internal program counter and copy of the internal status register are saved on the supervisor stack The saved value of the internal progr
304. rol of 9 4 CAS DRAM read cycles 7 7 CASx DRAM burst accesses 7 10 CMD STS direction of 10 2 CSx DMA access timing 8 8 GDMA read cycle during 8 7 DACK DMA access timing 8 8 GDMA handshaking 8 7 GDMA read cycle 8 7 DMA interface 2 8 DRAM interface 2 7 mavan DREQ default configuration 8 7 GDMA handshaking 8 7 DTACK asynchronous 000 Core timing 6 5 illegal memory address access 5 3 external bus master 2 6 external interrupts 5 4 FAULT driving high level on 9 4 FSYNC page band begin interrupt during 10 7 LDS lower data strobe 7 8 parallel port interface 2 9 print engine video controller interface 2 8 printer communication interface 2 8 RAS DRAM read cycles 7 7 SELECT driving high level on 9 3 STROBE during compatibility mode transfer 9 8 hardware handshaking disabled 9 10 system interface 2 4 WAIT asynchronous 000 Core timing 6 5 WE DRAM read cycles 7 7 DRAM write cycles 7 8 during refresh cycles 7 6 WRL DMA transfers during 8 6 GDMA write cycle 8 7 WRU DMA transfers during 8 6 GDMA write cycle 8 7 SIM 6 1 SL2BB_D 13 55 SL2BB_HD 13 57 SL2F_D 13 60 SL2F_HD 13 61 SL2UB_D 13 63 SL2UB_HD 13 64 SLTA see scanline table address SmartToner enabled 10 5 soft reset PVC 10 7 RGP 11 4 specifications 14 1 SR 5 7 stack frame exception 5 8 5 11 static column 7 1 STOP 13 66 Product For Raa ion Go to www freescale com Freescale Semiconductor
305. rough the normal bus arbitration procedure 1 The external device must have received the BG signal through the arbitration process 2 Inamultiple bus master situation it is important to be sure that only one processor has the bus at any given time For On This Product Go to www freescale com Freescale Semiconductor renee The external bus master can negate BR as soon as the MC68322 asserts EDTACK The bus is then granted back to the core when BR is negated If BR is negated before EDTACK is asserted BG remains active until EDTACK is asserted and negated The external bus master should not assert BR for long periods of time because this would starve the core and other modules for memory cycles DRAM accesses and refreshes continue regardless of bus arbitration Figure 4 11 illustrates a bus arbitration timing diagram 50 52 54 56 50 52 54 56 50 52 we No BS p p DS mmm EDTACK N CONTROLLER gt lt EXTERNAL READ gt lt CONTROLLER Figure 4 11 Bus Arbitration Timing Diagram 4 5 2 External Bus Master Read Cycle When the external bus master reads from DRAM chip selects or internal registers the data is internally latched at the end of the read cycle The MC68322 asserts EDTACK and drives the data out onto the data bus When the external bus master reads from the chip selects the data is latched on the CLK1 that RD is negated The chip select devices stop driving th
306. rted for the initial processor reset When RESET is driven by an external device the entire system including the core and internal registers are reset Resetting the MC68322 initializes the internal state The processor reads the reset vector table entry address 000 and loads the contents into the supervisor stack pointer Next the processor loads the contents of address 004 vector table entry 1 into the program counter Refer to Table 5 3 for more information about exception vector assignments The processor then initializes the interrupt level in the status register to a value of seven Figure 4 10 illustrates the timing of the reset operation RESET must be asserted for at least 132 clocks for initial reset For a subsequent external reset asserting this signal for 10 clock cycles or longer resets the MC68322 CLK1 5 VOLTS E T gt 132 CLOCKS lt 1 I 9 1 4 CLOCKS BUSCYCLES 00000 MM XNOTE3 X NOTE 4 XNOTES NOTE 6 ALL CONTROL SIGNALS INACTIVE DATA BUS IN READ MODE NOTES 1 Internal start up time 2 SSP high read in here 3 SSP low read in here 4 PC high read in here 5 PC low read in here 6 First instruction fetched here Figure 4 10 Reset Operation Timing Diagram If the core executes the reset instruction the internal state of the MC68322 its internal registers and its external devices are all unaffected Neithe
307. ruction will not affect any changes in the system and should be avoided due to the long execution time of the instruction A reset exception is initiated by RESET not the reset instruction The reset instruction does not assert the RESET signal and does not modify any internal registers The execution of the reset instruction does not affect the state or function of other on chip modules 5 4 2 2 INTERRUPT EXCEPTIONS An interrupt event is posted to the core by the interrupt controller using the internal IPL2 IPLO Interrupt events arriving at the core do not force immediate exception processing but the requests are given a pending status Pending interrupts are detected between instruction executions If the priority of the pending interrupt is lower than or equal to the current core priority mask level execution continues with the next instruction and the interrupt exception processing is postponed until the current core priority mask level becomes less than the pending interrupt event If the priority of the pending interrupt is greater than the current core priority mask level the exception processing sequence is started A copy of the internal status register is saved the privilege mode is set to supervisor mode tracing is suppressed and the core priority mask level is set to the level of the interrupt being acknowledged The core internally generates a vector number corresponding to the interrupt level number It then proceeds with the
308. rvisor Program Interrupt Acknowledge INTERNAL BUS REQUEST Output This signal is used by the internal bus arbitration control logic It should be connected directly to the M68000 emulator BR signal BG INTERNAL BUS GRANT Input This signal is used by the internal bus arbitration control logic It should be connected directly to the M68000 emulator BG signal I AVEC INTERNAL AUTOVECTOR Output This signal is used by an emulator to assert the AVEC signal during an interrupt acknowledge cycle It should be connected directly to the M68000 emulator AVEC or signal For On This Product Go to www freescale com _ Freescale Semiconductor RESET INTERNAL RESET Output This signal is used by an emulator to assert RESET signal Typically this signal is connected directly to the MC68000 ICE INTERNAL HALT Output This signal is used to assert the emulator HALT signal It should be connected directly to the M68000 emulator HALT signal ICE DATA LATCH ENABLE Output This signal is used by external latches to latch incoming data before being sent to the emulator ICEN ICE ENABLE Input This signal should be asserted during in circuit emulation because it will force the MC68322 to act as a slave device to an external M68000 processor It must be asserted or negated before the negation of RESET and remain th
309. s A 2 PUNGCUONM Gode 9 Sai 3 C 1 Register 1 D 1 ALTPIN SEL Bit Descriptions ee eoe reete eere apo ocu ee D 1 For Mare Un This Product Go to www freescale com Freescale Semiconductor SECTION 1 INTRODUCTION MC68322 is a high performance integrated printer processor that combines MC68000 compatible 000 core processor a RISC graphics processor a print engine video controller PVC and numerous system integration features on a single integrated circuit It is the first of Motorola s M68000 Family designed specifically for nonimpact printers The MC68322 provides a unique solution for new designs as well as an excellent migration path for existing M68000 powered printers Additionally the new chip finds ready application to the inkjet printer and multifunction peripheral fax modem printer markets and other embedded control applications which require very fast bit manipulations The dual processor and dual bus architecture gives the MC68322 the ability to deliver excellent performance Historically printer applications have been solved using a single general purpose processor with external application specific circuitry The MC68322 employs a highly specialized multiprocessor architecture that enables the user to take advantage of memory reduction
310. s 1 8 printer video controller soft reset register 5 14 printer video controller PVC burst cycles 7 1 DMA accesses 7 1 priviledge violation exception 5 11 privileged instructions listed 5 11 program flow control graphic orders 13 3 PVC reset interrupt event 10 15 PVC 10 1 PVCCR 10 3 PVCIR 10 6 R RDR 11 2 reallocating DMA resource 8 6 refresh cycle CAS before RAS timing 7 5 EC000 Core accesses 7 6 timing 7 6 timing parameters 7 5 refresh cycle 7 6 refresh cycles WE during 7 6 registers alternate pin D 2 chip select DMA timing 6 3 chip select recovery 6 4 chip select related 6 1 chip select 6 1 DMA speed 8 4 DRAM see DRAM registers DRAM control 7 5 DRAM 7 1 external interrupt 5 4 external interrupt described 5 4 GDMA configuration described 8 2 GDMA configuration 8 2 GDMA control 8 3 For ME RS internal status 5 1 interrupt event 4 6 5 1 interrupt level 5 1 location overlap priority 6 3 mask C 3 memory mapped C 1 module soft reset MSRR described 5 14 parallel port control 9 4 parallel port interface 9 2 PDMA configuration 8 2 PPI interrupt event 9 6 printer communication interrupt event 10 8 printer communication 10 2 printer control block 10 5 PVC control 10 3 PVC interrupt event 10 6 RGP diagnostic 11 2 RGP interrupt event 11 2 RGP start 11 2 software interrupt event described 5 3 software interrupt event 4 12 5 3 status see 000 Core status 4 8
311. s Before The RD Figure 14 10 Read Access 4 4 1 3 For More ie ash M product Go to www freescale com Freescale Semiconductor Inc UNM A WEA WUT ILIV CLK2 A25 A1 57 50 RD 015 00 5 R W EC000 Core Read Cycle AC Timing One Wait State Access RSET 2 RACC 0 RHLD 0 Hold Time of 1 CLK2s The Chip Select Negates Before The RD Figure 14 11 Read Access 6 2 1 3 s 52 s 57 T 25 1 eee CS7 CS0 WRU WRL 015 00 lt WAIT E SR 9 5 One R W 000 Core Write Cycle AC Timing Zero Wait State Access WSET 1 WACC 0 WHLD 0 Hold Time of 1 CLK2s The Chip Select Negates Before The RD Figure 14 12 Write Access 4 2 1 3 For On The Product Go to www freescale com Freescale Semiconductor MeV EU UNM FEWER WHI UVLO CLK2 A25 A1 CS7 CS0 WRU WRL 015 00 5 RW 000 Core Write Cycle AC Timing One Wait State Access WSET 1 0 WHLD 1 Hold Time of 1 CLK2s The Chip Select Negates Before The wru wrl Figure 14 13 Write Access 4 2 1 3 50 CLK2 0 E 00 CS7 CS0 WRU WRL D15 D0 5 RW 4 000 Core Write Cycle AC Timing One Wai
312. s clear and to the lower left corner of the bitmap when the B2T flag is set The warp of the unexpanded bitmap is set by the source width operand This value is added to SA to locate the beginning of each successive scanline Note that the source warp set by the SET SBMAP graphic order has no effect on this graphic order For Mort ON oduct to www freescale com Freescale Semiconductor Inc vwiuvis XOFF XMUL parameter is divided into two fields The least significant four bits contain the XMUL field which specifies the factor used to scale the unexpanded source bitmap in the X dimension XMUL must equal a specific value from 0 15 which represents a scaling factor of 1 16 Only certain scaling factors are supported as defined in Table 13 3 Values other than those listed are ignored and no X scaling is performed Table 13 3 Supported Scaling Factors EXPANSION FACTOR XMUL VALUE The XOFF field occupies the four most significant bits and indicates the number of bits to be clipped at the left edge of the expanded source bitmap XOFF ranges from 0 XMUL If XOFF is zero no clipping occurs at the left extent but if itis non zero XOFF number of bits in the left edge of the expanded bitmap are skipped and the next bit is the first one transferred to the destination bitmap The YOFF YMUL parameter is also divided into two fields The least significant four bits contain the Y
313. s issued at the bottom of every page end of page is determined by the BND bit in the PCB control field immediately after the last word of the last scanline is read from memory In response to a page end interrupt event the page or band buffer can be reclaimed and reused for the next page BUD Band Underrun This bit indicates a banding error which is posted when the last word of one band is read but the PCB register set specifically the page image bit address for the next band is not yet loaded Band underruns usually point to a page description that is too complicated for the given banding environment This bit is only set when the BND bit in the PCB control field is set thus indicating that the image data is a band VUD Video Underrun This bit indicates that a video underrun has occurred It is posted if the print engine requests video data faster than the PVC can access memory A video underrun is usually the result of a band underrun or PVC error but can also mean the memory configuration is too slow for the video rate of the print engine Address This bit indicates the PVC s attempt to read from DRAM memory that is nonexistent because of an out of range address The out of range address occurs when reading page image data and can be the result of loading an illegal memory address in the page image bit address register or reading beyond the end of memory space The PVC shuts down in response to an out of range
314. s only to load capacitance values greater than CL Output drive derating factors are not accurate for load capacitance values less than CL or for capacitance greater than 250 pF 4 Capacitance is periodically sampled rather than always tested For On The Product Go to www freescale com Freescale Semiconductor Me CR A WIE WUT ILUV 14 4 AC ELECTRICAL SPECIFICATIONS 14 4 1 Clock and Reset Timing Duc E pene EET Ls 5 1 The frequency of operation is equal to one half CLK2 frequency 2 MC68322 is a 100 static cell design and has no absolute lower limit on operating frequency However system requirements including the minimum DRAM refresh period require special attention below 4 MHz 3 Forpower up the MC68322 must be held in the reset state for 100 ms to allow stabilization of on chip circuitry After the system is powered up this requirement refers to the minimum pulse width required to reset the processor 4 RESET is an asynchronous input and is synchronized internally by the MC68322 It requires no setup or hold time in order to be recognized for proper operation However to guarantee recognition of the input at a certain edge of CLK2 RESETmust satisfy the setup requirement 20V CLK2 15V 08V Q
315. s scaled to match the resolution of the destination bitmap This results in an intermediate expanded source bitmap The pixels of the expanded source and destination bit maps are combined as specified by the Boolean code set in the last SET BOOL SD order The DA parameter specifies the physical bit address of the destination frame It must point to the upper left corner of the destination frame The destination frame will be packed since its warp is assumed to equal FW The FW and FH parameters define the area of the destination bitmap on which the operation is performed FW is the frame width in bits and at a maximum equals the quantity W x XMUL 1 where is the width of the unexpanded source bitmap FH is the frame height in scanlines and at a maximum equals the quantity H x YMUL 1 where H is the height of the unexpanded source bitmap Specifying FW FH as defined above causes the entire expanded source image to be combined with the destination bitmap Specifying an FW and or FH value less than the values defined by the above equations causes only a portion of the expanded source frame to be applied to the destination When used in combination with XOFF and YOFF clipping can be affected at any or all extents of the expanded source bitmap The SA parameter defines the unexpanded source bitmap bit address It must point to the upper left corner of the bitmap The warp of the bitmap is set by the SW operand This value is added to SA to
316. sampled After all eight bits of the status are sampled the print engine interface enters a recovery cycle The recovery time is one half CCLK period as programmed in the PCOMR s CCLK divisor field During the recovery time SBSY is not sampled and if a command operation is initiated it will be latched and executed after the recovery When the status operation is complete the PCIER s STR bit is set thus indicating that the PCOMR s printer status field is full If enabled this bit can and will cause an interrupt event SBSY is an asynchronous signal to the print engine interface and is internally synchronized to CLK1 The print engine should not assert the signal at any time during a command operation or recovery cycle Once SBSY has been asserted it must remain that way until the status operation is initiated Figure 10 9 illustrates the timing diagram for a status operation when the core supplies CCLK For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor IQ 1 2 3C 4 5 6 7C 8C 9C NOTES CBSY and CMDISTS are in high impedance A STS is sampled by the 000 core B Recovery cycle half CCLK period Any pending command is acknowledged after the recovery Figure 10 9 Status Operation MC68322 Supplied CCLK 10 3 3 2 CCLK SUPPLIED BY PRINT ENGINE In this mode the print engine is expected to supply eight h
317. serted during a command operation Figure 10 8 illustrates the timing diagram for a command operation when the print engine supplies CCLK For On This Product Go to www freescale com Freescale Semiconductor QI A MO NOTES SBSY and STS are not sampled during command operations transmitted with the first falling edge of CCLK B CMD sampled by the print engine CMD STS hold controlled by the CCLK divisor field D Recovery cycle half CCLK period Any print engine response is acknowledged after recovery cycle Figure 10 8 Command Operation Print Engine Supplies CCLK 10 3 3 Status Operation CCLK status information is sent to the MC68322 from the print engine During the status operation serial data is assembled into the PCOMR s printer status field Status information can be supplied to the MC68322 on either the STS or CMD STS signals If status information is driven on STS the CMD STS signal will be in a high impedance state CBSY is in a high impedance state during the status operation 10 3 3 1 CCLK SUPPLIED BY MC68322 In this mode the MC68322 print engine interface generates eight high to low transitions of CCLK so that the status data can be sampled at every rising edge The PICR s CCLK divisor field must be programmed to provide sufficient setup and hold time for the status data to be
318. set the new address overwrites the previously queued address Also when an error occurs RBY and DLF retain their state until the RGP is soft reset 11 2 RGP BASIC OPERATION The RGP can render either an entire page from a display list or multiple bands from a single banded display list The RGP is activated by writing the starting address of a display list to the RSR The RGP then executes the display list and renders a page or band image and when the end of the display list is reached the RGP generates an RGP done interrupt event to the core and waits for another display list address Be aware that a second display list address can be loaded while the RGP is working on the first display list In this case an interrupt is generated upon completion of the first display list and the second display begins executing immediately Also a second interrupt is generated upon completion of the second display list The ability of the RGP to render multiple bands from a single banded display list allows for complete freedom in the design of a banded memory system A banded display list contains band information near the beginning of the list This band information includes the address and size of the band as well as the band number that is to be processed The RGP uses this information to determine which orders from the display list to process and where in memory to create the bitmap image for the specific band After one band is fully rendered and the RGP
319. sfers SET_BOOL_SD Set Boolean Operator For Source Destination Transfers SET_BOOL_SHD Set Boolean Operator For Source Halftone Destination Transfers Program Flow Control JUMP Jump To The Specified Address In The Display List BENE Bit Block Transfers BL2F D bitBLT To Frame Destination Only BL2F SD bitBLT To Frame Source Destination BL2F SHD bitBLT To Frame Source Halftone Destination BL2UB D bitBLT To Unbanded bitmap Destination Only BL2UB SD bitBLT To Unbanded bitmap Source Destination BL2UB SHD bitBLT To Unbanded bitmap Source Halftone Destination BL2BB D bitBLT To Banded bitmap Destination Only BL2BB SD bitBLT To Banded bitmap Source Destination BL2BB SHD bitBLT To Banded bitmap Source Halftone Destination Expanded Bit Block Transfers BLT2F XD bitBLT To Frame expanded Source Destination BLT2F XHD bitBLT To Frame expanded Source Halftone Destination BLT2UB XD bitBLT To Unbanded bitmap expanded Source Destination BLT2UB XHD bitBLT To Unbanded bitmap expanded Source Halftone Destination BLT2BB XD bitBLT To Banded bitmap expanded Source Destination BLT2BB XHD bitBLT To Banded bitmap expanded Source Halftone Destination Scanline Transfers SL2F D Scanline To Frame Destination Only SL2F HD Scanline To Frame Halftone Destination SL2UB D Scanline To Unbanded bitmap Destination Only SL2UB HD Scanline To Unbanded bitmap Halftone Destination SL2BB D Scanline To Banded bitmap Destination Only SL2B
320. sion logic to return to idle The handshake controller immediately discontinues handshaking with the host terminates decompression and any pending DMA request is removed When the PPI state machine is in the idle state BUSY and ACK are negated If BSY2 and ACK2 are clear then BSY1 will be cleared and will be set RST also clears RLD and FLL bits in the PPCR The software should issue RST under error conditions such as when an invalid transition interrupt occurs or when the software detects a time out error 9 8 DATA TRANSFER RATE The expected data transfer rate in a system depends on several factors capability of the host computer memory speed and bandwidth used The block size of the data transfer affects the data rate because of the overhead involved Forward data transfers are DMA based and reverse data transfers are interrupt based Overhead cycles such as the negotiation phases are also interrupt based The following are expected data transfer rates Compatibility mode forward data rate 400K sec Actually the PPI is capable of a compatibility mode forward data rate of 2M sec The 400K sec is determined by the IEEE 1284 specification ECP mode forward data rate 2M sec ECP decompression forward data rate 4M sec Nibble mode reverse data rate 5K sec Byte mode reverse data rate 10K sec For On The Product Go to www freescale com Freescale Semicondu
321. t State Access WSET 1 WACC 1 WHLD 0 Hold Time of 1 CLK2s The Chip Select Negates Before The WRU WRL Figure 14 14 Write Access 4 4 1 3 For On The Product Go to www freescale com Freescale Semiconductor Inc _ s st s2 s3 s4 ss 5 s w so 015 00 RW so s s3 s4 w w s 5 57 7 77 Q er Figure 14 16 DMA Write Cycle AC Timing For On The Product Go to www freescale com Freescale Semiconductor CAPER NV WHI UIE JUV 14 4 3 DRAM Timing CLK2 10 0 55 50 51 50 MD15 MDO CLK2 MA10 MAO gt RAS5 RASO 51 50 MD15 MDO Figure 14 18 DRAM Write Cycle AC Timing For On This Product Go to www freescale com Freescale Semiconductor Me CR EE WEE WUT ILUV 14 4 4 IDMA Timing CHARACTERISTIC CES UNIT DACK Valid from CLK2 27 DREQ Asynchronous Input Hold after 2 28 DREQ Asynchronous Input Pulse Width NOTE Denotes that DREQ is an asynchronous input and is sync
322. t clock It is preferable to use the rising edge of the clock when there is a choice because it will produce slightly less jitter The prescaler can be set to divide by three This is useful in a situation where only one resolution is required because this would allow a common input clock for both VCLK and CLK2 For example if an 8 ppm engine at 300 x 300 dpi requires a dot clock of 2 5 MHz then VCLK could be 30 MHz This 30 MHz clock could also be used for the processor clock CLK2 so that an oscillator could be eliminated from the board For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor 10 4 There two sources for PVC reset interrupt event the MC68322 RESET pin and the MSRR s PVC bit The RESET pin resets the entire device while the PVC soft reset only resets the PVC and PLL logic The state of the PVC after each type of reset is similar in that The PLL is reset All PVC controllers return to idle The PVCIR s PFL and BSY bits are cleared There are two important differences during a MC68322 reset all PVC registers are cleared and any pending PVC interrupts are cleared Following the assertion of the RESET input all PVC registers are cleared to zeros This causes the PVC to assume a default interface The default interface uses a 1x clock interprets all inputs and drives all outputs
323. t sets one of these five interrupt sources in the PVCIR After any of these interrupts occur the PVC s operation is undefined and must be immediately reset by the module soft reset register s MSRR PVC bit to return it to normal operation OOFFF700 ENABLE LEVEL RESERVED Figure 10 4 PVC Interrupt Event Register Note The PVCIR is located in the interrupt register portion of the memory map and therefore is not necessarily located contiguously with the other print engine interface registers BSY PVC Busy This bit indicates when the PVC is executing a print operation PFL PCB Full This bit indicates when the PCB register set is available for a new print operation The PCB registers should only be loaded when the PFL bit is clear When the PFL bit is set the PCB register set should not be altered For On This Product Go to www freescale com Freescale Semiconductor PIII PBB Page Band Begin This bit is posted at the start of every page or band At the start of a page PBB is set after it receives FSYNC from the print engine and provides timing information to the software for controlling the PVCCR s PRT bit typically the timing of a print engine s PRINT signal is referenced to FSYNC When starting a band in the middle of a page a page band begin interrupt event is posted when the first page image data is read from memory PGE Page End This bit i
324. t the FR bit in the channel s configuration register and still have the DMA transfer terminate normally due to the transfer counters decrementing to zero If this condition occurs both the CMP and TCR bits will be set in the channel s interrupt event register For On The Product Go to www freescale com Freescale Semiconductor SECTION 9 PARALLEL PORT INTERFACE The MC68322 contains a direct connect fully IEEE 1284 Level 2 compliant bidirectional parallel port interface PPI The PPI supports four IEEE 1284 communications modes compatibility Centronics nibble byte and enhanced capabilities port ECP It also supports all variants of these modes including device ID requests and run length encoded RLE data compression The PPI contains specific hardware to support automatic handshaking during host to peripheral forward data transfers in compatibility and ECP modes and run length detection and decompression of host to peripheral data during ECP transfers This can substantially improve data rates when operating the parallel port in compatibility or ECP mode When hardware handshaking is used in combination with the PPI s dedicated DMA controller data rates as high as 2M per second can be achieved in ECP forward mode The software can disable and enable hardware handshaking to allow direct control of PPI signals as well as to support future protocols The remainder of IEEE 1284 operations n
325. t to the print engine Both the RGP and PVC require only a minimal amount of initialization and intervention by the core to produce an image and transfer it to the print engine Figure 1 2 illustrates the data flow of the graphics unit 1 4 MC68322 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction PROM MC68322 DRAM GRAPHICS UNIT DISPLAY RISC GRAPHICS LIST PROCESSOR RGP mi PRINT ENGINE VIDEO px CONTROLLER PVC PRINT ENGINE Figure 1 2 Graphics Unit Data Flow Diagram 1 2 3 Bus Interface Unit The dual bus architecture of the MC68322 allows the printing workload to be distributed among processing units and executed in parallel The bus interface unit BIU allows the core and graphics unit which reside on the MC68322 bus and graphics bus to function independently This is done through an arbitration unit which accommodates core accesses to DRAM residing on the graphics bus However to print pages correctly the graphics unit gets higher priority than the core for DRAM accesses The core performs instruction and PROM data fetches without any impact to graphics bus operations The BIU contains a single word writeback buffer that reduces peak bus traffic generated by multiple active modules The writeback buffer provides a no wait state write profile to the core and delays the write until the graphics unit stops using the
326. the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH to start at the lower right HXR and HYR must both be set to one The DA SA and HA parameters must point to the upper left corners of their respective frames Related Graphic Orders SET BOOL SHD SET HTBMAP SET SBMAP For Mort ON oduct to www freescale com Freescale Semiconductor supine SOURCE BITMAP DESTINATION UNBANDED BITMAP lt DWU gt BOOL_SHD USED TO COMBINE FRAMES HALFTONE BITMAP 1 TM Figure 13 15 Source Halftone Destination bitBLT to Frame For Mort farsi Shon On This Product Go to www freescale com Freescale Semiconductor Inc BLT2F XD Expanded Source Destination bitBLT to Frame PARAMETERS s DESCRIPTION Byte BLT2F XD Opcode Byte Reserved Long Word Destination physical bit address Word Destination frame width in bits Word Destination frame height in scanlines Long Word Unexpanded source physical bit address Word Unexpanded source frame warp in bits XOFF XMUL Two 4 bit Fields X offset and X multiplier in bits YOFF YMUL Two 4 bit Fields Y offset and Y multiplier in scanlines The BLT2F XD graphic order transfers a low resolution source frame to a destination frame Before being combined with the destination the source frame i
327. the number of scanlines remaining to the bottom edge HXR and HYR must be in the following ranges 1 x HXR x HW and 1 x HYR x HH where HW and HH are the width and height of the halftone bitmap respectively For example if the starting pixel in the halftone bitmap is determined to be at the upper left HXR must be set to HW and HYR to HH HTTA SLTA point to the most significant byte of the first specifier in their respective tables and DA and refer to the pixel to which the displacement of the first bit string specifier is added not necessarily the first bit of the first run Since both the scanline table and companion halftone table s specifiers must be placed at word boundaries HTTA and SLTA must be word aligned Related Graphic Orders SET BOOL HD SET HTBMAP SET UBMAP For Mort ON oduct to www freescale com Freescale Semiconductor Inc Puy SZ ti SCANLINE COMPANION DESTINATION TABLE HALFTONE TABLE UNBANDED BITMAP SLTA HTTA A DWU ins HALFTONE SPECIFIERS DA FIRST a DISPLACEMENT BITSTRING SPECIFIERS BOOL_HD USED TO COMBINE FRAMES HALFTONE BITMAP I x Tu Figure 13 33 Halftone Destination Scanline Transfer to Unbanded Bitmap For Mort farsi Shon On This Product Go to www freescale com Freescale Semiconductor MAT wires STOP Stop Display List Execution PARAMETE
328. timing register CSDTR is a dedicated register that provides access timing parameters to the chip select bank accessed by the general purpose DMA GDMA during DMA transfers These timing fields function in a similar manner as those in the upper word portion of a CSR However the normal timing parameters for the bank are not used when the bank is accessed by the GDMA See Section 8 DMA Interface for more details For More MES 822 ae BM oduct to www freescale com 5 Semiconductor chip select recovery register CSRR contains REC field that controls the chip select recovery time This recovery time applies to a chip select only if it has been enabled in the recovery select field The REC field provides a common programmable recovery value for all chip select banks Since the recovery time is common for all the chip select banks it should be programmed to satisfy the maximum recovery value for all chip select banks If the recovery time has not been satisfied between successive access to a bank with recovery enabled the second access is delayed Each bit of the recovery select field corresponds to a chip select bank If recovery is enabled it is forced for that bank regardless of when it is accessed by GDMA the core or an external bus master 6 2 SYNCHRONOUS AND ASYNCHRONOUS CHIP SELECT ACCESS TIMING In synchronous mode once the progra
329. tination frame and applies a halftone bitmap in the process Before being combined with the destination the source frame is scaled to match the resolution of the destination bitmap which results in an intermediate expanded source bitmap The pixels of the expanded source halftone and destination bit maps are combined as specified by the Boolean code set in the last SET BOOL SHD order The SET_HTBMAP graphic order must previously define the halftone bitmap dimensions During the processing of halftones wrapping occurs at the edges of the bitmap and this results in horizontal and vertical replication tiling of the bitmap to cover the entire destination frame area The DA parameter specifies the physical bit address of the destination frame It must point to the upper left corner of the destination frame The destination frame will be packed since its warp is assumed to equal FW The FW and FH parameters define the area of the destination bitmap on which the operation is performed FW is the frame width in bits and at a maximum equals the quantity W x XMUL 1 where W is the width of the unexpanded source bitmap FH is the frame height scanlines and at a maximum equals the quantity H x YMUL 1 where is the height of the unexpanded source bitmap Specifying FW and FH as defined above causes the entire expanded source image to be combined with the destination bitmap Specifying an FW and or FH value less than the values defined by the above eq
330. tion set are specifically designed to render images either top to bottom or bottom to top thus enabling banding of both 0 and 180 pages on duplex printers MC68322 USER S MANUAL 1 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Introduction There are two elements to keep in mind when determining image orientation the feed edge and the binding edge The feed edge of a page is the edge that is first fed into the print engine The binding edge of a page is the edge that will be used in the binding process For example if a document is to be stored in a three ring binder the binding edge would be the edge of the paper where the holes are punched To determine whether the second side of a page needs to be rotated the feed edge must be compared to the binding edge If the feed edge is the same as the binding edge then the second side does not need to be rotated However if the feed edge is different from the binding edge then the second side must be rotated 180 to have the proper orientation between both sides of the page Figure 1 9 illustrates a duplex printing operation The paper is fed by its short edge when the binding edge is defined as the long edge This means the second pass image should be rotated 180 During the first pass paper travels from the input hopper and under the drum and an image is placed on the page After fusing the page is placed face down in the duplex
331. to stop driving the data and address buses Only word sized write cycles are supported and there is no data strobe signal available to the external bus master The external bus master is required to supply valid data from the beginning of the cycle Figure 4 13 illustrates a write cycle from the external bus master For Mors On This Product Go to www freescale com Freescale Semiconductor Wr A25 A1 D15 D0 EDTACK NOTES lt A Master requests bus by asserting BR MC68322 grants bus by asserting BG _ Master drives 1 25 and asserts R W D Master asserts AS Master drives 00 015 F MC68322 and asserts EDTACK Master deasserts AS and stops driving 00 015 and 1 25 H MC68322 deasserts EDTACK Master deasserts BR J MC68322 deasserts BG Figure 4 13 External Bus Master Write Cycle 4 5 4 Illegal Address Interrupt If the external bus master accesses a memory location not mapped to a register DRAM or chip select the MC68322 asserts EDTACK immediately and waits for AS to be negated before it negates EDTACK This bad access by the external bus master causes an illegal address interrupt bit to be set in the software interrupt event register This causes a level 7 interrupt event to be posted to the core but no interrupts are posted to the external master For More ie ah m TN product Go to www freescale com Freescale Semiconductor S
332. to the printer The PPIR also contains eleven bits that control the parallel port interface signals These eleven bits consist of four read only bits that are used to read the logic level of the host input pins two read only bits to read the logic level on the BUSY and ACK printer output pins and five read write bits control the logic levels on the printer output pins Figure 9 2 illustrates the parallel port interface register 15 44 13 12 11 40 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED These bits are read only bits Figure 9 2 Parallel Port Interface Register ACKW ACK Width This field defines the ACK pulse width when compatibility mode is enabled PPCR MODE field 01 The ACK pulse width is selectable from 0 to 255 CLK1 periods wide At 16 MHz the software can set pulse widths anywhere in the range of 0 to 16 us If the field is clear no ACK pulse is issued Otherwise the cycle proceeds as normal ACKW can be changed at any time and with any PPCR MODE encoding selected but it can only be used during a compatibility mode handshaking cycle If ACKW is changed near the end of a data transfer when an ACK is already low then the new pulse width value does not affect the current cycle The new value of ACKW is used when the next cycle occurs CMD Command When read this bit provides the logic level of AUTOFD when STROBE transitioned from high to low with the PPCR s PDE bit clear If set A
333. ts which describe the outline of a set of characters via splines lines and arcs The outlines are scaled for the preferred point size through software algorithms The result is a set of scanline endpoints that must be filled to create a solid character The second occurs from vector images such as wire frame diagrams which are entered as either a series of line drawing graphic orders or as a previously generated bitmap Since these vector images contain a high percentage of white space they typically require less storage space when described as a series of scanline operations Scanline transfers operate on a destination bitmap and specify a halftone bitmap to render grayed or patterned images No source bitmap is involved in a scanline transfer 12 6 1 Scanline Tables and Bit String Specifiers A scanline table consists of a series of bit string specifiers representing an image that has been compressed using run length encoding For example bitmap fonts can be converted into this format to reduce memory requirements for font storage A scanline table can also be used to efficiently represent line art and filled polygon shapes Each bit string specifier describes a displacement along with a run length encoded definition of a graphics operation for the RGP to perform on a single scanline The MC68322 supports three different sizes of bit string specifier formats 16 32 and 48 bit The smaller formats help to reduce memory requirements when short
334. ts Write 7 0 Valid Data Bits Write 7 0 Valid Data Bits Write 7 0 Valid Data Bits Write 15 8 Valid Data Bits Write 15 8 NOTE Denotes That These Conditions Are A Result Of Current Implementation And May Not Appear On Future Devices For On The Product Go to www freescale com Freescale Semiconductor Inc n Une 2 0 INTERNAL INTERRUPT PRIORITY LEVEL Output These three active low outputs indicate the encoded priority level of the device requesting an interrupt Level 7 is the highest priority while level 0 indicates that no interrupts are requested Level 7 cannot be masked The least significant bit is provided in _IPLO and the most significant bit is contained in IPL2 Typically these signals are connected directly to the MC68000 ICE 2 1 INTERNAL FUNCTION CODE Input These function code input signals indicate the processing mode user or supervisor and the cycle type currently being executed see Table A 3 The information indicated by the function code outputs is valid whenever AS is active The function code signals are internal signals used to decode an interrupt acknowledge bus cycle Typically these signals are connected directly to the MC68000 ICE Table A 3 Function Code Outputs OUTPUT CYCLE TIME E Um We tw _ Undefined Reserved i Ww um men i Ww High Supervisor Data Supe
335. tware interrupt event register s SET field Writing a 1 to Bit O of the SET field generates a level 1 interrupt Bit 1 a level 2 and so on The EVENT field reflects the state of the pending software interrupt Software interrupts can be set at any time and multiple interrupts can be set at the same time if needed However keep in mind that setting an interrupt that has already been set will have no effect Software interrupts are cleared by writing the EVENT field Each bit corresponds to one of the seven software interrupts Writing a 1 to a bit position will clear that software interrupt while a zero in a bit position has no effect For Bit O writing a 1 clears a level 1 interrupt for Bit 6 writing a 1 clears a level 2 interrupt and so on The interrupt service routine must clear its interrupt to avoid another interrupt when the routine completes For On This Product Go to www freescale com Freescale Semiconductor senis Uox scq ce pi tui ell RR EAR The MC68322 completely decodes the address map and generates an internal DTACK If the core presents an address that does not match any of the programmed addresses for the modules none of the modules will generate DTACK This condition is called an illegal address When an illegal address is detected the core interface asserts an internal DTACK and sets a level 7 interrupt to indicate an error condition The software interrupt event register s CIA bit is then set
336. uations causes only a portion of the expanded source frame to be applied to the destination When used in combination with XOFF and YOFF clipping can be affected at any or all extents of the expanded source bitmap The SA parameter defines the unexpanded source bitmap bit address It must point to the upper left corner of the bitmap The warp of the bitmap is set by the SW parameter This value is added to SA to locate the beginning of each successive scanline Note that the source warp set by the SET SBMAP graphic order has no effect on this graphic order For Mort ON oduct to www freescale com _ Freescale Semiconductor Inc MAP wires XOFF XMUL parameter is divided into two fields The least significant four bits contain the XMUL field which specifies the factor used to scale the unexpanded source bitmap in the X dimension XMUL must equal a specific value from 0 15 which represents a scaling factor of 1 16 Only certain scaling factors are supported as defined in Table 13 3 Values other than those listed are ignored and no X scaling is performed The XOFF field occupies the four most significant bits and indicates the number of bits to be clipped at the left edge of the expanded source bitmap XOFF ranges from 0 XMUL If XOFF is zero no clipping occurs at the left extent but if itis non zero XOFF number of bits in the left edge of the expanded bitmap are skipped and the
337. uctor Inc This section summarizes the memory mapped registers for the MC68322 The following table contains the name of the register an image of the register in memory with all of its associated fields the address of the register at startup the register s encoding at startup and the page number where the register is described 7 Note All shaded areas are reserved for future use and should always be written as Zero Table C 1 Memory Mapped Register Set MEMORY MAP VALUE AT RESET Pee 6 5 4 3 2 SS mon evre CSRO SIZE BASE ADDRESS 27 18 OOFFFO000 XX011000 00000000 WHLD WSET WACC RHLD RSET RACC OOFFF002 11001111 11001111 CSR1 SIZE BASE ADDRESS A27 A18 OOFFFO10 XX000000 00000000 WHLD WSET WACC RHLD RSET RACC 12 00000000 00000000 CSR2 SIZE BASE ADDRESS 27 18 OOFFF020 XX000000 00000000 WHLD WSET WACC RHLD RSET RACC OOFFFO22 00000000 00000000 CSR3 SIZE BASE ADDRESS 27 18 OOFFF030 XX000000 00000000 WHLD WSET RHLD RSET RACC OOFFF032 00000000 00000000 CSR4 SIZE BASE ADDRESS A27 A18 OOFFF040 XX000000 00000000 WHLD WSET RHLD RSET RACC OOFFF042 00000000 00000000 CSR5 SIZE BASE ADDRESS 27 18 OOFFF050 XX000000 00000000 WHLD WSET WACC RHLD RSET RACC 00 052 00000000 00000000
338. uit emulation ICE device and interface board for the MC68322 A special in circuit emulation board out package is available to provide a full featured emulation device while using standard M68000 emulators The ICE device uses a 208 pin grid array PGA package instead of the production version 160 pin plastic quad flat pack PQFP These extra pins which connect to the MC68322 s ICE device interface between the logic board containing a MC68322 PQFP and a standard MC68000 ICE The ICE interface contains a PGA connector for the logic board the MC68322 ICE a small amount of logic and a connector for an MC68000 ICE with some minor modifications A 1 ICE INTERFACE SIGNALS The following pins are used to connect the MC68322 to an ICE The ICE bond out is for engineering use only and should not be used in production The ICE option aids in the reuse of existing emulators for standard M68000 Family processors Some of these signals are dedicated to this interface and only appear on the ICE bond out package In addition some of these signals are used by the processor bus and an external bus master interface The direction of the pins is from the perspective of the MC68322 Table A 1 lists a summary of the ICE interface signals Table A 1 ICE Interface Signal Summary mm om ome ___ te imm ma AVEC Low No No ICE Processor Halt For 11093259
339. ure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part T freescale semiconductor For More Information On This Product Go to www freescale com Freescale Semiconductor ABOUT THIS MANUAL The MC68322 Integrated Printer Processor User s Manual contains information about the programming capabilities registers and overall operation of the MC68322 device CONVENTIONS The following conventions should help you navigate through this manual Anything that is not on this list is in plain text Signals pins lines and bit names appear in uppercase text Register acronyms appear in uppercase text but their full names are in lowercase Cross references appear in initial cap bold text Instructions appear in lowercase bold text All acronyms and mnemonics are defined the first time they a
340. us is used to exchange data between an external host computer and the MC68322 SELECTIN Parallel Port Select In This input signal is used by the parallel port interface to request on line status information STROBE Data Strobe This input signal indicates when valid data is present on the parallel port data bus AUTOFD Parallel Port Autofeed This input signal indicates autofeed control INIT Initialization Input This input signal is used to initialize parallel port input control ACK Parallel Port Acknowledge This output signal indicates that a transfer on the parallel port data bus is complete BUSY Parallel Port Busy This output signal indicates that the parallel port is busy SELECT Parallel Port Selected This output signal indicates that the device on the parallel port is on line or off line PERROR Parallel Port Error This output signal indicates that a problem exists with the paper in the printer It could mean that the printer has a paper jam or is out of paper FAULT Parallel Port Fault This output signal indicates that an error condition exists with the printer It could mean that the printer is out of toner or has been taken offline For On The Product Go to www freescale com Freescale Semiconductor SECTION 3 THE CORE MC68322 has an embedded 000 core that controls its operation The full architecture provides for 32 bit address and data register operations via t
341. utine for that exception executes This rule does not apply to the reset exception Its handler is executed first even though it has the highest priority because the reset operation clears all other exceptions For On This Product Go to www freescale com Freescale Semiconductor Inc vau Ut acce Caio eus 5 4 3 Exception Bus Cycles Because the MC68322 has a self contained core all addresses generated during bus cycles should decode to an internal register chip select bank or DRAM In the event that an undefined memory location is accessed a core illegal address interrupt event is posted and generates an interrupt if enabled Therefore an external BERR is not required All vectors in the exception vector table should be initialized including the address error exception The core could have the stack pointer set to an odd byte boundary which would result in an address error exception 5 5 MODULE SOFT RESET REGISTER The module soft reset register MSRR contains four write only bit fields that are used to independently initialize a corresponding module to a known state Figure 5 9 illustrates the MSRR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Figure 5 7 Module Soft Reset Register The GDR and PDR bits when set reset the GDMA and PDMA respectively These two bits provide for a recovery from an addressing error or any other error that causes the
342. vel sensitive interrupt is received This bit is also forced clear if the MODEx field is set for edge sensitive interrupts 10 or 11 When an external interrupt occurs REQx is set and SENx is automatically cleared Because a level sensitive interrupt may not change caution must be taken so that the core is not constantly interrupted It is recommended that an external interrupt be disabled before the SENx field in the external interrupt register is initialized by the software For On The Product Go to www freescale com Freescale Semiconductor SERE MARET aeo C ou etus 5 3 TIMER MODULE For the operating software to monitor time the MC68322 provides a timer that continuously posts an interrupt event to the core at regular intervals Like the other modules of the MC68322 the timer runs independent of the core even though its interval can be changed by the core at any time A timer operation is initiated by a write to the interval field in the timer register At 16MHz the width of the timer register provides an interrupt frequency range from 125ns to more than one second Typically this register is only set once during software initialization to produce interrupts every 50ms Figure 5 3 illustrates the timer register 15 14 13 12 11 410 9 8 TIMER INTERVAL HIGH BYTE OOFFF602 TIMER INTERVAL LOW WORD rm 15 14 13 12 11 10 9 8 7 6 5 4 3 2
343. wn host situation The powered down host situation exists when the host computer is turned off while the printer is still powered up or vice versa The resistors help to avoid damage to the printer or host computer in the event that this situation exists for extended amounts of time CENT36 STROBE 1 PDO 2 PD1 3 nb i i 20 PD3 5 5 4 PD5 7 PD6 8 PD7 330 BUSY PD5 PERROR YN SELECT 3502 INIT AUTOFD FAULT LOGIC GND LOGIC GND AUX2 5V SELECTIN PD7 INIT AUTOFD SELECTIN Figure B 9 Parallel Port Connector Interface For On The Product Go to www freescale com Freescale Semiconductor rAMMUVuuvim B 8 CONFIGURING THE GENERIC PRINT ENGINE INTERFACE The print engine interface requires a minimal amount of external logic to connect to most print engines Due to the different front panel interfaces available from print engine manufactures the MC68322 may require an external latch or two as demonstrated here However the primary handshake and video signals can be connected directly to the print engine in most cases Figure B 10 illustrates the print engine interface Notice that the external 555 timer can be eliminated if the BG signal is used in its alternate function see Appendix D Alternate Pin Functions 5V VIDEO CONNECTOR 5V FRONT PANEL A CONN26 A e BD PPRDY B2 gt RDY T
344. writes the scanline graphic order to update most of its parameters The BAND number is incremented or decremented when the B2T flag is set DA and HA are written back corresponding to the pixel following the last run rendered or when the B2T flag is set the pixel preceding the next bit string specifier s run and HYR is written back with the number of remaining scanlines in the halftone frame to be transferred Last HTTA and SLTA point to the next specifier to be executed when the rest of the scanline table is rendered to the next band The contents of the scanline and companion halftone tables are left unchanged after a band fault Related Graphic Orders SET_BOOL_HD SET_HTBMAP SET_BBMAP For Mort RSE ON ANA oduct Go to www freescale com Freescale Semiconductor Inc Puy SCANLINE COMPANION DESTINATION TABLE HALFTONE TABLE BANDED BITMAP SLTA EN HTTA EN DWB lt gt FIRST SPECIFIERS SPECIFIERS _ EM HALFTONE BITMAP EOBPA HW BOOL_HD USED COMBINE FRAMES a Tu Figure 13 28 Halftone Destination Scanline Transfer to Banded Bitmap 0 Page SCANLINE COMPANION DESTINATION TABLE HALFTONE TABLE BANDED BITMAP EOBPA HALFTONE BITSTRING SPECIFIERS SPECIFIERS O BOOL_HD aE USED TO 5 SLTA lt DWB gt HALFTONE BITMAP
345. x or PLL mode and LSYNC in PLL mode only are asynchronous inputs and are synchronized internally by the MC68322 They require no setup or hold time to be recognized for proper operation However to guarantee recognition of an input at a certain edge of CLK2 the input must satisfy the hold requirement 4 speci cation is relativ e to the edge of VCLK selected by the VCP bit in the PVCCR LSYNC is a synchronous input when the PVC operates in 1x mode 6 minimum pulse widths for FSYNC and LSYNC depend on the video dot rate and is speci ed in video dot per iods dots In 1x mode the video dot period is equal to the VCLK period In PLL mode the video dot period is determined by the VCLK period and the con gur ation of the PLL For More MES 822 ae BM oduct to www freescale com Freescale Semiconductor Inc l nvr WEA 15731 975 CLK2 CBSY CCLK CMD STS Figure 14 20 Print Engine Interface Input AC Timing CCLK CMDISTS Figure 14 21 Print Engine Interface Output AC Timing GA VCLK Figure 14 22 Video Clock AC Timing For On The Product Go to www freescale com Freescale Semiconductor MWR UNM WHA ULV ILUV VCLK 43 43 LSYNC 7722 7 PLL MODE gt LSYNC lt 43 Figure 14 23 PVC AC Timing qr O
346. y addresses Once mapped to physical memory space the graphic transfer can begin The value for PSUBL can be computed from the physical address of the current band buffer and the logical address of the top most pixel in the band PSUBL buffer address top most pixel address PHYSICAL LOGICAL Given PSUBL the graphics unit can translate logical destination addresses to and from physical address space using the following calculations Map logical into physical DA PSUBL PSUBL Map physical into logical DA The parameter is used to detect band faults The address must specify the first bit outside the banded bitmap buffer As a graphic transfer proceeds the current destination address a physical address is compared against EOBPA If it is found to be greater than or equal to EOBPA or when the B2T flag is set less than or equal to a band fault occurs The transfer is prematurely terminated the current destination address is translated back into logical space and the logical address is written along with accompanying parameters back into the display list Related Graphic Orders BLT2BB D BLT2BB SD BLT2BB SHD BLT2BB XD BLT2BB XHD SL2BB D SL2BB HD For Mort ON oduct to www freescale com Freescale Semiconductor Inc MAT wires weet DESTINATION BANDED BITMAP lt
347. ynchronized internally by the GDMA interface it requires no setup or hold time to be recognized for proper operation However to guarantee recognition of the input at a certain edge of CLK DREQ must satisfy a setup requirement that it remain active for at least two consecutive CLK rising edges to be detected by the GDMA interface 2 Setup and hold requirements must be met to prevent the start of the next GDMA cycle If back to back GDMA cycles are preferred DREQ must stay active and detected as a low at this time Figure 8 5 GDMA 68322 Bus Read Or Write Cycle The GDMA can be mapped to any chip select bank To optimize DMA access timing the chip select DMA timing register is provided See Section 6 System Integration Module for more information This register provides a separate chip select bank timing that is specific to a DMA access During a GDMA access to a chip select bank the internal DACK signal has a timing that is identical to the CSx The DS bit in the GDMA configuration register controls the assertion of the CSx with DACK during a GDMA access 8 6 3 GDMA DRAM Bus Read and Write Cycles The DMA interface is one of five interfaces that internally arbitrates for control of the DRAM bus A GDMA DRAM bus read cycle request is generated when the internal data latch can accept new data This can occur either when the DMA interface is first started or after data is transferred to a destination A DRAM bus write cycle request
348. ysical bit address SA must point to the upper left corner of the source frame when the B2T flag is clear and to the lower left corner of the source frame when the B2T flag is set When a band fault is detected the MC68322 rewrites the graphic order to update some of the parameters The BAND number is incremented or decremented when the B2T flag is set DA and SA are repositioned to the starting pixel of the respective frame to be processed in the next band and FH is written back with the number of remaining scanlines in the frame to be transferred Related Graphic Orders SET BOOL SD SET BBMAP SET SBMAP For Mort ON oduct to www freescale com Freescale Semiconductor Inc MAT wires SOURCE BITMAP DESTINATION BANDED BITMAP e SW gt lt DWB SA A BOOL_SD USED TO COMBINE FRAMES EOBPA Figure 13 5 Source Destination bitBLT to Banded Bitmap 0 Page SOURCE BITMAP DESTINATION BANDED BITMAP lt Sw gt lt gt BOOL_SD USED TO COMBINE FRAMES lt DWB Figure 13 6 Source Destination bitBLT to Banded Bitmap 180 Page For Mort 160322 On This Product Go to www freescale com gt Freescale Semiconductor MAT wires BLT2BB SHD Source Halftone Destination bitBLT to Banded Bitmap PARAMETERS s DESCRIPTION Byte BLT2B
349. yte When the next data byte arrives BUSY remains low for the entire decompression period In the MC68322 depending on internal bus utilization a replication factor of 128 could result in BUSY remaining low for 1 to 2 ms while STROBE remains low As decompression occurs the PPI generates PDMA requests and data received interrupts events in exactly the same manner as when it receives uncompressed data When the run length counter decrements to zero the last PPIR DATA field read results in the BUSY being driven high and then low following the rising edge of STROBE The RLD bit is also cleared at this time After a run length command is received the next byte usually is a data byte If the next byte is also a run length then this new run length is used If the next byte is a channel address then a command received interrupt event is posted the state machine continues waiting for the next data byte If the PPCR s MODE field is changed after the run length command was received but before the data byte was received then RLD remains set When ECP with RLE is enabled again decompression will begin when the data byte is received If MODE is changed while decompression is occurring RLD is set and the data byte was received the decompression continues until completion If decompression must be immediately aborted RST should be issued in the PPCR The PPCR s FLL bit is set when the run length is received and immediately cleared when th

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