Using Synopsys VCS to connect a Company`s SystemC Verification
Contents
1. simulation vlogan cpp CPP ntb_opts uvm 1 1 sverilog vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ubus_if sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ubus_transfer_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ifs_command_monitor_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ubus_master_driver_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ubus_master_monitor_pkg VCS sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ubus_master_sequencer_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ubus_master_seq_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm 1 1 N incdir UVMC_HOME src connect sv UVMC_HOME src connect sv uvmc_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ifs_command_master_agent_pkg sv vlogan cpp CPP sverilog incdirt VCS_HOME etc uvm tb_uvm ubus_example_master_seq_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm tb_uvm ifs_command_master_agent_pkg sv vlogan cpp CPP sverilog incdir VCS_HOME etc uvm 1 1 tb_uvm uvm_master_module sv vlogan cpp CPP cc CC sysc sverilog sc_model sv_uvm_master sc_portmap masterVerilogToSystemCport map N t incdir VCS_HOME etc uvm 1 1 tb_uvm uvm_master_module sv vlogan cpp CPP cc2. trans command_from_TLM_sc endtask peek endclass ifs_command_monitor endpackage ifs_command_monitor_pkg
3. Appendix B contains the compile and run script used to execute the SystemC UVMC SystemVerilog mixed language simulation example 2 Bus Arbiter Example as Test Case We chose a switched bus arbiter implementation as a test case for this work It connects a configurable number of bus masters with a configurable number of memory bus slaves for read or write accesses refer to Figure 2 The design is simple enough to be understandable within short time and allows quick implementation with little risk of introducing bugs We used it for several mixed language simulations evaluations in the past and it is now available in VHDL Verilog and SC together with matching models of masters slaves and test bench setups In the scope of this work we completed this collection with a UVM SV test environment Uarra rr n L fin r nn JEE 86 JEE Figure 2 Switched bus arbiter example as DUV for the experiment of this work 3 Integrated Functional Verification Script Environment and Bus Arbiter Example A first introduction into Integrated Functional Verification Script Environment IFS is to be found in 2 and 3 IFS is tailored to the domain of automotive electronics system design and specifically satisfies the needs of engineers and system integrators for efficient test implementation IFS is a SC based library that compiles and simulates with a
4. German Federal Ministry for Education and Research Bundesministerium fiir Bildung und Forschung BMBF under the grant O1IS13022 project EffektiV The content of this publication lies within the responsibility of the authors 7 Literature 1 2 3 4 5 6 7 8 9 F Poppen M Trunzer J H Oetjens Connecting a Company s Verification Methodology to Standard Concepts of UVM DVCon Europe 2014 P Jores P Borthen R D lling H W Groth T Halfmann S Kern M Lampp M Olbrich M Pfost R Popp D Pronath P Rotter S Steinhorst G Wachutka Y Wang and S Weber Verifikation analoger Schaltungen Kurztitel VeronA Schlussbericht zur BMBF Forderinitiative IK T2020 2009 R Lissel and J Gerlach Introducing new verification methods into a company s design flow an industrial user s point of view DATE 2007 K Hylla J H Oetjens and W Nebel Using SystemC for an Extended MATLAB Simulink Verification Flow FDL 2008 R G rgen H Kleen J H Oetjens P Jores and W Nebel SystemC Based Verification of Complex Heterogeneous Systems Cyber Physical Systems Enabling Multi Nature Systems CPMNS 2012 J H Oetjens N Bannow M Becker O Bringmann A Burger M Chaari S Chakraborty R Drechsler W Ecker K Griittner T Kruse C Kuznik H M Le A Mauderer W Miiller D Miiller Gritschneder F Poppen H Post S Reiter W Rosenstie
5. UVM_MEDIUM Here we decode the TLM to generate the correct sequence_item ii from it case t cmd WRITE write_transaction t parameters READ read_transaction t parameters endcase this end_tr command_from_TLM_sc Inform task peek about his gt address_phase_grabbed endtask function void write_transaction string parameters if parameters size 2 begin uvm_info get_type_name ifs command_monitor write_transaction wrong number of parameters for write transaction UVM_MEDIUM end else begin command_from_TLM_sc read_write WRITE command_from_TLM_sc addr parameters 0 atoi command_from_TLM_sc data parameters 1 atoi end endfunction write_transaction function void read_transaction string parameters j if parameters size 2 begin uvm_info get_type_name ifs command_monitor read_transaction wrong number of parameters for read transaction UVM_MEDIUM end else begin command_from_TLM_sc read_write READ command_from_TLM_sc addr parameters 0 atoi command_from_TLM_sc data parameters 1 atoi end endfunction read_transaction task peek output ubus_transfer trans address_phase_grabbed uvm_info get_type_name sformatf ifs _command_monitor peek Informing driver to drive cmd d addr d data d command_from_TLM_sc read_write command_from_TLM_sc addr command_from_TLM_sc data UVM_MEDIUM
6. char sc_signa sc_signa sc_signa sc_signa sc_signa lt bool gt sig clk lt bool gt sig_rst lt bool gt sig_gnt lt int gt sig_rdata lt bool gt sig_ack sc_signa sc_signa sc_signa sc_signa sc_signa lt bool gt sig_req lt bool gt sig_rreq lt bool gt sig_wreq lt int gt sig_addr lt int gt sig_wdata Parameters SC_SNPS hdl_param lt std string gt str_param SC_HAS_PROCESS sv_uvm_master sv_uvm_master sc_module_name modelName sc_module modelName sig_clk new sc_signal lt bool gt sig_clk sig_rst new sc_signal lt bool gt sig_rst sig_gnt new sc_signal lt bool gt sig_gnt sig_rdata new sc_signal lt int gt sig_ack new sc_signal lt bool gt HDL_PARAM str_param MA sig_req sig_rreq sig_wreq sig_addr sig_wdata new sc_signal lt bool gt s new sc_signal lt bool gt sig new sc_signal lt bool gt s new sc_signal lt int gt s new sc_signal lt int gt sig_wdata HDL_MODULE Sv_uvm_master name SC_METHOD sv_uvm_master_clk_action basename sensitive lt lt clk snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_rst_action sensitive lt lt rst snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_gnt_action sensitive lt lt gnt snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_rdata_action sensitive lt lt rdata snps_sysc_mark_last_c
7. components are instantiable in our SystemC SC based IFS 3 test environment using UVM Connect to verify designs specified in VHDL AMS SystemC AMS Verilog AMS or Matlab Simulink 4 There we demonstrated that our approach and UVMC do not depend on proprietary technology and presented the applicability for mixed language simulators from Mentor and Cadence This paper is to extend the claim to cover Synopsys vcs mx as another mixed language simulation environment we make use of SystemVerilog UVM inside a SystemC test bench connected with UVMC using Synopsys simulator vcs mx 1 Introduction Automotive electronic today shows a constant increase in performance number of subsystems and their interoperability to compose most complex heterogeneous systems Guaranteeing properties of safety sustainability and comfort is a challenge which requires consistent verification of quality along every stage of the development process At the level of integrated circuit design EDA industry promotes the Universal Verification Methodology UVM 9 Such relatively new standards need to find their way into often in house verification concepts that have been out long before UVM and SystemVerilog SV Those concepts distinguish themselves from standard concepts in that they are more tailored to relevant use scenarios and efficient usage in special contexts Unfortunately when using non standard verification methodologies one cannot access and profit
8. sc_out lt bool gt sc_out lt bool gt sc_out lt int gt uvm_master_clk uvm_master_rst uvm_master_req uvm_master_gnt uvm_master_rreq uvm_master_wreq uvm_master_addr bil it tf ff it error Cannot compile for MTI_SYSTEMC and NC_SYSTEMC simultaniously endif elif defined NC_SYSTEMC ifndef MTI_SYSTEMC ifndef VCS class foreign_module_master public ncesc_foreign_module reset master request grant from arbiter read request write request address sc_out lt int gt uvm_master_wdata write data sc_in lt int gt uvm_master_rdata read data sc_in lt bool gt uvm_master_ack acknowledge foreign_module_master sc_module_name nm ncesc_foreign_module nm str_param nm hdl_instance hdl_name uvm_master_clk clk uvm_master_rst rst uvm_master_req reg uvm_master_gnt gnt uvm_master_rreq uvm_master_wreq req 1 const char hdl_name foreign module lt lt uvm_master_addr addr uvm_master_wdata wdata uvm_master_rdata rdata uvm_master_ack ack 2 Kk kk es cout lt lt hdl_instance lt lt endl ncsc_set_hdl_param str_param foreign_module_master CTOR str_param const char hdl_name const return hdl_instance foreign_module_master private std string str_param const char hdl_instance Elaborating foreign else error Cannot compile for NC_SYSTEMC and VCS simultaniousl
9. string ack_string name ack_string _R_ack alterString ack_string basename hdl_connect_v sig_ack ack_string c_str HDL_OUTPUT HDL_vcs std string req_string name alterString req_string basename req string req hdl_connect_v sig_req req_string c_str HDL_ std string rreq_string name alterString rreq_string basename rreq string rreq hdl_connect_v sig_rreq rreq_string c_str HDL_INPUT HDL_vcs std string wreq_string name alterString wreq_string basename wreq_string hdl_connect_v sig_wreq wreq_string c_str HDL_INPUT HDL_vcs std string addr_string name alterString addr_string basename addr_string addr hdl_connect_v sig_addr addr_string c_str HDL_INPUT HDL_vcs std string wdata_string name alterString wdata_string basename wdata_string wdata hdl_connect_v sig_wdata wdata_string c_str HDL_INPUT HDL_vcs NPUT HDL_vcs E vcsModel VcsDesign getDesignInstance gt addModel sv_uw vcsInstance vcsModel gt addInstance name vcsInstance gt setScObj this vcsInstance gt setNames sv_uv ter master name basename vesInstance gt addPort clk VcsPort INPUT_PORT 1 0 vesInstance gt addPort rst VcsPort INPUT_PORT 1 0 vesInstance gt addPort gnt VcsPort INPUT_PORT 1 0 vesInstance gt addPort rdata Vc
10. uvm_master_req vcs_uvm_master gt rreg uvm_master_rreq vcs_uvm_master gt wreg uvm_master_wreq vcs_uvm_master gt addr uvm_master_addr vcs_uvm_master gt wdata uvm_master_wdata foreign_module_master sv_uvm_master vcs_uvm_master F else error Cannot compile for VCS and NC_SYSTEMC simultaniously endif else error Cannot compile for VCS and MTI_SYSTEMC simultaniously endif else error Must select one of the three simulation environments VCS vcs MTI_SYSTEMC NC_SYSTEMC ncsim endif module Questa lt lt or Wrapper generated by Synopsys tool SystemC wrapper header for DKI connect HDL model import This file must be compiled with other SystemC files ifndef sv_uvm_master_h_ define sv_uvm_master_h_ include systemc h include lt string h gt include cosim bf hdl_connect_v h include cosim bf VcsDesign h include cosim bf snps_hdl_param h extern C unsigned int Msv_uvm master_l unsigned int std string BF_get_hdl_ name SC_CORE sc object wom extern struct sv_uvm_master yvcsModel VcsModel sc_module VcesInstance vcsInstance Input ports sc_in lt bool gt clk sc_in lt bool gt rst sc_in lt bool gt gnt sc_in lt int gt rdata sc_in lt bool gt ack Output ports sc_out lt bool gt sc_out lt bool gt sc_out lt bool gt sc_out lt int gt sc_out lt int gt req rreq wreq addr wdata
11. 17 C 2007 2013 Cadence Design Systems Inc 18 C 2006 2013 Synopsys Inc 19 C 2011 2013 Cypress Semiconductor Corp 20 3 usis Hoesen SSS Sti SCS Sse Seis Sea St SS Se eee e 21 kkkkeeeKEX Wrap uvm_master initialiseModule Raising objection for UVM phase run 222 see Sass Sa aS Se SS SSS SS SS SSS See SS oS SoS 23 UVMC 2 2 24 C 2009 2012 Mentor Graphics Corporation 25 Sesser a ee See Sts Goes See Sa Sieh See Scie 26 Registering SV side sc_wrap MS1 ifs_ monitor in and lookup string sc_wrap_MS1 for later connection with SC 27 UVM INFO 0 ns reporter RNTST Running test The wrapper raises an objection for the UVM run phase line 21 UVMC connects the SC and UVM TLM ports by referring to their label line 28 In line 34 the execute next command loop receives a msi write 100 98 user defined command from the IFS controller s CF and the wrapper s write method creates and sends a proper TLM message In line 35 the wrapper UVM connector receives the TLM message and creates a sequence item 36 The UVM agent s driver consumes the sequence item and applies according signal events to the DUV line 37 The SC slave TBM responds to the signal events line 38 28 Connected SC side bus_arbiter_tb MS1 port_10 to SV side sc_wrap_ MS1 ifs_monitor in 29 UVM_INFO tb_uvm ubus example master _seq_ pkg sv 134 0 ns sc_wrap_MS1 sequencere master_memory_seq master _memory seq master _memory_seq star
12. CC sysc sverilog sc_model sv_uvm_test incdir VCS_HOME etc uvm 1 1 tb_uvm uvm_test_module sv ves cpp CPP cc CC cflags g sysc sverilog sysc scv sysc deltasync N ntb_opts uvm 1 1 debug_all timescale lps l1ps N m32 cflags DVCS cflags DUVMC_NO_COUT_STL_LIST cflags DSC_INCLUDE_DYNAMIC_PROCESSES cflags cflags cflags cflags cflags cflags cflags DINCLUDE_U 1I VCS_HO 1I VCS_HO 1 UVMC_HO IS IFS_HO L Ztib says VM_AGENT cflags I cflags I VCS_HOME include scv 2 0 E etc systemc tlm include tlm E etc systemc tlm include tlm tlm_utils ME src connect sc cflags I IFS_HOME Include N E Source spirit 1 6 1 cflags I IFS_HOME Source spirit 1 6 1 miniboost N temc cflags I rtl_systemc S UVMC_HOME src connect sc uvme cpp N IFS_HOME Source cpp rtl_systemc arbiter cpp tb_systemc c tb_systemc ictrl cpp tb_systemc master cpp tb_systemc s tb_systemc wrap_uvm_master cpp N tb_systemc main cpp simv 10 Appen dix C lk_ifs cpp lave cpp Wrapper UVM connector is a UVM component derived from the UVM monitor class It receives the TLM message and creates an according sequence item The sequence item is forwarded through the UVM sequencer to the UVM driver package ifs_command_monitor_pkg import uvm_pkg include uvm_macros svh import ubus_transfer_pkg ubus_transfer import ubus_transfer_
13. Using Synopsys VCS to connect a Company s SystemC Verification Methodology to Standard Concepts of UVM Frank Poppen Marco Trunzer Jan Hendrik Oetjens OFFIS Institute Robert Bosch GmbH Robert Bosch GmbH for Information Technology Tel 49 441 9722 230 Tel 49 7121 35 2981 Tel 49 7121 35 4684 frank poppen offis de Marco Trunzer de bosch com Jan Hendrik Oetjens de bosch com Over the last decades intelligent electronics in heterogeneous systems improved all aspects of everyone s daily life An advantage a modern civilization cannot ignore The increasing complexity of the electronic components though makes us dependent on solving a growing design verification challenge Especially knowing that safety relevant functionality as in automotive driving is part of this development Standardized as well as proprietary concepts languages and tools line up for the task 6 Unfortunately there is no such thing as one size fits all in this Verification engineers need to choose and combine what fits best for the company the design team and application domain They create company s verification strategies with deep roots into the design process Changes to the strategy need to be done carefully and incrementally to ensure continued productivity This work is a twin of the previously published paper 1 and a copy of that in big parts enhanced by more code examples in the Appendixes A to C In 1 we compared concepts of UVM 9 and showed how UVM
14. a SC wrapper instead The methodology is described in the mixed language simulators user guide 10 11 and 12 and has two advantages Firstly the agent s driver receives full pin level access to the DUV s interface Secondly the test bench architecture is defined in the SC source code only If we change the test bench configuration of the bus arbiter for more masters only the SC sc_main needs to be modified to hook up additional wrapper modules Each wrapper instantiates the required UVM code by itself The verification engineer does not need to touch or even know UVM SV source code UVMC TLM BRM ee 5 X 3 gt slave0 wrapper as_pot SystemVerilog module Y Instance target_socket Wrapper UVM Connector uvm_root C init objection 3 t UVM Agent af ubus_example_tbo final bi i 2 bus execNextCmd wii a tr m ml slave2 arbiter gt VIF UVM UVM sequencer J UVMC_B_INITIATOR_SOCKET_FO driver a T A sc_main wa masteri O lt UVM S bus_arbiter_tb slave3 le master2 monitor N MS1 C gt l a m_UVM gt master3 w objector IM MS2 i z IM MS3 IM MS4 EE M SL1 in wrapper module using the foreign module interface Figure 5 SC instantiating UV Right side of Figure 5 shows a screenshot of an UVM agent instantiated inside SC using the elaborate_foreign_module hdl_name fun
15. ack_string R We alterString ack_string basename hdl_connect_v sig_ack ack_string c_str HDL_OUTPUT HDL_vcs std string req_string name alterString req_string basename req string req hdl_connect_v sig_req req_string c_str HDL_INPUT HDL_vcs std string rreq_string name alterString rreq_string basename rreq string rreq hdl_connect_v sig_rreq rreq_string c_str HDL_INPUT HDL_vcs std string wreq_string name alterString wreq_string basename wreq_string wreq hdl_connect_v sig_wreq wreq_string c_str HDL_INPUT HDL_vcs std string addr_string name alterString addr_string basename addr_string addr hdl_connect_v sig_addr addr_string c_str HDL_INPUT HDL_vcs std string wdata_string name alterString wdata_string basename wdata_string wdata hdl_connect_v sig_wdata wdata_string c_str HDL_INPUT HDL_vcs vcsModel VcsDesign getDesignInstance gt addModel Sv_uvm_master vesInstance vcsModel gt addiInstance name vcsInstance gt setScObj this vcsiInstance gt setNames sv_uvm_master name basename vesInstance gt addPort clk VcsPort INPUT_PORT 1 0 vesInstance gt addPort rst VcsPort NPUT_PORT 1 0 vesInstance gt addPort gnt VcsPort INPUT_PORT 1 0 vesInstance gt addPort rdata VcsPort INPUT_PORT 32 0 vesInstance gt addP
16. ating a SV UVM agent inside a TBM wrapper and connecting the two using UVMC We removed repeating lines blank lines and lines with little information to shorten the trace Lines 1 to 10 document the elaboration phase alse kekKKKEKKK Wrap uvm_master CTOR Connecting TLM port 2 Connecting an SC side proxy chan for bus arbiter _tb MSl port_10 with lookup string sc_wrap_MS1 for later connection with SV 3 kekKKEAKKKERR vm test CTOR instantiating UVMC test 4 INFO 0 s bus_arbiter_tb MS1 Registered module bus_arbiter_ tb MS1 5 also MS2 to MS4 6 INFO 0 s bus_arbiter_tb SL1 Registered module bus_arbiter tb SL1 7 also SL2 to SL4 8 INFO 0 s bus_arbiter_tb CLK Registered module bus_arbiter_tb CLK 9 INFO 0 s Loading script control cmd 10 INFO 0 s Finished loading Run of simulation starts in line 11 where UVM begins to traverse through its simulation phases build connect and finally entering the main run phase with line 28 Connecting the TLM ports between SC and UVM is established in two steps Firstly ports are created and labeled with a lookup string SC line 2 above UVM line 26 below 11 Chronologic VCS simulator copyright 1991 2014 12 Contains Synopsys proprietary information 13 Compiler version J 2014 12 1 Runtime version J 2014 12 1 Feb 20 11 15 2015 PA Derma SSE ae BS ae Se Se Si ee SS eS Se eae eee 15 UVM 1 1d Synopsys 16 C 2007 2013 Mentor Graphics Corporation
17. ctionality of Mentor Questa SC and UVM are interweaved with bare signal access between the two The left side of Figure 5 shows the implemented architecture of the experiment A wrapper TBM derived from the class IFS ModuleBase acts just like any other TBM with predefined commands and next command execution loop but fulfills three additional objectives Firstly the UVM agent is instantiated in the constructor of the wrapper yellow rectangle Instantiation implementation is proprietary to the chosen multi language simulation environment We evaluated Synopsys VCS HDL_MODULE 10 Mentor Graphics Questa simulator sc_foreign_module 11 and Cadence s Incisive ncsc_foreign_module 12 The concepts of the three simulators a very similar but still need individual coding Our source code for this is listed in Appendix A Secondly the wrapper implements a method to utilize UVMC s command API to set an objection for the UVM run phase The objection is mandatory as otherwise the UVM simulation of the single UVM agent would terminate right after start because of missing sequences and sequence items Thirdly the wrapper implements commands that are twins to the UVM agent s processable sequence items The following is a brief outline on the modus operandi e Start simulator elaborate SC and SV is instantiated inside SC e run 0 Starts execution of the SV phases build connect and the run phase e SC wrapper sets objection for the run phas
18. e SV will not leave run phase until removed e run all executes all TBMs execute next command loops Wrapper receives user defined command call from IFS controller s CF e Wrapper calls implementation method of user defined IFS command Method creates and sends TLM message via UVMC e Wrapper UVM connector is a UVM component derived from the UVM monitor class It receives the TLM message and creates an according sequence item The sequence item is forwarded through the UVM sequencer to the UVM driver e UVM Driver applies signal events to DUV s interface IFS command finished execution e Execute next command repeats until quit or last command is reached Wrapper removes UVM run phase objection by call to wrapper s finalize method Simulation ends The agent s original code for sequencer driver and monitor remains unchanged The IFS wrapper is fully reusable for future use in different environment configurations It is fully transparent to the IFS test developer who will not get into contact with UVM code behind the TBM wrapper 5 Report of Simulation Run We evaluated our approach with three tool setups The first setup consists of Mentor Graphics Questa 10 1c UVM 1 1b and UVMC v2 2 The second setup utilized Cadence Incisive 13 10 s005 and the third bases on Synopsy VCS MX vJ 2014 12 1 We believe that any setup complying with IEEE 1666 SC and IEEE 1800 SV should work The following is a full simulation run of SC IFS instanti
19. from the vast amount of resources available like third party verification Intellectual Property IP and skilled human resources On the other hand switching completely to UVM as a standard method means dispensing the already available in house verification IP and the benefits of a tailored solution Because of that even when there are good reasons to stay with an in house verification methodology it becomes necessary to interface to standard methodologies So like already stated in 2 an evolution of the verification method is more desirable than a radical revolution The methodology named IFS Integrated Functional verification Script environment was continuously enhanced from VHDL with VHDL AMS 2 to SC 3 Matlab Simulink 4 and now further on to SV and UVM Major aspects of the test bench architecture as defined by IFS can also be found in the established standard UVM that has its roots in the Open Verification Methodology OVM and the Verification Methodology Manual VMM Figure 1 matches basic concepts of both approaches that are directly comparable With removed details of UVM s concepts the IFS approach is less complex and simple to apply Moreover with VHDL AMS the IFS methodology already includes analog mixed signal AMS simulation at no additional cost including constraint random capabilities After an afternoon introduction analog designers and system integrators are able to use test benches and create command files for o
20. ing the CF SC code of test bench and TBM remains unchanged between different test runs removing recompilation and re elaboration from the verification process Additionally TBMs in VHDL and VHDL AMS are supported They are automatically connected to the SC IFS controller by no more than specifying a unique TBM command name for CF and a unique TBM ID number It is even possible to describe the test bench structure and interconnection in any HDL by using the standard mixed language capabilities of the simulators The left listing demonstrates a simple CF using predefined commands as well as user defined TBM commands Set Offset Set I Wait Write and Read of four bus masters accessing four memory slave modules through the DUV The right shows a simulation run with OSCI reference simulator CLK PERIOD 10 ns SystemC 2 3 0 ASI Nov 29 2013 14 57 17 CLK RESET 0 12 Copyright c 1996 2012 by all Contributors ALL RIGHTS RESERVED SYNC ALL NFO 0 s Loading script control cmd NFO 0 s Finished loading LK 0 s activate system clock of 10 ns LK 0 s reset gets active LK 120 ns reset gets passiv 120 ns L1 Config slave 1 11 120 ns ave_offset 300 L1 120 ns i 100 120 ns Config slave 2 12 120 ns ave_offset 200 20 ns int_wait_cycles 99 120 ns Config slave 3 20 ns ave_offset 100 20 ns int_wait_cycles 20 ns Config slave 4 ns set slave_offset 0 ns set int_wait_cycles ns Write Address ns Write Add
21. ion sensitive lt lt rdata snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_ack_action sensitive lt lt ack snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_req_action sensitive lt lt sig_req snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_rreq_action sensitive lt lt sig_rreq snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_wreq_action sensitive lt lt sig_wreq snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_addr_action sensitive lt lt sig_addr snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_wdata_action sensitive lt lt sig_wdata snps_sysc_mark_last_create_process_as_internal std string clk_string name clk_string _R_clk alterString clk_string basename hdl_connect_v sig_clk clk_string c_str HDL_OUTPUT HDL_vcs std string rst_string name rst_string _R_rst alterString rst_string basename hdl_connect_v sig_rst rst_string c_str HOL OUTPUT HDL ves std string gnt_string name gnt_string _R_gnt alterString gnt_string basename hdl_connect_v sig_gnt gnt_string c_str HDL_OUTPUT HDL_vcs std string rdata_string name rdata_string _R_rdata alterString rdata_string basename hdl_connect_v sig_rdata rdata_string c_str HDL_OUTPUT HDL wes std
22. l S Roth U Schlichtmann A von Schwerin B A Tabacaru and A Viehl Safety Evaluation of Automotive Electronics Using Virtual Prototypes State of the Art and Research Challenges Proceedings of the 51 Design Automation Conference DAC 2014 San Francisco CA USA M Barnasconi F Pecheux and T Vortler Advancing System Level Verification using UVM in SystemC Design and Verification Conference DVCon 2014 Adam Erickson Introducing UVM Connect at https verificationacademy com sessions introduction uvm connect Accellera Universal Verification Methodology UVM 1 1 User s Guide May 18 2011 10 Synopsys VCS MX VCS MXi User Guide J 2014 12 December 2014 11 Mentor Questa SIM User s Manual Including Support for Questa SV AFV 2012 12 Cadence SystemC Simulation User Guide 2012 8 App endix A The listing of Appendix A shows the source code of our TBM master wrapper which handles all three proprietary foreign language instantiation concepts of the three simulators Synopsys Mentor Questa Simulator define mr1_systemc and Cadence Incisive VCS define ves define NC_SYSTEMC Manually coded if defined MTI_SYSTEMC ifndef NC_SYSTEMC ifndef VCS class foreign_module_master t public c in cik sc_in lt bool gt sc_out lt bool gt sc_in lt bool gt sc_out lt bool gt sc_out lt bool gt sc_out lt int gt uvm_master_c
23. lk uvm_master_rst uvm_master_req uvm_master_gnt uvm_master_rreq uvm_master_wreq uvm_master_addr Gh eb td public sc_foreign_module reset master request grant from arbiter read request write request address sc_out lt int gt uvm_master_wdata write data sc_in lt int gt uvm_master_rdata read data sc_in lt bool gt uvm_master_ack acknowledge foreign_module_master sc_module_name nm sc_foreign_module nm uvm_master_clk c uvm_master_rst 1k j uvm_master_req req uvm_master_gnt gnt uvm_master_rreq rr uvm_master_wreq uvm master_addr uvm master_wdata a q ddr ata uvm_master_rdata rdata uvm_master_ack ack cout lt lt WERK k k k k KEK fc const char hdl_name gn_module_m LCYOR Y 3 Elaborating hdl_name lt lt endl paraml module name to take from worklib param2 number verilog module parameters param3 UVM name of module and TLM Port identifier else else SE E SE FE E E E E E std string tmp str_param N tmp nm tmp N const char generic_list 1 generic_list 0 elaborate_foreign_module hdl_name foreign_module_master wie strdup tmp c_str 1 generic_list error Cannot compile for MTI_SYSTEMC and VCS simultaniously endif public sc_in_clk sc_in lt bool gt sc_out lt bool gt sc_in lt bool gt
24. ny simulator complying with the IEEE 1666 SystemC standard Figure 3 depicts the setup of the bus arbiter example in an IFS environment bus arbiter VHDL or Verilog or SystemC Figure 3 IFS simulation environment for a bus arbiter test bench In a mixed language simulation environment the DUV s implementation could be any language like VHDL Verilog or SystemC as long as the DUV s interfaces are hooked up to IFS Test Bench Modules TBM A TBM acts as Bus Functional Model BFM and generates stimuli for the DUV All TBMs are derived from the class IFS_ ModuleBase which itself is derived from sc_module Therefore a TBM is a SC module enriched by predefined IFS commands print lt text gt wait lt time event gt sync lt TBMlist gt reportlevel lt severity gt notify lt event gt assign lt envVar gt quit and other TBM developers need to implement the BFM part of the behavior by user defined commands and register them with the IFS controller at runtime User defined commands are callable from the command file CF the same way as predefined commands Scheduled in parallel by the simulation kernel the TBMs each execute an endless loop in which they request the next command from the IFS controller s CF Execution is suspended on wait or sync TBMs terminate on reaching the last command or if the quit command is issued explicitly The concept allows the quick modification of test runs by exchanging or modify
25. ort ack VcsPort INPUT_PORT 1 0 vcesInstance gt addPort req VcsPort OUTPUT_PORT 1 0 vesInstance gt addPort rreq VcsPort OUTPUT_PORT 1 0 vesInstance gt addPort wreg VcsPor OUTPUT_PORT 1 0 vcesInstance gt addPort addr VcsPor OUTPUT_PORT 32 0 vcesInstance gt addPort wdata VcsPort OUTPUT_PORT 32 0 vcsInstance gt addParameter str_param VcsParam HDL_STRING MASTER sv_uvm_master sc_module_name modelName const std string amp str_param_ sc_module modelName HDL_PARAM str_param MASTER sig_clk new sc_signal lt bool gt sig_clk sig_rst new sc_signal lt bool gt sig_rst sig_gnt new sc_signal lt bool gt sig_gnt sig_rdata new sc_signal lt int gt s sig_ack new sc_signal lt bool gt s sig_req new sc_signal lt bool gt si sig_rreq new sc_signal lt bool gt s sig_wreq new sc_signal lt bool gt sig a sig_addr new sc_signal lt int gt sig_addr sig_wdata new sc_signal lt int gt sig_wdata HDL_MODULE sv_uvm_master name basename SC_METHOD sv_uvm_master_clk_action sensitive lt lt clk snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_rst_action sensitive lt lt rst snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_gnt_action sensitive lt lt gnt snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_rdata_act
26. our SC based IFS test environment The introduced approach is independent from the IFS library and therefore generic and applicable for any SC based test environment We have to admit though that the complex interference between SV UVM UVMC SC and IFS opens a wide potential for unclear behavior and bugs Instantiating single UVM components outside a UVM environment and using UVMC on top is not the intended use case by design of these technologies Documentation in this corner use case is slim and sometimes trial and error was the only solution to solve unclear error messages There is hope from the charter of the Accellera Multi Language Working Group MLWG to create a standard and functional reference for interoperability of multi language verification environments and components The MLWG realizes that VIP integration and interoperability problems are encountered frequently and not only between SC and SV as also stated in 6 Standardization is mandatory and should contribute to our future work on this topic The result of this work is practically applicable The standards for SV DPI and SC are mature enough to issue no portability problems between the three simulation environments we used For future work it is of interest to turn our approach upside down and instantiate an IFS TBM as UVM agent inside an UVM test bench From the gained experience we believe this to be a feasible approach Acknowledgements This work has been funded by the
27. pkg wrap_uvm_command import ubus_transfer_pkg NOP import ubus_transfer_pkg READ import ubus_transfer_pkg WRITE class ifs_command_monitor uvm_tim_b_target_socket ifs_command_monitor uvm_tlm_b_target_socket ifs_command_monitor uvm_blocking_peek_imp ubus_transfer ifs_command_monitor extends uvm_monitor in wrap_uvm_command in ifs_command_monitor_addr_ph_imp The following property holds the transaction information currently created from detected changes in the DB protected ubus_transfer command_from_TLM_sc monitor notifier that the address phase and full item has been collected protected event address_phase_grabbed protected event DEBUGevent Provide implementations of virtual methods such as get_type_name and create uvm_component_utils_begin ifs_command_monitor uvm_component_utils_end new constructor function new string name super new name in new in this command_from_TLM_sc ifs_command_monitor_addr_ph_imp uvm_component parent null parent new new ifs_command_monitor_addr_ph_imp this endfunction new task called via in socket virtual task b_transport wrap_uvm_command t uvm_tlm_time delay void this begin_tr command_from_TLM_sc uvm_info get_type_name S sformatf ifs _command_monitor b_transport SC TLM communication received cmd sh parameters sp t cmd t parameters
28. r_monitor_ pkg sv 137 sc_wrap MS1 monitor Master transfer collected 195 ns sc_wrap_MS1 monitor ubus_transfer inst read_write addr data master slave begin time ubus_transfer ubus_read_write_enum integral integral string string time time sc_wrap_MS1 0 wn 180 ns 195 ns end_time Lines 51 to 54 demonstrate that the other TBM masters operate in parallel just as well issuing write commands that are answered by the TBM slaves 51 bus_arbiter _tb MS2 820 ns Write Address 16 Value 32 52 bus_arbiter tb SL4 830 ns Write Address 16 Value 32 53 bus_arbiter_tb MS4 1010 ns Write Address 100 Value 98 54 bus_arbiter_tb SL3 1020 ns Write Address 100 Value 98 On reaching the quit command the run phase objection is being dropped line 60 and the simulation terminates 55 56 STs 58 55 60 61 62 INFO 2050 INFO 2050 bus_arbiter_tb SL1 bus_arbiter_tb SL1 End Of Test Script Reached INFO 2050 bus_arbiter_tb SL1 INFO 2050 ns Exiting simulation SystemC simulation stopped by user KRKKKKEEKKEKE Wrap uvm_ master finaliseModule vcs Simulation 2050000 ps ns ns ns Dropping objection for UVM phase run Report Time 6 Conclusions We show that it is possible to instantiate an UVM agent inside a SC test bench and control it to generate signal events for a DUV in a SC test environment Our objective was to reuse external UVM verification IP in
29. reate_process_as_internal SC_METHOD sv_uvm_master_ack_action sensitive lt lt ack snps_sysc_mark_last_create_process_as_internal SC_METHOD sv_uvm_master_req_action SC_METHOD sv_uvm_master_rreq_action j SC_METHOD sv_uvm_master_wreq_action j SC_METHOD sv_uvm_master_addr_action SC_METHOD sv_uvm_master_wdata_action sensitive lt lt sig_req snps_sysc_mark_last_create_process_as_internal sensitive lt lt sig_rreq snps_sysc_mark_last_create_process_as_internal sensitive lt lt sig_wreq snps_sysc_mark_last_create_process_as_internal sensitive lt lt sig_addr snps_sysc_mark_last_create_process_as_internal sensitive lt lt sig_wdata snps_sysc_mark_last_create_process_as_internal std string clk_string clk_string _R clk alterString clk_string name basename hdl_connect_v sig_clk clk_string c_str HDL_OUTPUT HDL_vcs std string rst_string name rst_string _R St Ne alterString rst_string basename hdl_connect_v sig_rst rst_string c_str HDL OUTPUT HDL_vcs std string gnt_string name gnt_string _R_gnt alterString gnt_string basename hdl_connect_v sig_gnt gnt_string c_str HDL_OUTPUT HDL_vcs std string rdata_string name rdata_string _R_rdata alterString rdata_string basename hdl_connect_v sig_rdata rdata_string c_str HDL_OUTPUT HDL_vcs std string ack_string name
30. ress ns Read Address ns Read Address ns Write Address ue ns Write Address ue ns Read Address ue ns Read Address ue ns Write Address ue ns Write Address ue ns Read Address ue ns Read Address 200 ue ns Write Address 300 ue ns Write Address 300 ue ns Read Address 300 ue ns Read Address 300 ue 640 ns SL1 End Of Test Script 640 ns SIMULATION END FROM COMMAND FILE 640 ns Exiting simulation OSCI SystemC Simulation stopped by user 640 ns Report 640 ns Encountered errors 0 640 ns Encountered warnings 0 D E Et print Config s Set_Offset 300 Set_I Wait 100 print Config s Set_Offset 200 Set_I Wait 99 print Config s Set_Offset 100 Set_I Wait 47 print Config s Set_Offset 0 Set_I Wait 69 rJ ical j E ON tn n n n n n n n n n n n E w E G s R 4s e 3 a EG P K WOWBWNNNPEP w trj O D E pa SYNC ALL oop 4 ALL SYNC ALL MS1 Write 100 i 100 i MS1 Read 100 i 100 i eol ALL SYNC ALL SL1 print End Of Test Script ALL QUIT tn Q vu 0 t C Z n a n n ANN 2 n n Z n n 2 OQ OQ O 4 Architecture of the Experiment Even though TLM and UVM concepts are not bound to a certain design language per se they are practically not available in all flavors languages SV is the choice of implementation for UVM SC is yet missing out on UVM concep
31. s instead In the remainder of this chapter we show how this is achieved The presented concept does not rely on the IFS library It is generally applicable in SC UVM Connect UVMC makes use of the SV Direct Programming Interface DPI and enables the communication of a SC model with a UVM model Both language models are compiled separately and co exist in parallel in a mixed language simulator environment It is possible to exchange TLM messages between the two as well as exchange control commands compare with Figure 4 This is the intended use of UVMC between SC and SV TLM1 g amp Jee Ke ec se Z sim Default v Instance Design unit Desig sc_main sc_main ScMo TLM2 N producer producer ScMo SC SV i sc_main sc_main ScThr m sv_main sv_main fast Modu UVM INITIAL 56 sv_main fast Proce INITIAL 60 s _main fast Proce Command S J std std ViPac V umf uvm_pkg uym_pkg ViIPac J m uvmc_pkq uvmc_pkg vlPac Figure 4 UVMC as link for TLM and commands between SC and SV source UVMC documentation Unfortunately this is not ideal for the use case of this work We need a standalone UVM agent without UVM environment to replace a TBM inside SC The abstraction level of the DUV model is register transfer level RTL and does not implement TLM ports The agent should communicate to the DUV via its UVM driver at signal level and not via TLM We therefore use the option to instantiate a foreign language module from
32. sPort INPUT_PORT 32 0 vesInstance gt addPort ack VcsPort INPUT_PORT 1 0 vesInstance gt addPort req VcsPort OUTPUT_PORT 1 0 vesInstance gt addPort rreq VcsPort OUTPUT_PORT 1 0 vesInstance gt addPort wregq VcsPort OUTPUT_PORT 1 0 vesInstance gt addPort addr VcsPort OUIPUT_PORT 32 0 vcesInstance gt addPort wdata VcesPort OUTPUT_PORT 32 0 vcsInstance gt addParameter str_param VcsParam HDL_STRING MASTER str_param str_param_ void sv_uvm_master_clk_action sig_clk gt write clk read void sv_uvm_master_rst_action sig_rst gt write rst read void sv_uvm_master_gnt_action sig_gnt gt write gnt read void sv_uvm_master_rdata_action sig_rdata gt write rdata read void sv_uvm_master_ack_action sig_ack gt write ack read void sv_uvm_master_req_action req write sig_req read void sv_uvm_master_rreq_action rvreq write sig_rreq read void sv_uvm_master_wreq_action wreq write sig_wreq read void sv_uvm_master_addr_action addr write sig_addr read void sv_uvm_master_wdata_action wdata write sig_wdata read const char kind const return dki module_verilog endif 9 Appen dix B Compile and run script used to execute the SystemC UVMC SystemVerilog mixed language
33. ting 30 bus_arbiter_tb CLK 100 ns reset gets passiv 31 bus_arbiter_tb SL1 100 ns set slave offset 300 32 configuring SL1 to SL4 33 UVM_INFO tb_uvm ubus_master_driver_pkg sv 89 110 ns sc_wrap MS1 driver ubus_master driver kk x xk ubus master driver get_and_drive Waiting for Item on seq_item_port 34 kkkkERKEKAE Wrap uvm Master Write Sending payload cmd 2 parameters 100 98 to MS1 socket at time 150 35 UVM_INFO tb_uvm ifs_command_monitor_pkg sv 75 150 ns sc_wrap_ MS1 ifs_ monitor ifs_command_monitor Seek RR I ifs _command_monitor b transport SC TLM communication received cmd 00000002 parameters 100 98 36 UVM_INFO tb_uvm ifs_command_monitor_pkg sv 116 150 ns sc_wrap MS1 ifs_ monitor ifs command monitor ifs command _monitor peek Informing driver to drive cmd 2 addr 100 data 98 37 UVM_INFO tb_uvm ubus_master_driver_pkg sv 91 150 ns sc_wrap MS1 driver ubus_master_ driver PEA REELS ubus_master_ driver get_and_drive Received Item on seq_item_port 38 bus_arbiter_tb SL3 190 ns Write Address 100 Value 98 39 UVM_INFO tb_uvm ubus_master_monitor_pkg sv 173 195 ns sc_wrap_ MS1 monitor ubus_master_ monitor collect_data_phase The UVM agent s monitor listens on the signal events between UVM agent and DUV and recognizes a correct write transaction lines 40 to 50 UVM_INFO tb_uvm ubus_maste
34. ts but literature shows work in progress 7 The similarities of the IFS and UVM concepts Figure 1 suggested a common basis for an interchangeable use To proof the assumption in an experiment we needed to connect SC IFS and SV UVM The Verification Academy offers UVM Connect to interconnect the two UVMC is an open source UVM OVM based library that provides TLM1 and TLM2 connectivity and object passing between SC and SV UVM OVM models and components It also provides a UVM Command API for accessing and controlling UVM simulation from SC or C or C UVM Connect allows you to reuse your SC architectural models as reference models in UVM OVM verification and or reuse SV UVM OVM agents to verify models in SC 8 We demonstrate here that the UVMC API is applicable in the substitution of an IFS TBM by an UVM a ent in a mixed language simulation that combines SC including SCV SystemC Verification Standard and SV UVM This way we open the door to make a full evolutionary inclusion of state of the art UVM verification IP in the well established IFS flow including its link to AMS simulation A TBM directly correlates to the functionality of an UVM agent Both act as transactor between test bench and DUV and translate messages commands to bit wiggles For complex IP it can become quite cumbersome to create a verified TBM When IP comes with a UVM test environment TBM reimplementation is redundant effort if we could reuse the delivered UVM agent
35. wn test cases All stakeholders in the development process digital designer analog designer verification engineer and system engineer make use of the same simple IFS command language to create self checking test cases Matching Concepts of Two Very Similar Methodologies IFS Controller IFS Test Bench Module TBM IFS Command File CF IFS TBM Command UVM Environment UVM Agent UVM Sequence UVM Sequence Item Test Environment Coverage Monitor sc_main RM TBM b Test Bench Module BFM Bus Functional Model TBM b Test Bench Module BFM Bus Functional Model Scoreboard Configuration a State of the art UVM approach Figure 1 Juxtaposition of a UVM and b IFS b Existing SystemC based approach We utilized a bus arbiter test case Chapter 2 as design under verification DUV inside an IFS simulation environment with bus master and bus slave Test Bench Modules TBM Chapter 3 In the architecture of our experiment Chapter 4 bus masters were successfully replaced by UVM agents and fully simulated in a holistic test bench simulation using Synopsys VCS Chapter 5 The document concludes in Chapter 6 The listing of Appendix A shows the source code of our TBM master wrapper which handles all three proprietary foreign language instantiation concepts of the three simulators Synopsys VCS Mentor Questa Simulator and Cadence Incisive
36. y endif else error Cannot compile for MTI_SYSTEMC and NC_SYSTEMC simultaniously endif elif defined VCS ifndef MTI_SYSTEMC ifndef NC_SYSTEMC include csrc sysc include sv_uvm_master h class foreign_module_master public sc_in_clk uvm_master_clk sc_in lt bool gt uvm_master_rst reset sc_out lt bool gt uvm_master_req master request sc_in lt bool gt uvm_master_gnt grant from arbiter sc_out lt bool gt uvm_master_rreq read request sc_out lt bool gt uvm_master_wreq write request sc_out lt int gt uvm_master_addr address sc_out lt int gt uvm_master_wdata write data sc_in lt int gt uvm_master_rdata read data sc_in lt bool gt uvm_master_ack acknowledge foreign_module_master sc_module_name name const char hdl_name uvm_master_clk clk uvm_master_rst rst uvm_master_req req uvm_master_gnt gnt uvm_master_rreq rreq uvm_master_wregq wreq uvm_master_addr addr uvm_master_wdata wdata uvm_master_rdata rdata uvm_master_ack ack std string tmp tmp name the class sv_uvm_master is generated by Synopsys tool see code below vcs_uvm_master new sv_uvm_master name tmp c_str Input ports vces_uvm_master gt clk uvm_master_clk vcs_uvm_master gt rst uvm_master_rst vcs_uvm_master gt gnt uvm_master_gnt vcs_uvm_master gt rdata uvm_master_rdata vcs_uvm_master gt ack uvm_master_ack Output ports vcs_uvm_master gt req
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