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RL78/G10 EEPROM Control by Simplified I2C Function

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1. STATUS Stores the status of I2C interrupt control function by function DATACOUNT Stores the number of data of I2C writing or reading SLAVEADDR 5 6 Slave address of I2C Function Subroutine List Table 5 7 and Table 5 8 shows the function subroutine Function Table 5 7 Function External Function Outline PUTDATA GETDATA Writing start processing to the specified block Reading start processing from the specified block PUT_ CHK Writing to EEPROM state check processing GET_ CHK Reading from EEPROM state check processing WAIT_END StopCond Waiting processing for the completion of access to EEPROM Execution of stop condition to I2C bus R_IICOO_Init Initialization of IIC00 SINITAU Initialization of TAUO1 IINTIIGOO ICOO interrupt handler Table 5 8 Function Internal Processing Function Function Outline StartCond Generates start condition to I2C bus R_IICO0O_send_Stop R_IICO0O_wait_bus Generates stop condition to 12C bus Releases DC bus R_IICOO_SCL_pulse Outputs SCL signal of 1 pulse R IC00 SCL high Raises SCL signal to high R IC00 SCL low R WC SCL Time falls SCL signal to low Secures the time of the pulse width of a SCL signal get slave Addr RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Calculates the address in I2C bus of EEPROM Page 23 of 81 RENESAS RL78 G10 EEPROM Control by
2. Constant SCLLOWW Count down Decrements a value of X register by 1 X register X register 1 No If X register is not 0 branches as a No judging Yes d v RET Figure 5 40 SCL Signal Width Securing R01AN2217EJ0100 Rev 1 00 Page 75 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 33 Calculation of Slave Address Figure 5 41 shows the calculation of slave address get_slave_Addr get_slave_Addr Read a block number Sets a value of variable BLOCK NUMBER to AX register Check the block number Compares the value of AX register with constant BLKNO Dummy status setup Sets constant PARA_ERR parameter error to variable STATUS Invert CY flag Sets CY flag when the block number specification error is Block number is normal occurred If CY flag is set branches as No judging Zz O Status setup Sets constant DC OK normal end to variable STATUS Calculate EEPROM address Converts block number into EEPROM address Ais Bis 16 EEPROM address setup Sets EEPROM address to variable EEPROMADDR Mask the upper address Extracts the information to be reflected in a slave address from EEPROM upper address Modify a slave address Reflects extracted information in a slave address Set the slave address Sets the created slave address to variable SLAVEADDR Vv lt D n RET Figure 5 41 Calculation of Slave Address RO1AN2217E
3. General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this document refer to the relevant sections of the document as well as any technical updates that have been generated for the products 1 Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset funct
4. 00000110B PMO register 11100110B Figure 5 7 VO Port Setup Function Note Refer to the section entitled Flowcharts in RL78 G10 Initialization Application Note RO1AN1454E for the configuration of the unused ports Port setting Port mode control register 0 PMC0 Switching between analog input and digital I O Port registers 0 PO Setup of an output latch of each port Port mode registers 0 PMO Selection of the I O mode of each port Symbol PMCO 7 6 5 4 3 2 1 0 a ECH Bits 4 to 1 POn pin digital VO analog input selection Digital I O alternate function other than analog input RO1AN2217EJ0100 Rev 1 00 Page 30 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Symbol PO 7 6 5 4 3 2 1 0 o o o Pos Pos poz f For Po Loj ojo o NE N HE GEE DA Bits 2 and 1 Pon POn pin output data control in output mode Input mode output buffer off Bit 0 Poo POO pin output data control in output mode Pre mode output buffer on Symbol PMO 7 6 5 4 3 2 1 0 Or mes rus Tee Poo 1 Li Li o o 1 1 o Bits 2 and 1 Pmon POn pin I O mode selection Input mode output buffer off Bit 0 PMOn POO pin UO mode selection Pre mode output buffer on Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method R
5. 3 Related Application Notes The application notes that are related to this application note are listed below for reference RL78 G10 Initialization RO1AN1454E Application Note RL78 G10 Timer Array Unit Interval Timer RO1AN1457E Application Note RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Page 9 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 4 Description of Hardware 4 1 Hardware Configuration Example Figure 4 1 shows an example of hardware configuration that is used for this application note RL78 G10 master LED Voc EEPROM slave R1EX24256B External pull up PO2 SCLOO P01 SDA00 P40 TOOLO L t For on chip debugger Figure 4 1 Hardware Configuration Cautions 1 The purpose of this circuit is only to provide the connection outline and the circuit is simplified accordingly When designing and implementing an actual circuit provide proper pin treatment and make sure that the hardware s electrical specifications are met connect the input only ports separately to Vpp orVss via a resistor 2 Vppmust be held at not lower than the reset release voltage Vspor that is specified as SPOR 3 Since EEPROM device address pins A0 Al A2 are pulled up inside EEPROM they are recognized un connecting RO1AN2217EJ0100 Rev 1 00 Page 10 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 4 2 List of Pins to be Used Figure 4 1 lists th
6. BLOCKNUMBER H AX register Variable BLOCKNUMBER Repeats the read processing for the number of EEPROM blocks Compares AX register and the constant BLKNO If CY flag is set constant BLKNO is larger than AX register value moves to the No judgment Figure 5 12 Main Processing 3 4 RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Page 37 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Clears INTPO interrupt request flag Clears INTPO interrupt mask flag gt HALT No INTPO interrupt occurs Yes BLOCK_NUMBER clear INTPO interrupt mask flag set 0 bit of PO register 0 IE bit 0 PIFO bit 0 PMKO bit 0 Waits while carrying out a loop until SW1 is pressed Keypress of SW1 starts EEPROM write processing again Moves to No judgment until SW1 is pressed Variable BLOCK NUMBER lt 0 PMKO bit 1 0 bit of PO register 1 Figure 5 13 Main Processing 4 4 RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Page 38 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 6 11ICO0 Initialization Figure 5 14 shows the IIC00 initialization R_IC00_Init Chanel 0 of SAUO is set to C00 at IIC initialization Fast mode is selected for ICOO setup In the simplified DC function of SAU since duty of a transfer clock cannot be set up freely it is necessary to set up a transmission clock so that the low level width
7. Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 43 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of initial output level of transmission channel Serial output register 0 SOO Setup of initial output level Symbol SOO 7 6 5 4 3 2 1 0 001 Note 16 pin products only Bits 1 and 0 S001 s000 1 1 Serial data output value is 1 Serial data output value is 0 Setup of serial clock output of transmission channel Serial clock output register CKO0 Setup of serial clock output Symbol CKOO 7 6 5 4 3 2 1 0 D o o o f o Coon cK 000 _ D o o o o o 1 1 Bits 1 and 0 CKO01 CKOOO Serial clock output of channel 0 1 1 Serial clock output value is 1 Serial clock output value is O Setup of port output mode register Port output mode register 0 POMO Sets a N ch open drain output VDD tolerant mode for transmitting data Symbol POMO Note Gees only Bit 1 Pomor P01 pin output mode selection N ch open drain output VDD tolerant mode RO1AN2217EJ0100 Rev 1 00 Page 44 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 7 INTIICOO Interrupt Entry Processing Figure 5 15 shows INTIICOO interrupt entry processing IINTIC00 Confirms a resp
8. Symbol SOEO 7 6 5 4 3 2 1 0 poo o o o een soos peo fo Foo fo fo Jo x fo Bit 0 SOE00 Serial output enable disable of channel 0 O Disables output by serial communication operation Setup of initial output level Serial output register 0 SOO Setting of the serial output level Symbol SOO 7 6 5 4 3 2 1 0 EES EECH o ml Note 16 pin products only Bit 0 SOOO Serial data output of channel 0 1 Serial data output value is 1 0 Serial data output value is 0 Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 72 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 28 DC Bus Release Processing Figure 5 36 shows DC bus release processing R ICO0O wait bus R IICOO wait bus The number of Sets the number of dummy clocks to be generated dummy clocks setup A register Constant RETRYCNT gt SCL pulse generation R_IICOO_ SCL pulse Outputs dummy clocks from SCL signal Counts the number of generated dummy clocks N Output of 9 clocks If the number of dummy clocks A register are not 0 are completed d e branches as a No judging Yes gt C 3 gt bd bai o 9 a C 3 3 De Q o o 9 a Q 6 C 2 O SDA signal check Sets the state of SDA signal to CY flag Invert CY flag Cl
9. a timer interrupt is not generated imer interrupt is not generated when counting is started Capture amp one count mode imer output does not change either 1 1 0 art trigger is invalid during counting operation that time a timer interrupt is not generated Other than above Setting prohibited Setup of Timer data register 0 Timer data register On TDROnH TDROnL Symbol TDROnH TDROnL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 63 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of disabling timer output Timer output enable register 0 TOEO Sets enabling disabling timer output of each channel Symbol TOEO 7 6 5 4 3 2 1 0 TOEO3 TOEO02 Note Note TOEO1 TOEOO 0 0 0 0 D D 0 x Note 16 pin products only Bit 1 TOE01 Timer output enable disable of channel 0 Disable output of timer Without reflecting on TOOn bit timer operation to fixed the output Writing to the TOOn bit is enabled and the level set in the TOOn bit is output from the TOOn pin Enable output of timer Reflected in the TOOn bit timer operation to generate the output waveform Writing to the TOOn bit is disabled writing is ignored Setup of output value of timer output pin Timer output register 0 TOO Sets the output valu
10. 2014 Figure 5 32 Stop Condition Execution Page 57 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 25 Timer Initialization Figure 5 33 shows the timer initialization SINITAU SINITAU Clock supply Sets TAUOEN bit and supplies clock Stops TAUO1 1 bit of TTHO register 1 Mimer SOP 1 bit of TTO register 1 Sets frequencies of CKOO and CKO1 in TPSO register Prescaler setup CK01 fCLK 16 when the fast mode is set CKO1 fCLK 64 when the normal mode is set Mode register setup TMRO1H register 10001000B Select 8 bit timer TMRO1L register 00000000B Interval timer Interval time setup TDRO1H register 124 100us 400us TOO1 output disabled 1 bit of TOEO register 0 TOO1 output disabled TOO register 00000000B Clears TOO1 output initialization Interrupt disabled TMMKO1H bit 1 Masks interrupt request TMIFO1H bit 0 Clears interrupt request v RET Figure 5 33 Timer Initialization R01AN2217EJ0100 Rev 1 00 Page 58 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Starting clock supply to the timer array unit Peripheral enable register 0 PERO Starts clock supply to the timer array unit 0 Symbol PERO 7 6 5 4 3 2 1 0 EE ooo ET Geel free EN ET EN EE ON OE x ON N EN EN EN ON EE EN Note 16 pin products only Bit 0 Conirol of timer array unit input clock Stops supply of input clock SFR us
11. 5 4 3 2 1 0 Pxt x xi x lo olo o_ Bits 7 to 0 PRS Selection of operation clock CKOK noe k 0 1 1 25MHz 12 5 MHz MHz 10MHz 20MHz PO O 1 Ol 0 fak sv 25vrc sme 10mHz 20 MHz Po of oft f t2 esu 125mhz 25MHz awe awe Po fo ft fo ffa 313khz 625khz usus 25MHz Toun 2 5 MHz 625 khz faw Laag Lsv av aus Z Z Z E z fou L 313Hz Ier 122 kHz 2 f z zula oi 1 0 1 CLK oe se atone caste Dee Ce 4 Note When changing the clock selected for CLK by changing the system clock control register CKC value stop timer array unit TTO OFH TTHO OAH Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 60 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of channel 0 operation mode Timer mode register On TMROnH TMROnL Selection of the operation clock f MCK Selection of the count clock Select the 16 or 8 bit timer Specifying the start trigger and capture trigger Selection of the valid edge of the timer input Setting of the operation mode Symbol TMROnH 7 6 5 4 3 2 1 0 ekson o o Gosen ser STS0n2 STSOnt STSOA0 Ee Ti Ts es To CKSOn1 Selection of operation clock fMCK of channel n F 0 operation cock cK00 set by ier dock sea regeer
12. 5 8 27 Stop Condition Generation EEPROM Control by Simplified 12C Function Figure 5 35 shows the stop condition generation R_HC00_send_Stop R_IICOO_send_Stop Stop IIC00 IICOO output disabled Falls SD Secure high level width of SCL R 1C00 SCL Time Operation A signal Wait for set up time R IC00 SCL Time Raises SCL signal R_IICOO_SCL_high Raises SDAsignal Clear CY flag Wait for hold time R IICO0 SCL Time Secures the high level width of SDA signal Stops operation of channel 0 IIC00 Bit O of STO register 1 Disables output of channel 0 IIC00 Bit 0 of SOEO register 0 Falls SDA signal SOO register 00000010B Waits for set up time of SDA signal Raises SCL signal Raises SDA signal stop condition generation SOO register 00000011B Clears CY flag as the processing is completed Waits for hold time of SDA signal Figure 5 35 Stop Condition Generation RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Page 71 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Stops the serial communication Serial channel stop register 0 STO Stops IIC00 operation Serial output enable register 0 SOEO Disables output Symbol STO 7 6 5 4 3 2 1 0 ER ERE e MEE SE WEEN HE Ed HE WEN HE EEN HE Ed HE EEN Er Ed HE Had Bit 0 STOO Operation stop trigger of channel 0 lees the GEO bit to 0 and stops the communication operation
13. ER 1 Operation clock CKO1 set by timer clock select register 0 TPSO Selection of count clock fTCLK of channel n Operation clock fMCK specified by the CKSOn1 bit Valid edge of input signal input from the TIOn pin Selection of 8 or 16 bit timer operation for channels 1 and 3 n 1 3 Operates as 8 bit timer Bits 2 to 0 STS001 Setting of start trigger or capture trigger of channel n STS002 STS000 f n 0 1 for 10 pin products n 0 to 3 for 16 pin products Only software trigger start is valid other trigger sources are unselected nan Both the edges of the TIOn pin input are used as a start trigger and a capture trigger When the channel is used as a slave channel with the one shot pulse output PWM output function or multiple PWM output function The interrupt request signal of the master channel INTTMOn is used as the start trigger he channel is used as a slave channel in two channel input with one ulse output function errupt request signal of the master channel INTTMOn is used as the igger edge of the TI03 pin input of the slave channel is used as the end Other than above ing prohibited RO1AN2217EJ0100 Rev 1 00 Page 61 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Symbol TMROnL 7 6 5 4 3 2 1 0 CISOn1 ClSOn0O 0 0 MDOn3 MDOn2 MDOn1 MDOnO p of of oT Fo of of 0 Bits 7 and 6 CISOn1 CISOn0 Selection of TIOn pin i
14. Function Name WAIT_END Outline Explanation Argument Return value Remarks RO1AN2217EJ0100 Sep 17 2014 Waiting processing for the completion of access to EEPROM Checks the value of variable STATUS and waits for the completion of processing None l CY flag 0 Normal end 1 Abnormal end Rev 1 00 Page 25 of 81 RENESAS RL78 G10 EEPROM Control by Simplified DC Function Function Name StopCond Outline Explanation Argument Return value Remarks Execution of stop condition to I2C bus Performs stop condition to DC bus Then checks SDA signal and if SDA signal is low performs the bus release processing After finishing bus release generates stop condition again None CY flag 0 Normal end FS 1 Abnormal end The pin is output state IICOO is stopped Function Name R_IICO0_Init Outline Explanation Argument Return value Remarks Initialization of IICOO Initializes the interval timer for confirming the completion of writing to EEPROM The interval is set to 100us at the time of the fast mode and to 400us at the time of the normal mode None None None Function Name SINITAU Outline Initialization of TAUO1 Explanation Initializes the interval timer of 100us for confirming the completion of writing to EEPROM Argument None Return value None Remarks None RO1AN2217EJ0100 Rev 1 00 Page 26 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Func
15. G10 EEPROM Control by Simplified 12C Function a If EEPROM reading processing is called under the standby state a parameter the target block number will be checked When the block number is wrong since it is a parameter error processing is ended If a parameter is right start condition will be generated and a slave address will be transmitted as LSB 0 b Checks a response from a slave by a interrupt request from INTIICOO When it is NACK response generates a stop condition and ends the processing When it is ACK response transmits EEPROM address At this time 2 bytes of address information is transmitted to EEPROM which is 32K bits or above and 1 byte of address information is transmitted to EEPROM which is 16K bits or less c The response from a slave is checked by the interrupt request of INTIICOO If it is a NACK response generates a stop condition and ends the processing When it is ACK response writes transmission data to SIO00 and starts transmission d Checks a response from a slave by INTIICO0 interrupt request If it is NACK response generates stop condition and finishes the processing If it is ACK response writes the next transmission data to SIO00 and starts the transmission If there is no next data generates stop condition completes the transmission and starts writing to EEPROM In order to confirm the completion of writing activates TMO1H as an interval timer of 100us At this time changes Variable STATUS into A
16. Simplified 12C Function 5 7 Function Subroutine Specifications This section describes the specifications for the functions subroutines that are used in this sample program 5 7 1 External Function Function Name PUTDATA Outline Writing start processing to the specified block Explanation Checks the state of the bus and generates start condition Then calculates the address of a cell from a block number and transmits a slave address Argument BLOCK_NUMBER Block number which data will be written in WRITE_BUFF Data to write Return value Variable STATUS TRANSMIT S Processing is started normally PARA_ERR B Th j maaie blank BUS_ERR _ The error in speci ication The bloc number was too large DC bus is not in the state which can be used Remarks Return value is stored into the global variable STATUS Function Name GETDATA Outline Reading start processing from the specified block Explanation Checks the state of the bus and generates start condition Then calculates the address of a cell from a block number and transmits a slave address Argument BLOCK_NUMBER Block number which data will be read from READ BUFF Read out data storing area Return value Variable STATUS RECEIVE Processing is started normally PARA_ERR The error in specification The block BUS_ERR number was too large 12 C bus is not in the state which can be used Remarks Return value is stored into the global variable STATUS RO1AN2217EJ0100 Rev 1
17. and subsequent processing is not performed When the writing reading of serial EEPROM carry out a normal end makes LED lighting state and moves to the waiting for SW1 keypress If SW1 is pressed makes LED lighting out state and performs writing reading all the memory areas of EEPROM 1 Initializes on chip peripheral functions lt Setting conditions gt a Sets I O port e Sets a digital I O to PMCO register e Sets the initial value to PO register as initializes LED connection pin P00 is high output SDA00 pin P01 is low output and SCLOO pin P02 is low output e Sets the initial value to PMO register as initializes LED connection pin PM00 is output SDAOO pin PMO1 is input and SCLOO PMO02 is input b Sets clock generator e Sets HOCODIV register to 20MHz c Initializes interruption related registers e Sets the mask of INTPO interrupt e Enables to detect falling edge of INTPO interrupt e Clears the interrupt request of INTPO interrupt 2 Clears the memory area used by a program a Clears the number of blocks writing reading variable BLOCK_ NUMBER b Clears data storage areas of reading and writing variable WRITE_BUFF READ BUFF R BUFF END c Clears I2C interrupt control status variable STATUS d Clears the number of data DC writing reading processing variable DATACOUNT e Clears the slave address of DC variable SLAVEADDR EE am 3 Initializes SAU as the simplified I2C functi
18. equal to 9 clocks EEPROM will make a SDA signal high level The reason is as follows EEPROM outputs data according to a transmission request from the master If the data is 0 low level EEPROM has stopped If SCL signal is detected EEPROM shifts to the next data output and stops the drive of a SDA signal after 8 clocks at the latest for the ACK reception from the master And after 9 clocks EEPROM detects NACK and stops transmission Dummy clock 8 clocks rough sketch SCL signal SDA signal S EEPROM makes SDA EEPROM releases signal into low level SDA signal for checking of ACK Figure 1 3 Bus Release Processing R01AN2217EJ0100 Rev 1 00 Page 7 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 1 3 Address Setup Processing of EEPROM 1 3 1 Targeted EEPROM Specification In this application note uses Serial EEPROM of Renesas Electronics The serial EEPROM varies in an addressing method of the memory cell in the EEPROM depending on capacity size Table 1 2 shows the specification of serial EEPROM used with this application note made by Renesas Electronics Table 1 2 Addressing Method of EEPROM BEE N N EE EO WEE EA N id a ue A2toA0 Jet bie 2nd byte 1EX24512B 16 bits a15toa0 at5toa8 1EX24256Bnote 15 bits a14toa0 a14toa8 1EX128B 14 bits a13toa0 a13toa8 a12toa8 2K 1EX24064A 1X24032A La 12bits a11toa0 alitoa8 a7 toad R1EX24016A
19. for escaping from interrupt processing after transmitting the data of A register to I2C bus IICWrite 1000 register A register Restore AX register Forwards the data of A register to SIOOO register and starts transmission Restores the value of AX register from a stack area Returns from interruption processing Figure 5 19 12C Write Processing RO1AN2217EJ0100 Rev 1 00 Page 47 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 12 12C Data Reception Start Processing Figure 5 20 shows the DC data reception start processing R_IICO0_RxDataST This is a processing routine of the completion of slave address transmission in master reception after restarting Stops IIC00 changes the mode of IICO0 from transmission to reception and reboots IIC00 Writes dummy data to SIOOO and starts receiving processing Dummy data set IICWrite Stops operation of IICOO 0 bit of STO register 1 Clears TxE00 bit of SCROOH register and sets RXEOO bit SCROOH register Constant CRXMODERXH Enables IICOO operation 0 bit of SSO register 1 Sets the next processing address R_IICOO_Rx_DataST into the variable NEXTADR Sets dummy data into A register for receiving A register FFH Branches to the function subroutine IICWrite Figure 5 20 I2C Data Reception Start Processing RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Pa
20. of EEPROM Gees esse sd Se cn ene ED Ge ee Gede Be ke eie ii Geek se ee ee ee gie 8 2 Operation Confirmation Conditions ee RR RE RR KEER RR RR ER EER RR ER EER ee AR EE Ee ee EE 9 3 Related Application Note is EER EKKE KEER RGN RE KAR Ak N EE ER ERNS NS ER GN N N ENE NE ke N Ee ee 9 4 Description Of Hardware iese ss as SS ERK RE AR RE NN RNAAR EN Ne EK ER BE Be N KERE EE Ke N eN EN 10 4 1 Hardware Configuration Example e esse ee esse en Rae EE Re AR Ke AR RR GA RR KEER KERE AK Ke AR Ka GR RR RR ENEE RR Ra Ge ER Ee ee 10 4 2 List of Pins to be Used iseer RE ER RE REG RR KERE GR RR KERE GR RR KERE GR AR KERE GR RR KERE GR AAR KERE GR RR KERE GR RR KERE GR RR KEER en 11 AE oi EE EE EE EE EE EE N EE 12 5 1 Operation Outline ii EE EE BEDE ae AE aes GE ee ea ee RD EE Da ee ee GER Ie Oe ieee Ge 12 5 2 Details of Serial EEPROM Control PrograM ees ee esse ee ss ee en seek ese ek Ke AR Rae e ER Ee ek KEee RR Ka ee ER Ee ee 14 5 2 1 jntertuptProcessing CIE sis EES Rd SERE GENE EE Eed ged og SERE GEE AES SEE Re EE Redes ds 14 5 2 2 EEPROM Control Program State TransitionS iese se ee ee es se ge ee es ee ke ee ee Re ee ee Re ee ee ee ke ee ee ee 15 5 3 Option Byte Settings use EE Ee ee EE EENS 21 5 4 or vi EE N an 21 ENEE ee 23 5 6 Function Subroutine List ius ei iS Ek ke kk aech SEENEN 23 5 7 Function Subroutine Specifications iis ee ee see REG Ge AE Re Ge AE Re Ge AE Re Ge AE Re Ge AE Re Ge AE ee 24 TA
21. 0 Fax 44 1628 585 900 nesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel Re Ro Tel Rei Uni Tel Re Un Tel Re 49 211 6503 0 Fax 49 211 6503 1327 nesas Electronics China Co Ltd om 1709 Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100191 P R China 86 10 8235 1155 Fax 86 10 8235 7679 nesas Electronics Shanghai Co Ltd it 301 Tower A Central Towers 555 Langao Road Putuo District Shanghai P R China 200333 86 21 2226 0888 Fax 86 21 2226 0999 nesas Electronics Hong Kong Limited it 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong 852 2265 6688 Fax 852 2886 9022 9044 nesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Tel Re 80 Tel Re Un Tel Re 886 2 8175 9600 Fax 886 2 8175 9670 nesas Electronics Singapore Pte Ltd Bendemeer Road Unit 06 02 Hyflux Innovation Centre Singapore 339949 65 6213 0200 Fax 65 6213 0300 nesas Electronics Malaysia Sdn Bhd it 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia 60 3 7955 9390 Fax 60 3 7955 9510 nesas Electronics Korea Co Ltd 12F 234 Teheran ro Gangnam Ku Seoul 135 920 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2014 Renesas Electronics Corporatio
22. 00 Page 24 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Function Name PUT_CHK Outline Explanation Argument Return value Remarks Writing to EEPROM state check processing Checks the state after start writing to EEPROM If the processing is completed Z flag is set None Z flag 1 Processing is completed Variable STATUS I2C_OK BUS ERR Normal end NO ACK1 _1 The state which cannot use a bus TRANSMIT _ No ACK response from a slave AFT_TX o Z flag 0 E Under slave address transmission Data transfer is completed and it is under writing Under continuation of processing If MSB of STATUS is 1 it is under processing If MSB of STATUS is 0 it is the completion of processing Function Name GET_CHK Outline Explanation Argument Return value Remarks Reading from EEPROM state check processing Checks the state after start reading from EEPROM If the processing is completed Z flag is set None Z flag 1 _ Processing is completed Variable STATUS I2C_OK Normal end BUS_ERR The state which cannot use a bus NO_ACK1 No ACK response from a slave Z flag 0 Under continuation of processing RECEIVE _ Under slave address transmission RxData Under receiving data RxLast _ Under receiving the final data If MSB of STATUS is 1 it is under processing If MSB of STATUS is 0 it is the completion of processing
23. 0100 Rev 1 00 Page 56 of 81 Sep 17 2014 RENESAS RL78 G10 5 8 24 Stop Condition Execution EEPROM Control by Simplified 12C Function Figure 5 32 shows the stop condition execution StopCond StopCond Setup status Stop condition generation j R_IIC0O0 send Stop Set SDA pin to input R 1IGO0 Yes l DC bus release wait bus Set SDA pin to output No Bus release is successful Yes No SDA signal is low level Stop condition generation j R_IIC0O send Stop pic Set SDA pin to output Interrupt disabled Vv RET Sets the status to normal end Variable STATUS Constant I2C_OK Generates stop condition by IICOO Sets SDA pin of PO which is used by SDA signal to input mode 1 bit of PMO register 1 Checks for SDA pin level of PO register If SDA pin of PO register is high level branches as No judging Outputs a dummy clock to 12C bus and waits for the bus release Sets SDA pin of PO which is used by SDA signal to output mode 1 bit of PMO register 0 If 12C bus release was successful generates stop condition When CY flag was set as a return value of R 1ICOO wait bus branches as No judging If I2C bus release was failed sets CY flag and returns Sets SDA pin of PO which is used by SDA signal to output mode 1 bit of PMO register 0 Sets the mask of IICOO interrupt request IICMKOO bit 1 RO1AN2217EJ0100 Rev 1 00 Sep 17
24. 1 keypress If SW1 is pressed makes LED lighting out state and performs writing reading all the memory areas of EEPROM The detail specification of this application note is shown below RL78 G10 microcontroller is used as the master and serial EEPROM is used as the slave Selects a target serial EEPROM from 512K bit 64K byte to 2K bit 256 byte Selectable serial EEPROMs are 2K bit 4K bit 8K bit 16K bit 32K bit 64K bit 128K bit 256K bit and 512K bit 256K bit serial EEPROM is selected as the default Selects a communication rate either first mode Max 384k bps or normal mode Max 100 kbps As for the transfer rate of simplified DC function the duty ration is 50 due to use SAU operation clock For this reason it is required to set a transfer rate that the low level width of a SCL signal meets the specification of I2C bus 1 3 us And the first mode is not 400kbps but around 384kbps Refer to RL78 G10 User s Manual Hardware for more information Accesses serial EEPROM per a data block unit defined beforehand In this application note the data size of 1 block is chosen from 4 8 16 bytes in order to avoid processing of the page boundary at the time of EEPROM writing Refer to 1 1 Page Boundary Processing for more information Bus release processing is performed in consideration of a possibility that DC bus is occupied Refer to 1 2 DC Bus Release Processing for more information Using interrupt
25. 2K _ 11bits a10toa0 a10toa8 a7toao R1EX24008A 1K 10bits a9toa0 a9 a8 a7toao R1EX24004A 512 9bits a8toa0 A0 a8 a7toao R1EX24002A 256 8bits a7toao atoao Note It is EEPROM used for the operation confirmation of this application note 1 3 2 Address Update Reading or writing is performed by specifying an address the address is updated automatically and comes to show the next address in EEPROM Therefore it is not necessary to specify an address each time when performing continuation writing and reading data However the continuation writing over a page boundary requires the described cautions 1 1 Page Boundary Processing 1 3 3 Writing Processing of EEPROM If a master RL78 G10 generates stop condition EEPROM will actually start writing data received to a memory cell The execution time of this writing processing for 1 page is about 5 ms and EEPROM does not responds ACK to a master RL78 G10 in this 5 ms In order to write data continuously it is necessary to transmit the next data after the waiting of the writing end waiting about 5 ms As a method of checking a writing completion waiting state start condition is generated from a master RL78 G10 and it transmits in the writing mode LSB 0 of EEPROM Although it becomes a NACK response under writing processing if writing is completed it becomes an ACK response and can check the state of EEPROM R01AN2217E
26. 2tEN ESAS APPLICATION NOTE RL78 G10 RO1AN2217EJ0100 Rev 1 00 EEPROM Control by Simplified I2C Function Sep 17 2014 Introduction This application note describes how to control the external serial EEPROM by using Simplified I2C function of the serial array unit SAU Realizes reading writing serial EEPROM through DC bus connection using Simplified 12C function by interrupt processing Target Device RL78 G10 When applying the sample program covered in this application note to another microcontroller modify the program according to the specifications for the target microcontroller and conduct an extensive evaluation of the modified program RO1AN2217EJ0100 Rev 1 00 Page 1 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified I2C Function Contents T Specification EE EE re ree EE 4 1 1 Page Boundary Processing users eke ER Re ER EER RR EE AR RA AR KEER ER KERR KRAAK Ge RR RARR RR EER AR RR GA RR Ra GR EE Ee ek KEER 6 12 12C Bus Release Processing users RR EE REGEER RE ARK RA ER BEER ER KEER KA AR KEER RR RAGE KRAAK RE GA RR REG RE Ee AR RE Gee 7 1 3 Address Setup Processing of EEPROM ene ese esse eek naas e Re ee EE Re AR Ke AR RR Ge RR Ke ee KRAAK Ge RR Ke ee RE Ee 8 1 3 1 Targeted EEPROM SpecificatiON iese see esse ee ke ee ee ee ke ee ee ee ke ee ee ee ke ee ee ee ke ee ee ee ke ee ee ee ke ee ee ee ke ee naa 8 1 3 2 Address Me GR EN AE EE EE EE EE N N 8 1 3 3 Writing Processing
27. 48 EEPROM Control Information Clear 2 Hardware initialization In Figure 5 49 initializes the hardware to be used And then generates stop condition and makes DC bus an initial state IICOO and timer initialize CALL IR HCO0 Init initialize ITCOO function CALL SINITAU Initialize 100us timer CALL StopCond IIC bus initialize bus free Figure 5 49 Hardware Initialization 3 Write to EEPROM processing In Figure 5 50 as a preprocessing to write data in EEPROM data to write in is set as memory area WRITE BUFF and the block number of EEPROM to write in variable BLOCK NUMBER is set Then a control function is called Activates the write to EEPROM processing by CALL PUTDATA and starts the write to EEPROM processing Since all processing is interrupt processing in the background shortly after starting processing will return It is possible to perform other processing simultaneously Here waits for the completion of CALL WAIT END processing without performing any others CY flag is set and returned if any errors occurred In this example if an error is detected an infinite loop will be carried out at ERRORLOOPI EI CALL PUTDATA write data to EEPROM NOP CALL WAIT END wait for complete ERRORLOOPI1 BC SERRORLOOPI loop if error Figure 5 50 Write to EEPROM Processing RO1AN2217EJ0100 Rev 1 00 Page 79 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 4 Read f
28. CO0 0 bit of STO register 1 Disables output of channel 0 IIC00 0 bit of SOEO register 0 IICOO operation stop IIC00 output disabled Raise SDA signal Raises SDA signal SOO register 00000011B Wait for set up time Waits for set up time of SDA signal R IIC00 SCL Time Raises SCL signal Raises SCL signal R 1IC00 SCL high Falls SDA signal start condition generation de SOO register 00000010B Wait for hold time Waits for hold time of SDA signal R 1ICO0 SCL Time Falls SCL signal for preparation to communicate Falls SCL signal CKOO register 00000010B Becure low level width of SCL signa Secures the low level width of SCL signal R_IIC00_ SCL_Time Enable IIC00 transmission Sets IIC00 transmission enabled for address transmission SCROOH register Constant CTXMODETxH IICOO output enabled Enables output of channel 0 IIC00 0 bit of SOEO register 1 IICOO operation enabled Enables operation of channel 0 I1COO 0 bit of SSO register 0 Interrupt request clear Clears IICOO interrupt request IICIFOO bit 0 Interrupt enabled Releases a mask of IICOO interrupt request IICMKOO bit 0 Vv RET Figure 5 34 Start Condition Generation StartCond RO1AN2217EJ0100 Rev 1 00 Page 66 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Stops the serial communication Serial channel stop register 0 STO Stops the serial communi
29. COO_Rx_RST to address the variable NEXTADR N If it is not a write processing of EEPROM variable STATUS constant RECEIVE branches as a No Yes judging Setup the next processing Sets the next processing address R_IIC00_Tx_DataST to address the variable NEXTADR A Lower address Sets the lower address of EEPROM to A register ICWrite Branches to the function subroutine IICWrite Figure 5 17 EEPROM Lower Address Transmitting R_IICO0_Tx_addr2 RO1AN2217EJ0100 Rev 1 00 Page 46 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 10 Restart Processing Setup Figure 5 18 shows the restart processing R_IICO0_Rx_ RST After the completion of address transmission of EEPROM in order to read data from EEPROM the communication direction of I2C bus is changed to master reception R_IICOO_Rx_RST Start condition generation StartCond Next processing address Sets the next processing address R_IICOO_Rx_DataST to setup variable NEXTADR Sets a slave address of EEPROM to A register Generates start condition for the change to read A register Slave address Read direction setup Sets LSB of A register and sets up as the read direction ICWErite Branches to the function subroutine IICWrite Figure 5 18 Restart Processing 5 8 11 DC Write Processing Figure 5 19 shows DC write processing IIC Write This processing is a common routine
30. Data reception waiting state gt No E EE lt _ A Yes INTIICOO amp remaining 2 bytes INTIICOO amp remaining 1 byte Reading reception or more data amp NACK response amp reception activation Reading received data amp reception activation gt e Ad Final data reception waiting state No Yes INTIICOO Reading received data amp f Stop condition generation N ANN Figure 5 2 Reading Processing State Transition 2 2 RO1AN2217EJ0100 Rev 1 00 Page 16 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function a If EEPROM reading processing is called under the standby state a parameter the target block number will be checked When the block number is wrong since it is a parameter error processing is ended If a parameter is right start condition will be generated and a slave address will be transmitted as LSB 0 b Checks a response from a slave by a interrupt request from INTIICOO When it is NACK response generates a stop condition and ends the processing When it is ACK response transmits EEPROM address At this time 2 bytes of address information is transmitted to EEPROM which is 32K bits or above and 1 byte of address information is transmitted to EEPROM which is 16K bits or less c The response from a slave is checked by the interrupt request of INTIICOO If it is a NACK response generates a stop condition and ends the processing When it is ACK r
31. EN External ei oi AR EE EE EE EE 24 5 7 2 Internal Processing Function ee ee ee ee GR ee Re ee Re ee Ge Re ee ee Re ee ee Re ee ee ke ee ee ee 27 98 die de EE N ER TE N EE RE EE 29 9 8 1 CPU Initialization FUNGON ER eins 29 5 8 2 MO eers EA EE RE EE EE OE EE OE EE EE 30 9 6 3 ee er Le TEE 32 5 84 Interrupt Setup es ities SES AR SE elds ee 33 S85 Main ProceSSINd EE 35 5 8 6 COO InitializatiON ee ee ee RR RA Ee RR ee RA ee ee RR ee ek Re ee ee ee ee GR Re ee ee Re ee ee ee Re ee 39 5 8 7 INTIICOO Interrupt Entry Processing se ee ees se ee ee ee ee ee ee ke ee Ge Re ee ee Re ee ee Re ee ek EN 45 5 8 8 EEPROM Upper Address Transmitting iese ee ee ee ee ee se ede ee ee ee ee ee ee Re ee ee ee ee ee ee ee Re Re ee ee ee ee 46 5 8 9 EEPROM Lower Address Transmitting iese esse se ees se ee ee ee se ke ee ee Ge ke ee ee Re ee ee Re ee ee ee ke ee ee ee 46 9 6 10 Restart Processing SetUP EE 47 Ek Me Write die RR RE ER E RE EN 47 5 8 12 DC Data Reception Start Processing ie se ee ee ee Ge Re ee ee Re ee ee Re ee ee Re ee ek ee ee ee 48 RO1AN2217EJ0100 Rev 1 00 Page 2 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 13 12C Data Reception PDroceseimg ie se ee ee ee ee Re ee Re ee Ge Re ee Ge Re ee ee ee Re ee ee Re ee ee ee 49 5 8 14 Final Data Reception ProcesSing iese ee ee ee Ge ee Re ee Ge RR ee ee Re ee ee Re ee ee ke ee ee ee 50 5 8 15 Data Transmission St
32. F This is the low level width determined by the transfer rate 100kbps Figure 5 45 Management Information by I2C Bus to be Used 5 Dummy clock setup parameter The number of the dummy clocks for making a bus release is defined as follows RETRYCNT EQU 10 max dummy SCL pulse number Figure 5 46 To Specify the Number of Dummy Clocks 6 Control information In this program uses global variables described in Figure 5 51 to access EEPROM The size of the program is suppressed by using the control information fixed in this way BLOCK NUMBER 2 index block number to access WRITE BUFF BLKSIZE write data buffer READ BUFF BLKSIZE read data buffer STATUS 1 result of operation Figure 5 47 EEPROM Control Information BLOCK_NUMBER The block number which control target EEPROM wants to access is specified WRITE_BUFF Data to write in EEPROM is set READ BUFF A buffer where the data read from EEPROM is stored RO1AN2217EJ0100 Rev 1 00 Page 78 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified I2C Function 5 9 2 Processing in the Sample Code The processing in the sample code is described below 1 EEPROM control information clear In Figure 5 48 clears EEPROM control information of internal memory buffer area initilize MOV B BLKSIZE 2 5 set data number CLRB A MAIN LOOPI MOV BLOCK NUMBER 1 B A clear memory DEC B count down data number BNZ MAIN_LOOP1 Figure 5
33. FT_TX and sets up under the writing processing after transmission e In order to confirm the completion of writing to EEPROM by INTTMO1H interrupt request transmits start condition and slave address LSB 0 f Checks a response from a slave by INTIICOO interrupt request If it is NACK response waits for the next INTTMO1H interrupt request If it is ACK response generates stop condition and stops IIC00 and TMO1H since writing to EEPROM is completed Variable STATUS is set to the completion of transmission RO1AN2217EJ0100 Rev 1 00 Page 20 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 3 Option Byte Settings Table 5 3 shows the option byte setting Table 5 3 Option Byte Setting Address Description OOOCOH 11101110B Watchdog timer operation stop Stops counting after the release from the reset state 000C1H 11110111B P125 RESET pin RESET input The on chip pull up resistor is always valid SPOR voltage Rising edge voltage 2 90V Falling edge voltage 2 84V 000C2H 11111001B HOCO 20MHz 000C3H 10000101B Enables the on chip debugger 5 4 Constants Table 5 4 and Table 5 5 list the constants that are used in this sample program Table 5 4 Constants for the Sample Program 1 2 Constant Setting Description CLKFREQ It is the definition which expressed the operation clock fCLK of RL78 G10 per kHz FAST_MODE It is defined at the time of the fast mode use When
34. J0100 Rev 1 00 Page 76 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 9 Sample Code Setup 5 9 1 The Way of Sample Code Setting The setup method for controlling serial EEPROM by sample code is shown below In the sample code the definition related to setup is described by the header file DEV amp EEPROM inc The device to be used defines the following 1 Control targets Target EEPROM for controlling is only one that is from 512K bits 64K bytes to 2K bits 256 bytes and defined in the header file according to EEPROM to be used 256K bit EEPROM is chosen by the default RESET 2KbitEEPROM 4KbitEEPROM 8KbitEEPROM 16KbitEEPROM 32KbitEEPROM RESET 64KbitEEPROM 128KbitEEPROM 256KbitEEPROM 512KbitEEPROM SET 2KbitEEPROM SET 4KbitEEPROM SET 8KbitEEPROM SET 16KbitEEPROM SET 32KbitEEPROM SET 64KbitEEPROM SET 128KbitEEPROM SET 256KbitEEPROM SET 512KbitEEPROM Figure 5 42 Definition of the target EEPROM 2 Block information It is the definition which shows the size of a block By default it is 4 bytes block BLKSIZE 4 4bytes block BLKSIZE 8bytes block BLKSIZE 16bytes block Figure 5 43 Block Information Although the block size can be changed into 8 or 16 bytes if makes it too large a possibility that futility will occur will become high In order to change delete of the head of a line to chan
35. J0100 Rev 1 00 Page 8 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 2 Operation Confirmation Conditions The sample code accompanying this application note has been run and confirmed under the conditions below Item Table 2 1 Operation Confirmation Conditions Contents MCU used RL78 G10 R5F10Y16 Operating frequency High speed on chip oscillator HOCO clock 20 MHz CPU peripheral hardware clock 20 MHz Operating voltage Integrated development environment CubeSuite 3 3V Operation is possible over a voltage range of 2 9 to 5 5 V SPOR Operating Voltage Rising voltage 2 90V Falling voltage 2 84V Renesas Electronics CubeSuite V2 02 01 Assembler CubeSuite Renesas Electronics RA78KOR V1 70 Integrated development environment e2studio Renesas Electronics e2studio V2 2 0 13 Assembler e2studio Renesas Electronics KPIT GNURL78 ELF Toolchain V14 0 1 Integrated development environment IAR Assembler IAR IAR Systems IAR Embedded Workbench for Renesas RL78 V1 40 2 IAR Systems IAR Assembler for Renesas RL78 V1 40 2 Board used RL78 G10 target board QB R5F10Y16 TB Table 2 2 EEPROM Specifications Item Contents EEPROM used R1EX24256B Operating voltage range single power supply 1 8V to 5 5V Maximum operation 400kHz frequency Capacity 256K bits Page size 64 bytes Rewriting time 5ms
36. O1AN2217EJ0100 Rev 1 00 Sep 17 2014 RENESAS Page 31 of 81 RL78 G10 EEPROM Control by Simplified 12C Function 5 8 3 Clock Generation Circuit Figure 5 8 shows the flowchart for clock generation circuit setup SINICLK Select frequency of high speed on chip oscillator HOCODIV2 to 0 bits 1 Sets HOCO frequency to 24 MHz Figure 5 8 Clock Generation Circuit Setup Selection of high speed on chip oscillator frequency High speed on chip oscillator frequency selection register HOCODIV Selects the frequency of high speed on chip oscillator Symbol HOCODIV dd 6 5 4 3 2 1 0 poo o o f o _fHocopiva Hoconiv Hocopivo oe 1 o o o o o o 1 Bits 2 to 0 HOGODIV2 HOCODIV 1 HOCODIV 0 _Fieh peed on chip oslator cok frequency seecron Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 32 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 4 Interrupt Setup Figure 5 9 shows the flowchart for setting up the interrupt a SINIINTPO gt Disable INTPO interrupt PMKO bit 1 Sets a mask for INTPO interrupt Falling edge detection enabled EGNO register 01H Enables falling edge detection of INTPO interrupt Clear interrupt request flag PIFO bit E 0 Clears INTPO interrupt request Figure 5 9 Interrupt Setup Setup INTPO p
37. alculates a slave address which is used at actual I2C bus Argument None Return value CY flag 0 The block number is normal 1 The block number is error Remarks None RO1AN2217EJ0100 Rev 1 00 Page 28 of 81 RENESAS RL78 G10 EEPROM Control by Simplified DC Function 5 8 Flowcharts Figure 5 5 shows the overall flowchart of the sample program described in this application note The option bytes are referenced before the initialization function is called CPU Initialization function RESET START Figure 5 5 Overall Flowchart 5 8 1 CPU Initialization Function Figure 5 6 shows the flowchart for the CPU initialization function RESET_START Set up ES register Set stack pointer Set up redirection Set up I O ports SINIPORT Set up clock generation circuit SINICLK Interrupt initialization SINIINTPO Call main routine main ES register 00H For table reference PIOR register 00H PMCO register 11100001B PO register 00000110B PMO register 11100110B Sets an operation clock to HOCO 20 MHz Initialization related to INTPO register Figure 5 6 CPU Initialization Function RO1AN2217EJ0100 Rev 1 00 Page 29 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 2 VO Port Setup Figure 5 7 shows the flowchart for I O port setup SINIPORT Set up port register PMCO register 11100001B PO register
38. anches to the data transmission processing Sets the next processing address R_IICOO_ TxData into the variable NEXTADR Figure 5 23 Data Transmission Start Processing RO1AN2217EJ0100 Rev 1 00 Page 50 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 16 Data Transmission Processing Figure 5 24 shows the data transmission processing R_IIC00_TxData This is the completion of data transmission processing of 1 byte If there is remaining data continues to transmit data read from buffer When there is no data generates stop condition start to write data to memory cell After that in order to check the completion of writing to EEPROM starts the interval timer for 100 ms it is 400 ms at the time of a normal mode in the fast mode R_IIC00_TxData Count the number of data Counts down the number of transmission data of variable DATACOUNT There is remaining data If the variable DATACOUNT is 0 branches as No judging lt D n Calculate data point Calculates a pointer for reading transmission data BC register save Saves the contents of BC register to be used for processing into a stack area Transmission data read Sets a data pointer to B register and reads send data from a buffer Restore BC register Restore the contents of BC register from a stack area ICWrite Branches to the function subroutine IICWrite Generate stop condition Generates sto
39. art Processing ie ee ese ee ee ee Re ee Ge RR ee Ge Re ee ee Re ee ee ke ee ee ee 50 5 8 16 Data Transmission Processing ee se ee ee Re ee ee Re ee ee Re ee Ge Re ee Ge RR ee ee Re ee ek ee ee ee 51 9 8 17 Completion of Data Writing aste EE SE EE N ee ge EE Ede ged de ED ed de dee ed es Eb ee De 52 5 8 18 Check Processing for Data Write Completion ie se ee RR ee Re ee ee 53 5 8 19 Write Start Processing to Specified Block 54 5 8 20 2C BUS ee do EE OE RE N 54 5 8 21 Specified Block Read out Start Processing iese ee se ee Re ee Re ee Ge Re ee Ge Re ee ee 55 5 8 22 Read Situation Check Processing ie ee se ee ee Re ee Ge Re ee Re ee Re ee nEn ee ee ee 55 5 8 23 Write Read Completion Waiting ProcesSing iese sk ee RR ee RA ee ee RR ee ee Re ee ee ee Re 56 5 8 24 Stop Condition Executors EE AS se Ke dn RE eg ed a se Rg eg ed daa Ee De eg EO Ae 57 MR do EI se N EE N OR Ed ales 58 5 8 26 Start Condition Generator EE ane pedi Ee ea EE AR GR ER EE Oes GN EE See Gee Oes GR EE eek eie 66 5 8 27 Stop Condition Generation E 71 5 8 28 DC Bus Release Processing iese ee se ee ee Re ee ee Re ee Re ee Ge Re ee ee ee ee ee Re ee ee ke ee ee ee 73 9 6 29 SEL Pulse Generations seed ER Ee seed EES Rek see geed dE eN Rye ego deed gee bede 73 5 8 30 AO NE ie AE OE EE EE N 74 5 8 31 SCL Signal Lowering iii ee ee ee AR ee Re AR ee ee ee ee ee ee ee RA ee ee ee Re ee ee Re ee ee ee 74 9 8 32 SCL Signal Widt
40. cation operation for IIC00 Serial output enable register 0 SOEO Disables output Symbol STO 7 6 5 4 3 2 1 0 Poo Poo Jo Jo et Bit 0 STOO Operation stop trigger of channel 0 Clears the SEO0 bit to 0 and stops the communication Operation Symbol SOEO 7 6 5 4 3 2 1 0 o o o o Laoenlsoel ole Foo Po Po fof fo Bit 0 SOE00 Serial output enable disable of channel 0 Disables output by serial communication operation Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method Setup of initial output level Serial output register 0 SOO Setting of initial output level Symbol SOO 7 6 5 4 3 2 1 0 S001 o o o o o o x 10 Note 16 pin products only Bit 0 SOOO Serial data output of channel 0 1 Serial data output value is 1 0 Serial data output value is 0 RO1AN2217EJ0100 Rev 1 00 Page 67 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of the serial click output for translation channel Serial clock output register CKOO Setting of the serial clock output level for starting the communication Symbol CKOO 7 6 5 4 3 2 1 0 poo o o o o o Coon ckooo 8 LD Lol Ta Bit 0 CKOOO Serial clock output of channel 0 1 Serial clock output value is 1 0 Serial clock output value is 0 Setup of the communi
41. cation operation for translation channel Serial communication operation setting register 00 SCROOH Setting of operation mode Symbol SCROOH 7 6 5 4 3 2 1 0 TXE00 Rxe00 DAPoo ckPoo o Eocoo PTC001 PTCO00 Pp 1 o o o o o 0 j o Bits 7 and 6 TXE00 RXEOO Setting of operation mode of channel 0 o 1 Reception only 1 0 Transmission only Bits 5 and 4 DAPOO CKPOO Selection of data and clock phase in CSI mode EES Be sure to set DAPOn CKPOn 0 0 in the UART mode and simplified DC mode Selection of masking of error interrupt signal INTSREO 0 Disables generation of error interrupt INTSREO INTSRO is generated 1 Enables generation of error interrupt INTSREO INTSRO is not generated if an error occurs Bits 1 and 0 Setting of parity bit in UART mode PTCOO1 PTCOOO Transmission 0 0 Does not output the parity bit Be sure to set PTCOn1 PTCOn0 0 0 in the CSI mode and simplified 12C mode Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 68 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Enables output of target channel for the serial communication operation Serial output enable register 0 SOEO Enables output Symbol SOEO 7 6 5 4 3 2 1 0 o o o o Leen soo RE N AR ee Bit 0 SOE00 Serial output e
42. dr1 Upper bytes transmitting processing of the EEPROM address after the completion of slave H EA address transmitting It is processing of only EEPROM of 32K to a 512K bit and common to transmission and reception The next processing is R UCO0 Tx addr2 2 R ICOO Tx addr2 Lower address transmitting processing of EEPROM This processing is common to 8 transmission and reception The next processing at the time of transmission is R_IICO00_TxDataST data transmission start The next processing at the time of reception is R 1ICO00 Rx RST restart 3 R IICOO Rx RST Performs the restart condition generate and the slave address transmission in reception mode after the completion of slave address transmission at the time of reception The next processing is R_IIC00_RxDataST data reception start 4 R IICOO RxDataST The start of data reception processing after the completion of slave address transmission in gt receiving mode The next processing is R_IIC00_RxData data reception 5 R_IICOO_RxData The data reception processing Stores received data to a buffer The next processing as follows The remaining data is 2 bytes or more R_IIC00_RxData The remaining data is 1 R 1ICOO Rx Last receiving the final data 6 R_IICOO_Rx_Last Stops IICO0 by the completion of final data reception and generates stop condition 7 R IICOO TxDataST Data transmission start processing after the completion of slave address transmission by 8 8 data transmission The next pr
43. e Explanation Outputs low and high to SCL signal by manipulating CKOO register After switching SCL signal the time for securing the low width or high width of a SCL signal is secured Argument None Return value None Remarks None RO1AN2217EJO100 Rev 1 00 Page 27 of 81 RENESAS RL78 G10 EEPROM Control by Simplified DC Function Function Name R_IICO0_SCL_high Outline Explanation Argument Return value Remarks Raises SCL signal to high In order to generate stop condition manipulates CKOO register to make SCL signal into high and secures the time for securing high width None None None Function Name R_IICO0_ SCL low Outline Explanation Argument Return value Remarks Falls SCL signal to low In order to move to the communication operation after generating start condition manipulates CKOO register to make SCL signal into low and secures the time for securing low width None None None Function Name R_IICO0_SCL_Time Outline Explanation Argument Return value Remarks Secures the time of the pulse width of a SCL signal Secures pulse width of SCL signal 1 3us None None None Function Name get_slave _Addr Sep 17 2014 Outline Calculates the address in 12C bus of EEPROM Explanation Calculates the information to incorporate a memory cell address of EEPROM into a slave address of I2C bus from the information which is set in variable area for internal EEPROM control And c
44. e of timer output pin of each channel Symbol TOO 7 6 5 4 3 2 1 0 DREES po fo fo fof xx tx fo Note 16 pin products only TOOO Timer output of channel 0 0 Timer output value is 0 1 Timer output value is 1 RO1AN2217EJ0100 Rev 1 00 Page 64 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of the timer capture completion interrupt Interrupt mask flag registers MKOL Clears the interrupt request flag Interrupt request flag registers IFOL Sets the interrupt mask Symbol MKOL 2 1 0 STMKO TMMKOO TMMKO1H SREMKO SRMKO CSIMKOO PMK1 PMKO WDTIMK IICMKOO Pox To at x x fT x fT x fT x fT x Bit 6 TMMKO1 Interrupt servicing control Interrupt servicing disabled Symbol IFOL 7 6 5 4 2 1 0 STIFO TMIFOO TMIFO1H SREIFO SRIFO CSIIFOO PIF1 PIFO WDTIIF IICIFOO pox EN EE EE Tx s x x Bit 6 DER Interrupt request flag No interrupt request signal is generated Interrupt request is generated interrupt request status Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 65 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 26 Start Condition Generation Figure 5 34 shows the start condition generation StartCond StartCond Stops operation of channel 0 II
45. e pins to be used and their functions Table 4 1 Pins to be Used and their Functions Pin Name VO Description POO Output LED drive port Under EEPROM read out writing processing Blinking Blinks LED whenever 1 block of writing reading processing of serial EEPROM is completed normally Lighting extinction An error is occurred at writing reading of EEPROM Waiting for SW1 keypress Lighting Waiting for SW1 keypress Extinction Accepts SW1 keypress and starts EEPROM writing reading processing again P01 SDA00 Input Simplified DC data input output Output PO2 SCLOO Output Simplified 12C clock output P137 INTPO Input Switch input SW1 At power on No operation Starts EEPROM writing reading processing Keypress Reads out EEPROM Waiting for keypress No operation Continues to wait keypress Keypress Starts EEPROM writing reading processing RO1AN2217EJ0100 Rev 1 00 Page 11 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 Software 5 1 Operation Outline This application note checks the SW1 state after the release from the reset When SW1 is pressed reads all memory areas of serial EEPROM When SWI is not pressed reads and writes all memory areas of serial EEPROM Blinks LED whenever block of writing reading processing of serial EEPROM is completed normally If the writing reading processing is failed stops LED blinking The state of LED is lighting or extinction
46. ears CY flag when SDA signal is high EA m 4 Figure 5 36 I2C Bus Release Processing 5 8 29 SCL Pulse Generation Figure 5 37 shows the SCL pulse generation R_IIC00 SCL _ pulse R_IICOO_SCL_pulse Lower SCL signal R_IICO0_ SCL low Lowers SCL signal Raise SCL signal R_IICOO_ SCL high Raises SCL signal Figure 5 37 SCL Pulse Generation RO1AN2217EJ0100 Rev 1 00 Page 73 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 30 SCL Signal Raising Figure 5 38 shows the SCL signal raising R_IIC00 SCL high R ICOO SCL high Raises SCL signal CKOO register 00000011B Raise SCL signal Secure high level width of SCL signal R_IIC00_ SCL Time Secures the high level width of SCL signal Figure 5 38 SCL Signal Raising 5 8 31 SCL Signal Lowering Figure 5 39 shows the SCL signal lowering R_IIC00_ SCL low R_IIC00O_SCL_low Raise SCL signal Raises SCL signal CKOO register 00000010B Secures the low level width of SCL signal Secure low level width of SCL signal R ICH SCL_Time v RET Figure 5 39 SCL Signal Lowering R01AN2217EJ0100 Rev 1 00 Page 74 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified l2C Function 5 8 32 SCL Signal Width Securing Figure 5 40 shows the SCL signal width securing R_IIC00_SCL_Time R_IICOO_SCL_Time Set t Sets a count value to X register BC X
47. ed by the timer array unit cannot be written The timer array unit is in the reset status Supplies input clock SFR used by the timer array unit can be read written Timer operation stop Timer channel stop register 0 TTO Counting operation is stopped for TAU Timer channel stop register 0 TTHO Counting operation is stopped for TAU Symbol TTO 7 6 5 4 3 2 1 0 pe fo fe fo pm 1e m r Note Note TTO1 TTOO Ee oo da NA EA RS Note 16 pin products only Bits 3 to 0 Operation stop trigger of channel n n 0 to 3 TEOn is cleared to 0 and counting operation is stopped TTO1 and TTO3 bits are the trigger to stop operation of the lower 8 bit timer when channels 1 and 3 are in the 8 bit timer mode Symbol TTHO 7 6 5 4 3 2 1 0 po fe fe e STI m o Note TTHO1 Poo o j o o x o 1 o Note 16 pin products only Bits 3 and 1 Operation stop trigger of channel n n 1 3 o0 INotiggeroperaton S O TEHOn is cleared to 0 and counting operation is stopped stop trigger is generated This bit is the trigger to stop operation of the higher 8 bit timer when channels 1 and 3 are used in the 8 bit timer mode R01AN2217EJ0100 Rev 1 00 Page 59 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of the timer clock frequency Timer clock select register 0 TPSO Selects the operation clock of timer array unit 0 Symbol TPSO 7 6
48. en a Note Note ADCEN Note SAUOEN TAUOEN ME MR ME OO ON NA AN AE N AE el Note 16 pin products only Bit 2 ISAUOEN Control of serial array unit 0 input clock supply Enables input clock supply SFR used by serial array unit 0 can be read written Setup of the serial clock frequency Serial clock select register 0 SPSO Selects the operation clock of serial array unit 0 Symbol SPSO 7 6 5 4 3 2 1 0 Po o o o0 o o o o Bits 7 to 0 Section of operation clock CKn n 0 1 3433 1 25MHz 2 5MHz 5MHz 10MHz 20MHz Po Oo o fax 125wne 25m sume 10m0 20 MEE o fo o feu ese 12m 25u smi Lo o o o o jaa orome ozs Lem 25mm Laus o f o es iseme asaz e25 vasvra ESME Poffo oan EE Z V Zz D KAZ GEN 9 8 kHz 19 5 kHz 39 kHz 78 kHz 156 GER 4 9 kHz 9 8 kHz 19 5 kHz 39 kHz 78 k GEN 2 5 KH 4 9 kHz 9 8 kHz 19 5 kHz 39 k Ede 1 22kHz 2 5kHz 9 8 kHz WA 625Hz 122 kHz 4 9 kHz da 313 Hz 625Hz 1 22kHz 2 5 KHz cial 78Hz 152 Hz 313 Hz 625 Hz 1 22 kHz Z zZ zZ z S z rA R01AN2217EJ0100 Rev 1 00 Page 40 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Clears Serial flag clear trigger register 0 Serial flag clear trigger register On SIROn Clears the error flag of SAU Symbol SIROn 7 6 5 4 3 2 1 0 FECTO Note Provided in the SIRO1 reg
49. er empty interrupt Occurs when data is transferred from the SDROOL register to the shift register Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 42 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of communication operation setting of transmission channel Serial communication operation setting register 00 SCROOH SCROOL Sets data length data transfer sequence and operation data Symbol SCROOH 7 6 5 4 3 2 1 0 Txe00 Rxe00 DAPo0 CKPo0 o Eocoo Prcoo PTCo00 ee Bits 7 and 6 TXEOO RXEO0 Setting of operation mode of channel 0 o o Disabie communication oS 1 o Transmission only Transmission reception Bit 2 EOCOO Selection of masking of error interrupt signal INTSREO Disables generation of error interrupt INTSREO INTSRO is generated 1 Enables generation of error interrupt INTSREO INTSRO is not generated if an error occurs Setup of transmission channel transfer clock Serial data register 00 SDROOH SDROOL Transfer clock frequency Undefined Symbol SDROOH Division ratio setting register SDROOL Transmit receive buffer register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 on jon on or on jo Jon jo oe lo Jo jode Jo Jo Jol Bits 7 to 1 SDROOH SDROOH 7 1 Transfer clock setting by dividing the operating clock fMCK
50. esponse generates a restart condition and transmits a slave address as LSB 1 d Checks a response from a slave by INTIICOO interrupt request If it is NACK response generates stop condition and ends the processing If it is ACK response stops IIC00 and then changes into receiving mode and reboots Activates the receiving operation by writing the dummy data to SIOOO e Stores received data into a buffer by INTIICOO interrupt request If the number of remaining receiving data is 2 or more activate the receiving operation by writing the dummy data to SIOO0 If the number of remaining receiving data is 1 disables ACK response SOE00 0 and activates the receiving operation by writing dummy data to SIOOO f Stores receiving data to a buffer by INTIICOO interrupt request Since the receiving processing is completed stops IICO0 operation generates stop condition and finishes the processing RO1AN2217EJ0100 Rev 1 00 Page 17 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 2 Writing processing state transition Figure 5 3 and Figure 5 4 show the serial EEPROM writing processing state transition Starts writing EEN EE NE Ee 7 gt a Standby state No ee Parameter error A Receiving request amp normal parameter Start condition generation amp Slave address transmission Transmission waiting state of slave address No rio oco Yes INTIICOO amp ACK resp
51. ge 3 Control parameter A parameter required for control of each EEPROM is defined below If the block information on EEPROM is specified required information will be set to a control parameter A parameter when 256K bit EEPROM is specified is shown below ELSEIF PROM256K EEPROM SET R1EX24256B 7 BLKNO SET 32768 BLKSIZE 8192 blocks device Figure 5 44 Control Parameter RO1AN2217EJ0100 Rev 1 00 Page 77 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function The meaning of each parameter is as follows a EEPROM Name of EEPROM It is a value of 0 2K bits to 8 512K bits b BLKNO The number of blocks included in EEPROM c MASK The upper bits of the cell address of EEPROM are shown It is used when specifying the slave address of I2 C bus It is 0x00 0x01 0x03 or 0x07 4 Transfer rate parameter The transfer rate of I2C bus is the fast mode or normal mode By the default it has set to the fast mode Initial setup is performed according to this mode Since it is necessary to set a transfer rate to also satisfy the specifications about the low level width of SCL signal a definition is given as follows If this value is set to SDROOH the wished transmission speed can be set up SIF FAST MODE This value is determined by the specifications of low level width 1 3us DIVIDE EQU CLKFREQ 10000 fast mode 384kbps ELSE DIVIDE EQU CLKFREQ 10000 normal mode 100kbps ENDI
52. ge 48 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 13 DC Data Reception Processing Figure 5 21 shows DC data reception processing R_IICO0_RxData Stores received data to a buffer When the next received data are the final data in order that a master responds a NACK disables the data output of IICOO and starts reception R_IICOO_RxData Dummy data set ICWrite Disable IIC00 data output Next processing address setup Dummy data set IICWrite Sa Yes Saves the contents of the BC register used by processing to a stack area Calculates the pointer for saving received data and sets it to B register Reads received data from SIO00 register Saves received data into the buffer Restores the contents of BC register from a stack area Counts down of the number of received data variable DATACOUNT If the number of remaining receiving data is 2 or more bytes branches to the processing to activate reception If the number of remaining receiving data is 0 branches as No judging Sets dummy data into A register for receiving A register FFH Branches to the function subroutine IICWrite Clears SOE00 bit and disables ACK response of IICOO Sets the next processing address R_IICOO_Rx_Last into the variable NEXTADR Sets dummy data into A register for receiving A register FFH Branches to the function subroutine IICWr
53. h Ti ue DEE 75 5 8 33 Calculation of Slave Address wi ui EE RE EE AGE ERGE EE Ge GR GEE GEE ek GR GE Gee GREG ek GR HEG de sewe Ee 76 5 9 Sample Eode Setup E 77 5 9 1 The Way of Sample Code Setting ie ee ee ee RR ee Re ee Ge Re ee ee ee ee Ge Re ee ee ee ee ee 71 5 9 2 Processing in the Sample Code 79 6 Sample Code KEER EE EERS ER SE REGEER NEER EE KANER SERE RS GER EE REEKS AR GEE EERS GENEES EDE EERS EE EER ERGER EES 81 1 Documents for Reference esse EK HE SE Sk N KERN RR N GN ARE ER RR NN ee Ke N Ge Gee nn 81 RO1AN2217EJO100 Rev 1 00 Page 3 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 1 Specification In this application note controls serial EEPROM which is connected to external with using Simplified I2C function of the serial array unit SAU Checks a state of SW1 after end of the rest Reads all memory areas of the serial EEPROM if SW1 is pressed Reads and writes data of all memory areas of the serial EEPROM if SW1 is not pressed Access to the serial EEPROM is performed per block data size chosen from 4 8 16 bytes Blinks LED whenever 1 block of writing reading processing of serial EEPROM is completed normally If the writing reading processing is failed stops LED blinking The state of LED is lighting or extinction and subsequent processing is not performed When the writing reading of serial EEPROM carry out a normal end makes LED lighting state and moves to the waiting for SW
54. he memory IE bit 1 Calls writing function to EEPROM and starts interrupt processing Waits for the completion of writing to EEPROM An infinite loop is carried out when the processing ends in an error When CY flag is set as the return value of WAIT_END moves to the No judgment PO register PO register 0x01 Variable BLOCKNUMBER BLOCKNUMBER 1 AX register Variable BLOCKNUMBER Repeats the write processing for the number of EEPROM blocks Compares AX register and the constant BLKNO If CY flag is set constant BLKNO is larger than AX register value moves to the No judgment Figure 5 11 Main Processing 2 4 RO1AN2217EJ0100 Rev 1 00 Page 36 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Block INDEX clear Interrupt enabled Read from EEPROM GETDATA Wait for the completion of reading from EEPROM WAIT END Yes LED output inversion Block INDEX increment No gt Complete reading for all blocks Reads from EEPROM Variable BLOCKNUMBER lt 0 IE bit 1 Calls reading function to EEPROM and starts interrupt processing Waits for the completion of reading from EEPROM An infinite loop is carried out when the processing ends in an error When CY flag is set as the return value of WAIT_END moves to the No judgment PO register PO register 0x01 Variable BLOCKNUMBER
55. he error status to STATUS Execute stop condition StopCond Restore AX register Restores the contents of AX register from a stack area Executes stop condition to DC bus v RETI Figure 5 15 INTIICOO Interrupt Entry Processing RO1AN2217EJ0100 Rev 1 00 Page 45 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 8 EEPROM Upper Address Transmitting Figure 5 16 shows EEPROM upper address transmitting R_IICO0_Tx_addr1 It is a processing routine which is used at EEPROM not less than 32K bits In control of EEPROM of 16K bit or less by IF sentence it will be in the state where anything does not have processing and EEPROM lower address transmitting processing R_IIC00_Tx_addr2 will start directly R_IICO00O_Tx_addr1 Sets the next processing address R_IICOO_Tx_addr2 to the Setup the next processing variable NEXTADR address A Upperaddress Sets the upper address of EEPROM to A register ICWrite Branches to the function subroutine IICWrite Figure 5 16 EEPROM Upper Address Transmitting R_IICOO_Tx_addr1 5 8 9 EEPROM Lower Address Transmitting Figure 5 17 shows EEPROM lower address transmitting R_IICO0_Tx_addr2 The memory cell to EEPROM selected in the slave address is addressed In 32K bits or more EEPROM it becomes transmission specified of a lower address R_IICO00_Tx_addr2 Setup the next processing Sets the next processing address R_II
56. iable WRITE_BUFF lt 0 Variable STATUS O Variable READ BUFF O Variable DATACOUNT lt 0 Variable R BUFF END O Variable Initialize DC SLAVEADDR lt 0 R_IICOO_Init Initializes the timer with the following setup values Fast mode 100us Normal mode 400us Initialize the timer SINITAU Performs the DC bus release processing DC bus release processing StopCond When SW1 is off performs writing processing to No EEPROM When SW1 is pressed moves to No judgment When SW1 is pressed performs reading processing from EEPROM Yes IE bit 0 Disable interrupt AX register Variable BLOCKNUMBER Block INDEX acquisition Shifts AX register to the 2 to 4 bit left according to block size EEPROM address translation B register Constant BLKSIZE Obtain the number of blocks Figure 5 10 Main Processing 1 4 RO1AN2217EJ0100 Rev 1 00 Page 35 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Obtain data to be written Set data to be written Enable interrupt Write to EEPROM PUTDATA Wait for the completion of EEPROM WAIT END No Normal end Yes LED output inversion Block INDEX increment Complete writing for all blocks Write processing to EEPROM A register A register variable READ BUFF 1 A register A register B register Sets data which to be written to EEPROM to t
57. ify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not
58. in edge detection Interrupt mask flag registers MKOL Sets up the interrupt mask flag External interrupt falling edge enable register 0 EGNO This register specifies the valid edge for INTPO Interrupt request flag registers IFOL Clears interrupt request flag Symbol MKOL wen Interrupt servicing control 1 Interrupt servicing disabled RO1AN2217EJ0100 Rev 1 00 Page 33 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Symbol EGNO INTPO pin valid edge selection 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges Symbol IFOL 7 6 5 4 2 1 0 TMIFOO TMIFO1H SREIFO SRIFO STIFO PIF1 PIFO WDTIIF CSIIFOO IICIFOO RECHNEN ee Bit 1 Pio Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated interrupt request status Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 34 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 5 Main Processing Figure 5 10 Figure 5 11 Figure 5 12 and Figure 5 13 show the flowchart for main processing Disable interrupt DI bit 1 Turn LED1 off Turns LED1 off O bit of PO register 1 oo j Clears using memory areas Initialize variables Variable BLOCK NUMBER O0 Var
59. ing as an error Goes to No judging when CY flag is set as a return value of get_slave_Addr Sets the status to reception Variable STATUS Constant RECEIVE STARTIICOO Starts access of I2C bus RET The end by error Setup status Figure 5 29 Specified Block Read out Start Processing GETDATA 5 8 22 Read Situation Check Processing Figure 5 3 shows the read situation check processing GET CHK The write situation check processing PUT CHK and the read situation check processing GET CHK are the same processings GET_CHK Reads a status Read status A register Variable STATUS Mask the operation mode Masks the operation mode of MSB and if it is normal end sets Z flag Set error to the flag Sets the error status to CY flag CY flag Variable STATUS 6 RET Figure 5 30 Read Situation Check Processing RO1AN2217EJ0100 Rev 1 00 Page 55 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 23 Write Read Completion Waiting Processing Figure 5 31 shows the write read completion waiting processing WAIT END WAIT_END gt No The processing is completed is Yes Set error to the flag Figure 5 31 Write Read Completion Waiting Processing Waiting for interruption While variable STATUS 7 is 1 this loop is continued as a No judging Sets the error status to CY flag CY flag Variable STATUS 6 RO1AN2217EJ
60. ing is shown below 1 Reading processing state transition Figure 5 1 and Figure 5 2 show the serial EEPROM reading processing state transition Startsreading k aaaaaa a Vv gt Standby state a No tee e ME A Yes Parameter error Receiving request amp normal parameter Start condition generation amp Slave address transmission Transmission waiting state of slave address Yes INTIICOO amp ACK response amp 16K bits or less INTIICOO amp NACK response Address transmission Stop condition generation b S B INTIICOO amp ACK response amp 32K bits or over Upper address transmission lt v Transmission waiting state of EEPROM upper address INTIICOO amp NACK response Yes Stop condition generation INTIICOO amp ACK response Lower address transmission Figure 5 1 Reading Processing State Transition 1 2 R01AN2217EJ0100 Rev 1 00 Page 15 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Transmission waiting state of EEPROM lower address No v INTIICOO amp NACK response Yes Stop condition generation Ad INTIICOO amp ACK response Restart amp slave address response Transmission waiting state of slave address No v INTIICOO amp NACK response Yes Stop condition generation INTIICOO Reception activation d
61. intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcompute
62. ion are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such a
63. ister only Bit 2 FECTOn Clear trigger of framing error of channel n the FEFOn bit of the SSROn register to 0 Bit 1 PECTOn Clear trigger of parity error flag of channel n e the PEFOn bit of the SSROn register to 0 Bit 0 OVCTOn Clear trigger of overrun error flag of channel n r e the OVFOn bit of the SSROn register to 0 RO1AN2217EJ0100 Rev 1 00 Page 41 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of the transmission channel operation Serial mode register 00 SMROOH SMROOL Interrupt source Operation mode Selection of the transfer clock Selection of fMCK Symbol SMROOH SMROOL 7 6 5 4 3 2 1 0 7 6 CKS CCS 00 00 oj jo o o o o o o f Leofo Bit 7 SMROOH 5 4 3 2 MD 1 Pi leet 1 0 MD MD 001 000 0 0 CKS00_ Selection of operation clock fMCK of channel 0 0 Operation clock CKOO set by the SPSO register 1 Operation clock CKO1 set by the SPSO register Bit 6 SMROOH Selection of transfer clock fTCLK of channel 0 Divided operation clock fMCK specified by the CKSO0 bit Clock input fSCK from the SCKp pin slave transfer in CSI mode Bits 2 and 1 SMROOL Mpo02_ mD001 Setting of operationmodeofchannelO O o O 2 o estmoes o 8 1 fuartmode o a o Simplified BCmodes SSS Bit O SMROOL MDOOO Selection of interrupt source of channel 0 0 Iransfer end interrupt i Buff
64. ite Figure 5 21 I2C Data Reception Processing RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Page 49 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 14 Final Data Reception Processing Figure 5 22 shows the final data reception processing R_IICO0_RxLast Stores the final received data to a buffer and stops receiving operation of IIC00 Generates stop condition and sets a status variable STATUS to the completion of receiving R IICOO Rx Last Reads received data from SIOOO register A register SIO00 register Read received data Stores received data into a buffer Variable R BUFF END A Store received data Stop IICOO operation Stops operation of IICO0 0 bit of STO register 1 Generates stop condition for the completion of Generate stop condition mie communication R_IICOO_send_Stop Sets the completion of communication constant Set the status of the TRNSEND to variable STATUS completion of receiving Restore AX register Restores the value of AX register from a stack area dl RETI Figure 5 22 Final Data Reception Processing 5 8 15 Data Transmission Start Processing Figure 5 23 shows the data transmission start processing R_IIC00_TxDataST This is the data transmission to EEPROM start processing Sets the next processing address R_IIC00_TxData into the variable NEXTADR R_IIC00_TxDataST Next processing address setup TxDATASUB Br
65. n All rights reserved Colophon 4 0
66. nable disable of channel 0 Disables output by serial communication operation Enables output by serial communication operation Entering the communication i Serial channel start register 0 SSO Starts the operation Symbol SSO 7 6 5 4 3 2 1 0 peo foo oe o f o o s so o Jj o j o o o j o j oJ 1 Bit 0 sam Operation start trigger of channel 0 1 Sets the SEOO bit to 1 and enters the communication wait status Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 69 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Setup of the timer capture completion interrupt Interrupt request flag registers IFOL Clears the interrupt request flag Interrupt mask flag registers MKOL Sets the interrupt mask Symbol IFOL 2 1 0 STIFO EER IICIFOO Bit 3 EU IICIFOO interrupt request flag No interrupt request signal is generated Interrupt request is generated interrupt request status Symbol MKOL 2 1 0 TMMKOO TMMKO1H SREMKO SRMKO CSIMKOO PMK1 PMKO WDTIMK ee ee eee Bit 3 IICMKOO Interrupt servicing control 0 _ Interrupt servicing enabled Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 70 of 81 Sep 17 2014 RENESAS RL78 G10
67. normally Normal end Waiting for SW1 keypress lluminates LED and waits SW1 keypress in HALT mode When SW1 is pressed extinguishes LED Figure 1 1 Operation Outline RO1AN2217EJ0100 Rev 1 00 Page 5 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 1 1 Page Boundary Processing EEPROM is divided into the page of the size which differs from 16 bytes to 128 bytes according to a kind When reading data from EEPROM paying attention to these page boundaries is not necessary but following cautions are required to write data in EEPROM As for the writing of EEPROM accessing to plural pages at one processing 1 block is prohibited Since a page will not be automatically updated if the address for writing arrives at the final address of a page before end of the writing it overwrites from the head address of the same page For this reason if it writes in being unconscious of a page boundary there is a possibility that data overwrite which is not expected has occurred In this application note in order to avoid the incorrect writing by page boundary access a data block is chosen from 4 8 16 byte in advance Since these block sizes are enough small to write in one page the page boundary is not need to be conscious EEPROM 1 block size Page size 4 8 16 bytes 64 bytes 1 block size Choses a writing block size from 4 8 16 bytes 4 8 16 bytes so that 1 block of write in proces
68. nput valid edge o 0 Falling edge Both edges when low level width is measured Start trigger Falling edge Capture trigger Rising edge Both edges when high level width is measured Start trigger Rising edge Capture trigger Falling edge 2 Count operation Setting of operation F i Corresponding function of mode of channel n Interval timer Square wave output Divider function PWM Interval timer mode output master TCR RAED Event counter mode External event counter Delay counter One shot pulse output Twochannel Down count input with one shot pulse output function master PWM output slave Capture amp one count Measurement of high low level width of Up count input signal Other than above Setting prohibited The operation of each mode changes depending on the operation of MDOn0 bit refer to the table below Note Refer to RL78 G10 User s Manual Hardware for more information about the register setting method RO1AN2217EJ0100 Rev 1 00 Page 62 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Bit 0 Operation mode Value set by the MDOn3 to MDOn1 bits Interval timer mode 0 0 0 Capture mode 0 1 0 Event counter mode 0 1 1 art trigger is invalid during counting operation One count mode Note 1 that time a timer interrupt is not generated 1 0 0 art trigger is valid during counting operation that time
69. number 0 0x01 0x02 0x03 0x04 Creates data to be written from the previous wrote data final value 0x00 Write block number 1 0x05 0x06 0x07 0x08 Creates data to be written from the previous wrote data final value 0x04 Write block number 16 0x41 0x42 0x43 0x44 Write block number 63 OxFD OxFE OxFF 0x00 Write block number 64 0x01 0x02 0x03 0x04 Note This application note shows control examples of EEPROM R1EX24256B by I2C bus using the simplified I2C functions of RL78 G10 IIC00 If channels or EEPRO to be used are changed conducts an extensive evaluation of the modified program RO1AN2217EJ0100 Rev 1 00 Page 13 of 81 Sep 17 2014 RENESAS RL78 G10 5 2 5 2 1 EEPROM Control by Simplified DC Function Details of Serial EEPROM Control Program Interrupt Processing Outline In this application note uses the interrupt request INTIC00 of simplified DC function IIC00 The communications processing with EEPROM is divided into some processing routines Table 5 2 shows those processing Table 5 2 Interrupt Processing Outline No Processing routine name Processing 0 INTIICOO If TICOO receives ACK makes to branch to processing of 1 to 9 of the following If NACK is received it will be checked whether STATUS is AFT_TX under EEPROM writing If it is AFT_TX nothing is done but error processing is performed if it is except AFT_TX 1 R IICOO Tx ad
70. ocessing is R_IC00_TxData data transmission 8 R IIC00 TxData The completion of data transmission of 1 byte The following data will be transmitted if E there is the remaining data The next processing is R_IIC00_TxData If the remaining day is lost generates stop condition EEPROM starts writing received data to the memory cell sets AFT_TX under EEPROM writing to STATUS and stops operation of IIC00 Activates the timer in order to confirm the completion of writing The next processing is IINTTMO1H timer interrupt 9 R EEPROM WT END The completion of writing processing of EEPROM the ACK response to slave address g E transmission Generates stop condition and stops the timer which confirms the completion of writing 10 IINTTMO1H Interval interruption in every 100 us or 400 u s Confirms the completion of writing at EEPROM transmission of slave address in transmission mode The response to this slave address transmission is INTIICOO interrupt request Transmission processing will be completed if the response becomes R EEPROM WT END EEPROM writing completion RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 Page 14 of 81 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 2 2 EEPROM Control Program State Transitions In this application note if the access processing to EEPROM begins a state will change by interrupt request INTIICOO generating of IIC00 The change state of read out and write in process
71. of a SCL signal may satisfy the specification value 1 3 ms of I2 C bus Therefore fast mode becomes a transfer rate of about 384k bps instead of 400k bps R_IICOO_Init Clock supply Sets SAUOEN bit and supplies clock Sets frequency of CKOO and CK499 by SPSO register Prescaler setup SPSO register 00H Clears SIROO register Error flag clear SIROO register 07H 8 SMROOH register 00000000B CKOO selection Mode register setup aes SMROOL register 00100100B simplified 12C transfer end interrupt Ss 8 SCROOH register 10000000B transfer mode no parity and type1 Communication operation setup SCROOL register 00010111B 8 bit length MSB fast and 1STOP bit SDROOH register Rate setting Fast mode 384kbps Communication rate setup Normal mode 100 kbps SDA pin output value initialization SOO register 00000011B SDA pin is high SCL pin output value initialization CKOOvregister 00000011B SCL pin is high N ch O D output of SDA pin POMO register 1 bit 1 N ch O D output Port mode setup Sets SCL pin and SDA pin to output ES H Figure 5 14 IICO0 Initialization RO1AN2217EJ0100 Rev 1 00 Page 39 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Start supplying clock to the serial array unit 0 Peripheral enable register 0 PERO Starts supplying clock to the serial array unit 0 Symbol PERO 7 6 5 4 3 2 1 0 STE ET Te
72. on a Sets SAUOEN bit of PERO register as a clock is provided to SAU b Sets SPSO register as the frequency of operation clock CK00 and operation clock CKO1 are 20MHz Cl Sets SIROO register as the error flag is cleared d Sets SMROOH register as the operation clock CK00 is selected e Sets SMROOL register as the simplified DC mode and the transfer end interrupt are set f Sets SCROOH register as the transfer mode no parity and type 1 are set g Sets SCROOL register as MSB first is set h Sets SDROOH register as the transfer clock is 384kbps at fast mode and 100kbps at normal mode i Sets SOOO bit of SOO register as SDA pin is high j Sets CKOOO bit of CKOO register as SCL pin is high k Sets POMO register as SDA pin and SCL pin are output we ao EE RO1AN2217EJ0100 Rev 1 00 Page 12 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 4 Sets TAUO for confirming the Transmit data completion Initializes TAUO to 100us at the fast mode and to 400us at the normal mode a Sets TAUOEN bit of PERO register to provide the clock to TAU b Sets TTHO1 bit of TTHO register and TTO1 bit of TTO register to stop the timer Cl Sets the frequency of the operation clock CK00 and the operation clock CK01 to f CLK 16 fast mode or fCLK 64 normal mode through TPSO register d Sets TMRO01H register as the operation clock CKO1 is selected and The 8 bit timer operation is set e Sets TMROIL register to set the in
73. onse INTIICOO amp NACK response amp 16K bits and below Address transmission Stop condition generation gt INTIICOO amp ACK response amp 32K bits and above y Upper address transmission Transmission waiting state of EEPROM upper address o INTIICOO amp NACK response Yes Stop condition generation INTIICOO amp ACK response Lower address transmission v g Figure 5 3 Writing Processing State Transition 1 2 R01AN2217EJ0100 Rev 1 00 Page 18 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function Transmission waiting state of EEPROM lower address EE A Yes INTIICOO amp NACK response INTIICOO amp ACK response e Data transmission c Data transmission waiting state No lt 0 ocer BEE e 4 Yes INTIICOO amp Remaining data exists Data transmission INTIICOO amp NACK response INTIICOO amp No remaining data IICOO stop amp Stop condition generation amp TMO1H activation gt v Data writing waitig state e No se L A Yes lt INTTMO1H Start condition generation amp Slave address transmission INTIICOO amp NACK INTIICOO amp ACK response Stop condition generation amp stop IIC00 response MA er vo Figure 5 4 Writing Processing State Transition 2 2 RO1AN2217EJ0100 Rev 1 00 Page 19 of 81 Sep 17 2014 RENESAS RL78
74. onse from EEPROM by INTIICOO interrupt processing If it is ACK response branches to the address address of the routine which actually processes of the value of the variable NEXTADR stored in advance If it is NACK response checks the state of writing of EEPROM When it is under writing Variable STATUS is AFT_TX processing is ended as it is and in the case of others error processing is performed The contents of the AX register used by processing are saved to a stack area In order to check the state of DC communication the contents of SSROO No If it is NACK response move to communication state Yes ee a ar If 1 bit of SSROO register is set it is No judging Variable Reads the value of NEXTADR into AX register address Branches to the address saved in AX register Branch destinations are indicated to the following flow charts R_IICOO_Tx_addr1 Upper address transmitting R_IICOO_Tx_addr2 Lower address transmitting R_IICOO_TxDataST Start of data reception processing R_IICOO_TxData Data transmission RLEEPROM_WT_END Completion of data writing R_IICOO_Rx_RST Restart R_IICOO_RxDataST Start of DC data reception R_IICOO_RxData 12C data reception R_IICOO_Rx_Last Final data reception Clears the error status of SSROO register No If it is under writing at EEPROM variable STATUS constant AFT_TX the processing is ended Yes as a No judging Set error status Variable Sets t
75. p condition for the completion of H ICOO send Stop transmission Status change Set a variable STATUS to under writing constant AFT_TX Next processing address Sets an address of the next processing to variable NEXTADR setup R_EEPROM_WT_END Activate TAUO1 Activates TAU01 to write completion check timing 1 bit of TSHO register 1 Interrupt flag clear TMIFO1H bit 0 Enable timer interrupt TMMKO01H bit 0 Restore AX register Restores the contents of AX register from a stack area RETI Figure 5 24 Data Transmission Processing RO1AN2217EJ0100 Rev 1 00 Page 51 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 17 Completion of Data Writing Figure 5 25 shows the completion of data writing R EEPROM WI END This flowchart describes a processing that the data to be written is received by EEPROM successfully The writing to EEPROM is completed by this processing R_EEPROM_WT_END Generate stop condition R_IICOO_send_Stop Set the completion of receiving status Generates stop condition for the completion of communication Sets the completion of communication constant TRNSEND to variable STATUS Stops TAUO1 which is used for check of the completion of writing 1 bit of TTHO register 1 Stop the timer interrup TMMKO01H bit 1 Stop TAU01 Clear the interrupt flag TMIFO1H bit 0 Restore AX register Restores the contents of AX register from a
76. processing writing reading EEPROM are performed in the background Table 1 1 shows the peripheral function to be used and its use Figure 1 1 shows the operation outline Table 1 1 Peripheral Function to be Used and its Use Peripheral Function Use Serial array unit SAU Using a simplified 12C function DC master transmission and reception are performed SCLOO pin and SDAOO pin are used Timer array unit 0 TAUO Uses the interval timer of 100us or 400us in order to check Channel 1 the completion of writing at data transmission processing A timer speed is switched to either first mode or normal mode RO1AN2217EJ0100 Rev 1 00 Page 4 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function End of the reset No operation of SW1 Keypress of SW1 Normal end Reading from all memory areas of EEPROM LED is illuminated or extinguished whenever the processing of 1 block is ended normally Writing to all memory areas of EEPROM LED is illuminated or extinguished whenever the processing of 1 block is ended normally Abnormal end Normal end Abnormal end Abnormal end EEPROM Access failure processing The infinite loop in LED lighting or a putting out lights state is continued Reading from all memory areas of EEPROM LED is illuminated or extinguished whenever the processing of 1 block is ended
77. r software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 Itis the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a thi
78. rd party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics SALES OFFICES Renesas Electronics Corporation http www renesas com TENESAS Rel Re er to http www renesas com for the latest and detailed information nesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel Re 1 408 588 6000 Fax 1 408 588 6130 nesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel Rei Du Tel Re 1 905 898 5441 Fax 1 905 898 3220 nesas Electronics Europe Limited kes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K 44 1628 585 10
79. rom EEPROM processing In Figure 5 51 as a read processing from EEPROM a block number is set to variable BLOCK NUMBER and a read out routine is called Here processing returns only by the read processing from EEPROM starting as well Waits for the completion of processing by CALL WAIT_END like the write processing CALL GETDATA NOP CALL WAIT END wait for complete ERRORLOOP2 BC ERRORLOOP2 loop if error Figure 5 51 Read from EEPROM Processing RO1AN2217EJ0100 Rev 1 00 Page 80 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 6 Sample Code The sample code is available on the Renesas Electronics Website 7 Documents for Reference RL78 G10 User s Manual Hardware RO1UHO384E RL78 Family User s Manual Software RO1US0015E The latest versions of the documents are available on the Renesas Electronics Website Technical Updates Technical Brochures The latest versions of the documents are available on the Renesas Electronics Website Website and Support Renesas Electronics Website http www renesas com Inquiries http www renesas com contact All trademarks and registered trademarks are the property of their respective owners RO1AN2217EJ0100 Rev 1 00 Sep 17 2014 RENESAS Page 81 of 81 Revision History lt RL78 G10 EEPROM Control by Simplified I2C Function gt Description Rev Date Page Summary Rev 1 00 Sep 17 2014 First edition issued
80. s characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test for the given product Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter mod
81. shown GC Ok 00000000B Normal end PARA_ERR 01000100B Parameter error NO_ACK1 01000000B No ACK response to Slave address NO_ACK2 01000001B Slave data error write protect BUS ERR 01100000B l2C Bus error TRANSMIT 10000000B Slave address transmission status AFT_TX TRANSMIT 20H Data writing status RECEIVE TRANSMIT 40H Receiving status TRNSEND 00H transmit completes SVAMSK 11111110B Mask R W bit RETRYCNT 9 Maximum number of dummy SCL pulses CTXMODETxH 10000000B CRXMODERxH 01000000B CTRXMODEL 00010111B CSMRDATAH 00000000B CSMRDATAL 00100100B R01AN2217EJ0100 Rev 1 00 Sep 17 2014 Initialization of IIC register Refer to the item of the flowchart for details Page 22 of 81 RENESAS RL78 G10 5 5 Variables EEPROM Control by Simplified 12C Function Table 5 6 lists the variables that are used in this sample program Table 5 6 Variables for the Sample Program Variable Outline NEXTADR Stores a transfer destination address EEPROMADDR Specifies EEPROM address BLOCK_NUMBER Specifies the block number which EEPROM of a controlled object wants to access WRITE_BUFF Sets data to write in EEPROM READ_BUFF A buffer which stores read data from EEPROM R_BUFF_END Stores data which is received at the end of specified size
82. sing may be settled in page size Page size 64 bytes Figure 1 2 EEPROM Page Boundary Processing RO1AN2217EJ0100 Rev 1 00 Page 6 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 1 2 DC Bus Release Processing When DC bus is used generates the stop condition first and makes the DC bus into a released state However if the slave EEPROM makes the SDA signal the low level stop condition cannot be generated and D C bus may be unable to be opened For example when read out of EEPROM has been interrupted by the reasons of the communications processing of 12C bus not having been finished normally on the way this abnormal condition occurs The following two can be considered as the cause 1 The master was reset by factors other than a power down during read out of EEPROM 2 The master answered ACK to the last data at the time of read out of EEPROM 1 will be in an abnormal condition because there is no means which applies reset to EEPROM from the outside 2 will be in an abnormal condition because it is necessary to certainly answer NACK to the received data in the case that data reception ends normally as well when the master of I2C bus ends reception operation In such a case the master of DC bus manipulates the SCL signal by software to generate the fake clocks dummy clocks of DC bus And waits for a SDA signal to become high level Ifa SCL signal is generated for longer than or
83. stack area RETI Figure 5 25 Completion of Data Writing RO1AN2217EJ0100 Rev 1 00 Page 52 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 18 Check Processing for Data Write Completion Figure 5 26 shows the check processing for data writing completion IINTTMO1H Starts transmission of a slave address in transmission mode to EEPROM by the interval interrupt The response from EEPROM to slave address is processed by IINTIICOO INTTMO1H Saves the contents of AX register to be used for processing into a stack area Clear the error flag of SSROO register SIROO register 07H Save AX register Clear the error flag Generates start condition to transmit slave address Writes a slave address to SIOOO in transmission mode and starts transmission Generate start condition StartCond Transmit a slave address SIOOO register constant SLAVE Restore AX register Restores the value of AX register from a stack RETI Figure 5 26 Check Processing for Data Write Completion RO1AN2217EJ0100 Rev 1 00 Page 53 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 19 Write Start Processing to Specified Block Figure 5 27 shows the write start processing to specified block PUTDATA PUTDATA Calculate slave address get_slave_Addr Calculates a slave address from specified block number and if the block number is ou
84. t of EEPROM s range ends the processing as an error The access range is correct When CY flag is set as a return value of get_slave_Addr moves to No judging Setup status Sets the status to transmission Variable STATUS Constant TRANSMIT STARTIICOO lt D n RET Figure 5 27 Write Start Processing to Specified Block 5 8 20 DC Bus Access Start Figure 5 28 shows the DC bus access start STARTIICOO This processing is a common routine for starting DC bus access STARTIICOO Sets the size of a block as the number of Number of data setup transmission data Variable DATACOUNT lt Constant BLKSIZE Next processing address i Sets the next processing address R_IIC00_Tx_addr1 into setup the variable NEXTADR Start condition generation Generates start condition to DC bus StartCond Writes slave address into SIOOO register A Variable SLAVEADDR SIO00 register A Slave address setup d RET Figure 5 28 I2C Bus Access Start RO1AN2217EJ0100 Rev 1 00 Page 54 of 81 Sep 17 2014 RENESAS RL78 G10 EEPROM Control by Simplified 12C Function 5 8 21 Specified Block Read out Start Processing Figure 5 29 shows the specified block read out start processing GETDATA GETDATA Calculate slave address get_slave_Addr N o Yes Calculates a slave address from specified block number and if the block number is out of EEPROM s range ends the process
85. terval timer f Sets TDROJH register as 100s at the fast mode and 400us at the normal mode g Sets TOEO1 bit of TOEO register to set TOO1 output disabled h Sets TOO register to set Timer output value 0 i Sets TMMKO1H bit of MKOL register to set the interrupt request mask j Sets TMIFO1H bit of IFOL register to set interrupt request clear 5 Generates stop condition and makes I2C bus the bus release status before using I2C bus In order to make I2C bus the bus released status waits for SDA signal becomes high by generating spurious I2C bus clock dummy clock through controlling SCLO0 signal by a program After becoming high of SDA signal generates the stop condition and releases the bus 6 Monitors the state of SW1 and if SW1 is pressed performs EEPROM reading processing If SW1 is not pressed performs reading and writing processing of EEPROM Refer to Chapter 5 2 for more information about EEPROM control part 7 Creates data to be written to EEPROM Creates data to be written based on selected block size 4 8 16 byte the number of blocks of EEPROM that is destination to write and the final 1 byte of write buffer The example of data to be written at the time of choosing 4 bytes as block size is shown in Table 5 1 Table 5 1 Data to be written into EEPROM Block number to be written The example of write data In the case that the block size is 4 bytes After reset releasing 0x00 0x00 0x00 0x00 Write block
86. tion 5 7 2 Internal Processing Function Function Name StartCond Outline Explanation Argument Return value Remarks Generates start condition to I2C bus Generates start condition to 12C bus by manipulating CKOO and SOO bit and makes IICOO operation enabled state None None ICOO will be in the state of operation enabled by transmitting permission Function Name R_IICOO_send_ Stop Outline Explanation Argument Return value Remarks Generates stop condition to 12C bus Stopping operation of IICOO and adjusting timing with using software generates stop condition raises SDA signal raises SCL signal and then raises SDA signal to 12C bus by manipulating CKOO and SOO bit None None None Function Name R_IICOO_wait_bus Outline Explanation Argument Return value Remarks Releases I2C bus Confirms that SDA signal is high If SDA signal is low checks the state of the SDA signal outputting 10 false clocks to SCL signal Even if outputs 9 clocks when a SDA signal does not become high it is considered as an error None Variable STATUS I2C_OK Confirmation of bus release SDA moves to BUS ERR high SDA still remains in low This is a countermeasure against the process discontinuation after data output from EEPROM because of CPU reset and so on Normally generates stop condition after this Function Name R_IICO0_SCL_pulse Sep 17 2014 Outline Outputs SCL signal of 1 puls
87. undefined it operates as a normal mode lt Fast mode setting gt DIVIDE 13 CLKFREQ 10000 384kbps lt Normal mode setting gt DIVIDE 50 CLKFREQ 10000 100 kbps lt Common gt CSDRDATA DIVIDE 1 2 SDROOH SCLLOWW DIVIDE 13 4 5 SCL low time SCLHIGHW DIVIDE2 13 4 5 SCL high time R1EX24002A 2K bit EEPROM R1EX24004A AK bit EEPROM R1EX24008A BK bit EEPROM R1EX24016A 16K bit EEPROM R1EX24032A 32K bit EEPROM R1EX24064A 64K bit EEPROM R1EX24128B 128K bit EEPROM R1EX24256B 256K bit EEPROM R1EX24512B 512K bit EEPROM EEPROM_MAX device end RO1AN2217EJ0100 Rev 1 00 Page 21 of 81 Sep 17 2014 RENESAS RL78 G10 Constant BLKSIZE EEPROM Control by Simplified 12C Function Table 5 5 Constants for the Sample Program 1 2 Setting Description The size of a block is defined By default it is 4 bytes block Although the block size can be changed into 8 or 16 bytes if makes it too large a possibility that futility will occur will become high SLAVE OAOH Slave address MASKO 00000000B Mask pattern MASK2 11111111B Mask pattern EEPROM R1EX24256B Name of EEPROM Its value is from 0 2K bits to 8 512K bits BLKNO 32768 BLKSIZE The number of blocks included in EEPROM A value is decided by capacity setup of EEPROM Here the value at the time of choosing 256K bit EEPROM is

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